74894 lines
5.5 MiB
74894 lines
5.5 MiB
; --------------------------------------------------------------------------------
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; @Title: TegraK1 On-Chip Peripherals
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; @Props: Released
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; @Author: LMH, MAJ, ZUO, TPP
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; @Changelog: 2015-05-07 TPP
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; 2017-10-16 BFG
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; @Manufacturer: NVIDIA - NVIDIA Corporation
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; @Doc: TegraK1_TRM_DP06905001_public.pdf (ver. v01p, 2014-03-20),
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; TegraK1_TRM_DP06905001_public_v03p.pdf (ver. v03p, 2014-10-15)
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; @Date: 2015-05-07
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; @Core: Cortex-A15MPCore
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; @Chip: TEGRAK1
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pertegrak1.per 9196 2018-05-08 16:01:46Z mkolodziejczyk $
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; Known problems:
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; Module Register Description
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; --------------------------------------------------------------------------------
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; SATA Configuration space There is lack of data about where exactly SATA/SATA0 configuration spaces are mapped to.
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; (Assumed base addresses may be wrong)
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; DMA Control Registers Documentation only say "I/O Mapped Registers behind a BAR.", so SATA IOBIST address has been used.
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; (Assumed base address may be wrong)
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; HOST1X PROTCHANNEL, CLASS Base addresses are unknown and they were not included
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; registers
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; XUSB_xHCI Whole module No base address
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; PMCC0, PMCC1 Whole module No base address
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; Display controller disp_window.ph All display trees have the same offset in doc
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config 16. 8.
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tree "Core Registers (Cortex-A15MPCore)"
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; --------------------------------------------------------------------------------
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; Identification registers
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; --------------------------------------------------------------------------------
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width 10.
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tree "ID Registers"
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group.long c15:0x0++0x0
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line.long 0x0 "MIDR,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
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rgroup.long c15:0x100++0x0
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line.long 0x0 "CTR,Cache Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "Reserved,Reserved,Reserved,Reserved,ARMv7,?..."
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bitfld.long 0x0 24.--27. " CWG ,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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bitfld.long 0x0 20.--23. " ERG ,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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textline " "
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bitfld.long 0x0 16.--19. " DMINLINE ,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,Reserved,Reserved,Physical"
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,8 words,16 words,?..."
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elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
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rgroup.long c15:0x100++0x0
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line.long 0x0 "CTR,Cache Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "Reserved,Reserved,Reserved,Reserved,ARMv7,?..."
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bitfld.long 0x0 24.--27. " CWG ,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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bitfld.long 0x0 20.--23. " ERG ,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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textline " "
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bitfld.long 0x0 16.--19. " DMINLINE ,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,8 words,?..."
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endif
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rgroup.long c15:0x300++0x0
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line.long 0x0 "TLBTR,TLB Type Register"
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bitfld.long 0x0 0. " NU ,Unified or Separate TLBs" "Unified,?..."
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rgroup.long c15:0x500++0x0
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line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
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bitfld.long 0x00 31. " MPERF ,Multiprocessing Extensions register format" "Not supported,Supported"
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bitfld.long 0x00 30. " U ,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor"
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bitfld.long 0x00 24. " MT ,Lowest level of affinity consist of logical processors" "Not implemented,Implemented"
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textline " "
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bitfld.long 0x00 8.--11. " CLUSTERID ,Value read in CLUSTERID configuration pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--1. " CPUID ,Value depends on the number of configured CPUs" "1,2,3,4"
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rgroup.long c15:0x400++0x0
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line.long 0x0 "MIDR2,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long c15:0x600++0x0
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line.long 0x0 "REVIDR,Revision ID Register"
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rgroup.long c15:0x700++0x0
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line.long 0x0 "MIDR3,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
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rgroup.long c15:0x0410++0x00
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 28.--31. " IS ,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " AR ,Auxiliary Register Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " SL ,Shareability levels" "Reserved,Implemented 2 levels,?..."
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bitfld.long 0x00 8.--11. " OSS ,Outer Shareable Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,PXN,64-bit,?..."
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elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
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rgroup.long c15:0x0410++0x00
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 28.--31. " IS ,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " AR ,Auxiliary Register Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " SL ,Shareability levels" "Reserved,Implemented 2 levels,?..."
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bitfld.long 0x00 8.--11. " OSS ,Outer Shareable Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
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endif
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if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
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rgroup.long c15:0x0510++0x00
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line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
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elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
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rgroup.long c15:0x0510++0x00
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line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,Required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
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endif
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rgroup.long c15:0x0610++0x00
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
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bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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rgroup.long c15:0x0710++0x00
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line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
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bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..."
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bitfld.long 0x00 24.--27. " PMS ,Physical memory size supported by processor caches" "Reserved,Reserved,40-bit,?..."
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bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " MB ,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Reserved,Supported,?..."
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if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
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rgroup.long c15:0x0020++0x00
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line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,BKPT,?..."
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Not supported,?..."
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elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
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rgroup.long c15:0x0020++0x00
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line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,BKPT,?..."
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Supported,?..."
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endif
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rgroup.long c15:0x0120++0x00
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line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1"
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bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " EARI ,Exception A and R Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " EXIN ,Exception in ARM Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0220++0x00
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line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2"
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bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,MUL/MLA/MLS,?..."
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bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,PLD/PLI/PLWD,?..."
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bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,LDRD/STRD,?..."
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rgroup.long c15:0x0320++0x00
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line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3"
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bitfld.long 0x00 28.--31. " TEEEI ,Thumb-EE Extensions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,TBB/TBH,?..."
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bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
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rgroup.long c15:0x0420++0x00
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line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4"
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bitfld.long 0x00 28.--31. " SWP_FRAC ,Memory System Locking Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,DMB/DSB/ISB,?..."
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bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
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rgroup.long c15:0x0010++0x00
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 12.--15. " STATE3 ,Thumb Execution Environment (Thumb-EE) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " STATE2 ,Support for Jazelle extension" "Not supported,?..."
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x0110++0x00
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 16.--19. " GT ,Generic Timer Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " VE ,Virtualization Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x0210++0x00
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " PMM ,Performance Monitor Model Support" "Reserved,Reserved,ID_DFR0,?..."
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TM_MM ,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CTM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1,?..."
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1/CP14,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1/CP14,?..."
|
|
if (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c15:0x6C9++0x0
|
|
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
|
|
bitfld.long 0x00 29. " PMCEID0[29] ,Bus cycle" "Not implemented,Implemented"
|
|
bitfld.long 0x00 28. " [28] ,Instruction architecturally executed. Condition code check pass, write to TTBR" "Not implemented,Implemented"
|
|
bitfld.long 0x00 27. " [27] ,Instruction speculatively executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 26. " [26] ,Local memory error" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [25] ,Bus access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 24. " [24] ,Level 2 data cache write-back" "Not implemented,Implemented"
|
|
bitfld.long 0x00 23. " [23] ,Level 2 data cache refill" "Not implemented,Implemented"
|
|
bitfld.long 0x00 22. " [22] ,Level 2 data cache access" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Level 1 instruction cache access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 20. " [20] ,Level 1 instruction cache access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 19. " [19] ,Data memory access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 15. " [15] ,Instruction architecturally executed, condition code check pass, unaligned load or store" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 14. " [14] ,Instruction architecturally executed, condition code check pass, procedure return" "Not implemented,Implemented"
|
|
bitfld.long 0x00 13. " [13] ,Instruction architecturally executed, immediate branch" "Not implemented,Implemented"
|
|
bitfld.long 0x00 12. " [12] ,Instruction architecturally executed, condition code check pass, software change of the PC" "Not implemented,Implemented"
|
|
bitfld.long 0x00 11. " [11] ,Instruction architecturally executed, condition code check pass, write to CONTEXTIDR" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [10] ,Instruction architecturally executed, condition code check pass, exception return" "Not implemented,Implemented"
|
|
bitfld.long 0x00 9. " [9] ,Exception taken" "Not implemented,Implemented"
|
|
bitfld.long 0x00 8. " [8] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 7. " [7] ,Instruction architecturally executed, condition code check pass, store" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Instruction architecturally executed, condition code check pass, load" "Not implemented,Implemented"
|
|
bitfld.long 0x00 5. " [5] ,Level 1 data TLB refill" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. " [2] ,Level 1 instruction TLB refill" "Not implemented,Implemented"
|
|
bitfld.long 0x00 1. " [1] ,Level 1 instruction cache refill" "Not implemented,Implemented"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c15:0x6C9++0x0
|
|
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
|
|
bitfld.long 0x00 31. " PMCEID0[31] ,Level 1 instruction cache access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 30. " [30] ,Level 1 data memory access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 29. " [29] ,Level 1 data memory access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 28. " [28] ,Level 1 data memory access" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Branches or other change in program flow that could have been predicted by the branch prediction resources of the processor" "Not implemented,Implemented"
|
|
bitfld.long 0x00 26. " [26] ,Branch mispredicted or not predicted" "Not implemented,Implemented"
|
|
bitfld.long 0x00 25. " [25] ,Unaligned access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 24. " [24] ,Unaligned access" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Branch speculatively executed - Procedure return" "Not implemented,Implemented"
|
|
bitfld.long 0x00 22. " [22] ,Branch speculatively executed - Immediate branch" "Not implemented,Implemented"
|
|
bitfld.long 0x00 21. " [21] ,Instruction speculatively executed - Software change of the PC" "Not implemented,Implemented"
|
|
bitfld.long 0x00 20. " [20] ,Write to translation table register (TTBR0 or TTBR1)" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Change to ContextID retired" "Not implemented,Implemented"
|
|
bitfld.long 0x00 18. " [18] ,Exception return architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 17. " [17] ,Exception taken. Counts the number of exceptions architecturally taken" "Not implemented,Implemented"
|
|
bitfld.long 0x00 16. " [16] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 14. " [14] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 13. " [13] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 12. " [12] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 10. " [10] ,Instruction architecturally executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 9. " [9] ,Store instruction speculatively executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 8. " [8] ,Store instruction speculatively executed" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Load instruction speculatively executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 6. " [6] ,Load instruction speculatively executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 5. " [5] ,Data read or write operation that causes a TLB refill at (at least) the lowest level of TLB" "Not implemented,Implemented"
|
|
bitfld.long 0x00 4. " [4] ,Data read or write operation that causes a cache access at (at least) the lowest level of data or unified cache" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Data read or write operation that causes a cache access at (at least) the lowest level of data or unified cache" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. " [2] ,Data read or write operation that causes a refill at (at least) the lowest level of data or unified cache" "Not implemented,Implemented"
|
|
bitfld.long 0x00 1. " [1] ,Instruction fetch that causes a TLB refill at (at least) the lowest level of TLB" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " [0] ,Instruction fetch that causes a refill at (at least) the lowest level of instruction or unified cache" "Not implemented,Implemented"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
rgroup.long c15:0x6C9++0x0
|
|
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
|
|
bitfld.long 0x00 29. " PMCEID0[29] ,Bus cycle" "Not implemented,Implemented"
|
|
bitfld.long 0x00 28. " [28] ,Instruction architecturally executed. Condition code check pass, write to TTBR" "Not implemented,Implemented"
|
|
bitfld.long 0x00 27. " [27] ,Instruction speculatively executed" "Not implemented,Implemented"
|
|
bitfld.long 0x00 26. " [26] ,Local memory error" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [25] ,Bus access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 24. " [24] ,Level 2 data cache write-back" "Not implemented,Implemented"
|
|
bitfld.long 0x00 23. " [23] ,Level 2 data cache refill" "Not implemented,Implemented"
|
|
bitfld.long 0x00 22. " [22] ,Level 2 data cache access" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Level 1 instruction cache access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 20. " [20] ,Level 1 instruction cache access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 19. " [19] ,Data memory access" "Not implemented,Implemented"
|
|
bitfld.long 0x00 14. " [14] ,Instruction architecturally executed, condition code check pass, procedure return" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Instruction architecturally executed, condition code check pass, write to CONTEXTIDR" "Not implemented,Implemented"
|
|
bitfld.long 0x00 10. " [10] ,Instruction architecturally executed, condition code check pass, exception return" "Not implemented,Implemented"
|
|
bitfld.long 0x00 9. " [9] ,Exception taken" "Not implemented,Implemented"
|
|
bitfld.long 0x00 5. " [5] ,Level 1 data TLB refill" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [2] ,Level 1 instruction TLB refill" "Not implemented,Implemented"
|
|
bitfld.long 0x00 1. " [1] ,Level 1 instruction cache refill" "Not implemented,Implemented"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
tree "System Control and Configuration"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c15:0x1++0x0
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big"
|
|
textline " "
|
|
bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c15:0x1++0x0
|
|
line.long 0x0 "SCTLR,System Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big"
|
|
bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " A ,Alignment Fault Check enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " M ,Address translation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c15:0x0101++0x0
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 6. " SMP ,Enables coherent requests to the processor" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASSE ,ACE STREX Signalling Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " L2PF ,Enable L2 prefetch" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " L1PF ,Enable L1 prefetch" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x101++0x0
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 31. " SDEH ,Snoop-delayed exclusive handling" "Normal,Modified"
|
|
bitfld.long 0x00 30. " FMCEA ,Force main clock processor enable active" "Not prevented,Prevented"
|
|
bitfld.long 0x00 29. " FNVCEA ,Force NEON/VFP clock enable active" "Not prevented,Prevented"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " WSNAT ,Write streaming no-allocate threshold" "12th,128th,512th,Disabled"
|
|
bitfld.long 0x00 25.--26. " WSNL1AT ,Write streaming no L1-allocate threshold" "14th,64th,128th,Disabled"
|
|
bitfld.long 0x00 24. " NCSE ,Non-cacheable streaming enhancement" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FIORRTTSSAW ,Forces in-order requests to the same set and way" "Not forced,Forced"
|
|
bitfld.long 0x00 22. " FIOLI ,Force in-order load issue" "Not forced,Forced"
|
|
bitfld.long 0x00 21. " DL2TLBP ,Disabled L2 TLB prefetching" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DL2TBWIPAPAC ,Disable L2 TBW IPA PA cache" "No,Yes"
|
|
bitfld.long 0x00 19. " DL2TBWS1WC ,Disable L2 TBW Stage 1 walk cache" "No,Yes"
|
|
bitfld.long 0x00 18. " DL2TBWS1L2PAC ,Disable L2 TBW stage 1 L2 PA cache" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DL2TLBPO ,Disable L2 TLB Performance Optimization" "No,Yes"
|
|
bitfld.long 0x00 16. " EFSOADLR ,Enables full Strongly-ordered and Device load replay" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " FIIBEU ,Force in-order issue in branch execution unit" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FLOIGCDPC ,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Limited"
|
|
bitfld.long 0x00 13. " FACP14WCP15 ,Flush after CP14 and CP15 writes" "Normal,Flushed"
|
|
bitfld.long 0x00 12. " FPCP14CP15 ,Force push of CP14 and CP15 registers" "Not forced,Pushed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FOISEG ,Force one instruction to start and end a group" "Not forced,Forced"
|
|
bitfld.long 0x00 10. " FSAEIG ,Force serialization after each instruction group" "Not forced,Forced"
|
|
bitfld.long 0x00 9. " DFRO ,Disable flag renaming optimization" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EWFIIANOPI ,Executes WFI instructions as NOP instructions" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " EWFEIANOPI ,Executes WFE instructions as NOP instructions" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SMP ,Broadcast of cache and TLB maintenance operations enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EPLDIANOP ,Execute PLD and PLDW instructions as a NOP instruction" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIP ,Disable indirect predictor" "No,Yes"
|
|
bitfld.long 0x00 3. " DMBTB ,Disable micro-BTB" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LOLBDPF ,Limits to one loop buffer detect per flush" "Normal,Limited"
|
|
bitfld.long 0x00 1. " DLB ,Disable loop buffer" "No,Yes"
|
|
bitfld.long 0x00 0. " EIBTB ,Enable invalidate of BTB" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c15:0x101++0x0
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 28. " DBDI ,Disable branch dual issue" "No,Yes"
|
|
bitfld.long 0x00 15. " DDVM ,Disable Distributed Virtual Memory (DVM) transactions" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " L1PCTL ,L1 Data prefetch control" "Disabled,1 pre-fetch,2 pre-fetches,3 pre-fetches"
|
|
textline " "
|
|
bitfld.long 0x00 12. " L1RADIS ,L1 Data Cache read-allocate mode disable" "No,Yes"
|
|
bitfld.long 0x00 11. " L2RADIS ,L2 Data Cache read-allocate mode disable" "No,Yes"
|
|
bitfld.long 0x00 10. " DODMBS ,Disable optimised data memory barrier behaviour" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SMP ,Enables coherent requests to the processor" "Disabled,Enabled"
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x140F++0x00
|
|
line.long 0x0 "ACTLR2,Auxiliary Control Register 2"
|
|
bitfld.long 0x00 31. " ECRCG ,Enable CPU regional clock gates" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EDCCADCCI ,Execute data cache clean as data cache clean/invalidate" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
hgroup.long c15:0x140F++0x00
|
|
hide.long 0x0 "ACTLR2,Auxiliary Control Register 2"
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c15:0x201++0x00
|
|
line.long 0x0 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x0 22.--23. " CP11 ,Coprocessor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 20.--21. " CP10 ,Coprocessor access control" "Denied,Privileged,Reserved,Full"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c15:0x201++0x00
|
|
line.long 0x0 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x0 30. " D32DIS ,Disable use of registers D16-D31 of the VFP register file" "No,Yes"
|
|
bitfld.long 0x0 22.--23. " CP11 ,Coprocessor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 20.--21. " CP10 ,Coprocessor access control" "Denied,Privileged,Reserved,Full"
|
|
endif
|
|
group.long c15:0x11++0x0
|
|
line.long 0x0 "SCR,Secure Configuration Register"
|
|
bitfld.long 0x00 9. " SIF ,Secure Instruction Fetch" "Permitted,Not permitted"
|
|
bitfld.long 0x00 8. " HCE ,Hyp Call enable" "Undefined,Enabled"
|
|
bitfld.long 0x00 7. " SCD ,Secure Monitor Call disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
|
|
bitfld.long 0x00 4. " FW ,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
|
|
bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
|
|
bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure"
|
|
group.long c15:0x0111++0x00
|
|
line.long 0x00 "SDER,Secure Debug Enable Register"
|
|
bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x0211++0x00
|
|
line.long 0x00 "NSACR,Non-Secure Access Control Register"
|
|
bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " NS_L2ERR ,L2 internal asynchronous error and AXI asynchronous error writeable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c15:0x0211++0x00
|
|
line.long 0x00 "NSACR,Non-Secure Access Control Register"
|
|
bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register file" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c15:0x0211++0x00
|
|
line.long 0x00 "NSACR,Non-Secure Access Control Register"
|
|
bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Non-writeable,Writeable"
|
|
bitfld.long 0x00 17. " NS_L2ERR ,Determines if the L2 Extended Control Register(L2ECTLR), is writeable in Non-secure state" "Non-writeable,Writeable"
|
|
bitfld.long 0x00 16. " NS_ACTLR_PF_WRITE ,Determines if the ACTLR.L1PF and ACTLR.L2PF registers are writeable in Non-secure state" "Non-writeable,Writeable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register file" "No,Yes"
|
|
bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted"
|
|
endif
|
|
group.long c15:0x000C++0x00
|
|
line.long 0x00 "VBAR,Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " VBADDR ,Vector Base Address"
|
|
group.long c15:0x010C++0x00
|
|
line.long 0x00 "MVBAR,Monitor Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " MVBADDR ,Monitor Vector Base Address"
|
|
textline " "
|
|
rgroup.long c15:0x001C++0x00
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 8. " A ,External abort pending flag" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " I ,Interrupt pending flag" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " F ,Fast interrupt pending flag" "Not pending,Pending"
|
|
textline " "
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c15:0x400F++0x00
|
|
line.long 0x00 "CBAR,Configuration Base Address Register"
|
|
hexmask.long.tbyte 0x00 15.--31. 1. " PERIPHBASE[31:15] ,Periphbase[31:15]"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PERIPHBASE[39:32] ,Periphbase[39:32]"
|
|
else
|
|
hgroup.long c15:0x400F++0x00
|
|
hide.long 0x00 "CBAR,Configuration Base Address Register"
|
|
endif
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c15:0x1609))&0x3)==0x3)
|
|
group.long c15:0x1609++0x00
|
|
line.long 0x00 "SCUCTLR,SCU Control Register"
|
|
bitfld.long 0x00 30. " PRM3 ,Disable processor 3 retention" "No,Yes"
|
|
bitfld.long 0x00 28.--29. " PPS3 ,Processor 3 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 26. " PRM2 ,Disable processor 2 retention" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " PPS2 ,Processor 2 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes"
|
|
bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes"
|
|
bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 7. " CPSMP[3] ,Copy of the ACTLR.SMP for processor 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPSMP[2] ,Copy of the ACTLR.SMP for processor 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4"
|
|
textline " "
|
|
elif (((d.l(c15:0x1609))&0x3)==0x2)
|
|
group.long c15:0x1609++0x00
|
|
line.long 0x00 "SCUCTLR,SCU Control Register"
|
|
bitfld.long 0x00 26. " PRM2 ,Disable processor 2 retention" "No,Yes"
|
|
bitfld.long 0x00 24.--25. " PPS2 ,Processor 2 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes"
|
|
bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CPSMP[2] ,Copy of the ACTLR.SMP for processor 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4"
|
|
textline " "
|
|
elif (((d.l(c15:0x1609))&0x3)==0x1)
|
|
group.long c15:0x1609++0x00
|
|
line.long 0x00 "SCUCTLR,SCU Control Register"
|
|
bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes"
|
|
bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4"
|
|
textline " "
|
|
elif (((d.l(c15:0x1609))&0x3)==0x0)
|
|
group.long c15:0x1609++0x00
|
|
line.long 0x00 "SCUCTLR,SCU Control Register"
|
|
bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes"
|
|
bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown"
|
|
bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4"
|
|
textline " "
|
|
endif
|
|
group.long c15:0x410F++0x00
|
|
line.long 0x00 "FILASTARTR,Peripheral port start address register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " FLT_START_ADDR ,Start address of the peripheral port physical memory region"
|
|
bitfld.long 0x00 0. " FILT_EN ,FLT_START_ADDR and FLT_END_ADDR are valid" "Invalid,Valid"
|
|
group.long c15:0x420F++0x00
|
|
line.long 0x00 "FILAENDR,Peripheral port end address register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " FLT_END_ADDR ,End address of the peripheral port physical memory region"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
hgroup.long c15:0x1609++0x00
|
|
hide.long 0x00 "SCUCTLR,SCU Control Register"
|
|
hgroup.long c15:0x410F++0x00
|
|
hide.long 0x00 "FILASTARTR,Peripheral port start address register"
|
|
hgroup.long c15:0x420F++0x00
|
|
hide.long 0x00 "FILAENDR,Peripheral port end address register"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
tree "Memory Management Unit"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c15:0x0001++0x0
|
|
line.long 0x0 "SCTLR,System Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big"
|
|
bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " A ,Alignment Fault Check enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " M ,Address translation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c15:0x1++0x0
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big"
|
|
bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
if (((d.l(c15:0x0002))&0x2)==0x2)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000)
|
|
group.long c15:0x0002++0x00
|
|
line.long 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB0_ADDR ,Translation table base 0 address"
|
|
bitfld.long 0x00 5. " NOS ,Not Outer Shareable bit" "Outer,Inner"
|
|
bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High"
|
|
bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable"
|
|
bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
elif (((d.l(c15:0x0002))&0x2)==0x0)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000)
|
|
group.long c15:0x0002++0x00
|
|
line.long 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB0_ADDR ,Translation table base 0 address"
|
|
bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable"
|
|
bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
elif (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.quad c15:0x10020++0x01
|
|
line.quad 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.quad.byte 0x00 48.--55. 1. " ASID ,ASID for the translation table base address"
|
|
hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address"
|
|
endif
|
|
if (((d.l(c15:0x0102))&0x2)==0x2)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000)
|
|
group.long c15:0x0102++0x00
|
|
line.long 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB1_ADDR ,Translation table base 1 address"
|
|
bitfld.long 0x00 5. " NOS ,Not Outer Shareable bit" "Outer,Inner"
|
|
bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High"
|
|
bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable"
|
|
bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
elif (((d.l(c15:0x0102))&0x2)==0x0)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000)
|
|
group.long c15:0x0102++0x00
|
|
line.long 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB1_ADDR ,Translation table base 1 address"
|
|
bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable"
|
|
bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
elif (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.quad c15:0x11020++0x01
|
|
line.quad 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.quad.byte 0x00 48.--55. 1. " ASID ,ASID for the translation table base address"
|
|
hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address"
|
|
endif
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x00000000)
|
|
group.long c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x00 31. " EAE ,Extended Address Enable" "32-bit,40-bit"
|
|
bitfld.long 0x00 5. " PD1 ,Translation table walk Disable bit for TTBR1" "No,Yes"
|
|
bitfld.long 0x00 4. " PD0 ,Translation table walk Disable bit for TTBR0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " N ,Indicate the width of the base address held in TTBR0" "16KB,8KB,4KB,2KB,1KB,512 bytes,256 bytes,128 bytes"
|
|
else
|
|
group.long c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x00 31. " EAE ,Extended Address Enable" "32-bit,40-bit"
|
|
bitfld.long 0x00 30. " IMP ,IMPLEMENTATION DEFINED" "Low,High"
|
|
bitfld.long 0x00 28.--29. " SH1 ,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " ORGN1 ,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 24.--25. " IRGN1 ,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 23. " EPD1 ,Translation table walk disable for translations using TTBR1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 22. " A1 ,Selects whether TTBR0 or TTBR1 defines the ASID" "TTBR0,TTBR1"
|
|
bitfld.long 0x00 16.--18. " T1SZ ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using TTBR0" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
bitfld.long 0x00 7. " EPD0 ,Translation table walk disable for translations using TTBR0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " T0SZ ,The Size offset of the TTBR0 addressed memory region" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
group.long c15:0x0003++0x00
|
|
line.long 0x00 "DACR,Domain Access Control Register"
|
|
bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Synchronous parity error on memory access,Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/First level,Synchronous parity error on memory access on translation table walk/Second level,Synchronous parity error on memory access on translation table walk/Third level,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Lockdown Abort,Reserved,Reserved,Reserved,Reserved,Reserved,Coprocessor Abort,?..."
|
|
else
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " FS ,Fault Status" "Reserved,Alignment fault,Reserved,Reserved,Instruction cache maintenance fault,Translation fault/First level,Access flag fault/Second level,Translation fault/Second level,Synchronous external abort,Domain fault/First level,Reserved,Domain fault/Second level,Synchronous external abort/First level,Permission fault/First level,Synchronous external abort/Second level,Permission fault/Second level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external abort,Reserved,Asynchronous parity error on memory access,Synchronous parity error on memory access,Reserved,Reserved,Synchronous parity error on translation table walk/First level,Reserved,Synchronous parity error on translation table walk/Second level,Reserved"
|
|
endif
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..."
|
|
else
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Non-translation/synchronous external,Domain/section,Reserved,Domain/page,L1/synchronous external,Permission/section,L2/synchronous external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
endif
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x00000000)
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Reserved,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
else
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Reserved,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..."
|
|
endif
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x0015++0x00
|
|
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
|
|
bitfld.long 0x00 31. " VALID ,L1 or L2 ECC double bit error indicator" "No error,Error"
|
|
hexmask.long.byte 0x00 24.--30. 1. " RAMID ,RAM identifier"
|
|
bitfld.long 0x00 23. " L2E ,L2 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index"
|
|
else
|
|
hgroup.long c15:0x0015++0x00
|
|
hide.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
|
|
endif
|
|
group.long c15:0x0006++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Reserved,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Synchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/First level,Synchronous parity error on memory access on translation table walk/Second level,Synchronous parity error on memory access on translation table walk/Third level,?..."
|
|
else
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Reserved,Debug event,Access flag fault/First level,Reserved,Translation fault/First level,Access flag fault/Second level,Translation fault/Second level,Non-translation/synchronous external abort,Domain fault/First level,Reserved,Domain fault/Second level,Synchronous external abort on translation table walk/First level,Permission fault/First level,Synchronous external abort on translation table walk/Second level,Permission fault/Second level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access,Reserved,Reserved,Synchronous parity error on translation table walk,Reserved,Synchronous parity error on translation table walk,Reserved"
|
|
endif
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
if (((d.l(c15:0x0202))&0x80000000)==0x80000000)
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " STATUS ,Generated Exception Type" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access fault flag/First level,Access fault flag/Second level,Access fault flag/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Reserved,Debug event,?..."
|
|
else
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Reserved,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Non-translation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,?..."
|
|
endif
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c15:0x202))&0x80000000)==0x80000000)
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR"
|
|
bitfld.long 0x00 9. " LPAE ,Large physical address extension" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Reserved,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..."
|
|
else
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR"
|
|
bitfld.long 0x00 9. " LPAE ,Large physical address extension" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Reserved,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
endif
|
|
endif
|
|
group.long c15:0x0206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
if (((d.l(c15:0x202))&0x80000000)==0x80000000&&((d.q(c15:0x0047))&0x1)==0x0)
|
|
group.quad c15:0x0047++0x01
|
|
line.quad 0x00 "PAR,Physical Address Register"
|
|
hexmask.quad.byte 0x00 56.--63. 1. " ATTR ,Memory attributes for the returned PA"
|
|
hexmask.quad 0x00 12.--39. 0x1000 " PA ,Physical Address"
|
|
bitfld.quad 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used"
|
|
textline " "
|
|
bitfld.quad 0x00 9. " NS ,Non-secure" "Secure,Non-secure"
|
|
bitfld.quad 0x00 7.--8. " SH ,Shareability attribute" "Non-shareable,Unpredictable,Outer Shareable,Inner Shareable"
|
|
bitfld.quad 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful"
|
|
textline " "
|
|
elif (((d.l(c15:0x202))&0x80000000)==0x80000000&&((d.q(c15:0x0047))&0x1)==0x1)
|
|
group.quad c15:0x0047++0x01
|
|
line.quad 0x00 "PAR,Physical Address Register"
|
|
bitfld.quad 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used"
|
|
bitfld.quad 0x00 9. " FSTAGE ,Translation stage at which the translation aborted" "Stage 1,Stage 2"
|
|
bitfld.quad 0x00 8. " S2WLK ,Stage 2 fault during a stage 1 translation table walk" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.quad 0x00 1.--6. " FS ,Fault status field" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,Synchronous parity error on memory access, Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/1st lvl,Synchronous parity error on memory access on translation table walk/2nd lvl,Synchronous parity error on memory access on translation table walk/3rd lvl,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Domain fault/1st lvl,Domain fault/2nd lvl,Reserved"
|
|
textline " "
|
|
bitfld.quad 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful"
|
|
textline " "
|
|
elif (((d.l(c15:0x202))&0x80000000)==0x00&&((d.q(c15:0x0047))&0x1)==0x0)
|
|
group.long c15:0x0047++0x00
|
|
line.long 0x00 "PAR,Physical Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x1000 " PA ,Physical Address"
|
|
bitfld.long 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used"
|
|
bitfld.long 0x00 10. " NOS ,Not Outer Shareable attribute" "Outer shareable,Not outer shareable"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NS ,Non-secure" "Secure,Non-secure"
|
|
bitfld.long 0x00 7. " SH ,Shareability attribute" "Non-shareable,Shareable"
|
|
bitfld.long 0x00 4.--6. " INNER ,Inner memory attributes" "Non-cacheable,Strongly-ordered,-,Device,-,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " OUTER ,Outer memory attributes" "Non-cacheable,Write-Back Write-Allocate,Write-Through no Write-Allocate,Write-Back no Write-Allocate"
|
|
bitfld.long 0x00 1. " SS ,Supersection" "Not a Supersection,Supersection"
|
|
bitfld.long 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful"
|
|
textline " "
|
|
elif (((d.l(c15:0x202))&0x80000000)==0x00&&((d.q(c15:0x0047))&0x1)==0x1)
|
|
group.long c15:0x0047++0x00
|
|
line.long 0x00 "PAR,Physical Address Register"
|
|
bitfld.long 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 1.--6. " FS ,Fault status" "Reserved,Alignment fault,Debug event,Access flag fault/1st lvl,Fault on instruction cache maintenance,Translation fault/1st lvl,Access flag fault/2nd lvl,Translation fault/2nd lvl,Synchronous external abort,Domain fault/1st lvl,Reserved,Domain fault/2nd lvl,Synchronous external abort on translation table walk/1st lvl,Permission fault/1st lvl,Synchronous external abort on translation table walk/2nd lvl,Permission fault/2nd lvl,TLB conflict abort,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external abort,Reserved,Asynchronous parity error on memory access,Synchronous parity error on memory access,,,Synchronous parity error on translation table walk/1st lvl,Reserved,Synchronous parity error on translation table walk/2nd lvl,Reserved,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful"
|
|
textline " "
|
|
endif
|
|
if (((d.l(c15:0x202))&0x80000000)==0x80000000)
|
|
group.long c15:0x002A++0x00
|
|
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0"
|
|
group.long c15:0x012A++0x00
|
|
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x003A++0x00
|
|
line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0"
|
|
group.long c15:0x013A++0x00
|
|
line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
hgroup.long c15:0x003A++0x00
|
|
hide.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0"
|
|
hgroup.long c15:0x013A++0x00
|
|
hide.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1"
|
|
endif
|
|
else
|
|
group.long c15:0x002A++0x0
|
|
line.long 0x00 "PRRR,Primary Region Remap Register"
|
|
bitfld.long 0x00 31. " NOS7 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 30. " NOS6 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 29. " NOS5 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 28. " NOS4 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 27. " NOS3 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 26. " NOS2 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 25. " NOS1 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 24. " NOS0 ,Outer Shareable property mapping for memory attributes" "Outer,Inner"
|
|
bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
|
|
textline " "
|
|
bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
|
|
bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
group.long c15:0x012A++0x0
|
|
line.long 0x00 "NMRR,Normal Memory Remap Register"
|
|
bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate"
|
|
textline " "
|
|
endif
|
|
if (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x400F++0x00
|
|
line.long 0x00 "CBAR,Configuration Base Address Register"
|
|
hexmask.long.tbyte 0x00 15.--31. 0x80 " PERIPHBASE[31:15] ,Periphbase[31:15]"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PERIPHBASE[39:32] ,Periphbase[39:32]"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
hgroup.long c15:0x400F++0x00
|
|
hide.long 0x00 "CBAR,Configuration Base Address Register"
|
|
endif
|
|
textline " "
|
|
if (((d.l(c15:0x202))&0x80000000)==0x80000000)
|
|
group.long c15:0x10d++0x00
|
|
line.long 0x0 "CONTEXTIDR,Context ID Register"
|
|
else
|
|
group.long c15:0x10d++0x00
|
|
line.long 0x0 "CONTEXTIDR,Context ID Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " PROCID ,Process identifier"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ASID ,Address space identifier"
|
|
endif
|
|
group.long c15:0x020D++0x00
|
|
line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register"
|
|
group.long c15:0x030D++0x00
|
|
line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register"
|
|
group.long c15:0x040D++0x00
|
|
line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register"
|
|
group.long c15:0x420D++0x00
|
|
line.long 0x00 "HTPIDR,Hyp Software Thread ID Register"
|
|
tree.end
|
|
width 15.
|
|
tree "Virtualization Extensions"
|
|
group.long c15:0x4000++0x00
|
|
line.long 0x0 "VPIDR,Virtualization Processor ID Register"
|
|
group.long c15:0x4500++0x00
|
|
line.long 0x0 "VMPIDR,Virtualization Multiprocessor ID Register"
|
|
group.long c15:0x4001++0x00
|
|
line.long 0x00 "HSCTLR,System Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big"
|
|
bitfld.long 0x0 19. " WXN ,Write permission implies XN" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " M ,Enable address translation" "Disabled,Enabled"
|
|
group.long c15:0x4011++0x00
|
|
line.long 0x00 "HCR,Hyp Configuration Register"
|
|
bitfld.long 0x00 27. " TGE ,Trap General Exceptions" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TVM ,Trap Virtual Memory Controls" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " TTLB ,Trap TLB maintenance instructions" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TPU ,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TPC ,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TSW ,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TAC ,Trap Auxiliary Control Register Accesses" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TIDCP ,Trap Lockdown" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TSC ,Trap SMC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TID3 ,Trap ID Group 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TID2 ,Trap ID Group 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TID1 ,Trap ID Group 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TID0 ,Trap ID Group 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TWE ,Trap WFE" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TWI ,Trap WFI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DC ,Default Cacheable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " BSU ,Barrier Shareability Upgrade" "No effect,Inner,Outer,Full system"
|
|
bitfld.long 0x00 9. " FB ,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VA ,Virtual External Asynchronous Abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 7. " VI ,Virtual IRQ interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " VF ,Virtual FIQ interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AMO ,A-bit Mask Override" "No override,Override"
|
|
bitfld.long 0x00 4. " IMO ,I-bit Mask Override" "No override,Override"
|
|
bitfld.long 0x00 3. " FMO ,F-bit Mask Override" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PTW ,Protected Table Walk" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SWIO ,Set/Way Invalidation Override" "No override,Override"
|
|
bitfld.long 0x00 0. " VM ,Second Stage of Translation Enable" "Disabled,Enabled"
|
|
group.long c15:0x4111++0x00
|
|
line.long 0x00 "HDCR,Hyp Debug Control Register"
|
|
bitfld.long 0x00 11. " TDRA ,Trap Debug ROM Access" "No effect,Valid"
|
|
bitfld.long 0x00 10. " TDOSA ,Trap Debug OS-related register Access" "No effect,Valid"
|
|
bitfld.long 0x00 9. " TDA ,Trap Debug Access" "No effect,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TDE ,Trap Debug Exceptions" "No effect,Valid"
|
|
bitfld.long 0x00 7. " HPME ,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TPM ,Trap Performance Monitors accesses" "No effect,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TPMCR ,Trap Performance Monitor Control Register accesses" "No effect,Valid"
|
|
bitfld.long 0x00 0.--4. " HPMN ,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long c15:0x4211++0x00
|
|
line.long 0x00 "HCPTR,Hyp Coprocessor Trap Register"
|
|
bitfld.long 0x0 31. " TCPAC ,Trap Coprocessor Access Control" "Not trapped,Trapped"
|
|
bitfld.long 0x0 15. " TASE ,Trap Advanced SIMD extensions" "Not trapped,Trapped"
|
|
bitfld.long 0x0 11. " TCP11 ,Trap coprocessor 11" "Not trapped,Trapped"
|
|
textline " "
|
|
bitfld.long 0x0 10. " TCP10 ,Trap coprocessor 10" "Not trapped,Trapped"
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hyp Syndrome Register"
|
|
bitfld.long 0x00 26.--31. " EC ,Exception class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 25. " IL ,Instruction length" "16-bit,32-bit"
|
|
hexmask.long 0x00 0.--24. 1. " ISS ,Instruction specific syndrome"
|
|
group.long c15:0x4311++0x00
|
|
line.long 0x00 "HSTR,Hyp System Trap Register"
|
|
bitfld.long 0x00 17. " TJDBX ,Trap Jazelle-DBX" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TTEE ,Trap ThumbEE" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " T15 ,Trap to Hyp mode Non-secure priv 15" "Not trapped,Trapped"
|
|
textline " "
|
|
bitfld.long 0x00 13. " T13 ,Trap to Hyp mode Non-secure priv 13" "Not trapped,Trapped"
|
|
bitfld.long 0x00 12. " T12 ,Trap to Hyp mode Non-secure priv 12" "Not trapped,Trapped"
|
|
bitfld.long 0x00 11. " T11 ,Trap to Hyp mode Non-secure priv 11" "Not trapped,Trapped"
|
|
textline " "
|
|
bitfld.long 0x00 10. " T10 ,Trap to Hyp mode Non-secure priv 10" "Not trapped,Trapped"
|
|
bitfld.long 0x00 9. " T9 ,Trap to Hyp mode Non-secure priv 9" "Not trapped,Trapped"
|
|
bitfld.long 0x00 8. " T8 ,Trap to Hyp mode Non-secure priv 8" "Not trapped,Trapped"
|
|
textline " "
|
|
bitfld.long 0x00 7. " T7 ,Trap to Hyp mode Non-secure priv 7" "Not trapped,Trapped"
|
|
bitfld.long 0x00 6. " T6 ,Trap to Hyp mode Non-secure priv 6" "Not trapped,Trapped"
|
|
bitfld.long 0x00 5. " T5 ,Trap to Hyp mode Non-secure priv 5" "Not trapped,Trapped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " T3 ,Trap to Hyp mode Non-secure priv 3" "Not trapped,Trapped"
|
|
bitfld.long 0x00 2. " T2 ,Trap to Hyp mode Non-secure priv 2" "Not trapped,Trapped"
|
|
bitfld.long 0x00 1. " T1 ,Trap to Hyp mode Non-secure priv 1" "Not trapped,Trapped"
|
|
textline " "
|
|
bitfld.long 0x00 0. " T0 ,Trap to Hyp mode Non-secure priv 0" "Not trapped,Trapped"
|
|
group.quad c15:0x14020++0x01
|
|
line.quad 0x00 "HTTBR,Hyp Translation Table Base Register"
|
|
hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address"
|
|
group.long c15:0x4202++0x00
|
|
line.long 0x00 "HTCR,Hyp Translation Control Register"
|
|
bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using HTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " T0SZ ,The Size offset(four-bit signed integer) of the VTCR addressed region" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1"
|
|
group.quad c15:0x16020++0x01
|
|
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
|
|
hexmask.quad.byte 0x00 48.--55. 1. " VMID ,VMID for the translation table"
|
|
hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address"
|
|
group.long c15:0x4212++0x00
|
|
line.long 0x00 "VTCR,Virtualization Translation Control Register"
|
|
bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SL0 ,Starting Level for VTCR addressed region" "Second level,First level,Reserved,Reserved"
|
|
bitfld.long 0x00 4. " S ,Sign extension bit" "0,1"
|
|
bitfld.long 0x00 0.--3. " T0SZ ,The Size offset(four-bit signed integer) of the VTCR addressed region" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x4015++0x00
|
|
line.long 0x00 "HADFSR,Hyp Auxiliary Data Fault Status Syndrome Register"
|
|
bitfld.long 0x00 31. " VALID ,L1 or L2 ECC double bit error indicator" "No error,Error"
|
|
hexmask.long.byte 0x00 24.--30. 1. " RAMID ,RAM identifier"
|
|
bitfld.long 0x00 23. " L2E ,L2 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index"
|
|
endif
|
|
group.long c15:0x4006++0x00
|
|
line.long 0x00 "HDFAR,Hyp Data Fault Address Register"
|
|
group.long c15:0x4025++0x00
|
|
line.long 0x00 "HSR,Hyp Syndrome Register"
|
|
bitfld.long 0x00 26.--31. " EC ,Exception class" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC,Trapped Jazelle instruction,Trapped BXJ,Reserved,Trapped MRRC,Reserved,Reserved,Reserved,Reserved,SVC,HVC,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,Reserved,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
|
|
textline " "
|
|
bitfld.long 0x00 25. " IL ,Instruction length" "16-bit,32-bit"
|
|
hexmask.long 0x00 0.--24. 1. " ISS ,Instruction specific syndrome"
|
|
group.long c15:0x4206++0x00
|
|
line.long 0x00 "HIFAR,Hyp Instruction Fault Address Register"
|
|
group.long c15:0x4406++0x00
|
|
line.long 0x00 "HPFAR,Hyp IPA Fault Address Register"
|
|
hexmask.long 0x00 4.--31. 1. " FIPA ,Faulting IPA bits"
|
|
textline " "
|
|
hgroup.long c15:0x407++0x00
|
|
hide.long 0x00 "NOP,No Operation Register"
|
|
in
|
|
wgroup.long c15:0x17++0x00
|
|
line.long 0x00 "ICIALLUIS,Invalidate All Instruction Caches To PoU Inner Shareable Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x617++0x00
|
|
line.long 0x00 "BPIALLIS,Invalidate Entire Branch Predictor Array Inner Shareable Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x57++0x00
|
|
line.long 0x00 "ICIALLU,Invalidate Entire Instruction Cache Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x157++0x00
|
|
line.long 0x00 "ICIMVAU,Invalidate Instruction Cache Line by VA to Point-of-Unification Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x457++0x00
|
|
line.long 0x00 "CP15ISB,Instruction Synchronization Barrier Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x657++0x00
|
|
line.long 0x00 "BPIALL,Invalidate Entire Branch Predictor Array (NOP) Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x757++0x00
|
|
line.long 0x00 "BPIMVA,Invalidate MVA From Branch Predictors Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.word 0x00 5.--15. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x167++0x00
|
|
line.long 0x00 "DCIMVAC,Invalidate Data Cache Line by VA to PoC Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x267++0x00
|
|
line.long 0x00 "DCISW,Invalidate Data Cache Line by Set/Way Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x0087++0x00
|
|
line.long 0x00 "ATS1CPR,Stage 1 current state PL1 read"
|
|
wgroup.long c15:0x0187++0x00
|
|
line.long 0x00 "ATS1CPW,Stage 1 current state PL1 write"
|
|
wgroup.long c15:0x0287++0x00
|
|
line.long 0x00 "ATS1CUR,Stage 1 current state unprivileged (PL0) read"
|
|
wgroup.long c15:0x0387++0x00
|
|
line.long 0x00 "ATS1CUW,Stage 1 current state unprivileged (PL0) write"
|
|
wgroup.long c15:0x0487++0x00
|
|
line.long 0x00 "ATS12NSOPR,Stages 1 and 2 Non-secure PL1 read"
|
|
wgroup.long c15:0x0587++0x00
|
|
line.long 0x00 "ATS12NSOPW,Stages 1 and 2 Non-secure PL1 write"
|
|
wgroup.long c15:0x0687++0x00
|
|
line.long 0x00 "ATS12NSOUR,Stages 1 and 2 Non-secure unprivileged (PL0) read"
|
|
wgroup.long c15:0x0787++0x00
|
|
line.long 0x00 "ATS12NSOUW,Stages 1 and 2 Non-secure unprivileged (PL0) write"
|
|
wgroup.long c15:0x1a7++0x00
|
|
line.long 0x00 "DCCMVAC,Clean Data Cache Line to PoC by VA Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x2a7++0x00
|
|
line.long 0x00 "DCCSW,Clean Data Cache Line by Set/Way Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x4a7++0x00
|
|
line.long 0x00 "CP15DSB,Data Synchronization Barrier Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDRESS ,Address to invalidate or clean"
|
|
wgroup.long c15:0x5a7++0x00
|
|
line.long 0x00 "CP15DMB,Data Memory Barrier Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDRESS ,Address to invalidate or clean"
|
|
wgroup.long c15:0x1b7++0x00
|
|
line.long 0x00 "DCCMVAU,Clean Data Or Unified Cache Line By VA To PoU Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
wgroup.long c15:0x1e7++0x00
|
|
line.long 0x00 "DCCIMVAC,Clean and Invalidate Data Cache Line by VA to PoC Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
wgroup.long c15:0x2e7++0x00
|
|
line.long 0x00 "DCCISW,Clean and Invalidate Data Cache Line by Set/Way Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
wgroup.long c15:0x4087++0x00
|
|
line.long 0x00 "ATS1HR,Address Translate Stage 1 Hyp mode Read"
|
|
wgroup.long c15:0x4187++0x00
|
|
line.long 0x00 "ATS1HW,Address Translate Stage 1 Hyp mode Write"
|
|
wgroup.long c15:0x0038++0x00
|
|
line.long 0x00 "TLBIALLIS,Invalidate entire TLB Inner Shareable"
|
|
wgroup.long c15:0x0138++0x00
|
|
line.long 0x00 "TLBIMVAIS,Invalidate unified TLB entry by MVA Inner Shareable"
|
|
wgroup.long c15:0x0238++0x00
|
|
line.long 0x00 "TLBIASIDIS,Invalidate unified TLB byASID match Inner Shareable"
|
|
wgroup.long c15:0x0338++0x00
|
|
line.long 0x00 "TLBIMVAAIS,Invalidate unified TLB by MVA all ASID Inner Shareable"
|
|
wgroup.long c15:0x0058++0x00
|
|
line.long 0x00 "ITLBIALL,Invalidate instruction TLB"
|
|
wgroup.long c15:0x0158++0x00
|
|
line.long 0x00 "ITLBIMVA,Invalidate instruction TLB entry by MVA"
|
|
wgroup.long c15:0x0258++0x00
|
|
line.long 0x00 "ITLBIASID,Invalidate instruction TLB by ASID match"
|
|
wgroup.long c15:0x0068++0x00
|
|
line.long 0x00 "DTLBIALL,Invalidate data TLB"
|
|
wgroup.long c15:0x0168++0x00
|
|
line.long 0x00 "DTLBIMVA,Invalidate data TLB entry by MVA"
|
|
wgroup.long c15:0x0268++0x00
|
|
line.long 0x00 "DTLBIASID,Invalidate data TLB by ASID match"
|
|
wgroup.long c15:0x0078++0x00
|
|
line.long 0x00 "TLBIALL,Invalidate unified TLB"
|
|
wgroup.long c15:0x0178++0x00
|
|
line.long 0x00 "TLBIMVA,Invalidate unified TLB entry by MVA"
|
|
wgroup.long c15:0x0278++0x00
|
|
line.long 0x00 "TLBIASID,Invalidate unified TLB byASID match"
|
|
wgroup.long c15:0x0378++0x00
|
|
line.long 0x00 "TLBIMVAA,Invalidate unified TLB by MVA all ASID"
|
|
wgroup.long c15:0x4038++0x00
|
|
line.long 0x00 "TLBIALLHIS,Invalidate entire Hyp unified TLB Inner Shareable"
|
|
wgroup.long c15:0x4138++0x00
|
|
line.long 0x00 "TLBIMVAHIS,Invalidate Hyp unified TLB entry by MVA Inner Shareable"
|
|
wgroup.long c15:0x4438++0x00
|
|
line.long 0x00 "TLBIALLNSNHIS,Invalidate entire Non-secure Non-Hyp unified TLB Inner Shareable"
|
|
wgroup.long c15:0x4078++0x00
|
|
line.long 0x00 "TLBIALLH,Invalidate entire Hyp unified TLB"
|
|
wgroup.long c15:0x4178++0x00
|
|
line.long 0x00 "TLBIMVAH,Invalidate Hyp unified TLB entry by MVA"
|
|
wgroup.long c15:0x4478++0x00
|
|
line.long 0x00 "TLBIALLNSNH,Invalidate entire Non-secure Non-Hyp unified TLB"
|
|
group.long c15:0x402A++0x00
|
|
line.long 0x00 "HMAIR0,Hyp Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0"
|
|
group.long c15:0x412A++0x00
|
|
line.long 0x00 "HMAIR1,Hyp Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x403A++0x00
|
|
line.long 0x00 "HAMAIR0,Hyp Auxiliary Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0"
|
|
group.long c15:0x413A++0x00
|
|
line.long 0x00 "HAMAIR1,Hyp Auxiliary Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4"
|
|
else
|
|
hgroup.long c15:0x403A++0x00
|
|
hide.long 0x00 "HAMAIR0,Hyp Auxiliary Memory Attribute Indirection Register 0"
|
|
hgroup.long c15:0x413A++0x00
|
|
hide.long 0x00 "HAMAIR1,Hyp Auxiliary Memory Attribute Indirection Register 1"
|
|
endif
|
|
group.long c15:0x400C++0x00
|
|
line.long 0x00 "HVBAR,Hyp Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " HVBADDR ,Hyp Vector Base Address"
|
|
tree.end
|
|
width 12.
|
|
tree "Cache Control and Configuration"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
rgroup.long c15:0x1100++0x0
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOUU ,Level of Unification Uniprocessor" "Reserved,Level 2,?..."
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Reserved,Reserved,Level 3,?..."
|
|
bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Reserved,Level 2,?..."
|
|
bitfld.long 0x00 18.--20. " CTYPE7 ,Cache type for levels 7" "No cache,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CTYPE6 ,Cache type for levels 6" "No cache,?..."
|
|
bitfld.long 0x00 12.--14. " CTYPE5 ,Cache type for levels 5" "No cache,?..."
|
|
bitfld.long 0x00 9.--11. " CTYPE4 ,Cache type for levels 4" "No cache,?..."
|
|
bitfld.long 0x00 6.--8. " CTYPE3 ,Cache type for levels 3" "No cache,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..."
|
|
bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..."
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c15:0x1100++0x0
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOUU ,Level of Unification Uniprocessor" "Reserved,Level 2,?..."
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Reserved,Reserved,Level 3,?..."
|
|
bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Reserved,Level 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "Not implemented,Reserved,Reserved,Reserved,Unified,?..."
|
|
bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..."
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
rgroup.long c15:0x1000++0x0
|
|
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported"
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported"
|
|
hexmask.long.word 0x00 13.--27. 1. " SETS ,Number of Sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "Reserved,Reserved,16 words,?..."
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c15:0x1000++0x0
|
|
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported"
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported"
|
|
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of Sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "Reserved,8 words,16 words,?..."
|
|
endif
|
|
group.long c15:0x2000++0x0
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level of required cache" "Level 1,Level 2,?..."
|
|
bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data/Unified,Instruction"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
wgroup.long c15:0x10EF++0x00
|
|
line.long 0x00 "DCCIALL,Data Cache Clean and Invalidate All Register"
|
|
bitfld.long 0x00 1.--2. " LEVEL ,Cache level" "L1,L2,Reserved,Reserved"
|
|
else
|
|
hgroup.long c15:0x10EF++0x00
|
|
hide.long 0x00 "DCCIALL,Data Cache Clean and Invalidate All Register"
|
|
endif
|
|
tree "Level 1 memory system"
|
|
width 10.
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x000F++0x00
|
|
line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register"
|
|
group.long c15:0x010F++0x00
|
|
line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register"
|
|
group.long c15:0x020F++0x00
|
|
line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register"
|
|
group.long c15:0x001F++0x00
|
|
line.long 0x00 "DL1DATA0,Data L1 Data 0 Register"
|
|
group.long c15:0x011F++0x00
|
|
line.long 0x00 "DL1DATA1,Data L1 Data 1 Register"
|
|
group.long c15:0x021F++0x00
|
|
line.long 0x00 "DL1DATA2,Data L1 Data 2 Register"
|
|
group.long c15:0x031F++0x00
|
|
line.long 0x00 "DL1DATA3,Data L1 Data 3 Register"
|
|
wgroup.long c15:0x004F++0x00
|
|
line.long 0x00 "RAMINDEX,RAM Index Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RAMID ,RAM identifier"
|
|
bitfld.long 0x00 18.--21. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index"
|
|
textline " "
|
|
group.quad c15:0x100F0++0x01
|
|
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. " FATAL ,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. " OEC ,Other error count"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " REC ,Repeat error count"
|
|
bitfld.quad 0x00 31. " VALID ,Valid bit" "Not valid,Valid"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 24.--30. 1. " RAMID ,RAM Identifier"
|
|
bitfld.quad 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.quad.tbyte 0x00 0.--17. 1. " IND ,Index"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c15:0x300F++0x0
|
|
line.long 0x00 "CDBGDR0,Data Register 0"
|
|
rgroup.long c15:0x310F++0x0
|
|
line.long 0x00 "CDBGDR1,Data Register 1"
|
|
rgroup.long c15:0x320F++0x0
|
|
line.long 0x00 "CDBGDR2,Data Register 2"
|
|
wgroup.long c15:0x302F++0x0
|
|
line.long 0x00 "CDBGDCT,Data Cache Tag Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.tbyte 0x00 6.--29. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CWDO ,Cache word data offset" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x312F++0x0
|
|
line.long 0x00 "CDBGICT,Instruction Cache Tag Read Operation Register"
|
|
bitfld.long 0x00 31. " CW ,Cache Way" "Low,High"
|
|
hexmask.long 0x00 5.--30. 1. " SI ,Set index"
|
|
bitfld.long 0x00 2.--4. " CDEO ,Cache data element offset" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x304F++0x0
|
|
line.long 0x00 "CDBGDCD,Data Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.tbyte 0x00 6.--29. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CWDO ,Cache word data offset" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 31. " CW ,Cache Way" "Low,High"
|
|
hexmask.long 0x00 5.--30. 1. " SI ,Set index"
|
|
bitfld.long 0x00 2.--4. " CDEO ,Cache data element offset" "0,1,2,3,4,5,6,7"
|
|
wgroup.long c15:0x324F++0x0
|
|
line.long 0x00 "CDBGTD,TLB Data Read Operation Register"
|
|
bitfld.long 0x00 31. " TLB_WAY ,TLB Way" "Low,High"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TLB_IND ,TLB index"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c15:0x300F++0x0
|
|
line.long 0x00 "CDBGDR0,Data Register 0"
|
|
bitfld.long 0x00 31. " PMOESID ,Partial MOESI state / Dirty" "Low,High"
|
|
bitfld.long 0x00 30. " POMA ,Partial Outer memory attribute" "Low,High"
|
|
bitfld.long 0x00 29. " PMOESIE ,Partial MOESI state / Exclusive" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PMOESIV ,Partial MOESI state / Valid" "Low,High"
|
|
bitfld.long 0x00 27. " NS ,Non-Secure state" "Low,High"
|
|
hexmask.long 0x00 0.--26. 1. " TA ,Tag Address"
|
|
rgroup.long c15:0x310F++0x0
|
|
line.long 0x00 "CDBGDR1,Data Register 1"
|
|
bitfld.long 0x00 0. " PMOESID ,Partial MOESI state / Globally shared" "Low,High"
|
|
rgroup.long c15:0x320F++0x0
|
|
line.long 0x00 "CDBGDR2,Data Register 2"
|
|
wgroup.long c15:0x302F++0x0
|
|
line.long 0x00 "CDBGDCT,Data Cache Tag Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index"
|
|
wgroup.long c15:0x312F++0x0
|
|
line.long 0x00 "CDBGICT,Instruction Cache Tag Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long 0x00 6.--30. 1. " SI ,Set index"
|
|
wgroup.long c15:0x304F++0x0
|
|
line.long 0x00 "CDBGDCD,Data Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
if (((d.l(c15:0x1000))&0xFFFE000)==0x1DE000)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FE000&&((d.l(c15:0x2000))&0x3)==0x1)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.byte 0x00 6.--13. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FE000&&((d.l(c15:0x2000))&0x3)==0x2)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.word 0x00 6.--15. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0x3FE000)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.word 0x00 6.--16. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0x7FE000)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.word 0x00 6.--17. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0xFFE000)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.word 0x00 6.--18. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FFE000)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.word 0x00 6.--19. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
elif (((d.l(c15:0x1000))&0xFFFE000)==0x3FFE000)
|
|
wgroup.long c15:0x314F++0x0
|
|
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3"
|
|
hexmask.long.word 0x00 6.--20. 1. " SI ,Set index"
|
|
bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
|
|
else
|
|
hgroup.long c15:0x314F++0x0
|
|
hide.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
|
|
endif
|
|
if (((d.l(c15:0x324F))&0x100)==0x100)
|
|
wgroup.long c15:0x324F++0x0
|
|
line.long 0x00 "CDBGTD,TLB Data Read Operation Register"
|
|
bitfld.long 0x00 8. " TYPE ,Type" "RAM0,RAM1"
|
|
else
|
|
wgroup.long c15:0x324F++0x0
|
|
line.long 0x00 "CDBGTD,TLB Data Read Operation Register"
|
|
bitfld.long 0x00 30.--31. " TLB_WAY ,TLB Way" "0,1,2,3"
|
|
bitfld.long 0x00 8. " TYPE ,Type" "RAM0,RAM1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TLB_IND ,TLB index"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Level 2 memory system"
|
|
width 11.
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x1209++0x0
|
|
line.long 0x00 "L2CTLR,L2 Control Register"
|
|
rbitfld.long 0x00 31. " L2RSTDISABLE ,L2 hardware reset disable pin monitor" "No,Yes"
|
|
bitfld.long 0x00 24.--25. " NCPU , Number of CPU" "1,2,3,4"
|
|
bitfld.long 0x00 23. " IE ,Interrupt Controller" "Not present,Present"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ECCPE ,ECC and parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TRAMS ,L2 Tag RAM setup" "0 cycle,1 cycle"
|
|
bitfld.long 0x00 10.--11. " DRAMSLICE ,Data RAM slice" "0,1,2,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TRAMS ,L2 Tag RAM setup" "0 cycle,1 cycle"
|
|
bitfld.long 0x00 6.--8. " TRAML ,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles"
|
|
bitfld.long 0x00 5. " DRAMS ,L2 Data RAM setup" "0 cycle,1 cycle"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " DRAML ,L2 Data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c15:0x1209++0x0
|
|
line.long 0x00 "L2CTLR,L2 Control Register"
|
|
bitfld.long 0x00 24.--25. " NCPU ,Number of CPU" "1,2,3,4"
|
|
bitfld.long 0x00 23. " IE ,Interrupt Controller" "Not present,Present"
|
|
bitfld.long 0x00 0. " DRAML ,L2 data RAM latency" "2 cycles,3 cycles"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c15:0x1209++0x0
|
|
line.long 0x00 "L2CTLR,L2 Control Register"
|
|
rbitfld.long 0x00 31. " L2RSTDISABLE ,L2 hardware reset disable pin monitor" "No,Yes"
|
|
bitfld.long 0x00 27.--30. " IWINC ,Controls index incrementation method" "1.,1.,3.,7.,15.,31.,63.,127.,255.,511.,1023.,2047.,4095.,8191.,8191.,8191."
|
|
rbitfld.long 0x00 24.--25. " NCPU , Number of CPU" "1,2,3,4"
|
|
bitfld.long 0x00 20. " SFEN , Snoop Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " L2ECCD ,L2 ECC Disable" "No,Yes"
|
|
bitfld.long 0x00 18. " L2CD ,L2 cache disable" "No,Yes"
|
|
bitfld.long 0x00 15.--17. " TRAMSL ,Tag RAM setup latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x00 12.--14. " TRAMRL ,Tag RAM read latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " TRAMWL ,Tag RAM write latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x00 6.--8. " DRAMSL ,Data RAM setup latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x00 3.--5. " DRAMRL ,Data RAM read latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
bitfld.long 0x00 0.--2. " DRAMWL ,Data RAM write latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c15:0x1309++0x0
|
|
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
|
|
bitfld.long 0x00 30. " L2INTASYNCERR ,L2 internal asynchronous error" "No error,Error"
|
|
bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error"
|
|
group.long c15:0x100F++0x00
|
|
line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register"
|
|
bitfld.long 0x00 28. " FL2TBCEA ,Forces L2 tag bank clock enable active" "Not forced,Forced"
|
|
bitfld.long 0x00 27. " FL2LCEA ,Forces L2 logic clock enable active" "Not forced,Forced"
|
|
bitfld.long 0x00 26. " EL2GTRCG ,Enables L2 GIC and Timer regional clock gates" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ERTSI ,Enables replay threshold single issue" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ECWRM ,Enable CPU WFI retention mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EUCE ,Enables UniqueClean evictions with data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DSCDT ,Disables SharedClean data transfers" "No,Yes"
|
|
bitfld.long 0x00 12. " DWCWBE ,Disable multiple outstanding WriteClean/WriteBack/Evicts using the same AWID" "No,Yes"
|
|
bitfld.long 0x00 11. " DDSB ,Disables DSB with no DVM synchronization" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DNSDAR ,Disables non-secure debug array read" "No,Yes"
|
|
bitfld.long 0x00 9. " EPF ,Enable use of Prefetch bit in L2 cache replacement algorithm" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DDVMCMOMB ,Disables Distributed Virtual Memory (DVM) transactions and cache maintenance operation message broadcast" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EHDT ,Enables hazard detect timeout" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DSTFM ,Disables shared transactions from master" "No,Yes"
|
|
bitfld.long 0x00 4. " DWUAWLUTFM ,Disables WriteUnique and WriteLineUnique transactions from master" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DCEPTE ,Disables clean/evict push to external" "No,Yes"
|
|
bitfld.long 0x00 2. " LTORPTB ,Limit to one request per tag bank" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EARTT ,Enable arbitration replay threshold timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DPF ,Disable prefetch forwarding" "No,Yes"
|
|
group.long c15:0x130F++0x00
|
|
line.long 0x00 "L2PFR,L2 Prefetch Control Register"
|
|
bitfld.long 0x00 12. " DDTOLSPR ,Disable dynamic throttling of load/store prefetch requests" "No,Yes"
|
|
bitfld.long 0x00 11. " EPRFRUT ,Enable prefetch request from ReadUnique transactions" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DTWDAP ,Disable table walk descriptor access prefetch" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " L2IFPD ,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines"
|
|
bitfld.long 0x00 4.--5. " L2LSDPD ,L2 load/store data prefetch distance" "0 lines,2 lines,4 lines,8 lines"
|
|
textline " "
|
|
group.quad c15:0x110F0++0x01
|
|
line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
|
|
bitfld.quad 0x00 63. " FATAL ,Fatal bit" "0,1"
|
|
hexmask.quad.byte 0x00 40.--47. 1. " OEC ,Other error count"
|
|
hexmask.quad.byte 0x00 32.--39. 1. " REC ,Repeat error count"
|
|
bitfld.quad 0x00 31. " VALID ,Valid bit" "Not valid,Valid"
|
|
textline " "
|
|
hexmask.quad.byte 0x00 24.--30. 1. " RAMID ,RAM Identifier"
|
|
bitfld.quad 0x00 18.--21. " C/W ,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
|
|
hexmask.quad.tbyte 0x00 0.--17. 1. " IND ,Index"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c15:0x1309++0x0
|
|
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
|
|
bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error"
|
|
hgroup.quad c15:0x110F0++0x01
|
|
hide.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c15:0x1309++0x0
|
|
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
|
|
bitfld.long 0x00 30. " ECCUNERR ,ECC uncorrectable error " "No error,Error"
|
|
bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error"
|
|
bitfld.long 0x00 0. " L2DRC ,Disable L2 retention" "No,Yes"
|
|
rgroup.long c15:0x1609++0x00
|
|
line.long 0x00 "L2MRERRSR,L2 Memory Error Syndrome Register"
|
|
bitfld.long 0x00 31. " FATAL ,Fatal bit" "0,1"
|
|
bitfld.long 0x00 25.--30. " OEC ,Other error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 19.--24. " REC ,Repeat error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 6.--18. 1. " ERRLIND ,Index Error Location"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " ERRLWAY ,Way Error Location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " RAMID ,RAM Identifier" "TAG,DATA"
|
|
bitfld.long 0x00 0. " VALID ,Valid bit" "Not valid,Valid"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
width 12.
|
|
tree "System Performance Monitor"
|
|
group.long c15:0xc9++0x00
|
|
line.long 0x0 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "No,Yes"
|
|
bitfld.long 0x00 4. " X ,Export Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle"
|
|
textline " "
|
|
bitfld.long 0x00 2. " C ,Clock Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " P ,Performance Counter Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " E ,All Counters Enable" "Disabled,Enabled"
|
|
group.long c15:0x1c9++0x00
|
|
line.long 0x00 "PMNCNTENSET,Count Enable Set Register "
|
|
bitfld.long 0x00 5. " P5 ,Event Counter 5 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Event Counter 4 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,Event Counter 3 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Event Counter 2 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Event Counter 1 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Event Counter 0 enable bit" "Disabled,Enabled"
|
|
group.long c15:0x2c9++0x00
|
|
line.long 0x00 "PMCNTENCLR,Count Enable Clear Register"
|
|
eventfld.long 0x00 5. " P5 ,Event Counter 5 clear bit" "Disabled,Enabled"
|
|
eventfld.long 0x00 4. " P4 ,Event Counter 4 clear bit" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Event Counter 3 clear bit" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 2. " P2 ,Event Counter 2 clear bit" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Event Counter 1 clear bit" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Event Counter 0 clear bit" "Disabled,Enabled"
|
|
group.long c15:0x3c9++0x00
|
|
line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register"
|
|
eventfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 4. " P4 ,PMN4 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow"
|
|
group.long c15:0x4c9++0x00
|
|
line.long 0x00 "PMSWINC,Performance Monitor Software Increment"
|
|
bitfld.long 0x00 5. " P5 ,Increment PMN5" "No action,Increment"
|
|
bitfld.long 0x00 4. " P4 ,Increment PMN4" "No action,Increment"
|
|
bitfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
bitfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
bitfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group.long c15:0x5c9++0x00
|
|
line.long 0x00 "PMSELR,Performance Monitor Select Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Current event counter select" "0,1,2,3,4,5,?..."
|
|
group.long c15:0xd9++0x00
|
|
line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register"
|
|
group.long c15:0x1d9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register"
|
|
bitfld.long 0x00 31. " P ,Execution at PL1 events counting disable" "No,Yes"
|
|
bitfld.long 0x00 30. " U ,Execution at PL0 events counting disable" "No,Yes"
|
|
bitfld.long 0x00 29. " NSK ,Execution in Non-secure state at PL1 events counting disable" "No,Yes"
|
|
bitfld.long 0x00 28. " NSU ,Execution in Non-secure state at PL0 events counting disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " NSH ,Execution in Non-secure state at PL2 events counting enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EVTCOUNT ,Event to count"
|
|
group.long c15:0x2d9++0x00
|
|
line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register"
|
|
group.long c15:0xe9++0x00
|
|
line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User mode access enable" "Disabled,Enabled"
|
|
group.long c15:0x1e9++0x00
|
|
line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set"
|
|
bitfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
group.long c15:0x2e9++0x00
|
|
line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear"
|
|
eventfld.long 0x00 5. " P5 ,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 4. " P4 ,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " P1 ,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Overflow Interrupt Clear" "Disabled,Enabled"
|
|
group.long c15:0x3e9++0x00
|
|
line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register"
|
|
bitfld.long 0x00 31. " C ,PMCCNTR overflow bit" "Not overflowed,Overflowed"
|
|
bitfld.long 0x00 30. " P30 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " P29 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " P28 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " P27 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " P26 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " P25 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " P24 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " P23 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P22 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " P21 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P20 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P19 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P18 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " P17 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P16 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " P15 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P14 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " P13 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " P12 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P11 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " P10 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " P9 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " P8 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " P6 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,Event Counter Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " P2 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,Event Counter Overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,Event Counter Overflow" "Disabled,Enabled"
|
|
tree.end
|
|
width 12.
|
|
tree "System Timer Register"
|
|
group.long c15:0x000E++0x00
|
|
line.long 0x00 "CNTFRQ,Counter Frequency Register"
|
|
group.long c15:0x001E++0x00
|
|
line.long 0x00 "CNTKCTL,Timer PL1 Control Register"
|
|
bitfld.long 0x00 9. " PL0PTEN ,Controls whether the physical timer registers are accessible from PL0 modes" "Not accessible,Accessible"
|
|
bitfld.long 0x00 8. " PL0VTEN ,Controls whether the virtual timer registers are accessible from PL0 modes" "Not accessible,Accessible"
|
|
bitfld.long 0x00 4.--7. " EVNTI ,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EVNTDIR ,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
|
|
bitfld.long 0x00 2. " EVNTEN ,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PL0VCTEN ,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PL0PCTEN ,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible"
|
|
textline ""
|
|
group.quad c15:0x100E0++0x01
|
|
line.quad 0x00 "CNTPCT,Counter Physical Count Register"
|
|
group.quad c15:0x120E0++0x01
|
|
line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register"
|
|
group.long c15:0x002E++0x00
|
|
line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Timer Value Register"
|
|
group.long c15:0x012E++0x00
|
|
line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register"
|
|
bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled"
|
|
textline ""
|
|
group.quad c15:0x110E0++0x01
|
|
line.quad 0x00 "CNTVCT,Counter Virtual Count Register"
|
|
group.quad c15:0x130E0++0x01
|
|
line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register"
|
|
group.long c15:0x003E++0x00
|
|
line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register"
|
|
group.long c15:0x013E++0x00
|
|
line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register"
|
|
bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled"
|
|
group.quad c15:0x140E0++0x01
|
|
line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register"
|
|
textline ""
|
|
group.long c15:0x401E++0x00
|
|
line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register"
|
|
bitfld.long 0x00 4.--7. " EVNTI ,Selects which bit of CNTPCTis the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 3. " EVNTDIR ,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
|
|
bitfld.long 0x00 2. " EVNTEN ,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PL1VCTEN ,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible"
|
|
bitfld.long 0x00 0. " PL1PCTEN ,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible"
|
|
group.quad c15:0x160E0++0x01
|
|
line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register"
|
|
group.long c15:0x402E++0x00
|
|
line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register"
|
|
group.long c15:0x412E++0x00
|
|
line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register"
|
|
bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled"
|
|
tree.end
|
|
width 11.
|
|
width 15.
|
|
tree "Debug Registers"
|
|
rgroup.long c14:0.++0x0
|
|
line.long 0x0 "DBGDIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version"
|
|
bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High"
|
|
bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Supported,Not supported"
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Not implemented,Implemented"
|
|
hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number"
|
|
textline " "
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
wgroup.long c14:6.++0x0
|
|
line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c14:1.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " DBGNOPWRDWN ,Debug no power-down" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
wgroup.long c14:5.++0x0
|
|
line.long 0x00 "DBGDTRTX,Debug Transmit/Receive Register (Internal View)"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c14:195.))&0x1)==0x1)
|
|
group.long c14:1.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
rbitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
|
|
rbitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
rbitfld.long 0x00 18. " NS ,Non-secure state status" "Secure,Non-secure"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
rbitfld.long 0x00 9. " FS ,Fault status" "No exception,Exception"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
else
|
|
rgroup.long c14:1.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)"
|
|
rbitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
rbitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
rbitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
rbitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
rbitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
rbitfld.long 0x00 18. " NS ,Non-secure state status" "Secure,Non-secure"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " FS ,Fault status" "No exception,Exception"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
endif
|
|
wgroup.long c14:5.++0x0
|
|
line.long 0x00 "DBGDTRTX,Debug Transmit/Receive Register (Internal View)"
|
|
endif
|
|
group.long c14:0x7++0x0
|
|
line.long 0x00 "DBGVCR,Debug Vector Catch register"
|
|
bitfld.long 0x00 31. " NSF ,FIQ vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " NSI ,IRG vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " NSD ,Data Abort vector catch in Non-secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " NSP ,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " NSS ,SVC vector catch in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " NSU ,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " NSHF ,FIQ interrupt exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " NSHI ,IRQ interrupt exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " NSHE ,Hyp Trap or Hyp mode entry exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " NSHD ,Data Abort, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " NSHP ,Prefetch Abort, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " NSHC ,Hypervisor Call. from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " NSHU ,Undefined Instruction, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MF ,FIQ vector catch enable, in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MI ,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " MD ,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MP ,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MS ,SMC vector catch enable in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SF ,FIQ vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SI ,IRQ vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SD ,Data Abort vector catch in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SP ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SS ,SVC vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SU ,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " R ,Reset vector catch enable" "Disabled,Enabled"
|
|
group.long c14:9.++0x0
|
|
line.long 0x00 "DBGECR,Debug Event Catch Register"
|
|
bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled"
|
|
group.long c14:32.++0x0
|
|
line.long 0x00 "DBGDTRRX,Debug Receive Register (External View)"
|
|
wgroup.long c14:33.++0x0
|
|
line.long 0x00 "DBGITR,Debug Instruction Transfer Register"
|
|
rgroup.long c14:33.++0x0
|
|
line.long 0x00 "DBGPCSR,Program Counter Sampling Register"
|
|
hexmask.long 0x00 2.--31. 1. " PCS ,Program Counter sample value"
|
|
bitfld.long 0x00 0.--1. " T ,Meaning of PC sample value" "ARM,Thumb,Reserved,Thumb"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
bitfld.long 0x00 25. " PIPEADC ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " FS ,Fault Status" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
bitfld.long 0x00 25. " PIPEADC ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " DBGNOPWRDWN ,Debug no power-down" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c14:195.))&0x1)==0x1)
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
rbitfld.long 0x00 25. " PIPEADV ,Sticky Pipeline Advance bit" "Not idle,Idle"
|
|
rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not complete,Complete"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Discarded"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " FS ,Fault status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
else
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)"
|
|
rbitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
rbitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
rbitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched"
|
|
textline " "
|
|
rbitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched"
|
|
rbitfld.long 0x00 25. " PIPEADV ,Sticky Pipeline Advance bit" "Not idle,Idle"
|
|
rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not complete,Complete"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Discarded"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled"
|
|
rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
bitfld.long 0x00 9. " FS ,Fault status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..."
|
|
rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
endif
|
|
endif
|
|
wgroup.long c14:35.++0x0
|
|
line.long 0x00 "DBGDTRTX,Debug Transmit Register (External View)"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
wgroup.long c14:36.++0x0
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear"
|
|
bitfld.long 0x00 1. " RRQ ,Restart request" "No effect,Restart"
|
|
bitfld.long 0x00 0. " HRQ ,Halt request" "No effect,Halt"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
wgroup.long c14:36.++0x0
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 4. " CBRRQ ,CBRRQ" "Low,High"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart"
|
|
bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt"
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
group.long c14:37.++0x0
|
|
line.long 0x00 "DBGEACR,Debug External Auxiliary Control Register"
|
|
bitfld.long 0x00 3. " CDRS ,Core debug reset status" "No reset,Reset"
|
|
bitfld.long 0x00 2. " DECRR ,Debug extend core reset request" "No request,Request"
|
|
bitfld.long 0x00 1. " DPDO ,Debug power-down override" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DCSC ,Debug clock stop control" "Stopped,Running"
|
|
textline " "
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:37.++0x0
|
|
line.long 0x00 "DBGEACR,Debug External Auxiliary Control Register"
|
|
bitfld.long 0x00 3. " CDRS ,Core debug reset status" "No reset,Reset"
|
|
endif
|
|
rgroup.long c14:40.++0x0
|
|
line.long 0x00 "DBGPCSR,Program Counter Sampling Register"
|
|
hexmask.long 0x00 2.--31. 1. " PCS ,Program Counter sample value"
|
|
bitfld.long 0x00 0.--1. " T ,Meaning of PC sample value" "ARM,Thumb,?..."
|
|
rgroup.long c14:41.++0x0
|
|
line.long 0x00 "DBGCIDSR,DBGCIDSR"
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c14:42.++0x0
|
|
line.long 0x00 "DBGVIDSR,Virtualization ID Sampling Register"
|
|
bitfld.long 0x00 31. " NS ,NS state sample" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " H ,Hyp mode sample" "Not associated,Associated"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VMID ,VMID sample"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c14:42.++0x0
|
|
line.long 0x00 "DBGVIDSR,DBGVIDSR"
|
|
endif
|
|
width 15.
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
textline " "
|
|
wgroup.long c14:958.++0x0
|
|
line.long 0x00 "DBGITOCTRL,Debug Integration Output Control Register"
|
|
bitfld.long 0x00 3. " NPMUIRQ ,Drives the nPMUIRQ output" "Low,High"
|
|
bitfld.long 0x00 2. " CTI_PMUIRQ ,Drives the internal signal equivalent to PMUIRQ that goes from the Performance Monitor Unit (PMU) to the Cross Trigger Interface (CTI)" "Low,High"
|
|
bitfld.long 0x00 1. " CTI_DBGRESTARTED ,Drives the internal signal that goes from the Debug unit to the CTI to acknowledge success of a debug restart command" "Low,High"
|
|
bitfld.long 0x00 0. " CTI_DBGTRIGGER ,Drives the internal signal equivalent to DBGTRIGGER that goes from the Debug unit to the CTI" "Low,High"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
textline " "
|
|
wgroup.long c14:958.++0x0
|
|
line.long 0x00 "DBGITMISCOUT,Integration Miscellaneous Signals Output Register"
|
|
bitfld.long 0x00 9. " DBGRESTARTED ,Value of the DBGRESTARTED output pin" "Low,High"
|
|
bitfld.long 0x00 4. " PMUIRQ ,Value of PMUIRQ output pin" "Low,High"
|
|
bitfld.long 0x00 0. " DBGACK ,Value of the DBGACK output pin" "Low,High"
|
|
endif
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE")
|
|
rgroup.long c14:959.++0x0
|
|
line.long 0x00 "DBGITISR,Debug Integration Input Status Register"
|
|
bitfld.long 0x00 3. " DBGSWENABLE ,Reads the state of the DBGSWENABLE input" "Low,High"
|
|
bitfld.long 0x00 2. " CTI_DBGRESTART ,CTI debug restart" "Low,High"
|
|
bitfld.long 0x00 1. " CTI_EDBGRQ ,CTI debug request" "Low,High"
|
|
bitfld.long 0x00 0. " EDBGRQ ,Reads the state of the EDBGRQ input" "Low,High"
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
textline " "
|
|
rgroup.long c14:959.++0x0
|
|
line.long 0x00 "DBGITMISCIN,Integration Miscellaneous Signals Input Register"
|
|
bitfld.long 0x00 2. " NFIQ ,Read value of nFIQ input pin" "Low,High"
|
|
bitfld.long 0x00 1. " NIRQ ,Read value of nIRQ input pin" "Low,High"
|
|
bitfld.long 0x00 0. " EDBGRQ ,Read value of EDBGRQ input pin" "Low,High"
|
|
endif
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
if (((d.l(c15:0x202))&0x80000000)==0x80000000)
|
|
rgroup.quad c14:128.++0x1
|
|
line.quad 0x0 "DBGDRAR,Debug ROM Address Register"
|
|
hexmask.quad 0x0 12.--39. 0x1000 " ROMADDR ,ROM physical address"
|
|
bitfld.quad 0x0 0.--1. " VALID ,ROM table address valid" "Not valid,Reserved,Reserved,Valid"
|
|
rgroup.quad c14:256.++0x1
|
|
line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register"
|
|
hexmask.quad 0x0 12.--39. 0x1000 " SELFOFFSET ,Debug bus self-address offset value"
|
|
bitfld.quad 0x0 0.--1. " VALID ,Debug self address offset valid" "Not valid,Reserved,Reserved,Valid"
|
|
else
|
|
rgroup.long c14:128.++0x0
|
|
line.long 0x0 "DBGDRAR,Debug ROM Address Register"
|
|
hexmask.long 0x0 12.--31. 0x1000 " ROMADDR ,ROM physical address"
|
|
bitfld.long 0x0 0.--1. " VALID ,ROM table address valid" "Not valid,Reserved,Reserved,Valid"
|
|
rgroup.long c14:256.++0x0
|
|
line.long 0x0 "DBGDSAR,Debug Self Address Offset Register"
|
|
hexmask.long 0x0 12.--31. 0x1000 " SELFOFFSET ,Debug bus self-address offset value"
|
|
bitfld.long 0x0 0.--1. " VALID ,Debug self address offset valid" "Not valid,Reserved,Reserved,Valid"
|
|
endif
|
|
group.long c14:195.++0x00
|
|
line.long 0x00 "DBGOSDLR,OS Double Lock Register"
|
|
bitfld.long 0x00 0. " DLK ,OS Double Lock control bit" "Unlocked,Locked"
|
|
else
|
|
hgroup.quad c14:128.++0x1
|
|
hide.quad 0x0 "DBGDRAR,Debug ROM Address Register"
|
|
hgroup.quad c14:256.++0x1
|
|
hide.quad 0x0 "DBGDSAR,Debug Self Address Offset Register"
|
|
hgroup.long c14:195.++0x00
|
|
hide.long 0x00 "DBGOSDLR,OS Double Lock Register"
|
|
endif
|
|
wgroup.long c14:192.++0x00
|
|
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
|
|
rgroup.long c14:193.++0x00
|
|
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 1. " OSLK ,Status of the OS Lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. 3. " OSLM ,OS Lock Model implemented Bit" "Reserved,Reserved,W/o DBGOSSRR,?..."
|
|
group.long c14:196.++0x00
|
|
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
|
|
bitfld.long 0x00 3. " COREPURQ ,Core Power Up Request" "Low,High"
|
|
bitfld.long 0x00 2. " HCWR ,Hold Core Warm Reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " CWRR ,Core Warm Reset Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CORENPDRQ ,Core No Power down Request" "Low,High"
|
|
rgroup.long c14:197.++0x0
|
|
line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register"
|
|
bitfld.long 0x00 6. " DLK ,OS Double Lock status" "Low,High"
|
|
bitfld.long 0x00 5. " OSLK ,OS Lock status" "Low,High"
|
|
bitfld.long 0x00 4. " HALTED ,Halted" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Low,High"
|
|
bitfld.long 0x00 2. " RS ,Reset Status" "Low,High"
|
|
bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PU ,Power-up Status" "Low,High"
|
|
tree "Processor ID registers"
|
|
rgroup.long c14:(832.+0.)++0x00
|
|
line.long 0x00 "PIDR0,Processor ID register 0"
|
|
rgroup.long c14:(832.+1.)++0x00
|
|
line.long 0x00 "PIDR1,Processor ID register 1"
|
|
rgroup.long c14:(832.+2.)++0x00
|
|
line.long 0x00 "PIDR2,Processor ID register 2"
|
|
rgroup.long c14:(832.+3.)++0x00
|
|
line.long 0x00 "PIDR3,Processor ID register 3"
|
|
rgroup.long c14:(832.+4.)++0x00
|
|
line.long 0x00 "PIDR4,Processor ID register 4"
|
|
rgroup.long c14:(832.+5.)++0x00
|
|
line.long 0x00 "PIDR5,Processor ID register 5"
|
|
rgroup.long c14:(832.+6.)++0x00
|
|
line.long 0x00 "PIDR6,Processor ID register 6"
|
|
rgroup.long c14:(832.+7.)++0x00
|
|
line.long 0x00 "PIDR7,Processor ID register 7"
|
|
rgroup.long c14:(832.+8.)++0x00
|
|
line.long 0x00 "PIDR8,Processor ID register 8"
|
|
rgroup.long c14:(832.+9.)++0x00
|
|
line.long 0x00 "PIDR9,Processor ID register 9"
|
|
rgroup.long c14:(832.+10.)++0x00
|
|
line.long 0x00 "PIDR10,Processor ID register 10"
|
|
rgroup.long c14:(832.+11.)++0x00
|
|
line.long 0x00 "PIDR11,Processor ID register 11"
|
|
rgroup.long c14:(832.+12.)++0x00
|
|
line.long 0x00 "PIDR12,Processor ID register 12"
|
|
rgroup.long c14:(832.+13.)++0x00
|
|
line.long 0x00 "PIDR13,Processor ID register 13"
|
|
rgroup.long c14:(832.+14.)++0x00
|
|
line.long 0x00 "PIDR14,Processor ID register 14"
|
|
rgroup.long c14:(832.+15.)++0x00
|
|
line.long 0x00 "PIDR15,Processor ID register 15"
|
|
rgroup.long c14:(832.+16.)++0x00
|
|
line.long 0x00 "PIDR16,Processor ID register 16"
|
|
rgroup.long c14:(832.+17.)++0x00
|
|
line.long 0x00 "PIDR17,Processor ID register 17"
|
|
rgroup.long c14:(832.+18.)++0x00
|
|
line.long 0x00 "PIDR18,Processor ID register 18"
|
|
rgroup.long c14:(832.+19.)++0x00
|
|
line.long 0x00 "PIDR19,Processor ID register 19"
|
|
rgroup.long c14:(832.+20.)++0x00
|
|
line.long 0x00 "PIDR20,Processor ID register 20"
|
|
rgroup.long c14:(832.+21.)++0x00
|
|
line.long 0x00 "PIDR21,Processor ID register 21"
|
|
rgroup.long c14:(832.+22.)++0x00
|
|
line.long 0x00 "PIDR22,Processor ID register 22"
|
|
rgroup.long c14:(832.+23.)++0x00
|
|
line.long 0x00 "PIDR23,Processor ID register 23"
|
|
rgroup.long c14:(832.+24.)++0x00
|
|
line.long 0x00 "PIDR24,Processor ID register 24"
|
|
rgroup.long c14:(832.+25.)++0x00
|
|
line.long 0x00 "PIDR25,Processor ID register 25"
|
|
rgroup.long c14:(832.+26.)++0x00
|
|
line.long 0x00 "PIDR26,Processor ID register 26"
|
|
rgroup.long c14:(832.+27.)++0x00
|
|
line.long 0x00 "PIDR27,Processor ID register 27"
|
|
rgroup.long c14:(832.+28.)++0x00
|
|
line.long 0x00 "PIDR28,Processor ID register 28"
|
|
rgroup.long c14:(832.+29.)++0x00
|
|
line.long 0x00 "PIDR29,Processor ID register 29"
|
|
rgroup.long c14:(832.+30.)++0x00
|
|
line.long 0x00 "PIDR30,Processor ID register 30"
|
|
rgroup.long c14:(832.+31.)++0x00
|
|
line.long 0x00 "PIDR31,Processor ID register 31"
|
|
rgroup.long c14:(832.+32.)++0x00
|
|
line.long 0x00 "PIDR32,Processor ID register 32"
|
|
rgroup.long c14:(832.+33.)++0x00
|
|
line.long 0x00 "PIDR33,Processor ID register 33"
|
|
rgroup.long c14:(832.+34.)++0x00
|
|
line.long 0x00 "PIDR34,Processor ID register 34"
|
|
rgroup.long c14:(832.+35.)++0x00
|
|
line.long 0x00 "PIDR35,Processor ID register 35"
|
|
rgroup.long c14:(832.+36.)++0x00
|
|
line.long 0x00 "PIDR36,Processor ID register 36"
|
|
rgroup.long c14:(832.+37.)++0x00
|
|
line.long 0x00 "PIDR37,Processor ID register 37"
|
|
rgroup.long c14:(832.+38.)++0x00
|
|
line.long 0x00 "PIDR38,Processor ID register 38"
|
|
rgroup.long c14:(832.+39.)++0x00
|
|
line.long 0x00 "PIDR39,Processor ID register 39"
|
|
rgroup.long c14:(832.+40.)++0x00
|
|
line.long 0x00 "PIDR40,Processor ID register 40"
|
|
rgroup.long c14:(832.+41.)++0x00
|
|
line.long 0x00 "PIDR41,Processor ID register 41"
|
|
rgroup.long c14:(832.+42.)++0x00
|
|
line.long 0x00 "PIDR42,Processor ID register 42"
|
|
rgroup.long c14:(832.+43.)++0x00
|
|
line.long 0x00 "PIDR43,Processor ID register 43"
|
|
rgroup.long c14:(832.+44.)++0x00
|
|
line.long 0x00 "PIDR44,Processor ID register 44"
|
|
rgroup.long c14:(832.+45.)++0x00
|
|
line.long 0x00 "PIDR45,Processor ID register 45"
|
|
rgroup.long c14:(832.+46.)++0x00
|
|
line.long 0x00 "PIDR46,Processor ID register 46"
|
|
rgroup.long c14:(832.+47.)++0x00
|
|
line.long 0x00 "PIDR47,Processor ID register 47"
|
|
rgroup.long c14:(832.+48.)++0x00
|
|
line.long 0x00 "PIDR48,Processor ID register 48"
|
|
rgroup.long c14:(832.+49.)++0x00
|
|
line.long 0x00 "PIDR49,Processor ID register 49"
|
|
rgroup.long c14:(832.+50.)++0x00
|
|
line.long 0x00 "PIDR50,Processor ID register 50"
|
|
rgroup.long c14:(832.+51.)++0x00
|
|
line.long 0x00 "PIDR51,Processor ID register 51"
|
|
rgroup.long c14:(832.+52.)++0x00
|
|
line.long 0x00 "PIDR52,Processor ID register 52"
|
|
rgroup.long c14:(832.+53.)++0x00
|
|
line.long 0x00 "PIDR53,Processor ID register 53"
|
|
rgroup.long c14:(832.+54.)++0x00
|
|
line.long 0x00 "PIDR54,Processor ID register 54"
|
|
rgroup.long c14:(832.+55.)++0x00
|
|
line.long 0x00 "PIDR55,Processor ID register 55"
|
|
rgroup.long c14:(832.+56.)++0x00
|
|
line.long 0x00 "PIDR56,Processor ID register 56"
|
|
rgroup.long c14:(832.+57.)++0x00
|
|
line.long 0x00 "PIDR57,Processor ID register 57"
|
|
rgroup.long c14:(832.+58.)++0x00
|
|
line.long 0x00 "PIDR58,Processor ID register 58"
|
|
rgroup.long c14:(832.+59.)++0x00
|
|
line.long 0x00 "PIDR59,Processor ID register 59"
|
|
rgroup.long c14:(832.+60.)++0x00
|
|
line.long 0x00 "PIDR60,Processor ID register 60"
|
|
rgroup.long c14:(832.+61.)++0x00
|
|
line.long 0x00 "PIDR61,Processor ID register 61"
|
|
rgroup.long c14:(832.+62.)++0x00
|
|
line.long 0x00 "PIDR62,Processor ID register 62"
|
|
rgroup.long c14:(832.+63.)++0x00
|
|
line.long 0x00 "PIDR63,Processor ID register 63"
|
|
tree.end
|
|
tree "Coresight Management Registers"
|
|
group.long c14:960.++0x0
|
|
line.long 0x00 "DBGITCTRL,Debug Integration Mode Control Register"
|
|
bitfld.long 0x00 0. " IME ,Integration Mode Enable" "Disabled,Enabled"
|
|
group.long c14:1000.++0x0
|
|
line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7 Set" "Not set,Set"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6 Set" "Not set,Set"
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5 Set" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4 Set" "Not set,Set"
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3 Set" "Not set,Set"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2 Set" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1 Set" "Not set,Set"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0 Set" "Not set,Set"
|
|
group.long c14:1001.++0x0
|
|
line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5 Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2 Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1 Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0 Clear" "Not cleared,Cleared"
|
|
wgroup.long c14:1004.++0x00
|
|
line.long 0x00 "DBGLAR,Lock Access Register"
|
|
rgroup.long c14:1005.++0x00
|
|
line.long 0x00 "DBGLSR,Lock Status Register"
|
|
bitfld.long 0x00 2. " NTT ,Not 32-bit access" "32-bit,Not 32-bit"
|
|
bitfld.long 0x00 1. " SLK ,Software Lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " SLI ,Software Lock Implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
rgroup.long c14:1006.++0x0
|
|
line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug features implementation" "No effect,Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enable (DBGEN OR NIDEN) AND (SPIDEN OR SPNIDEN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implementation" "No effect,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enable (DBGEN AND SPIDEN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enable (DBGEN OR NIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enable (DBGEN)" "Disabled,Enabled"
|
|
textline " "
|
|
if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
rgroup.long c14:1009.++0x0
|
|
line.long 0x0 "DBGDEVID1,Debug Device ID Register 1"
|
|
bitfld.long 0x00 0.--3. " PCSROFFSET ,Defines the offset applied to DBGPCSR samples" "Depends on instr set state,No offset,?..."
|
|
elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
rgroup.long c14:1009.++0x0
|
|
line.long 0x0 "DBGDEVID1,Debug Device ID Register 1"
|
|
bitfld.long 0x00 0.--3. " PCSROFFSET ,Defines the offset applied to DBGPCSR samples" "Reserved,No offset,?..."
|
|
endif
|
|
textline " "
|
|
rgroup.long c14:1010.++0x0
|
|
line.long 0x0 "DBGDEVID0,Debug Device ID Register 0"
|
|
bitfld.long 0x0 24.--27. " AR ,Debug External Auxiliary Control Register support status" "Reserved,Supported,?..."
|
|
bitfld.long 0x0 20.--23. " DL ,Support for Debug OS Double Lock Register" "Reserved,Supported,?..."
|
|
bitfld.long 0x0 16.--19. " VE ,Specifies implementation of Virtualization Extension" "Reserved,Implemented,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12.--15. " VC ,Form of the vector catch event implemented" "Implemented,?..."
|
|
bitfld.long 0x0 8.--11. " BPAM ,Level of support for Immediate Virtual Address matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
|
|
bitfld.long 0x0 4.--7. " WPAM ,Level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..."
|
|
textline " "
|
|
bitfld.long 0x0 0.--3. " PCS ,Level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..."
|
|
textline " "
|
|
rgroup.long c14:1011.++0x00
|
|
line.long 0x00 "DBGDEVTYPE,Debug Device Type Register"
|
|
bitfld.long 0x00 4.--7. " T ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " C ,Main class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long c14:1016.++0x00
|
|
line.long 0x00 "DBGPID0,Debug Peripheral ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number [7:0]"
|
|
rgroup.long c14:1017.++0x00
|
|
line.long 0x00 "DBGPID1,Debug Peripheral ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " JEPID[3:0] ,JEP Identity Code[3:0]"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PN[11:8] ,Part Number [11:8]"
|
|
rgroup.long c14:1018.++0x00
|
|
line.long 0x00 "DBGPID2,Debug Peripheral ID 2"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REV ,Revision"
|
|
bitfld.long 0x00 3. " UJEPCODE ,Uses JEP Code" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--2. 1. " JEPID[6:4] ,JEP Identity Code[6:4]"
|
|
rgroup.long c14:1019.++0x00
|
|
line.long 0x00 "DBGPID3,Debug Peripheral ID 3"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REVAND ,Manufacturing revision"
|
|
hexmask.long.byte 0x00 0.--3. 1. " CM ,Customer modified"
|
|
rgroup.long c14:1012.++0x00
|
|
line.long 0x00 "DBGPID4,Debug Peripheral ID 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CONT_CODE ,JEP 106 Continuation code"
|
|
rgroup.long c14:1020.++0x00
|
|
line.long 0x00 "DBGCID0,Debug Component ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 0"
|
|
rgroup.long c14:1021.++0x00
|
|
line.long 0x00 "DBGCID1,Debug Component ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " CC ,Component class"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble byte 1"
|
|
rgroup.long c14:1022.++0x00
|
|
line.long 0x00 "DBGCID2,Debug Component ID 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 2"
|
|
rgroup.long c14:1023.++0x00
|
|
line.long 0x00 "DBGCID3,Debug Component ID 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 3"
|
|
tree.end
|
|
tree.end
|
|
width 10.
|
|
tree "Breakpoint Registers"
|
|
if ((d.l(c14:80.+0.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+0.)++0x0
|
|
line.long 0x00 "DBGBVR0,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+0.)++0x0
|
|
line.long 0x00 "DBGBVR0,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+0.)++0x0
|
|
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+1.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+1.)++0x0
|
|
line.long 0x00 "DBGBVR1,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+1.)++0x0
|
|
line.long 0x00 "DBGBVR1,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+1.)++0x0
|
|
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+2.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+2.)++0x0
|
|
line.long 0x00 "DBGBVR2,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+2.)++0x0
|
|
line.long 0x00 "DBGBVR2,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+2.)++0x0
|
|
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+3.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+3.)++0x0
|
|
line.long 0x00 "DBGBVR3,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+3.)++0x0
|
|
line.long 0x00 "DBGBVR3,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+3.)++0x0
|
|
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+4.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+4.)++0x0
|
|
line.long 0x00 "DBGBVR4,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+4.)++0x0
|
|
line.long 0x00 "DBGBVR4,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+4.)++0x0
|
|
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
if ((d.l(c14:80.+5.)&0x500000)==(0x500000||0x400000||0x100000||0x0))
|
|
group.long c14:(64.+5.)++0x0
|
|
line.long 0x00 "DBGBVR5,Breakpoint Value Register(Address comparison)"
|
|
hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31"
|
|
else
|
|
group.long c14:(64.+5.)++0x0
|
|
line.long 0x00 "DBGBVR5,Breakpoint Value Register(Context matching)"
|
|
endif
|
|
group.long c14:(80.+5.)++0x0
|
|
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
|
|
bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..."
|
|
bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode"
|
|
bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled"
|
|
group.long c14:148.++0x0
|
|
line.long 0x00 "DBGBXVR0,Debug Breakpoint Extended Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VMID , VMID value"
|
|
group.long c14:149.++0x0
|
|
line.long 0x00 "DBGBXVR1,Debug Breakpoint Extended Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VMID , VMID value"
|
|
tree.end
|
|
width 10.
|
|
tree "Watchpoint Control Registers"
|
|
group.long c14:(96.+0.)++0x00
|
|
line.long 0x00 "DBGWVR0,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DA ,Data address"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c14:(112.+0.)++0x00
|
|
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any"
|
|
bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:(112.+0.)++0x00
|
|
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
group.long c14:(96.+1.)++0x00
|
|
line.long 0x00 "DBGWVR1,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DA ,Data address"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c14:(112.+1.)++0x00
|
|
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any"
|
|
bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:(112.+1.)++0x00
|
|
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
group.long c14:(96.+2.)++0x00
|
|
line.long 0x00 "DBGWVR2,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DA ,Data address"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c14:(112.+2.)++0x00
|
|
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any"
|
|
bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:(112.+2.)++0x00
|
|
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
group.long c14:(96.+3.)++0x00
|
|
line.long 0x00 "DBGWVR3,Watchpoint Value Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DA ,Data address"
|
|
if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE")
|
|
group.long c14:(112.+3.)++0x00
|
|
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure"
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1"
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any"
|
|
bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled"
|
|
elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE")
|
|
group.long c14:(112.+3.)++0x00
|
|
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
|
|
bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled"
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..."
|
|
bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
width 0xb
|
|
tree "vGIC 2.0 (Virtual Generic Interrupt Controller)"
|
|
base ad:0x50040000
|
|
width 11.
|
|
tree "CPU Interface registers"
|
|
if (((d.l(ad:0x50040000+0x04))&0x400)==0x400)
|
|
group.long 0x00++0x03 "Interrupt Controller Physical CPU Interface"
|
|
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
|
|
bitfld.long 0x00 9. " EOIMODENS ,Behaviour of non-secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate interrupt,Priority drop only"
|
|
bitfld.long 0x00 6. " IRQBYPDISGRP1 ,Determine if bypass IRQ signal is signalled to the processor" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FIQBYPDISGRP1 ,Determine if bypass FIQ signal is signalled to the processor" "Yes,No"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable for signalling interrupts" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03 "Interrupt Controller Physical CPU Interface"
|
|
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
|
|
bitfld.long 0x00 10. " EOIMODENS ,Behaviour of secure accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate interrupt,Priority drop only"
|
|
bitfld.long 0x00 9. " EOIMODES ,Behaviour of accesses to the GICC_EOIR and GICC_DIR registers" "Priority drop/Deactivate interrupt,Priority drop only"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IRQBYPDISGRP1 ,Determine if bypass IRQ signal is signalled to the processor" "Yes,No"
|
|
bitfld.long 0x00 7. " FIQBYPDISGRP0 ,Determine if bypass FIQ signal is signalled to the processor" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Determine if bypass IRQ signal is signalled to the processor" "Yes,No"
|
|
bitfld.long 0x00 5. " FIQBYPDISGRP1 ,Determine if bypass FIQ signal is signalled to the processor" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CBPR ,Group interrupts control" "BPR and ABPR,BPR"
|
|
bitfld.long 0x00 3. " FIQEN ,Group 0 interrupts signal control" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ACKCTL ,IAR and HPPIR control" "0,1"
|
|
bitfld.long 0x00 1. " ENABLEGRP1 ,Enable for signalling interrupts of group 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLEGRP0 ,Enable for signalling interrupts of group 0" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface"
|
|
if (((d.l(ad:0x50040000))&0x400)==0x400)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GICC_BPR,Binary Point Register"
|
|
bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register"
|
|
in
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "GICC_EOIR,End Of Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,ACKINTID value from the corresponding ICCIAR access"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "GICC_RPR,Running Priority Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "GICC_HPPIR,Highest Pending Interrupt Register"
|
|
in
|
|
if (((d.l(ad:0x50040000))&0x400)==0x400)
|
|
group.long 0x01C++0x03
|
|
line.long 0x00 "GICC_ABPR,Aliased Binary Point Register"
|
|
bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "GICC_AIAR,Aliased interrupt acknowledge Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " INTERRUPTID ,Interrupt ID"
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "GICC_AEOIR,Aliased end of Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " INTERRUPTID ,Interrupt ID value from the corresponding GICC_AIAR access"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "GICC_AHPIR,Aliased Highest Priority Pending Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,Interrupt ID of the highest priority pending interrupt"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "GICC_APR0,Active priority register"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "GICC_NSAPR0,Non-secure active priority register"
|
|
rgroup.long 0x0FC++0x03 "CPU Interface Identification"
|
|
line.long 0x00 "GICC_IIDR,CPU Interface Identification Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " PRODUCTID ,An IMPLEMENTATION DEFINED product identifier"
|
|
bitfld.long 0x00 16.--19. " ARCHIT_VER ,GIC architecture version" ",GICv1,GICv2,,,,,,,,,,,,,"
|
|
hexmask.long.byte 0x00 12.--15. 1. " REV ,An IMPLEMENTATION DEFINED revision number for the CPU interface"
|
|
hexmask.long.word 0x00 0.--11. 1. " IMPLEMENTER ,Contains the JEP106 code of the company"
|
|
tree.end
|
|
tree "Distributor registers"
|
|
if (((d.l(ad:0x50040000))&0x400)==0x400)
|
|
group.long 0x1000++0x03 "Distributor Interrupt Controller"
|
|
line.long 0x00 "GICD_CTLR,Interrupt Distributor Control Register"
|
|
bitfld.long 0x00 4. " CBPR ,Controls which Binary Pointer Register Group 0/Group 1" "ICCBPR for Group 0/ICCABPR for Group 1,ICCBPR for Both"
|
|
bitfld.long 0x00 3. " FIQEN ,Indicates using of FIQ or IRQ signal for interrupts" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ACKCTL ,Interrupt acknowledge control" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 1. " ENABLEGRP1 ,Enable for signalling interrupts of Group 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLEGRP0 ,Enable for signalling interrupts of Group 0" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1000++0x03 "Distributor Interrupt Controller"
|
|
line.long 0x00 "GICD_CTLR,Interrupt Distributor Control Register"
|
|
bitfld.long 0x00 0. " ENABLE ,Global enable for pending interrupts from the Distributor to the CPU" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x1004++0x03
|
|
line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 11.--15. " LSPI ,Number of supported Lockable Shared Peripheral Interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10. " SECURITYEXTN ,Indicate whether interrupt controller implements the security extensions" "Not implemented,Implemented"
|
|
bitfld.long 0x00 5.--7. " CPUNO ,Number of supported CPU interfaces" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " ITLINENO ,Number of provided INTIDs" "32,64,96,128,160,192,224,256,288,320,352,384,416,448,480,512,544,576,608,640,672,704,736,768,800,832,864,896,928,960,992,1024"
|
|
rgroup.long 0x1008++0x03
|
|
line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PRODUCTID ,An IMPEMENTATION DEFINED product identifier"
|
|
hexmask.long.byte 0x00 16.--19. 1. " VARIANT ,An IMPEMENTATION DEFINED variant number"
|
|
hexmask.long.byte 0x00 12.--15. 1. " REVISION ,An IMPEMENTATION DEFINED revision number"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " IMPLEMENTER ,JEP106 code of the company that implemented GIC Distributor"
|
|
width 16.
|
|
tree "Interrupt Security"
|
|
if (((d.l(ad:0x50040000))&0x400)==0x400)
|
|
group.long 0x1080++0x03
|
|
line.long 0x00 "GICD_IGROUPR0,Interrupt group register (SGI,PPI)"
|
|
bitfld.long 0x00 31. " PPI_SS_15 ,Group status for PPI ID 31 SDMMC4" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " PPI_SS_14 ,Group status for PPI ID 30 OWR" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " PPI_SS_13 ,Group status for PPI ID 29 ARB_SEM_GNT_CPU" "Group 0,Group 1"
|
|
bitfld.long 0x00 28. " PPI_SS_12 ,Group status for PPI ID 28 ARB_SEM_GNT_COP" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " PPI_SS_11 ,Group status for PPI ID 27 AHB_DMA_CPU" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPI_SS_10 ,Group status for PPI ID 26 APB_DMA_CPU" "Group 0,Group 1"
|
|
bitfld.long 0x00 25. " PPI_SS_9 ,Group status for PPI ID 25 VCP" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " PPI_SS_7 ,Group status for PPI ID 23 SATA_CTL" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " PPI_SS_5 ,Group status for PPI ID 21 USB2" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " PPI_SS_4 ,Group status for PPI ID 20 USB" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PPI_SS_3 ,Group status for PPI ID 19 SDMMC3" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " PPI_SS_2 ,Group status for PPI ID 18 AVP_UCQ" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " PPI_SS_1 ,Group status for PPI ID 17 VDE" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SGI_SS_15 ,Group status for SGI ID 15 SDMMC2" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " SGI_SS_14 ,Group status for SGI ID 14 SDMMC1" "Group 0,Group 1"
|
|
bitfld.long 0x00 13. " SGI_SS_13 ,Group status for SGI ID 13 SATA_RX_STAT" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " SGI_SS_12 ,Group status for SGI ID 12 VDE_SXE" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " SGI_SS_11 ,Group status for SGI ID 11 VDE_BSEA" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SGI_SS_10 ,Group status for SGI ID 10 VDE_BSEV" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " SGI_SS_9 ,Group status for SGI ID 9 VDE_SYNC_TOKEN" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " SGI_SS_8 ,Group status for SGI ID 8 VDE_UCQ" "Group 0,Group 1"
|
|
bitfld.long 0x00 7. " SGI_SS_7 ,Group status for SGI ID 7 SHR_SEM_UTBOX_EMPTY" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " SGI_SS_6 ,Group status for SGI ID 6 SHR_SEM_UTBOX_FULL" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SGI_SS_5 ,Group status for SGI ID 5 SHR_SEM_INBOX_EMPTY" "Group 0,Group 1"
|
|
bitfld.long 0x00 4. " SGI_SS_4 ,Group status for SGI ID 4 SHR_SEM_INBOX_FULL" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " SGI_SS_3 ,Group status for SGI ID 3 CEC" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " SGI_SS_2 ,Group status for SGI ID 2 RTC" "Group 0,Group 1"
|
|
bitfld.long 0x00 1. " SGI_SS_1 ,Group status for SGI ID 1 TMR2" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SGI_SS_0 ,Group status for SGI ID 0 TMR1" "Group 0,Group 1"
|
|
endif
|
|
group.long 0x1084++0xF
|
|
line.long 0x00 "GICD_IGROUPR1,Interrupt security registers (SPI[31:0])"
|
|
bitfld.long 0x00 31. " SPI_SS_31 ,Group status SPI 31 ID 63 I2C6" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " SPI_SS_30 ,Group status SPI 30 ID 62 CLDVFS" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " SPI_SS_29 ,Group status SPI 29 ID 61 AHB_DMA_COP" "Group 0,Group 1"
|
|
bitfld.long 0x00 28. " SPI_SS_28 ,Group status SPI 28 ID 60 APB_DMA_COP" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " SPI_SS_27 ,Group status SPI 27 ID 59 SPI1" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SPI_SS_26 ,Group status SPI 26 ID 58 SE" "Group 0,Group 1"
|
|
bitfld.long 0x00 25. " SPI_SS_25 ,Group status SPI 25 ID 57 USB3_DEV_PME" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " SPI_SS_24 ,Group status SPI 24 ID 56 USB3_DEV_SMI" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " SPI_SS_23 ,Group status SPI 23 ID 55 GPIO5" "Group 0,Group 1"
|
|
bitfld.long 0x00 22. " SPI_SS_22 ,Group status SPI 22 ID 54 STAT_MON" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SPI_SS_21 ,Group status SPI 21 ID 53 I2C5" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " SPI_SS_10 ,Group status SPI 20 ID 52 VFIR" "Group 0,Group 1"
|
|
bitfld.long 0x00 19. " SPI_SS_19 ,Group status SPI 19 ID 51 EDP" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " SPI_SS_18 ,Group status SPI 18 ID 50 TSEC" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " SPI_SS_17 ,Group status SPI 17 ID 49 XUSB_PADCTL" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPI_SS_16 ,Group status SPI 16 ID 48 THERMAL" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " SPI_SS_15 ,Group status SPI 15 ID 47 HSI" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " SPI_SS_14 ,Group status SPI 14 ID 46 UARTC" "Group 0,Group 1"
|
|
bitfld.long 0x00 13. " SPI_SS_13 ,Group status SPI 13 ID 45 ACTMON" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " SPI_SS_12 ,Group status SPI 12 ID 44 USB3_DEV_HOST" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPI_SS_11 ,Group status SPI 11 ID 43 USB3_HOST_PME" "Group 0,Group 1"
|
|
bitfld.long 0x00 10. " SPI_SS_10 ,Group status SPI 10 ID 42 TMR4" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " SPI_SS_9 ,Group status SPI 9 ID 41 TMR3" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " SPI_SS_8 ,Group status SPI 8 ID 40 USB3_HOST_SMI" "Group 0,Group 1"
|
|
bitfld.long 0x00 7. " SPI_SS_7 ,Group status SPI 7 ID 39 USB3_HOST_INT" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPI_SS_6 ,Group status SPI 6 ID 38 I2C" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " SPI_SS_5 ,Group status SPI 5 ID 37 UARTB" "Group 0,Group 1"
|
|
bitfld.long 0x00 4. " SPI_SS_4 ,Group status SPI 4 ID 36 UARTA" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " SPI_SS_3 ,Group status SPI 3 ID 35 GPIO4" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " SPI_SS_2 ,Group status SPI 2 ID 34 GPIO3" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPI_SS_1 ,Group status SPI 1 ID 33 GPIO2" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " SPI_SS_0 ,Group status SPI 0 ID 32 GPIO1" "Group 0,Group 1"
|
|
line.long 0x04 "GICD_IGROUPR2,Interrupt security registers SPI[63:32]"
|
|
bitfld.long 0x04 31. " SPI_SS_63 ,Group status SPI 63 ID 95 SW_INTR" "Group 0,Group 1"
|
|
bitfld.long 0x04 28. " SPI_SS_60 ,Group status SPI 60 ID 92 I2C3" "Group 0,Group 1"
|
|
bitfld.long 0x04 26. " SPI_SS_58 ,Group status SPI 58 ID 90 UARTD" "Group 0,Group 1"
|
|
bitfld.long 0x04 25. " SPI_SS_57 ,Group status SPI 57 ID 89 GPIO7" "Group 0,Group 1"
|
|
bitfld.long 0x04 23. " SPI_SS_55 ,Group status SPI 55 ID 87 GPIO6" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SPI_SS_54 ,Group status SPI 54 ID 86 PMU_EXT" "Group 0,Group 1"
|
|
bitfld.long 0x04 20. " SPI_SS_52 ,Group status SPI 52 ID 84 I2C2" "Group 0,Group 1"
|
|
bitfld.long 0x04 19. " SPI_SS_51 ,Group status SPI 51 ID 83 SPI3" "Group 0,Group 1"
|
|
bitfld.long 0x04 18. " SPI_SS_50 ,Group status SPI 50 ID 82 SPI2" "Group 0,Group 1"
|
|
bitfld.long 0x04 17. " SPI_SS_49 ,Group status SPI 49 ID 81 HDA" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SPI_SS_47 ,Group status SPI 47 ID 79 SPI6" "Group 0,Group 1"
|
|
bitfld.long 0x04 14. " SPI_SS_46 ,Group status SPI 46 ID 78 EMC" "Group 0,Group 1"
|
|
bitfld.long 0x04 13. " SPI_SS_45 ,Group status SPI 45 ID 77 MC" "Group 0,Group 1"
|
|
bitfld.long 0x04 12. " SPI_SS_44 ,Group status SPI 44 ID 76 SOR" "Group 0,Group 1"
|
|
bitfld.long 0x04 11. " SPI_SS_43 ,Group status SPI 43 ID 75 HDMI" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x04 10. " SPI_SS_42 ,Group status SPI 42 ID 74 DISPLAYB" "Group 0,Group 1"
|
|
bitfld.long 0x04 9. " SPI_SS_41 ,Group status SPI 41 ID 73 DISPLAY" "Group 0,Group 1"
|
|
bitfld.long 0x04 8. " SPI_SS_40 ,Group status SPI 40 ID 72 VIC" "Group 0,Group 1"
|
|
bitfld.long 0x04 7. " SPI_SS_39 ,Group status SPI 39 ID 71 ISP" "Group 0,Group 1"
|
|
bitfld.long 0x04 6. " SPI_SS_38 ,Group status SPI 38 ID 70 ISPB" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SPI_SS_37 ,Group status SPI 37 ID 69 VI" "Group 0,Group 1"
|
|
bitfld.long 0x04 4. " SPI_SS_36 ,Group status SPI 36 ID 68 MSENC" "Group 0,Group 1"
|
|
bitfld.long 0x04 3. " SPI_SS_35 ,Group status SPI 35 ID 67 HOST1X_GEN_CPU" "Group 0,Group 1"
|
|
bitfld.long 0x04 2. " SPI_SS_34 ,Group status SPI 34 ID 66 HOST1X_GEN_COP" "Group 0,Group 1"
|
|
bitfld.long 0x04 1. " SPI_SS_33 ,Group status SPI 33 ID 65 HOST1X_SYNCPT_ CPU" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SPI_SS_32 ,Group status SPI 32 ID 64 HOST1X_SYNCPT_ COP" "Group 0,Group 1"
|
|
line.long 0x08 "GICD_IGROUPR3,Interrupt security registers SPI[95:64]"
|
|
bitfld.long 0x08 31. " SPI_SS_95 ,Group status SPI 95 ID 127 HIER_GROUP1_ CPU" "Group 0,Group 1"
|
|
bitfld.long 0x08 30. " SPI_SS_94 ,Group status SPI 94 ID 126 CAR" "Group 0,Group 1"
|
|
bitfld.long 0x08 29. " SPI_SS_93 ,Group status SPI 93 ID 125 GPIO8" "Group 0,Group 1"
|
|
bitfld.long 0x08 28. " SPI_SS_92 ,Group status SPI 92 ID 124 WDT_AVP" "Group 0,Group 1"
|
|
bitfld.long 0x08 27. " SPI_SS_91 ,Group status SPI 91 ID 123 WDT_CPU" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x08 26. " SPI_SS_90 ,Group status SPI 90 ID 122 HIER_GROUP1_ COP" "Group 0,Group 1"
|
|
bitfld.long 0x08 25. " SPI_SS_89 ,Group status SPI 89 ID 121 TMR5" "Group 0,Group 1"
|
|
bitfld.long 0x08 24. " SPI_SS_88 ,Group status SPI 88 ID 120 I2C4" "Group 0,Group 1"
|
|
bitfld.long 0x08 23. " SPI_SS_87 ,Group status SPI 87 ID 119 APB_DMA_CH15" "Group 0,Group 1"
|
|
bitfld.long 0x08 22. " SPI_SS_86 ,Group status SPI 86 ID 118 APB_DMA_CH14" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SPI_SS_85 ,Group status SPI 85 ID 117 APB_DMA_CH13" "Group 0,Group 1"
|
|
bitfld.long 0x08 20. " SPI_SS_84 ,Group status SPI 84 ID 116 APB_DMA_CH12" "Group 0,Group 1"
|
|
bitfld.long 0x08 19. " SPI_SS_83 ,Group status SPI 83 ID 115 APB_DMA_CH11" "Group 0,Group 1"
|
|
bitfld.long 0x08 18. " SPI_SS_82 ,Group status SPI 82 ID 114 APB_DMA_CH10" "Group 0,Group 1"
|
|
bitfld.long 0x08 17. " SPI_SS_81 ,Group status SPI 81 ID 113 APB_DMA_CH9" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x08 16. " SPI_SS_80 ,Group status SPI 80 ID 112 APB_DMA_CH8" "Group 0,Group 1"
|
|
bitfld.long 0x08 15. " SPI_SS_79 ,Group status SPI 79 ID 111 APB_DMA_CH7" "Group 0,Group 1"
|
|
bitfld.long 0x08 14. " SPI_SS_78 ,Group status SPI 78 ID 110 APB_DMA_CH6" "Group 0,Group 1"
|
|
bitfld.long 0x08 13. " SPI_SS_77 ,Group status SPI 77 ID 109 APB_DMA_CH5" "Group 0,Group 1"
|
|
bitfld.long 0x08 12. " SPI_SS_76 ,Group status SPI 76 ID 108 APB_DMA_CH4" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SPI_SS_75 ,Group status SPI 75 ID 107 APB_DMA_CH3" "Group 0,Group 1"
|
|
bitfld.long 0x08 10. " SPI_SS_74 ,Group status SPI 74 ID 106 APB_DMA_CH2" "Group 0,Group 1"
|
|
bitfld.long 0x08 9. " SPI_SS_73 ,Group status SPI 73 ID 105 APB_DMA_CH1" "Group 0,Group 1"
|
|
bitfld.long 0x08 8. " SPI_SS_72 ,Group status SPI 72 ID 104 APB_DMA_CH0" "Group 0,Group 1"
|
|
bitfld.long 0x08 7. " SPI_SS_71 ,Group status SPI 71 ID 103 AUDIO_CLUSTER" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SPI_SS_69 ,Group status SPI 69 ID 101 AVP_CACHE" "Group 0,Group 1"
|
|
bitfld.long 0x08 4. " SPI_SS_68 ,Group status SPI 68 ID 100 PCIE_WAKE" "Group 0,Group 1"
|
|
bitfld.long 0x08 3. " SPI_SS_67 ,Group status SPI 67 ID 99 HOST1X_GEN_CPU" "Group 0,Group 1"
|
|
bitfld.long 0x08 2. " SPI_SS_66 ,Group status SPI 66 ID 98 HOST1X_GEN_COP" "Group 0,Group 1"
|
|
bitfld.long 0x08 1. " SPI_SS_65 ,Group status SPI 65 ID 97 HOST1X_SYNCPT_CPU" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SPI_SS_64 ,Group status SPI 64 ID 96 HOST1X_SYNCPT_COP" "Group 0,Group 1"
|
|
line.long 0x0C "GICD_IGROUPR4,Interrupt security registers SPI[127:96]"
|
|
bitfld.long 0x0C 31. " SPI_SS_127 ,Group status SPI 127 ID 159 ARDPAUX" "Group 0,Group 1"
|
|
bitfld.long 0x0C 30. " SPI_SS_126 ,Group status SPI 126 ID 158 GPU_NONSTALL" "Group 0,Group 1"
|
|
bitfld.long 0x0C 29. " SPI_SS_123 ,Group status SPI 125 ID 157 GPU_STALL" "Group 0,Group 1"
|
|
bitfld.long 0x0C 28. " SPI_SS_122 ,Group status SPI 124 ID 156 TMR0" "Group 0,Group 1"
|
|
bitfld.long 0x0C 27. " SPI_SS_121 ,Group status SPI 123 ID 155 TMR9" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x0C 26. " SPI_SS_120 ,Group status SPI 122 ID 154 TMR8" "Group 0,Group 1"
|
|
bitfld.long 0x0C 25. " SPI_SS_119 ,Group status SPI 121 ID 153 TMR7" "Group 0,Group 1"
|
|
bitfld.long 0x0C 24. " SPI_SS_118 ,Group status SPI 120 ID 152 TMR6" "Group 0,Group 1"
|
|
bitfld.long 0x0C 23. " SPI_SS_117 ,Group status SPI 119 ID 151 SDMMC4_SYS" "Group 0,Group 1"
|
|
bitfld.long 0x0C 22. " SPI_SS_116 ,Group status SPI 118 ID 150 SDMMC3_SYS" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " SPI_SS_115 ,Group status SPI 117 ID 149 SDMMC2_SYS" "Group 0,Group 1"
|
|
bitfld.long 0x0C 20. " SPI_SS_114 ,Group status SPI 116 ID 148 SDMMC1_SYS" "Group 0,Group 1"
|
|
bitfld.long 0x0C 19. " SPI_SS_113 ,Group status SPI 115 ID 147 CPU3_PMU_INTR" "Group 0,Group 1"
|
|
bitfld.long 0x0C 18. " SPI_SS_112 ,Group status SPI 114 ID 146 CPU2_PMU_INTR" "Group 0,Group 1"
|
|
bitfld.long 0x0C 17. " SPI_SS_111 ,Group status SPI 113 ID 145 CPU1_PMU_INTR" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " SPI_SS_110 ,Group status SPI 112 ID 144 CPU0_PMU_INTR" "Group 0,Group 1"
|
|
bitfld.long 0x0C 15. " SPI_SS_111 ,Group status SPI 111 ID 143 APB_DMA_CH31" "Group 0,Group 1"
|
|
bitfld.long 0x0C 14. " SPI_SS_110 ,Group status SPI 110 ID 142 APB_DMA_CH30" "Group 0,Group 1"
|
|
bitfld.long 0x0C 13. " SPI_SS_109 ,Group status SPI 109 ID 141 APB_DMA_CH29" "Group 0,Group 1"
|
|
bitfld.long 0x0C 12. " SPI_SS_108 ,Group status SPI 108 ID 140 APB_DMA_CH28" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " SPI_SS_107 ,Group status SPI 107 ID 139 APB_DMA_CH27" "Group 0,Group 1"
|
|
bitfld.long 0x0C 10. " SPI_SS_106 ,Group status SPI 106 ID 138 APB_DMA_CH26" "Group 0,Group 1"
|
|
bitfld.long 0x0C 9. " SPI_SS_105 ,Group status SPI 105 ID 137 APB_DMA_CH25" "Group 0,Group 1"
|
|
bitfld.long 0x0C 8. " SPI_SS_104 ,Group status SPI 104 ID 136 APB_DMA_CH24" "Group 0,Group 1"
|
|
bitfld.long 0x0C 7. " SPI_SS_103 ,Group status SPI 103 ID 135 APB_DMA_CH23" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " SPI_SS_102 ,Group status SPI 102 ID 134 APB_DMA_CH22" "Group 0,Group 1"
|
|
bitfld.long 0x0C 5. " SPI_SS_101 ,Group status SPI 101 ID 133 APB_DMA_CH21" "Group 0,Group 1"
|
|
bitfld.long 0x0C 4. " SPI_SS_100 ,Group status SPI 100 ID 132 APB_DMA_CH20" "Group 0,Group 1"
|
|
bitfld.long 0x0C 3. " SPI_SS_99 ,Group status SPI 99 ID 131 APB_DMA_CH19" "Group 0,Group 1"
|
|
bitfld.long 0x0C 2. " SPI_SS_98 ,Group status SPI 98 ID 130 APB_DMA_CH18" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SPI_SS_97 ,Group status SPI 97 ID 129 APB_DMA_CH17" "Group 0,Group 1"
|
|
bitfld.long 0x0C 0. " SPI_SS_96 ,Group status SPI 96 ID 128 APB_DMA_CH16" "Group 0,Group 1"
|
|
tree.end
|
|
tree "Interrupt Set-Enable"
|
|
group.long 0x1100++0x03
|
|
line.long 0x00 "GICD_IGROUPR0,Interrupt group register (SGI,PPI)"
|
|
bitfld.long 0x00 31. " PPI_SE_15 ,Set-enable for PPI ID 31 SDMMC4" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PPI_SE_14 ,Set-enable for PPI ID 30 OWR" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PPI_SE_13 ,Set-enable for PPI ID 29 ARB_SEM_GNT_CPU" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PPI_SE_12 ,Set-enable for PPI ID 28 ARB_SEM_GNT_COP" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PPI_SE_11 ,Set-enable for PPI ID 27 AHB_DMA_CPU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPI_SE_10 ,Set-enable for PPI ID 26 APB_DMA_CPU" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PPI_SE_9 ,Set-enable for PPI ID 25 VCP" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PPI_SE_7 ,Set-enable for PPI ID 23 SATA_CTL" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " PPI_SE_5 ,Set-enable for PPI ID 21 USB2" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PPI_SE_4 ,Set-enable for PPI ID 20 USB" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PPI_SE_3 ,Set-enable for PPI ID 19 SDMMC3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PPI_SE_2 ,Set-enable for PPI ID 18 AVP_UCQ" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PPI_SE_1 ,Set-enable for PPI ID 17 VDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SGI_SE_15 ,Set-enable for SGI ID 15 SDMMC2" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SGI_SE_14 ,Set-enable for SGI ID 14 SDMMC1" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SGI_SE_13 ,Set-enable for SGI ID 13 SATA_RX_STAT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SGI_SE_12 ,Set-enable for SGI ID 12 VDE_SXE" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SGI_SE_11 ,Set-enable for SGI ID 11 VDE_BSEA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SGI_SE_10 ,Set-enable for SGI ID 10 VDE_BSEV" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SGI_SE_9 ,Set-enable for SGI ID 9 VDE_SYNC_TOKEN" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SGI_SE_8 ,Set-enable for SGI ID 8 VDE_UCQ" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SGI_SE_7 ,Set-enable for SGI ID 7 SHR_SEM_UTBOX_EMPTY" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SGI_SE_6 ,Set-enable for SGI ID 6 SHR_SEM_UTBOX_FULL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SGI_SE_5 ,Set-enable for SGI ID 5 SHR_SEM_INBOX_EMPTY" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SGI_SE_4 ,Set-enable for SGI ID 4 SHR_SEM_INBOX_FULL" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SGI_SE_3 ,Set-enable for SGI ID 3 CEC" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SGI_SE_2 ,Set-enable for SGI ID 2 RTC" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SGI_SE_1 ,Set-enable for SGI ID 1 TMR2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SGI_SE_0 ,Set-enable for SGI ID 0 TMR1" "Disabled,Enabled"
|
|
group.long 0x1104++0xF
|
|
line.long 0x00 "GICD_IGROUPR1,Interrupt Set-enable (SPI[31:0])"
|
|
bitfld.long 0x00 31. " SPI_SE_31 ,Set-enable SPI 31 ID 63 I2C6" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SPI_SE_30 ,Set-enable SPI 30 ID 62 CLDVFS" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SPI_SE_29 ,Set-enable SPI 29 ID 61 AHB_DMA_COP" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SPI_SE_28 ,Set-enable SPI 28 ID 60 APB_DMA_COP" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SPI_SE_27 ,Set-enable SPI 27 ID 59 SPI1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SPI_SE_26 ,Set-enable SPI 26 ID 58 SE" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " SPI_SE_25 ,Set-enable SPI 25 ID 57 USB3_DEV_PME" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SPI_SE_24 ,Set-enable SPI 24 ID 56 USB3_DEV_SMI" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SPI_SE_23 ,Set-enable SPI 23 ID 55 GPIO5" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " SPI_SE_22 ,Set-enable SPI 22 ID 54 STAT_MON" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SPI_SE_21 ,Set-enable SPI 21 ID 53 I2C5" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SPI_SE_10 ,Set-enable SPI 20 ID 52 VFIR" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SPI_SE_19 ,Set-enable SPI 19 ID 51 EDP" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SPI_SE_18 ,Set-enable SPI 18 ID 50 TSEC" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SPI_SE_17 ,Set-enable SPI 17 ID 49 XUSB_PADCTL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPI_SE_16 ,Set-enable SPI 16 ID 48 THERMAL" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SPI_SE_15 ,Set-enable SPI 15 ID 47 HSI" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SPI_SE_14 ,Set-enable SPI 14 ID 46 UARTC" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SPI_SE_13 ,Set-enable SPI 13 ID 45 ACTMON" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SPI_SE_12 ,Set-enable SPI 12 ID 44 USB3_DEV_HOST" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPI_SE_11 ,Set-enable SPI 11 ID 43 USB3_HOST_PME" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SPI_SE_10 ,Set-enable SPI 10 ID 42 TMR4" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SPI_SE_9 ,Set-enable SPI 9 ID 41 TMR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SPI_SE_8 ,Set-enable SPI 8 ID 40 USB3_HOST_SMI" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SPI_SE_7 ,Set-enable SPI 7 ID 39 USB3_HOST_INT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPI_SE_6 ,Set-enable SPI 6 ID 38 I2C" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SPI_SE_5 ,Set-enable SPI 5 ID 37 UARTB" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SPI_SE_4 ,Set-enable SPI 4 ID 36 UARTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SPI_SE_3 ,Set-enable SPI 3 ID 35 GPIO4" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SPI_SE_2 ,Set-enable SPI 2 ID 34 GPIO3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPI_SE_1 ,Set-enable SPI 1 ID 33 GPIO2" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SPI_SE_0 ,Set-enable SPI 0 ID 32 GPIO1" "Disabled,Enabled"
|
|
line.long 0x04 "GICD_IGROUPR2,Interrupt Set-enable SPI[63:32]"
|
|
bitfld.long 0x04 31. " SPI_SE_63 ,Set-enable SPI 63 ID 95 SW_INTR" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " SPI_SE_60 ,Set-enable SPI 60 ID 92 I2C3" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " SPI_SE_58 ,Set-enable SPI 58 ID 90 UARTD" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " SPI_SE_57 ,Set-enable SPI 57 ID 89 GPIO7" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " SPI_SE_55 ,Set-enable SPI 55 ID 87 GPIO6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SPI_SE_54 ,Set-enable SPI 54 ID 86 PMU_EXT" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " SPI_SE_52 ,Set-enable SPI 52 ID 84 I2C2" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " SPI_SE_51 ,Set-enable SPI 51 ID 83 SPI3" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " SPI_SE_50 ,Set-enable SPI 50 ID 82 SPI2" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " SPI_SE_49 ,Set-enable SPI 49 ID 81 HDA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SPI_SE_47 ,Set-enable SPI 47 ID 79 SPI6" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " SPI_SE_46 ,Set-enable SPI 46 ID 78 EMC" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " SPI_SE_45 ,Set-enable SPI 45 ID 77 MC" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " SPI_SE_44 ,Set-enable SPI 44 ID 76 SOR" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " SPI_SE_43 ,Set-enable SPI 43 ID 75 HDMI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " SPI_SE_42 ,Set-enable SPI 42 ID 74 DISPLAYB" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " SPI_SE_41 ,Set-enable SPI 41 ID 73 DISPLAY" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " SPI_SE_40 ,Set-enable SPI 40 ID 72 VIC" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " SPI_SE_39 ,Set-enable SPI 39 ID 71 ISP" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " SPI_SE_38 ,Set-enable SPI 38 ID 70 ISPB" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SPI_SE_37 ,Set-enable SPI 37 ID 69 VI" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " SPI_SE_36 ,Set-enable SPI 36 ID 68 MSENC" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " SPI_SE_35 ,Set-enable SPI 35 ID 67 HOST1X_GEN_CPU" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SPI_SE_34 ,Set-enable SPI 34 ID 66 HOST1X_GEN_COP" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " SPI_SE_33 ,Set-enable SPI 33 ID 65 HOST1X_SYNCPT_ CPU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SPI_SE_32 ,Set-enable SPI 32 ID 64 HOST1X_SYNCPT_ COP" "Disabled,Enabled"
|
|
line.long 0x08 "GICD_IGROUPR3,Interrupt Set-enable SPI[95:64]"
|
|
bitfld.long 0x08 31. " SPI_SE_95 ,Set-enable SPI 95 ID 127 HIER_GROUP1_ CPU" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " SPI_SE_94 ,Set-enable SPI 94 ID 126 CAR" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " SPI_SE_93 ,Set-enable SPI 93 ID 125 GPIO8" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " SPI_SE_92 ,Set-enable SPI 92 ID 124 WDT_AVP" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " SPI_SE_91 ,Set-enable SPI 91 ID 123 WDT_CPU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 26. " SPI_SE_90 ,Set-enable SPI 90 ID 122 HIER_GROUP1_ COP" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " SPI_SE_89 ,Set-enable SPI 89 ID 121 TMR5" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " SPI_SE_88 ,Set-enable SPI 88 ID 120 I2C4" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " SPI_SE_87 ,Set-enable SPI 87 ID 119 APB_DMA_CH15" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " SPI_SE_86 ,Set-enable SPI 86 ID 118 APB_DMA_CH14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SPI_SE_85 ,Set-enable SPI 85 ID 117 APB_DMA_CH13" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " SPI_SE_84 ,Set-enable SPI 84 ID 116 APB_DMA_CH12" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " SPI_SE_83 ,Set-enable SPI 83 ID 115 APB_DMA_CH11" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " SPI_SE_82 ,Set-enable SPI 82 ID 114 APB_DMA_CH10" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " SPI_SE_81 ,Set-enable SPI 81 ID 113 APB_DMA_CH9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " SPI_SE_80 ,Set-enable SPI 80 ID 112 APB_DMA_CH8" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " SPI_SE_79 ,Set-enable SPI 79 ID 111 APB_DMA_CH7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " SPI_SE_78 ,Set-enable SPI 78 ID 110 APB_DMA_CH6" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " SPI_SE_77 ,Set-enable SPI 77 ID 109 APB_DMA_CH5" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " SPI_SE_76 ,Set-enable SPI 76 ID 108 APB_DMA_CH4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SPI_SE_75 ,Set-enable SPI 75 ID 107 APB_DMA_CH3" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " SPI_SE_74 ,Set-enable SPI 74 ID 106 APB_DMA_CH2" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " SPI_SE_73 ,Set-enable SPI 73 ID 105 APB_DMA_CH1" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " SPI_SE_72 ,Set-enable SPI 72 ID 104 APB_DMA_CH0" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " SPI_SE_71 ,Set-enable SPI 71 ID 103 AUDIO_CLUSTER" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SPI_SE_69 ,Set-enable SPI 69 ID 101 AVP_CACHE" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " SPI_SE_68 ,Set-enable SPI 68 ID 100 PCIE_WAKE" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " SPI_SE_67 ,Set-enable SPI 67 ID 99 HOST1X_GEN_CPU" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SPI_SE_66 ,Set-enable SPI 66 ID 98 HOST1X_GEN_COP" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " SPI_SE_65 ,Set-enable SPI 65 ID 97 HOST1X_SYNCPT_CPU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SPI_SE_64 ,Set-enable SPI 64 ID 96 HOST1X_SYNCPT_COP" "Disabled,Enabled"
|
|
line.long 0x0C "GICD_IGROUPR4,Interrupt Set-enable SPI[127:96]"
|
|
bitfld.long 0x0C 31. " SPI_SE_127 ,Set-enable SPI 127 ID 159 ARDPAUX" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " SPI_SE_126 ,Set-enable SPI 126 ID 158 GPU_NONSTALL" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " SPI_SE_123 ,Set-enable SPI 125 ID 157 GPU_STALL" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " SPI_SE_122 ,Set-enable SPI 124 ID 156 TMR0" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " SPI_SE_121 ,Set-enable SPI 123 ID 155 TMR9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 26. " SPI_SE_120 ,Set-enable SPI 122 ID 154 TMR8" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " SPI_SE_119 ,Set-enable SPI 121 ID 153 TMR7" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " SPI_SE_118 ,Set-enable SPI 120 ID 152 TMR6" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " SPI_SE_117 ,Set-enable SPI 119 ID 151 SDMMC4_SYS" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " SPI_SE_116 ,Set-enable SPI 118 ID 150 SDMMC3_SYS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " SPI_SE_115 ,Set-enable SPI 117 ID 149 SDMMC2_SYS" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " SPI_SE_114 ,Set-enable SPI 116 ID 148 SDMMC1_SYS" "Disabled,Enabled"
|
|
bitfld.long 0x0C 19. " SPI_SE_113 ,Set-enable SPI 115 ID 147 CPU3_PMU_INTR" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " SPI_SE_112 ,Set-enable SPI 114 ID 146 CPU2_PMU_INTR" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " SPI_SE_111 ,Set-enable SPI 113 ID 145 CPU1_PMU_INTR" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " SPI_SE_110 ,Set-enable SPI 112 ID 144 CPU0_PMU_INTR" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " SPI_SE_111 ,Set-enable SPI 111 ID 143 APB_DMA_CH31" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " SPI_SE_110 ,Set-enable SPI 110 ID 142 APB_DMA_CH30" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " SPI_SE_109 ,Set-enable SPI 109 ID 141 APB_DMA_CH29" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " SPI_SE_108 ,Set-enable SPI 108 ID 140 APB_DMA_CH28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " SPI_SE_107 ,Set-enable SPI 107 ID 139 APB_DMA_CH27" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " SPI_SE_106 ,Set-enable SPI 106 ID 138 APB_DMA_CH26" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " SPI_SE_105 ,Set-enable SPI 105 ID 137 APB_DMA_CH25" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " SPI_SE_104 ,Set-enable SPI 104 ID 136 APB_DMA_CH24" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " SPI_SE_103 ,Set-enable SPI 103 ID 135 APB_DMA_CH23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " SPI_SE_102 ,Set-enable SPI 102 ID 134 APB_DMA_CH22" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " SPI_SE_101 ,Set-enable SPI 101 ID 133 APB_DMA_CH21" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " SPI_SE_100 ,Set-enable SPI 100 ID 132 APB_DMA_CH20" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " SPI_SE_99 ,Set-enable SPI 99 ID 131 APB_DMA_CH19" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SPI_SE_98 ,Set-enable SPI 98 ID 130 APB_DMA_CH18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SPI_SE_97 ,Set-enable SPI 97 ID 129 APB_DMA_CH17" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " SPI_SE_96 ,Set-enable SPI 96 ID 128 APB_DMA_CH16" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Clear-Enable"
|
|
width 17.
|
|
group.long 0x1180++0x03
|
|
line.long 0x00 "GICD_ICENABLER0,Interrupt clear-enable register (SGI,PPI)"
|
|
bitfld.long 0x00 31. " PPI_CE_15 ,Clear-enable for PPI ID 31 SDMMC4" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PPI_CE_14 ,Clear-enable for PPI ID 30 OWR" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PPI_CE_13 ,Clear-enable for PPI ID 29 ARB_SEM_GNT_CPU" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PPI_CE_12 ,Clear-enable for PPI ID 28 ARB_SEM_GNT_COP" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PPI_CE_11 ,Clear-enable for PPI ID 27 AHB_DMA_CPU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPI_CE_10 ,Clear-enable for PPI ID 26 APB_DMA_CPU" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PPI_CE_9 ,Clear-enable for PPI ID 25 VCP" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PPI_CE_7 ,Clear-enable for PPI ID 23 SATA_CTL" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " PPI_CE_5 ,Clear-enable for PPI ID 21 USB2" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PPI_CE_4 ,Clear-enable for PPI ID 20 USB" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PPI_CE_3 ,Clear-enable for PPI ID 19 SDMMC3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PPI_CE_2 ,Clear-enable for PPI ID 18 AVP_UCQ" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PPI_CE_1 ,Clear-enable for PPI ID 17 VDE" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SGI_CE_15 ,Clear-enable for SGI ID 15 SDMMC2" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " SGI_CE_14 ,Clear-enable for SGI ID 14 SDMMC1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " SGI_CE_13 ,Clear-enable for SGI ID 13 SATA_RX_STAT" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " SGI_CE_12 ,Clear-enable for SGI ID 12 VDE_SXE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " SGI_CE_11 ,Clear-enable for SGI ID 11 VDE_BSEA" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " SGI_CE_10 ,Clear-enable for SGI ID 10 VDE_BSEV" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " SGI_CE_9 ,Clear-enable for SGI ID 9 VDE_SYNC_TOKEN" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " SGI_CE_8 ,Clear-enable for SGI ID 8 VDE_UCQ" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " SGI_CE_7 ,Clear-enable for SGI ID 7 SHR_SEM_UTBOX_EMPTY" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " SGI_CE_6 ,Clear-enable for SGI ID 6 SHR_SEM_UTBOX_FULL" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " SGI_CE_5 ,Clear-enable for SGI ID 5 SHR_SEM_INBOX_EMPTY" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " SGI_CE_4 ,Clear-enable for SGI ID 4 SHR_SEM_INBOX_FULL" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " SGI_CE_3 ,Clear-enable for SGI ID 3 CEC" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " SGI_CE_2 ,Clear-enable for SGI ID 2 RTC" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " SGI_CE_1 ,Clear-enable for SGI ID 1 TMR2" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " SGI_CE_0 ,Clear-enable for SGI ID 0 TMR1" "Disabled,Enabled"
|
|
group.long 0x1104++0xF
|
|
line.long 0x00 "GICD_ICENABLER1,Interrupt Clear-enable (SPI[31:0])"
|
|
bitfld.long 0x00 31. " SPI_CE_31 ,Clear-enable SPI 31 ID 63 I2C6" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SPI_CE_30 ,Clear-enable SPI 30 ID 62 CLDVFS" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SPI_CE_29 ,Clear-enable SPI 29 ID 61 AHB_DMA_COP" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SPI_CE_28 ,Clear-enable SPI 28 ID 60 APB_DMA_COP" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SPI_CE_27 ,Clear-enable SPI 27 ID 59 SPI1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SPI_CE_26 ,Clear-enable SPI 26 ID 58 SE" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " SPI_CE_25 ,Clear-enable SPI 25 ID 57 USB3_DEV_PME" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SPI_CE_24 ,Clear-enable SPI 24 ID 56 USB3_DEV_SMI" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SPI_CE_23 ,Clear-enable SPI 23 ID 55 GPIO5" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " SPI_CE_22 ,Clear-enable SPI 22 ID 54 STAT_MON" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SPI_CE_21 ,Clear-enable SPI 21 ID 53 I2C5" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SPI_CE_10 ,Clear-enable SPI 20 ID 52 VFIR" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SPI_CE_19 ,Clear-enable SPI 19 ID 51 EDP" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SPI_CE_18 ,Clear-enable SPI 18 ID 50 TSEC" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SPI_CE_17 ,Clear-enable SPI 17 ID 49 XUSB_PADCTL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPI_CE_16 ,Clear-enable SPI 16 ID 48 THERMAL" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SPI_CE_15 ,Clear-enable SPI 15 ID 47 HSI" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SPI_CE_14 ,Clear-enable SPI 14 ID 46 UARTC" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SPI_CE_13 ,Clear-enable SPI 13 ID 45 ACTMON" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SPI_CE_12 ,Clear-enable SPI 12 ID 44 USB3_DEV_HOST" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPI_CE_11 ,Clear-enable SPI 11 ID 43 USB3_HOST_PME" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SPI_CE_10 ,Clear-enable SPI 10 ID 42 TMR4" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SPI_CE_9 ,Clear-enable SPI 9 ID 41 TMR3" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SPI_CE_8 ,Clear-enable SPI 8 ID 40 USB3_HOST_SMI" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SPI_CE_7 ,Clear-enable SPI 7 ID 39 USB3_HOST_INT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPI_CE_6 ,Clear-enable SPI 6 ID 38 I2C" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SPI_CE_5 ,Clear-enable SPI 5 ID 37 UARTB" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SPI_CE_4 ,Clear-enable SPI 4 ID 36 UARTA" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SPI_CE_3 ,Clear-enable SPI 3 ID 35 GPIO4" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SPI_CE_2 ,Clear-enable SPI 2 ID 34 GPIO3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPI_CE_1 ,Clear-enable SPI 1 ID 33 GPIO2" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SPI_CE_0 ,Clear-enable SPI 0 ID 32 GPIO1" "Disabled,Enabled"
|
|
line.long 0x04 "GICD_ICENABLER2,Interrupt Clear-enable SPI[63:32]"
|
|
bitfld.long 0x04 31. " SPI_CE_63 ,Clear-enable SPI 63 ID 95 SW_INTR" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " SPI_CE_60 ,Clear-enable SPI 60 ID 92 I2C3" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " SPI_CE_58 ,Clear-enable SPI 58 ID 90 UARTD" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " SPI_CE_57 ,Clear-enable SPI 57 ID 89 GPIO7" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " SPI_CE_55 ,Clear-enable SPI 55 ID 87 GPIO6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SPI_CE_54 ,Clear-enable SPI 54 ID 86 PMU_EXT" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " SPI_CE_52 ,Clear-enable SPI 52 ID 84 I2C2" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " SPI_CE_51 ,Clear-enable SPI 51 ID 83 SPI3" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " SPI_CE_50 ,Clear-enable SPI 50 ID 82 SPI2" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " SPI_CE_49 ,Clear-enable SPI 49 ID 81 HDA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SPI_CE_47 ,Clear-enable SPI 47 ID 79 SPI6" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " SPI_CE_46 ,Clear-enable SPI 46 ID 78 EMC" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " SPI_CE_45 ,Clear-enable SPI 45 ID 77 MC" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " SPI_CE_44 ,Clear-enable SPI 44 ID 76 SOR" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " SPI_CE_43 ,Clear-enable SPI 43 ID 75 HDMI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " SPI_CE_42 ,Clear-enable SPI 42 ID 74 DISPLAYB" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " SPI_CE_41 ,Clear-enable SPI 41 ID 73 DISPLAY" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " SPI_CE_40 ,Clear-enable SPI 40 ID 72 VIC" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " SPI_CE_39 ,Clear-enable SPI 39 ID 71 ISP" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " SPI_CE_38 ,Clear-enable SPI 38 ID 70 ISPB" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SPI_CE_37 ,Clear-enable SPI 37 ID 69 VI" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " SPI_CE_36 ,Clear-enable SPI 36 ID 68 MSENC" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " SPI_CE_35 ,Clear-enable SPI 35 ID 67 HOST1X_GEN_CPU" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SPI_CE_34 ,Clear-enable SPI 34 ID 66 HOST1X_GEN_COP" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " SPI_CE_33 ,Clear-enable SPI 33 ID 65 HOST1X_SYNCPT_ CPU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SPI_CE_32 ,Clear-enable SPI 32 ID 64 HOST1X_SYNCPT_ COP" "Disabled,Enabled"
|
|
line.long 0x08 "GICD_ICENABLER3,Interrupt Clear-enable SPI[95:64]"
|
|
bitfld.long 0x08 31. " SPI_CE_95 ,Clear-enable SPI 95 ID 127 HIER_clear-enable1_ CPU" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " SPI_CE_94 ,Clear-enable SPI 94 ID 126 CAR" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " SPI_CE_93 ,Clear-enable SPI 93 ID 125 GPIO8" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " SPI_CE_92 ,Clear-enable SPI 92 ID 124 WDT_AVP" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " SPI_CE_91 ,Clear-enable SPI 91 ID 123 WDT_CPU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 26. " SPI_CE_90 ,Clear-enable SPI 90 ID 122 HIER_clear-enable1_ COP" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " SPI_CE_89 ,Clear-enable SPI 89 ID 121 TMR5" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " SPI_CE_88 ,Clear-enable SPI 88 ID 120 I2C4" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " SPI_CE_87 ,Clear-enable SPI 87 ID 119 APB_DMA_CH15" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " SPI_CE_86 ,Clear-enable SPI 86 ID 118 APB_DMA_CH14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SPI_CE_85 ,Clear-enable SPI 85 ID 117 APB_DMA_CH13" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " SPI_CE_84 ,Clear-enable SPI 84 ID 116 APB_DMA_CH12" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " SPI_CE_83 ,Clear-enable SPI 83 ID 115 APB_DMA_CH11" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " SPI_CE_82 ,Clear-enable SPI 82 ID 114 APB_DMA_CH10" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " SPI_CE_81 ,Clear-enable SPI 81 ID 113 APB_DMA_CH9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " SPI_CE_80 ,Clear-enable SPI 80 ID 112 APB_DMA_CH8" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " SPI_CE_79 ,Clear-enable SPI 79 ID 111 APB_DMA_CH7" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " SPI_CE_78 ,Clear-enable SPI 78 ID 110 APB_DMA_CH6" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " SPI_CE_77 ,Clear-enable SPI 77 ID 109 APB_DMA_CH5" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " SPI_CE_76 ,Clear-enable SPI 76 ID 108 APB_DMA_CH4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SPI_CE_75 ,Clear-enable SPI 75 ID 107 APB_DMA_CH3" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " SPI_CE_74 ,Clear-enable SPI 74 ID 106 APB_DMA_CH2" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " SPI_CE_73 ,Clear-enable SPI 73 ID 105 APB_DMA_CH1" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " SPI_CE_72 ,Clear-enable SPI 72 ID 104 APB_DMA_CH0" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " SPI_CE_71 ,Clear-enable SPI 71 ID 103 AUDIO_CLUSTER" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SPI_CE_69 ,Clear-enable SPI 69 ID 101 AVP_CACHE" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " SPI_CE_68 ,Clear-enable SPI 68 ID 100 PCIE_WAKE" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " SPI_CE_67 ,Clear-enable SPI 67 ID 99 HOST1X_GEN_CPU" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SPI_CE_66 ,Clear-enable SPI 66 ID 98 HOST1X_GEN_COP" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " SPI_CE_65 ,Clear-enable SPI 65 ID 97 HOST1X_SYNCPT_CPU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SPI_CE_64 ,Clear-enable SPI 64 ID 96 HOST1X_SYNCPT_COP" "Disabled,Enabled"
|
|
line.long 0x0C "GICD_ICENABLER4,Interrupt Clear-enable SPI[127:96]"
|
|
bitfld.long 0x0C 31. " SPI_CE_127 ,Clear-enable SPI 127 ID 159 ARDPAUX" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " SPI_CE_126 ,Clear-enable SPI 126 ID 158 GPU_NONSTALL" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " SPI_CE_123 ,Clear-enable SPI 125 ID 157 GPU_STALL" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " SPI_CE_122 ,Clear-enable SPI 124 ID 156 TMR0" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " SPI_CE_121 ,Clear-enable SPI 123 ID 155 TMR9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 26. " SPI_CE_120 ,Clear-enable SPI 122 ID 154 TMR8" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " SPI_CE_119 ,Clear-enable SPI 121 ID 153 TMR7" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " SPI_CE_118 ,Clear-enable SPI 120 ID 152 TMR6" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " SPI_CE_117 ,Clear-enable SPI 119 ID 151 SDMMC4_SYS" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " SPI_CE_116 ,Clear-enable SPI 118 ID 150 SDMMC3_SYS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " SPI_CE_115 ,Clear-enable SPI 117 ID 149 SDMMC2_SYS" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " SPI_CE_114 ,Clear-enable SPI 116 ID 148 SDMMC1_SYS" "Disabled,Enabled"
|
|
bitfld.long 0x0C 19. " SPI_CE_113 ,Clear-enable SPI 115 ID 147 CPU3_PMU_INTR" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " SPI_CE_112 ,Clear-enable SPI 114 ID 146 CPU2_PMU_INTR" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " SPI_CE_111 ,Clear-enable SPI 113 ID 145 CPU1_PMU_INTR" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " SPI_CE_110 ,Clear-enable SPI 112 ID 144 CPU0_PMU_INTR" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " SPI_CE_111 ,Clear-enable SPI 111 ID 143 APB_DMA_CH31" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " SPI_CE_110 ,Clear-enable SPI 110 ID 142 APB_DMA_CH30" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " SPI_CE_109 ,Clear-enable SPI 109 ID 141 APB_DMA_CH29" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " SPI_CE_108 ,Clear-enable SPI 108 ID 140 APB_DMA_CH28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " SPI_CE_107 ,Clear-enable SPI 107 ID 139 APB_DMA_CH27" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " SPI_CE_106 ,Clear-enable SPI 106 ID 138 APB_DMA_CH26" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " SPI_CE_105 ,Clear-enable SPI 105 ID 137 APB_DMA_CH25" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " SPI_CE_104 ,Clear-enable SPI 104 ID 136 APB_DMA_CH24" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " SPI_CE_103 ,Clear-enable SPI 103 ID 135 APB_DMA_CH23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " SPI_CE_102 ,Clear-enable SPI 102 ID 134 APB_DMA_CH22" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " SPI_CE_101 ,Clear-enable SPI 101 ID 133 APB_DMA_CH21" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " SPI_CE_100 ,Clear-enable SPI 100 ID 132 APB_DMA_CH20" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " SPI_CE_99 ,Clear-enable SPI 99 ID 131 APB_DMA_CH19" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SPI_CE_98 ,Clear-enable SPI 98 ID 130 APB_DMA_CH18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SPI_CE_97 ,Clear-enable SPI 97 ID 129 APB_DMA_CH17" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " SPI_CE_96 ,Clear-enable SPI 96 ID 128 APB_DMA_CH16" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Set-pending"
|
|
width 15.
|
|
group.long 0x1200++0x03
|
|
line.long 0x00 "GICD_ISPENDR0,Interrupt pending-set register (SGI,PPI)"
|
|
bitfld.long 0x00 31. " PPI_SP_15 ,Set-pending for PPI ID 31 SDMMC4" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " PPI_SP_14 ,Set-pending for PPI ID 30 OWR" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " PPI_SP_13 ,Set-pending for PPI ID 29 ARB_SEM_GNT_CPU" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " PPI_SP_12 ,Set-pending for PPI ID 28 ARB_SEM_GNT_COP" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " PPI_SP_11 ,Set-pending for PPI ID 27 AHB_DMA_CPU" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPI_SP_10 ,Set-pending for PPI ID 26 APB_DMA_CPU" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " PPI_SP_9 ,Set-pending for PPI ID 25 VCP" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " PPI_SP_7 ,Set-pending for PPI ID 23 SATA_CTL" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " PPI_SP_5 ,Set-pending for PPI ID 21 USB2" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " PPI_SP_4 ,Set-pending for PPI ID 20 USB" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PPI_SP_3 ,Set-pending for PPI ID 19 SDMMC3" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " PPI_SP_2 ,Set-pending for PPI ID 18 AVP_UCQ" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " PPI_SP_1 ,Set-pending for PPI ID 17 VDE" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SGI_SP_15 ,Set-pending for SGI ID 15 SDMMC2" "Not pending,Pending"
|
|
rbitfld.long 0x00 14. " SGI_SP_14 ,Set-pending for SGI ID 14 SDMMC1" "Not pending,Pending"
|
|
rbitfld.long 0x00 13. " SGI_SP_13 ,Set-pending for SGI ID 13 SATA_RX_STAT" "Not pending,Pending"
|
|
rbitfld.long 0x00 12. " SGI_SP_12 ,Set-pending for SGI ID 12 VDE_SXE" "Not pending,Pending"
|
|
rbitfld.long 0x00 11. " SGI_SP_11 ,Set-pending for SGI ID 11 VDE_BSEA" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " SGI_SP_10 ,Set-pending for SGI ID 10 VDE_BSEV" "Not pending,Pending"
|
|
rbitfld.long 0x00 9. " SGI_SP_9 ,Set-pending for SGI ID 9 VDE_SYNC_TOKEN" "Not pending,Pending"
|
|
rbitfld.long 0x00 8. " SGI_SP_8 ,Set-pending for SGI ID 8 VDE_UCQ" "Not pending,Pending"
|
|
rbitfld.long 0x00 7. " SGI_SP_7 ,Set-pending for SGI ID 7 SHR_SEM_UTBOX_EMPTY" "Not pending,Pending"
|
|
rbitfld.long 0x00 6. " SGI_SP_6 ,Set-pending for SGI ID 6 SHR_SEM_UTBOX_FULL" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " SGI_SP_5 ,Set-pending for SGI ID 5 SHR_SEM_INBOX_EMPTY" "Not pending,Pending"
|
|
rbitfld.long 0x00 4. " SGI_SP_4 ,Set-pending for SGI ID 4 SHR_SEM_INBOX_FULL" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " SGI_SP_3 ,Set-pending for SGI ID 3 CEC" "Not pending,Pending"
|
|
rbitfld.long 0x00 2. " SGI_SP_2 ,Set-pending for SGI ID 2 RTC" "Not pending,Pending"
|
|
rbitfld.long 0x00 1. " SGI_SP_1 ,Set-pending for SGI ID 1 TMR2" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " SGI_SP_0 ,Set-pending for SGI ID 0 TMR1" "Not pending,Pending"
|
|
group.long 0x1104++0xF
|
|
line.long 0x00 "GICD_ISPENDR1,Interrupt Set-pending (SPI[31:0])"
|
|
bitfld.long 0x00 31. " SPI_SP_31 ,Set-pending SPI 31 ID 63 I2C6" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SPI_SP_30 ,Set-pending SPI 30 ID 62 CLDVFS" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " SPI_SP_29 ,Set-pending SPI 29 ID 61 AHB_DMA_COP" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " SPI_SP_28 ,Set-pending SPI 28 ID 60 APB_DMA_COP" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " SPI_SP_27 ,Set-pending SPI 27 ID 59 SPI1" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SPI_SP_26 ,Set-pending SPI 26 ID 58 SE" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " SPI_SP_25 ,Set-pending SPI 25 ID 57 USB3_DEV_PME" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " SPI_SP_24 ,Set-pending SPI 24 ID 56 USB3_DEV_SMI" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " SPI_SP_23 ,Set-pending SPI 23 ID 55 GPIO5" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " SPI_SP_22 ,Set-pending SPI 22 ID 54 STAT_MON" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SPI_SP_21 ,Set-pending SPI 21 ID 53 I2C5" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " SPI_SP_10 ,Set-pending SPI 20 ID 52 VFIR" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " SPI_SP_19 ,Set-pending SPI 19 ID 51 EDP" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " SPI_SP_18 ,Set-pending SPI 18 ID 50 TSEC" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " SPI_SP_17 ,Set-pending SPI 17 ID 49 XUSB_PADCTL" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPI_SP_16 ,Set-pending SPI 16 ID 48 THERMAL" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " SPI_SP_15 ,Set-pending SPI 15 ID 47 HSI" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " SPI_SP_14 ,Set-pending SPI 14 ID 46 UARTC" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " SPI_SP_13 ,Set-pending SPI 13 ID 45 ACTMON" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " SPI_SP_12 ,Set-pending SPI 12 ID 44 USB3_DEV_HOST" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPI_SP_11 ,Set-pending SPI 11 ID 43 USB3_HOST_PME" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " SPI_SP_10 ,Set-pending SPI 10 ID 42 TMR4" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " SPI_SP_9 ,Set-pending SPI 9 ID 41 TMR3" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " SPI_SP_8 ,Set-pending SPI 8 ID 40 USB3_HOST_SMI" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " SPI_SP_7 ,Set-pending SPI 7 ID 39 USB3_HOST_INT" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPI_SP_6 ,Set-pending SPI 6 ID 38 I2C" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " SPI_SP_5 ,Set-pending SPI 5 ID 37 UARTB" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " SPI_SP_4 ,Set-pending SPI 4 ID 36 UARTA" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " SPI_SP_3 ,Set-pending SPI 3 ID 35 GPIO4" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SPI_SP_2 ,Set-pending SPI 2 ID 34 GPIO3" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPI_SP_1 ,Set-pending SPI 1 ID 33 GPIO2" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SPI_SP_0 ,Set-pending SPI 0 ID 32 GPIO1" "Not pending,Pending"
|
|
line.long 0x04 "GICD_ISPENDR2,Interrupt Set-pending SPI[63:32]"
|
|
bitfld.long 0x04 31. " SPI_SP_63 ,Set-pending SPI 63 ID 95 SW_INTR" "Not pending,Pending"
|
|
bitfld.long 0x04 28. " SPI_SP_60 ,Set-pending SPI 60 ID 92 I2C3" "Not pending,Pending"
|
|
bitfld.long 0x04 26. " SPI_SP_58 ,Set-pending SPI 58 ID 90 UARTD" "Not pending,Pending"
|
|
bitfld.long 0x04 25. " SPI_SP_57 ,Set-pending SPI 57 ID 89 GPIO7" "Not pending,Pending"
|
|
bitfld.long 0x04 23. " SPI_SP_55 ,Set-pending SPI 55 ID 87 GPIO6" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SPI_SP_54 ,Set-pending SPI 54 ID 86 PMU_EXT" "Not pending,Pending"
|
|
bitfld.long 0x04 20. " SPI_SP_52 ,Set-pending SPI 52 ID 84 I2C2" "Not pending,Pending"
|
|
bitfld.long 0x04 19. " SPI_SP_51 ,Set-pending SPI 51 ID 83 SPI3" "Not pending,Pending"
|
|
bitfld.long 0x04 18. " SPI_SP_50 ,Set-pending SPI 50 ID 82 SPI2" "Not pending,Pending"
|
|
bitfld.long 0x04 17. " SPI_SP_49 ,Set-pending SPI 49 ID 81 HDA" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SPI_SP_47 ,Set-pending SPI 47 ID 79 SPI6" "Not pending,Pending"
|
|
bitfld.long 0x04 14. " SPI_SP_46 ,Set-pending SPI 46 ID 78 EMC" "Not pending,Pending"
|
|
bitfld.long 0x04 13. " SPI_SP_45 ,Set-pending SPI 45 ID 77 MC" "Not pending,Pending"
|
|
bitfld.long 0x04 12. " SPI_SP_44 ,Set-pending SPI 44 ID 76 SOR" "Not pending,Pending"
|
|
bitfld.long 0x04 11. " SPI_SP_43 ,Set-pending SPI 43 ID 75 HDMI" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 10. " SPI_SP_42 ,Set-pending SPI 42 ID 74 DISPLAYB" "Not pending,Pending"
|
|
bitfld.long 0x04 9. " SPI_SP_41 ,Set-pending SPI 41 ID 73 DISPLAY" "Not pending,Pending"
|
|
bitfld.long 0x04 8. " SPI_SP_40 ,Set-pending SPI 40 ID 72 VIC" "Not pending,Pending"
|
|
bitfld.long 0x04 7. " SPI_SP_39 ,Set-pending SPI 39 ID 71 ISP" "Not pending,Pending"
|
|
bitfld.long 0x04 6. " SPI_SP_38 ,Set-pending SPI 38 ID 70 ISPB" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SPI_SP_37 ,Set-pending SPI 37 ID 69 VI" "Not pending,Pending"
|
|
bitfld.long 0x04 4. " SPI_SP_36 ,Set-pending SPI 36 ID 68 MSENC" "Not pending,Pending"
|
|
bitfld.long 0x04 3. " SPI_SP_35 ,Set-pending SPI 35 ID 67 HOST1X_GEN_CPU" "Not pending,Pending"
|
|
bitfld.long 0x04 2. " SPI_SP_34 ,Set-pending SPI 34 ID 66 HOST1X_GEN_COP" "Not pending,Pending"
|
|
bitfld.long 0x04 1. " SPI_SP_33 ,Set-pending SPI 33 ID 65 HOST1X_SYNCPT_ CPU" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SPI_SP_32 ,Set-pending SPI 32 ID 64 HOST1X_SYNCPT_ COP" "Not pending,Pending"
|
|
line.long 0x08 "GICD_ISPENDR3,Interrupt Set-pending SPI[95:64]"
|
|
bitfld.long 0x08 31. " SPI_SP_95 ,Set-pending SPI 95 ID 127 HIER_GROUP1_ CPU" "Not pending,Pending"
|
|
bitfld.long 0x08 30. " SPI_SP_94 ,Set-pending SPI 94 ID 126 CAR" "Not pending,Pending"
|
|
bitfld.long 0x08 29. " SPI_SP_93 ,Set-pending SPI 93 ID 125 GPIO8" "Not pending,Pending"
|
|
bitfld.long 0x08 28. " SPI_SP_92 ,Set-pending SPI 92 ID 124 WDT_AVP" "Not pending,Pending"
|
|
bitfld.long 0x08 27. " SPI_SP_91 ,Set-pending SPI 91 ID 123 WDT_CPU" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 26. " SPI_SP_90 ,Set-pending SPI 90 ID 122 HIER_pending-set1_ COP" "Not pending,Pending"
|
|
bitfld.long 0x08 25. " SPI_SP_89 ,Set-pending SPI 89 ID 121 TMR5" "Not pending,Pending"
|
|
bitfld.long 0x08 24. " SPI_SP_88 ,Set-pending SPI 88 ID 120 I2C4" "Not pending,Pending"
|
|
bitfld.long 0x08 23. " SPI_SP_87 ,Set-pending SPI 87 ID 119 APB_DMA_CH15" "Not pending,Pending"
|
|
bitfld.long 0x08 22. " SPI_SP_86 ,Set-pending SPI 86 ID 118 APB_DMA_CH14" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SPI_SP_85 ,Set-pending SPI 85 ID 117 APB_DMA_CH13" "Not pending,Pending"
|
|
bitfld.long 0x08 20. " SPI_SP_84 ,Set-pending SPI 84 ID 116 APB_DMA_CH12" "Not pending,Pending"
|
|
bitfld.long 0x08 19. " SPI_SP_83 ,Set-pending SPI 83 ID 115 APB_DMA_CH11" "Not pending,Pending"
|
|
bitfld.long 0x08 18. " SPI_SP_82 ,Set-pending SPI 82 ID 114 APB_DMA_CH10" "Not pending,Pending"
|
|
bitfld.long 0x08 17. " SPI_SP_81 ,Set-pending SPI 81 ID 113 APB_DMA_CH9" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 16. " SPI_SP_80 ,Set-pending SPI 80 ID 112 APB_DMA_CH8" "Not pending,Pending"
|
|
bitfld.long 0x08 15. " SPI_SP_79 ,Set-pending SPI 79 ID 111 APB_DMA_CH7" "Not pending,Pending"
|
|
bitfld.long 0x08 14. " SPI_SP_78 ,Set-pending SPI 78 ID 110 APB_DMA_CH6" "Not pending,Pending"
|
|
bitfld.long 0x08 13. " SPI_SP_77 ,Set-pending SPI 77 ID 109 APB_DMA_CH5" "Not pending,Pending"
|
|
bitfld.long 0x08 12. " SPI_SP_76 ,Set-pending SPI 76 ID 108 APB_DMA_CH4" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SPI_SP_75 ,Set-pending SPI 75 ID 107 APB_DMA_CH3" "Not pending,Pending"
|
|
bitfld.long 0x08 10. " SPI_SP_74 ,Set-pending SPI 74 ID 106 APB_DMA_CH2" "Not pending,Pending"
|
|
bitfld.long 0x08 9. " SPI_SP_73 ,Set-pending SPI 73 ID 105 APB_DMA_CH1" "Not pending,Pending"
|
|
bitfld.long 0x08 8. " SPI_SP_72 ,Set-pending SPI 72 ID 104 APB_DMA_CH0" "Not pending,Pending"
|
|
bitfld.long 0x08 7. " SPI_SP_71 ,Set-pending SPI 71 ID 103 AUDIO_CLUSTER" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SPI_SP_69 ,Set-pending SPI 69 ID 101 AVP_CACHE" "Not pending,Pending"
|
|
bitfld.long 0x08 4. " SPI_SP_68 ,Set-pending SPI 68 ID 100 PCIE_WAKE" "Not pending,Pending"
|
|
bitfld.long 0x08 3. " SPI_SP_67 ,Set-pending SPI 67 ID 99 HOST1X_GEN_CPU" "Not pending,Pending"
|
|
bitfld.long 0x08 2. " SPI_SP_66 ,Set-pending SPI 66 ID 98 HOST1X_GEN_COP" "Not pending,Pending"
|
|
bitfld.long 0x08 1. " SPI_SP_65 ,Set-pending SPI 65 ID 97 HOST1X_SYNCPT_CPU" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SPI_SP_64 ,Set-pending SPI 64 ID 96 HOST1X_SYNCPT_COP" "Not pending,Pending"
|
|
line.long 0x0C "GICD_ISPENDR4,Interrupt Set-pending SPI[127:96]"
|
|
bitfld.long 0x0C 31. " SPI_SP_127 ,Set-pending SPI 127 ID 159 ARDPAUX" "Not pending,Pending"
|
|
bitfld.long 0x0C 30. " SPI_SP_126 ,Set-pending SPI 126 ID 158 GPU_NONSTALL" "Not pending,Pending"
|
|
bitfld.long 0x0C 29. " SPI_SP_123 ,Set-pending SPI 125 ID 157 GPU_STALL" "Not pending,Pending"
|
|
bitfld.long 0x0C 28. " SPI_SP_122 ,Set-pending SPI 124 ID 156 TMR0" "Not pending,Pending"
|
|
bitfld.long 0x0C 27. " SPI_SP_121 ,Set-pending SPI 123 ID 155 TMR9" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 26. " SPI_SP_120 ,Set-pending SPI 122 ID 154 TMR8" "Not pending,Pending"
|
|
bitfld.long 0x0C 25. " SPI_SP_119 ,Set-pending SPI 121 ID 153 TMR7" "Not pending,Pending"
|
|
bitfld.long 0x0C 24. " SPI_SP_118 ,Set-pending SPI 120 ID 152 TMR6" "Not pending,Pending"
|
|
bitfld.long 0x0C 23. " SPI_SP_117 ,Set-pending SPI 119 ID 151 SDMMC4_SYS" "Not pending,Pending"
|
|
bitfld.long 0x0C 22. " SPI_SP_116 ,Set-pending SPI 118 ID 150 SDMMC3_SYS" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " SPI_SP_115 ,Set-pending SPI 117 ID 149 SDMMC2_SYS" "Not pending,Pending"
|
|
bitfld.long 0x0C 20. " SPI_SP_114 ,Set-pending SPI 116 ID 148 SDMMC1_SYS" "Not pending,Pending"
|
|
bitfld.long 0x0C 19. " SPI_SP_113 ,Set-pending SPI 115 ID 147 CPU3_PMU_INTR" "Not pending,Pending"
|
|
bitfld.long 0x0C 18. " SPI_SP_112 ,Set-pending SPI 114 ID 146 CPU2_PMU_INTR" "Not pending,Pending"
|
|
bitfld.long 0x0C 17. " SPI_SP_111 ,Set-pending SPI 113 ID 145 CPU1_PMU_INTR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " SPI_SP_110 ,Set-pending SPI 112 ID 144 CPU0_PMU_INTR" "Not pending,Pending"
|
|
bitfld.long 0x0C 15. " SPI_SP_111 ,Set-pending SPI 111 ID 143 APB_DMA_CH31" "Not pending,Pending"
|
|
bitfld.long 0x0C 14. " SPI_SP_110 ,Set-pending SPI 110 ID 142 APB_DMA_CH30" "Not pending,Pending"
|
|
bitfld.long 0x0C 13. " SPI_SP_109 ,Set-pending SPI 109 ID 141 APB_DMA_CH29" "Not pending,Pending"
|
|
bitfld.long 0x0C 12. " SPI_SP_108 ,Set-pending SPI 108 ID 140 APB_DMA_CH28" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " SPI_SP_107 ,Set-pending SPI 107 ID 139 APB_DMA_CH27" "Not pending,Pending"
|
|
bitfld.long 0x0C 10. " SPI_SP_106 ,Set-pending SPI 106 ID 138 APB_DMA_CH26" "Not pending,Pending"
|
|
bitfld.long 0x0C 9. " SPI_SP_105 ,Set-pending SPI 105 ID 137 APB_DMA_CH25" "Not pending,Pending"
|
|
bitfld.long 0x0C 8. " SPI_SP_104 ,Set-pending SPI 104 ID 136 APB_DMA_CH24" "Not pending,Pending"
|
|
bitfld.long 0x0C 7. " SPI_SP_103 ,Set-pending SPI 103 ID 135 APB_DMA_CH23" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " SPI_SP_102 ,Set-pending SPI 102 ID 134 APB_DMA_CH22" "Not pending,Pending"
|
|
bitfld.long 0x0C 5. " SPI_SP_101 ,Set-pending SPI 101 ID 133 APB_DMA_CH21" "Not pending,Pending"
|
|
bitfld.long 0x0C 4. " SPI_SP_100 ,Set-pending SPI 100 ID 132 APB_DMA_CH20" "Not pending,Pending"
|
|
bitfld.long 0x0C 3. " SPI_SP_99 ,Set-pending SPI 99 ID 131 APB_DMA_CH19" "Not pending,Pending"
|
|
bitfld.long 0x0C 2. " SPI_SP_98 ,Set-pending SPI 98 ID 130 APB_DMA_CH18" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SPI_SP_97 ,Set-pending SPI 97 ID 129 APB_DMA_CH17" "Not pending,Pending"
|
|
bitfld.long 0x0C 0. " SPI_SP_96 ,Set-pending SPI 96 ID 128 APB_DMA_CH16" "Not pending,Pending"
|
|
tree.end
|
|
tree "Interrupt Clear-pending"
|
|
group.long 0x1280++0x03
|
|
line.long 0x00 "GICD_ICPENDR0,Interrupt pending-Clear register (SGI,PPI)"
|
|
bitfld.long 0x00 31. " PPI_CP_15 ,Clear-pending for PPI ID 31 SDMMC4" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " PPI_CP_14 ,Clear-pending for PPI ID 30 OWR" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " PPI_CP_13 ,Clear-pending for PPI ID 29 ARB_SEM_GNT_CPU" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " PPI_CP_12 ,Clear-pending for PPI ID 28 ARB_SEM_GNT_COP" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " PPI_CP_11 ,Clear-pending for PPI ID 27 AHB_DMA_CPU" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPI_CP_10 ,Clear-pending for PPI ID 26 APB_DMA_CPU" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " PPI_CP_9 ,Clear-pending for PPI ID 25 VCP" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " PPI_CP_7 ,Clear-pending for PPI ID 23 SATA_CTL" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " PPI_CP_5 ,Clear-pending for PPI ID 21 USB2" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " PPI_CP_4 ,Clear-pending for PPI ID 20 USB" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PPI_CP_3 ,Clear-pending for PPI ID 19 SDMMC3" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " PPI_CP_2 ,Clear-pending for PPI ID 18 AVP_UCQ" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " PPI_CP_1 ,Clear-pending for PPI ID 17 VDE" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SGI_CP_15 ,Clear-pending for SGI ID 15 SDMMC2" "Not pending,Pending"
|
|
rbitfld.long 0x00 14. " SGI_CP_14 ,Clear-pending for SGI ID 14 SDMMC1" "Not pending,Pending"
|
|
rbitfld.long 0x00 13. " SGI_CP_13 ,Clear-pending for SGI ID 13 SATA_RX_STAT" "Not pending,Pending"
|
|
rbitfld.long 0x00 12. " SGI_CP_12 ,Clear-pending for SGI ID 12 VDE_SXE" "Not pending,Pending"
|
|
rbitfld.long 0x00 11. " SGI_CP_11 ,Clear-pending for SGI ID 11 VDE_BSEA" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " SGI_CP_10 ,Clear-pending for SGI ID 10 VDE_BSEV" "Not pending,Pending"
|
|
rbitfld.long 0x00 9. " SGI_CP_9 ,Clear-pending for SGI ID 9 VDE_SYNC_TOKEN" "Not pending,Pending"
|
|
rbitfld.long 0x00 8. " SGI_CP_8 ,Clear-pending for SGI ID 8 VDE_UCQ" "Not pending,Pending"
|
|
rbitfld.long 0x00 7. " SGI_CP_7 ,Clear-pending for SGI ID 7 SHR_SEM_UTBOX_EMPTY" "Not pending,Pending"
|
|
rbitfld.long 0x00 6. " SGI_CP_6 ,Clear-pending for SGI ID 6 SHR_SEM_UTBOX_FULL" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " SGI_CP_5 ,Clear-pending for SGI ID 5 SHR_SEM_INBOX_EMPTY" "Not pending,Pending"
|
|
rbitfld.long 0x00 4. " SGI_CP_4 ,Clear-pending for SGI ID 4 SHR_SEM_INBOX_FULL" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " SGI_CP_3 ,Clear-pending for SGI ID 3 CEC" "Not pending,Pending"
|
|
rbitfld.long 0x00 2. " SGI_CP_2 ,Clear-pending for SGI ID 2 RTC" "Not pending,Pending"
|
|
rbitfld.long 0x00 1. " SGI_CP_1 ,Clear-pending for SGI ID 1 TMR2" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " SGI_CP_0 ,Clear-pending for SGI ID 0 TMR1" "Not pending,Pending"
|
|
group.long 0x1284++0xF
|
|
line.long 0x00 "GICD_ICPENDR1,Interrupt Clear-pending (SPI[31:0])"
|
|
bitfld.long 0x00 31. " SPI_CP_31 ,Clear-pending SPI 31 ID 63 I2C6" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SPI_CP_30 ,Clear-pending SPI 30 ID 62 CLDVFS" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " SPI_CP_29 ,Clear-pending SPI 29 ID 61 AHB_DMA_COP" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " SPI_CP_28 ,Clear-pending SPI 28 ID 60 APB_DMA_COP" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " SPI_CP_27 ,Clear-pending SPI 27 ID 59 SPI1" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SPI_CP_26 ,Clear-pending SPI 26 ID 58 SE" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " SPI_CP_25 ,Clear-pending SPI 25 ID 57 USB3_DEV_PME" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " SPI_CP_24 ,Clear-pending SPI 24 ID 56 USB3_DEV_SMI" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " SPI_CP_23 ,Clear-pending SPI 23 ID 55 GPIO5" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " SPI_CP_22 ,Clear-pending SPI 22 ID 54 STAT_MON" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SPI_CP_21 ,Clear-pending SPI 21 ID 53 I2C5" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " SPI_CP_10 ,Clear-pending SPI 20 ID 52 VFIR" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " SPI_CP_19 ,Clear-pending SPI 19 ID 51 EDP" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " SPI_CP_18 ,Clear-pending SPI 18 ID 50 TSEC" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " SPI_CP_17 ,Clear-pending SPI 17 ID 49 XUSB_PADCTL" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPI_CP_16 ,Clear-pending SPI 16 ID 48 THERMAL" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " SPI_CP_15 ,Clear-pending SPI 15 ID 47 HSI" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " SPI_CP_14 ,Clear-pending SPI 14 ID 46 UARTC" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " SPI_CP_13 ,Clear-pending SPI 13 ID 45 ACTMON" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " SPI_CP_12 ,Clear-pending SPI 12 ID 44 USB3_DEV_HOST" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPI_CP_11 ,Clear-pending SPI 11 ID 43 USB3_HOST_PME" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " SPI_CP_10 ,Clear-pending SPI 10 ID 42 TMR4" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " SPI_CP_9 ,Clear-pending SPI 9 ID 41 TMR3" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " SPI_CP_8 ,Clear-pending SPI 8 ID 40 USB3_HOST_SMI" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " SPI_CP_7 ,Clear-pending SPI 7 ID 39 USB3_HOST_INT" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPI_CP_6 ,Clear-pending SPI 6 ID 38 I2C" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " SPI_CP_5 ,Clear-pending SPI 5 ID 37 UARTB" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " SPI_CP_4 ,Clear-pending SPI 4 ID 36 UARTA" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " SPI_CP_3 ,Clear-pending SPI 3 ID 35 GPIO4" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SPI_CP_2 ,Clear-pending SPI 2 ID 34 GPIO3" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPI_CP_1 ,Clear-pending SPI 1 ID 33 GPIO2" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SPI_CP_0 ,Clear-pending SPI 0 ID 32 GPIO1" "Not pending,Pending"
|
|
line.long 0x04 "GICD_ICPENDR2,Interrupt Clear-pending SPI[63:32]"
|
|
bitfld.long 0x04 31. " SPI_CP_63 ,Clear-pending SPI 63 ID 95 SW_INTR" "Not pending,Pending"
|
|
bitfld.long 0x04 28. " SPI_CP_60 ,Clear-pending SPI 60 ID 92 I2C3" "Not pending,Pending"
|
|
bitfld.long 0x04 26. " SPI_CP_58 ,Clear-pending SPI 58 ID 90 UARTD" "Not pending,Pending"
|
|
bitfld.long 0x04 25. " SPI_CP_57 ,Clear-pending SPI 57 ID 89 GPIO7" "Not pending,Pending"
|
|
bitfld.long 0x04 23. " SPI_CP_55 ,Clear-pending SPI 55 ID 87 GPIO6" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SPI_CP_54 ,Clear-pending SPI 54 ID 86 PMU_EXT" "Not pending,Pending"
|
|
bitfld.long 0x04 20. " SPI_CP_52 ,Clear-pending SPI 52 ID 84 I2C2" "Not pending,Pending"
|
|
bitfld.long 0x04 19. " SPI_CP_51 ,Clear-pending SPI 51 ID 83 SPI3" "Not pending,Pending"
|
|
bitfld.long 0x04 18. " SPI_CP_50 ,Clear-pending SPI 50 ID 82 SPI2" "Not pending,Pending"
|
|
bitfld.long 0x04 17. " SPI_CP_49 ,Clear-pending SPI 49 ID 81 HDA" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SPI_CP_47 ,Clear-pending SPI 47 ID 79 SPI6" "Not pending,Pending"
|
|
bitfld.long 0x04 14. " SPI_CP_46 ,Clear-pending SPI 46 ID 78 EMC" "Not pending,Pending"
|
|
bitfld.long 0x04 13. " SPI_CP_45 ,Clear-pending SPI 45 ID 77 MC" "Not pending,Pending"
|
|
bitfld.long 0x04 12. " SPI_CP_44 ,Clear-pending SPI 44 ID 76 SOR" "Not pending,Pending"
|
|
bitfld.long 0x04 11. " SPI_CP_43 ,Clear-pending SPI 43 ID 75 HDMI" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 10. " SPI_CP_42 ,Clear-pending SPI 42 ID 74 DISPLAYB" "Not pending,Pending"
|
|
bitfld.long 0x04 9. " SPI_CP_41 ,Clear-pending SPI 41 ID 73 DISPLAY" "Not pending,Pending"
|
|
bitfld.long 0x04 8. " SPI_CP_40 ,Clear-pending SPI 40 ID 72 VIC" "Not pending,Pending"
|
|
bitfld.long 0x04 7. " SPI_CP_39 ,Clear-pending SPI 39 ID 71 ISP" "Not pending,Pending"
|
|
bitfld.long 0x04 6. " SPI_CP_38 ,Clear-pending SPI 38 ID 70 ISPB" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SPI_CP_37 ,Clear-pending SPI 37 ID 69 VI" "Not pending,Pending"
|
|
bitfld.long 0x04 4. " SPI_CP_36 ,Clear-pending SPI 36 ID 68 MSENC" "Not pending,Pending"
|
|
bitfld.long 0x04 3. " SPI_CP_35 ,Clear-pending SPI 35 ID 67 HOST1X_GEN_CPU" "Not pending,Pending"
|
|
bitfld.long 0x04 2. " SPI_CP_34 ,Clear-pending SPI 34 ID 66 HOST1X_GEN_COP" "Not pending,Pending"
|
|
bitfld.long 0x04 1. " SPI_CP_33 ,Clear-pending SPI 33 ID 65 HOST1X_SYNCPT_ CPU" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SPI_CP_32 ,Clear-pending SPI 32 ID 64 HOST1X_SYNCPT_ COP" "Not pending,Pending"
|
|
line.long 0x08 "GICD_ICPENDR3,Interrupt Clear-pending SPI[95:64]"
|
|
bitfld.long 0x08 31. " SPI_CP_95 ,Clear-pending SPI 95 ID 127 HIER_pending-Clear1_ CPU" "Not pending,Pending"
|
|
bitfld.long 0x08 30. " SPI_CP_94 ,Clear-pending SPI 94 ID 126 CAR" "Not pending,Pending"
|
|
bitfld.long 0x08 29. " SPI_CP_93 ,Clear-pending SPI 93 ID 125 GPIO8" "Not pending,Pending"
|
|
bitfld.long 0x08 28. " SPI_CP_92 ,Clear-pending SPI 92 ID 124 WDT_AVP" "Not pending,Pending"
|
|
bitfld.long 0x08 27. " SPI_CP_91 ,Clear-pending SPI 91 ID 123 WDT_CPU" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 26. " SPI_CP_90 ,Clear-pending SPI 90 ID 122 HIER_pending-Clear1_ COP" "Not pending,Pending"
|
|
bitfld.long 0x08 25. " SPI_CP_89 ,Clear-pending SPI 89 ID 121 TMR5" "Not pending,Pending"
|
|
bitfld.long 0x08 24. " SPI_CP_88 ,Clear-pending SPI 88 ID 120 I2C4" "Not pending,Pending"
|
|
bitfld.long 0x08 23. " SPI_CP_87 ,Clear-pending SPI 87 ID 119 APB_DMA_CH15" "Not pending,Pending"
|
|
bitfld.long 0x08 22. " SPI_CP_86 ,Clear-pending SPI 86 ID 118 APB_DMA_CH14" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SPI_CP_85 ,Clear-pending SPI 85 ID 117 APB_DMA_CH13" "Not pending,Pending"
|
|
bitfld.long 0x08 20. " SPI_CP_84 ,Clear-pending SPI 84 ID 116 APB_DMA_CH12" "Not pending,Pending"
|
|
bitfld.long 0x08 19. " SPI_CP_83 ,Clear-pending SPI 83 ID 115 APB_DMA_CH11" "Not pending,Pending"
|
|
bitfld.long 0x08 18. " SPI_CP_82 ,Clear-pending SPI 82 ID 114 APB_DMA_CH10" "Not pending,Pending"
|
|
bitfld.long 0x08 17. " SPI_CP_81 ,Clear-pending SPI 81 ID 113 APB_DMA_CH9" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 16. " SPI_CP_80 ,Clear-pending SPI 80 ID 112 APB_DMA_CH8" "Not pending,Pending"
|
|
bitfld.long 0x08 15. " SPI_CP_79 ,Clear-pending SPI 79 ID 111 APB_DMA_CH7" "Not pending,Pending"
|
|
bitfld.long 0x08 14. " SPI_CP_78 ,Clear-pending SPI 78 ID 110 APB_DMA_CH6" "Not pending,Pending"
|
|
bitfld.long 0x08 13. " SPI_CP_77 ,Clear-pending SPI 77 ID 109 APB_DMA_CH5" "Not pending,Pending"
|
|
bitfld.long 0x08 12. " SPI_CP_76 ,Clear-pending SPI 76 ID 108 APB_DMA_CH4" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SPI_CP_75 ,Clear-pending SPI 75 ID 107 APB_DMA_CH3" "Not pending,Pending"
|
|
bitfld.long 0x08 10. " SPI_CP_74 ,Clear-pending SPI 74 ID 106 APB_DMA_CH2" "Not pending,Pending"
|
|
bitfld.long 0x08 9. " SPI_CP_73 ,Clear-pending SPI 73 ID 105 APB_DMA_CH1" "Not pending,Pending"
|
|
bitfld.long 0x08 8. " SPI_CP_72 ,Clear-pending SPI 72 ID 104 APB_DMA_CH0" "Not pending,Pending"
|
|
bitfld.long 0x08 7. " SPI_CP_71 ,Clear-pending SPI 71 ID 103 AUDIO_CLUSTER" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SPI_CP_69 ,Clear-pending SPI 69 ID 101 AVP_CACHE" "Not pending,Pending"
|
|
bitfld.long 0x08 4. " SPI_CP_68 ,Clear-pending SPI 68 ID 100 PCIE_WAKE" "Not pending,Pending"
|
|
bitfld.long 0x08 3. " SPI_CP_67 ,Clear-pending SPI 67 ID 99 HOST1X_GEN_CPU" "Not pending,Pending"
|
|
bitfld.long 0x08 2. " SPI_CP_66 ,Clear-pending SPI 66 ID 98 HOST1X_GEN_COP" "Not pending,Pending"
|
|
bitfld.long 0x08 1. " SPI_CP_65 ,Clear-pending SPI 65 ID 97 HOST1X_SYNCPT_CPU" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SPI_CP_64 ,Clear-pending SPI 64 ID 96 HOST1X_SYNCPT_COP" "Not pending,Pending"
|
|
line.long 0x0C "GICD_ICPENDR4,Interrupt Clear-pending SPI[127:96]"
|
|
bitfld.long 0x0C 31. " SPI_CP_127 ,Clear-pending SPI 127 ID 159 ARDPAUX" "Not pending,Pending"
|
|
bitfld.long 0x0C 30. " SPI_CP_126 ,Clear-pending SPI 126 ID 158 GPU_NONSTALL" "Not pending,Pending"
|
|
bitfld.long 0x0C 29. " SPI_CP_123 ,Clear-pending SPI 125 ID 157 GPU_STALL" "Not pending,Pending"
|
|
bitfld.long 0x0C 28. " SPI_CP_122 ,Clear-pending SPI 124 ID 156 TMR0" "Not pending,Pending"
|
|
bitfld.long 0x0C 27. " SPI_CP_121 ,Clear-pending SPI 123 ID 155 TMR9" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 26. " SPI_CP_120 ,Clear-pending SPI 122 ID 154 TMR8" "Not pending,Pending"
|
|
bitfld.long 0x0C 25. " SPI_CP_119 ,Clear-pending SPI 121 ID 153 TMR7" "Not pending,Pending"
|
|
bitfld.long 0x0C 24. " SPI_CP_118 ,Clear-pending SPI 120 ID 152 TMR6" "Not pending,Pending"
|
|
bitfld.long 0x0C 23. " SPI_CP_117 ,Clear-pending SPI 119 ID 151 SDMMC4_SYS" "Not pending,Pending"
|
|
bitfld.long 0x0C 22. " SPI_CP_116 ,Clear-pending SPI 118 ID 150 SDMMC3_SYS" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " SPI_CP_115 ,Clear-pending SPI 117 ID 149 SDMMC2_SYS" "Not pending,Pending"
|
|
bitfld.long 0x0C 20. " SPI_CP_114 ,Clear-pending SPI 116 ID 148 SDMMC1_SYS" "Not pending,Pending"
|
|
bitfld.long 0x0C 19. " SPI_CP_113 ,Clear-pending SPI 115 ID 147 CPU3_PMU_INTR" "Not pending,Pending"
|
|
bitfld.long 0x0C 18. " SPI_CP_112 ,Clear-pending SPI 114 ID 146 CPU2_PMU_INTR" "Not pending,Pending"
|
|
bitfld.long 0x0C 17. " SPI_CP_111 ,Clear-pending SPI 113 ID 145 CPU1_PMU_INTR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " SPI_CP_110 ,Clear-pending SPI 112 ID 144 CPU0_PMU_INTR" "Not pending,Pending"
|
|
bitfld.long 0x0C 15. " SPI_CP_111 ,Clear-pending SPI 111 ID 143 APB_DMA_CH31" "Not pending,Pending"
|
|
bitfld.long 0x0C 14. " SPI_CP_110 ,Clear-pending SPI 110 ID 142 APB_DMA_CH30" "Not pending,Pending"
|
|
bitfld.long 0x0C 13. " SPI_CP_109 ,Clear-pending SPI 109 ID 141 APB_DMA_CH29" "Not pending,Pending"
|
|
bitfld.long 0x0C 12. " SPI_CP_108 ,Clear-pending SPI 108 ID 140 APB_DMA_CH28" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " SPI_CP_107 ,Clear-pending SPI 107 ID 139 APB_DMA_CH27" "Not pending,Pending"
|
|
bitfld.long 0x0C 10. " SPI_CP_106 ,Clear-pending SPI 106 ID 138 APB_DMA_CH26" "Not pending,Pending"
|
|
bitfld.long 0x0C 9. " SPI_CP_105 ,Clear-pending SPI 105 ID 137 APB_DMA_CH25" "Not pending,Pending"
|
|
bitfld.long 0x0C 8. " SPI_CP_104 ,Clear-pending SPI 104 ID 136 APB_DMA_CH24" "Not pending,Pending"
|
|
bitfld.long 0x0C 7. " SPI_CP_103 ,Clear-pending SPI 103 ID 135 APB_DMA_CH23" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " SPI_CP_102 ,Clear-pending SPI 102 ID 134 APB_DMA_CH22" "Not pending,Pending"
|
|
bitfld.long 0x0C 5. " SPI_CP_101 ,Clear-pending SPI 101 ID 133 APB_DMA_CH21" "Not pending,Pending"
|
|
bitfld.long 0x0C 4. " SPI_CP_100 ,Clear-pending SPI 100 ID 132 APB_DMA_CH20" "Not pending,Pending"
|
|
bitfld.long 0x0C 3. " SPI_CP_99 ,Clear-pending SPI 99 ID 131 APB_DMA_CH19" "Not pending,Pending"
|
|
bitfld.long 0x0C 2. " SPI_CP_98 ,Clear-pending SPI 98 ID 130 APB_DMA_CH18" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SPI_CP_97 ,Clear-pending SPI 97 ID 129 APB_DMA_CH17" "Not pending,Pending"
|
|
bitfld.long 0x0C 0. " SPI_CP_96 ,Clear-pending SPI 96 ID 128 APB_DMA_CH16" "Not pending,Pending"
|
|
tree.end
|
|
tree "Interrupt Active status"
|
|
group.long 0x1300++0x03
|
|
line.long 0x00 "GICD_ISPENDR0,Interrupt pending-set register (SGI,PPI)"
|
|
bitfld.long 0x00 31. " PPI_AS_15 ,Active status for PPI ID 31 SDMMC4" "No active,Active"
|
|
bitfld.long 0x00 30. " PPI_AS_14 ,Active status for PPI ID 30 OWR" "No active,Active"
|
|
bitfld.long 0x00 29. " PPI_AS_13 ,Active status for PPI ID 29 ARB_SEM_GNT_CPU" "No active,Active"
|
|
bitfld.long 0x00 28. " PPI_AS_12 ,Active status for PPI ID 28 ARB_SEM_GNT_COP" "No active,Active"
|
|
bitfld.long 0x00 27. " PPI_AS_11 ,Active status for PPI ID 27 AHB_DMA_CPU" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPI_AS_10 ,Active status for PPI ID 26 APB_DMA_CPU" "No active,Active"
|
|
bitfld.long 0x00 25. " PPI_AS_9 ,Active status for PPI ID 25 VCP" "No active,Active"
|
|
bitfld.long 0x00 23. " PPI_AS_7 ,Active status for PPI ID 23 SATA_CTL" "No active,Active"
|
|
bitfld.long 0x00 21. " PPI_AS_5 ,Active status for PPI ID 21 USB2" "No active,Active"
|
|
bitfld.long 0x00 20. " PPI_AS_4 ,Active status for PPI ID 20 USB" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PPI_AS_3 ,Active status for PPI ID 19 SDMMC3" "No active,Active"
|
|
bitfld.long 0x00 18. " PPI_AS_2 ,Active status for PPI ID 18 AVP_UCQ" "No active,Active"
|
|
bitfld.long 0x00 17. " PPI_AS_1 ,Active status for PPI ID 17 VDE" "No active,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SGI_AS_15 ,Active status for SGI ID 15 SDMMC2" "No active,Active"
|
|
rbitfld.long 0x00 14. " SGI_AS_14 ,Active status for SGI ID 14 SDMMC1" "No active,Active"
|
|
rbitfld.long 0x00 13. " SGI_AS_13 ,Active status for SGI ID 13 SATA_RX_STAT" "No active,Active"
|
|
rbitfld.long 0x00 12. " SGI_AS_12 ,Active status for SGI ID 12 VDE_SXE" "No active,Active"
|
|
rbitfld.long 0x00 11. " SGI_AS_11 ,Active status for SGI ID 11 VDE_BSEA" "No active,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " SGI_AS_10 ,Active status for SGI ID 10 VDE_BSEV" "No active,Active"
|
|
rbitfld.long 0x00 9. " SGI_AS_9 ,Active status for SGI ID 9 VDE_SYNC_TOKEN" "No active,Active"
|
|
rbitfld.long 0x00 8. " SGI_AS_8 ,Active status for SGI ID 8 VDE_UCQ" "No active,Active"
|
|
rbitfld.long 0x00 7. " SGI_AS_7 ,Active status for SGI ID 7 SHR_SEM_UTBOX_EMPTY" "No active,Active"
|
|
rbitfld.long 0x00 6. " SGI_AS_6 ,Active status for SGI ID 6 SHR_SEM_UTBOX_FULL" "No active,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " SGI_AS_5 ,Active status for SGI ID 5 SHR_SEM_INBOX_EMPTY" "No active,Active"
|
|
rbitfld.long 0x00 4. " SGI_AS_4 ,Active status for SGI ID 4 SHR_SEM_INBOX_FULL" "No active,Active"
|
|
rbitfld.long 0x00 3. " SGI_AS_3 ,Active status for SGI ID 3 CEC" "No active,Active"
|
|
rbitfld.long 0x00 2. " SGI_AS_2 ,Active status for SGI ID 2 RTC" "No active,Active"
|
|
rbitfld.long 0x00 1. " SGI_AS_1 ,Active status for SGI ID 1 TMR2" "No active,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " SGI_AS_0 ,Active status for SGI ID 0 TMR1" "No active,Active"
|
|
group.long 0x1304++0xF
|
|
line.long 0x00 "GICD_ISPENDR1,Interrupt Active status (SPI[31:0])"
|
|
bitfld.long 0x00 31. " SPI_AS_31 ,Active status SPI 31 ID 63 I2C6" "No active,Active"
|
|
bitfld.long 0x00 30. " SPI_AS_30 ,Active status SPI 30 ID 62 CLDVFS" "No active,Active"
|
|
bitfld.long 0x00 29. " SPI_AS_29 ,Active status SPI 29 ID 61 AHB_DMA_COP" "No active,Active"
|
|
bitfld.long 0x00 28. " SPI_AS_28 ,Active status SPI 28 ID 60 APB_DMA_COP" "No active,Active"
|
|
bitfld.long 0x00 27. " SPI_AS_27 ,Active status SPI 27 ID 59 SPI1" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SPI_AS_26 ,Active status SPI 26 ID 58 SE" "No active,Active"
|
|
bitfld.long 0x00 25. " SPI_AS_25 ,Active status SPI 25 ID 57 USB3_DEV_PME" "No active,Active"
|
|
bitfld.long 0x00 24. " SPI_AS_24 ,Active status SPI 24 ID 56 USB3_DEV_SMI" "No active,Active"
|
|
bitfld.long 0x00 23. " SPI_AS_23 ,Active status SPI 23 ID 55 GPIO5" "No active,Active"
|
|
bitfld.long 0x00 22. " SPI_AS_22 ,Active status SPI 22 ID 54 STAT_MON" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SPI_AS_21 ,Active status SPI 21 ID 53 I2C5" "No active,Active"
|
|
bitfld.long 0x00 20. " SPI_AS_10 ,Active status SPI 20 ID 52 VFIR" "No active,Active"
|
|
bitfld.long 0x00 19. " SPI_AS_19 ,Active status SPI 19 ID 51 EDP" "No active,Active"
|
|
bitfld.long 0x00 18. " SPI_AS_18 ,Active status SPI 18 ID 50 TSEC" "No active,Active"
|
|
bitfld.long 0x00 17. " SPI_AS_17 ,Active status SPI 17 ID 49 XUSB_PADCTL" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SPI_AS_16 ,Active status SPI 16 ID 48 THERMAL" "No active,Active"
|
|
bitfld.long 0x00 15. " SPI_AS_15 ,Active status SPI 15 ID 47 HSI" "No active,Active"
|
|
bitfld.long 0x00 14. " SPI_AS_14 ,Active status SPI 14 ID 46 UARTC" "No active,Active"
|
|
bitfld.long 0x00 13. " SPI_AS_13 ,Active status SPI 13 ID 45 ACTMON" "No active,Active"
|
|
bitfld.long 0x00 12. " SPI_AS_12 ,Active status SPI 12 ID 44 USB3_DEV_HOST" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPI_AS_11 ,Active status SPI 11 ID 43 USB3_HOST_PME" "No active,Active"
|
|
bitfld.long 0x00 10. " SPI_AS_10 ,Active status SPI 10 ID 42 TMR4" "No active,Active"
|
|
bitfld.long 0x00 9. " SPI_AS_9 ,Active status SPI 9 ID 41 TMR3" "No active,Active"
|
|
bitfld.long 0x00 8. " SPI_AS_8 ,Active status SPI 8 ID 40 USB3_HOST_SMI" "No active,Active"
|
|
bitfld.long 0x00 7. " SPI_AS_7 ,Active status SPI 7 ID 39 USB3_HOST_INT" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SPI_AS_6 ,Active status SPI 6 ID 38 I2C" "No active,Active"
|
|
bitfld.long 0x00 5. " SPI_AS_5 ,Active status SPI 5 ID 37 UARTB" "No active,Active"
|
|
bitfld.long 0x00 4. " SPI_AS_4 ,Active status SPI 4 ID 36 UARTA" "No active,Active"
|
|
bitfld.long 0x00 3. " SPI_AS_3 ,Active status SPI 3 ID 35 GPIO4" "No active,Active"
|
|
bitfld.long 0x00 2. " SPI_AS_2 ,Active status SPI 2 ID 34 GPIO3" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPI_AS_1 ,Active status SPI 1 ID 33 GPIO2" "No active,Active"
|
|
bitfld.long 0x00 0. " SPI_AS_0 ,Active status SPI 0 ID 32 GPIO1" "No active,Active"
|
|
line.long 0x04 "GICD_ISPENDR2,Interrupt Active status SPI[63:32]"
|
|
bitfld.long 0x04 31. " SPI_AS_63 ,Active status SPI 63 ID 95 SW_INTR" "No active,Active"
|
|
bitfld.long 0x04 28. " SPI_AS_60 ,Active status SPI 60 ID 92 I2C3" "No active,Active"
|
|
bitfld.long 0x04 26. " SPI_AS_58 ,Active status SPI 58 ID 90 UARTD" "No active,Active"
|
|
bitfld.long 0x04 25. " SPI_AS_57 ,Active status SPI 57 ID 89 GPIO7" "No active,Active"
|
|
bitfld.long 0x04 23. " SPI_AS_55 ,Active status SPI 55 ID 87 GPIO6" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SPI_AS_54 ,Active status SPI 54 ID 86 PMU_EXT" "No active,Active"
|
|
bitfld.long 0x04 20. " SPI_AS_52 ,Active status SPI 52 ID 84 I2C2" "No active,Active"
|
|
bitfld.long 0x04 19. " SPI_AS_51 ,Active status SPI 51 ID 83 SPI3" "No active,Active"
|
|
bitfld.long 0x04 18. " SPI_AS_50 ,Active status SPI 50 ID 82 SPI2" "No active,Active"
|
|
bitfld.long 0x04 17. " SPI_AS_49 ,Active status SPI 49 ID 81 HDA" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SPI_AS_47 ,Active status SPI 47 ID 79 SPI6" "No active,Active"
|
|
bitfld.long 0x04 14. " SPI_AS_46 ,Active status SPI 46 ID 78 EMC" "No active,Active"
|
|
bitfld.long 0x04 13. " SPI_AS_45 ,Active status SPI 45 ID 77 MC" "No active,Active"
|
|
bitfld.long 0x04 12. " SPI_AS_44 ,Active status SPI 44 ID 76 SOR" "No active,Active"
|
|
bitfld.long 0x04 11. " SPI_AS_43 ,Active status SPI 43 ID 75 HDMI" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 10. " SPI_AS_42 ,Active status SPI 42 ID 74 DISPLAYB" "No active,Active"
|
|
bitfld.long 0x04 9. " SPI_AS_41 ,Active status SPI 41 ID 73 DISPLAY" "No active,Active"
|
|
bitfld.long 0x04 8. " SPI_AS_40 ,Active status SPI 40 ID 72 VIC" "No active,Active"
|
|
bitfld.long 0x04 7. " SPI_AS_39 ,Active status SPI 39 ID 71 ISP" "No active,Active"
|
|
bitfld.long 0x04 6. " SPI_AS_38 ,Active status SPI 38 ID 70 ISPB" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SPI_AS_37 ,Active status SPI 37 ID 69 VI" "No active,Active"
|
|
bitfld.long 0x04 4. " SPI_AS_36 ,Active status SPI 36 ID 68 MSENC" "No active,Active"
|
|
bitfld.long 0x04 3. " SPI_AS_35 ,Active status SPI 35 ID 67 HOST1X_GEN_CPU" "No active,Active"
|
|
bitfld.long 0x04 2. " SPI_AS_34 ,Active status SPI 34 ID 66 HOST1X_GEN_COP" "No active,Active"
|
|
bitfld.long 0x04 1. " SPI_AS_33 ,Active status SPI 33 ID 65 HOST1X_SYNCPT_ CPU" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SPI_AS_32 ,Active status SPI 32 ID 64 HOST1X_SYNCPT_ COP" "No active,Active"
|
|
line.long 0x08 "GICD_ISPENDR3,Interrupt Active status SPI[95:64]"
|
|
bitfld.long 0x08 31. " SPI_AS_95 ,Active status SPI 95 ID 127 HIER_pending-set1_ CPU" "No active,Active"
|
|
bitfld.long 0x08 30. " SPI_AS_94 ,Active status SPI 94 ID 126 CAR" "No active,Active"
|
|
bitfld.long 0x08 29. " SPI_AS_93 ,Active status SPI 93 ID 125 GPIO8" "No active,Active"
|
|
bitfld.long 0x08 28. " SPI_AS_92 ,Active status SPI 92 ID 124 WDT_AVP" "No active,Active"
|
|
bitfld.long 0x08 27. " SPI_AS_91 ,Active status SPI 91 ID 123 WDT_CPU" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 26. " SPI_AS_90 ,Active status SPI 90 ID 122 HIER_pending-set1_ COP" "No active,Active"
|
|
bitfld.long 0x08 25. " SPI_AS_89 ,Active status SPI 89 ID 121 TMR5" "No active,Active"
|
|
bitfld.long 0x08 24. " SPI_AS_88 ,Active status SPI 88 ID 120 I2C4" "No active,Active"
|
|
bitfld.long 0x08 23. " SPI_AS_87 ,Active status SPI 87 ID 119 APB_DMA_CH15" "No active,Active"
|
|
bitfld.long 0x08 22. " SPI_AS_86 ,Active status SPI 86 ID 118 APB_DMA_CH14" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SPI_AS_85 ,Active status SPI 85 ID 117 APB_DMA_CH13" "No active,Active"
|
|
bitfld.long 0x08 20. " SPI_AS_84 ,Active status SPI 84 ID 116 APB_DMA_CH12" "No active,Active"
|
|
bitfld.long 0x08 19. " SPI_AS_83 ,Active status SPI 83 ID 115 APB_DMA_CH11" "No active,Active"
|
|
bitfld.long 0x08 18. " SPI_AS_82 ,Active status SPI 82 ID 114 APB_DMA_CH10" "No active,Active"
|
|
bitfld.long 0x08 17. " SPI_AS_81 ,Active status SPI 81 ID 113 APB_DMA_CH9" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 16. " SPI_AS_80 ,Active status SPI 80 ID 112 APB_DMA_CH8" "No active,Active"
|
|
bitfld.long 0x08 15. " SPI_AS_79 ,Active status SPI 79 ID 111 APB_DMA_CH7" "No active,Active"
|
|
bitfld.long 0x08 14. " SPI_AS_78 ,Active status SPI 78 ID 110 APB_DMA_CH6" "No active,Active"
|
|
bitfld.long 0x08 13. " SPI_AS_77 ,Active status SPI 77 ID 109 APB_DMA_CH5" "No active,Active"
|
|
bitfld.long 0x08 12. " SPI_AS_76 ,Active status SPI 76 ID 108 APB_DMA_CH4" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SPI_AS_75 ,Active status SPI 75 ID 107 APB_DMA_CH3" "No active,Active"
|
|
bitfld.long 0x08 10. " SPI_AS_74 ,Active status SPI 74 ID 106 APB_DMA_CH2" "No active,Active"
|
|
bitfld.long 0x08 9. " SPI_AS_73 ,Active status SPI 73 ID 105 APB_DMA_CH1" "No active,Active"
|
|
bitfld.long 0x08 8. " SPI_AS_72 ,Active status SPI 72 ID 104 APB_DMA_CH0" "No active,Active"
|
|
bitfld.long 0x08 7. " SPI_AS_71 ,Active status SPI 71 ID 103 AUDIO_CLUSTER" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SPI_AS_69 ,Active status SPI 69 ID 101 AVP_CACHE" "No active,Active"
|
|
bitfld.long 0x08 4. " SPI_AS_68 ,Active status SPI 68 ID 100 PCIE_WAKE" "No active,Active"
|
|
bitfld.long 0x08 3. " SPI_AS_67 ,Active status SPI 67 ID 99 HOST1X_GEN_CPU" "No active,Active"
|
|
bitfld.long 0x08 2. " SPI_AS_66 ,Active status SPI 66 ID 98 HOST1X_GEN_COP" "No active,Active"
|
|
bitfld.long 0x08 1. " SPI_AS_65 ,Active status SPI 65 ID 97 HOST1X_SYNCPT_CPU" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SPI_AS_64 ,Active status SPI 64 ID 96 HOST1X_SYNCPT_COP" "No active,Active"
|
|
line.long 0x0C "GICD_ISPENDR4,Interrupt Active status SPI[127:96]"
|
|
bitfld.long 0x0C 31. " SPI_AS_127 ,Active status SPI 127 ID 159 ARDPAUX" "No active,Active"
|
|
bitfld.long 0x0C 30. " SPI_AS_126 ,Active status SPI 126 ID 158 GPU_NONSTALL" "No active,Active"
|
|
bitfld.long 0x0C 29. " SPI_AS_123 ,Active status SPI 125 ID 157 GPU_STALL" "No active,Active"
|
|
bitfld.long 0x0C 28. " SPI_AS_122 ,Active status SPI 124 ID 156 TMR0" "No active,Active"
|
|
bitfld.long 0x0C 27. " SPI_AS_121 ,Active status SPI 123 ID 155 TMR9" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x0C 26. " SPI_AS_120 ,Active status SPI 122 ID 154 TMR8" "No active,Active"
|
|
bitfld.long 0x0C 25. " SPI_AS_119 ,Active status SPI 121 ID 153 TMR7" "No active,Active"
|
|
bitfld.long 0x0C 24. " SPI_AS_118 ,Active status SPI 120 ID 152 TMR6" "No active,Active"
|
|
bitfld.long 0x0C 23. " SPI_AS_117 ,Active status SPI 119 ID 151 SDMMC4_SYS" "No active,Active"
|
|
bitfld.long 0x0C 22. " SPI_AS_116 ,Active status SPI 118 ID 150 SDMMC3_SYS" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " SPI_AS_115 ,Active status SPI 117 ID 149 SDMMC2_SYS" "No active,Active"
|
|
bitfld.long 0x0C 20. " SPI_AS_114 ,Active status SPI 116 ID 148 SDMMC1_SYS" "No active,Active"
|
|
bitfld.long 0x0C 19. " SPI_AS_113 ,Active status SPI 115 ID 147 CPU3_PMU_INTR" "No active,Active"
|
|
bitfld.long 0x0C 18. " SPI_AS_112 ,Active status SPI 114 ID 146 CPU2_PMU_INTR" "No active,Active"
|
|
bitfld.long 0x0C 17. " SPI_AS_111 ,Active status SPI 113 ID 145 CPU1_PMU_INTR" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " SPI_AS_110 ,Active status SPI 112 ID 144 CPU0_PMU_INTR" "No active,Active"
|
|
bitfld.long 0x0C 15. " SPI_AS_111 ,Active status SPI 111 ID 143 APB_DMA_CH31" "No active,Active"
|
|
bitfld.long 0x0C 14. " SPI_AS_110 ,Active status SPI 110 ID 142 APB_DMA_CH30" "No active,Active"
|
|
bitfld.long 0x0C 13. " SPI_AS_109 ,Active status SPI 109 ID 141 APB_DMA_CH29" "No active,Active"
|
|
bitfld.long 0x0C 12. " SPI_AS_108 ,Active status SPI 108 ID 140 APB_DMA_CH28" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " SPI_AS_107 ,Active status SPI 107 ID 139 APB_DMA_CH27" "No active,Active"
|
|
bitfld.long 0x0C 10. " SPI_AS_106 ,Active status SPI 106 ID 138 APB_DMA_CH26" "No active,Active"
|
|
bitfld.long 0x0C 9. " SPI_AS_105 ,Active status SPI 105 ID 137 APB_DMA_CH25" "No active,Active"
|
|
bitfld.long 0x0C 8. " SPI_AS_104 ,Active status SPI 104 ID 136 APB_DMA_CH24" "No active,Active"
|
|
bitfld.long 0x0C 7. " SPI_AS_103 ,Active status SPI 103 ID 135 APB_DMA_CH23" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " SPI_AS_102 ,Active status SPI 102 ID 134 APB_DMA_CH22" "No active,Active"
|
|
bitfld.long 0x0C 5. " SPI_AS_101 ,Active status SPI 101 ID 133 APB_DMA_CH21" "No active,Active"
|
|
bitfld.long 0x0C 4. " SPI_AS_100 ,Active status SPI 100 ID 132 APB_DMA_CH20" "No active,Active"
|
|
bitfld.long 0x0C 3. " SPI_AS_99 ,Active status SPI 99 ID 131 APB_DMA_CH19" "No active,Active"
|
|
bitfld.long 0x0C 2. " SPI_AS_98 ,Active status SPI 98 ID 130 APB_DMA_CH18" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SPI_AS_97 ,Active status SPI 97 ID 129 APB_DMA_CH17" "No active,Active"
|
|
bitfld.long 0x0C 0. " SPI_AS_96 ,Active status SPI 96 ID 128 APB_DMA_CH16" "No active,Active"
|
|
tree.end
|
|
tree "Priority Level"
|
|
width 19.
|
|
group.long 0x1400++0x0F "SGI Priority"
|
|
line.long 0x0 "GICD_IPRIORITYR0,Priority level register for SGI [3:0]"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x4 "GICD_IPRIORITYR1,Priority level register for SGI [7:4]"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x8 "GICD_IPRIORITYR2,Priority level register for SGI [11:8]"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0xC "GICD_IPRIORITYR3,Priority level register for SGI [15:12]"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
rgroup.long 0x1410++0x03 "PPI Priority"
|
|
line.long 0x00 "GICD_IPRIORITYR4,Priority level register for PPI [3:0]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
rgroup.long 0x1414++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR5,Priority level register for PPI [7:4]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
rgroup.long 0x1418++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR6,Priority level register for PPI [11:9]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
rgroup.long 0x141C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR7,Priority level register for PPI [15:12]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
group.long 0x1420++0x1F "SPI Priority"
|
|
line.long 0x0 "GICD_IPRIORITYR8,Priority level register for SPI [3:0]"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x4 "GICD_IPRIORITYR9,Priority level register for SPI [7:4]"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x8 "GICD_IPRIORITYR10,Priority level register for SPI [11:8]"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0xC "GICD_IPRIORITYR11,Priority level register for SPI [15:12]"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x10 "GICD_IPRIORITYR12,Priority level register for SPI [19:16]"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x14 "GICD_IPRIORITYR13,Priority level register for SPI [23:20]"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x18 "GICD_IPRIORITYR14,Priority level register for SPI [27:24]"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x1C "GICD_IPRIORITYR15,Priority level register for SPI [31:28]"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
group.long 0x1440++0x0F
|
|
line.long 0x0 "GICD_IPRIORITYR16,Priority level register for SPI [35:32]"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x4 "GICD_IPRIORITYR17,Priority level register for SPI [39:36]"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x8 "GICD_IPRIORITYR18,Priority level register for SPI [43:40]"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0xC "GICD_IPRIORITYR19,Priority level register for SPI [47:44]"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
group.long 0x1450++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR20,Priority level register for SPI [51:49]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
group.long 0x1454++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR21,Priority level register for SPI [55,54,52]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
group.long 0x1458++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR22,Priority level register for SPI [58,57]"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
group.long 0x145C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR23,Priority level register for SPI [63:60]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
group.long 0x1460++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR24,Priority level register for SPI [67:64]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
group.long 0x1464++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR25,Priority level register for SPI [71,69,68]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
group.long 0x1468++0x37
|
|
line.long 0x0 "GICD_IPRIORITYR26,Priority level register for SPI [75:72]"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x4 "GICD_IPRIORITYR27,Priority level register for SPI [79:76]"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x8 "GICD_IPRIORITYR28,Priority level register for SPI [83:80]"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0xC "GICD_IPRIORITYR29,Priority level register for SPI [87:84]"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x10 "GICD_IPRIORITYR30,Priority level register for SPI [91:88]"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x14 "GICD_IPRIORITYR31,Priority level register for SPI [95:92]"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x18 "GICD_IPRIORITYR32,Priority level register for SPI [99:96]"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x1C "GICD_IPRIORITYR33,Priority level register for SPI [103:100]"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x20 "GICD_IPRIORITYR34,Priority level register for SPI [107:104]"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x24 "GICD_IPRIORITYR35,Priority level register for SPI [111:108]"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x28 "GICD_IPRIORITYR36,Priority level register for SPI [115:112]"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x2C "GICD_IPRIORITYR37,Priority level register for SPI [119:116]"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x30 "GICD_IPRIORITYR38,Priority level register for SPI [123:120]"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x34 "GICD_IPRIORITYR39,Priority level register for SPI [127:124]"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
tree.end
|
|
tree "Processor Targets"
|
|
width 19.
|
|
group.long 0x1800++0x0F "SGI Processor target"
|
|
line.long 0x0 "GICD_ITARGETSR0,Processor target register for SGI [3:0]"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x4 "GICD_ITARGETSR1,Processor target register for SGI [7:4]"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x8 "GICD_ITARGETSR2,Processor target register for SGI [11:8]"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0xC "GICD_ITARGETSR3,Processor target register for SGI [15:12]"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
rgroup.long 0x1810++0x03 "PPI Processor target"
|
|
line.long 0x00 "GICD_ITARGETSR4,Processor target register for PPI [3:0]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
rgroup.long 0x1814++0x03
|
|
line.long 0x00 "GICD_ITARGETSR5,Processor target register for PPI [7:4]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
rgroup.long 0x1818++0x03
|
|
line.long 0x00 "GICD_ITARGETSR6,Processor target register for PPI [11:9]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
rgroup.long 0x181C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR7,Processor target register for PPI [15:12]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
group.long 0x1820++0x1F "SPI Processor target"
|
|
line.long 0x0 "GICD_ITARGETSR8,Processor target register for SPI [3:0]"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x4 "GICD_ITARGETSR9,Processor target register for SPI [7:4]"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x8 "GICD_ITARGETSR10,Processor target register for SPI [11:8]"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0xC "GICD_ITARGETSR11,Processor target register for SPI [15:12]"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x10 "GICD_ITARGETSR12,Processor target register for SPI [19:16]"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x14 "GICD_ITARGETSR13,Processor target register for SPI [23:20]"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x18 "GICD_ITARGETSR14,Processor target register for SPI [27:24]"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x1C "GICD_ITARGETSR15,Processor target register for SPI [31:28]"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
group.long 0x1840++0x0F
|
|
line.long 0x0 "GICD_ITARGETSR16,Processor target register for SPI [35:32]"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x4 "GICD_ITARGETSR17,Processor target register for SPI [39:36]"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x8 "GICD_ITARGETSR18,Processor target register for SPI [43:40]"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0xC "GICD_ITARGETSR19,Processor target register for SPI [47:44]"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
group.long 0x1850++0x03
|
|
line.long 0x00 "GICD_ITARGETSR20,Processor target register for SPI [51:49]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
group.long 0x1854++0x03
|
|
line.long 0x00 "GICD_ITARGETSR21,Processor target register for SPI [55,54,52]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
group.long 0x1858++0x03
|
|
line.long 0x00 "GICD_ITARGETSR22,Processor target register for SPI [58,57]"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
group.long 0x185C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR23,Processor target register for SPI [63:60]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
group.long 0x1860++0x03
|
|
line.long 0x00 "GICD_ITARGETSR24,Processor target register for SPI [67:64]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
group.long 0x1864++0x03
|
|
line.long 0x00 "GICD_ITARGETSR25,Processor target register for SPI [71,69,68]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
group.long 0x1868++0x37
|
|
line.long 0x0 "GICD_ITARGETSR26,Processor target register for SPI [75:72]"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x4 "GICD_ITARGETSR27,Processor target register for SPI [79:76]"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x8 "GICD_ITARGETSR28,Processor target register for SPI [83:80]"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0xC "GICD_ITARGETSR29,Processor target register for SPI [87:84]"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x10 "GICD_ITARGETSR30,Processor target register for SPI [91:88]"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x14 "GICD_ITARGETSR31,Processor target register for SPI [95:92]"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x18 "GICD_ITARGETSR32,Processor target register for SPI [99:96]"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x1C "GICD_ITARGETSR33,Processor target register for SPI [103:100]"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x20 "GICD_ITARGETSR34,Processor target register for SPI [107:104]"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x24 "GICD_ITARGETSR35,Processor target register for SPI [111:108]"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x28 "GICD_ITARGETSR36,Processor target register for SPI [115:112]"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x2C "GICD_ITARGETSR37,Processor target register for SPI [119:116]"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x30 "GICD_ITARGETSR38,Processor target register for SPI [123:120]"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
line.long 0x34 "GICD_ITARGETSR39,Processor target register for SPI [127:124]"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PBO3 ,Byte offset 3"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PBO2 ,Byte offset 2"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PBO1 ,Byte offset 1"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PBO0 ,Byte offset 0"
|
|
tree.end
|
|
tree "Interrupt Configuration"
|
|
width 14.
|
|
group.long 0x1C00++0x27
|
|
line.long 0x00 "GICD_ICFGR0,Interrupt Configuration SGI Register"
|
|
bitfld.long 0x00 30.--31. " SGI[15] ,Interrupt Configuration SGI[15]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x00 28.--29. " SGI[14] ,Interrupt Configuration SGI[14]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x00 26.--27. " SGI[13] ,Interrupt Configuration SGI[13]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " SGI[12] ,Interrupt Configuration SGI[12]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x00 22.--23. " SGI[11] ,Interrupt Configuration SGI[11]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x00 20.--21. " SGI[10] ,Interrupt Configuration SGI[10]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " SGI[9] ,Interrupt Configuration SGI[9]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x00 16.--17. " SGI[8] ,Interrupt Configuration SGI[8]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x00 14.--15. " SGI[7] ,Interrupt Configuration SGI[7]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SGI[6] ,Interrupt Configuration SGI[6]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x00 10.--11. " SGI[5] ,Interrupt Configuration SGI[5]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x00 8.--9. " SGI[4] ,Interrupt Configuration SGI[4]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SGI[3] ,Interrupt Configuration SGI[3]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x00 4.--5. " SGI[2] ,Interrupt Configuration SGI[2]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x00 2.--3. " SGI[1] ,Interrupt Configuration SGI[1]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SGI[0] ,Interrupt Configuration SGI[0]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
line.long 0x04 "GICD_ICFGR1,Interrupt Configuration PPI Register"
|
|
bitfld.long 0x04 30.--31. " PPI[15] ,Interrupt Configuration PPI[15]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x04 28.--29. " PPI[14] ,Interrupt Configuration PPI[14]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x04 26.--27. " PPI[13] ,Interrupt Configuration PPI[13]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x04 24.--25. " PPI[12] ,Interrupt Configuration PPI[12]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x04 22.--23. " PPI[11] ,Interrupt Configuration PPI[11]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x04 20.--21. " PPI[10] ,Interrupt Configuration PPI[10]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " PPI[9] ,Interrupt Configuration PPI[9]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x04 14.--15. " PPI[7] ,Interrupt Configuration PPI[7]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x04 10.--11. " PPI[5] ,Interrupt Configuration PPI[5]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " PPI[4] ,Interrupt Configuration PPI[4]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x04 6.--7. " PPI[3] ,Interrupt Configuration PPI[3]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x04 4.--5. " PPI[2] ,Interrupt Configuration PPI[2]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " PPI[1] ,Interrupt Configuration PPI[1]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
line.long 0x08 "GICD_ICFGR2,Interrupt Configuration SPI[15:0] Register"
|
|
bitfld.long 0x08 30.--31. " SPI[15] ,Interrupt Configuration SPI[15]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x08 28.--29. " SPI[14] ,Interrupt Configuration SPI[14]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x08 26.--27. " SPI[13] ,Interrupt Configuration SPI[13]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " SPI[12] ,Interrupt Configuration SPI[12]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x08 22.--23. " SPI[11] ,Interrupt Configuration SPI[11]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x08 20.--21. " SPI[10] ,Interrupt Configuration SPI[10]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " SPI[9] ,Interrupt Configuration SPI[9]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x08 16.--17. " SPI[8] ,Interrupt Configuration SPI[8]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x08 14.--15. " SPI[7] ,Interrupt Configuration SPI[7]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " SPI[6] ,Interrupt Configuration SPI[6]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x08 10.--11. " SPI[5] ,Interrupt Configuration SPI[5]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x08 8.--9. " SPI[4] ,Interrupt Configuration SPI[4]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " SPI[3] ,Interrupt Configuration SPI[3]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x08 4.--5. " SPI[2] ,Interrupt Configuration SPI[2]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x08 2.--3. " SPI[1] ,Interrupt Configuration SPI[1]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " SPI[0] ,Interrupt Configuration SPI[0]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
line.long 0x0C "GICD_ICFGR3,Interrupt Configuration SPI[31:16] Register"
|
|
bitfld.long 0x0C 30.--31. " SPI[31] ,Interrupt Configuration SPI[31]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x0C 28.--29. " SPI[30] ,Interrupt Configuration SPI[30]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x0C 26.--27. " SPI[29] ,Interrupt Configuration SPI[29]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " SPI[28] ,Interrupt Configuration SPI[28]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x0C 22.--23. " SPI[27] ,Interrupt Configuration SPI[27]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x0C 20.--21. " SPI[26] ,Interrupt Configuration SPI[26]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " SPI[25] ,Interrupt Configuration SPI[25]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x0C 16.--17. " SPI[24] ,Interrupt Configuration SPI[24]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x0C 14.--15. " SPI[23] ,Interrupt Configuration SPI[23]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " SPI[22] ,Interrupt Configuration SPI[22]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x0C 10.--11. " SPI[21] ,Interrupt Configuration SPI[21]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x0C 8.--9. " SPI[20] ,Interrupt Configuration SPI[20]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " SPI[19] ,Interrupt Configuration SPI[19]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x0C 4.--5. " SPI[18] ,Interrupt Configuration SPI[18]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x0C 2.--3. " SPI[17] ,Interrupt Configuration SPI[17]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " SPI[16] ,Interrupt Configuration SPI[16]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
line.long 0x10 "GICD_ICFGR4,Interrupt Configuration SPI[47:32] Register"
|
|
bitfld.long 0x10 30.--31. " SPI[47] ,Interrupt Configuration SPI[47]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x10 28.--29. " SPI[46] ,Interrupt Configuration SPI[46]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x10 26.--27. " SPI[45] ,Interrupt Configuration SPI[45]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x10 24.--25. " SPI[44] ,Interrupt Configuration SPI[44]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x10 22.--23. " SPI[43] ,Interrupt Configuration SPI[43]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x10 20.--21. " SPI[42] ,Interrupt Configuration SPI[42]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x10 18.--19. " SPI[41] ,Interrupt Configuration SPI[41]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x10 16.--17. " SPI[40] ,Interrupt Configuration SPI[40]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x10 14.--15. " SPI[39] ,Interrupt Configuration SPI[39]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x10 12.--13. " SPI[38] ,Interrupt Configuration SPI[38]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x10 10.--11. " SPI[37] ,Interrupt Configuration SPI[37]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x10 8.--9. " SPI[36] ,Interrupt Configuration SPI[36]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x10 6.--7. " SPI[35] ,Interrupt Configuration SPI[35]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x10 4.--5. " SPI[34] ,Interrupt Configuration SPI[34]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x10 2.--3. " SPI[33] ,Interrupt Configuration SPI[33]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " SPI[32] ,Interrupt Configuration SPI[32]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
line.long 0x14 "GICD_ICFGR5,Interrupt Configuration SPI[63:48] Register"
|
|
bitfld.long 0x14 30.--31. " SPI[63] ,Interrupt Configuration SPI[63]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x14 28.--29. " SPI[62] ,Interrupt Configuration SPI[62]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x14 26.--27. " SPI[61] ,Interrupt Configuration SPI[61]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x14 24.--25. " SPI[60] ,Interrupt Configuration SPI[60]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x14 20.--21. " SPI[58] ,Interrupt Configuration SPI[58]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x14 18.--19. " SPI[57] ,Interrupt Configuration SPI[57]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x14 14.--15. " SPI[55] ,Interrupt Configuration SPI[55]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x14 12.--13. " SPI[54] ,Interrupt Configuration SPI[54]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x14 8.--9. " SPI[52] ,Interrupt Configuration SPI[52]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x14 6.--7. " SPI[51] ,Interrupt Configuration SPI[51]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x14 4.--5. " SPI[50] ,Interrupt Configuration SPI[50]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x14 2.--3. " SPI[49] ,Interrupt Configuration SPI[49]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
line.long 0x18 "GICD_ICFGR6,Interrupt Configuration SPI[79:64] Register"
|
|
bitfld.long 0x18 30.--31. " SPI[79] ,Interrupt Configuration SPI[79]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x18 28.--29. " SPI[78] ,Interrupt Configuration SPI[78]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x18 26.--27. " SPI[77] ,Interrupt Configuration SPI[77]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x18 24.--25. " SPI[76] ,Interrupt Configuration SPI[76]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x18 22.--23. " SPI[75] ,Interrupt Configuration SPI[75]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x18 20.--21. " SPI[74] ,Interrupt Configuration SPI[74]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x18 18.--19. " SPI[73] ,Interrupt Configuration SPI[73]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x18 16.--17. " SPI[72] ,Interrupt Configuration SPI[72]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x18 14.--15. " SPI[71] ,Interrupt Configuration SPI[71]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x18 10.--11. " SPI[69] ,Interrupt Configuration SPI[69]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x18 8.--9. " SPI[68] ,Interrupt Configuration SPI[68]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x18 6.--7. " SPI[67] ,Interrupt Configuration SPI[67]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x18 4.--5. " SPI[66] ,Interrupt Configuration SPI[66]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x18 2.--3. " SPI[65] ,Interrupt Configuration SPI[65]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x18 0.--1. " SPI[64] ,Interrupt Configuration SPI[64]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
line.long 0x1C "GICD_ICFGR7,Interrupt Configuration SPI[95:80] Register"
|
|
bitfld.long 0x1C 30.--31. " SPI[95] ,Interrupt Configuration SPI[95]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x1C 28.--29. " SPI[94] ,Interrupt Configuration SPI[94]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x1C 26.--27. " SPI[93] ,Interrupt Configuration SPI[93]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x1C 24.--25. " SPI[92] ,Interrupt Configuration SPI[92]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x1C 22.--23. " SPI[91] ,Interrupt Configuration SPI[91]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x1C 20.--21. " SPI[90] ,Interrupt Configuration SPI[90]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x1C 18.--19. " SPI[89] ,Interrupt Configuration SPI[89]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x1C 16.--17. " SPI[88] ,Interrupt Configuration SPI[88]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x1C 14.--15. " SPI[87] ,Interrupt Configuration SPI[87]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x1C 12.--13. " SPI[86] ,Interrupt Configuration SPI[86]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x1C 10.--11. " SPI[85] ,Interrupt Configuration SPI[85]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x1C 8.--9. " SPI[84] ,Interrupt Configuration SPI[84]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x1C 6.--7. " SPI[83] ,Interrupt Configuration SPI[83]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x1C 4.--5. " SPI[82] ,Interrupt Configuration SPI[82]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x1C 2.--3. " SPI[81] ,Interrupt Configuration SPI[81]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--1. " SPI[80] ,Interrupt Configuration SPI[80]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
line.long 0x20 "GICD_ICFGR8,Interrupt Configuration SPI[111:96] Register"
|
|
bitfld.long 0x20 30.--31. " SPI[111] ,Interrupt Configuration SPI[111]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x20 28.--29. " SPI[110] ,Interrupt Configuration SPI[110]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x20 26.--27. " SPI[109] ,Interrupt Configuration SPI[109]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x20 24.--25. " SPI[108] ,Interrupt Configuration SPI[108]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x20 22.--23. " SPI[107] ,Interrupt Configuration SPI[107]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x20 20.--21. " SPI[106] ,Interrupt Configuration SPI[106]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x20 18.--19. " SPI[105] ,Interrupt Configuration SPI[105]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x20 16.--17. " SPI[104] ,Interrupt Configuration SPI[104]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x20 14.--15. " SPI[103] ,Interrupt Configuration SPI[103]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x20 12.--13. " SPI[102] ,Interrupt Configuration SPI[102]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x20 10.--11. " SPI[101] ,Interrupt Configuration SPI[101]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x20 8.--9. " SPI[100] ,Interrupt Configuration SPI[100]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x20 6.--7. " SPI[99] ,Interrupt Configuration SPI[99]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x20 4.--5. " SPI[98] ,Interrupt Configuration SPI[98]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x20 2.--3. " SPI[97] ,Interrupt Configuration SPI[97]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x20 0.--1. " SPI[96] ,Interrupt Configuration SPI[96]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
line.long 0x24 "GICD_ICFGR9,Interrupt Configuration SPI[127:112] Register"
|
|
bitfld.long 0x24 30.--31. " SPI[127] ,Interrupt Configuration SPI[127]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x24 28.--29. " SPI[126] ,Interrupt Configuration SPI[126]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x24 26.--27. " SPI[125] ,Interrupt Configuration SPI[125]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x24 24.--25. " SPI[124] ,Interrupt Configuration SPI[124]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x24 22.--23. " SPI[123] ,Interrupt Configuration SPI[123]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x24 20.--21. " SPI[122] ,Interrupt Configuration SPI[122]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x24 18.--19. " SPI[121] ,Interrupt Configuration SPI[121]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x24 16.--17. " SPI[120] ,Interrupt Configuration SPI[120]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x24 14.--15. " SPI[119] ,Interrupt Configuration SPI[119]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x24 12.--13. " SPI[118] ,Interrupt Configuration SPI[118]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x24 10.--11. " SPI[117] ,Interrupt Configuration SPI[117]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x24 8.--9. " SPI[116] ,Interrupt Configuration SPI[116]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x24 6.--7. " SPI[115] ,Interrupt Configuration SPI[115]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x24 4.--5. " SPI[114] ,Interrupt Configuration SPI[114]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
bitfld.long 0x24 2.--3. " SPI[113] ,Interrupt Configuration SPI[113]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x24 0.--1. " SPI[112] ,Interrupt Configuration SPI[112]" "N-N software/Level high,1-N software/Level high,N-N software/Rising edge,1-N software/Rising edge"
|
|
tree.end
|
|
tree "Private/Shared Peripheral Interrupt Status Registers"
|
|
width 13.
|
|
rgroup.long 0x1D00++0x03
|
|
line.long 0x00 "GICD_PPISR,PPI Status Register"
|
|
bitfld.long 0x00 15. " PPI_ID31 ,PPI_ID31 Status" "Low,High"
|
|
bitfld.long 0x00 14. " PPI_ID30 ,PPI_ID30 Status" "Low,High"
|
|
bitfld.long 0x00 13. " PPI_ID29 ,PPI_ID29 Status" "Low,High"
|
|
bitfld.long 0x00 12. " PPI_ID28 ,PPI_ID28 Status" "Low,High"
|
|
bitfld.long 0x00 11. " PPI_ID27 ,PPI_ID27 Status" "Low,High"
|
|
bitfld.long 0x00 10. " PPI_ID26 ,PPI_ID26 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PPI_ID25 ,PPI_ID25 Status" "Low,High"
|
|
bitfld.long 0x00 8. " PPI_ID24 ,PPI_ID24 Status" "Low,High"
|
|
bitfld.long 0x00 7. " PPI_ID23 ,PPI_ID23 Status" "Low,High"
|
|
bitfld.long 0x00 6. " PPI_ID22 ,PPI_ID22 Status" "Low,High"
|
|
bitfld.long 0x00 5. " PPI_ID21 ,PPI_ID21 Status" "Low,High"
|
|
bitfld.long 0x00 4. " PPI_ID20 ,PPI_ID20 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PPI_ID19 ,PPI_ID19 Status" "Low,High"
|
|
bitfld.long 0x00 2. " PPI_ID18 ,PPI_ID18 Status" "Low,High"
|
|
bitfld.long 0x00 1. " PPI_ID17 ,PPI_ID17 Status" "Low,High"
|
|
bitfld.long 0x00 0. " PPI_ID16 ,PPI_ID16 Status" "Low,High"
|
|
rgroup.long 0x1D04++0x0F
|
|
line.long 0x00 "GICD_SPISR0,SPI[31:0] Status Register"
|
|
bitfld.long 0x00 31. " SPI_ID31 ,SPI_ID31 Status" "Low,High"
|
|
bitfld.long 0x00 30. " SPI_ID30 ,SPI_ID30 Status" "Low,High"
|
|
bitfld.long 0x00 29. " SPI_ID29 ,SPI_ID29 Status" "Low,High"
|
|
bitfld.long 0x00 28. " SPI_ID28 ,SPI_ID28 Status" "Low,High"
|
|
bitfld.long 0x00 27. " SPI_ID27 ,SPI_ID27 Status" "Low,High"
|
|
bitfld.long 0x00 26. " SPI_ID26 ,SPI_ID26 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPI_ID25 ,SPI_ID25 Status" "Low,High"
|
|
bitfld.long 0x00 24. " SPI_ID24 ,SPI_ID24 Status" "Low,High"
|
|
bitfld.long 0x00 23. " SPI_ID23 ,SPI_ID23 Status" "Low,High"
|
|
bitfld.long 0x00 22. " SPI_ID22 ,SPI_ID22 Status" "Low,High"
|
|
bitfld.long 0x00 21. " SPI_ID21 ,SPI_ID21 Status" "Low,High"
|
|
bitfld.long 0x00 20. " SPI_ID20 ,SPI_ID20 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SPI_ID19 ,SPI_ID19 Status" "Low,High"
|
|
bitfld.long 0x00 18. " SPI_ID18 ,SPI_ID18 Status" "Low,High"
|
|
bitfld.long 0x00 17. " SPI_ID17 ,SPI_ID17 Status" "Low,High"
|
|
bitfld.long 0x00 16. " SPI_ID16 ,SPI_ID16 Status" "Low,High"
|
|
bitfld.long 0x00 15. " SPI_ID15 ,SPI_ID15 Status" "Low,High"
|
|
bitfld.long 0x00 14. " SPI_ID14 ,SPI_ID14 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SPI_ID13 ,SPI_ID13 Status" "Low,High"
|
|
bitfld.long 0x00 12. " SPI_ID12 ,SPI_ID12 Status" "Low,High"
|
|
bitfld.long 0x00 11. " SPI_ID11 ,SPI_ID11 Status" "Low,High"
|
|
bitfld.long 0x00 10. " SPI_ID10 ,SPI_ID10 Status" "Low,High"
|
|
bitfld.long 0x00 9. " SPI_ID9 ,SPI_ID9 Status" "Low,High"
|
|
bitfld.long 0x00 8. " SPI_ID8 ,SPI_ID8 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SPI_ID7 ,SPI_ID7 Status" "Low,High"
|
|
bitfld.long 0x00 6. " SPI_ID6 ,SPI_ID6 Status" "Low,High"
|
|
bitfld.long 0x00 5. " SPI_ID5 ,SPI_ID5 Status" "Low,High"
|
|
bitfld.long 0x00 4. " SPI_ID4 ,SPI_ID4 Status" "Low,High"
|
|
bitfld.long 0x00 3. " SPI_ID3 ,SPI_ID3 Status" "Low,High"
|
|
bitfld.long 0x00 2. " SPI_ID2 ,SPI_ID2 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPI_ID1 ,SPI_ID1 Status" "Low,High"
|
|
bitfld.long 0x00 0. " SPI_ID0 ,SPI_ID0 Status" "Low,High"
|
|
line.long 0x04 "GICD_SPISR1,SPI[63:32] Status Register"
|
|
bitfld.long 0x04 31. " SPI_ID63 ,SPI_ID63 Status" "Low,High"
|
|
bitfld.long 0x04 30. " SPI_ID62 ,SPI_ID62 Status" "Low,High"
|
|
bitfld.long 0x04 29. " SPI_ID61 ,SPI_ID61 Status" "Low,High"
|
|
bitfld.long 0x04 28. " SPI_ID60 ,SPI_ID60 Status" "Low,High"
|
|
bitfld.long 0x04 26. " SPI_ID58 ,SPI_ID58 Status" "Low,High"
|
|
bitfld.long 0x04 25. " SPI_ID57 ,SPI_ID57 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 23. " SPI_ID55 ,SPI_ID55 Status" "Low,High"
|
|
bitfld.long 0x04 22. " SPI_ID54 ,SPI_ID54 Status" "Low,High"
|
|
bitfld.long 0x04 20. " SPI_ID52 ,SPI_ID52 Status" "Low,High"
|
|
bitfld.long 0x04 19. " SPI_ID51 ,SPI_ID51 Status" "Low,High"
|
|
bitfld.long 0x04 18. " SPI_ID50 ,SPI_ID50 Status" "Low,High"
|
|
bitfld.long 0x04 17. " SPI_ID49 ,SPI_ID49 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SPI_ID47 ,SPI_ID47 Status" "Low,High"
|
|
bitfld.long 0x04 14. " SPI_ID46 ,SPI_ID46 Status" "Low,High"
|
|
bitfld.long 0x04 13. " SPI_ID45 ,SPI_ID45 Status" "Low,High"
|
|
bitfld.long 0x04 12. " SPI_ID44 ,SPI_ID44 Status" "Low,High"
|
|
bitfld.long 0x04 11. " SPI_ID43 ,SPI_ID43 Status" "Low,High"
|
|
bitfld.long 0x04 10. " SPI_ID42 ,SPI_ID42 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 9. " SPI_ID41 ,SPI_ID41 Status" "Low,High"
|
|
bitfld.long 0x04 8. " SPI_ID40 ,SPI_ID40 Status" "Low,High"
|
|
bitfld.long 0x04 7. " SPI_ID39 ,SPI_ID39 Status" "Low,High"
|
|
bitfld.long 0x04 6. " SPI_ID38 ,SPI_ID38 Status" "Low,High"
|
|
bitfld.long 0x04 5. " SPI_ID37 ,SPI_ID37 Status" "Low,High"
|
|
bitfld.long 0x04 4. " SPI_ID36 ,SPI_ID36 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SPI_ID35 ,SPI_ID35 Status" "Low,High"
|
|
bitfld.long 0x04 2. " SPI_ID34 ,SPI_ID34 Status" "Low,High"
|
|
bitfld.long 0x04 1. " SPI_ID33 ,SPI_ID33 Status" "Low,High"
|
|
bitfld.long 0x04 0. " SPI_ID32 ,SPI_ID32 Status" "Low,High"
|
|
line.long 0x08 "GICD_SPISR2,SPI[95:64] Status Register"
|
|
bitfld.long 0x08 31. " SPI_ID95 ,SPI_ID95 Status" "Low,High"
|
|
bitfld.long 0x08 30. " SPI_ID94 ,SPI_ID94 Status" "Low,High"
|
|
bitfld.long 0x08 29. " SPI_ID93 ,SPI_ID93 Status" "Low,High"
|
|
bitfld.long 0x08 28. " SPI_ID92 ,SPI_ID92 Status" "Low,High"
|
|
bitfld.long 0x08 27. " SPI_ID91 ,SPI_ID91 Status" "Low,High"
|
|
bitfld.long 0x08 26. " SPI_ID90 ,SPI_ID90 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 25. " SPI_ID89 ,SPI_ID89 Status" "Low,High"
|
|
bitfld.long 0x08 24. " SPI_ID88 ,SPI_ID88 Status" "Low,High"
|
|
bitfld.long 0x08 23. " SPI_ID87 ,SPI_ID87 Status" "Low,High"
|
|
bitfld.long 0x08 22. " SPI_ID86 ,SPI_ID86 Status" "Low,High"
|
|
bitfld.long 0x08 21. " SPI_ID85 ,SPI_ID85 Status" "Low,High"
|
|
bitfld.long 0x08 20. " SPI_ID84 ,SPI_ID84 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 19. " SPI_ID83 ,SPI_ID83 Status" "Low,High"
|
|
bitfld.long 0x08 18. " SPI_ID82 ,SPI_ID82 Status" "Low,High"
|
|
bitfld.long 0x08 17. " SPI_ID81 ,SPI_ID81 Status" "Low,High"
|
|
bitfld.long 0x08 16. " SPI_ID80 ,SPI_ID80 Status" "Low,High"
|
|
bitfld.long 0x08 15. " SPI_ID79 ,SPI_ID79 Status" "Low,High"
|
|
bitfld.long 0x08 14. " SPI_ID78 ,SPI_ID78 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 13. " SPI_ID77 ,SPI_ID77 Status" "Low,High"
|
|
bitfld.long 0x08 12. " SPI_ID76 ,SPI_ID76 Status" "Low,High"
|
|
bitfld.long 0x08 11. " SPI_ID75 ,SPI_ID75 Status" "Low,High"
|
|
bitfld.long 0x08 10. " SPI_ID74 ,SPI_ID74 Status" "Low,High"
|
|
bitfld.long 0x08 9. " SPI_ID73 ,SPI_ID73 Status" "Low,High"
|
|
bitfld.long 0x08 8. " SPI_ID72 ,SPI_ID72 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SPI_ID71 ,SPI_ID71 Status" "Low,High"
|
|
bitfld.long 0x08 5. " SPI_ID69 ,SPI_ID69 Status" "Low,High"
|
|
bitfld.long 0x08 4. " SPI_ID68 ,SPI_ID68 Status" "Low,High"
|
|
bitfld.long 0x08 3. " SPI_ID67 ,SPI_ID67 Status" "Low,High"
|
|
bitfld.long 0x08 2. " SPI_ID66 ,SPI_ID66 Status" "Low,High"
|
|
bitfld.long 0x08 1. " SPI_ID65 ,SPI_ID65 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SPI_ID64 ,SPI_ID64 Status" "Low,High"
|
|
line.long 0x0C "GICD_SPISR3,SPI[127:96] Status Register"
|
|
bitfld.long 0x0C 31. " SPI_ID127 ,SPI_ID127 Status" "Low,High"
|
|
bitfld.long 0x0C 30. " SPI_ID126 ,SPI_ID126 Status" "Low,High"
|
|
bitfld.long 0x0C 29. " SPI_ID125 ,SPI_ID125 Status" "Low,High"
|
|
bitfld.long 0x0C 28. " SPI_ID124 ,SPI_ID124 Status" "Low,High"
|
|
bitfld.long 0x0C 27. " SPI_ID123 ,SPI_ID123 Status" "Low,High"
|
|
bitfld.long 0x0C 26. " SPI_ID122 ,SPI_ID122 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " SPI_ID121 ,SPI_ID121 Status" "Low,High"
|
|
bitfld.long 0x0C 24. " SPI_ID120 ,SPI_ID120 Status" "Low,High"
|
|
bitfld.long 0x0C 23. " SPI_ID119 ,SPI_ID119 Status" "Low,High"
|
|
bitfld.long 0x0C 22. " SPI_ID118 ,SPI_ID118 Status" "Low,High"
|
|
bitfld.long 0x0C 21. " SPI_ID117 ,SPI_ID117 Status" "Low,High"
|
|
bitfld.long 0x0C 20. " SPI_ID116 ,SPI_ID116 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " SPI_ID115 ,SPI_ID115 Status" "Low,High"
|
|
bitfld.long 0x0C 18. " SPI_ID114 ,SPI_ID114 Status" "Low,High"
|
|
bitfld.long 0x0C 17. " SPI_ID113 ,SPI_ID113 Status" "Low,High"
|
|
bitfld.long 0x0C 16. " SPI_ID112 ,SPI_ID112 Status" "Low,High"
|
|
bitfld.long 0x0C 15. " SPI_ID111 ,SPI_ID111 Status" "Low,High"
|
|
bitfld.long 0x0C 14. " SPI_ID110 ,SPI_ID110 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " SPI_ID109 ,SPI_ID109 Status" "Low,High"
|
|
bitfld.long 0x0C 12. " SPI_ID108 ,SPI_ID108 Status" "Low,High"
|
|
bitfld.long 0x0C 11. " SPI_ID107 ,SPI_ID107 Status" "Low,High"
|
|
bitfld.long 0x0C 10. " SPI_ID106 ,SPI_ID106 Status" "Low,High"
|
|
bitfld.long 0x0C 9. " SPI_ID105 ,SPI_ID105 Status" "Low,High"
|
|
bitfld.long 0x0C 8. " SPI_ID104 ,SPI_ID104 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " SPI_ID103 ,SPI_ID103 Status" "Low,High"
|
|
bitfld.long 0x0C 6. " SPI_ID102 ,SPI_ID102 Status" "Low,High"
|
|
bitfld.long 0x0C 5. " SPI_ID101 ,SPI_ID101 Status" "Low,High"
|
|
bitfld.long 0x0C 4. " SPI_ID100 ,SPI_ID100 Status" "Low,High"
|
|
bitfld.long 0x0C 3. " SPI_ID99 ,SPI_ID99 Status" "Low,High"
|
|
bitfld.long 0x0C 2. " SPI_ID98 ,SPI_ID98 Status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SPI_ID97 ,SPI_ID97 Status" "Low,High"
|
|
bitfld.long 0x0C 0. " SPI_ID96 ,SPI_ID96 Status" "Low,High"
|
|
tree.end
|
|
width 11.
|
|
wgroup.long 0x1F00++0x03 "Software Generated Interrupt"
|
|
line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
|
|
bitfld.long 0x00 24.--25. " TRG_LIST_FLT ,Distributor SGI processing" "CPUTargetList,All interfaces,Requested only,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPU_TRG_LIST ,CPU Target List"
|
|
bitfld.long 0x00 15. " NSATT ,Security value of the SGI" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SGIINTID ,Interrupt ID of the SGI to forward to the specified CPU interfaces" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree "SGI pending registers"
|
|
width 16.
|
|
group.long 0xF10++0x0F
|
|
line.long 0x00 "GICD_CPENDSGIR0,Clear-pending register 0 for SGI [3:0]"
|
|
bitfld.long 0x00 31. " SGI_CP3_7 ,Clear Pending Bit 3_7 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 30. " SGI_CP3_6 ,Clear Pending Bit 3_6 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 29. " SGI_CP3_5 ,Clear Pending Bit 3_5 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SGI_CP3_4 ,Clear Pending Bit 3_4 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 27. " SGI_CP3_3 ,Clear Pending Bit 3_3 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 26. " SGI_CP3_2 ,Clear Pending Bit 3_2 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SGI_CP3_1 ,Clear Pending Bit 3_1 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 24. " SGI_CP3_0 ,Clear Pending Bit 3_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 23. " SGI_CP2_7 ,Clear Pending Bit 2_7 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SGI_CP2_6 ,Clear Pending Bit 2_6 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 21. " SGI_CP2_5 ,Clear Pending Bit 2_5 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 20. " SGI_CP2_4 ,Clear Pending Bit 2_4 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SGI_CP2_3 ,Clear Pending Bit 2_3 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 18. " SGI_CP2_2 ,Clear Pending Bit 2_2 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 17. " SGI_CP2_1 ,Clear Pending Bit 2_1 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SGI_CP2_0 ,Clear Pending Bit 2_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 15. " SGI_CP1_7 ,Clear Pending Bit 1_7 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 14. " SGI_CP1_6 ,Clear Pending Bit 1_6 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SGI_CP1_5 ,Clear Pending Bit 1_5 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 12. " SGI_CP1_4 ,Clear Pending Bit 1_4 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 11. " SGI_CP1_3 ,Clear Pending Bit 1_3 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SGI_CP1_2 ,Clear Pending Bit 1_2 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 9. " SGI_CP1_1 ,Clear Pending Bit 1_1 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 8. " SGI_CP1_0 ,Clear Pending Bit 1_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SGI_CP0_7 ,Clear Pending Bit 0_7 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 6. " SGI_CP0_6 ,Clear Pending Bit 0_6 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 5. " SGI_CP0_5 ,Clear Pending Bit 0_5 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SGI_CP0_4 ,Clear Pending Bit 0_4 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 3. " SGI_CP0_3 ,Clear Pending Bit 0_3 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 2. " SGI_CP0_2 ,Clear Pending Bit 0_2 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SGI_CP0_1 ,Clear Pending Bit 0_1 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x00 0. " SGI_CP0_0 ,Clear Pending Bit 0_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
line.long 0x04 "GICD_CPENDSGIR1,Clear-pending register 1 for SGI [7:4]"
|
|
bitfld.long 0x04 31. " SGI_CP7_7 ,Clear Pending Bit 7_7 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 30. " SGI_CP7_6 ,Clear Pending Bit 7_6 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 29. " SGI_CP7_5 ,Clear Pending Bit 7_5 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x04 28. " SGI_CP7_4 ,Clear Pending Bit 7_4 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 27. " SGI_CP7_3 ,Clear Pending Bit 7_3 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 26. " SGI_CP7_2 ,Clear Pending Bit 7_2 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x04 25. " SGI_CP7_1 ,Clear Pending Bit 7_1 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 24. " SGI_CP7_0 ,Clear Pending Bit 7_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 23. " SGI_CP6_7 ,Clear Pending Bit 6_7 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SGI_CP6_6 ,Clear Pending Bit 6_6 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 21. " SGI_CP6_5 ,Clear Pending Bit 6_5 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 20. " SGI_CP6_4 ,Clear Pending Bit 6_4 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x04 19. " SGI_CP6_3 ,Clear Pending Bit 6_3 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 18. " SGI_CP6_2 ,Clear Pending Bit 6_2 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 17. " SGI_CP6_1 ,Clear Pending Bit 6_1 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x04 16. " SGI_CP6_0 ,Clear Pending Bit 6_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 15. " SGI_CP5_7 ,Clear Pending Bit 5_7 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 14. " SGI_CP5_6 ,Clear Pending Bit 5_6 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x04 13. " SGI_CP5_5 ,Clear Pending Bit 5_5 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 12. " SGI_CP5_4 ,Clear Pending Bit 5_4 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 11. " SGI_CP5_3 ,Clear Pending Bit 5_3 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x04 10. " SGI_CP5_2 ,Clear Pending Bit 5_2 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 9. " SGI_CP5_1 ,Clear Pending Bit 5_1 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 8. " SGI_CP5_0 ,Clear Pending Bit 5_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SGI_CP4_7 ,Clear Pending Bit 4_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 6. " SGI_CP4_6 ,Clear Pending Bit 4_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 5. " SGI_CP4_5 ,Clear Pending Bit 4_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x04 4. " SGI_CP4_4 ,Clear Pending Bit 4_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 3. " SGI_CP4_3 ,Clear Pending Bit 4_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 2. " SGI_CP4_2 ,Clear Pending Bit 4_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SGI_CP4_1 ,Clear Pending Bit 4_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x04 0. " SGI_CP4_0 ,Clear Pending Bit 4_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
line.long 0x08 "GICD_CPENDSGIR2,Clear-pending register 2 for SGI [11:8]"
|
|
bitfld.long 0x08 31. " SGI_CP11_7 ,Clear Pending Bit 11_7 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 30. " SGI_CP11_6 ,Clear Pending Bit 11_6 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 29. " SGI_CP11_5 ,Clear Pending Bit 11_5 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 28. " SGI_CP11_4 ,Clear Pending Bit 11_4 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 27. " SGI_CP11_3 ,Clear Pending Bit 11_3 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 26. " SGI_CP11_2 ,Clear Pending Bit 11_2 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 25. " SGI_CP11_1 ,Clear Pending Bit 11_1 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 24. " SGI_CP11_0 ,Clear Pending Bit 11_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 23. " SGI_CP10_7 ,Clear Pending Bit 10_7 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 22. " SGI_CP10_6 ,Clear Pending Bit 10_6 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 21. " SGI_CP10_5 ,Clear Pending Bit 10_5 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 20. " SGI_CP10_4 ,Clear Pending Bit 10_4 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 19. " SGI_CP10_3 ,Clear Pending Bit 10_3 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 18. " SGI_CP10_2 ,Clear Pending Bit 10_2 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 17. " SGI_CP10_1 ,Clear Pending Bit 10_1 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 16. " SGI_CP10_0 ,Clear Pending Bit 10_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 15. " SGI_CP9_7 ,Clear Pending Bit 9_7 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 14. " SGI_CP9_6 ,Clear Pending Bit 9_6 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 13. " SGI_CP9_5 ,Clear Pending Bit 9_5 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 12. " SGI_CP9_4 ,Clear Pending Bit 9_4 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 11. " SGI_CP9_3 ,Clear Pending Bit 9_3 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 10. " SGI_CP9_2 ,Clear Pending Bit 9_2 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 9. " SGI_CP9_1 ,Clear Pending Bit 9_1 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 8. " SGI_CP9_0 ,Clear Pending Bit 9_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SGI_CP8_7 ,Clear Pending Bit 8_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 6. " SGI_CP8_6 ,Clear Pending Bit 8_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 5. " SGI_CP8_5 ,Clear Pending Bit 8_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 4. " SGI_CP8_4 ,Clear Pending Bit 8_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 3. " SGI_CP8_3 ,Clear Pending Bit 8_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 2. " SGI_CP8_2 ,Clear Pending Bit 8_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SGI_CP8_1 ,Clear Pending Bit 8_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x08 0. " SGI_CP8_0 ,Clear Pending Bit 8_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
line.long 0x0C "GICD_CPENDSGIR3,Clear-pending register 3 for SGI [15:12]"
|
|
bitfld.long 0x0C 31. " SGI_CP15_7 ,Clear Pending Bit 15_7 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 30. " SGI_CP15_6 ,Clear Pending Bit 15_6 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 29. " SGI_CP15_5 ,Clear Pending Bit 15_5 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " SGI_CP15_4 ,Clear Pending Bit 15_4 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 27. " SGI_CP15_3 ,Clear Pending Bit 15_3 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 26. " SGI_CP15_2 ,Clear Pending Bit 15_2 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " SGI_CP15_1 ,Clear Pending Bit 15_1 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 24. " SGI_CP15_0 ,Clear Pending Bit 15_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 23. " SGI_CP14_7 ,Clear Pending Bit 14_7 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " SGI_CP14_6 ,Clear Pending Bit 14_6 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 21. " SGI_CP14_5 ,Clear Pending Bit 14_5 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 20. " SGI_CP14_4 ,Clear Pending Bit 14_4 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " SGI_CP14_3 ,Clear Pending Bit 14_3 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 18. " SGI_CP14_2 ,Clear Pending Bit 14_2 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 17. " SGI_CP14_1 ,Clear Pending Bit 14_1 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " SGI_CP14_0 ,Clear Pending Bit 14_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 15. " SGI_CP13_7 ,Clear Pending Bit 13_7 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 14. " SGI_CP13_6 ,Clear Pending Bit 13_6 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " SGI_CP13_5 ,Clear Pending Bit 13_5 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 12. " SGI_CP13_4 ,Clear Pending Bit 13_4 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 11. " SGI_CP13_3 ,Clear Pending Bit 13_3 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " SGI_CP13_2 ,Clear Pending Bit 13_2 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 9. " SGI_CP13_1 ,Clear Pending Bit 13_1 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 8. " SGI_CP13_0 ,Clear Pending Bit 13_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " SGI_CP12_7 ,Clear Pending Bit 12_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 6. " SGI_CP12_6 ,Clear Pending Bit 12_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 5. " SGI_CP12_5 ,Clear Pending Bit 12_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " SGI_CP12_4 ,Clear Pending Bit 12_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 3. " SGI_CP12_3 ,Clear Pending Bit 12_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 2. " SGI_CP12_2 ,Clear Pending Bit 12_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SGI_CP12_1 ,Clear Pending Bit 12_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
bitfld.long 0x0C 0. " SGI_CP12_0 ,Clear Pending Bit 12_0 [read/write]" "Not pending/No effect,Pending/Clear"
|
|
textline ""
|
|
group.long 0xF20++0x0F
|
|
line.long 0x00 "GICD_SPENDSGIR0,Set-Pending register 0 for SGI [3:0]"
|
|
bitfld.long 0x00 31. " SGI_CP3_7 ,Set Pending Bit 3_7" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SGI_CP3_6 ,Set Pending Bit 3_6" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " SGI_CP3_5 ,Set Pending Bit 3_5" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SGI_CP3_4 ,Set Pending Bit 3_4" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " SGI_CP3_3 ,Set Pending Bit 3_3" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " SGI_CP3_2 ,Set Pending Bit 3_2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SGI_CP3_1 ,Set Pending Bit 3_1" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " SGI_CP3_0 ,Set Pending Bit 3_0" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " SGI_CP2_7 ,Set Pending Bit 2_7" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SGI_CP2_6 ,Set Pending Bit 2_6" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SGI_CP2_5 ,Set Pending Bit 2_5" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " SGI_CP2_4 ,Set Pending Bit 2_4" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SGI_CP2_3 ,Set Pending Bit 2_3" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " SGI_CP2_2 ,Set Pending Bit 2_2" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " SGI_CP2_1 ,Set Pending Bit 2_1" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SGI_CP2_0 ,Set Pending Bit 2_0" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " SGI_CP1_7 ,Set Pending Bit 1_7" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " SGI_CP1_6 ,Set Pending Bit 1_6" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SGI_CP1_5 ,Set Pending Bit 1_5" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " SGI_CP1_4 ,Set Pending Bit 1_4" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " SGI_CP1_3 ,Set Pending Bit 1_3" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SGI_CP1_2 ,Set Pending Bit 1_2" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " SGI_CP1_1 ,Set Pending Bit 1_1" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " SGI_CP1_0 ,Set Pending Bit 1_0" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SGI_CP0_7 ,Set Pending Bit 0_7" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " SGI_CP0_6 ,Set Pending Bit 0_6" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " SGI_CP0_5 ,Set Pending Bit 0_5" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SGI_CP0_4 ,Set Pending Bit 0_4" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " SGI_CP0_3 ,Set Pending Bit 0_3" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SGI_CP0_2 ,Set Pending Bit 0_2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SGI_CP0_1 ,Set Pending Bit 0_1" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SGI_CP0_0 ,Set Pending Bit 0_0" "Not pending,Pending"
|
|
line.long 0x04 "GICD_SPENDSGIR1,Set-Pending register 1 for SGI [7:4]"
|
|
bitfld.long 0x04 31. " SGI_CP7_7 ,Set Pending Bit 7_7" "Not pending,Pending"
|
|
bitfld.long 0x04 30. " SGI_CP7_6 ,Set Pending Bit 7_6" "Not pending,Pending"
|
|
bitfld.long 0x04 29. " SGI_CP7_5 ,Set Pending Bit 7_5" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 28. " SGI_CP7_4 ,Set Pending Bit 7_4" "Not pending,Pending"
|
|
bitfld.long 0x04 27. " SGI_CP7_3 ,Set Pending Bit 7_3" "Not pending,Pending"
|
|
bitfld.long 0x04 26. " SGI_CP7_2 ,Set Pending Bit 7_2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 25. " SGI_CP7_1 ,Set Pending Bit 7_1" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " SGI_CP7_0 ,Set Pending Bit 7_0" "Not pending,Pending"
|
|
bitfld.long 0x04 23. " SGI_CP6_7 ,Set Pending Bit 6_7" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SGI_CP6_6 ,Set Pending Bit 6_6" "Not pending,Pending"
|
|
bitfld.long 0x04 21. " SGI_CP6_5 ,Set Pending Bit 6_5" "Not pending,Pending"
|
|
bitfld.long 0x04 20. " SGI_CP6_4 ,Set Pending Bit 6_4" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 19. " SGI_CP6_3 ,Set Pending Bit 6_3" "Not pending,Pending"
|
|
bitfld.long 0x04 18. " SGI_CP6_2 ,Set Pending Bit 6_2" "Not pending,Pending"
|
|
bitfld.long 0x04 17. " SGI_CP6_1 ,Set Pending Bit 6_1" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 16. " SGI_CP6_0 ,Set Pending Bit 6_0" "Not pending,Pending"
|
|
bitfld.long 0x04 15. " SGI_CP5_7 ,Set Pending Bit 5_7" "Not pending,Pending"
|
|
bitfld.long 0x04 14. " SGI_CP5_6 ,Set Pending Bit 5_6" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 13. " SGI_CP5_5 ,Set Pending Bit 5_5" "Not pending,Pending"
|
|
bitfld.long 0x04 12. " SGI_CP5_4 ,Set Pending Bit 5_4" "Not pending,Pending"
|
|
bitfld.long 0x04 11. " SGI_CP5_3 ,Set Pending Bit 5_3" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 10. " SGI_CP5_2 ,Set Pending Bit 5_2" "Not pending,Pending"
|
|
bitfld.long 0x04 9. " SGI_CP5_1 ,Set Pending Bit 5_1" "Not pending,Pending"
|
|
bitfld.long 0x04 8. " SGI_CP5_0 ,Set Pending Bit 5_0" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SGI_CP4_7 ,Set Pending Bit 4_0" "Not pending,Pending"
|
|
bitfld.long 0x04 6. " SGI_CP4_6 ,Set Pending Bit 4_0" "Not pending,Pending"
|
|
bitfld.long 0x04 5. " SGI_CP4_5 ,Set Pending Bit 4_0" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 4. " SGI_CP4_4 ,Set Pending Bit 4_0" "Not pending,Pending"
|
|
bitfld.long 0x04 3. " SGI_CP4_3 ,Set Pending Bit 4_0" "Not pending,Pending"
|
|
bitfld.long 0x04 2. " SGI_CP4_2 ,Set Pending Bit 4_0" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SGI_CP4_1 ,Set Pending Bit 4_0" "Not pending,Pending"
|
|
bitfld.long 0x04 0. " SGI_CP4_0 ,Set Pending Bit 4_0" "Not pending,Pending"
|
|
line.long 0x08 "GICD_SPENDSGIR2,Set-Pending register 2 for SGI [11:8]"
|
|
bitfld.long 0x08 31. " SGI_CP11_7 ,Set Pending Bit 11_7" "Not pending,Pending"
|
|
bitfld.long 0x08 30. " SGI_CP11_6 ,Set Pending Bit 11_6" "Not pending,Pending"
|
|
bitfld.long 0x08 29. " SGI_CP11_5 ,Set Pending Bit 11_5" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 28. " SGI_CP11_4 ,Set Pending Bit 11_4" "Not pending,Pending"
|
|
bitfld.long 0x08 27. " SGI_CP11_3 ,Set Pending Bit 11_3" "Not pending,Pending"
|
|
bitfld.long 0x08 26. " SGI_CP11_2 ,Set Pending Bit 11_2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 25. " SGI_CP11_1 ,Set Pending Bit 11_1" "Not pending,Pending"
|
|
bitfld.long 0x08 24. " SGI_CP11_0 ,Set Pending Bit 11_0" "Not pending,Pending"
|
|
bitfld.long 0x08 23. " SGI_CP10_7 ,Set Pending Bit 10_7" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 22. " SGI_CP10_6 ,Set Pending Bit 10_6" "Not pending,Pending"
|
|
bitfld.long 0x08 21. " SGI_CP10_5 ,Set Pending Bit 10_5" "Not pending,Pending"
|
|
bitfld.long 0x08 20. " SGI_CP10_4 ,Set Pending Bit 10_4" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 19. " SGI_CP10_3 ,Set Pending Bit 10_3" "Not pending,Pending"
|
|
bitfld.long 0x08 18. " SGI_CP10_2 ,Set Pending Bit 10_2" "Not pending,Pending"
|
|
bitfld.long 0x08 17. " SGI_CP10_1 ,Set Pending Bit 10_1" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 16. " SGI_CP10_0 ,Set Pending Bit 10_0" "Not pending,Pending"
|
|
bitfld.long 0x08 15. " SGI_CP9_7 ,Set Pending Bit 9_7" "Not pending,Pending"
|
|
bitfld.long 0x08 14. " SGI_CP9_6 ,Set Pending Bit 9_6" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 13. " SGI_CP9_5 ,Set Pending Bit 9_5" "Not pending,Pending"
|
|
bitfld.long 0x08 12. " SGI_CP9_4 ,Set Pending Bit 9_4" "Not pending,Pending"
|
|
bitfld.long 0x08 11. " SGI_CP9_3 ,Set Pending Bit 9_3" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 10. " SGI_CP9_2 ,Set Pending Bit 9_2" "Not pending,Pending"
|
|
bitfld.long 0x08 9. " SGI_CP9_1 ,Set Pending Bit 9_1" "Not pending,Pending"
|
|
bitfld.long 0x08 8. " SGI_CP9_0 ,Set Pending Bit 9_0" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SGI_CP8_7 ,Set Pending Bit 8_0" "Not pending,Pending"
|
|
bitfld.long 0x08 6. " SGI_CP8_6 ,Set Pending Bit 8_0" "Not pending,Pending"
|
|
bitfld.long 0x08 5. " SGI_CP8_5 ,Set Pending Bit 8_0" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 4. " SGI_CP8_4 ,Set Pending Bit 8_0" "Not pending,Pending"
|
|
bitfld.long 0x08 3. " SGI_CP8_3 ,Set Pending Bit 8_0" "Not pending,Pending"
|
|
bitfld.long 0x08 2. " SGI_CP8_2 ,Set Pending Bit 8_0" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SGI_CP8_1 ,Set Pending Bit 8_0" "Not pending,Pending"
|
|
bitfld.long 0x08 0. " SGI_CP8_0 ,Set Pending Bit 8_0" "Not pending,Pending"
|
|
line.long 0x0C "GICD_SPENDSGIR3,Set-Pending register 3 for SGI [15:12]"
|
|
bitfld.long 0x0C 31. " SGI_CP15_7 ,Set Pending Bit 15_7" "Not pending,Pending"
|
|
bitfld.long 0x0C 30. " SGI_CP15_6 ,Set Pending Bit 15_6" "Not pending,Pending"
|
|
bitfld.long 0x0C 29. " SGI_CP15_5 ,Set Pending Bit 15_5" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " SGI_CP15_4 ,Set Pending Bit 15_4" "Not pending,Pending"
|
|
bitfld.long 0x0C 27. " SGI_CP15_3 ,Set Pending Bit 15_3" "Not pending,Pending"
|
|
bitfld.long 0x0C 26. " SGI_CP15_2 ,Set Pending Bit 15_2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " SGI_CP15_1 ,Set Pending Bit 15_1" "Not pending,Pending"
|
|
bitfld.long 0x0C 24. " SGI_CP15_0 ,Set Pending Bit 15_0" "Not pending,Pending"
|
|
bitfld.long 0x0C 23. " SGI_CP14_7 ,Set Pending Bit 14_7" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " SGI_CP14_6 ,Set Pending Bit 14_6" "Not pending,Pending"
|
|
bitfld.long 0x0C 21. " SGI_CP14_5 ,Set Pending Bit 14_5" "Not pending,Pending"
|
|
bitfld.long 0x0C 20. " SGI_CP14_4 ,Set Pending Bit 14_4" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " SGI_CP14_3 ,Set Pending Bit 14_3" "Not pending,Pending"
|
|
bitfld.long 0x0C 18. " SGI_CP14_2 ,Set Pending Bit 14_2" "Not pending,Pending"
|
|
bitfld.long 0x0C 17. " SGI_CP14_1 ,Set Pending Bit 14_1" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " SGI_CP14_0 ,Set Pending Bit 14_0" "Not pending,Pending"
|
|
bitfld.long 0x0C 15. " SGI_CP13_7 ,Set Pending Bit 13_7" "Not pending,Pending"
|
|
bitfld.long 0x0C 14. " SGI_CP13_6 ,Set Pending Bit 13_6" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " SGI_CP13_5 ,Set Pending Bit 13_5" "Not pending,Pending"
|
|
bitfld.long 0x0C 12. " SGI_CP13_4 ,Set Pending Bit 13_4" "Not pending,Pending"
|
|
bitfld.long 0x0C 11. " SGI_CP13_3 ,Set Pending Bit 13_3" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " SGI_CP13_2 ,Set Pending Bit 13_2" "Not pending,Pending"
|
|
bitfld.long 0x0C 9. " SGI_CP13_1 ,Set Pending Bit 13_1" "Not pending,Pending"
|
|
bitfld.long 0x0C 8. " SGI_CP13_0 ,Set Pending Bit 13_0" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " SGI_CP12_7 ,Set Pending Bit 12_0" "Not pending,Pending"
|
|
bitfld.long 0x0C 6. " SGI_CP12_6 ,Set Pending Bit 12_0" "Not pending,Pending"
|
|
bitfld.long 0x0C 5. " SGI_CP12_5 ,Set Pending Bit 12_0" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " SGI_CP12_4 ,Set Pending Bit 12_0" "Not pending,Pending"
|
|
bitfld.long 0x0C 3. " SGI_CP12_3 ,Set Pending Bit 12_0" "Not pending,Pending"
|
|
bitfld.long 0x0C 2. " SGI_CP12_2 ,Set Pending Bit 12_0" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SGI_CP12_1 ,Set Pending Bit 12_0" "Not pending,Pending"
|
|
bitfld.long 0x0C 0. " SGI_CP12_0 ,Set Pending Bit 12_0" "Not pending,Pending"
|
|
tree.end
|
|
tree "ID registers"
|
|
width 12.
|
|
rgroup.long 0x1FD0++0x03
|
|
line.long 0x00 "GICD_PIDR4,Peripheral ID 4 register"
|
|
bitfld.long 0x00 0.--3. " PIDR4 ,ARM-defined revision field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long 0x1FD4++0x0B
|
|
hide.long 0x00 "GICD_PIDR5,Peripheral ID 5 register"
|
|
hide.long 0x04 "GICD_PIDR6,Peripheral ID 6 register"
|
|
hide.long 0x08 "GICD_PIDR7,Peripheral ID 7 register"
|
|
rgroup.long 0x1FE0++0x0F
|
|
line.long 0x00 "GICD_PIDR0,Peripheral ID 0 register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PIDR0 ,ARM-defined DevID field"
|
|
line.long 0x04 "GICD_PIDR1,Peripheral ID 1 register"
|
|
bitfld.long 0x04 4.--7. " PIDR1_ARC ,ARM-defined ArchID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " PIDR1_DEV ,ARM-defined DevID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "GICD_PIDR2,Peripheral ID 2 register"
|
|
bitfld.long 0x08 4.--7. " PIDR2_ARCR ,ArchRev field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 3. " PIDR2_JEP ,ARM-defined UsesJEPcode field" "0,1"
|
|
bitfld.long 0x08 0.--2. " PIDR_ARC ,ARM-defined ArchID field" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "GICD_PIDR3,Peripheral ID 3 register"
|
|
bitfld.long 0x0C 4.--7. " PIDR3_REV ,ARM-defined revision field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1FF0++0x0F
|
|
line.long 0x0 "GICD_CIDR0,Component ID 0 register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CIDR0 ,ARM-defined fixed values for the preamble for the component discovery"
|
|
line.long 0x4 "GICD_CIDR1,Component ID 1 register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CIDR1 ,ARM-defined fixed values for the preamble for the component discovery"
|
|
line.long 0x8 "GICD_CIDR2,Component ID 2 register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CIDR2 ,ARM-defined fixed values for the preamble for the component discovery"
|
|
line.long 0xC "GICD_CIDR3,Component ID 3 register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CIDR3 ,ARM-defined fixed values for the preamble for the component discovery"
|
|
tree.end
|
|
tree.end
|
|
tree "Virtual Interface Control"
|
|
width 13.
|
|
base ad:0x50044000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GICH_HCR,Hypervisor control register"
|
|
bitfld.long 0x00 27.--31. " EOICOUNT ,Number of EOIs received without entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " VGRP1DIE ,VM disable group 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VGRP1EIE ,VM enable group 1 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VGRP0DIE ,VM disable group 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VGRP0EIE ,VM enable group 0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NPIE ,No pending interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LRENPIE ,List register entry not present interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UIE ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Virtual CPU interface enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "GICH_VTR,VGIC Type Register"
|
|
bitfld.long 0x00 29.--31. " PRIBITS ,Number of priority bits" ",,,,5 bits 32 PRI levels,?..."
|
|
bitfld.long 0x00 26.--28. " PREBITS ,Number of pre-emption bits" ",,,,5 bits 32 PRE levels,?..."
|
|
bitfld.long 0x00 0.--5. " LSITREGS ,Number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GICH_VMCR,Virtual machine control register"
|
|
bitfld.long 0x00 27.--31. " VMPRIMASK ,Virtual interrupt priority filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21.--23. " VMBP ,VM binary point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. " VMABP ,VM aliased binary point" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VEM ,GICV_EOIR/GICV_AEOIR and GICV_DIR behaviour control" "0,1"
|
|
bitfld.long 0x00 4. " VMCBPR ,GICV_BPR group control" "Group 0,Group 0 and 1"
|
|
bitfld.long 0x00 3. " VMFIQEN ,Group 0 interrupts control" "Virtual IRQs,Virtual FIQs"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VMACKCTL ,CPU interrupt acknowledgement" "0,1"
|
|
bitfld.long 0x00 1. " VMGRP1EN ,Group 1 virtual interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VMGRP0EN ,Group 0 virtual interrupts enable" "Disabled,Enabled"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GICH_MISR,Maintenance interrupt status register"
|
|
bitfld.long 0x00 7. " VGR1D ,Disabled group 1 maintenance interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VGR1E ,Enabled group 1 maintenance interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VGR0D ,Disabled group 0 maintenance interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VGR0E ,Enabled group 0 maintenance interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NP ,No pending maintenance interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LRENP ,List register entry not present maintenance interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " U ,Underflow maintenance interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EOI ,EOI maintenance interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "GICH_EISR0,End of interrupt status register"
|
|
bitfld.long 0x00 31. " REG31 ,List register EOI status bit 31" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 30. " REG30 ,List register EOI status bit 30" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 29. " REG29 ,List register EOI status bit 29" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 28. " REG28 ,List register EOI status bit 28" "Has no EOI,Has EOI"
|
|
textline " "
|
|
bitfld.long 0x00 27. " REG27 ,List register EOI status bit 27" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 26. " REG26 ,List register EOI status bit 26" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 25. " REG25 ,List register EOI status bit 25" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 24. " REG24 ,List register EOI status bit 24" "Has no EOI,Has EOI"
|
|
textline " "
|
|
bitfld.long 0x00 23. " REG23 ,List register EOI status bit 23" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 22. " REG22 ,List register EOI status bit 22" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 21. " REG21 ,List register EOI status bit 21" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 20. " REG20 ,List register EOI status bit 20" "Has no EOI,Has EOI"
|
|
textline " "
|
|
bitfld.long 0x00 19. " REG19 ,List register EOI status bit 19" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 18. " REG18 ,List register EOI status bit 18" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 17. " REG17 ,List register EOI status bit 17" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 16. " REG16 ,List register EOI status bit 16" "Has no EOI,Has EOI"
|
|
textline " "
|
|
bitfld.long 0x00 15. " REG15 ,List register EOI status bit 15" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 14. " REG14 ,List register EOI status bit 14" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 13. " REG13 ,List register EOI status bit 13" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 12. " REG12 ,List register EOI status bit 12" "Has no EOI,Has EOI"
|
|
textline " "
|
|
bitfld.long 0x00 11. " REG11 ,List register EOI status bit 11" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 10. " REG10 ,List register EOI status bit 10" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 9. " REG9 ,List register EOI status bit 9" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 8. " REG8 ,List register EOI status bit 8" "Has no EOI,Has EOI"
|
|
textline " "
|
|
bitfld.long 0x00 7. " REG7 ,List register EOI status bit 7" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 6. " REG6 ,List register EOI status bit 6" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 5. " REG5 ,List register EOI status bit 5" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 4. " REG4 ,List register EOI status bit 4" "Has no EOI,Has EOI"
|
|
textline " "
|
|
bitfld.long 0x00 3. " REG3 ,List register EOI status bit 3" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 2. " REG2 ,List register EOI status bit 2" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 1. " REG1 ,List register EOI status bit 1" "Has no EOI,Has EOI"
|
|
bitfld.long 0x00 0. " REG0 ,List register EOI status bit 0" "Has no EOI,Has EOI"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "GICH_ELSER0,Empty list register status register"
|
|
bitfld.long 0x00 31. " REG31 ,List register status bit 31" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 30. " REG30 ,List register status bit 30" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 29. " REG29 ,List register status bit 29" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 28. " REG28 ,List register status bit 28" "Has interrupt,Has no interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " REG27 ,List register status bit 27" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 26. " REG26 ,List register status bit 26" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 25. " REG25 ,List register status bit 25" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 24. " REG24 ,List register status bit 24" "Has interrupt,Has no interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " REG23 ,List register status bit 23" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 22. " REG22 ,List register status bit 22" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 21. " REG21 ,List register status bit 21" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 20. " REG20 ,List register status bit 20" "Has interrupt,Has no interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " REG19 ,List register status bit 19" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 18. " REG18 ,List register status bit 18" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 17. " REG17 ,List register status bit 17" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 16. " REG16 ,List register status bit 16" "Has interrupt,Has no interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " REG15 ,List register status bit 15" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 14. " REG14 ,List register status bit 14" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 13. " REG13 ,List register status bit 13" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 12. " REG12 ,List register status bit 12" "Has interrupt,Has no interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " REG11 ,List register status bit 11" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 10. " REG10 ,List register status bit 10" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 9. " REG9 ,List register status bit 9" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 8. " REG8 ,List register status bit 8" "Has interrupt,Has no interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " REG7 ,List register status bit 7" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 6. " REG6 ,List register status bit 6" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 5. " REG5 ,List register status bit 5" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 4. " REG4 ,List register status bit 4" "Has interrupt,Has no interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " REG3 ,List register status bit 3" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 2. " REG2 ,List register status bit 2" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 1. " REG1 ,List register status bit 1" "Has interrupt,Has no interrupt"
|
|
bitfld.long 0x00 0. " REG0 ,List register status bit 0" "Has interrupt,Has no interrupt"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "GICH_APR0,Active priority register"
|
|
bitfld.long 0x00 31. " APR31 ,Bit31 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 30. " APR30 ,Bit30 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 29. " APR29 ,Bit29 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 28. " APR28 ,Bit28 preemption level activation" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 27. " APR27 ,Bit27 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 26. " APR26 ,Bit26 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 25. " APR25 ,Bit25 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 24. " APR24 ,Bit24 preemption level activation" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " APR23 ,Bit23 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 22. " APR22 ,Bit22 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 21. " APR21 ,Bit21 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 20. " APR20 ,Bit20 preemption level activation" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " APR19 ,Bit19 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 18. " APR18 ,Bit18 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 17. " APR17 ,Bit17 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 16. " APR16 ,Bit16 preemption level activation" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " APR15 ,Bit15 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 14. " APR14 ,Bit14 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 13. " APR13 ,Bit13 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 12. " APR12 ,Bit12 preemption level activation" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " APR11 ,Bit11 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 10. " APR10 ,Bit10 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 9. " APR9 ,Bit9 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 8. " APR8 ,Bit8 preemption level activation" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " APR7 ,Bit7 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 6. " APR6 ,Bit6 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 5. " APR5 ,Bit5 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 4. " APR4 ,Bit4 preemption level activation" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " APR3 ,Bit3 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 2. " APR2 ,Bit2 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 1. " APR1 ,Bit1 preemption level activation" "Not active,Active"
|
|
bitfld.long 0x00 0. " APR0 ,Bit0 preemption level activation" "Not active,Active"
|
|
if (((d.l(ad:0x50044000+0x100))&0x80000000)==0x00000000)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "GICH_LR0,List register 0"
|
|
bitfld.long 0x00 31. " HW ,Virtual interrupt hardware/software mode" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GRP1 ,Group virtual interrupt switch" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,State of interrupt" "Invalid,Pending,Active,Pending and active"
|
|
textline " "
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19. " EOI ,EOI maintenance interrupt trigger" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,VirtualID for CPU interface"
|
|
else
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "GICH_LR0,List register 0"
|
|
bitfld.long 0x00 31. " HW ,Virtual interrupt hardware/software mode" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GRP1 ,Group virtual interrupt switch" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,State of interrupt" "Invalid,Pending,Active,Pending and active"
|
|
textline " "
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Physical interrupt ID"
|
|
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,VirtualID for CPU interface"
|
|
endif
|
|
if (((d.l(ad:0x50044000+0x104))&0x80000000)==0x00000000)
|
|
group.long 0x104++0x0F
|
|
line.long 0x00 "GICH_LR1,List register 1"
|
|
bitfld.long 0x00 31. " HW ,Virtual interrupt hardware/software mode" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GRP1 ,Group virtual interrupt switch" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,State of interrupt" "Invalid,Pending,Active,Pending and active"
|
|
textline " "
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19. " EOI ,EOI maintenance interrupt trigger" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,VirtualID for CPU interface"
|
|
else
|
|
group.long 0x104++0x0F
|
|
line.long 0x00 "GICH_LR1,List register 1"
|
|
bitfld.long 0x00 31. " HW ,Virtual interrupt hardware/software mode" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GRP1 ,Group virtual interrupt switch" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,State of interrupt" "Invalid,Pending,Active,Pending and active"
|
|
textline " "
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Physical interrupt ID"
|
|
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,VirtualID for CPU interface"
|
|
endif
|
|
if (((d.l(ad:0x50044000+0x108))&0x80000000)==0x00000000)
|
|
group.long 0x108++0x0F
|
|
line.long 0x00 "GICH_LR2,List register 2"
|
|
bitfld.long 0x00 31. " HW ,Virtual interrupt hardware/software mode" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GRP1 ,Group virtual interrupt switch" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,State of interrupt" "Invalid,Pending,Active,Pending and active"
|
|
textline " "
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19. " EOI ,EOI maintenance interrupt trigger" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,VirtualID for CPU interface"
|
|
else
|
|
group.long 0x108++0x0F
|
|
line.long 0x00 "GICH_LR2,List register 2"
|
|
bitfld.long 0x00 31. " HW ,Virtual interrupt hardware/software mode" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GRP1 ,Group virtual interrupt switch" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,State of interrupt" "Invalid,Pending,Active,Pending and active"
|
|
textline " "
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Physical interrupt ID"
|
|
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,VirtualID for CPU interface"
|
|
endif
|
|
if (((d.l(ad:0x50044000+0x10C))&0x80000000)==0x00000000)
|
|
group.long 0x10C++0x0F
|
|
line.long 0x00 "GICH_LR3,List register 3"
|
|
bitfld.long 0x00 31. " HW ,Virtual interrupt hardware/software mode" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GRP1 ,Group virtual interrupt switch" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,State of interrupt" "Invalid,Pending,Active,Pending and active"
|
|
textline " "
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19. " EOI ,EOI maintenance interrupt trigger" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,VirtualID for CPU interface"
|
|
else
|
|
group.long 0x10C++0x0F
|
|
line.long 0x00 "GICH_LR3,List register 3"
|
|
bitfld.long 0x00 31. " HW ,Virtual interrupt hardware/software mode" "Software,Hardware"
|
|
bitfld.long 0x00 30. " GRP1 ,Group virtual interrupt switch" "Group 0,Group 1"
|
|
bitfld.long 0x00 28.--29. " STATE ,State of interrupt" "Invalid,Pending,Active,Pending and active"
|
|
textline " "
|
|
bitfld.long 0x00 23.--27. " PRIORITY ,Priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 10.--19. 1. " PHYSICALID ,Physical interrupt ID"
|
|
hexmask.long.word 0x00 0.--9. 1. " VIRTUALID ,VirtualID for CPU interface"
|
|
endif
|
|
tree.end
|
|
width 13.
|
|
tree "Virtual CPU Interface"
|
|
base ad:0x50046000
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "GICV_CTLR,Virtual machine control register"
|
|
bitfld.long 0x00 9. " EOIMODES ,Behaviour of accesses to the GICV_EOIR/GICV_AEOIR and GICV_DIR registers" "Priority drop/Deactivate interrupt,Priority drop only"
|
|
bitfld.long 0x00 4. " CBPR ,Group interrupts control" "BPR and ABPR,BPR"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FIQEN ,Group 0 interrupts signal control" "IRQ,FIQ"
|
|
bitfld.long 0x00 2. " ACKCTL ,GICV_IAR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENABLEGRP1 ,Enable for signalling interrupts of group 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLEGRP0 ,Enable for signalling interrupts of group 0" "Disabled,Enabled"
|
|
line.long 0x04 "GICV_PMR,VM priority mask register"
|
|
bitfld.long 0x04 3.--7. " PRIORITY ,Virtual interrupt priority filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "GICV_BPR,VM binary point register"
|
|
bitfld.long 0x08 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7"
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "GICV_IAR,Interrupt Acknowledge Register"
|
|
in
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "GICV_EOIR,End Of Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,ACKINTID value from the corresponding GICV_IAR access"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "GICV_RPR,Running Priority Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority virtual interrupt"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "GICV_HPPIR,Highest Pending Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,Interrupt ID of the highest priority pending interrupt"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GICV_ABPR,Aliased Binary Point Register"
|
|
bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "GICV_AIAR,Aliased interrupt acknowledge Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " INTERRUPTID ,Interrupt ID"
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "GICV_AEOIR,Aliased end of Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " INTERRUPTID ,Interrupt ID value from the corresponding GICV_AIAR access"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "GICV_AHPPIR,Aliased Highest Priority Pending Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,Interrupt ID of the highest priority pending interrupt"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "GICV_APR0,Active priority register"
|
|
rgroup.long 0xFC++0x03 "CPU Interface Identification"
|
|
line.long 0x00 "GICV_IIDR,CPU Interface Identification Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " PRODUCTID ,An IMPLEMENTATION DEFINED product identifier"
|
|
bitfld.long 0x00 16.--19. " ARCHIT_VER ,GIC architecture version" ",,GICv2,?..."
|
|
bitfld.long 0x00 12.--15. " REVISION ,An IMPLEMENTATION DEFINED revision number for the CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " IMPLEMENTER ,Contains the JEP106 code of the company"
|
|
wgroup.long 0x1000++0x03 "Interrupt Deactivation"
|
|
line.long 0x00 "GICV_DIR,Deactivate Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " INTERRUPTID ,Interrupt ID"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "Semaphores"
|
|
tree "Arbitration Semaphores"
|
|
base ad:0x60002000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SMP_GNT_ST_0,Semaphore granted status register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " ARB_31 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " ARB_30 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " ARB_29 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " ARB_28 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " ARB_27 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " ARB_26 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " ARB_25 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " ARB_24 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " ARB_23 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " ARB_22 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " ARB_21 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " ARB_20 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " ARB_19 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " ARB_18 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " ARB_17 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " ARB_16 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " ARB_15 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " ARB_14 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " ARB_13 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " ARB_12 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " ARB_11 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " ARB_10 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " ARB_9 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " ARB_8 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " ARB_7 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " ARB_6 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " ARB_5 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " ARB_4 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " ARB_3 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " ARB_2 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " ARB_1 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " ARB_0 ,Semaphore granted status for processor" "Not granted,Granted"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SMP_REQ_ST_0,Arbitration request pending status register"
|
|
bitfld.long 0x00 31. " REQ_31 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " REQ_30 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " REQ_29 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " REQ_28 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " REQ_27 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " REQ_26 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " REQ_25 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " REQ_24 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 23. " REQ_23 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " REQ_22 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " REQ_21 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " REQ_20 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " REQ_19 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " REQ_18 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " REQ_17 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " REQ_16 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 15. " REQ_15 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " REQ_14 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " REQ_13 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " REQ_12 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " REQ_11 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " REQ_10 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " REQ_9 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " REQ_8 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " REQ_7 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " REQ_6 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " REQ_5 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " REQ_4 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " REQ_3 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " REQ_2 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " REQ_1 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " REQ_0 ,Corresponding bit request pending status" "Not pending,Pending"
|
|
width 0xb
|
|
tree.end
|
|
tree "Resource Semaphores"
|
|
base ad:0x60001000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SMP_STA_0,Shared resource semaphore status register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " SMP_31 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " SMP_30 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " SMP_29 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " SMP_28 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " SMP_27 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " SMP_26 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " SMP_25 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " SMP_24 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " SMP_23 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " SMP_22 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " SMP_21 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " SMP_20 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " SMP_19 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " SMP_18 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " SMP_17 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " SMP_16 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " SMP_15 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " SMP_14 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " SMP_13 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " SMP_12 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SMP_11 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " SMP_10 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " SMP_9 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " SMP_8 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SMP_7 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " SMP_6 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SMP_5 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " SMP_4 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " SMP_3 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " SMP_2 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SMP_1 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SMP_0 ,Shared resource semaphore status bit" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "INBOX_0,Shared resource inbox"
|
|
bitfld.long 0x00 31. " IE_IBF ,Interrupt CPU on INBOX Full" "Empty,Full"
|
|
bitfld.long 0x00 30. " IE_IBE ,Interrupt COP on INBOX Empty" "Empty,Full"
|
|
eventfld.long 0x00 29. " TAG ,TAG" "Invalid,Valid"
|
|
bitfld.long 0x00 24.--27. " IN_BOX_STAT ,INBOX status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 17.--23. 1. " IN_BOX_CMD ,INBOX command"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " IN_BOX_DATA ,INBOX data"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "OUTBOX_0,Shared resource outbox"
|
|
bitfld.long 0x00 31. " IE_OBF ,Interrupt CPU on OUTBOX Full" "Empty,Full"
|
|
bitfld.long 0x00 30. " IE_OBE ,Interrupt COP on OUTBOX Empty" "Empty,Full"
|
|
eventfld.long 0x00 29. " TAG ,TAG" "Invalid,Valid"
|
|
bitfld.long 0x00 24.--27. " OUT_BOX_STAT ,OUTBOX status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 17.--23. 1. " OUT_BOX_CMD ,OUTBOX command"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " OUT_BOX_DATA ,OUTBOX data"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "GPIO Controller/Pin MUX"
|
|
tree "GPIO 1"
|
|
tree "Port A"
|
|
base ad:0x6000D000
|
|
; 0 - GPIO controller number
|
|
; 0x0 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x0)++0x03
|
|
line.long 0x00 "GPIO_CNF_0,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "GPIO_OE_0,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x0)++0x03
|
|
line.long 0x00 "GPIO_OUT_0,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x0)++0x03
|
|
line.long 0x00 "GPIO_IN_0,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_0,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_0,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_0,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_0,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_0,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_0,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_0,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x0)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P0_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_0,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_0,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_0,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x0)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P0_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port B"
|
|
base ad:0x6000D000
|
|
; 0 - GPIO controller number
|
|
; 0x4 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x4)++0x03
|
|
line.long 0x00 "GPIO_CNF_0,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x4)++0x03
|
|
line.long 0x00 "GPIO_OE_0,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x4)++0x03
|
|
line.long 0x00 "GPIO_OUT_0,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x4)++0x03
|
|
line.long 0x00 "GPIO_IN_0,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_0,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_0,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_0,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_0,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_0,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_0,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_0,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x4)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P0_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_0,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_0,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_0,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x4)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P0_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port C"
|
|
base ad:0x6000D000
|
|
; 0 - GPIO controller number
|
|
; 0x8 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x8)++0x03
|
|
line.long 0x00 "GPIO_CNF_0,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x8)++0x03
|
|
line.long 0x00 "GPIO_OE_0,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x8)++0x03
|
|
line.long 0x00 "GPIO_OUT_0,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x8)++0x03
|
|
line.long 0x00 "GPIO_IN_0,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_0,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_0,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_0,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_0,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_0,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_0,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_0,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x8)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P0_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_0,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_0,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_0,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x8)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P0_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port D"
|
|
base ad:0x6000D000
|
|
; 0 - GPIO controller number
|
|
; 0xC - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0xC)++0x03
|
|
line.long 0x00 "GPIO_CNF_0,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0xC)++0x03
|
|
line.long 0x00 "GPIO_OE_0,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0xC)++0x03
|
|
line.long 0x00 "GPIO_OUT_0,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0xC)++0x03
|
|
line.long 0x00 "GPIO_IN_0,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_0,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_0,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_0,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_0,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_0,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_0,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_0,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0xC)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P0_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_0,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_0,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_0,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0xC)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P0_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "GPIO 2"
|
|
tree "Port E"
|
|
base ad:0x6000D100
|
|
; 1 - GPIO controller number
|
|
; 0x0 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x0)++0x03
|
|
line.long 0x00 "GPIO_CNF_1,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "GPIO_OE_1,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x0)++0x03
|
|
line.long 0x00 "GPIO_OUT_1,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x0)++0x03
|
|
line.long 0x00 "GPIO_IN_1,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_1,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_1,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_1,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_1,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_1,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_1,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_1,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x0)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P1_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_1,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_1,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_1,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x0)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P1_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port F"
|
|
base ad:0x6000D100
|
|
; 1 - GPIO controller number
|
|
; 0x4 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x4)++0x03
|
|
line.long 0x00 "GPIO_CNF_1,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x4)++0x03
|
|
line.long 0x00 "GPIO_OE_1,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x4)++0x03
|
|
line.long 0x00 "GPIO_OUT_1,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x4)++0x03
|
|
line.long 0x00 "GPIO_IN_1,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_1,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_1,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_1,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_1,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_1,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_1,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_1,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x4)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P1_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_1,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_1,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_1,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x4)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P1_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port G"
|
|
base ad:0x6000D100
|
|
; 1 - GPIO controller number
|
|
; 0x8 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x8)++0x03
|
|
line.long 0x00 "GPIO_CNF_1,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x8)++0x03
|
|
line.long 0x00 "GPIO_OE_1,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x8)++0x03
|
|
line.long 0x00 "GPIO_OUT_1,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x8)++0x03
|
|
line.long 0x00 "GPIO_IN_1,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_1,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_1,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_1,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_1,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_1,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_1,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_1,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x8)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P1_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_1,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_1,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_1,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x8)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P1_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port H"
|
|
base ad:0x6000D100
|
|
; 1 - GPIO controller number
|
|
; 0xC - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0xC)++0x03
|
|
line.long 0x00 "GPIO_CNF_1,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0xC)++0x03
|
|
line.long 0x00 "GPIO_OE_1,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0xC)++0x03
|
|
line.long 0x00 "GPIO_OUT_1,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0xC)++0x03
|
|
line.long 0x00 "GPIO_IN_1,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_1,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_1,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_1,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_1,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_1,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_1,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_1,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0xC)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P1_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_1,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_1,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_1,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0xC)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P1_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "GPIO 3"
|
|
tree "Port I"
|
|
base ad:0x6000D200
|
|
; 2 - GPIO controller number
|
|
; 0x0 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x0)++0x03
|
|
line.long 0x00 "GPIO_CNF_2,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "GPIO_OE_2,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x0)++0x03
|
|
line.long 0x00 "GPIO_OUT_2,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x0)++0x03
|
|
line.long 0x00 "GPIO_IN_2,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_2,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_2,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_2,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_2,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_2,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_2,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_2,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x0)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P2_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_2,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_2,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_2,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x0)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P2_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port J"
|
|
base ad:0x6000D200
|
|
; 2 - GPIO controller number
|
|
; 0x4 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x4)++0x03
|
|
line.long 0x00 "GPIO_CNF_2,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x4)++0x03
|
|
line.long 0x00 "GPIO_OE_2,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x4)++0x03
|
|
line.long 0x00 "GPIO_OUT_2,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x4)++0x03
|
|
line.long 0x00 "GPIO_IN_2,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_2,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_2,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_2,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_2,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_2,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_2,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_2,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x4)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P2_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_2,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_2,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_2,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x4)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P2_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port K"
|
|
base ad:0x6000D200
|
|
; 2 - GPIO controller number
|
|
; 0x8 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x8)++0x03
|
|
line.long 0x00 "GPIO_CNF_2,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x8)++0x03
|
|
line.long 0x00 "GPIO_OE_2,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x8)++0x03
|
|
line.long 0x00 "GPIO_OUT_2,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x8)++0x03
|
|
line.long 0x00 "GPIO_IN_2,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_2,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_2,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_2,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_2,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_2,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_2,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_2,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x8)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P2_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_2,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_2,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_2,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x8)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P2_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port L"
|
|
base ad:0x6000D200
|
|
; 2 - GPIO controller number
|
|
; 0xC - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0xC)++0x03
|
|
line.long 0x00 "GPIO_CNF_2,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0xC)++0x03
|
|
line.long 0x00 "GPIO_OE_2,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0xC)++0x03
|
|
line.long 0x00 "GPIO_OUT_2,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0xC)++0x03
|
|
line.long 0x00 "GPIO_IN_2,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_2,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_2,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_2,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_2,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_2,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_2,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_2,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0xC)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P2_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_2,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_2,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_2,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0xC)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P2_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "GPIO 4"
|
|
tree "Port M"
|
|
base ad:0x6000D300
|
|
; 3 - GPIO controller number
|
|
; 0x0 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x0)++0x03
|
|
line.long 0x00 "GPIO_CNF_3,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "GPIO_OE_3,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x0)++0x03
|
|
line.long 0x00 "GPIO_OUT_3,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x0)++0x03
|
|
line.long 0x00 "GPIO_IN_3,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_3,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_3,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_3,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_3,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_3,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_3,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_3,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x0)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P3_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_3,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_3,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_3,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x0)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P3_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port N"
|
|
base ad:0x6000D300
|
|
; 3 - GPIO controller number
|
|
; 0x4 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x4)++0x03
|
|
line.long 0x00 "GPIO_CNF_3,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x4)++0x03
|
|
line.long 0x00 "GPIO_OE_3,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x4)++0x03
|
|
line.long 0x00 "GPIO_OUT_3,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x4)++0x03
|
|
line.long 0x00 "GPIO_IN_3,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_3,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_3,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_3,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_3,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_3,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_3,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_3,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x4)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P3_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_3,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_3,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_3,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x4)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P3_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port O"
|
|
base ad:0x6000D300
|
|
; 3 - GPIO controller number
|
|
; 0x8 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x8)++0x03
|
|
line.long 0x00 "GPIO_CNF_3,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x8)++0x03
|
|
line.long 0x00 "GPIO_OE_3,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x8)++0x03
|
|
line.long 0x00 "GPIO_OUT_3,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x8)++0x03
|
|
line.long 0x00 "GPIO_IN_3,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_3,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_3,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_3,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_3,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_3,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_3,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_3,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x8)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P3_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_3,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_3,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_3,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x8)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P3_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port P"
|
|
base ad:0x6000D300
|
|
; 3 - GPIO controller number
|
|
; 0xC - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0xC)++0x03
|
|
line.long 0x00 "GPIO_CNF_3,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0xC)++0x03
|
|
line.long 0x00 "GPIO_OE_3,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0xC)++0x03
|
|
line.long 0x00 "GPIO_OUT_3,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0xC)++0x03
|
|
line.long 0x00 "GPIO_IN_3,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_3,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_3,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_3,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_3,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_3,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_3,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_3,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0xC)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P3_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_3,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_3,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_3,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0xC)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P3_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "GPIO 5"
|
|
tree "Port Q"
|
|
base ad:0x6000D400
|
|
; 4 - GPIO controller number
|
|
; 0x0 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x0)++0x03
|
|
line.long 0x00 "GPIO_CNF_4,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "GPIO_OE_4,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x0)++0x03
|
|
line.long 0x00 "GPIO_OUT_4,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x0)++0x03
|
|
line.long 0x00 "GPIO_IN_4,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_4,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_4,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_4,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_4,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_4,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_4,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_4,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x0)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P4_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_4,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_4,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_4,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x0)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P4_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port R"
|
|
base ad:0x6000D400
|
|
; 4 - GPIO controller number
|
|
; 0x4 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x4)++0x03
|
|
line.long 0x00 "GPIO_CNF_4,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x4)++0x03
|
|
line.long 0x00 "GPIO_OE_4,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x4)++0x03
|
|
line.long 0x00 "GPIO_OUT_4,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x4)++0x03
|
|
line.long 0x00 "GPIO_IN_4,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_4,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_4,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_4,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_4,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_4,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_4,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_4,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x4)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P4_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_4,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_4,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_4,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x4)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P4_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port S"
|
|
base ad:0x6000D400
|
|
; 4 - GPIO controller number
|
|
; 0x8 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x8)++0x03
|
|
line.long 0x00 "GPIO_CNF_4,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x8)++0x03
|
|
line.long 0x00 "GPIO_OE_4,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x8)++0x03
|
|
line.long 0x00 "GPIO_OUT_4,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x8)++0x03
|
|
line.long 0x00 "GPIO_IN_4,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_4,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_4,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_4,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_4,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_4,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_4,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_4,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x8)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P4_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_4,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_4,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_4,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x8)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P4_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port T"
|
|
base ad:0x6000D400
|
|
; 4 - GPIO controller number
|
|
; 0xC - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0xC)++0x03
|
|
line.long 0x00 "GPIO_CNF_4,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0xC)++0x03
|
|
line.long 0x00 "GPIO_OE_4,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0xC)++0x03
|
|
line.long 0x00 "GPIO_OUT_4,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0xC)++0x03
|
|
line.long 0x00 "GPIO_IN_4,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_4,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_4,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_4,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_4,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_4,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_4,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_4,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0xC)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P4_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_4,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_4,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_4,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0xC)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P4_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "GPIO 6"
|
|
tree "Port U"
|
|
base ad:0x6000D500
|
|
; 5 - GPIO controller number
|
|
; 0x0 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x0)++0x03
|
|
line.long 0x00 "GPIO_CNF_5,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "GPIO_OE_5,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x0)++0x03
|
|
line.long 0x00 "GPIO_OUT_5,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x0)++0x03
|
|
line.long 0x00 "GPIO_IN_5,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_5,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_5,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_5,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_5,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_5,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_5,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_5,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x0)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P5_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_5,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_5,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_5,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x0)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P5_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port V"
|
|
base ad:0x6000D500
|
|
; 5 - GPIO controller number
|
|
; 0x4 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x4)++0x03
|
|
line.long 0x00 "GPIO_CNF_5,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x4)++0x03
|
|
line.long 0x00 "GPIO_OE_5,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x4)++0x03
|
|
line.long 0x00 "GPIO_OUT_5,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x4)++0x03
|
|
line.long 0x00 "GPIO_IN_5,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_5,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_5,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_5,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_5,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_5,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_5,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_5,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x4)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P5_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_5,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_5,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_5,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x4)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P5_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port W"
|
|
base ad:0x6000D500
|
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; 5 - GPIO controller number
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; 0x8 - Address offset
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width 16.
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tree.open "Lower offset access (Read-Modify-Write)"
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group.long (0x00+0x8)++0x03
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line.long 0x00 "GPIO_CNF_5,GPIO port configuration register"
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bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
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bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
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bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
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bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
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bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
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bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
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bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
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bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
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bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
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bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
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textline " "
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bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
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bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
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bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
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bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
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group.long (0x10+0x8)++0x03
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line.long 0x00 "GPIO_OE_5,GPIO port enable register"
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bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
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bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
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bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
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bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
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textline " "
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bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
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bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
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bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
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bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
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textline " "
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group.long (0x20+0x8)++0x03
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line.long 0x00 "GPIO_OUT_5,GPIO port output value register"
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bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
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bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
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bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
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bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
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textline " "
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bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
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bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
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bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
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bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
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rgroup.long (0x30+0x8)++0x03
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line.long 0x00 "GPIO_IN_5,GPIO port input value register"
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bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
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bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
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bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
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bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
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textline " "
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bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
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bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
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bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
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bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
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group.long (0x40+0x8)++0x03
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line.long 0x00 "GPIO_INT_STA_5,GPIO port interrupt status register"
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bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
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bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
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bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
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bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
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textline " "
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bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
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bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
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bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
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bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
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group.long (0x50+0x8)++0x03
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line.long 0x00 "GPIO_INT_ENB_5,GPIO port interrupt enabled register"
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bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
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bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
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bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
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bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
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bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
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bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
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bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
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group.long (0x60+0x8)++0x03
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line.long 0x00 "GPIO_INT_LVL_5,GPIO port interrupt activation level register"
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bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
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bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
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bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
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bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
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textline " "
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bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
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bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
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bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
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bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
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textline " "
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bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
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bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
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bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
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bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
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textline " "
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bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
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bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
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bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
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bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
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textline " "
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bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
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bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
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bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
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bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
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textline " "
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bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
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bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
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bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
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bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
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wgroup.long (0x70+0x8)++0x03
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line.long 0x00 "GPIO_INT_CLR_5,GPIO port interrupt flag set-to-clear register"
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bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
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bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
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bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
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bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
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textline " "
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bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
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bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
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bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
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bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
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tree.end
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width 20.
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tree.open "Upper offset access (Per-Pin Mask Write)"
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group.long (0x80+0x8)++0x03
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line.long 0x00 "GPIO_MSK_CNF_5,Masked primary GPIO/SFIO config register"
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bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
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bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
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bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
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bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
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textline " "
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bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
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bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
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bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
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bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
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group.long (0x90+0x8)++0x03
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line.long 0x00 "GPIO_MSK_OE_5,GPIO masked output enable"
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bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
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bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
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bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
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bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
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textline " "
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bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
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bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
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bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
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bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
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group.long (0xA0+0x8)++0x03
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line.long 0x00 "GPIO_MSK_OUT_5,GPIO masked output enable"
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bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
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bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
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bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
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bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
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textline " "
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bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
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bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
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bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
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bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
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sif CPUIS("TEGRAX1")
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group.long (0xB0+0x8)++0x03
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line.long 0x00 "GPIO_DB_CTRL_P5_0,GPIO PORT 3 Debounce Control Register"
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bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
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bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
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bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
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bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
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textline " "
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bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
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bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
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bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
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bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
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endif
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group.long (0xC0+0x8)++0x03
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line.long 0x00 "GPIO_MSK_INT_STA_5,GPIO masked interrupt status"
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bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
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bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
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bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
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bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
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textline " "
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bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
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bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
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bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
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bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
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group.long (0xD0+0x8)++0x03
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line.long 0x00 "GPIO_MSK_INT_ENB_5,GPIO masked interrupt enable"
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bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
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bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
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bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
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bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
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textline " "
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bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
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bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
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bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
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bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
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group.long (0xE0+0x8)++0x03
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line.long 0x00 "GPIO_MSK_INT_LVL_5,GPIO masked interrupt activation levels"
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bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
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bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
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bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
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bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
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textline " "
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bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
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bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
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bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
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bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
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sif CPUIS("TEGRAX1")
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group.long (0xF0+0x8)++0x03
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line.long 0x00 "GPIO_DB_CTRL_P5_0,GPIO PORT 0 Debounce Control Register"
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hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
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endif
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tree.end
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width 0xB
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tree.end
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tree "Port X"
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base ad:0x6000D500
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; 5 - GPIO controller number
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; 0xC - Address offset
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width 16.
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tree.open "Lower offset access (Read-Modify-Write)"
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group.long (0x00+0xC)++0x03
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line.long 0x00 "GPIO_CNF_5,GPIO port configuration register"
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bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
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bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
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bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
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bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
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bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
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bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
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bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
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bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
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bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
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bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
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textline " "
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bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
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bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
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bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
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bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
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group.long (0x10+0xC)++0x03
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line.long 0x00 "GPIO_OE_5,GPIO port enable register"
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bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
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bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
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bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
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textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0xC)++0x03
|
|
line.long 0x00 "GPIO_OUT_5,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0xC)++0x03
|
|
line.long 0x00 "GPIO_IN_5,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_5,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_5,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_5,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_5,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_5,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_5,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_5,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0xC)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P5_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_5,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_5,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_5,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0xC)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P5_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "GPIO 7"
|
|
tree "Port Y"
|
|
base ad:0x6000D600
|
|
; 6 - GPIO controller number
|
|
; 0x0 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x0)++0x03
|
|
line.long 0x00 "GPIO_CNF_6,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "GPIO_OE_6,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x0)++0x03
|
|
line.long 0x00 "GPIO_OUT_6,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x0)++0x03
|
|
line.long 0x00 "GPIO_IN_6,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_6,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_6,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_6,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_6,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_6,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_6,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_6,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x0)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P6_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_6,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_6,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_6,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x0)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P6_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port Z"
|
|
base ad:0x6000D600
|
|
; 6 - GPIO controller number
|
|
; 0x4 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x4)++0x03
|
|
line.long 0x00 "GPIO_CNF_6,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x4)++0x03
|
|
line.long 0x00 "GPIO_OE_6,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x4)++0x03
|
|
line.long 0x00 "GPIO_OUT_6,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x4)++0x03
|
|
line.long 0x00 "GPIO_IN_6,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_6,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_6,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_6,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_6,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_6,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_6,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_6,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x4)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P6_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_6,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_6,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_6,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x4)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P6_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port AA"
|
|
base ad:0x6000D600
|
|
; 6 - GPIO controller number
|
|
; 0x8 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x8)++0x03
|
|
line.long 0x00 "GPIO_CNF_6,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x8)++0x03
|
|
line.long 0x00 "GPIO_OE_6,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x8)++0x03
|
|
line.long 0x00 "GPIO_OUT_6,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x8)++0x03
|
|
line.long 0x00 "GPIO_IN_6,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_6,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_6,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_6,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_6,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_6,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_6,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_6,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x8)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P6_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_6,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_6,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_6,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x8)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P6_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port BB"
|
|
base ad:0x6000D600
|
|
; 6 - GPIO controller number
|
|
; 0xC - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0xC)++0x03
|
|
line.long 0x00 "GPIO_CNF_6,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0xC)++0x03
|
|
line.long 0x00 "GPIO_OE_6,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0xC)++0x03
|
|
line.long 0x00 "GPIO_OUT_6,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0xC)++0x03
|
|
line.long 0x00 "GPIO_IN_6,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_6,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_6,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_6,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0xC)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_6,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_6,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_6,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_6,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0xC)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P6_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_6,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_6,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0xC)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_6,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0xC)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P6_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "GPIO 8"
|
|
tree "Port CC"
|
|
base ad:0x6000D700
|
|
; 7 - GPIO controller number
|
|
; 0x0 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x0)++0x03
|
|
line.long 0x00 "GPIO_CNF_7,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x0)++0x03
|
|
line.long 0x00 "GPIO_OE_7,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x0)++0x03
|
|
line.long 0x00 "GPIO_OUT_7,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x0)++0x03
|
|
line.long 0x00 "GPIO_IN_7,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_7,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_7,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_7,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x0)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_7,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_7,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_7,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_7,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x0)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P7_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_7,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_7,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x0)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_7,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x0)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P7_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port DD"
|
|
base ad:0x6000D700
|
|
; 7 - GPIO controller number
|
|
; 0x4 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x4)++0x03
|
|
line.long 0x00 "GPIO_CNF_7,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x4)++0x03
|
|
line.long 0x00 "GPIO_OE_7,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x4)++0x03
|
|
line.long 0x00 "GPIO_OUT_7,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x4)++0x03
|
|
line.long 0x00 "GPIO_IN_7,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_7,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_7,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_7,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x4)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_7,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_7,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_7,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_7,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x4)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P7_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_7,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_7,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x4)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_7,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x4)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P7_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Port EE"
|
|
base ad:0x6000D700
|
|
; 7 - GPIO controller number
|
|
; 0x8 - Address offset
|
|
width 16.
|
|
tree.open "Lower offset access (Read-Modify-Write)"
|
|
group.long (0x00+0x8)++0x03
|
|
line.long 0x00 "GPIO_CNF_7,GPIO port configuration register"
|
|
bitfld.long 0x00 15. " LOCK_7 ,Lock access to pin 7 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LOCK_6 ,Lock access to pin 6 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " LOCK_5 ,Lock access to pin 5 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " LOCK_4 ,Lock access to pin 4 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LOCK_3 ,Lock access to pin 3 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LOCK_2 ,Lock access to pin 2 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LOCK_1 ,Lock access to pin 1 CNF,OE and OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LOCK_0 ,Lock access to pin 0 CNF,OE and OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 GPIO or SFIO type" "SFIO,GPIO"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 GPIO or SFIO mode" "SPIO,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 GPIO or SFIO mode" "SPIO,GPIO"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 GPIO or SFIO mode" "SPIO,GPIO"
|
|
group.long (0x10+0x8)++0x03
|
|
line.long 0x00 "GPIO_OE_7,GPIO port enable register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Signal state 7 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 6. " BIT_6 ,Signal state 6 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 5. " BIT_5 ,Signal state 5 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 4. " BIT_4 ,Signal state 4 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Signal state 3 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 2. " BIT_2 ,Signal state 2 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 1. " BIT_1 ,Signal state 1 (GPIO mode only)" "Tri state,Driven"
|
|
bitfld.long 0x00 0. " BIT_0 ,Signal state 0 (GPIO mode only)" "Tri state,Driven"
|
|
textline " "
|
|
group.long (0x20+0x8)++0x03
|
|
line.long 0x00 "GPIO_OUT_7,GPIO port output value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 output value 7 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 output value 6 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 4 output value 5 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 output value 4 (GPIO mode and output enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 output value 3 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 output value 2 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 output value 1 (GPIO mode and output enabled)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 output value 0 (GPIO mode and output enabled)" "Low,High"
|
|
rgroup.long (0x30+0x8)++0x03
|
|
line.long 0x00 "GPIO_IN_7,GPIO port input value register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 input value 7 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 input value 6 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 input value 5 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 input value 4 (GPIO mode only)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 input value 3 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 input value 2 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 input value 1 (GPIO mode only)" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 input value 0 (GPIO mode only)" "Low,High"
|
|
group.long (0x40+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_STA_7,GPIO port interrupt status register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt status 7 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt status 6 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt status 5 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt status 4 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt status 3 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt status 2 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt status 1 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt status 0 (GPIO mode and interrupt enabled)" "Not active,Active"
|
|
group.long (0x50+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_ENB_7,GPIO port interrupt enabled register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt enable 7 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt enable 6 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt enable 5 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt enable 4 (GPIO mode only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt enable 3 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt enable 2 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt enable 1 (GPIO mode only)" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt enable 0 (GPIO mode only)" "Disabled,Enabled"
|
|
group.long (0x60+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_LVL_7,GPIO port interrupt activation level register"
|
|
bitfld.long 0x00 23. " DELTA_7 ,Pin 7 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 22. " DELTA_6 ,Pin 6 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 21. " DELTA_5 ,Pin 5 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 20. " DELTA_4 ,Pin 4 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DELTA_3 ,Pin 3 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 18. " DELTA_2 ,Pin 2 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 17. " DELTA_1 ,Pin 1 any edge interrupt trigger" "No,Yes"
|
|
bitfld.long 0x00 16. " DELTA_0 ,Pin 0 any edge interrupt trigger" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EDGE_7 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 14. " EDGE_6 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 13. " EDGE_5 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 12. " EDGE_4 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EDGE_3 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 10. " EDGE_2 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 9. " EDGE_1 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
bitfld.long 0x00 8. " EDGE_0 ,Configure as edge-triggered interrupt" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BIT_7 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 6. " BIT_6 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 5. " BIT_5 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 4. " BIT_4 ,Interrupt activation level or edge" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 2. " BIT_2 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 1. " BIT_1 ,Interrupt activation level or edge" "Low,High"
|
|
bitfld.long 0x00 0. " BIT_0 ,Interrupt activation level or edge" "Low,High"
|
|
wgroup.long (0x70+0x8)++0x03
|
|
line.long 0x00 "GPIO_INT_CLR_7,GPIO port interrupt flag set-to-clear register"
|
|
bitfld.long 0x00 7. " BIT_7 ,Pin 7 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 6. " BIT_6 ,Pin 6 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 5. " BIT_5 ,Pin 5 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 4. " BIT_4 ,Pin 4 interrupt clear" "Set,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BIT_3 ,Pin 3 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 2. " BIT_2 ,Pin 2 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 1. " BIT_1 ,Pin 1 interrupt clear" "Set,Clear"
|
|
bitfld.long 0x00 0. " BIT_0 ,Pin 0 interrupt clear" "Set,Clear"
|
|
tree.end
|
|
width 20.
|
|
tree.open "Upper offset access (Per-Pin Mask Write)"
|
|
group.long (0x80+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_CNF_7,Masked primary GPIO/SFIO config register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 GPIO or SFIO type" "SPIO,GPIO,Set SPIO,Set GPIO"
|
|
group.long (0x90+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_OE_7,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 Signal state" "Tri state,Driven,Set Tri state,Set Driven"
|
|
group.long (0xA0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_OUT_7,GPIO masked output enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 output value" "Low,High,Set Low,Set High"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 output value" "Low,High,Set Low,Set High"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 output value" "Low,High,Set Low,Set High"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xB0+0x8)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P7_0,GPIO PORT 3 Debounce Control Register"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Enable debounce logic for Port 3 pin 7" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Enable debounce logic for Port 3 pin 6" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Enable debounce logic for Port 3 pin 5" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Enable debounce logic for Port 3 pin 4" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Enable debounce logic for Port 3 pin 3" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Enable debounce logic for Port 3 pin 2" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Enable debounce logic for Port 3 pin 1" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Enable debounce logic for Port 3 pin 0" "Disabled,Enabled,Set Disabled,Set Enabled"
|
|
endif
|
|
group.long (0xC0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_STA_7,GPIO masked interrupt status"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt status" "Not active,Active,Disable interrupt,Set interrupt"
|
|
group.long (0xD0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_ENB_7,GPIO masked interrupt enable"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt enable" "Disabled,Enabled,Disable,Enable"
|
|
group.long (0xE0+0x8)++0x03
|
|
line.long 0x00 "GPIO_MSK_INT_LVL_7,GPIO masked interrupt activation levels"
|
|
bitfld.long 0x00 7. 15. " BIT_7 ,Pin 7 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 6. 14. " BIT_6 ,Pin 6 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 5. 13. " BIT_5 ,Pin 5 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 4. 12. " BIT_4 ,Pin 4 interrupt activation level" "Low,High,Set low,Set high"
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " BIT_3 ,Pin 3 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 2. 10. " BIT_2 ,Pin 2 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 1. 9. " BIT_1 ,Pin 1 interrupt activation level" "Low,High,Set low,Set high"
|
|
bitfld.long 0x00 0. 8. " BIT_0 ,Pin 0 interrupt activation level" "Low,High,Set low,Set high"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long (0xF0+0x8)++0x03
|
|
line.long 0x00 "GPIO_DB_CTRL_P7_0,GPIO PORT 0 Debounce Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P0_DBC_CNT ,Debounce count in miliseconds"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "Pinmux Registers"
|
|
base ad:0x70003000
|
|
width 21.
|
|
group.long 0x3000++0x1F
|
|
line.long 0x00 "ULPI_DATA0_0,Ulpi_Data Controller"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " PULL_UP ,Pull_up control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,SPI3 control" "SPI3,HSI,UARTA,ULPI"
|
|
line.long 0x04 "ULPI_DATA1_0,Ulpi_Data Controller"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2.--3. " PULL_UP ,Pull_up control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,SPI3 control" "SPI3,HSI,UARTA,ULPI"
|
|
line.long 0x08 "ULPI_DATA2_0, Ulpi_Data Controller"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2.--3. " PULL_UP ,Pull_up control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM , SPI3 control" "SPI3,HSI,UARTA,ULPI"
|
|
line.long 0x0C "ULPI_DATA3_0, Ulpi_Data Controller"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2.--3. " PULL_UP ,Pull_up control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM , SPI3 control" "SPI3,HSI,UARTA,ULPI"
|
|
line.long 0x10 "ULPI_DATA4_0,Ulpi_Data Controller"
|
|
bitfld.long 0x10 7. " LOCK ,LOCK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " E_INPUT ,E_INPUT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " TRISTATE ,TRISTATE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2.--3. " PULL_UP ,Pull_up control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x10 0.--1. " PM , SPI3 control" "SPI2,HSI,UARTA,ULPI"
|
|
line.long 0x14 "ULPI_DATA5_0,Ulpi_Data Controller"
|
|
bitfld.long 0x14 7. " LOCK ,LOCK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " E_INPUT ,E_INPUT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " TRISTATE ,TRISTATE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2.--3. " PULL_UP ,Pull_up control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x14 0.--1. " PM ,SPI3 control" "SPI2,HSI,UARTA,ULPI"
|
|
line.long 0x18 "ULPI_DATA6_0,Ulpi_Data Controller"
|
|
bitfld.long 0x18 7. " LOCK , LOCK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " E_INPUT , E_INPUT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " TRISTATE , TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x18 2.--3. " PULL_UP , Pull_up control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x18 0.--1. " PM , SPI3 control" "SPI2,HSI,UARTA,ULPI"
|
|
line.long 0x1C "ULPI_DATA0_7,Ulpi_Data Controller"
|
|
bitfld.long 0x1C 7. " LOCK ,LOCK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " E_INPUT ,E_INPUT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x1C 2.--3. " PULL_UP ,Pull_up control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x1C 0.--1. " PM ,SPI3 control" "SPI2,HSI,UARTA,ULPI"
|
|
group.long 0x3020++0x13
|
|
line.long 0x00 "ULPI_CLK_0,Ulpi_Clk Controller"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD controller" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM controller" "SPI1,SPI5,UARTD,ULPI"
|
|
line.long 0x04 "ULPI_DIR_0,Ulpi_Dir_0 Controller"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD controller" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM controller" "SPI1,SPI5,UARTD,ULPI"
|
|
line.long 0x08 "ULPI_NXT_0,Ulpi_Nxt_0 Controller"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "SPI1,SPI5,UARTD,ULPI"
|
|
line.long 0x0C "ULPI_STP_0,Ulpi_Stp_0 Controller"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "SPI1,SPI5,UARTD,ULPI"
|
|
line.long 0x10 "DAP3_FS_0,Dap3_Fs_0"
|
|
bitfld.long 0x10 7. " LOCK ,LOCK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " E_INPUT ,E_INPUT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x10 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x10 0.--1. " PM ,I2S2 control" "I2S2,SPI5,DISPLAYA,DISPLAYB"
|
|
group.long 0x3034++0x13
|
|
line.long 0x00 "DAP3_DIN_0,Dap3_Din_0 Controller"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PULL_DOWN ,PULL_DOWN control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,I2S2 control " "I2S2,SPI5,DISPLAYA,DISPLAYB"
|
|
line.long 0x04 "DAP3_DOUT_0,Dap3_Dout_0 Controller"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control " "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PULL_DOWN ,PULL_DOWN control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,I2S2 control" "I2S2,SPI5,DISPLAYA,?..."
|
|
line.long 0x08 "DAP3_SCLK_0,Dap3_Sclk_0 Controller"
|
|
bitfld.long 0x08 7. " LOCK ,LOCL control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PULL_DOWN ,PULL_DOWN control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "I2S2,SPI5,,DISPLAYB"
|
|
line.long 0x0C "GPIO_PV0_0,Gpio_Pv0_0 Controller"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control " ",?..."
|
|
line.long 0x10 "GPIO_PV1_0,Gpio_Pv1_0 Controller"
|
|
bitfld.long 0x10 7. " LOCK ,LOCk control" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x10 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x10 0.--1. " PM ,PM control" ",?..."
|
|
group.long 0x3048++0x17
|
|
line.long 0x00 "SDMMC1_CLK_0, SDMMC1_Clk_0 Controller"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PULL_DOWN ,PULL_DOWN control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "SDMMC1,CLK12,?..."
|
|
line.long 0x04 "SDMMC1_CMD_0,SDMMC1_Cmd_0 Controller"
|
|
bitfld.long 0x04 7. " LOCK ,LOCk control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PULL_UP ,PULL_UP control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,SDMMC1 control " "SDMMC1,SPDIF,SPI4,UARTA"
|
|
line.long 0x08 "SDMMC1_DAT3_0,SDMMC1_data3_0 Controller"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PULL_UP ,PULL_UP control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,SDMMC1 control" "SDMMC1,SPDIF,SPI4,UARTA"
|
|
line.long 0x0C "SDMMC1_DAT2_0,SDMMC1_Dat2_0 Controller"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PULL_UP ,PULL_UP control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,SDMMC1 control" "SDMMC1,PWM0,SPI4,UARTA"
|
|
line.long 0x10 "SDMMC1_DAT1_0,SDMMC1_Dat1_0 Controller"
|
|
bitfld.long 0x10 7. " LOCK ,LOCK control " "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x10 2.--3. " PULL_UP ,PULL_UP control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x10 0.--1. " PM ,SDMMC1 control" "SDMMC1,PWM1,SPI4,UARTA"
|
|
line.long 0x14 "SDMMC1_DAT0_0,SDMMC1_Dat0_0 Controller"
|
|
bitfld.long 0x14 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x14 2.--3. " PULL_UP ,PULL_UP control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x14 0.--1. " PM ,SDMMC1 control" "SDMMC1,,SPI4,UARTA"
|
|
group.long 0x3068++0x07
|
|
line.long 0x00 "CLK2_OUT_0, CLK2_Out_0 Controller"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "Extperiph2,?..."
|
|
line.long 0x04 "CLK2_REQ_0,CLK2_Req_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "DAP,?..."
|
|
group.long 0x3110++0x0B
|
|
line.long 0x00 "HDMI_INT_0,HDMI_int_0"
|
|
bitfld.long 0x00 9. " RCV_SEL ,RCV_SEL" "Normal,High"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" ",?..."
|
|
line.long 0x04 "DDC_SCL_0,DDC_SCL_0"
|
|
bitfld.long 0x04 9. " RCV_SEL ,RCV_SEL" "Normal,High"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "I2C4,?..."
|
|
line.long 0x08 "DDC_SDA_0,DDC_SDA_0"
|
|
bitfld.long 0x08 9. " RCV_SEL ,RCV_SEL" "Normal,High"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "I2C4,?..."
|
|
group.long 0x3164++0x0F
|
|
line.long 0x00 "UART_RXD_0,UART2_RXD_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "IRDA,SPDIF,UARTA,SPI4"
|
|
line.long 0x04 "UART2_TXD_0,UART2_TXD_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "IRDA,SPDIF,UARTA,SPI4"
|
|
line.long 0x08 "UART2_RTS_N_0, UART2_RTS_N_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM , PM control" "UARTA,UARTB,GMI,SPI4"
|
|
line.long 0x0C "UART2_CTS_N_0,UART2_CTS_N_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM , PM control" "UARTA,UARTB,GMI,SPI4"
|
|
group.long 0x3174++0x0F
|
|
line.long 0x00 "UART3_TXD_0,Pinmux_AuxUART3_TXD_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "UARTC,,GMI,SPI4"
|
|
line.long 0x04 "UART3_RXD_0,UART3_RXD_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "UARTC,,GMI,SPI4"
|
|
line.long 0x08 "UART3_CTS_N_0,UART3_CTS_N_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "UARTC,SDMMC1,DTV,GMI"
|
|
line.long 0x0C "UART3_RTS_N_0,UART3_RTS_N_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "UARTC,PWM0,DTV,GMI"
|
|
group.long 0x3184++0x13
|
|
line.long 0x00 "GPIO_PU0_0,GPIO_PU0_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "DIsabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "OWR,UARTA,GMI,?..."
|
|
line.long 0x04 "GPIO_PU1_0,GPIO_PU1_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "DIsabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" ",UARTA,GMI,?..."
|
|
line.long 0x08 "GPIO_PU2_0,GPIO_PU2_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" ",UARTA,GMI,?..."
|
|
line.long 0x0C "GPIO_PU3_0,GPIO_PU3_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "PWM0,UARTA,GMI,DISPLAYB"
|
|
line.long 0x10 "GPIO_PU4_0,GPIO_PU4_0"
|
|
bitfld.long 0x10 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x10 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x10 0.--1. " PM ,PM control" "PWM1,UARTA,GMI,DISPLAYB"
|
|
group.long 0x3198++0x0F
|
|
line.long 0x00 "GPIO_PU5_0,GPIO_PU5_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "PWM2,UARTA,GMI,DISPLAYB"
|
|
line.long 0x04 "GPIO_PU6_0,GPIO_PU6_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "PWM3,UARTA,,GMI"
|
|
line.long 0x08 "GEN1_I2C_SDA_0,GEN1_I2C_SDA_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " OD ,OD control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "I2C1,?..."
|
|
line.long 0x0C "GEN1_I2C_SCL_0,GEN1_I2C_SCL_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " OD ,OD control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "I2C1,?..."
|
|
group.long 0x31A8++0x0F
|
|
line.long 0x00 "DAP4_FS_0,DAP4_FS_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "I2S3,GMI,DTV,?..."
|
|
line.long 0x04 "DAP4_DIN_0,DAP4_DIN_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "I2S3,GMI,?..."
|
|
line.long 0x08 "DAP4_DOUT_0,DAP4_DOUT_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "I2S3,GMI,DTV,?..."
|
|
line.long 0x0C "DAP4_SCLK_0,DAP4_SCLK_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "I2S3,GMI,?..."
|
|
group.long 0x31B8++0x0F
|
|
line.long 0x00 "CLK3_OUT_0,CLK3_OUT_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,EXTPERIPH3 control" "EXTPERIPH3,?..."
|
|
line.long 0x04 "CLK3_REQ_0,CLK3_REQ_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "DEV3,?..."
|
|
line.long 0x08 "GPIO_PC7_0,GPIO_PC7_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" ",,GMI,GMI_ALT"
|
|
line.long 0x0C "GPIO_PI5_0,GPIO_PI5_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "SDMMC2A,,GMI,?..."
|
|
group.long 0x31C8++0x0F
|
|
line.long 0x00 "GPIO_PI7_0,GPIO_PI7_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" ",TRACE,GMI,DTV"
|
|
line.long 0x04 "GPIO_PK0_0,GPIO_PK0_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" ",SDMMC3,GMI,SOC"
|
|
line.long 0x08 "GPIO_PK1_0,GPIO_PK1_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "SDMMC2A,TRACE,GMI,?..."
|
|
line.long 0x0C "GPIO_PJ0_0,GPIO_PJ0_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" ",,GMI,USB"
|
|
group.long 0x31D8++0x0F
|
|
line.long 0x00 "GPIO_PJ2_0,GPIO_PJ2_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" ",,GMI,SOC"
|
|
line.long 0x04 "GPIO_PK3_0,GPIO_PK3_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "SDMMC2A,TRACE,GMI,CCLA"
|
|
line.long 0x08 "GPIO_PK4_0,GPIO_PK4_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "SDMMC2A,,GMI,GMI_ALT"
|
|
line.long 0x0C "GPIO_PK2_0,GPIO_PK2_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" ",,GMI,?..."
|
|
group.long 0x31E8++0x0F
|
|
line.long 0x00 "GPIO_PI3_0,GPIO_PI3_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" ",,GMI,SPI4"
|
|
line.long 0x04 "GPIO_PI6_0,GPIO_PI6_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" ",,GMI,SDMMC2A"
|
|
line.long 0x08 "GPIO_PG0_0,GPIO_PG0_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" ",,GMI,?..."
|
|
line.long 0x0C "GPIO_PG1_0,GPIO_PG1_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" ",,GMI,SPI4"
|
|
group.long 0x31FB++0x0F
|
|
line.long 0x00 "GPIO_PG2_0,GPIO_PG2_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" ",TRACE,GMI,?..."
|
|
line.long 0x04 "GPIO_PG3_0,GPIO_PG3_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" ",TRACE,GMI,?..."
|
|
line.long 0x08 "GPIO_PG4_0,GPIO_PG4_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" ",TMDS,GMI,SPI4"
|
|
line.long 0x0C "GPIO_PG5_0,GPIO_PG5_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" ",,GMI,SPI4"
|
|
group.long 0x3208++0x0F
|
|
line.long 0x00 "GPIO_PG6_0,GPIO_PG6_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" ",,GMI,SPI4"
|
|
line.long 0x04 "GPIO_PG7_0,GPIO_PG7_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" ",,GMI,SPI4"
|
|
line.long 0x08 "GPIO_PH0_0,GPIO_PH0_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "PWM0,TRACE,GMI,DTV"
|
|
line.long 0x0C "GPIO_PH1_0,GPIO_PH1_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "PWM1,TMDS,GMI,DISPLAYA"
|
|
group.long 0x3218++0x0F
|
|
line.long 0x00 "GPIO_PH2_0,GPIO_PH2_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "PWM2,TMDS,GMI,CLDVFS"
|
|
line.long 0x04 "GPIO_PH3_0,GPIO_PH3_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "PWM3,SPI4,GMI,CLDVFS"
|
|
line.long 0x08 "GPIO_PH4_0,GPIO_PH4_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "SDMMC2A,,GMI,?..."
|
|
line.long 0x0C "GPIO_PH5_0,GPIO_PH5_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "SDMMC2A,,GMI,?..."
|
|
group.long 0x3228++0x0F
|
|
line.long 0x00 "GPIO_PH6_0,GPIO_PH6_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "SDMMC2A,TRACE,GMI,DTV"
|
|
line.long 0x04 "GPIO_PH7_0,GPIO_PH7_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "SDMMC2A,TRACE,GMI,DTV"
|
|
line.long 0x08 "GPIO_PJ7_0,GPIO_PJ7_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "UARTD,,GMI,GMI_ALT"
|
|
line.long 0x0C "GPIO_PB0_0,GPIO_PB0_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "UARTD,,GMI,?..."
|
|
group.long 0x3238++0x0F
|
|
line.long 0x00 "GPIO_PB1_0,GPIO_PB1_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "UARTD,,GMI,?..."
|
|
line.long 0x04 "GPIO_PK7_0,GPIO_PK7_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "UARTD,,GMI,?..."
|
|
line.long 0x08 "GPIO_PI0_0,GPIO_PI0_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" ",,GMI,?..."
|
|
line.long 0x0C "GPIO_PI1_0,GPIO_PI1_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" ",,GMI,?..."
|
|
group.long 0x3248++0x0F
|
|
line.long 0x00 "GPIO_PI2_0,GPIO_PI2_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "SDMMC2A,TRACE,GMI,?..."
|
|
line.long 0x04 "GPIO_PI4_0,GPIO_PI4_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "SPI4,TRACE,GMI,DISPLAYA"
|
|
line.long 0x08 "GEN2_I2C_SCL_0,GEN2_I2C_SCL_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " OD ,OD control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "I2C2,,GMI,?..."
|
|
line.long 0x0C "GEN2_I2C_SDA_0,GEN2_I2C_SDA_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " OD ,OD control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "I2C2,,GMI,?..."
|
|
group.long 0x3258++0x0F
|
|
line.long 0x00 "SDMMC4_CLK_0,SDMMC4_CLK_0"
|
|
bitfld.long 0x00 8. " IO_RESET ,IO_RESET control" "Normal,IOreset"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "SDMMC4,,GMI,?..."
|
|
line.long 0x04 "SDMMC4_CMD_0,SDMMC4_CMD_0"
|
|
bitfld.long 0x04 8. " IO_RESET ,IO_RESET control" "Normal,IOreset"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "SDMMC4,,GMI,?..."
|
|
line.long 0x08 "SDMMC4_DAT0_0,SDMMC4_DAT0_0"
|
|
bitfld.long 0x08 8. " IO_RESET ,IO_RESET control" "Normal,IOreset"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "SDMMC4,SPI3,GMI,?..."
|
|
line.long 0x0C "SDMMC4_DAT1_0,SDMMC4_DAT1_0"
|
|
bitfld.long 0x0C 8. " IO_RESET ,IO_RESET control" "Normal,IOreset"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "SDMMC4,SPI3,GMI,?..."
|
|
group.long 0x3268++0x0F
|
|
line.long 0x00 "SDMMC4_DAT2_0,SDMMC4_DAT2_0"
|
|
bitfld.long 0x00 8. " IO_RESET ,IO_RESET control" "Normal,IOreset"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "SDMMC4,SPI3,GMI,?..."
|
|
line.long 0x04 "SDMMC4_DAT3_0,SDMMC4_DAT3_0"
|
|
bitfld.long 0x04 8. " IO_RESET ,IO_RESET control" "Normal,IOreset"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "SDMMC4,SPI3,GMI,?..."
|
|
line.long 0x08 "SDMMC4_DAT4_0,SDMMC4_DAT4_0"
|
|
bitfld.long 0x08 8. " IO_RESET ,IO_RESET control" "Normal,IOreset"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "SDMMC4,SPI3,GMI,?..."
|
|
line.long 0x0C "SDMMC4_DAT5_0,SDMMC4_DAT5_0"
|
|
bitfld.long 0x0C 8. " IO_RESET ,IO_RESET control" "Normal,IOreset"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "SDMMC4,SPI3,?..."
|
|
group.long 0x3278++0x07
|
|
line.long 0x00 "SDMMC4_DAT6_0,SDMMC4_DAT6_0"
|
|
bitfld.long 0x00 8. " IO_RESET ,IO_RESET control" "Normal,IOreset"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "SDMMC4,SPI3,GMI,?..."
|
|
line.long 0x04 "SDMMC4_DAT7_0,SDMMC4_DAT7_0"
|
|
bitfld.long 0x04 8. " IO_RESET ,IO_RESET control" "Normal,IOreset"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "SDMMC4,,GMI,?..."
|
|
group.long 0x3284++0x0F
|
|
line.long 0x00 "CAM_MCLK_0,CAM_MCLK_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "VI,VI_ALT1,VI_ALT3,SDMMC2B"
|
|
line.long 0x04 "GPIO_PCC1_0,GPIO_PCC1_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "I2S4,,,SDMMC2B"
|
|
line.long 0x08 "GPIO_PBB0_0,GPIO_PBB0_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "VGP6,VIMCLK2,SDMMC2B,VIMCLK2_ALT"
|
|
line.long 0x0C "CAM_I2C_SCL_0,CAM_I2C_SCL_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " OD ,OD control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "VGP1,I2C3,,SDMMC2B"
|
|
group.long 0x3294++0x0F
|
|
line.long 0x00 "CAM_I2C_SDA_0,CAM_I2C_SDA_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " OD ,OD control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "VGP2,I2C3,,SDMMC2B"
|
|
line.long 0x04 "GPIO_PBB3_0,GPIO_PBB3_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "VGP3,DISPLAYA,DISPLAYB,SDMMC2B"
|
|
line.long 0x08 "GPIO_PBB4_0,GPIO_PBB4_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "VGP4,DISPLAYA,DISPLAYB,SDMMC2B"
|
|
line.long 0x0C "GPIO_PBB5_0,GPIO_PBB5_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "VGP5,DISPLAYA,,SDMMC2B"
|
|
group.long 0x32A4++0x0F
|
|
line.long 0x00 "GPIO_PBB6_0,GPIO_PBB6_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "I2S4,,DISPLAYB,SDMMC2B"
|
|
line.long 0x04 "GPIO_PBB7_0,GPIO_PBB7_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "I2S4,,,SDMMC2B"
|
|
line.long 0x08 "GPIO_PCC2_0,GPIO_PCC2_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "I2S4,,SDMMC3,SDMMC2B"
|
|
line.long 0x0C "JTAG_RTCK_0,JTAG_RTCK_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "RTCK,?..."
|
|
group.long 0x32B4++0x0F
|
|
line.long 0x00 "PWR_I2C_SCL_0,PWR_I2C_SCL_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "I2CPWR,?..."
|
|
line.long 0x04 "PWR_I2C_SDA_0,PWR_I2C_SDA_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "I2CPWR,?..."
|
|
line.long 0x08 "KB_ROW0_0,KB_ROW0_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "KBC,?..."
|
|
line.long 0x0C "KB_ROW1_0,KB_ROW1_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "KBC,?..."
|
|
group.long 0x32C4++0x0F
|
|
line.long 0x00 "KB_ROW2_0,KB_ROW2_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "KBC,?..."
|
|
line.long 0x04 "KB_ROW3_0,KB_ROW3_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "KBC,DISPLAYA,SYS,DISPLAYB"
|
|
line.long 0x08 "KB_ROW4_0,KB_ROW4_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "KBC,DISPLAYA,,DISPLAYB"
|
|
line.long 0x0C "KB_ROW5_0,KB_ROW5_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "KBC,DISPLAYA,,DISPLAYB"
|
|
group.long 0x32D4++0x0F
|
|
line.long 0x00 "KB_ROW6_0,KB_ROW6_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "KBC,DISPLAYA,DISPLAYA_ALT,DISPLAYB"
|
|
line.long 0x04 "KB_ROW7_0,KB_ROW7_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "KBC,,CLDVFS,UARTA"
|
|
line.long 0x08 "KB_ROW8_0,KB_ROW8_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "KBC,,CLDVFS,UARTA"
|
|
line.long 0x0C "KB_ROW9_0,KB_ROW9_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "KBC,,,UARTA"
|
|
group.long 0x32E4++0x0F
|
|
line.long 0x00 "KB_ROW10_0,KB_ROW10_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "KBC,,,UARTA"
|
|
line.long 0x04 "KB_ROW11_0,KB_ROW11_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "KBC,,,IRDA"
|
|
line.long 0x08 "KB_ROW12_0,KB_ROW12_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "KBC,,,IRDA"
|
|
line.long 0x0C "KB_ROW13_0,KB_ROW13_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "KBC,,SPI2,?..."
|
|
group.long 0x32F4++0x0F
|
|
line.long 0x00 "KB_ROW14_0,KB_ROW14_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "KBC,,SPI2,?..."
|
|
line.long 0x04 "KB_ROW15_0,KB_ROW15_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "KBC,SOC,?..."
|
|
line.long 0x08 "KB_COL0_0,KB_COL0_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "KBC,,SPI2,?..."
|
|
line.long 0x0C "KB_COL1_0,KB_COL1_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "KBC,,SPI2,?..."
|
|
group.long 0x3304++0x0F
|
|
line.long 0x00 "KB_COL2_0,KB_COL2_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "KBC,,SPI2,?..."
|
|
line.long 0x04 "KB_COL3_0,KB_COL3_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "KBC,DISPLAYA,PWM,UARTA"
|
|
line.long 0x08 "KB_COL4_0,KB_COL4_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "KBC,OWR,SDMMC3,UARTA"
|
|
line.long 0x0C "KB_COL5_0,KB_COL5_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "KBC,,SDMMC3,?..."
|
|
group.long 0x3314++0x0B
|
|
line.long 0x00 "KB_COL6_0,KB_COL6_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "KBC,,SPI2,UARTD"
|
|
line.long 0x04 "KB_COL7_0,KB_COL7_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "KBC,,SPI2,UARTD"
|
|
line.long 0x08 "CLK_32K_OUT_0,CLK_32K_OUT_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "BLInk,SOC,?..."
|
|
group.long 0x3324++0x0F
|
|
line.long 0x00 "CORE_PWR_REQ_0,CORE_PWR_REQ_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "PWRON,?..."
|
|
line.long 0x04 "CPU_PWR_REQ_0,CPU_PWR_REQ_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "CPU,?..."
|
|
line.long 0x08 "PWR_INT_N_0,PWR_INT_N_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "PMI,?..."
|
|
line.long 0x0C "CLK_32K_IN_0,CLK_32K_IN_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "CLK,?..."
|
|
group.long 0x3334++0x0F
|
|
line.long 0x00 "OWR_0,OWR_0"
|
|
bitfld.long 0x00 9. " RCV_SEL ,RCV_SEL" "Normal,High"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "OWR,?..."
|
|
line.long 0x04 "DAP1_FS_0,DAP1_FS_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "I2S0,HDA,GMI,?..."
|
|
line.long 0x08 "DAP1_DIN_0,DAP1_DIN_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "I2S0,HDA,GMI,?..."
|
|
line.long 0x0C "DAP1_DOUT_0,DAP1_DOUT_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "I2S0,HDA,GMI,SATA"
|
|
group.long 0x3344++0x0F
|
|
line.long 0x00 "DAP1_SCLK_0,DAP1_SCLK_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "I2S0,HDA,GMI,?..."
|
|
line.long 0x04 "DAP_MCLK1_REQ_0,DAP_MCLK1_REQ_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "DAP,DAP1,SATA,?..."
|
|
line.long 0x08 "DAP_MCLK1_0,DAP_MCLK1_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "EXTPERIPH1,DAP2,?..."
|
|
line.long 0x0C "SPDIF_IN_0,SPDIF_IN_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "SPDIF,,,I2C3"
|
|
group.long 0x3354++0x0F
|
|
line.long 0x00 "SPDIF_OUT_0,SPDIF_OUT_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "SPDIF,,,I2C3"
|
|
line.long 0x04 "DAP2_FS_0,DAP2_FS_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "I2S1,HDA,GMI,?..."
|
|
line.long 0x08 "DAP2_DIN_0,DAP2_DIN_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "I2S1,HDA,GMI,?..."
|
|
line.long 0x0C "DAP2_DOUT_0,DAP2_DOUT_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "I2S1,HDA,GMI,?..."
|
|
group.long 0x3364++0x0F
|
|
line.long 0x00 "DAP2_SCLK_0,DAP2_SCLK_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "I2S1,HDA,GMI,?..."
|
|
line.long 0x04 "DVFS_PWM_0,DVFS_PWM_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "SPI6,CLDVFS,GMI,?..."
|
|
line.long 0x08 "GPIO_X1_AUD_0,GPIO_X1_AUD_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "SPI6,,GMI,?..."
|
|
line.long 0x0C "GPIO_X3_AUD_0,GPIO_X3_AUD_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "SPI6,SPI1,GMI,?..."
|
|
group.long 0x3374++0x13
|
|
line.long 0x00 "DVFS_CLK_0,DVFS_CLK_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "SPI6,CLDVFS,GMI,?..."
|
|
line.long 0x04 "GPIO_X4_AUD_0,GPIO_X4_AUD_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "GMI,SPI1,SPI2,DAP2"
|
|
line.long 0x08 "GPIO_X5_AUD_0,GPIO_X5_AUD_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "GMI,SPI1,SPI2,?..."
|
|
line.long 0x0C "GPIO_X6_AUD_0,GPIO_X6_AUD_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "SPI6,SPI1,SPI2,GMI"
|
|
line.long 0x10 "GPIO_X7_AUD_0,GPIO_X7_AUD_0"
|
|
bitfld.long 0x10 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x10 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x10 0.--1. " PM ,PM control" ",SPI1,SPI2,?..."
|
|
group.long 0x3390++0x0F
|
|
line.long 0x00 "SDMMC3_CLK_0,SDMMC3_CLK_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "SDMMC3,,,SPI3"
|
|
line.long 0x04 "SDMMC3_CMD_0,SDMMC3_CMD_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "SDMMC3,PWM3,UARTA,SPI3"
|
|
line.long 0x08 "SDMMC3_DAT0_0,SDMMC3_DAT0_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "SDMMC3,,,SPI3"
|
|
line.long 0x0C "SDMMC3_DAT1_0,SDMMC3_DAT1_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "SDMMC3,PWM2,UARTA,SPI3"
|
|
group.long 0x33A0++0x07
|
|
line.long 0x00 "SDMMC3_DAT2_0,SDMMC3_DAT2_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "SDMMC3,PWM1,DISPLAYA,SPI3"
|
|
line.long 0x04 "SDMMC3_DAT3_0,SDMMC3_DAT3_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "SDMMC3,PWM0,DISPLAYB,SPI3"
|
|
group.long 0x33BC++0x0B
|
|
line.long 0x00 "PEX_L0_RST_N_0,PEX_L0_RST_N_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "PE0,?..."
|
|
line.long 0x04 "PEX_L0_CLKREQ_N_0,PEX_L0_CLKREQ_N_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "PE0,?..."
|
|
line.long 0x08 "PEX_WAKE_N_0,PEX_WAKE_N_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "PE,?..."
|
|
group.long 0x33CC++0x07
|
|
line.long 0x00 "PEX_L1_RST_N_0,PEX_L1_RST_N_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "PE1,?..."
|
|
line.long 0x04 "PEX_L1_CLKREQ_N_0,PEX_L1_CLKREQ_N_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "PE1,,,SPI3"
|
|
group.long 0x33E0++0x1F
|
|
line.long 0x00 "AUX_HDMI_CEC_0,HDMI_CEC_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " OD ,OD control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "CEC,?..."
|
|
line.long 0x04 "SDMMC1_WP_N_0,SDMMC1_WP_N_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "SDMMC1,CLK12,SPI4,UARTA"
|
|
line.long 0x08 "SDMMC3_CD_N_0,SDMMC3_CD_N_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" "SDMMC3,OWR,?..."
|
|
line.long 0x0C "SDMMC3_DAT0_0,SDMMC3_DAT0_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "SDMMC3,,,SPI3"
|
|
line.long 0x10 "GPIO_W2_AUD_0,GPIO_W2_AUD_0"
|
|
bitfld.long 0x10 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x10 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x10 0.--1. " PM ,PM control" "SPI6,,SPI2,I2C1"
|
|
line.long 0x14 "GPIO_W3_AUD_0,GPIO_W3_AUD_0"
|
|
bitfld.long 0x14 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x14 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x14 0.--1. " PM ,PM control" "SPI6,SPI1,SPI2,I2C1"
|
|
line.long 0x18 "USB_VBUS_EN0_0,USB_VBUS_EN0_0"
|
|
bitfld.long 0x18 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " OD ,OD control" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x18 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x18 0.--1. " PM ,PM control" "USB,?..."
|
|
line.long 0x1C "USB_VBUS_EN1_0,USB_VBUS_EN1_0"
|
|
bitfld.long 0x1C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x1C 6. " OD ,OD control" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x1C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x1C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x1C 0.--1. " PM ,PM control" "USB,?..."
|
|
group.long 0x3400++0x1B
|
|
line.long 0x00 "SDMMC3_CLK_LB_OUT_0,SDMMC3_CLK_LB_OUT_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "SDMMC3,?..."
|
|
line.long 0x04 "GMI_CLK_LB_0,GMI_CLK_LB_0"
|
|
bitfld.long 0x04 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x04 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x04 0.--1. " PM ,PM control" "SDMMC2A,,GMI,?..."
|
|
line.long 0x08 "RESET_OUT_N_0,RESET_OUT_N_0"
|
|
bitfld.long 0x08 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x08 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x08 0.--1. " PM ,PM control" ",,,RESET_OUT_N"
|
|
line.long 0x0C "KB_ROW16_0,KB_ROW16_0"
|
|
bitfld.long 0x0C 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x0C 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x0C 0.--1. " PM ,PM control" "KBC,,,UARTC"
|
|
line.long 0x010 "KB_ROW17_0,KB_ROW17_0"
|
|
bitfld.long 0x10 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x10 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x10 0.--1. " PM ,PM control" "KBC,,,UARTC"
|
|
line.long 0x14 "USB_VBUS_EN2_0,USB_VBUS_EN2_0"
|
|
bitfld.long 0x14 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " OD ,OD control" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x14 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x14 0.--1. " PM ,PM control" "USB,?..."
|
|
line.long 0x18 "GPIO_PFF2_0,GPIO_PFF2_0"
|
|
bitfld.long 0x18 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x18 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x18 0.--1. " PM ,PM control" "SATA,?..."
|
|
group.long 0x3430++0x03
|
|
line.long 0x00 "DP_HPD_0,DP_HPD_0"
|
|
bitfld.long 0x00 7. " LOCK ,LOCK control" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E_INPUT ,E_INPUT control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TRISTATE ,TRISTATE control" "Normal,Tristate"
|
|
bitfld.long 0x00 2.--3. " PUPD ,PUPD control" "Normal,PULL_DOWN,PULL_UP,?..."
|
|
bitfld.long 0x00 0.--1. " PM ,PM control" "DP,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Power Management Controller"
|
|
base ad:0x7000E400
|
|
tree "PMC Control"
|
|
width 15.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CNTRL_0,PMC control register"
|
|
bitfld.long 0x00 20.--21. " CPUWRGOOD_SEL ,CPUWRGOOD pin select" "SOC_THERM_OC1,SOC_THERM_OC2,SOC_THERM_OC3,SOC_THERM_OC4"
|
|
bitfld.long 0x00 19. " CPUWRGOOD_EN ,CPU_PWR_GOOD signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " FUSE_OVERRIDE ,Fuse override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INTR_POLARITY ,INTR polarity inversion" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CPUPWRREQ_OE ,Power request output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CPUPWRREQ_POLARITY ,Power request polarity inversion" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SIDE_EFFECT_LP0 ,Entering LP0 after powering down CPU" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " AOINIT ,AO initialize purely SW diagnostic and interpretation" "Not done,Done"
|
|
bitfld.long 0x00 12. " PWRGATE_DIS ,Power gating disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYSCLK_OE ,Enable output of system enable clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SYSCLK_POLARITY ,SYS_CLK_REQ enable polarity inversion" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PWRREQ_OE ,CORE_PWR_REQ output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PWRREQ_POLARITY ,CORE_PWR_REQ polarity inversion" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " BLINK_EN ,Blinking counter and blink output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LATCHWAKE_EN ,Enable latching wakeup events" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MAIN_RST ,Reset everything but scratch 0 and reset status" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RTC_RST ,Software reset to RTC" "No reset,Reset"
|
|
bitfld.long 0x00 1. " RTC_CLK_DIS ,Disable 32kHz clock to RTC" "No,Yes"
|
|
textline " "
|
|
line.long 0x04 "SEC_DISABLE_0,Secure register disable"
|
|
bitfld.long 0x04 21. " TSC_NS_WRITE ,Non-secure write-disable for the PMC_TSC_MULT register and the PMC_DPD_ENABLE register-bit" "Off,On"
|
|
bitfld.long 0x04 20. " AMAP_WRITE ,PMC_GLB_AMAP_CFG disable write" "Off,On"
|
|
bitfld.long 0x04 19. " READ7 ,Disable read from secure register 7" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 18. " WRITE7 ,Disable write from secure register 7" "Off,On"
|
|
bitfld.long 0x04 17. " READ6 ,Disable read from secure register 6" "Off,On"
|
|
bitfld.long 0x04 16. " WRITE6 ,Disable write from secure register 6" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 15. " READ5 ,Disable read from secure register 5" "Off,On"
|
|
bitfld.long 0x04 14. " WRITE5 ,Disable write from secure register 5" "Off,On"
|
|
bitfld.long 0x04 13. " READ4 ,Disable read from secure register 4" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 12. " WRITE4 ,Disable write from secure register 4" "Off,On"
|
|
bitfld.long 0x04 11. " READ3 ,Disable read from secure register 3" "Off,On"
|
|
bitfld.long 0x04 10. " WRITE3 ,Disable write from secure register 3" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 9. " READ2 ,Disable read from secure register 2" "Off,On"
|
|
bitfld.long 0x04 8. " WRITE2 ,Disable write from secure register 2" "Off,On"
|
|
bitfld.long 0x04 7. " READ1 ,Disable read from secure register 1" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 6. " WRITE1 ,Disable write from secure register 1" "Off,On"
|
|
bitfld.long 0x04 5. " READ0 ,Disable read from secure register 0" "Off,On"
|
|
bitfld.long 0x04 4. " WRITE0 ,Disable write from secure register 0" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 1. " READ ,Disable read from secure registers - all" "Off,On"
|
|
bitfld.long 0x04 0. " WRITE ,Disable write from secure registers - all" "Off,On"
|
|
textline " "
|
|
line.long 0x08 "PMC_SWRST_0,Register write which resets PMC only"
|
|
bitfld.long 0x08 0. " RST ,Software reset to PMC only" "Disabled,Enabled"
|
|
textline " "
|
|
tree.end
|
|
tree "Wake Control"
|
|
width 18.
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "WAKE_MASK_0,PMC wake-up event mask"
|
|
bitfld.long 0x00 31. " RESET_N ,External reset wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DAP1_DOUT ,Pin dap1_dout wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " KB_ROW15 ,Pin kb_row15 wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " KB_ROW14 ,Pin kb_row14 wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " KB_ROW8 ,Pin kb_row8 wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " KB_ROW13 ,Pin kb_row13 wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " KB_ROW12 ,Pin kb_row12 wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " GP3_PV[0] ,Pin gp3_pv[0] wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " GPIO_Pi[5] ,Pin gpio_pi[5] wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " USB_VBUS_WAKEUP[1] ,Pin usb_vbus_wakeup[1] wake level" "Active low,Active High"
|
|
bitfld.long 0x00 19. " USB1_VBUS ,Pin usb1_vbus wake level" "Active low,Active High"
|
|
bitfld.long 0x00 18. " PWR_INT ,Pin pwr_int wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " KBC_INTERRUPT ,KBC wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RTC_IRQ ,RTC wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " GPIO_PJ[2] ,Pin gpio_pj[2] wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PE_WAKE_N ,Pin pe_wake_n wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SDMMC1_DAT1 ,Pin sdmmc1_dat1 wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " GPIO_W2_AUD ,Pin gpio_w2_aud wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPIO_W3_AUD ,Pin gpio_w3_aud wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SDMMC4_DAT1 ,Pin sdmmc4_dat1 wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " KB_ROW10 ,Pin kb_row10 wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " GPIO_PC ,Pin gpio_pc wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " GP3_PU[6] ,Pin gp3_pu[6] wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " GP3_PU[5] ,Pin gp3_pu[5] wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HDMI_INT ,Pin hdmi_int wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SDMMC3_DAT1 ,Pin sdmmc3_dat1 wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " GP3_PV[1] ,Pin gp3_pv[1] wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ULPI_DATA4 ,Pin ulpi_data4 wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "WAKE_LVL_0,PMC wake level"
|
|
bitfld.long 0x04 31. " RESET_N ,External reset wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " DAP1_DOUT ,Pin dap1_dout wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " KB_ROW15 ,Pin kb_row15 wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " KB_ROW14 ,Pin kb_row14 wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " KB_ROW8 ,Pin kb_row8 wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " KB_ROW13 ,Pin kb_row13 wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " KB_ROW12 ,Pin kb_row12 wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " GP3_PV[0] ,Pin gp3_pv[0] wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " GPIO_Pi[5] ,Pin gpio_pi[5] wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " USB_VBUS_WAKEUP[1] ,Pin usb_vbus_wakeup[1] wake level" "Active low,Active High"
|
|
bitfld.long 0x04 19. " USB1_VBUS ,Pin usb1_vbus wake level" "Active low,Active High"
|
|
bitfld.long 0x04 18. " PWR_INT ,Pin pwr_int wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " KBC_INTERRUPT ,KBC wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " RTC_IRQ ,RTC wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " GPIO_PJ[2] ,Pin gpio_pj[2] wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14. " PE_WAKE_N ,Pin pe_wake_n wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " SDMMC1_DAT1 ,Pin sdmmc1_dat1 wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " GPIO_W2_AUD ,Pin gpio_w2_aud wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " GPIO_W3_AUD ,Pin gpio_w3_aud wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " SDMMC4_DAT1 ,Pin sdmmc4_dat1 wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " KB_ROW10 ,Pin kb_row10 wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " GPIO_PC ,Pin gpio_pc wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " GP3_PU[6] ,Pin gp3_pu[6] wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " GP3_PU[5] ,Pin gp3_pu[5] wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " HDMI_INT ,Pin hdmi_int wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " SDMMC3_DAT1 ,Pin sdmmc3_dat1 wake enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " GP3_PV[1] ,Pin gp3_pv[1] wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ULPI_DATA4 ,Pin ulpi_data4 wake enable" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x08 "WAKE_STATUS_0,PMC wake status"
|
|
eventfld.long 0x08 31. " RESET_N ,External reset wake enable" "Not set,Set"
|
|
eventfld.long 0x08 30. " DAP1_DOUT ,Pin dap1_dout wake enable" "Not set,Set"
|
|
eventfld.long 0x08 29. " KB_ROW15 ,Pin kb_row15 wake enable" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x08 28. " KB_ROW14 ,Pin kb_row14 wake enable" "Not set,Set"
|
|
eventfld.long 0x08 27. " KB_ROW8 ,Pin kb_row8 wake enable" "Not set,Set"
|
|
eventfld.long 0x08 26. " KB_ROW13 ,Pin kb_row13 wake enable" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x08 25. " KB_ROW12 ,Pin kb_row12 wake enable" "Not set,Set"
|
|
eventfld.long 0x08 24. " GP3_PV[0] ,Pin gp3_pv[0] wake enable" "Not set,Set"
|
|
eventfld.long 0x08 23. " GPIO_Pi[5] ,Pin gpio_pi[5] wake enable" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x08 20. " USB_VBUS_WAKEUP[1] ,Pin usb_vbus_wakeup[1] wake level" "Not set,Set"
|
|
eventfld.long 0x08 19. " USB1_VBUS ,Pin usb1_vbus wake level" "Not set,Set"
|
|
eventfld.long 0x08 18. " PWR_INT ,Pin pwr_int wake enable" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x08 17. " KBC_INTERRUPT ,KBC wake enable" "Not set,Set"
|
|
eventfld.long 0x08 16. " RTC_IRQ ,RTC wake enable" "Not set,Set"
|
|
eventfld.long 0x08 15. " GPIO_PJ[2] ,Pin gpio_pj[2] wake enable" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x08 14. " PE_WAKE_N ,Pin pe_wake_n wake enable" "Not set,Set"
|
|
eventfld.long 0x08 13. " SDMMC1_DAT1 ,Pin sdmmc1_dat1 wake enable" "Not set,Set"
|
|
eventfld.long 0x08 12. " GPIO_W2_AUD ,Pin gpio_w2_aud wake enable" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x08 11. " GPIO_W3_AUD ,Pin gpio_w3_aud wake enable" "Not set,Set"
|
|
eventfld.long 0x08 10. " SDMMC4_DAT1 ,Pin sdmmc4_dat1 wake enable" "Not set,Set"
|
|
eventfld.long 0x08 9. " KB_ROW10 ,Pin kb_row10 wake enable" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x08 8. " GPIO_PC ,Pin gpio_pc wake enable" "Not set,Set"
|
|
eventfld.long 0x08 7. " GP3_PU[6] ,Pin gp3_pu[6] wake enable" "Not set,Set"
|
|
eventfld.long 0x08 6. " GP3_PU[5] ,Pin gp3_pu[5] wake enable" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x08 4. " HDMI_INT ,Pin hdmi_int wake enable" "Not set,Set"
|
|
eventfld.long 0x08 3. " SDMMC3_DAT1 ,Pin sdmmc3_dat1 wake enable" "Not set,Set"
|
|
eventfld.long 0x08 1. " GP3_PV[1] ,Pin gp3_pv[1] wake enable" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x08 0. " ULPI_DATA4 ,Pin ulpi_data4 wake enable" "Not set,Set"
|
|
textline " "
|
|
line.long 0x0C "SW_WAKE_STATUS_0,PMC software wake status"
|
|
eventfld.long 0x0C 31. " RESET_N ,External reset wake enable" "Not set,Set"
|
|
eventfld.long 0x0C 30. " DAP1_DOUT ,Pin dap1_dout wake enable" "Not set,Set"
|
|
eventfld.long 0x0C 29. " KB_ROW15 ,Pin kb_row15 wake enable" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x0C 28. " KB_ROW14 ,Pin kb_row14 wake enable" "Not set,Set"
|
|
eventfld.long 0x0C 27. " KB_ROW8 ,Pin kb_row8 wake enable" "Not set,Set"
|
|
eventfld.long 0x0C 26. " KB_ROW13 ,Pin kb_row13 wake enable" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " KB_ROW12 ,Pin kb_row12 wake enable" "Not set,Set"
|
|
eventfld.long 0x0C 24. " GP3_PV[0] ,Pin gp3_pv[0] wake enable" "Not set,Set"
|
|
eventfld.long 0x0C 23. " GPIO_Pi[5] ,Pin gpio_pi[5] wake enable" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x0C 20. " USB_VBUS_WAKEUP[1] ,Pin usb_vbus_wakeup[1] wake level" "Not set,Set"
|
|
eventfld.long 0x0C 19. " USB1_VBUS ,Pin usb1_vbus wake level" "Not set,Set"
|
|
eventfld.long 0x0C 18. " PWR_INT ,Pin pwr_int wake enable" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x0C 17. " KBC_INTERRUPT ,KBC wake enable" "Not set,Set"
|
|
eventfld.long 0x0C 16. " RTC_IRQ ,RTC wake enable" "Not set,Set"
|
|
eventfld.long 0x0C 15. " GPIO_PJ[2] ,Pin gpio_pj[2] wake enable" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x0C 14. " PE_WAKE_N ,Pin pe_wake_n wake enable" "Not set,Set"
|
|
eventfld.long 0x0C 13. " SDMMC1_DAT1 ,Pin sdmmc1_dat1 wake enable" "Not set,Set"
|
|
eventfld.long 0x0C 12. " GPIO_W2_AUD ,Pin gpio_w2_aud wake enable" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x0C 11. " GPIO_W3_AUD ,Pin gpio_w3_aud wake enable" "Not set,Set"
|
|
eventfld.long 0x0C 10. " SDMMC4_DAT1 ,Pin sdmmc4_dat1 wake enable" "Not set,Set"
|
|
eventfld.long 0x0C 9. " KB_ROW10 ,Pin kb_row10 wake enable" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x0C 8. " GPIO_PC ,Pin gpio_pc wake enable" "Not set,Set"
|
|
eventfld.long 0x0C 7. " GP3_PU[6] ,Pin gp3_pu[6] wake enable" "Not set,Set"
|
|
eventfld.long 0x0C 6. " GP3_PU[5] ,Pin gp3_pu[5] wake enable" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x0C 4. " HDMI_INT ,Pin hdmi_int wake enable" "Not set,Set"
|
|
eventfld.long 0x0C 3. " SDMMC3_DAT1 ,Pin sdmmc3_dat1 wake enable" "Not set,Set"
|
|
eventfld.long 0x0C 1. " GP3_PV[1] ,Pin gp3_pv[1] wake enable" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x0C 0. " ULPI_DATA4 ,Pin ulpi_data4 wake enable" "Not set,Set"
|
|
textline " "
|
|
tree.end
|
|
width 18.
|
|
tree "DPD Control"
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "DPD_PADS_ORIDE_0,DPD pads override"
|
|
bitfld.long 0x00 31. " KBC_ROW16 ,Override DPD idle state with row 16 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " KBC_ROW15 ,Override DPD idle state with row15 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " KBC_ROW14 ,Override DPD idle state with row14 output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " KBC_ROW13 ,Override DPD idle state with row 13 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " KBC_ROW12 ,Override DPD idle state with row 12 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " KBC_ROW11 ,Override DPD idle state with row 11 output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " KBC_ROW10 ,Override DPD idle state with row 10 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " KBC_ROW9 ,Override DPD idle state with row 9 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " KBC_ROW8 ,Override DPD idle state with row 8 output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " KBC_ROW7 ,Override DPD idle state with row 7 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYS_CLK_REQ ,Override DPD idle state with column with SYS_CLK_REQ output" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " BLINK ,Override DPD idle state with blink output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " KBC_ROW6 ,Override DPD idle state with row 6 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " KBC_ROW5 ,Override DPD idle state with row 5 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " KBC_ROW4 ,Override DPD idle state with row 4 output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " KBC_ROW3 ,Override DPD idle state with row 3 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " KBC_ROW2 ,Override DPD idle state with row 2 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " KBC_ROW1 ,Override DPD idle state with row 1 output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " KBC_ROW0 ,Override DPD idle state with row 0 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " KBC_COL12 ,Override DPD idle state with column 12 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " KBC_COL11 ,Override DPD idle state with column 11 output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " KBC_COL10 ,Override DPD idle state with column 10 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " KBC_COL9 ,Override DPD idle state with column 9 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " KBC_COL8 ,Override DPD idle state with column 8 output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " KBC_COL7 ,Override DPD idle state with column 7 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " KBC_COL6 ,Override DPD idle state with column 6 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " KBC_COL5 ,Override DPD idle state with column 5 output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " KBC_COL4 ,Override DPD idle state with column 4 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " KBC_COL3 ,Override DPD idle state with column 3 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " KBC_COL2 ,Override DPD idle state with column 2 output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " KBC_COL1 ,Override DPD idle state with column 1 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " KBC_COL0 ,Override DPD idle state with column 0 output" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "DPD_SAMPLE_0,Deep power down sample"
|
|
bitfld.long 0x04 0. " ON ,Sampling of pads set value" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x08 "DPD_ENABLE_0,Deep power down enable register"
|
|
bitfld.long 0x08 1. " TSC_MULT_EN ,TSC multiplier enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ON ,Sampling of pads data trigger" "Disabled,Enabled"
|
|
textline " "
|
|
tree.end
|
|
tree "Power Control 1"
|
|
width 23.
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PWRGATE_TIMER_OFF_0,Power gate timer off register"
|
|
bitfld.long 0x00 28.--31. " RAIL7 ,Timer value for rail 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " RAIL6 ,Timer value for rail 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " RAIL5 ,Timer value for rail 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " RAIL4 ,Timer value for rail 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " RAIL3 ,Timer value for rail 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RAIL2 ,Timer value for rail 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " RAIL1 ,Timer value for rail 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RAIL0 ,Timer value for rail 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "CLAMP_STATUS_0,Clamp_Status_0 register"
|
|
bitfld.long 0x00 24. " IRAM ,Clamp status of IRAM partition" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " VIC ,Clamp status of VIC partition" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " XUSBC ,Clamp status of XUSBC partition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " XUSBB ,Clamp status of XUSBB partition" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " XUSBA ,Clamp status of XUSBA partition" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DISB ,Clamp status of DISB partition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DIS ,Clamp status of DIS partition" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SOR ,Clamp status of SOR partition" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " C1NC ,Clamp status of cluster1 nENABLE CPU partition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " C0NC ,Clamp status of cluster0 nENABLE CPU partition" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CE0 ,Clamp status of CE0 partition" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " CELP ,Clamp status of CELP partition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CE3 ,Clamp status of CE3 partition" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CE2 ,Clamp status of CE2 partition" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CE1 ,Clamp status of CE1 partition" "Diabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SAX ,Clamp status of SAX partition" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " HEG ,Clamp status of HEG partition" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MPE ,Clamp status of MPE partition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VDE ,Clamp status of VDE partition" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PCX ,Clamp status of PCX partition" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " VE ,Clamp status of VE partition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TD ,Clamp status of TD partition" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CRAIL ,Clamp status of CPU Rail" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "PWRGATE_TOGGLE_0,Power gate toggle"
|
|
bitfld.long 0x00 8. " START ,Start power down/up" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " PARTID ,ID of partition to be toggled" "CRAIL,TD,Video Encode,PCX,Video Decode,L2 Cache,MPEG Encode,HEG,SAX,CE1,CE2,CE3,CELP,CE0,C0NC,C1NC,SOR,DIS,DISB,XUSBA,XUSBB,XUSBC,VIC,IRAM,..."
|
|
textline " "
|
|
line.long 0x04 "REMOVE_CLAMPING_CMD_0,Clamping remove register"
|
|
bitfld.long 0x04 24. " IRAM ,Remove clamping from IRAM partition" "No,Yes"
|
|
bitfld.long 0x04 23. " VIC ,Remove clamping from VIC partition" "No,Yes"
|
|
bitfld.long 0x04 22. " XUSBC ,Remove clamping from XUSBC partition" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 21. " XUSBB ,Remove clamping from XUSBB partition" "No,Yes"
|
|
bitfld.long 0x04 20. " XUSBA ,Remove clamping from XUSBA partition" "No,Yes"
|
|
bitfld.long 0x04 19. " DISB ,Remove clamping from DISB partition" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 18. " DIS ,Remove clamping from DIS partition" "No,Yes"
|
|
bitfld.long 0x04 17. " SOR ,Remove clamping from SOR partition" "No,Yes"
|
|
bitfld.long 0x04 16. " C1NC ,Remove clamping form cluster 1 non-CPU partition" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 15. " C0NC ,Remove clamping from cluster 0 non-CPU partition" "No,Yes"
|
|
bitfld.long 0x04 14. " CE0 ,Remove clamping from CE0 partition" "No,Yes"
|
|
bitfld.long 0x04 12. " A9LP ,Remove clamping to A9LP" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CE3 ,Remove clamping to CE3" "No,Yes"
|
|
bitfld.long 0x04 10. " CE2 ,Remove clamping to CE2" "No,Yes"
|
|
bitfld.long 0x04 9. " CE1 ,Remove clamping to CE1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 8. " SAX ,Remove clamping to SAX" "No,Yes"
|
|
bitfld.long 0x04 7. " HEG ,Remove clamping to HEG" "No,Yes"
|
|
bitfld.long 0x04 5. " L2C ,Remove clamping to L2_CACHE" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PCX ,Remove clamping to PCX" "No,Yes"
|
|
bitfld.long 0x04 3. " VDE ,Remove clamping to VDE" "No,Yes"
|
|
bitfld.long 0x04 2. " VE ,Remove clamping to VE" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TD ,Remove clamping to TD" "No,Yes"
|
|
bitfld.long 0x04 0. " CRAIL ,Remove clamping to CPU Rail domain" "No,Yes"
|
|
textline " "
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "PWRGATE_STATUS_0,Power gate status"
|
|
bitfld.long 0x00 24. " IRAM ,Status of IRAM partition" "Off,On"
|
|
bitfld.long 0x00 23. " VIC ,Status of VIC partition" "Off,On"
|
|
bitfld.long 0x00 22. " XUSBC ,Status of XUSBC partition" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 21. " XUSBB ,Status of XUSBB partition" "Off,On"
|
|
bitfld.long 0x00 20. " XUSBA ,Status of XUSBA partition" "Off,On"
|
|
bitfld.long 0x00 19. " DISB ,Status of DISB partition" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DIS ,Status of DIS partition" "Off,On"
|
|
bitfld.long 0x00 17. " SOR ,Satus of SOR partition" "Off,On"
|
|
bitfld.long 0x00 16. " C1NC ,Status of cluster1 non_CPU partition" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 15. " C0NC ,Status of cluster0 non-CPU partition" "Off,On"
|
|
bitfld.long 0x00 14. " CE0 ,Status of CE0 partition" "Off,On"
|
|
bitfld.long 0x00 12. " CELP ,Status of CELP partition" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CE3 ,Status of CE3 partition" "Off,On"
|
|
bitfld.long 0x00 10. " CE2 ,Status of CE2 partition" "Off,On"
|
|
bitfld.long 0x00 9. " CE1 ,Status of CE1 partition" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SAX ,Status of SAX partition" "Off,On"
|
|
bitfld.long 0x00 7. " HEG ,Status of HEG partition" "Off,On"
|
|
bitfld.long 0x00 6. " MPE ,Status of MPE partition" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 5. " L2C ,Status of L2C partition" "Off,On"
|
|
bitfld.long 0x00 4. " VDE ,Status of VDE partition" "Off,On"
|
|
bitfld.long 0x00 3. " PCX ,Status of PCX partition" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VE ,Status of VE partition" "Off,On"
|
|
bitfld.long 0x00 1. " TD ,Status of TD partition" "Off,On"
|
|
bitfld.long 0x00 0. " CRAIL ,Status of CPU Rail partition" "Off,On"
|
|
textline " "
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "PWRGOOD_TIMER_0,Power good timer"
|
|
hexmask.long.byte 0x00 16.--23. 1. " OSC_PREPWR ,OSC clock stabilization timer prior to SoC pwr-req assertion"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OSC_POSTPWR ,OSC clock stabilization timer after SoC rail power stabilized"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PWRGOOD ,SoC rail power -on stabilization timer"
|
|
textline " "
|
|
line.long 0x04 "BLINK_TIMER_0,Blink timer"
|
|
hexmask.long.word 0x04 16.--31. 1. " DATA_OFF ,Time off"
|
|
bitfld.long 0x04 15. " FORCE_BLINK ,32 kHz clock select for output" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 0.--14. 1. " DATA_ON ,Time on"
|
|
textline " "
|
|
group.long 0x44++0x0B
|
|
line.long 0x00 "NO_IOPOWER_0,No I/O power register"
|
|
bitfld.long 0x00 17. " SYS_2 ,Rail AO I/Os" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " MEM_COMP , MEM0 ADDR1(comp cell I/Os)" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " HV ,Rail HV I/Os" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SDMMC4 ,Rail sdmmc4 I/Os" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SDMMC3 ,Rail sdmmc3 I/Os" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SDMMC1 ,Rail sdmmc1 I/Os" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PEX_CNTRL ,Rail pex_cntrl I/Os" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CAM ,Rail cam I/Os" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MIPI ,Rail mipi I/Os" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MEM ,Rail mem I/Os" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AUDIO ,Rail i2s I/Os" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VI ,Rail dvi I/Os" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BB ,Rail dlcd I/Os" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " UART ,Rail dbg I/Os" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NAND ,Rail at3 I/Os" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SYS ,Rail ao I/Os" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "PWR_DET_0,Power detect"
|
|
bitfld.long 0x04 17. " SYS_2 ,Rail AO I/Os" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " HV ,HV rail" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " SDMMC3 ,Rail sdmmc3 I/Os" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " SDMMC1 ,Rail sdmmc1 I/Os" "Enabled,Disabled"
|
|
bitfld.long 0x04 11. " PEX_CNTRL ,Rail pex_cntrl I/Os" "Enabled,Disabled"
|
|
bitfld.long 0x04 10. " CAM ,Rail cam I/Os" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " AUDIO ,Rail i2s I/Os" "Enabled,Disabled"
|
|
bitfld.long 0x04 3. " BB ,Rail dlcd I/Os" "Enabled,Disabled"
|
|
bitfld.long 0x04 2. " UART ,Rail dbg I/Os" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " NAND ,Rail at3 I/Os" "Enabled,Disabled"
|
|
bitfld.long 0x04 0. " SYS ,Rail ao I/Os" "Enabled,Disabled"
|
|
textline " "
|
|
line.long 0x08 "PWR_DET_LATCH_0,Power detect latch"
|
|
bitfld.long 0x08 0. " LATCH ,Power detect latch" "Enabled,Disabled"
|
|
textline " "
|
|
tree.end
|
|
tree "Scratch Registers 1"
|
|
width 22.
|
|
group.long 0x50++0x5F
|
|
line.long 0x0 "SCRATCH0_0,Scratch register 0"
|
|
line.long 0x4 "SCRATCH1_0,Scratch register 1"
|
|
line.long 0x8 "SCRATCH2_0,Scratch register 2"
|
|
line.long 0xC "SCRATCH3_0,Scratch register 3"
|
|
line.long 0x10 "SCRATCH4_0,Scratch register 4"
|
|
line.long 0x14 "SCRATCH5_0,Scratch register 5"
|
|
line.long 0x18 "SCRATCH6_0,Scratch register 6"
|
|
line.long 0x1C "SCRATCH7_0,Scratch register 7"
|
|
line.long 0x20 "SCRATCH8_0,Scratch register 8"
|
|
line.long 0x24 "SCRATCH9_0,Scratch register 9"
|
|
line.long 0x28 "SCRATCH10_0,Scratch register 10"
|
|
line.long 0x2C "SCRATCH11_0,Scratch register 11"
|
|
line.long 0x30 "SCRATCH12_0,Scratch register 12"
|
|
line.long 0x34 "SCRATCH13_0,Scratch register 13"
|
|
line.long 0x38 "SCRATCH14_0,Scratch register 14"
|
|
line.long 0x3C "SCRATCH15_0,Scratch register 15"
|
|
line.long 0x40 "SCRATCH16_0,Scratch register 16"
|
|
line.long 0x44 "SCRATCH17_0,Scratch register 17"
|
|
line.long 0x48 "SCRATCH18_0,Scratch register 18"
|
|
line.long 0x4C "SCRATCH19_0,Scratch register 19"
|
|
line.long 0x50 "SCRATCH20_0,Scratch register 20"
|
|
line.long 0x54 "SCRATCH21_0,Scratch register 21"
|
|
line.long 0x58 "SCRATCH22_0,Scratch register 22"
|
|
line.long 0x5C "SCRATCH23_0,Scratch register 23"
|
|
group.long 0xB0++0x17
|
|
line.long 0x0 "SECURE_SCRATCH0_0,Secure scratch register 0"
|
|
line.long 0x4 "SECURE_SCRATCH1_0,Secure scratch register 1"
|
|
line.long 0x8 "SECURE_SCRATCH2_0,Secure scratch register 2"
|
|
line.long 0xC "SECURE_SCRATCH3_0,Secure scratch register 3"
|
|
line.long 0x10 "SECURE_SCRATCH4_0,Secure scratch register 4"
|
|
line.long 0x14 "SECURE_SCRATCH5_0,Secure scratch register 5"
|
|
tree.end
|
|
tree "Power Control 2"
|
|
width 22.
|
|
group.long 0xC8++0x23
|
|
line.long 0x00 "CPUPWRGOOD_TIMER_0,CPU power good timer"
|
|
line.long 0x04 "CPUPWROFF_TIMER_0,CPU power off timer"
|
|
line.long 0x08 "PG_MASK_0,PG mask register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PCX ,Mask PCX rail"
|
|
hexmask.long.byte 0x08 16.--23. 1. " VD ,Mask BDE rail"
|
|
hexmask.long.byte 0x08 8.--15. 1. " VE ,Mask VE rail"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " TD ,Mask TD rail"
|
|
textline " "
|
|
line.long 0x0C "PG_MASK_1_0,PG mask 1 register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " SAX ,Mask SAX rail"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " HEG ,Mask HEG rail"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " MPE ,Mask MPE rail"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " L2C ,Mask L2C rail" "0,1"
|
|
textline " "
|
|
line.long 0x10 "AUTO_WAKE_LVL_0,Wake pads sampling control register"
|
|
bitfld.long 0x10 0. " SMPL ,Causes PMC to sample the wake pads" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x14 "AUTO_WAKE_LVL_MASK_0,Wake pads sampling enable register"
|
|
line.long 0x18 "WAKE_DELAY_0,Wake delay control register"
|
|
hexmask.long.word 0x18 0.--15. 1. " VALUE ,Delay value"
|
|
textline " "
|
|
line.long 0x1C "PWR_DET_VAL_0,Power detect cells control register"
|
|
bitfld.long 0x1C 17. " SYS_2 ,Rail AO I/Os " "Enabled,Disabled"
|
|
bitfld.long 0x1C 15. " HV ,Rail HV I/Os" "Enabled,Disabled"
|
|
bitfld.long 0x1C 13. " SDMMC3 ,Rail sdmmc3 I/Os" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " SDMMC1 ,Rail sdmmc1 I/Os" "Enabled,Disabled"
|
|
bitfld.long 0x1C 11. " PEX_CNTRL ,Rail pex_cntrl I/Os" "Enabled,Disabled"
|
|
bitfld.long 0x1C 10. " CAM ,Rail cam I/Os" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x1C 5. " AUDIO ,Rail i2s I/Os" "Enabled,Disabled"
|
|
bitfld.long 0x1C 3. " BB ,Rail dlcd I/Os" "Enabled,Disabled"
|
|
bitfld.long 0x1C 2. " UART ,Rail dbg I/Os" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " NAND ,Rail at3 I/Os" "Enabled,Disabled"
|
|
bitfld.long 0x1C 0. " SYS ,Rail ao I/Os" "Enabled,Disabled"
|
|
textline " "
|
|
line.long 0x20 "DDR_PWR_0,E_18V pin from DDR pads control register"
|
|
bitfld.long 0x20 1. " EMMC ,GMI pins set" "E_12V,E_18V"
|
|
bitfld.long 0x20 0. " VAL ,DVI pins set" "E_12V,E_18V"
|
|
textline " "
|
|
group.long 0xEC++0x0F
|
|
line.long 0x00 "USB_DEBOUNCE_DEL_0,Clock cycles for USB signal events debouncing"
|
|
bitfld.long 0x00 20.--23. " UHSIC_LINE_DEB_CNT ,Number of 32kHz debounce cycles for UHSIC port 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " UTMIP_LINE_DEB_CNT ,Number of 32kHz debounce cycles for UTMIP port 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " VAL ,Debounce period for ID and VBUS events"
|
|
textline " "
|
|
line.long 0x04 "USB_AO_0,Power down for various USB features"
|
|
bitfld.long 0x04 17. " DATA_VAl_PD_P1 ,Power Down D-Data_Val receiver for UHSIC P1" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " STROBE_VAL_PD_P1 ,Power Down Strobe_Val receiver for UHSIC P1" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " DATA_VAL_PD_P0 ,Power down D- DATA_VAL receiver for UHSIC P0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " STROBE_VAL_PD_P0 ,Power down Power down D+ STROBE_VAL receiver for UHSIC P0" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " ID_PD_P2 ,Power down D Wake up for UTMIP" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VBUS_WAKEUP_PD_P2 ,Power down Vbus Wake Up for UTMIP P2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " USBON_VAL_PD_P2 ,Power down D- USBOP_VAL receiver for UTMIP P0" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " USBOP_VAL_PD_P2 ,D+ USBOP_VAL receiver for UTMIP P0" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " ID_PD_P1 ,Power down ID Wake up for UTMIP P1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " VBUS_WAKEUP_PD_P1 ,Power Down Vbus Wake Up for UTMIP P1" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " USBON_VAL_PD_P1 ,Power down D- USBOP_VAL receiver for UTMIP P0" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " USBOP_VAL_PD_P1 ,Power down D+ USBOP_VAL receiver for UTMIP P0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ID_PD_P0 ,Power down ID Wake up for UTMIP" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " VBUS_WAKEUP_PD_P0 ,Power down Vbus Wake Up for UTMIP P0" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " USBON_VAL_PD_P0 ,Power down D- USBOP_VAL receiver for UTMIP P0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " USBOP_VAL_PD_P0 ,Power down D+ USBOP_VAL receiver for UTMIP P0" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x08 "CRYPTO_OP_0,Crypto engine disable sticky register"
|
|
bitfld.long 0x08 0. " VAL ,Crypto engine disable" "Enabled,Disabled"
|
|
textline " "
|
|
line.long 0x0C "PLLP_WB0_OVERRIDE_0,Master control for all wb0 pll override"
|
|
bitfld.long 0x0C 12. " PLLM_ENABLE ,PLLM enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " PLLM_OVERRIDE_ENABLE ,PLLM override enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " PLLU_ENABLE ,PLLU enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " PLLU_OVERRIDE_ENABLE ,PLLU override enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " OSC_OVERRIDE_ENABLE ,OSC override enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6.--7. " PLL_REF_DIV ,PLL reference clock divide for all pll's" "/1,/2,/4,"
|
|
textline " "
|
|
bitfld.long 0x0C 2.--5. " OSC_FREQ ,Oscillator frequency for shared pll reference" "13 MHz,16.8 MHz,,,19.2 MHz,38.4 MHz,,,12 MHz,48 MHz,,,26 Mhz,,,"
|
|
bitfld.long 0x0C 1. " PLLP_ENABLE ,PLLE enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PLLP_OVERRIDE_ENABLE ,PLLP override enable" "Disabled,Enabled"
|
|
textline " "
|
|
tree.end
|
|
tree "Scratch Registers 2"
|
|
width 25.
|
|
group.long 0xFC++0x4B
|
|
line.long 0x0 "SCRATCH24_0,Scratch register 24"
|
|
line.long 0x4 "SCRATCH25_0,Scratch register 25"
|
|
line.long 0x8 "SCRATCH26_0,Scratch register 26"
|
|
line.long 0xC "SCRATCH27_0,Scratch register 27"
|
|
line.long 0x10 "SCRATCH28_0,Scratch register 28"
|
|
line.long 0x14 "SCRATCH29_0,Scratch register 29"
|
|
line.long 0x18 "SCRATCH30_0,Scratch register 30"
|
|
line.long 0x1C "SCRATCH31_0,Scratch register 31"
|
|
line.long 0x20 "SCRATCH32_0,Scratch register 32"
|
|
line.long 0x24 "SCRATCH33_0,Scratch register 33"
|
|
line.long 0x28 "SCRATCH34_0,Scratch register 34"
|
|
line.long 0x2C "SCRATCH35_0,Scratch register 35"
|
|
line.long 0x30 "SCRATCH36_0,Scratch register 36"
|
|
line.long 0x34 "SCRATCH37_0,Scratch register 37"
|
|
line.long 0x38 "SCRATCH38_0,Scratch register 38"
|
|
line.long 0x3C "SCRATCH39_0,Scratch register 39"
|
|
line.long 0x40 "SCRATCH40_0,Scratch register 40"
|
|
line.long 0x44 "SCRATCH41_0,Scratch register 41"
|
|
line.long 0x48 "SCRATCH42_0,Scratch register 42"
|
|
group.long 0x148++0x0B
|
|
line.long 0x0 "BONDOUT_MIRROR0_0,Secure scratch register 0"
|
|
line.long 0x4 "BONDOUT_MIRROR1_0,Secure scratch register 1"
|
|
line.long 0x8 "BONDOUT_MIRROR2_0,Secure scratch register 2"
|
|
group.long 0x154++0x0B
|
|
line.long 0x00 "SYS_33V_EN_0,Voltage select"
|
|
bitfld.long 0x00 0. " VAL ,Voltage value select" "1.8 V,3.3 V"
|
|
line.long 0x04 "BONDOUT_MIRROR_ACCESS_0,Write and read control for bondout secure registers"
|
|
bitfld.long 0x04 1. " BREAD ,Disable read from bondout secure registers" "No,Yes"
|
|
bitfld.long 0x04 0. " BWRITE ,Disable write to bondout secure registers" "No,Yes"
|
|
line.long 0x08 "GATE_0,APBDEV gate wake "
|
|
bitfld.long 0x08 0. " GATE_WAKE ,Gate_Wake" "Off,On"
|
|
tree.end
|
|
tree "Wake Control 2"
|
|
width 20.
|
|
group.long 0x160++0x0F
|
|
line.long 0x00 "WAKE2_MASK_0,Wake-up event mask"
|
|
bitfld.long 0x00 26. " WAKE2_[26] ,Wake enable for 2pmc_xusb_system_wakeup event" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " WAKE2_[25] ,Wake enable for spdif_in event" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " WAKE2_[24] ,Wake enable for sdmmc3_cd_n event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WAKE2_[23] ,Wake enable fort uart3_cts_n event" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WAKE2_[22] ,Wake enable for kb_col5 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WAKE2_[21] ,Wake enable for cam_i2c_scl event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WAKE2_[20] ,Wake enable for hdmi_cec event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " WAKE2_[19] ,Wake enable for kb_col0 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " WAKE2_[18] ,Wake enable for kb_row4 event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " WAKE2_[17] ,Wake enable for kb_row7 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " WAKE2_[16] ,Wake enable for cam_i2c_sda event" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WAKE2_[15] ,Wake enable for gen2_i2c_sda event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " WAKE2_[14] ,Wake enable for pwr_i2c_sda event" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " WAKE2_[13] ,Wake enable for gpio_pbb6 event" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WAKE2_[12] ,Wake enable for gen1_i2c1_sda event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE2_[11] ,Wake enable for uhsic2_line_wakeup_event" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " WAKE2_[10] ,Wake enable for uhsic_line_wakeup_event " "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " WAKE2_[9] ,Wake enable for utmip2_line_wakeup_event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WAKE2_[8] ,Wake enable for utmip1_line_wakeup event" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " WAKE2_[7] ,Wake enable for utmip0_line_wakeup_event" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " WAKE2_[3] ,Wake enable for gpio_pi[6] event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WAKE2_[2] ,Wake enable for gpio_pk[2] event" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WAKE2_[1] ,Wake enable for gpio_pj[0]" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WAKE2_[0] ,Wake enable for ulpi_data3" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "WAKE2_LVL_0,PMC wake level"
|
|
bitfld.long 0x04 26. " WAKE2_[26] ,Active wake level for 2pmc_xusb_system_wakeup event" "Low,High"
|
|
bitfld.long 0x04 25. " WAKE2_[25] ,Active wake level for spdif_in event" "Low,High"
|
|
bitfld.long 0x04 24. " WAKE2_[24] ,Active wake level for sdmmc3_cd_n event" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 23. " WAKE2_[23] ,Active wake level fort uart3_cts_n event" "Low,High"
|
|
bitfld.long 0x04 22. " WAKE2_[22] ,Active wake level for kb_col5 event" "Low,High"
|
|
bitfld.long 0x04 21. " WAKE2_[21] ,Active wake level for cam_i2c_scl event" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 20. " WAKE2_[20] ,Active wake level for hdmi_cec event" "Low,High"
|
|
bitfld.long 0x04 19. " WAKE2_[19] ,Active wake level for kb_col0 event" "Low,High"
|
|
bitfld.long 0x04 18. " WAKE2_[18] ,Active wake level for kb_row4 event" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 17. " WAKE2_[17] ,Active wake level for kb_row7 event" "Low,High"
|
|
bitfld.long 0x04 16. " WAKE2_[16] ,Active wake level for cam_i2c_sda event" "Low,High"
|
|
bitfld.long 0x04 15. " WAKE2_[15] ,Active wake level for gen2_i2c_sda event" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 14. " WAKE2_[14] ,Active wake level for pwr_i2c_sda event" "Low,High"
|
|
bitfld.long 0x04 13. " WAKE2_[13] ,Active wake level for gpio_pbb6 event" "Low,High"
|
|
bitfld.long 0x04 12. " WAKE2_[12] ,Active wake level for gen1_i2c1_sda event" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 11. " WAKE2_[11] ,Active wake level for uhsic2_line_wakeup_event" "Low,High"
|
|
bitfld.long 0x04 10. " WAKE2_[10] ,Active wake level for uhsic_line_wakeup_event " "Low,High"
|
|
bitfld.long 0x04 9. " WAKE2_[9] ,Active wake level for utmip2_line_wakeup_event" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAKE2_[8] ,Active wake level for utmip1_line_wakeup event" "Low,High"
|
|
bitfld.long 0x04 7. " WAKE2_[7] ,Active wake level for utmip0_line_wakeup_event" "Low,High"
|
|
bitfld.long 0x04 3. " WAKE2_[3] ,Active wake level for gpio_pi[6] event" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 2. " WAKE2_[2] ,Active wake level for gpio_pk[2] event" "Low,High"
|
|
bitfld.long 0x04 1. " WAKE2_[1] ,Active wake level for gpio_pj[0]" "Low,High"
|
|
bitfld.long 0x04 0. " WAKE2_[0] ,Active wake level for ulpi_data3" "Low,High"
|
|
textline " "
|
|
line.long 0x08 "WAKE2_STATUS_0,PMC wake status"
|
|
eventfld.long 0x08 26. " WAKE2_[26] ,Wake status for 2pmc_xusb_system_wakeup event" "Not set,Set"
|
|
eventfld.long 0x08 25. " WAKE2_[25] ,Wake status level for spdif_in event" "Not set,Set"
|
|
eventfld.long 0x08 24. " WAKE2_[24] ,Wake status level for sdmmc3_cd_n event" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x08 23. " WAKE2_[23] ,Wake status level fort uart3_cts_n event" "Not set,Set"
|
|
eventfld.long 0x08 22. " WAKE2_[22] ,Wake status level for kb_col5 event" "Not set,Set"
|
|
eventfld.long 0x08 21. " WAKE2_[21] ,Wake status level for cam_i2c_scl event" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x08 20. " WAKE2_[20] ,Wake status level for hdmi_cec event" "Not set,Set"
|
|
eventfld.long 0x08 19. " ,Wake status level for kb_col0 event" "Not set,Set"
|
|
eventfld.long 0x08 18. " WAKE2_[18] ,Wake status level for kb_row4 event" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x08 17. " WAKE2_[17] ,Wake status level for kb_row7 event" "Not set,Set"
|
|
eventfld.long 0x08 16. " WAKE2_[16] ,Wake status level for cam_i2c_sda event" "Not set,Set"
|
|
eventfld.long 0x08 15. " WAKE2_[15] ,Wake status level for gen2_i2c_sda event" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x08 14. " WAKE2_[14] ,Wake status level for pwr_i2c_sda event" "Not set,Set"
|
|
eventfld.long 0x08 13. " WAKE2_[13] ,Wake status level for gpio_pbb6 event" "Not set,Set"
|
|
eventfld.long 0x08 12. " WAKE2_[12] ,Wake status level for gen1_i2c1_sda event" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x08 11. " WAKE2_[11] ,Wake status level for uhsic2_line_wakeup_event" "Not set,Set"
|
|
eventfld.long 0x08 10. " WAKE2_[10] ,Wake status level for uhsic_line_wakeup_event " "Not set,Set"
|
|
eventfld.long 0x08 9. " WAKE2_[9] ,Wake status level for utmip2_line_wakeup_event" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x08 8. " WAKE2_[8] ,Wake status level for utmip1_line_wakeup event" "Not set,Set"
|
|
eventfld.long 0x08 7. " WAKE2_[7] ,Wake status level for utmip0_line_wakeup_event" "Not set,Set"
|
|
eventfld.long 0x08 3. " WAKE2_[3] ,Wake status level for gpio_pi[6] event" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x08 2. " WAKE2_[2] ,Wake status level for gpio_pk[2] event" "Not set,Set"
|
|
eventfld.long 0x08 1. " WAKE2_[1] ,Wake status level for gpio_pj[0]" "Not set,Set"
|
|
eventfld.long 0x08 0. " WAKE2_[0] ,Wake status level for ulpi_data3" "Not set,Set"
|
|
textline " "
|
|
line.long 0x0C "SW_WAKE2_STATUS_0,PMC software wake status"
|
|
eventfld.long 0x0C 26. " WAKE2_[26] ,Wake status for 2pmc_xusb_system_wakeup event" "Not set,Set"
|
|
eventfld.long 0x0C 25. " WAKE2_[25] ,Wake status level for spdif_in event" "Not set,Set"
|
|
eventfld.long 0x0C 24. " WAKE2_[24] ,Wake status level for sdmmc3_cd_n event" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x0C 23. " WAKE2_[23] ,Wake status level fort uart3_cts_n event" "Not set,Set"
|
|
eventfld.long 0x0C 22. " WAKE2_[22] ,Wake status level for kb_col5 event" "Not set,Set"
|
|
eventfld.long 0x0C 21. " WAKE2_[21] ,Wake status level for cam_i2c_scl event" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x0C 20. " WAKE2_[20] ,Wake status level for hdmi_cec event" "Not set,Set"
|
|
eventfld.long 0x0C 19. " ,Wake status level for kb_col0 event" "Not set,Set"
|
|
eventfld.long 0x0C 18. " WAKE2_[18] ,Wake status level for kb_row4 event" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x0C 17. " WAKE2_[17] ,Wake status level for kb_row7 event" "Not set,Set"
|
|
eventfld.long 0x0C 16. " WAKE2_[16] ,Wake status level for cam_i2c_sda event" "Not set,Set"
|
|
eventfld.long 0x0C 15. " WAKE2_[15] ,Wake status level for gen2_i2c_sda event" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x0C 14. " WAKE2_[14] ,Wake status level for pwr_i2c_sda event" "Not set,Set"
|
|
eventfld.long 0x0C 13. " WAKE2_[13] ,Wake status level for gpio_pbb6 event" "Not set,Set"
|
|
eventfld.long 0x0C 12. " WAKE2_[12] ,Wake status level for gen1_i2c1_sda event" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x0C 11. " WAKE2_[11] ,Wake status level for uhsic2_line_wakeup_event" "Not set,Set"
|
|
eventfld.long 0x0C 10. " WAKE2_[10] ,Wake status level for uhsic_line_wakeup_event " "Not set,Set"
|
|
eventfld.long 0x0C 9. " WAKE2_[9] ,Wake status level for utmip2_line_wakeup_event" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x0C 8. " WAKE2_[8] ,Wake status level for utmip1_line_wakeup event" "Not set,Set"
|
|
eventfld.long 0x0C 7. " WAKE2_[7] ,Wake status level for utmip0_line_wakeup_event" "Not set,Set"
|
|
eventfld.long 0x0C 3. " WAKE2_[3] ,Wake status level for gpio_pi[6] event" "Not set,Set"
|
|
textline " "
|
|
eventfld.long 0x0C 2. " WAKE2_[2] ,Wake status level for gpio_pk[2] event" "Not set,Set"
|
|
eventfld.long 0x0C 1. " WAKE2_[1] ,Wake status level for gpio_pj[0]" "Not set,Set"
|
|
eventfld.long 0x0C 0. " WAKE2_[0] ,Wake status level for ulpi_data3" "Not set,Set"
|
|
textline " "
|
|
tree.end
|
|
tree "Power gate"
|
|
width 22.
|
|
group.long 0x174++0x0F
|
|
line.long 0x00 "PG_MASK_2_0,PG mask register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IRAM ,Mask IRAm rail"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIC ,Mask CELP rail"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CELP ,Mask CELP rail"
|
|
line.long 0x4 "PG_MASK_CE1_0,CE1 rail mask"
|
|
hexmask.long.byte 0x4 0.--7. 1. " MASK ,Mask CE1 rail"
|
|
line.long 0x8 "PG_MASK_CE2_0,CE2 rail mask"
|
|
hexmask.long.byte 0x8 0.--7. 1. " MASK ,Mask CE1 rail"
|
|
line.long 0xC "PG_MASK_CE3_0,CE3 rail mask"
|
|
hexmask.long.byte 0xC 0.--7. 1. " MASK ,Mask CE1 rail"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "PWRGATE_TIMER_CE_0_0,Power gate timer value for CE 0 counter"
|
|
bitfld.long 0x00 28.--31. " RAIL7 ,Timer Value for rail 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " RAIL6 ,Timer Value for rail 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " RAIL5 ,Timer Value for rail 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " RAIL4 ,Timer Value for rail 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " RAIL3 ,Timer Value for rail 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RAIL2 ,Timer value for rail 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " RAIL1 ,Timer value for rail 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RAIL0 ,Timer value for rail" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Power Control 3"
|
|
width 17.
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "OSC_EDPD_OVER_0,Oscillator control in LP0 mode"
|
|
bitfld.long 0x00 23. " CLK_OK ,Crystal oscillator clk_ok signal" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " OSC_CTRL_SELECT ,Oscillator cell control" "CAR,PMC"
|
|
bitfld.long 0x00 20.--21. " XO_LP0_MODE ,Controls oscillator during LP0" "DPD,Off,On,EXT_REQ"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--19. 1. " OSCFI_SPARE ,Crystal oscillator spare register control"
|
|
hexmask.long.byte 0x00 7.--11. 1. " XODS ,Crystal oscillator duty cycle control"
|
|
hexmask.long.byte 0x00 1.--6. 1. " XOFS ,Crystal oscillator drive strength control"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XOBP ,Crystal oscillator bypass enable" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "CLK_OUT_CNTRL_0,Clock outputs control register"
|
|
bitfld.long 0x04 22.--23. " CLK3_SRC_SEL ,Clock 3 source select" "OSC_DIV1,OSC_DIV2,OSC_DIV3,CAR"
|
|
bitfld.long 0x04 20.--21. " CLK3_IDLE_STATE ,Clock 3 idle state" "Low,High,Tris,"
|
|
bitfld.long 0x04 18. " CLK3_FORCE_EN ,Force clock running regardless of ACCEPT_REQ or INVERT_REQ" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 17. " CLK3_INVERT_REQ ,Clock 3 invert" "Not inverted,Inverted"
|
|
bitfld.long 0x04 16. " CLK3_ACCEPT_REQ ,Clock 3 accept" "No accepted,Accepted"
|
|
bitfld.long 0x04 14.--15. " CLK2_SRC_SEL ,Clock 2 source select" "OSC_DIV1,OSC_DIV2,OSC_DIV3,CAR"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " CLK2_IDLE_STATE ,Clock 2 idle state" "Low,High,Tris,"
|
|
bitfld.long 0x04 10. " CLK2_FORCE_EN ,Force clock running regardless of ACCEPT_REQ or INVERT_REQ" "Not forced,Forced"
|
|
bitfld.long 0x04 9. " CLK2_INVERT_REQ ,Clock 2 invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x04 8. " CLK2_ACCEPT_REQ ,Clock 2 accept" "No accepted,Accepted"
|
|
bitfld.long 0x04 6.--7. " CLK1_SRC_SEL ,Clock 1 source select" "OSC_DIV1,OSC_DIV2,OSC_DIV3,CAR"
|
|
bitfld.long 0x04 4.--5. " CLK1_IDLE_STATE ,Clock 1 idle state" "Low,High,Tris,"
|
|
textline " "
|
|
bitfld.long 0x04 2. " CLK1_FORCE_EN ,Force clock running regardless of ACCEPT_REQ or INVERT_REQ" "Not forced,Forced"
|
|
bitfld.long 0x04 1. " CLK1_INVERT_REQ ,Clock 1 invert" "Not inverted,Inverted"
|
|
bitfld.long 0x04 0. " CLK1_ACCEPT_REQ ,Clock 1 accept" "No accepted,Accepted"
|
|
textline " "
|
|
line.long 0x08 "SENSOR_CTRL_0,Sensor shutdown and control"
|
|
bitfld.long 0x08 2. " BLOCK_SCRATCH_WRITE ,Block writes to scratch registers" "Off,On"
|
|
bitfld.long 0x08 1. " ENABLE_RST ,Enables reset on sensor going up" "Off,On"
|
|
bitfld.long 0x08 0. " ENABLE_PG ,Power gate cpus on temp sensor going up" "Off,On"
|
|
textline " "
|
|
line.long 0x0C "RST_STATUS_0,Simplified reset and reset source"
|
|
bitfld.long 0x0C 0.--2. " RST_SOURCE ,Source of reset" "POR,Watchdog,Sensor,SW_MAIN,LP0,..."
|
|
textline " "
|
|
tree.end
|
|
tree "IO DPD Control"
|
|
width 18.
|
|
group.long 0x1B8++0x13
|
|
line.long 0x00 "IO_DPD_REQ_0,DPD request"
|
|
bitfld.long 0x00 30.--31. " CODE ,Code of operation for all set bits" "IDLE,DPD_OFF,DPD_ON,"
|
|
bitfld.long 0x00 28. " HDMI ,Puts HDMI in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x00 22. " COMP ,COMP in deep power down mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 19. " HSIC ,Puts HSIC in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x00 17. " AUDIO ,Puts AUDIO in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x00 15. " BB ,Puts BB in/out of deep power down mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 14. " UART ,Puts UART in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x00 13. " NAND ,Puts NAND in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x00 12. " USB_BIAS ,Puts USB_BIAS in/out of deep power down mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 11. " USB2 ,Puts USB2 in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x00 10. " USB1 ,Puts USB1 in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x00 9. " USB0 ,Puts USB0 in/out of deep power down mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PEX_CLK2 ,Puts PEX_CLK2 in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x00 5. " PEX_CLK1 ,Puts PEX_CLK1 in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x00 4. " PEX_BIAS ,Puts PEX_BIAS in/out of deep power down mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MIPI_BIAS ,Puts MIPI_BIAS in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x00 2. " DSI ,Puts DSI in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x00 1. " CSIB ,Puts CSIB in/out of deep power down mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CSIA ,Puts CSIA in/out of deep power down mode" "Off,On"
|
|
textline " "
|
|
line.long 0x04 "IO_DPD_STATUS_0,DPD status"
|
|
bitfld.long 0x04 28. " HDMI ,HDMI in deep power down mode" "Off,On"
|
|
bitfld.long 0x04 22. " COMP ,COMP in deep power down mode" "Off,On"
|
|
bitfld.long 0x04 19. " HSIC ,HSIC in deep power down mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 17. " AUDIO ,AUDIO in deep power down mode" "Off,On"
|
|
bitfld.long 0x04 16. " VI ,VI in deep power down mode" "Off,On"
|
|
bitfld.long 0x04 15. " BB ,BB in deep power down mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 14. " UART ,UART in deep power down mode" "Off,On"
|
|
bitfld.long 0x04 13. " NAND ,NAND in deep power down mode" "Off,On"
|
|
bitfld.long 0x04 12. " USB_BIAS ,USB_BIAS in deep power down mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 11. " USB2 ,USB2 in deep power down mode" "Off,On"
|
|
bitfld.long 0x04 10. " USB1 ,USB1 in deep power down mode" "Off,On"
|
|
bitfld.long 0x04 9. " USB0 ,USB0 in deep power down mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 6. " PEX_CLK2 ,PEX_CLK2 in deep power down mode" "Off,On"
|
|
bitfld.long 0x04 5. " PEX_CLK1 ,PEX_CLK1 in deep power down mode" "Off,On"
|
|
bitfld.long 0x04 4. " PEX_BIAS ,PEX_BIAS in deep power down mode" "Off,On"
|
|
textline " "
|
|
rbitfld.long 0x04 3. " MIPI_BIAS ,MIPI_BIAS in deep power down mode" "Off,On"
|
|
rbitfld.long 0x04 2. " DSI ,DSI in deep power down mode" "Off,On"
|
|
rbitfld.long 0x04 1. " CSIB ,CSIB in deep power down mode" "Off,On"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " CSIA ,CSIA in deep power down mode" "Off,On"
|
|
textline " "
|
|
line.long 0x08 "IO_DPD2_REQ_0,DPD request 2"
|
|
bitfld.long 0x08 30.--31. " CODE ,Code of operation for all set bits" "IDLE,DPD_OFF,DPD_ON,"
|
|
bitfld.long 0x08 26. " SYS_DDC ,Direct DC pads" "Off,On"
|
|
bitfld.long 0x08 25. " LVDS ,LVDS is in DPD by default" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x08 12. " CSIE ,CSIE in/out of deep power mode" "Off,On"
|
|
bitfld.long 0x08 9. " DSID ,Puts DSID in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x08 8. " DSIC ,Puts DSIC in/out of deep power down mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DSIB ,Puts DSIB in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x08 6. " HV ,Puts HV rail in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x08 5. " RES_RAIL , Res rail" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CAM ,Puts CAM in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x08 3. " SDMMC4 ,Puts SDMMC4 in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x08 2. " SDMMC3 ,Puts SDMMC3 in/out of deep power down mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SDMMC1 ,Puts SDMMC1 in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x08 0. " PEX_CNTRL ,Puts PEX_CNTRL in/out of deep power down mode" "Off,On"
|
|
textline " "
|
|
line.long 0x0C "IO_DPD2_STATUS_0,DPD status 2"
|
|
bitfld.long 0x0C 26. " SYS_DDC ,DC direct pads" "Off,On"
|
|
bitfld.long 0x0C 25. " LVDS ,LVDS is in DPD by default" "Off,On"
|
|
bitfld.long 0x0C 12. " CSIE ,CSIE in/out of deep power down mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CSID ,CSID in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x0C 10. " CSIC ,CSIC in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x0C 9. " DSID ,DSID in/out of deep power down mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " DSIC ,DSIC in/out of deep power down mode" "Off,On"
|
|
bitfld.long 0x0C 7. " DSIB ,DSI in deep power down mode" "Off,On"
|
|
bitfld.long 0x0C 6. " HV ,HV rail in/out of deep power down mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CAM ,CAM in deep power down mode" "Off,On"
|
|
bitfld.long 0x0C 3. " SDMMC4 ,SDMMC4 in deep power down mode" "Off,On"
|
|
bitfld.long 0x0C 2. " SDMMC3 ,SDMMC3 in deep power down mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SDMMC1 ,SDMMC1 in deep power down mode" "Off,On"
|
|
bitfld.long 0x0C 0. " PEX_CNTRL ,PEX_CNTRL in deep power down mode" "Off,On"
|
|
textline " "
|
|
line.long 0x10 "SEL_DPD_TIM_0,Timer for e_dpd and sel_dpd deassertion times separation"
|
|
hexmask.long.byte 0x10 0.--6. 1. " SEL_DPD_TIM ,Timer which separates e_dpd deassertion time from sel_dpd deassertion time"
|
|
textline " "
|
|
tree.end
|
|
tree "Power Control 4"
|
|
width 26.
|
|
group.long 0x1CC++0x07
|
|
line.long 0x00 "VDDP_SEL_0,Power set for new DDR pads"
|
|
bitfld.long 0x00 0.--1. " DATA ,VDDP sel bits to ddr pads" "00,01,10,11"
|
|
textline " "
|
|
line.long 0x04 "DDR_CFG_0,Package type for CAR/PMC control"
|
|
bitfld.long 0x04 17. " XM0_MCKE_B1_TRI ,Tristate conttrol for xm2_mcke_b_1_pad" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " XM0_MCKE_B0_TRI ,Tristate control for xm2_mcke_b_0_pad" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " XM0_MCKE1_TRI , Tristate control for xm2_mcke_o_pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14. " XM0_MCKE0_TRI ,Tristate control for xm2_mcke_0_pad" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " XM0_RESET_DPDIO_0 ,DPD output control for reset pad" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XM0_RESET_TRI ,Tristate control reset pad" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x1DC++0x0F
|
|
line.long 0x00 "PLLM_WB0_OVERRIDE_FREQ_0,PLL WB override register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PLLM_DIVN ,PLLM feedback divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PLLM_DIVM ,PLL input divider"
|
|
textline " "
|
|
line.long 0x04 "TEST_PWRGATE_0,Force test power gate override"
|
|
bitfld.long 0x04 4. " RESET_DEBUG ,Used for debug,assertion of reset" "Off,On"
|
|
bitfld.long 0x04 3. " DPD_ENABLE_DEBUG ,Used for debug,assertion of dpd_enable" "Off,On"
|
|
bitfld.long 0x04 2. " MAIN_CLAMP_DEBUG ,Used for debug,assertion of main clamp" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " OP ,Force power gated partition" "None,FORCE_ON,FORCE_OFF,"
|
|
textline " "
|
|
line.long 0x08 "PWRGATE_TIMER_MULT_0,Multiple power gating control"
|
|
bitfld.long 0x08 3.--5. " MULT_CPU ,Multiplier for CPU" "1,2,4,8,16,..."
|
|
bitfld.long 0x08 0.--2. " MULT ,Time multiplier for each rail" "1,2,4,8,16,..."
|
|
textline " "
|
|
line.long 0x0C "DSI_SEL_DPD_0,SEL_DPD for DSI pad control"
|
|
bitfld.long 0x0C 3. " SET_DSID ,DSID set" "Off,On"
|
|
bitfld.long 0x0C 2. " SET_DSIC ,DSIC set " "Off,On"
|
|
bitfld.long 0x0C 1. " SET_DSIB ,DSIB set " "Off,On"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " SET_DSIA ,DSIA set" "Off,On"
|
|
textline " "
|
|
tree.end
|
|
tree "UTMIP & UHSIC Control"
|
|
width 29.
|
|
group.long 0x1EC++0x07
|
|
line.long 0x00 "UTMIP_UHSIC_TRIGGERS_0,Triggers for USB ports"
|
|
bitfld.long 0x00 15. " UHSIC_CLR_WAKE_ALARM_P0 ,Clear wake event for UHSIC port 0" "Null,Trig"
|
|
bitfld.long 0x00 14. " UTMIP_CLR_WAKE_ALARM_P2 ,Clear wake event for UTMIP port 2" "Null,Trig"
|
|
textline " "
|
|
bitfld.long 0x00 13. " UTMIP_CLR_WAKE_ALARM_P1 ,Clear wake event for UTMIP port 1" "Null,Trig"
|
|
bitfld.long 0x00 12. " UTMIP_CLR_WAKE_ALARM_P0 ,Clear wake event for UTMIP port 0" "Null,Trig"
|
|
textline " "
|
|
bitfld.long 0x00 11. " UHSIC_FORCE_WALK_P0 ,Force pointer walk for UHSIC port 0" "Null,Trig"
|
|
bitfld.long 0x00 10. " UTMIP_FORCE_WALK_P2 ,Force pointer walk for UTMIP port 2" "Null,Trig"
|
|
textline " "
|
|
bitfld.long 0x00 9. " UTMIP_FORCE_WALK_P1 ,Force pointer walk for UTMIP port 1" "Null,Trig"
|
|
bitfld.long 0x00 8. " UTMIP_FORCE_WALK_P0 ,Force pointer walk for UTMIP port 0" "Null,Trig"
|
|
textline " "
|
|
bitfld.long 0x00 6. " UTMIP_CAP_CFG_P2 ,Capture pad configuration for UTMIP port 2" "Null,Trig"
|
|
bitfld.long 0x00 5. " UTMIP_CAP_CFG_P1 ,Capture pad configuration for UTMIP port 1" "Null,Trig"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UTMIP_CAP_CFG_P0 ,Capture pad configuration for UTMIP port 0" "Null,Trig"
|
|
bitfld.long 0x00 3. " UHSIC_CLR_WALK_PTR_P0 ,Clear sleep walk pointer for UHSIC port 0" "Null,Trig"
|
|
textline " "
|
|
bitfld.long 0x00 2. " UTMIP_CLR_WALK_PTR_P2 ,Clear sleep walk pointer for UTMIP port 2" "Null,Trig"
|
|
bitfld.long 0x00 1. " UTMIP_CLR_WALK_PTR_P1 ,Clear sleep walk pointer for UTMIP port 1" "Null,Trig"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UTMIP_CLR_WALK_PTR_P0 ,Clear sleep walk pointer for UTMIP port 0" "Null,Trig"
|
|
line.long 0x04 "UTMIP_UHSIC_SAVED_STATE_0,Saved DPD state for all UTMIP and UHSIC ports"
|
|
bitfld.long 0x04 31. " UHSIC_WAKE_EX_P0 ,Wake up on anything except a Particular Line Value (P0)" "Off,On"
|
|
bitfld.long 0x04 30. " UHSIC_IGNORE_MASTER_CFG_P0 ,UHSIC ignore master config (P0)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 25.--29. " UHSIC_SCRATCH_P0 ,Scratch information about P0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 24. " UHSIC_MODE_P0 ,UHSIC speed prior to DPD" "HS,RST"
|
|
textline " "
|
|
bitfld.long 0x04 23. " UTMIP_WAKE_EX_P2 ,Wake up on anything except a Particular Line Value (P2)" "Off,On"
|
|
bitfld.long 0x04 22. " UTMIP_IGNORE_MASTER_CFG_P2 ,UTMIP ignore master config (P2)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 18.--21. " UTMIP_SCRATCH_P2 ,Scratch information about P2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--17. " UTMIP_SPEED_P2 ,UTMIP speed prior to DPD (P2)" "HS,FS,LS,RST"
|
|
textline " "
|
|
bitfld.long 0x04 15. " UTMIP_WAKE_EX_P1 ,Wake up on anything except a Particular Line Value (P1)" "Off,On"
|
|
bitfld.long 0x04 14. " UTMIP_IGNORE_MASTER_CFG_P1 ,UTMIP ignore master config (P1)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 10.--13. " UTMIP_SCRATCH_P1 ,Scratch information about the P1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--9. " UTMIP_SPEED_P1 ,UTMIP speed prior to DPD" "HS,FS,LS,RST"
|
|
textline " "
|
|
bitfld.long 0x04 7. " UTMIP_WAKE_EX_P0 ,Wake up on anything except a Particular Line Value (P0)" "Off,On"
|
|
bitfld.long 0x04 6. " UTMIP_IGNORE_MASTER_CFG_P0 ,UTMIP ignore master config (P0)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 2.--5. " UTMIP_SCRATCH_P0 ,Scratch information about the port 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--1. " UTMIP_SPEED_P0 ,UTMIP speed prior to DPD" "HS,FS,LS,RST"
|
|
rgroup.long 0x1F4++0x03
|
|
line.long 0x00 "UTMIP_PAD_CFG_0,I/O pad config for port 0"
|
|
bitfld.long 0x00 29. " LSBIAS_SEL_P2 ,I/O pad LSBIAS_SEL for UTMIP P2" "0,1"
|
|
bitfld.long 0x00 28. " LO_SPD ,I/O pad LO_SPD for UTMIP P2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SPARE_P2 ,I/O pad SPARE1..0 for UTMIP P2" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " FS_SLEW_P2 ,I/O pad SLEW1..0 for UTMIP P2" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " LS_FSLEW_P2 ,I/O pad LS_FSLEW1..0 for UTMIP P2" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " LS_RSLEW_P2 ,I/O pad LS_RSLEW1..0 for UTMIP P2" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 19. " LSBIAS_SEL_P1 ,I/O pad LSBIAS_SEL for UTMIP P1" "0,1"
|
|
bitfld.long 0x00 18. " LO_SPD_P1 ,I/O pad LO_SPD for UTMIP P1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SPARE_P1 ,I/O pad SPARE1..0 for UTMIP P1" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " FS_SLEW_P1 ,I/O pad SLEW1..0 for UTMIP P1" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " LS_FSLEW_P1 ,I/O pad LS_FSLEW1..0 for UTMIP P1" "0,1,2,3"
|
|
bitfld.long 0x00 10.--11. " LS_RSLEW_P1 ,I/O pad LS_RSLEW1..0 for UTMIP P1" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 9. " LSBIAS_SEL_P0 ,I/O pad LSBIAS_SEL for UTMIP P0" "0,1"
|
|
bitfld.long 0x00 8. " LO_SPD_P0 ,I/O pad LO_SPD for UTMIP P0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SPARE_P0 ,I/O pad SPARE1..0 for UTMIP P0" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " FS_SLEW_P0 ,I/O pad SLEW1..0 for UTMIP P0" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " LS_FSLEW_P0 ,I/O pad LS_FSLEW1..0 for UTMIP P0" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " LS_RSLEW_P0 ,I/O pad LS_RSLEW1..0 for UTMIP P0" "0,1,2,3"
|
|
group.long 0x1F8++0x1B
|
|
line.long 0x00 "UTMIP_TERM_PAD_CFG_0,I/O termination config for all UTMIP ports"
|
|
bitfld.long 0x00 5.--9. " TCTRL_VAL ,HS termination calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,,"
|
|
bitfld.long 0x00 0.--4. " RCTRL_VAL ,1.5 kOhm pull up calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,,,,,,,,,,,,,,,"
|
|
line.long 0x04 "UTMIP_UHSIC_SLEEP_CFG_0,Sleep walk sequence enables"
|
|
bitfld.long 0x04 28.--31. " UHSIC_WAKE_VAL_P0 ,Line value wake up condition on UHSIC P0" "SD00,SD01,SD10,SD11,S0,S1,,,D0,,D1,,None,SEDGE,DEDGE,Any"
|
|
bitfld.long 0x04 24. " UHSIC_MASTER_ENABLE_P0 ,Enable use of master pins on UHSIC P0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20.--23. " UTMIP_WAKE_VAP_P2 ,Line value wake up condition on UTMIP P2" "SE0,FSK,FSJ,SE1,DM0,DM1,,,DP0,,DP1,,NONE,DMEDGE,DPEDGE,Any"
|
|
bitfld.long 0x04 19. " UTMIP_TCTRL_USE_PMC_P2 ,Use PMC saved TCTRL on UTMIP P2" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 18. " UTMIP_RCTRL_USE_PMC_P2 ,Use PMC saved RCTRL on UTMIP P2" "No,Yes"
|
|
bitfld.long 0x04 17. " UTMIP_FSLS_USE_PMC_P2 ,Use PMC Saved Pad config on UTMIP P2" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 16. " UTMIP_MASTER_ENABLE_P2 ,Enable use of master pins on UTMIP P2" "Disabled,Enabled"
|
|
bitfld.long 0x04 12.--15. " UTMIP_WAKE_VAL_P1 ,Line Value Wake Up Condition on UTMIP P1" "SE0,FSK,FSJ,SE1,DM0,DM1,,,DP0,,DP1,,NONE,DMEDGE,DPEDGE,Any"
|
|
textline " "
|
|
bitfld.long 0x04 11. " UTMIP_TCTRL_USE_PMC_P1 ,Use PMC Saved TCTRL on UTMIP P1" "No,Yes"
|
|
bitfld.long 0x04 10. " UTMIP_RCTRL_USE_PMC_P1 ,Use PMC Saved RCTRL on UTMIP P1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 9. " UTMIP_FSLS_USE_PMC_P1 ,Use PMC Saved Pad config on UTMIP P1" "No,Yes"
|
|
bitfld.long 0x04 8. " UTMIP_MASTER_ENABLE_P1 ,Enable use of master pins on UTMIP P1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " UTMIP_WAKE_VAL_P0 ,Line Value Wake Up Condition on UTMIP P0" "SE0,FSK,FSJ,SE1,DM0,DM1,,,DP0,,DP1,,None,DMEDGE,DPEDGE,Any"
|
|
bitfld.long 0x04 3. " UTMIP_TCTRL_USE_PMC_P0 ,Use PMC Saved TCTRL on UTMIP P0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 2. " UTMIP_RCTRL_USE_PMC_P0 ,Use PMC Saved RCTRL on UTMIP P0" "No,Yes"
|
|
bitfld.long 0x04 1. " UTMIP_FSLS_USE_PMC_P0 ,Use PMC Saved Pad config on UTMIP P0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " UTMIP_MASTER_ENABLE_P0 ,Enable use of master pins on UTMIP P0" "Disabled,Enabled"
|
|
line.long 0x08 "UTMIP_UHSIC_SLEEPWALK_CFG_0,Sleep walk sequence enables"
|
|
bitfld.long 0x08 31. " UHSIC_LINEVAL_WALK_EN_P0 ,Perform Walk on USB line value wake up for UHSIC P0" "No,Yes"
|
|
bitfld.long 0x08 30. " UHSIC_WAKE_WALK_EN_P0 ,Perform Walk on any chip wake up event for UHSIC P0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 29. " UHSIC_GPIO_WALK_EN_P0 ,Perform Walk on associated GPIO event for UHSIC P0" "No,Yes"
|
|
bitfld.long 0x08 24.--28. " UHSIC_DESIGNATED_GPIO_P0 ,GPIO Number associated with UHSIC P0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 23. " UTMIP_LINEVAL_WALK_EN_P2 ,Perform Walk on USB line value wake up for UTMIP P2" "No,Yes"
|
|
bitfld.long 0x08 22. " UTMIP_WAKE_WALK_EN_P2 ,Perform Walk on any chip wake up event for UTMIP P2" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 21. " UTMIP_GPIO_WALK_EN_P2 ,Perform Walk on associated GPIO event for UTMIP P2" "No,Yes"
|
|
bitfld.long 0x08 16.--20. " UTMIP_DESIGNATED_GPIO_P2 ,GPIO Number associated with UTMIP P2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 15. " UTMIP_LINEVAL_WALK_EN_P1 ,Perform Walk on USB line value wake up for UTMIP P1" "No,Yes"
|
|
bitfld.long 0x08 14. " UTMIP_WAKE_WALK_EN_P1 ,Perform Walk on any chip wake up event for UTMIP P1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 13. " UTMIP_GPIO_WALK_EN_P1 ,Perform Walk on associated GPIO event for UTMIP P1" "No,Yes"
|
|
bitfld.long 0x08 8.--12. " UTMIP_DESIGNATED_GPIO_P1 ,GPIO Number associated with UTMIP P1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 7. " UTMIP_LINEVAL_WALK_EN_P0 ,Perform Walk on USB line value wake up for UTMIP P0" "No,Yes"
|
|
bitfld.long 0x08 6. " UTMIP_WAKE_WALK_EN_P0 ,Perform Walk on any chip wake up event for UTMIP P0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 5. " UTMIP_GPIO_WALK_EN_P0 ,Perform Walk on associated GPIO event for UTMIP P0" "No,Yes"
|
|
bitfld.long 0x08 0.--4. " UTMIP_DESIGNATED_GPIO_P0 ,GPIO Number associated with UTMIP P0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
width 22.
|
|
line.long 0x0C "UTMIP_SLEEPWALK_P0_0,Signalling sequence for UTMIP port 0 wakeup"
|
|
bitfld.long 0x0C 30. " HIGHZ_D ,Phase D Enable Single Ended Drivers" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " AN_D ,Phase D Drive Single Ended Value on D- line" "0,1"
|
|
bitfld.long 0x0C 28. " AP_D ,Phase D Drive Single Ended Value on D+ line" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " USBON_RPU_D ,Phase D 1.5kOhm Pull up on D- Line" "No,Yes"
|
|
bitfld.long 0x0C 26. " USBOP_RPU_D ,Phase D 1.5kOhm Pull Up on D+ Line" "No,Yes"
|
|
bitfld.long 0x0C 25. " USBON_RPD_D ,Phase D 15kOhm Pull Down on D- Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " USBOP_RPD_D ,Phase D 15kOhm Pull Down on D+ Line" "No,Yes"
|
|
bitfld.long 0x0C 22. " HIGHZ_C ,Phase C Enable Single Ended Drivers" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " AN_C ,Phase C Drive Single Ended Value on D- line" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 20. " AP_C ,Phase C Drive Single Ended Value on D+ line" "0,1"
|
|
bitfld.long 0x0C 19. " USBON_RPU_C ,Phase C 1.5kOhm Pull up on D- Line" "No,Yes"
|
|
bitfld.long 0x0C 18. " USBOP_RPU_C ,Phase C 1.5kOhm Pull Up on D+ Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " USBON_RPD_C ,Phase C 15kOhm Pull Down on D- Line" "No,Yes"
|
|
bitfld.long 0x0C 16. " USBOP_RPD_C ,Phase C 15kOhm Pull Down on D+ Line" "No,Yes"
|
|
bitfld.long 0x0C 14. " HIGHZ_B ,Phase B Enable Single Ended Drivers" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " AN_B ,Phase B Drive Single Ended Value on D- line" "0,1"
|
|
bitfld.long 0x0C 12. " AP_B ,Phase B Drive Single Ended Value on D+ line" "0,1"
|
|
bitfld.long 0x0C 11. " USBON_RPU_B ,Phase B 1.5kOhm Pull up on D- Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " USBOP_RPU_B ,Phase B 1.5kOhm Pull Up on D+ Line" "No,Yes"
|
|
bitfld.long 0x0C 9. " USBON_RPD_B ,Phase B 15kOhm Pull Down on D- Line" "No,Yes"
|
|
bitfld.long 0x0C 8. " USBOP_RPD_B ,Phase B 15kOhm Pull Down on D+ Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " HIGHZ_A ,Phase A Enable Single Ended Drivers" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " AN_A ,Phase A Drive Single Ended Value on D- line" "0,1"
|
|
bitfld.long 0x0C 4. " AP_A ,Phase A Drive Single Ended Value on D+ line" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " USBON_RPU_A ,Phase A 1.5kOhm Pull up on D- Line" "No,Yes"
|
|
bitfld.long 0x0C 2. " USBOP_RPU_A ,Phase A 1.5kOhm Pull Up on D+ Line" "No,Yes"
|
|
bitfld.long 0x0C 1. " USBON_RPD_A ,Phase A 15kOhm Pull Down on D- Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " USBOP_RPD_A ,Phase A 15kOhm Pull Down on D+ Line" "No,Yes"
|
|
textline " "
|
|
line.long 0x10 "UTMIP_SLEEPWALK_P1_0,Signalling sequence for UTMIP port 1 Wakeup"
|
|
bitfld.long 0x10 30. " HIGHZ_D ,Phase D Enable Single Ended Drivers" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " AN_D ,Phase D Drive Single Ended Value on D- line" "0,1"
|
|
bitfld.long 0x10 28. " AP_D ,Phase D Drive Single Ended Value on D+ line" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 27. " USBON_RPU_D ,Phase D 1.5kOhm Pull up on D- Line" "No,Yes"
|
|
bitfld.long 0x10 26. " USBOP_RPU_D ,Phase D 1.5kOhm Pull Up on D+ Line" "No,Yes"
|
|
bitfld.long 0x10 25. " USBON_RPD_D ,Phase D 15kOhm Pull Down on D- Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x10 24. " USBOP_RPD_D ,Phase D 15kOhm Pull Down on D+ Line" "No,Yes"
|
|
bitfld.long 0x10 22. " HIGHZ_C ,Phase C Enable Single Ended Drivers" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " AN_C ,Phase C Drive Single Ended Value on D- line" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 20. " AP_C ,Phase C Drive Single Ended Value on D+ line" "0,1"
|
|
bitfld.long 0x10 19. " USBON_RPU_C ,Phase C 1.5kOhm Pull up on D- Line" "No,Yes"
|
|
bitfld.long 0x10 18. " USBOP_RPU_C ,Phase C 1.5kOhm Pull Up on D+ Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x10 17. " USBON_RPD_C ,Phase C 15kOhm Pull Down on D- Line" "No,Yes"
|
|
bitfld.long 0x10 16. " USBOP_RPD_C ,Phase C 15kOhm Pull Down on D+ Line" "No,Yes"
|
|
bitfld.long 0x10 14. " HIGHZ_B ,Phase B Enable Single Ended Drivers" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " AN_B ,Phase B Drive Single Ended Value on D- line" "0,1"
|
|
bitfld.long 0x10 12. " AP_B ,Phase B Drive Single Ended Value on D+ line" "0,1"
|
|
bitfld.long 0x10 11. " USBON_RPU_B ,Phase B 1.5kOhm Pull up on D- Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x10 10. " USBOP_RPU_B ,Phase B 1.5kOhm Pull Up on D+ Line" "No,Yes"
|
|
bitfld.long 0x10 9. " USBON_RPD_B ,Phase B 15kOhm Pull Down on D- Line" "No,Yes"
|
|
bitfld.long 0x10 8. " USBOP_RPD_B ,Phase B 15kOhm Pull Down on D+ Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x10 6. " HIGHZ_A ,Phase A Enable Single Ended Drivers" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " AN_A ,Phase A Drive Single Ended Value on D- line" "0,1"
|
|
bitfld.long 0x10 4. " AP_A ,Phase A Drive Single Ended Value on D+ line" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 3. " USBON_RPU_A ,Phase A 1.5kOhm Pull up on D- Line" "No,Yes"
|
|
bitfld.long 0x10 2. " USBOP_RPU_A ,Phase A 1.5kOhm Pull Up on D+ Line" "No,Yes"
|
|
bitfld.long 0x10 1. " USBON_RPD_A ,Phase A 15kOhm Pull Down on D- Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x10 0. " USBOP_RPD_A ,Phase A 15kOhm Pull Down on D+ Line" "No,Yes"
|
|
textline " "
|
|
line.long 0x14 "UTMIP_SLEEPWALK_P2_0,Signalling sequence for UTMIP port 2 wakeup"
|
|
bitfld.long 0x14 30. " HIGHZ_D ,Phase D Enable Single Ended Drivers" "Disabled,Enabled"
|
|
bitfld.long 0x14 29. " AN_D ,Phase D Drive Single Ended Value on D- line" "0,1"
|
|
bitfld.long 0x14 28. " AP_D ,Phase D Drive Single Ended Value on D+ line" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 27. " USBON_RPU_D ,Phase D 1.5kOhm Pull up on D- Line" "No,Yes"
|
|
bitfld.long 0x14 26. " USBOP_RPU_D ,Phase D 1.5kOhm Pull Up on D+ Line" "No,Yes"
|
|
bitfld.long 0x14 25. " USBON_RPD_D ,Phase D 15kOhm Pull Down on D- Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x14 24. " USBOP_RPD_D ,Phase D 15kOhm Pull Down on D+ Line" "No,Yes"
|
|
bitfld.long 0x14 22. " HIGHZ_C ,Phase C Enable Single Ended Drivers" "Disabled,Enabled"
|
|
bitfld.long 0x14 21. " AN_C ,Phase C Drive Single Ended Value on D- line" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 20. " AP_C ,Phase C Drive Single Ended Value on D+ line" "0,1"
|
|
bitfld.long 0x14 19. " USBON_RPU_C ,Phase C 1.5kOhm Pull up on D- Line" "No,Yes"
|
|
bitfld.long 0x14 18. " USBOP_RPU_C ,Phase C 1.5kOhm Pull Up on D+ Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x14 17. " USBON_RPD_C ,Phase C 15kOhm Pull Down on D- Line" "No,Yes"
|
|
bitfld.long 0x14 16. " USBOP_RPD_C ,Phase C 15kOhm Pull Down on D+ Line" "No,Yes"
|
|
bitfld.long 0x14 14. " HIGHZ_B ,Phase B Enable Single Ended Drivers" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " AN_B ,Phase B Drive Single Ended Value on D- line" "0,1"
|
|
bitfld.long 0x14 12. " AP_B ,Phase B Drive Single Ended Value on D+ line" "0,1"
|
|
bitfld.long 0x14 11. " USBON_RPU_B ,Phase B 1.5kOhm Pull up on D- Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x14 10. " USBOP_RPU_B ,Phase B 1.5kOhm Pull Up on D+ Line" "No,Yes"
|
|
bitfld.long 0x14 9. " USBON_RPD_B ,Phase B 15kOhm Pull Down on D- Line" "No,Yes"
|
|
bitfld.long 0x14 8. " USBOP_RPD_B ,Phase B 15kOhm Pull Down on D+ Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x14 6. " HIGHZ_A ,Phase A Enable Single Ended Drivers" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " AN_A ,Phase A Drive Single Ended Value on D- line" "0,1"
|
|
bitfld.long 0x14 4. " AP_A ,Phase A Drive Single Ended Value on D+ line" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 3. " USBON_RPU_A ,Phase A 1.5kOhm Pull up on D- Line" "No,Yes"
|
|
bitfld.long 0x14 2. " USBOP_RPU_A ,Phase A 1.5kOhm Pull Up on D+ Line" "No,Yes"
|
|
bitfld.long 0x14 1. " USBON_RPD_A ,Phase A 15kOhm Pull Down on D- Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x14 0. " USBOP_RPD_A ,Phase A 15kOhm Pull Down on D+ Line" "No,Yes"
|
|
textline " "
|
|
line.long 0x18 "UHSIC_SLEEPWALK_P0_0,Signalling sequence for UHSIC port 0 wakeup"
|
|
bitfld.long 0x18 27. " UHSIC_DATA_RPU_D ,Phase D Pull up on DATA Line" "No,Yes"
|
|
bitfld.long 0x18 26. " UHSIC_STROBE_RPU_D ,Phase D Pull Up on STROBE Line" "No,Yes"
|
|
bitfld.long 0x18 25. " UHSIC_DATA_RPD_D ,Phase D Pull Down on DATA Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x18 24. " UHSIC_STROBE_RPD_D ,Phase D Pull Down on STROBE Line" "No,Yes"
|
|
bitfld.long 0x18 19. " UHSIC_DATA_RPU_C ,Phase C Pull up on DATA Line" "No,Yes"
|
|
bitfld.long 0x18 18. " UHSIC_STROBE_RPU_C ,Phase C Pull Up on STROBE Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x18 17. " UHSIC_DATA_RPD_C ,Phase C Pull Down on DATA Line" "No,Yes"
|
|
bitfld.long 0x18 16. " UHSIC_STROBE_RPD_C ,Phase C Pull Down on STROBE Line" "No,Yes"
|
|
bitfld.long 0x18 11. " UHSIC_DATA_RPU_B ,Phase B Pull up on DATA Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x18 10. " UHSIC_STROBE_RPU_B ,Phase B Pull Up on STROBE Line" "No,Yes"
|
|
bitfld.long 0x18 9. " UHSIC_DATA_RPD_B ,Phase B Pull Down on DATA Line" "No,Yes"
|
|
bitfld.long 0x18 8. " UHSIC_STROBE_RPD_B ,Phase B Pull Down on STROBE Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x18 3. " UHSIC_DATA_RPU_A ,Phase A Pull up on DATA Line" "No,Yes"
|
|
bitfld.long 0x18 2. " UHSIC_STROBE_RPU_A ,Phase A Pull Up on STROBE Line" "No,Yes"
|
|
bitfld.long 0x18 1. " UHSIC_DATA_RPD_A ,Phase A Pull Down on DATA Line" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x18 0. " UHSIC_STROBE_RPD_A ,Phase A Pull Down on STROBE Line" "No,Yes"
|
|
textline " "
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "UTMIP_UHSIC_STATUS_0,Status of UTMIP UHSIC wakeup circuitry"
|
|
bitfld.long 0x00 19. " UHSIC_WAKE_ALARM_P0 ,A wake event occurred on UHSIC port 0" "No,Yes"
|
|
bitfld.long 0x00 18. " UTMIP_WAKE_ALARM_P2 ,A wake event occurred on UTMIP port 2" "No,Yes"
|
|
bitfld.long 0x00 17. " UTMIP_WAKE_ALARM_P1 ,A wake event occurred on UTMIP port 1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " UTMIP_WAKE_ALARM_P0 ,A wake event occurred on UTMIP port 0" "No,Yes"
|
|
bitfld.long 0x00 15. " DATA_VAL_P0 ,Value of DATA line detector for UHSIC port 0" "0,1"
|
|
bitfld.long 0x00 14. " STROBE_VAL_P0 ,Value of STROBE line detector for UHSIC port 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " USBON_VAL_P2 ,Value of D- line detector for UTMIP port 2" "0,1"
|
|
bitfld.long 0x00 12. " USBOP_VAL_P2 ,Value of D+ line detector for UTMIP port 2" "0,1"
|
|
bitfld.long 0x00 11. " USBON_VAL_P1 ,Value of D- line detector for UTMIP port 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " USBOP_VAL_P1 ,Value of D+ line detector for UTMIP port 1" "0,1"
|
|
bitfld.long 0x00 9. " USBON_VAL_P0 ,Value of D- line detector for UTMIP port 0" "0,1"
|
|
bitfld.long 0x00 8. " USBOP_VAL_P0 ,Value of D+ line detector for UTMIP port 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " UHSIC_WALK_PTR_P0 ,Walk pointer for UHSIC port 0" "0,1,,..."
|
|
bitfld.long 0x00 4.--5. " UTMIP_WALK_PTR_P2 ,Walk pointer for UTMIP port 2" "0,1,,..."
|
|
bitfld.long 0x00 2.--3. " UTMIP_WALK_PTR_P1 ,Walk pointer for UTMIP port 1" "0,1,,..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " UTMIP_WALK_PTR_P0 ,Walk pointer for UMTIP port 0" "0,1,,..."
|
|
textline " "
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "UTMIP_UHSIC_FAKE_0,Fake the line value for the PM pad macro"
|
|
bitfld.long 0x00 27. " UTMIP_ID_FAKE_EN_P2 ,Enable the fake ID value for UTMIP P2" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " UTMIP_ID_FAKE_VAL_P2 ,Fake ID value for UTMIP P2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " UTMIP_VBUS_FAKE_EN_P2 ,Enable the fake VBUS WAKEUP value for UTMIP P2" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " UTMIP_VBUS_FAKE_VAL_P2 ,Fake VBUS WAKEUP value for UTMIP P2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " UTMIP_ID_FAKE_EN_P1 ,Enable the fake ID value for UTMIP P1" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " UTMIP_ID_FAKE_VAL_P1 ,Fake ID value for UTMIP P1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " UTMIP_VBUS_FAKE_EN_P1 ,Enable the fake VBUS WAKEUP value for UTMIP P1" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " UTMIP_VBUS_FAKE_VAL_P1 ,Fake VBUS WAKEUP value for UTMIP P1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " UTMIP_ID_FAKE_EN_P0 ,Enable the fake ID value for UTMIP P0" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " UTMIP_ID_FAKE_VAL_P0 ,Fake ID value for UTMIP P0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " UTMIP_VBUS_FAKE_EN_P0 ,Enable the fake VBUS WAKEUP value for UTMIP P0" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " UTMIP_VBUS_FAKE_VAL_P0 ,Fake VBUS WAKEUP value for UTMIP P0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " UHSIC_FAKE_DATA_EN_P0 ,Enable the fake line value for DATA for the PMC pad macro for UHSIC P0" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " UHSIC_FAKE_STROBE_EN_P0 ,Enable the fake line value for STROBE for the PMC pad macro for UHSIC P0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " UHSIC_FAKE_DATA_VAL_P0 ,Fake line value for DATA for the PMC pad macro for UHSIC P0" "0,1"
|
|
bitfld.long 0x00 12. " UHSIC_FAKE_STROBE_VAL_P0 ,Fake line value for STROBE for the PMC pad macro for UHSIC P0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " UTMIP_FAKE_USBON_EN_P2 ,Enable the fake line value for D- for the PMC pad macro for UTMIP P2" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " UTMIP_FAKE_USBOP_EN_P2 ,Enable the fake line value for D+ for the PMC pad macro for UTMIP P2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " UTMIP_FAKE_USBON_VAL_P2 ,Fake line value for D- for the PMC pad macro for UTMIP P2" "0,1"
|
|
bitfld.long 0x00 8. " UTMIP_FAKE_USBOP_VAL_P2 ,Fake line value for D+ for the PMC pad macro for UTMIP P2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " UTMIP_FAKE_USBON_EN_P1 ,Enable the fake line value for D- for the PMC pad macro for UTMIP P1" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " UTMIP_FAKE_USBOP_EN_P1 ,Enable the fake line value for D+ for the PMC pad macro for UTMIP P1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " UTMIP_FAKE_USBON_VAL_P1 ,Fake line value for D- for the PMC pad macro for UTMIP P1" "0,1"
|
|
bitfld.long 0x00 4. " UTMIP_FAKE_USBOP_VAL_P1 ,Fake line value for D+ for the PMC pad macro for UTMIP P1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " UTMIP_FAKE_USBON_EN_P0 ,Enable the fake line value for D- for the PMC pad macro for UTMIP P0" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " UTMIP_FAKE_USBOP_EN_P0 ,Enable the fake line value for D+ for the PMC pad macro for UTMIP P0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UTMIP_FAKE_USBON_VAL_P0 ,Fake line value for D- for the PMC pad macro for UTMIP P0" "0,1"
|
|
bitfld.long 0x00 0. " UTMIP_FAKE_USBOP_VAL_P0 ,Fake line value for D+ for the PMC pad macro for UTMIP P0" "0,1"
|
|
tree.end
|
|
tree "Scratch Registers 3"
|
|
width 20.
|
|
group.long 0x21C++0x07
|
|
line.long 0x0 "BONDOUT_MIRROR3_0,Secure scratch register 3"
|
|
line.long 0x4 "BONDOUT_MIRROR4_0,Secure scratch register 4"
|
|
group.long 0x224++0x07
|
|
line.long 0x0 "SECURE_SCRATCH6_0,Secure scratch register 6"
|
|
line.long 0x4 "SECURE_SCRATCH7_0,Secure scratch register 7"
|
|
group.long 0x22C++0x23
|
|
line.long 0x0 "SCRATCH43_0,Scratch register 43"
|
|
line.long 0x4 "SCRATCH44_0,Scratch register 44"
|
|
line.long 0x8 "SCRATCH45_0,Scratch register 45"
|
|
line.long 0xC "SCRATCH46_0,Scratch register 46"
|
|
line.long 0x10 "SCRATCH47_0,Scratch register 47"
|
|
line.long 0x14 "SCRATCH48_0,Scratch register 48"
|
|
line.long 0x18 "SCRATCH49_0,Scratch register 49"
|
|
line.long 0x1C "SCRATCH50_0,Scratch register 50"
|
|
line.long 0x20 "SCRATCH51_0,Scratch register 51"
|
|
group.long 0x250++0x07
|
|
line.long 0x00 "SCRATCH52_0,Scratch register 52"
|
|
hexmask.long.word 0x00 16.--31. 1. " SCRATCH_PMU_A_0_HIWORD_RANGE ,Scratch pmu A 0 hiword range"
|
|
hexmask.long.word 0x00 0.--15. 1. " SCRATCH_PMU_A_0_LOWORD_RANGE ,Scratch pmu A 0 loword range"
|
|
textline " "
|
|
line.long 0x04 "SCRATCH53_0,Scratch register 53"
|
|
bitfld.long 0x04 31. " SCRATCH_PMU_B_0_RST_ENABLE_RANGE ,Scratch pmu B 0 reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27.--29. " SCRATCH_PMU_B_0_CNTLR_ID_RANGE ,Scratch PMU B 0 controller ID" "I2C1,I2C2,I2C3,I2C4,I2C PMU,..."
|
|
textline " "
|
|
bitfld.long 0x04 24.--26. " SCRATCH_PMU_B_0_PINMUX_RANGE ,Pinmux range" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SCRATCH_PMU_B_0CHKSUM_RANGE ,Checksum Range"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SCRATCH_PMU_B_0_16BITOP_RANGE ,Scratch PMU B 0 16 bitop range" "0,1"
|
|
bitfld.long 0x04 14. " SCRATCH_PMU_B_0_USE_GPIO_RANGE , Scratch pmu B 0 GPIO range" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--6. 1. " SCRATCH_PMU_B_0_I2CSLV1_RANGE ,I2C Slave Address"
|
|
textline " "
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "POR_DPD_CTRL_0, POR DPD Controller"
|
|
bitfld.long 0x00 31. " MEM0_HOLD_CKE_LOW_OVR ,Register control to pull CKE low" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MEM0_ADDR1_CLK_SEL_DPD ,Sets sel_dpd to clock buffer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MEM0_ADDR0_CLK_SEL_DPD , Sets sel_dpd to clock buffer" "Disabled,Enabled"
|
|
textline " "
|
|
tree.end
|
|
tree "UTMIP & UHSIC Config"
|
|
width 30.
|
|
group.long 0x308++0x0B
|
|
line.long 0x00 "UTMIP_UHSIC_LINE_WAKEUP_0,UHSIC and UTMIP latching line wake-up event control"
|
|
bitfld.long 0x00 3. " UHSIC_LINE_WAKEUP_EN_P0 ,Enables latching line wake-up event on UHSIC p0" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " UTMIP_LINE_WAKEUP_EN_P2 ,Enables latching line wake-up event on UTMIP p2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UTMIP_LINE_WAKEUP_EN_P1 ,Enables latching line wake-up event on UTMIP p1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UTMIP_LINE_WAKEUP_EN_P0 ,Enables latching line wake-up event on UTMIP p0" "Disabled,Enabled"
|
|
line.long 0x04 "UTMIP_BIAS_MASTER_CNTRL_0,UTMIP master bias control"
|
|
bitfld.long 0x04 3. " UTMIP_BIAS_MASTER_AWAKE_AND ,Master awake AND setup" "0,1"
|
|
bitfld.long 0x04 2. " UTMIP_BIAS_MASTER_AWAKE_OR ,Master awake OR setup" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 1. " UTMIP_BIAS_MASTER_PROG_VAL ,Master programmable value" "0,1"
|
|
bitfld.long 0x04 0. " UTMIP_BIAS_MASTER_PROG_CTRL ,Use programmable value on BIAS" "No,yes"
|
|
line.long 0x08 "UTMIP_MASTER_CONFIG_0,UHSIC and UTMIP master configuration"
|
|
bitfld.long 0x08 3. " UHSIC_PWR_P0 ,Enables UHSIC p0 low power mode" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " UTMIP_PWR_P2 ,Enables UTMIP p2 low power mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " UTMIP_PWR_P1 ,Enables UTMIP p1 low power mode" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " UTMIP_PWR_P0 ,Enables UTMIP p0 low power mode" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "UTMIP_UHSIC2_TRIGGERS_0,Triggers for USB Ports"
|
|
bitfld.long 0x00 3. " UHSIC_CLR_WAKE_ALARM_P1 ,Clear wake event for UHSIC port 0" "Null,Trig"
|
|
bitfld.long 0x00 2. " UHSIC_FORCE_WALK_P1 ,Force pointer walk for UHSIC port 0" "Null,Trig"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UHSIH_RESERVED_P1 ,Reserved for UHSIC port 0" "Null,Trig"
|
|
bitfld.long 0x00 0. " UHSIC_CLR_WALK_PTR_P1 ,Clear sleep walk pionter for UHSIC port 1" "Null,Trig"
|
|
textline " "
|
|
group.long 0x280++0x0B
|
|
line.long 0x00 "UTMIP_UHSIC2_SAVED_STATE_0,Saved DPD State for all UTMIP and UHSIC Ports"
|
|
bitfld.long 0x00 7. " UHSIC_WAKE_EX_P1 ,Wake up on anything except a particular line value" "Off,On"
|
|
bitfld.long 0x00 6. " UHSIC_IGNORE_MASTER_CFG_P1 ,Ignore master CFG P1" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--5. 1. " UHSIC_SCRATCH_P1 ,UHSIC scratch P1"
|
|
bitfld.long 0x00 0. " UHSIC_MODE_P1 ,Speed prior to DPD" "HS,RST"
|
|
textline " "
|
|
line.long 0x04 "UTMIP_UHSIC2_SLEEP_CFG_0,Sleep Walk Sequence Enables"
|
|
bitfld.long 0x04 4.--7. " UHSIC_WAKE_VAL_P1 ,Value Wake Up Condition on UHSIC P1" "SD00,SD01,SD10,SD11,S0,S1,,,D0,,D1,,NONE,SEDGE,DEDGE,ANY"
|
|
bitfld.long 0x04 0. " UHSIC_MASTER_ENABLE_P1 ,Enable use of master pins on UHSIC P1" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x08 "UTMIP_UHSIC2_SLEEPWALK_CFG_0,Sleep Walk Sequence Enables"
|
|
bitfld.long 0x08 7. " UHSIC_LINEVAL_WALK_EN_P1 ,USB line value wake up for UHSIC P1" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " UHSIC_WAKE_WALK_EN_P1 ,Perform walk on any chip wake up event for UHSIC P1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " UHSIC_GPIO_WALK_EN_P1 ,Perform walk on assiciated GPIO enevt for UHSIC P1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0.--4. " UHSIC_DESIGNATED_GPIO_P1 ,GPIO number associated with UHSIC P1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "UHSIC2_SLEEPWALK_P1_0,Signaling Sequence for UHSIC Port 0 Wakeup"
|
|
bitfld.long 0x00 27. " UHSIC_DATA_RPU_D ,Phase D Pull up on DATA Line" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " UHSIC_STROBE_RPU_D ,Phase D Pull Up on STROBE Line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " UHSIC_DATA_RPD_D ,Phase D Pull DOwn on Data Line" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " UHSIC_STROBE_RPD_D ,Phase D Pull Down on Strobe Line " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " UHSIC_DATA_RPU_C ,Phase C Pull up on DATA Line" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " UHSIC_STROBE_RPU_C ,Phase C Pull Up on STROBE Line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " UHSIC_DATA_RPD_C ,Phase C Pull Down on DATA Line" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " UHSIC_STROBE_RPD_C ,Phase C Pull Down on STROBE Line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " UHSIC_DATA_RPU_B ,Phase B Pull up on DATA Line" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " UHSIC_STROBE_RPU_B ,Phase B Pull Up on STROBE Line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " UHSIC_DATA_RPD_B ,Phase B Pull Down on DATA Line" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " UHSIC_STROBE_RPD_B ,Phase B Pull Down on Strobe Line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " UHSIC_DATA_RPU_A ,Phase A Pull up on DATA Line " "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " UHSIC_STROBE_RPU_A ,Phase A Pull Up on STROBE LINE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UHSIC_DATA_RPD_A ,Phase A Pull Down on DATA Line" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UHSIC_STROBE_RPD_A ,Phase A Pull Down on STROBE Line" "Disabled,Enabled"
|
|
rgroup.long 0x290++0x03
|
|
line.long 0x00 "UTMIP_UHSIC2_STATUS_0,Status of UTMIP UHSIC Wakeup Circuitry"
|
|
bitfld.long 0x00 4. " UHSIC_WAKE_ALARM_P1 ,Wake event occured on UHSIC port 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DATA_VAL_P1 ,Value of DATA line detector for UHSIC port 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " STROBE_VAL_P1 ,Value of STROBE line detector for UHSIC port 1" "0,1"
|
|
bitfld.long 0x00 0.--1. " UHSIC_WALK_PTR_P1 ,Walk pointer for UHSIC port 0" "0,1,2,3"
|
|
textline " "
|
|
group.long 0x294++0x07
|
|
line.long 0x00 "UTMIP_UHSIC2_FAKE_0,Fake the Line value for the PMC Pad Micro"
|
|
bitfld.long 0x00 3. " UHSIC_FAKE_DATA_EN_P1 ,Enable for DATA for PMC pad macro for UHSIC P0" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " UHSIC_FAKE_STROBE_EN_P1 ,Value for STROBE for the PMC pad macro for UHSIC P0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UHSIC_FAKE_DATA_VAL_P1 ,Value for DATA for the PMC pad macro for UHSIC P0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UHSIC_FAKE_STROBE_VAL_P1 ,Vlue STROBE for the PMC pad macro for UHSIC P0" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "UTMIP_UHSIC2_LINE_WAKEUP_0,PMC UTMIP UHSIC2 Line Wake up"
|
|
bitfld.long 0x04 0. " UHSIC_LINE_WAKEUP_EN_P1 ,Enable latching line wake-up event on UHSIC P1" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x29C++0x07
|
|
line.long 0x00 "UTMIP_MASTER2_CONFIG_0,PMC Utmip Master2 Config_0"
|
|
bitfld.long 0x00 0. " UHSIC_PWR_P1 ,Enables UHSIC P1 low power mode" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "UTMIP_UHSIC_RPD_CFG_0,PMC Utmip UHSIC rpd cfg_0"
|
|
bitfld.long 0x04 8. " WEAKPD_ANYTIME_P2 ,Weakpd anytime P2" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " DP_WEAKPD_CFG_P2 ,DP weakpd cfg P2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DM_WEAKPD_CFG_P2 ,Dm weakpd cfg P2" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " WEAKPD_ANYTIME_P1 ,Weakpd anytime P1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " DP_WEAKPD_CFG_P1 ,DP weakpd cfg P1" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " DM_WEAKPD_CFG_P1 ,DM weakpd cfg P1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " WEAKPD_ANYTIME_P0 ,Weakpd anytime P0" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " DP_WEAKPD_CFG_P0 ,DP weakpd cfg P0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " DM_WEAKPD_CFG_P0 ,DM weakpd cfg P0" "Disabled,Enabled"
|
|
tree.end
|
|
width 23.
|
|
group.long 0x2A4++0x07
|
|
line.long 0x00 "PG_MASK_CE0_0,PMC PG mask CE0_0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MASK ,Mask CE1 rail"
|
|
textline " "
|
|
line.long 0x04 "PG_MASK_3_0,PMC PG mask 3_0"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DISB ,Mask DISB rail"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DIS ,Mask DIS rail"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " C1NC ,Mask C1NC rail"
|
|
hexmask.long.byte 0x04 0.--7. 1. " C0NC ,Mask C0NC rail"
|
|
textline " "
|
|
group.long 0x2AC++0x0F
|
|
line.long 0x00 "PG_MASK_4_0,PMC PG mask 4_0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SOR ,Mask SOR rail"
|
|
hexmask.long.byte 0x00 16.--23. 1. " XUSBC ,Mask XUSBC rail"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " XUSBB ,Mask XUSBB rail"
|
|
hexmask.long.byte 0x00 0.--7. 1. " XUSBA ,Mask XUSBA rail"
|
|
textline " "
|
|
line.long 0x04 "PLLM_WB0_OVERRIDE2_0,PMC PLLM WB0 override2_0"
|
|
bitfld.long 0x04 27. " DIV2 ,New divide by 2" "Not divided,/2"
|
|
bitfld.long 0x04 26. " KVCO ,KVCO/VCO gain" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 24.--25. " KCP ,Charge pump control" "0,1,2,3"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " SETUP ,Setup"
|
|
textline " "
|
|
line.long 0x08 "TSC_MULT_0,PMC TSC mult 0"
|
|
bitfld.long 0x08 17.--19. " TICK_SEL ,Time stamp counter bits" "Bit0,Bit1,Bit2,Bit3,Bit4,Bit5,..."
|
|
rbitfld.long 0x08 16. " FREQ_STS ,Clock frequency for counter" "Oscillator freq,32 kHz"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--15. 1. " MULT_VAL ,TSC multiply value"
|
|
textline " "
|
|
line.long 0x0C "CPU_VSENSE_OVERRIDE_0,PMC CPU VSENSE override_0"
|
|
bitfld.long 0x0C 5. " VDD ,VDD sensing override" "0,1"
|
|
bitfld.long 0x0C 4. " C0NC ,C0NC VVDD partition sensing override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " CE3 ,CE3 VVDD partition sensing override" "0,1"
|
|
bitfld.long 0x0C 2. " CE2 ,CE2 VVDD partition sensing override " "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CE1 ,CE1 VVDD partition sensing override " "0,1"
|
|
bitfld.long 0x0C 0. " CE0 ,CE0 VVDD partition sensing override" "0,1"
|
|
textline " "
|
|
group.long 0x2BC++0x0F
|
|
line.long 0x00 "GLB_AMAP_CFG,GLB AMAP CFG Controller"
|
|
bitfld.long 0x00 16. " AHB_A2_RSVD ,AHB A2 rsvd aperture" "MMIO,DRAM"
|
|
bitfld.long 0x00 15. " AHB_A1_RSVD ,AHB A1 rsvd aperture" "MMIO,DRAM"
|
|
textline " "
|
|
bitfld.long 0x00 14. " AHB_A1 ,AHB A1 aperture" "MMIO,DRAM"
|
|
bitfld.long 0x00 13. " APB_RSVD ,APB rsvd aperture" "MMIO,DRAM"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EXTIO_RSVD ,EXTIO rsvd aperture" "MMIO,DRAM"
|
|
bitfld.long 0x00 11. " PPSB_RSVD ,PPSB RSVD aperture" "MMIO,DRAM"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GART_GPU ,GART GPU aperture" "MMIO,DRAM"
|
|
bitfld.long 0x00 9. " GFX_HOST_RSVD ,GFX HOST rsvd aperture" "MMIO,DRAM"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VERIF_RSVD ,VERIF rsvd aperture" "MMIO,DRAM"
|
|
bitfld.long 0x00 7. " NOR_A3 ,NOR A3 aperture" "MMIO,DRAM"
|
|
textline " "
|
|
bitfld.long 0x00 6. " NOR_A2 ,NOR A2 aperture" "MMIO,DRAM"
|
|
bitfld.long 0x00 5. " NOR_A1 ,NOR A1 aperture" "MMIO,DRAM"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRAM_RSVD ,IRAM rsvd aperture" "MMIO,DRAM"
|
|
bitfld.long 0x00 3. " PCIE_A3 ,PCIE A3 aperture" "MMIO,DRAM"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCIE_A2 , PCIE A2 aperture" "MMIO,DRAM"
|
|
bitfld.long 0x00 1. " PCIE_A1 , PCIE A1 aperture" "MMIO,DRAM"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IROM_LOVEC ,IROM Lovec aperture" "MMIO,DRAM"
|
|
line.long 0x04 "STICKY_BITS_0,PMC Sticky Bits 0 Controller"
|
|
bitfld.long 0x04 8. " VI ,VI" "0,1"
|
|
bitfld.long 0x04 7. " CDD_EN ,Customer Denver DFD Enable" "DFD disabled,DFD enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " JTAG_STS ,Secure Sticky One bit to propagate JTAG across LP0" "Enabled,Disabled"
|
|
bitfld.long 0x04 5. " VDE4 ,VDE4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 4. " VDE3 ,VDE3" "0,1"
|
|
bitfld.long 0x04 3. " VDE2 ,VDE2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VDE1 ,VDE1" "0,1"
|
|
bitfld.long 0x04 1. " VDE0 ,VDE0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 0. " HDA_LPBK_DIS ,Sticky one bt to disable the loopback in HDA codec" "0,1"
|
|
line.long 0x08 "SEC_DISABLE2_0,PMC SEC DISABLE2 Controller"
|
|
bitfld.long 0x08 31. " READ23 ,Disable reads from secure register 23" "Off,On"
|
|
bitfld.long 0x08 30. " WRITE23 ,Disable writes from secure register 23" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x08 29. " READ22 ,Disable reads from secure register 22" "Off,On"
|
|
bitfld.long 0x08 28. " WRITE22 ,Disable writes from secure register 22" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x08 27. " READ21 ,Disable reads from secure register 21" "Off,On"
|
|
bitfld.long 0x08 26. " WRITE21 ,Disable writes from secure register 21" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x08 25. " READ20 ,Disable reads from secure register 20" "Off,On"
|
|
bitfld.long 0x08 24. " WRITE20 ,Disable writes from secure register 20" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x08 23. " READ19 ,Disable reads from secure register 19" "Off,On"
|
|
bitfld.long 0x08 22. " WRITE19 ,Disable writes from secure register 19" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x08 21. " READ18 ,Disable reads from secure register 18" "Off,On"
|
|
bitfld.long 0x08 20. " WRITE18 ,Disable writes from secure register 18" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x08 19. " READ17 ,Disable reads from secure register 17" "Off,On"
|
|
bitfld.long 0x08 18. " WRITE17 ,Disable writes from secure register 17" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x08 17. " READ16 ,Disable reads from secure register 16" "Off,On"
|
|
bitfld.long 0x08 16. " WRITE16 ,Disable writes from secure register 16" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x08 15. " READ15 ,Disable reads from secure register 15" "Off,On"
|
|
bitfld.long 0x08 14. " WRITE15 ,Disable writes from secure register 15" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x08 13. " READ14 ,Disable reads from secure register 14" "Off,On"
|
|
bitfld.long 0x08 12. " WRITE14 ,Disable writes from secure register 14" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x08 11. " READ13 ,Disable reads from secure register 13" "Off,On"
|
|
bitfld.long 0x08 10. " WRITE13 ,Disable writes from secure register 13" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x08 9. " READ12 ,Disable reads from secure register 12" "Off,On"
|
|
bitfld.long 0x08 8. " WRITE12 ,Disable writes from secure register 12" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x08 7. " READ11 ,Disable reads from secure register 11" "Off,On"
|
|
bitfld.long 0x08 6. " WRITE11 ,Disable writes from secure register 11" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x08 5. " READ10 ,Disable reads from secure register 10" "Off,On"
|
|
bitfld.long 0x08 4. " WRITE10 ,Disable writes from secure register 10" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x08 3. " READ9 ,Disable reads from secure register 9" "Off,On"
|
|
bitfld.long 0x08 2. " WRITE9 ,Disable writes from secure register 9" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x08 1. " READ8 ,Disable reads from secure register 8" "Off,On"
|
|
bitfld.long 0x08 0. " WRITE8 ,Disable writes from secure register 8" "Off,On"
|
|
textline " "
|
|
line.long 0x0C "WEAK_BIAS_0,PMC WEAK BIAS_0 Controller"
|
|
bitfld.long 0x0C 16.--17. " XM0_DATA1 ,vttgen_4_6_pad vttgen_5_7_pad" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " XM0_ADDR1 ,addr1/addr2_vttgen_0_pad" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 10.--11. " XM0_DATA0 , vttgen_0_2_pad vttgen_1_3_pad" "0,1,2,3"
|
|
bitfld.long 0x0C 8.--9. " EMMC ,EMMC" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " XM0_ADDR0 ,addr0/addr3_vttgen_0_pad" "0,1,2,3"
|
|
bitfld.long 0x0C 0.--1. " XM0_CLK ,Weak_blas controls for CH0 VTTGEN " "0,1,2,3"
|
|
textline " "
|
|
group.long 0x2CC++0x0F
|
|
line.long 0x00 "REG_SHORT_0,PMC reg short_0 Controller"
|
|
bitfld.long 0x00 17. " DPD_VAL_XM0_DATA1 ,Reg_short value DPD for mem0_data1_vttgen_4_6_pad/_5_7_pad" "0,1"
|
|
bitfld.long 0x00 16. " DPD_VAL_XM0_ADDR1 ,Reg_short value DPD for mem0_addr1/addr2_vttgen_0_pad" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " VAL_XM0_DATA1 ,Reg_short value during normal operation for mem0_data1_vttgen_4_6/_5_7_pad" "0,1"
|
|
bitfld.long 0x00 12. " VAL_XM0_ADDR1 , Reg_short value during normal operation for mem0_data1_vttgen_4_6/_5_7_pad" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DPD_VAL_XM0_DATA0 ,Reg_short value during DPD for mem0_data0_vttgen_0_2/_1_3_pad" "0,1"
|
|
bitfld.long 0x00 8. " VAL_XM0_DATA0 ,Reg_short value during normal operation for mem0_data0_vttgen_0_2_pad,mem0_data0_vttgen_1_3_pad" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DPD_VAL_XM0_ADDR0 ,Reg_short value during DPD operation for mem0_addr0/addr3_vttgen_0_pad" "0,1"
|
|
bitfld.long 0x00 4. " DPD_VAL_XM0_CLK ,Reg_short value during DPD operation for mem0_mclk0_vttgen_0_pad" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " VAL_XM0_ADDR0 ,Reg_short value during normal operation for mem0_addr0/addr3_vttgen_0_pad" "0,1"
|
|
bitfld.long 0x00 0. " VAL_XM0_CLK ,Reg_short value during normal operation for mem0_mclk_vttgen_0_pad" "0,1"
|
|
line.long 0x04 "PG_MASK_ANDOR_0 ,PMC PG MASK ANDOR_0 Controller"
|
|
bitfld.long 0x04 24. " IRAM ,IRAM" "AND,OR"
|
|
bitfld.long 0x04 23. " VIC ,VIC" "AND,OR"
|
|
textline " "
|
|
bitfld.long 0x04 22. " XUSBC ,Override for XUSBC" "AND,OR"
|
|
bitfld.long 0x04 21. " XUSBB ,Override for XUSBB" "AND,OR"
|
|
textline " "
|
|
bitfld.long 0x04 20. " XUSBA ,Override for XUSBA" "AND,OR"
|
|
bitfld.long 0x04 19. " DISB ,Override for DISB partition" "AND,OR"
|
|
textline " "
|
|
bitfld.long 0x04 18. " DIS ,Override for DIS partition" "AND,OR"
|
|
bitfld.long 0x04 17. " SOR ,SOR" "AND,OR"
|
|
textline " "
|
|
bitfld.long 0x04 16. " C1NC ,Override for Cluster 1 Non-CPU partition" "AND,OR"
|
|
bitfld.long 0x04 15. " C0NC ,Override for Cluster 0 Non_CPU partition" "AND,OR"
|
|
textline " "
|
|
bitfld.long 0x04 14. " CE0 ,Override for CPU0 partition" "AND,OR"
|
|
bitfld.long 0x04 12. " CELP ,Override for CELP partition " "AND,OR"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CE3 ,Override for CE3 partition" "AND,OR"
|
|
bitfld.long 0x04 10. " CE2 ,Override for CE2 partition" "AND,OR"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CE1 ,Override for CE1 partition" "AND,OR"
|
|
bitfld.long 0x04 8. " SAX ,SAX" "AND,OR"
|
|
textline " "
|
|
bitfld.long 0x04 7. " HEG ,Override for HEG partition" "AND,OR"
|
|
bitfld.long 0x04 6. " MPE ,Override for MPE partition" "AND,OR"
|
|
textline " "
|
|
bitfld.long 0x04 4. " VDE ,Override for VDE0 partition" "AND,OR"
|
|
bitfld.long 0x04 3. " PCX ,PCX" "AND,OR"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VE ,Override for VE partition" "AND,OR"
|
|
bitfld.long 0x04 1. " TD ,Override for TD partition" "AND,OR"
|
|
textline " "
|
|
line.long 0x08 "GPU_RG_CNTRL_0 ,GPU Rail Gating Register"
|
|
bitfld.long 0x08 0. " RAIL_CLAMP ,Enabling and removing GPU-SOC clamps" "Disabled,Enabled"
|
|
line.long 0x0C "SEC_DISABLE3_0, PMC SEC DISABLE 3_0 Controller"
|
|
bitfld.long 0x0C 23. " READ35 ,Disable reads from secure register 35" "Off,On"
|
|
bitfld.long 0x0C 22. " WRITE35 ,Disable writes to secure register 35" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " READ34 ,Disable reads from secure register 34" "Off,On"
|
|
bitfld.long 0x0C 20. " WRITE34 ,Disable writes to secure register 34" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " READ33 ,Disable reads from secure register 33" "Off,On"
|
|
bitfld.long 0x0C 18. " WRITE33 ,Disable writes from secure register 33" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " READ32 ,Disable reads from secure register 32" "Off,On"
|
|
bitfld.long 0x0C 16. " WRITE32 ,Disable writes to secure register 32" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " READ31 ,Disable reads from secure register 31" "Off,On"
|
|
bitfld.long 0x0C 14. " WRITE31 ,Disable writes to secure register 31" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " READ30 ,Disable reads from secure register 30" "Off,On"
|
|
bitfld.long 0x0C 12. " WRITE30 ,Disable writes to secure register 30" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " READ29 ,Disable reads from secure register 29" "Off,On"
|
|
bitfld.long 0x0C 10. " WRITE29 ,Disable writes from secure register 29" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " READ28 ,Disable reads from secure register 28" "Off,On"
|
|
bitfld.long 0x0C 8. " WRITE28 ,Disable writes to secure register 28" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " READ27 ,Disable reads from secure register 27" "Off,On"
|
|
bitfld.long 0x0C 6. " WRITE27 ,Disable writes from secure register 27" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " READ26 ,Disable reads to secure register 26" "Off,On"
|
|
bitfld.long 0x0C 4. " WRITE26 ,Disable writes from secure register 26" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " READ25 ,Disable reads to secure register 25" "Off,On"
|
|
bitfld.long 0x0C 2. " WRITE25 ,Disable writes from secure register 25" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " READ24 ,Disable reads from secure register 24" "Off,On"
|
|
bitfld.long 0x0C 0. " WRITE24 ,Disable writes from secure register 24" "Off,On"
|
|
textline " "
|
|
tree "Scratch Registers 4"
|
|
width 25.
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "SECURE_SCRATCH8_0,Secure scratch register 8"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "SECURE_SCRATCH9_0,Secure scratch register 9"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "SECURE_SCRATCH10_0,Secure scratch register 10"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "SECURE_SCRATCH11_0,Secure scratch register 11"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "SECURE_SCRATCH12_0,Secure scratch register 12"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "SECURE_SCRATCH13_0,Secure scratch register 13"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "SECURE_SCRATCH14_0,Secure scratch register 14"
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "SECURE_SCRATCH15_0,Secure scratch register 15"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "SECURE_SCRATCH16_0,Secure scratch register 16"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "SECURE_SCRATCH17_0,Secure scratch register 17"
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "SECURE_SCRATCH18_0,Secure scratch register 18"
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "SECURE_SCRATCH19_0,Secure scratch register 19"
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "SECURE_SCRATCH20_0,Secure scratch register 20"
|
|
group.long 0x334++0x03
|
|
line.long 0x00 "SECURE_SCRATCH21_0,Secure scratch register 21"
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "SECURE_SCRATCH22_0,Secure scratch register 22"
|
|
group.long 0x33C++0x03
|
|
line.long 0x00 "SECURE_SCRATCH23_0,Secure scratch register 23"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "SECURE_SCRATCH24_0,Secure scratch register 24"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "SECURE_SCRATCH25_0,Secure scratch register 25"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "SECURE_SCRATCH26_0,Secure scratch register 26"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "SECURE_SCRATCH27_0,Secure scratch register 27"
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "SECURE_SCRATCH28_0,Secure scratch register 28"
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "SECURE_SCRATCH29_0,Secure scratch register 29"
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "SECURE_SCRATCH30_0,Secure scratch register 30"
|
|
group.long 0x35C++0x03
|
|
line.long 0x00 "SECURE_SCRATCH31_0,Secure scratch register 31"
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "SECURE_SCRATCH32_0,Secure scratch register 32"
|
|
group.long 0x364++0x03
|
|
line.long 0x00 "SECURE_SCRATCH33_0,Secure scratch register 33"
|
|
group.long 0x368++0x03
|
|
line.long 0x00 "SECURE_SCRATCH34_0,Secure scratch register 34"
|
|
group.long 0x36C++0x03
|
|
line.long 0x00 "SECURE_SCRATCH35_0,Secure scratch register 35"
|
|
tree.end
|
|
width 19.
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "CNTRL_2_0,Wake interrupt,LP0BB,and Some Miscellaneous Controls"
|
|
bitfld.long 0x00 13. " KB_SYSCLK_PM_CFG ,Muxes between net kb_row3 and SYS_CLK_REQ and drives" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " HOLD_CKE_LOW_EN ,Enable for the PMC to assert CKE low" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SYSCLK_DATA ,SYS_CLK_REQ data value" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYSCLK_ORRIDE ,SYS_CLK_REQ data override mux control" "HW,SYSCLK_DATA"
|
|
textline " "
|
|
group.long 0x45C++0x0B
|
|
line.long 0x00 "IO_DPD3_REQ_0,DPD Request 3 Register"
|
|
bitfld.long 0x00 30.--31. " CODE ,Code of operation for all set bits" "IDLE,DPD_OFF,DPD_ON,"
|
|
bitfld.long 0x00 27. " DDR_DATA1_VTTGEN ,Mem0_data1_vttgen_4_6/_5_7_ pad" "Off,On"
|
|
bitfld.long 0x00 26. " DDR_DATA0_VTTGEN , Mem0_data0_vttgen_0_2/_1_3_pad" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DDR_CLKBUF1 ,Mem0_addr1/2_clkbuf_0/1_pad" "Off,On"
|
|
bitfld.long 0x00 24. " DDR_CLKBUF0 ,Mem0_addr0/3_clkbuf_0/1_pad" "Off,On"
|
|
bitfld.long 0x00 23. " DDR_ADDR1_VTTGEN ,Mem0_addr1/2_vttgen_0_pad" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DDR_ADDR0_VTTGEN ,Mem0_addr0/3_vttgen_0_pad" "Off,On"
|
|
bitfld.long 0x00 20. " DDR_CLK_VTTGEN ,Mem0_mclk0_vttgen_0_pad" "Off,On"
|
|
bitfld.long 0x00 19. " DDR_CLK_B ,Xm2_mclkb_pad" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DDR_CLK ,Xm2_mclk_pad" "Off,On"
|
|
bitfld.long 0x00 17. " DISC_BIAS ,Mem0_bias_0_pad" "Off,On"
|
|
bitfld.long 0x00 16. " DDR_MCS_B1 ,Xm2_mcs_b_1_pad" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DDR_MCS_B0 ,Xm2_mcs_b_0_pad" "Off,On"
|
|
bitfld.long 0x00 14. " DDR_MCKE_B1 ,Xm2_mcke_b_1_pad" "Off,On"
|
|
bitfld.long 0x00 12. " DDR_ODT_B1 ,Xm2_odt_b_0_pad" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DDR_ODT_B1 ,Xm2_odt_b_0_pad" "Off,On"
|
|
bitfld.long 0x00 10. " DDR_ADR1 ,Xm2_ma/mba/ma_b_pad" "Off,On"
|
|
bitfld.long 0x00 9. " DDR_ADR0 ,Xm2_ma/mras_n/mcas_n_pad" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DDR_RESET ,Xm2_reset_pad" "Off,On"
|
|
bitfld.long 0x00 7. " DDR_MCS1 ,Xm2_mcs_1_pad" "Off,On"
|
|
bitfld.long 0x00 6. " DDR_MCS0 ,Xm2_mcs_0_pad" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DDR_MCKE1 ,Xm2_mcke_1_pad" "Off,On"
|
|
bitfld.long 0x00 4. " DDR_MCKE0 ,XM2_mcke_0_pad" "Off,On"
|
|
bitfld.long 0x00 3. " DDR_ODT1 ,Xm2_odt_1_pad" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DDR_DATA1 ,Xm2_data(0,1,2,3)_pad" "Off,On"
|
|
bitfld.long 0x00 1. " DDR_DATA1 ,Xm2_data(0,1,2,3)_pad" "Off,On"
|
|
bitfld.long 0x00 0. " DDR_DATA0 ,Xm2_data(4,5,6,7)_pad" "Off,On"
|
|
textline " "
|
|
line.long 0x04 "IO_DPD3_SATUS_0,DPD Status 3 register"
|
|
bitfld.long 0x04 27. " DDR_DATA_1_VTTGEN ,Mem0_data1_vttgen_4_6/5_7_pad" "Off,On"
|
|
bitfld.long 0x04 26. " DDR_DATA0_VTTGEN ,Mem0_data0_vttgen_0_2/1_3_pad" "Off,On"
|
|
bitfld.long 0x04 25. " DDR_CLK_BUF1 ,Mem0_addr1/2_clkbuf_0_pad" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 24. " DDR_CLKBUF0 ,Mem0_addr0/3_clkbuf_0/1_pad" "Off,On"
|
|
bitfld.long 0x04 23. " DDR_ADDR1_VTTGEN ,Mem0_addr1/2_vttgen_0_pad" "Off,On"
|
|
bitfld.long 0x04 22. " DDR_ADDR0_VTTGEN ,Mem0_addr0/3_vttgen_0_pad" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 20. " DDR_CLK_VTTGEN ,Mem0_mclk0_vttgen_0_pad" "Off,On"
|
|
bitfld.long 0x04 19. " DDR_CLK_B ,Xm2_mclkb_pad" "Off,On"
|
|
bitfld.long 0x04 18. " DDR_CLK ,Xm2_mclk_pad" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 17. " DISC_BIAS , mem0_bias_0_pad" "Off,On"
|
|
bitfld.long 0x04 16. " DDR_MCS_B1 ,Xm2_mcs_b_1_pad" "Off,On"
|
|
bitfld.long 0x04 15. " DDR_MCS_B0 ,Xm2_mcs_b_0_pad" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 14. " DDR_MCKE_B1 ,Xm2_mcke_b_1_pad" "Off,On"
|
|
bitfld.long 0x04 13. " DDR_MCKE_B0 ,Xm2_mcke_b_0_pad" "Off,On"
|
|
bitfld.long 0x04 12. " DDR_ODT_B1 ,Xm2_odt_b_1_pad" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 11. " DDR_ODT_B0 ,Xm2_odt_b_0_pad" "Off,On"
|
|
bitfld.long 0x04 10. " DDR_ADDR1 ,Xm2_ma/mba/ma_b_pad" "Off,On"
|
|
bitfld.long 0x04 9. " DDR_ADDR0 ,Xm2_ma/mras_n/mcas_n_pad" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DDR_RESET ,Xm2_reset_pad" "Off,On"
|
|
bitfld.long 0x04 7. " DDR_MCS1 ,Xm2_mcs_1_pad" "Off,On"
|
|
bitfld.long 0x04 6. " DDR_MCKE1 ,Xm2_mcs_0_pad" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 5. " DDR_MCKE1 ,Xm2_mcke_1_pad" "Off,On"
|
|
bitfld.long 0x04 4. " DDR_MCKE0 ,Xm2_mcke_0_pad" "Off,On"
|
|
bitfld.long 0x04 3. " DDR_ODT1 ,Xm2_odt_1_pad" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DDR_DATA1 ,Xm2_odt_0_pad" "Off,On"
|
|
bitfld.long 0x04 1. " DDR_DATA1 ,Xm2_data(0,1,2,3)_pad" "Off,On"
|
|
bitfld.long 0x04 0. " DDR_DATA0 ,Xm2_data(4,5,6,7)_pad" "Off,On"
|
|
textline " "
|
|
line.long 0x08 "STRAPPING_OPT_A_0,Strapping options Register"
|
|
bitfld.long 0x08 26.--29. " BOOT_SELECT ,Read at power-on reset time from gmi_ad strap pads" "MPCORE_G,MPCORE_LP,..."
|
|
bitfld.long 0x08 25. " BOOT_SRC_USB_RECOVERY_MODE ,Read at power_on reset time from gmi_oe_n strap pad" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " BOOT_SRC_NOR_BOOT ,Read at power-on reset time from gmi_wr_n strap pad" "IROM,NOR"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " ARM_JTAG ,Read at power-on reset time from gmi_ad strap pads" "SERIAL,CPU,COP,SERIAL_ALT"
|
|
bitfld.long 0x08 9. " BOOT_FAST_UART ,UART Boot speed from TMC JTAG config bit" "SLOW,FAST"
|
|
bitfld.long 0x08 8. " MIO_WIDTH ,MIO_WIDTH" "RSVD1,RSVD2"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " RAM_CODE ,Read at power-on reset time from gmi_ad" "LPDDR3_800,ELPIDA_LPDDR2,RSVD2,DDR3_2GB,RSVD4,DDR3_2GB_NO_DSR,DDR3_934,DDR3_800,RSVD8,DDR3_x64_2GB,DDR3_X64_8GB_667,DDR3_X64_8GB_800,..."
|
|
bitfld.long 0x08 0. " NOR_WIDTH ,NOR_WIDTH" "RSVD1,RSVD2"
|
|
textline " "
|
|
tree "Scratch Registers 5"
|
|
width 16.
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SCRATCH56_0,General purpose register storage 56"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "SCRATCH57_0,General purpose register storage 57"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "SCRATCH58_0,General purpose register storage 58"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "SCRATCH59_0,General purpose register storage 59"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "SCRATCH60_0,General purpose register storage 60"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "SCRATCH61_0,General purpose register storage 61"
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "SCRATCH62_0,General purpose register storage 62"
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "SCRATCH63_0,General purpose register storage 63"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "SCRATCH64_0,General purpose register storage 64"
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "SCRATCH65_0,General purpose register storage 65"
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "SCRATCH66_0,General purpose register storage 66"
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "SCRATCH67_0,General purpose register storage 67"
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "SCRATCH68_0,General purpose register storage 68"
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "SCRATCH69_0,General purpose register storage 69"
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "SCRATCH70_0,General purpose register storage 70"
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "SCRATCH71_0,General purpose register storage 71"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "SCRATCH72_0,General purpose register storage 72"
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "SCRATCH73_0,General purpose register storage 73"
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "SCRATCH74_0,General purpose register storage 74"
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "SCRATCH75_0,General purpose register storage 75"
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "SCRATCH76_0,General purpose register storage 76"
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "SCRATCH77_0,General purpose register storage 77"
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "SCRATCH78_0,General purpose register storage 78"
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "SCRATCH79_0,General purpose register storage 79"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "SCRATCH80_0,General purpose register storage 80"
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "SCRATCH81_0,General purpose register storage 81"
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "SCRATCH82_0,General purpose register storage 82"
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "SCRATCH83_0,General purpose register storage 83"
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "SCRATCH84_0,General purpose register storage 84"
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "SCRATCH85_0,General purpose register storage 85"
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "SCRATCH86_0,General purpose register storage 86"
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "SCRATCH87_0,General purpose register storage 87"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "SCRATCH88_0,General purpose register storage 88"
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "SCRATCH89_0,General purpose register storage 89"
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "SCRATCH90_0,General purpose register storage 90"
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "SCRATCH91_0,General purpose register storage 91"
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "SCRATCH92_0,General purpose register storage 92"
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "SCRATCH93_0,General purpose register storage 93"
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "SCRATCH94_0,General purpose register storage 94"
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "SCRATCH95_0,General purpose register storage 95"
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "SCRATCH96_0,General purpose register storage 96"
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "SCRATCH97_0,General purpose register storage 97"
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "SCRATCH98_0,General purpose register storage 98"
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "SCRATCH99_0,General purpose register storage 99"
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "SCRATCH100_0,General purpose register storage 100"
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "SCRATCH101_0,General purpose register storage 101"
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "SCRATCH102_0,General purpose register storage 102"
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "SCRATCH103_0,General purpose register storage 103"
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "SCRATCH104_0,General purpose register storage 104"
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "SCRATCH105_0,General purpose register storage 105"
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "SCRATCH106_0,General purpose register storage 106"
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "SCRATCH107_0,General purpose register storage 107"
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "SCRATCH108_0,General purpose register storage 108"
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "SCRATCH109_0,General purpose register storage 109"
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "SCRATCH110_0,General purpose register storage 110"
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "SCRATCH111_0,General purpose register storage 111"
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "SCRATCH112_0,General purpose register storage 112"
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "SCRATCH113_0,General purpose register storage 113"
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "SCRATCH114_0,General purpose register storage 114"
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "SCRATCH115_0,General purpose register storage 115"
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "SCRATCH116_0,General purpose register storage 116"
|
|
group.long 0x6F4++0x03
|
|
line.long 0x00 "SCRATCH117_0,General purpose register storage 117"
|
|
group.long 0x6F8++0x03
|
|
line.long 0x00 "SCRATCH118_0,General purpose register storage 118"
|
|
group.long 0x6FC++0x03
|
|
line.long 0x00 "SCRATCH119_0,General purpose register storage 119"
|
|
tree.end
|
|
;No base address in memory map
|
|
; tree "Secure Boot Control"
|
|
; width 18.
|
|
; group.long 0x00++0x0B
|
|
; line.long 0x00 "SB_CSR_0,Secure boot control status register"
|
|
; bitfld.long 0x00 12.--15. " COT_FAIL_COUNT ,Chain-of-Trust fail count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
; bitfld.long 0x00 8.--11. " SWDM_FAIL_COUNT ,Secure watchdog monitor fail count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
; bitfld.long 0x00 7. " SWDM_ENABLE ,Secure watchdog monitor enable" "Disabled,Enabled"
|
|
; textline " "
|
|
; bitfld.long 0x00 6. " HANG ,Secure boot hang" "Disabled,Enabled"
|
|
; bitfld.long 0x00 5. " JTAG_DISABLE ,Secure JTAG disable" "Enabled,Disabled"
|
|
; bitfld.long 0x00 4. " PIROM_DISABLE ,Protected iROM disable" "Enabled,Disabled"
|
|
; textline " "
|
|
; bitfld.long 0x00 1. " NS_RST_VEC_WR_DIS ,Non-secure reset vector write disable" "Enabled,Disabled"
|
|
; bitfld.long 0x00 0. " SECURE_BOOT_FLAG ,Booted into secure mode" "Disabled,Enabled"
|
|
; line.long 0x04 "SB_PIROM_START_0,Secure boot protected ROM start"
|
|
; line.long 0x08 "SB_PFCFG_0,Secure boot processor feature configuration register"
|
|
; bitfld.long 0x08 24. " CS_DEADSTATUS_EN ,Coresight Debug bit to enable return codes on bad accesses" "Disabled,Enabled"
|
|
; bitfld.long 0x08 23. " CS_ACCESS_CHECK_EN ,Debug bit to Enable Checking for bad Csite accesses such as when CPU not in active partition" "Disabled,Enabled"
|
|
; bitfld.long 0x08 22. " CS_CODES_EN ,Coresight Debug bit to Enable Status Codes" "Disabled,Enabled"
|
|
; textline " "
|
|
; bitfld.long 0x08 21. " CS_TIMEOUT_TM ,Coresight Timeout Testmode" "Disabled,Enabled"
|
|
; rbitfld.long 0x08 20. " DBGACK_AVP ,DBGACKnowledge Status from AVP" "Disabled,Enabled"
|
|
; rbitfld.long 0x08 19. " DBGACK_CPU3 ,DBGACKnowledge Status from CPU3" "Disabled,Enabled"
|
|
; textline " "
|
|
; rbitfld.long 0x08 18. " DBGACK_CPU2 ,DBGACKnowledge Status from CPU2" "Disabled,Enabled"
|
|
; rbitfld.long 0x08 17. " DBGACK_CPU1 ,DBGACKnowledge Status from CPU1" "Disabled,Enabled"
|
|
; rbitfld.long 0x08 16. " DBGACK_CPU0 ,DBGACKnowledge Status from CPU0 " "Disabled,Enabled"
|
|
; textline " "
|
|
; bitfld.long 0x08 12. " EDBGRQ_AVP ,External Debug Request for AVP" "Disabled,Enabled"
|
|
; bitfld.long 0x08 11. " EDBGRQ_CPU3 ,External Debug Request for CPU3 via coresight" "Disabled,Enabled"
|
|
; bitfld.long 0x08 10. " EDBGRQ_CPU2 ,External Debug Request for CPU2 via coresight" "Disabled,Enabled"
|
|
; textline " "
|
|
; bitfld.long 0x08 9. " EDBGRQ_CPU1 ,External Debug Request for CPU1 via coresight" "Disabled,Enabled"
|
|
; bitfld.long 0x08 8. " EDBGRQ_CPU0 ,External Debug Request for CPU0 via coresight" "Disabled,Enabled"
|
|
; bitfld.long 0x08 7. " CS_TIMEOUT_EN ,Coresight Timeout Enable RTCK delay control" "Disabled,Enabled"
|
|
; textline " "
|
|
; bitfld.long 0x08 6. " CS_RTCK_SPEED ,RTCK delay (Synchronized or Direct)" "Slow,Fast"
|
|
; bitfld.long 0x08 5. " CP15SDISABLE ,Disable access to system control registers enum" "Enabled,Disabled"
|
|
; bitfld.long 0x08 4. " CFGSDISABLE ,Disable access to secure control registers" "Enabled,Disabled"
|
|
; textline " "
|
|
; bitfld.long 0x08 3. " DBGEN ,Debug Enable (Not the same as JTAG enable)" "Disabled,Enabled"
|
|
; bitfld.long 0x08 2. " NIDEN ,Non-Invasive Debug Enable" "Disabled,Enabled"
|
|
; bitfld.long 0x08 1. " SPIDEN ,Secure Privileged Invasive Debug Enable" "Disabled,Enabled"
|
|
; textline " "
|
|
; bitfld.long 0x08 0. " SPNIDEN ,Secure Privileged Non-Invasive Debug Enable" "Disabled,Enabled"
|
|
; tree.end
|
|
width 0xb
|
|
; tree "PMCC0"
|
|
; base ad:
|
|
; %include tegrak1/pmcc0.ph
|
|
; tree.end
|
|
; tree "PMCC1"
|
|
; base ad:
|
|
; %include tegrak1/pmcc1.ph
|
|
; tree.end
|
|
tree.end
|
|
tree "RTC"
|
|
base ad:0x7000E000
|
|
width 33.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONTROL_0,Control Register"
|
|
bitfld.long 0x00 0. " WR_SEC_CNT ,Disable writes to SECONDS counter" "No,Yes"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "BUSY_0,Busy Register"
|
|
bitfld.long 0x00 0. " STATUS ,Idle and busy status" "Idle,Busy"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SECONDS_0,Seconds Counter Register"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "SHADOW_SECONDS_0,Shadowed Seconds Counter Register"
|
|
line.long 0x04 "MILLI_SECONDS_0,Milliseconds Counter Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " MILLI_SECONDS ,Milliseconds counter increments using Bresenham algorithm"
|
|
group.long 0x14++0x1B
|
|
line.long 0x00 "SECONDS_ALARM0_0,Seconds Alarm0 Register"
|
|
line.long 0x04 "SECONDS_ALARM1_0,Seconds Alarm1 Register"
|
|
line.long 0x08 "MILLI_SECONDS_ALARM_0,Milliseconds Alarm Register"
|
|
hexmask.long.word 0x08 0.--9. 1. " MSEC_MATCH_VALUE ,Milliseconds match value"
|
|
line.long 0x0C "SECONDS_COUNTDOWN_ALARM_0,Countdown Alarm Register"
|
|
bitfld.long 0x0C 31. " ENABLE ,Enable bit for the countdown operation" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " REPEAT ,Repeat bit for the countdown operation" "Disabled,Enabled"
|
|
hexmask.long 0x0C 0.--29. 1. " VALUE ,Number of milliseconds to countdown"
|
|
line.long 0x10 "MILLI_SECONDS_COUNTDOWN_ALARM_0,Countdown Milliseconds Alarm Register"
|
|
bitfld.long 0x10 31. " ENABLE ,Enable bit for the countdown operation" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " REPEAT ,Repeat bit for the countdown operation" "Disabled,Enabled"
|
|
hexmask.long 0x10 0.--29. 1. " VALUE ,Number of milliseconds to countdown"
|
|
line.long 0x14 "INTR_MASK_0,Interrupt Mask Register"
|
|
bitfld.long 0x14 4. " MSEC_CDN_ALARM ,MSEC_CDN_ALARM interrupt" "Not masked,Masked"
|
|
bitfld.long 0x14 3. " SEC_CDN_ALARM ,SEC_CDN_ALARM interrupt" "Not masked,Masked"
|
|
bitfld.long 0x14 2. " MSEC_ALARM ,MSEC_ALARM interrupt" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x14 1. " SEC_ALARM1 ,SEC_ALARM1 interrupt" "Not masked,Masked"
|
|
bitfld.long 0x14 0. " SEC_ALARM0 ,SEC_ALARM0 interrupt" "Not masked,Masked"
|
|
line.long 0x18 "INTR_STATUS_0,Interrupt Status Register"
|
|
eventfld.long 0x18 4. " MSEC_CDN_ALARM ,MSEC_CDN_ALARM interrupt condition condition" "No interrupt,Interrupt"
|
|
eventfld.long 0x18 3. " SEC_CDN_ALARM ,SEC_CDN_ALARM interrupt condition" "No interrupt,Interrupt"
|
|
eventfld.long 0x18 2. " MSEC_ALARM ,MSEC_ALARM interrupt condition" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x18 1. " SEC_ALARM1 ,SEC_ALARM1 interrupt condition" "No interrupt,Interrupt"
|
|
eventfld.long 0x18 0. " SEC_ALARM0 ,SEC_ALARM0 interrupt condition" "No interrupt,Interrupt"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "INTR_SOURCE_0,Interrupt Source Register"
|
|
bitfld.long 0x00 4. " MSEC_CDN_ALARM ,MSEC_CDN_ALARM interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " SEC_CDN_ALARM ,SEC_CDN_ALARM interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " MSEC_ALARM ,MSEC_ALARM interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEC_ALARM1 ,SEC_ALARM1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " SEC_ALARM0 ,SEC_ALARM0 interrupt" "No interrupt,Interrupt"
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "INTR_SET_0,Interrupt Set Register"
|
|
bitfld.long 0x00 4. " MSEC_CDN_ALARM ,MSEC_CDN_ALARM interrupt status bit" "Not set,Set"
|
|
bitfld.long 0x00 3. " SEC_CDN_ALARM ,SEC_CDN_ALARM interrupt status bit" "Not set,Set"
|
|
bitfld.long 0x00 2. " MSEC_ALARM ,MSEC_ALARM interrupt status bit" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEC_ALARM1 ,SEC_ALARM1 interrupt status bit" "Not set,Set"
|
|
bitfld.long 0x00 0. " SEC_ALARM0 ,SEC_ALARM0 interrupt status bit" "Not set,Set"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CORRECTION_FACTOR_0,Correction Factor Register"
|
|
bitfld.long 0x00 9. " DIRECTION ,Direction status" "Decrement,Increment"
|
|
hexmask.long.word 0x00 0.--8. 1. " PPM ,PPM value"
|
|
width 0xb
|
|
tree.end
|
|
tree "Host Subsystem"
|
|
tree "Channel 0"
|
|
base ad:0x50000000
|
|
width 27.
|
|
tree "Channel Registers"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CHANNEL_FIFOSTAT_0,Host1X Channel FIFOSTAT_0"
|
|
bitfld.long 0x00 31. " INDRDY ,Indicates that INDCOUNT == 0 so it should be OK to issue another read" "0,1"
|
|
bitfld.long 0x00 24.--28. " OUTFENTRIES ,Number of entries available for reading in this channel's output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " REGNUMEMPTY ,Register write/read FIFO free count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CFGATHER ,Indicates whether GATHER is active" "Idle,Busy"
|
|
bitfld.long 0x00 11. " CFEMPTY ,Indicates whether the command FIFO is empty" "Not empty,Empty"
|
|
hexmask.long.word 0x00 0.--10. 1. " CFNUMEMPTY ,Command FIFO free count"
|
|
if (((per.l(ad:0x50000000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type: Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long 0x00 2.--25. 0x04 " INDOFFSET ,Frame buffer address"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type:Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET ,Register offset"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
endif
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "CHANNEL_INDICT_0,Indirect Register Access Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDCOUNT ,Indcount"
|
|
line.long 0x04 "CHANNEL_IDDATA_0,Host1X Channel INDDATA_0"
|
|
line.long 0x08 "CHANNEL_RAISE_0,DMA And RAISE/REFCOUNT Functionality"
|
|
hexmask.long 0x08 2.--31. 1. " RAISE ,Channel's RAISE vector"
|
|
line.long 0x0C "CHANNEL_DMASTART_0,Host1X Channel DMSTART_0"
|
|
hexmask.long 0x0C 2.--31. 0x04 " DMASTART ,Cmdbuf frame buffer ofset"
|
|
line.long 0x10 "CHANNEL_DMAPUT_0, Host1X Channel DMAPUT_0"
|
|
hexmask.long 0x10 2.--31. 0x04 " DMAPUT ,Cmdbuf frame buffer offset"
|
|
rgroup.long 0x1C++0x0B
|
|
line.long 0x00 "CHANNEL_DMAGET_0,Host1X Channel DMAGET_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " DMAGET ,Cmdbuf frame buffer offset"
|
|
line.long 0x04 "CHANNEL_DMAEND_0 ,Host1X Channel DMAEND_0"
|
|
hexmask.long 0x04 2.--31. 0x04 " DMAEND ,Cmdbuf frame buffer offset"
|
|
line.long 0x08 "CHANNEL_DMACTRL_0,DMA Control Register"
|
|
bitfld.long 0x08 2. " DMAINITGET ,Reset GET pointer to the value of DMAPUT when DMAGETRST is asserted" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " DMAGETRST ,Reset GET pointer to 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " DMASTOP ,Stop DMA from fetching on this channel" "Run,Stop"
|
|
if (((per.l(ad:0x50000000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " INDOFFSET2 ,Frame buffer address"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID2 ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET2 ,Register offset"
|
|
endif
|
|
group.long 0x90++0x2B
|
|
line.long 0x00 "CHANNEL_TICKCOUNT_HI_0,Host1X Channel TICKCOUNT HI 0"
|
|
line.long 0x04 "CHANNEL_TICKCOUNT_LO_0,Host1X Channel TICKCOUNT LO 0"
|
|
line.long 0x08 "CHANNEL_CHANNELCTRL_0,Host1X Channel CHANNELCTRL_0"
|
|
bitfld.long 0x08 2. " KERNEL_FILTER_GBUFFER ,Enable setclass command filter for gather buffers" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ENABLETICKCNT ,Enable tick counter" "Disabled,Enabled"
|
|
line.long 0x0C "CHANNEL_PAYLOAD_0,Host1X Channel PAYLOAD_0"
|
|
line.long 0x10 "CHANNEL_STALLCTRL_0,Host1X Channel STALLCTRL_0"
|
|
bitfld.long 0x10 0. " ENABLE_CHANNEL_STALL ,Enable channel STALL" "Disabled,Enabled"
|
|
line.long 0x14 "CHANNEL_STALLCOUNT_HI_0,Host1X Channel STALLCOUNT Hi 0"
|
|
line.long 0x18 "CHANNEL_STALLCOUNT_LO_0,Host1X Channel STALLCOUNT Lo 0"
|
|
line.long 0x1C "CHANNEL_XFERCTRL_0,Host1X Channel XFERCTRL 0"
|
|
bitfld.long 0x1C 0. " ENABLE_CHANNEL_XFER ,Enable channel XFER" "Disabled,Enabled"
|
|
line.long 0x20 "CHANNEL_CHANNEL_XFER_HI_0,Host1X Channel XFER Hi 0"
|
|
line.long 0x24 "CHANNEL_CHANNEL_XFER_LO_0,Host1X Channel XFER Lo 0"
|
|
line.long 0x28 "CHANNEL_CHANNEL_SPARE_0,Host1x Channel SPARE 0"
|
|
hexmask.long.word 0x28 16.--31. 1. " CHANNEL_SPARE_HI ,Channel SPARE Hi"
|
|
hexmask.long.word 0x28 0.--15. 1. " CHANNEL_SPARE_LO ,CHannel SPARE Lo"
|
|
tree.end
|
|
; base (ad:0x50000000+0x2000) - ACTMON1(MSENC)
|
|
; base (ad:0x50000000+0x2040) - ACTMON2(VIC)
|
|
width 23.
|
|
base (ad:0x50000000+0x2100)
|
|
tree "SYNC (Synchronous Registers)"
|
|
sif CPUIS("TEGRAX1")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " VII2C_INT , VII2C interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOR1_INT ,SOR1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NVENC_INT ,NVENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " NVDEC_INT ,NVDEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 14. " NVJPG_INT ,NVJPG interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " TSECB_INT ,TSECB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " DPAUX1_INT ,DPAUX1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 4. " CPU_TZ_ILLEGAL_TZ_ACCESS_MASK ,Mask CPU_TZ_ILLEGAL_TZ_ACCESS" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 27. " VII2C_INT_C0MASK ,Interrupt mask for VII2C interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SOR1_INT_C0MASK ,Interrupt mask for SOR1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " NVENC_INT_C0MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " NVDEC_INT_C0MASK ,Interrupt mask for NVDEC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NVJPG_INT_C0MASK ,Interrupt mask for NVJPG interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " TSECB_INT_C0MASK ,Interrupt mask for TSECB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " DPAUX1_INT_C0MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 27. " VII2C_INT_C1MASK ,Interrupt mask for VII2C interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 22. " SOR1_INT_C1MASK ,Interrupt mask for SOR1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NVENC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " NVDEC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 14. " NVJPG_INT_C1MASK ,Interrupt mask for NVJPG interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " TSECB_INT_C1MASK ,Interrupt mask for TSECB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " DPAUX1_INT_C1MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " XBAR_TSEC_TIMEOUT_ID ,Id of the CPU which timed out and updated" "TSEC,XBAR"
|
|
eventfld.long 0x00 21. " WAIT_INT13 ,WAIT has completed on channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " WAIT_INT12 ,WAIT has completed on channel 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,Invalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " WAIT_INT13 ,WAIT interrupt mask 13" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " WAIT_INT12 ,WAIT interrupt mask 12" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 ACTMON interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 13. " CMDPP_ILLEGAL_OPCODE_INT13 ,CMPP 13 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 12. " CMDPP_ILLEGAL_OPCODE_INT12 ,CMPP 12 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " CMDPP_ILLEGAL_OPCODE_INTMASK13 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 12. " CMDPP_ILLEGAL_OPCODE_INTMASK12 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--13. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
wgroup.long 0xB0++0x0B
|
|
line.long 0x00 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x00 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x04 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x04 27. " VII2C_TEARDOWN ,VII2C teardown" "No action,Teardown"
|
|
bitfld.long 0x04 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x04 22. " SOR1_TEARDOWN ,SOR1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x04 19. " NVENC_TEARDOWN ,NVENC teardown" "No action,Teardown"
|
|
bitfld.long 0x04 18. " NVDEC_TEARDOWN ,NVEDC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 14. " NVJPG_TEARDOWN ,JVJPG teardown" "No action,Teardown"
|
|
bitfld.long 0x04 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " TSECB_TEARDOWN ,TSECB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DPAUX1_TEARDOWN ,DPAUX1 teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x47
|
|
line.long 0x00 "SYNC_DISPLAY_STATUS_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_STATUS_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_STATUS_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_STATUS_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_SOR1_STATUS_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,SOR1 currcl"
|
|
line.long 0x14 "SYNC_SOR_STATUS,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_STATUS_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_STATUS_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_STATUS_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_STATUS_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_NVENC_STATUS_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,NVENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_STATUS_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
line.long 0x34 "SYNC_NVDEC_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x34 16.--25. 1. " ISPB_CURRCL ,NVDEC currcl"
|
|
line.long 0x38 "SYNC_NVJPG_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x38 16.--25. 1. " ISPB_CURRCL ,NVJPG currcl"
|
|
line.long 0x3C "SYNC_VII2C_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x3C 16.--25. 1. " ISPB_CURRCL ,VII2C currcl"
|
|
line.long 0x40 "SYNC_DPAUX1_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x40 16.--25. 1. " ISPB_CURRCL ,DPAUX1 currcl"
|
|
line.long 0x44 "SYNC_TSECB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x44 16.--25. 1. " ISPB_CURRCL ,TSECB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
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|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 13. " HIPRI_CH13 ,HIPRI ch 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " HIPRI_CH12 ,HIPRI ch 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " MSENC_INT ,MSENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " HDMI_INT ,HDMi int " "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " MSENC_INT_C0MASK ,Interrupt mask for MSENC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " HDMI_INT_C0MASK ,Interrupt mask for HDMI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 19. " MSENC_INT_C1MASK ,Interrupt mask for MSENC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HDMI_INT_C1MASK ,Interrupt mask for HDMI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,INvalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " XBAR_TSEC_TIMEOUT_ID ,ID of the CPU which timed out and updated the timeout address" "Tsec,Xbar"
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 actmon interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 actmon interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--11. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
line.long 0x04 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x04 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x08 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x08 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
bitfld.long 0x08 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x08 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x08 19. " MSENC_TEARDOWN ,MSENC teardown" "No action,Teardown"
|
|
bitfld.long 0x08 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 10. " HDMI_TEARDOWN ,HDMI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x33
|
|
line.long 0x00 "SYNC_DISPLAY_Status_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_Status_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_Status_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_Status_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_HDMI_Status_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,HDMI currcl"
|
|
line.long 0x14 "SYNC_SOR_Status,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_Status_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_Status_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_Status_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_Status_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_MSENC_Status_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,MSENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_Status_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_Status_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
endif
|
|
width 23.
|
|
tree "MLOCK registers"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_0_0,Host1X Sync MLOCK_0_0"
|
|
bitfld.long 0x00 0. " MLOCK_0 ,Mlock_0" "Released,Held"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_1_0,Host1X Sync MLOCK_1_0"
|
|
bitfld.long 0x00 0. " MLOCK_1 ,Mlock_1" "Released,Held"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_2_0,Host1X Sync MLOCK_2_0"
|
|
bitfld.long 0x00 0. " MLOCK_2 ,Mlock_2" "Released,Held"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_3_0,Host1X Sync MLOCK_3_0"
|
|
bitfld.long 0x00 0. " MLOCK_3 ,Mlock_3" "Released,Held"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_4_0,Host1X Sync MLOCK_4_0"
|
|
bitfld.long 0x00 0. " MLOCK_4 ,Mlock_4" "Released,Held"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_5_0,Host1X Sync MLOCK_5_0"
|
|
bitfld.long 0x00 0. " MLOCK_5 ,Mlock_5" "Released,Held"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_6_0,Host1X Sync MLOCK_6_0"
|
|
bitfld.long 0x00 0. " MLOCK_6 ,Mlock_6" "Released,Held"
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_7_0,Host1X Sync MLOCK_7_0"
|
|
bitfld.long 0x00 0. " MLOCK_7 ,Mlock_7" "Released,Held"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_8_0,Host1X Sync MLOCK_8_0"
|
|
bitfld.long 0x00 0. " MLOCK_8 ,Mlock_8" "Released,Held"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_9_0,Host1X Sync MLOCK_9_0"
|
|
bitfld.long 0x00 0. " MLOCK_9 ,Mlock_9" "Released,Held"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_10_0,Host1X Sync MLOCK_10_0"
|
|
bitfld.long 0x00 0. " MLOCK_10 ,Mlock_10" "Released,Held"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_11_0,Host1X Sync MLOCK_11_0"
|
|
bitfld.long 0x00 0. " MLOCK_11 ,Mlock_11" "Released,Held"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_12_0,Host1X Sync MLOCK_12_0"
|
|
bitfld.long 0x00 0. " MLOCK_12 ,Mlock_12" "Released,Held"
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_13_0,Host1X Sync MLOCK_13_0"
|
|
bitfld.long 0x00 0. " MLOCK_13 ,Mlock_13" "Released,Held"
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_14_0,Host1X Sync MLOCK_14_0"
|
|
bitfld.long 0x00 0. " MLOCK_14 ,Mlock_14" "Released,Held"
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_15_0,Host1X Sync MLOCK_15_0"
|
|
bitfld.long 0x00 0. " MLOCK_15 ,Mlock_15" "Released,Held"
|
|
textline " "
|
|
rgroup.long 0x340++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_0_0,Host1X Sync MLOCK Owner 0_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_0 ,Mlock owner chid 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_0 ,MLOCK CPU owns 0" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_0 ,MLOCK CH owns 0" "Not owned,Owned"
|
|
rgroup.long 0x344++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_1_0,Host1X Sync MLOCK Owner 1_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_1 ,Mlock owner chid 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_1 ,MLOCK CPU owns 1" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_1 ,MLOCK CH owns 1" "Not owned,Owned"
|
|
rgroup.long 0x348++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_2_0,Host1X Sync MLOCK Owner 2_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_2 ,Mlock owner chid 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_2 ,MLOCK CPU owns 2" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_2 ,MLOCK CH owns 2" "Not owned,Owned"
|
|
rgroup.long 0x34C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_3_0,Host1X Sync MLOCK Owner 3_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_3 ,Mlock owner chid 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_3 ,MLOCK CPU owns 3" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_3 ,MLOCK CH owns 3" "Not owned,Owned"
|
|
rgroup.long 0x350++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_4_0,Host1X Sync MLOCK Owner 4_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_4 ,Mlock owner chid 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_4 ,MLOCK CPU owns 4" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_4 ,MLOCK CH owns 4" "Not owned,Owned"
|
|
rgroup.long 0x354++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_5_0,Host1X Sync MLOCK Owner 5_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_5 ,Mlock owner chid 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_5 ,MLOCK CPU owns 5" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_5 ,MLOCK CH owns 5" "Not owned,Owned"
|
|
rgroup.long 0x358++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_6_0,Host1X Sync MLOCK Owner 6_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_6 ,Mlock owner chid 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_6 ,MLOCK CPU owns 6" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_6 ,MLOCK CH owns 6" "Not owned,Owned"
|
|
rgroup.long 0x35C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_7_0,Host1X Sync MLOCK Owner 7_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_7 ,Mlock owner chid 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_7 ,MLOCK CPU owns 7" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_7 ,MLOCK CH owns 7" "Not owned,Owned"
|
|
rgroup.long 0x360++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_8_0,Host1X Sync MLOCK Owner 8_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_8 ,Mlock owner chid 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_8 ,MLOCK CPU owns 8" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_8 ,MLOCK CH owns 8" "Not owned,Owned"
|
|
rgroup.long 0x364++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_9_0,Host1X Sync MLOCK Owner 9_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_9 ,Mlock owner chid 9" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_9 ,MLOCK CPU owns 9" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_9 ,MLOCK CH owns 9" "Not owned,Owned"
|
|
rgroup.long 0x368++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_10_0,Host1X Sync MLOCK Owner 10_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_10 ,Mlock owner chid 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_10 ,MLOCK CPU owns 10" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_10 ,MLOCK CH owns 10" "Not owned,Owned"
|
|
rgroup.long 0x36C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_11_0,Host1X Sync MLOCK Owner 11_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_11 ,Mlock owner chid 11" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_11 ,MLOCK CPU owns 11" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_11 ,MLOCK CH owns 11" "Not owned,Owned"
|
|
rgroup.long 0x370++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_12_0,Host1X Sync MLOCK Owner 12_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_12 ,Mlock owner chid 12" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_12 ,MLOCK CPU owns 12" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_12 ,MLOCK CH owns 12" "Not owned,Owned"
|
|
rgroup.long 0x374++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_13_0,Host1X Sync MLOCK Owner 13_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_13 ,Mlock owner chid 13" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_13 ,MLOCK CPU owns 13" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_13 ,MLOCK CH owns 13" "Not owned,Owned"
|
|
rgroup.long 0x378++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_14_0,Host1X Sync MLOCK Owner 14_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_14 ,Mlock owner chid 14" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_14 ,MLOCK CPU owns 14" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_14 ,MLOCK CH owns 14" "Not owned,Owned"
|
|
rgroup.long 0x37C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_15_0,Host1X Sync MLOCK Owner 15_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_15 ,Mlock owner chid 15" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_15 ,MLOCK CPU owns 15" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_15 ,MLOCK CH owns 15" "Not owned,Owned"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_ERROR_0_0,Host1X Sync Mlock Error 0_0"
|
|
bitfld.long 0x00 15. " MLOCK_ERROR_15 ,Mlock error 15" "No error,Error"
|
|
bitfld.long 0x00 14. " MLOCK_ERROR_14 ,Mlock error 14" "No error,Error"
|
|
bitfld.long 0x00 13. " MLOCK_ERROR_13 ,Mlock error 13" "No error,Error"
|
|
bitfld.long 0x00 12. " MLOCK_ERROR_12 ,Mlock error 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MLOCK_ERROR_11 ,Mlock error 11" "No error,Error"
|
|
bitfld.long 0x00 10. " MLOCK_ERROR_10 ,Mlock error 10" "No error,Error"
|
|
bitfld.long 0x00 9. " MLOCK_ERROR_9 ,Mlock error 9" "No error,Error"
|
|
bitfld.long 0x00 8. " MLOCK_ERROR_8 ,Mlock error 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MLOCK_ERROR_7 ,Mlock error 7" "No error,Error"
|
|
bitfld.long 0x00 6. " MLOCK_ERROR_6 ,Mlock error 6" "No error,Error"
|
|
bitfld.long 0x00 5. " MLOCK_ERROR_5 ,Mlock error 5" "No error,Error"
|
|
bitfld.long 0x00 4. " MLOCK_ERROR_4 ,Mlock error 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MLOCK_ERROR_3 ,Mlock error 3" "No error,Error"
|
|
bitfld.long 0x00 2. " MLOCK_ERROR_2 ,Mlock error 2" "No error,Error"
|
|
bitfld.long 0x00 1. " MLOCK_ERROR_1 ,Mlock error 1" "No error,Error"
|
|
bitfld.long 0x00 0. " MLOCK_ERROR_0 ,Mlock error 0" "No error,Error"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_0_0,Host1X Sync Syncpt Base 0_0"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_1_0,Host1X Sync Syncpt Base 1_0"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_2_0,Host1X Sync Syncpt Base 2_0"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_3_0,Host1X Sync Syncpt Base 3_0"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_4_0,Host1X Sync Syncpt Base 4_0"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_5_0,Host1X Sync Syncpt Base 5_0"
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_6_0,Host1X Sync Syncpt Base 6_0"
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_7_0,Host1X Sync Syncpt Base 7_0"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_8_0,Host1X Sync Syncpt Base 8_0"
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_9_0,Host1X Sync Syncpt Base 9_0"
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_10_0,Host1X Sync Syncpt Base 10_0"
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_11_0,Host1X Sync Syncpt Base 11_0"
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_12_0,Host1X Sync Syncpt Base 12_0"
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_13_0,Host1X Sync Syncpt Base 13_0"
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_14_0,Host1X Sync Syncpt Base 14_0"
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_15_0,Host1X Sync Syncpt Base 15_0"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_16_0,Host1X Sync Syncpt Base 16_0"
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_17_0,Host1X Sync Syncpt Base 17_0"
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_18_0,Host1X Sync Syncpt Base 18_0"
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_19_0,Host1X Sync Syncpt Base 19_0"
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_20_0,Host1X Sync Syncpt Base 20_0"
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_21_0,Host1X Sync Syncpt Base 21_0"
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_22_0,Host1X Sync Syncpt Base 22_0"
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_23_0,Host1X Sync Syncpt Base 23_0"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_24_0,Host1X Sync Syncpt Base 24_0"
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_25_0,Host1X Sync Syncpt Base 25_0"
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_26_0,Host1X Sync Syncpt Base 26_0"
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_27_0,Host1X Sync Syncpt Base 27_0"
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_28_0,Host1X Sync Syncpt Base 28_0"
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_29_0,Host1X Sync Syncpt Base 29_0"
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_30_0,Host1X Sync Syncpt Base 30_0"
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_31_0,Host1X Sync Syncpt Base 31_0"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_32_0,Host1X Sync Syncpt Base 32_0"
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_33_0,Host1X Sync Syncpt Base 33_0"
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_34_0,Host1X Sync Syncpt Base 34_0"
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_35_0,Host1X Sync Syncpt Base 35_0"
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_36_0,Host1X Sync Syncpt Base 36_0"
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_37_0,Host1X Sync Syncpt Base 37_0"
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_38_0,Host1X Sync Syncpt Base 38_0"
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_39_0,Host1X Sync Syncpt Base 39_0"
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_40_0,Host1X Sync Syncpt Base 40_0"
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_41_0,Host1X Sync Syncpt Base 41_0"
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_42_0,Host1X Sync Syncpt Base 42_0"
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_43_0,Host1X Sync Syncpt Base 43_0"
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_44_0,Host1X Sync Syncpt Base 44_0"
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_45_0,Host1X Sync Syncpt Base 45_0"
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_46_0,Host1X Sync Syncpt Base 46_0"
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_47_0,Host1X Sync Syncpt Base 47_0"
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_48_0,Host1X Sync Syncpt Base 48_0"
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_49_0,Host1X Sync Syncpt Base 49_0"
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_50_0,Host1X Sync Syncpt Base 50_0"
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_51_0,Host1X Sync Syncpt Base 51_0"
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_52_0,Host1X Sync Syncpt Base 52_0"
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_53_0,Host1X Sync Syncpt Base 53_0"
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_54_0,Host1X Sync Syncpt Base 54_0"
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_55_0,Host1X Sync Syncpt Base 55_0"
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_56_0,Host1X Sync Syncpt Base 56_0"
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_57_0,Host1X Sync Syncpt Base 57_0"
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_58_0,Host1X Sync Syncpt Base 58_0"
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_59_0,Host1X Sync Syncpt Base 59_0"
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_60_0,Host1X Sync Syncpt Base 60_0"
|
|
group.long 0x6F4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_61_0,Host1X Sync Syncpt Base 61_0"
|
|
group.long 0x6F8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_62_0,Host1X Sync Syncpt Base 62_0"
|
|
group.long 0x6FC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_63_0,Host1X Sync Syncpt Base 63_0"
|
|
tree.end
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0x50004000
|
|
width 27.
|
|
tree "Channel Registers"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CHANNEL_FIFOSTAT_0,Host1X Channel FIFOSTAT_0"
|
|
bitfld.long 0x00 31. " INDRDY ,Indicates that INDCOUNT == 0 so it should be OK to issue another read" "0,1"
|
|
bitfld.long 0x00 24.--28. " OUTFENTRIES ,Number of entries available for reading in this channel's output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " REGNUMEMPTY ,Register write/read FIFO free count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CFGATHER ,Indicates whether GATHER is active" "Idle,Busy"
|
|
bitfld.long 0x00 11. " CFEMPTY ,Indicates whether the command FIFO is empty" "Not empty,Empty"
|
|
hexmask.long.word 0x00 0.--10. 1. " CFNUMEMPTY ,Command FIFO free count"
|
|
if (((per.l(ad:0x50004000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type: Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long 0x00 2.--25. 0x04 " INDOFFSET ,Frame buffer address"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type:Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET ,Register offset"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
endif
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "CHANNEL_INDICT_0,Indirect Register Access Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDCOUNT ,Indcount"
|
|
line.long 0x04 "CHANNEL_IDDATA_0,Host1X Channel INDDATA_0"
|
|
line.long 0x08 "CHANNEL_RAISE_0,DMA And RAISE/REFCOUNT Functionality"
|
|
hexmask.long 0x08 2.--31. 1. " RAISE ,Channel's RAISE vector"
|
|
line.long 0x0C "CHANNEL_DMASTART_0,Host1X Channel DMSTART_0"
|
|
hexmask.long 0x0C 2.--31. 0x04 " DMASTART ,Cmdbuf frame buffer ofset"
|
|
line.long 0x10 "CHANNEL_DMAPUT_0, Host1X Channel DMAPUT_0"
|
|
hexmask.long 0x10 2.--31. 0x04 " DMAPUT ,Cmdbuf frame buffer offset"
|
|
rgroup.long 0x1C++0x0B
|
|
line.long 0x00 "CHANNEL_DMAGET_0,Host1X Channel DMAGET_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " DMAGET ,Cmdbuf frame buffer offset"
|
|
line.long 0x04 "CHANNEL_DMAEND_0 ,Host1X Channel DMAEND_0"
|
|
hexmask.long 0x04 2.--31. 0x04 " DMAEND ,Cmdbuf frame buffer offset"
|
|
line.long 0x08 "CHANNEL_DMACTRL_0,DMA Control Register"
|
|
bitfld.long 0x08 2. " DMAINITGET ,Reset GET pointer to the value of DMAPUT when DMAGETRST is asserted" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " DMAGETRST ,Reset GET pointer to 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " DMASTOP ,Stop DMA from fetching on this channel" "Run,Stop"
|
|
if (((per.l(ad:0x50004000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " INDOFFSET2 ,Frame buffer address"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID2 ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET2 ,Register offset"
|
|
endif
|
|
group.long 0x90++0x2B
|
|
line.long 0x00 "CHANNEL_TICKCOUNT_HI_0,Host1X Channel TICKCOUNT HI 0"
|
|
line.long 0x04 "CHANNEL_TICKCOUNT_LO_0,Host1X Channel TICKCOUNT LO 0"
|
|
line.long 0x08 "CHANNEL_CHANNELCTRL_0,Host1X Channel CHANNELCTRL_0"
|
|
bitfld.long 0x08 2. " KERNEL_FILTER_GBUFFER ,Enable setclass command filter for gather buffers" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ENABLETICKCNT ,Enable tick counter" "Disabled,Enabled"
|
|
line.long 0x0C "CHANNEL_PAYLOAD_0,Host1X Channel PAYLOAD_0"
|
|
line.long 0x10 "CHANNEL_STALLCTRL_0,Host1X Channel STALLCTRL_0"
|
|
bitfld.long 0x10 0. " ENABLE_CHANNEL_STALL ,Enable channel STALL" "Disabled,Enabled"
|
|
line.long 0x14 "CHANNEL_STALLCOUNT_HI_0,Host1X Channel STALLCOUNT Hi 0"
|
|
line.long 0x18 "CHANNEL_STALLCOUNT_LO_0,Host1X Channel STALLCOUNT Lo 0"
|
|
line.long 0x1C "CHANNEL_XFERCTRL_0,Host1X Channel XFERCTRL 0"
|
|
bitfld.long 0x1C 0. " ENABLE_CHANNEL_XFER ,Enable channel XFER" "Disabled,Enabled"
|
|
line.long 0x20 "CHANNEL_CHANNEL_XFER_HI_0,Host1X Channel XFER Hi 0"
|
|
line.long 0x24 "CHANNEL_CHANNEL_XFER_LO_0,Host1X Channel XFER Lo 0"
|
|
line.long 0x28 "CHANNEL_CHANNEL_SPARE_0,Host1x Channel SPARE 0"
|
|
hexmask.long.word 0x28 16.--31. 1. " CHANNEL_SPARE_HI ,Channel SPARE Hi"
|
|
hexmask.long.word 0x28 0.--15. 1. " CHANNEL_SPARE_LO ,CHannel SPARE Lo"
|
|
tree.end
|
|
; base (ad:0x50004000+0x2000) - ACTMON1(MSENC)
|
|
; base (ad:0x50004000+0x2040) - ACTMON2(VIC)
|
|
width 23.
|
|
base (ad:0x50004000+0x2100)
|
|
tree "SYNC (Synchronous Registers)"
|
|
sif CPUIS("TEGRAX1")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " VII2C_INT , VII2C interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOR1_INT ,SOR1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NVENC_INT ,NVENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " NVDEC_INT ,NVDEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 14. " NVJPG_INT ,NVJPG interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " TSECB_INT ,TSECB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " DPAUX1_INT ,DPAUX1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 4. " CPU_TZ_ILLEGAL_TZ_ACCESS_MASK ,Mask CPU_TZ_ILLEGAL_TZ_ACCESS" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 27. " VII2C_INT_C0MASK ,Interrupt mask for VII2C interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SOR1_INT_C0MASK ,Interrupt mask for SOR1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " NVENC_INT_C0MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " NVDEC_INT_C0MASK ,Interrupt mask for NVDEC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NVJPG_INT_C0MASK ,Interrupt mask for NVJPG interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " TSECB_INT_C0MASK ,Interrupt mask for TSECB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " DPAUX1_INT_C0MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 27. " VII2C_INT_C1MASK ,Interrupt mask for VII2C interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 22. " SOR1_INT_C1MASK ,Interrupt mask for SOR1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NVENC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " NVDEC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 14. " NVJPG_INT_C1MASK ,Interrupt mask for NVJPG interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " TSECB_INT_C1MASK ,Interrupt mask for TSECB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " DPAUX1_INT_C1MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " XBAR_TSEC_TIMEOUT_ID ,Id of the CPU which timed out and updated" "TSEC,XBAR"
|
|
eventfld.long 0x00 21. " WAIT_INT13 ,WAIT has completed on channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " WAIT_INT12 ,WAIT has completed on channel 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,Invalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " WAIT_INT13 ,WAIT interrupt mask 13" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " WAIT_INT12 ,WAIT interrupt mask 12" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 ACTMON interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 13. " CMDPP_ILLEGAL_OPCODE_INT13 ,CMPP 13 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 12. " CMDPP_ILLEGAL_OPCODE_INT12 ,CMPP 12 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " CMDPP_ILLEGAL_OPCODE_INTMASK13 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 12. " CMDPP_ILLEGAL_OPCODE_INTMASK12 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--13. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
wgroup.long 0xB0++0x0B
|
|
line.long 0x00 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x00 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x04 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x04 27. " VII2C_TEARDOWN ,VII2C teardown" "No action,Teardown"
|
|
bitfld.long 0x04 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x04 22. " SOR1_TEARDOWN ,SOR1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x04 19. " NVENC_TEARDOWN ,NVENC teardown" "No action,Teardown"
|
|
bitfld.long 0x04 18. " NVDEC_TEARDOWN ,NVEDC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 14. " NVJPG_TEARDOWN ,JVJPG teardown" "No action,Teardown"
|
|
bitfld.long 0x04 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " TSECB_TEARDOWN ,TSECB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DPAUX1_TEARDOWN ,DPAUX1 teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x47
|
|
line.long 0x00 "SYNC_DISPLAY_STATUS_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_STATUS_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_STATUS_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_STATUS_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_SOR1_STATUS_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,SOR1 currcl"
|
|
line.long 0x14 "SYNC_SOR_STATUS,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_STATUS_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_STATUS_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_STATUS_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_STATUS_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_NVENC_STATUS_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,NVENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_STATUS_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
line.long 0x34 "SYNC_NVDEC_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x34 16.--25. 1. " ISPB_CURRCL ,NVDEC currcl"
|
|
line.long 0x38 "SYNC_NVJPG_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x38 16.--25. 1. " ISPB_CURRCL ,NVJPG currcl"
|
|
line.long 0x3C "SYNC_VII2C_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x3C 16.--25. 1. " ISPB_CURRCL ,VII2C currcl"
|
|
line.long 0x40 "SYNC_DPAUX1_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x40 16.--25. 1. " ISPB_CURRCL ,DPAUX1 currcl"
|
|
line.long 0x44 "SYNC_TSECB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x44 16.--25. 1. " ISPB_CURRCL ,TSECB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 13. " HIPRI_CH13 ,HIPRI ch 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " HIPRI_CH12 ,HIPRI ch 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " MSENC_INT ,MSENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " HDMI_INT ,HDMi int " "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " MSENC_INT_C0MASK ,Interrupt mask for MSENC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " HDMI_INT_C0MASK ,Interrupt mask for HDMI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 19. " MSENC_INT_C1MASK ,Interrupt mask for MSENC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HDMI_INT_C1MASK ,Interrupt mask for HDMI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,INvalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " XBAR_TSEC_TIMEOUT_ID ,ID of the CPU which timed out and updated the timeout address" "Tsec,Xbar"
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 actmon interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 actmon interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--11. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
line.long 0x04 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x04 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x08 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x08 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
bitfld.long 0x08 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x08 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x08 19. " MSENC_TEARDOWN ,MSENC teardown" "No action,Teardown"
|
|
bitfld.long 0x08 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 10. " HDMI_TEARDOWN ,HDMI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x33
|
|
line.long 0x00 "SYNC_DISPLAY_Status_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_Status_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_Status_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_Status_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_HDMI_Status_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,HDMI currcl"
|
|
line.long 0x14 "SYNC_SOR_Status,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_Status_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_Status_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_Status_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_Status_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_MSENC_Status_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,MSENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_Status_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_Status_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
endif
|
|
width 23.
|
|
tree "MLOCK registers"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_0_0,Host1X Sync MLOCK_0_0"
|
|
bitfld.long 0x00 0. " MLOCK_0 ,Mlock_0" "Released,Held"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_1_0,Host1X Sync MLOCK_1_0"
|
|
bitfld.long 0x00 0. " MLOCK_1 ,Mlock_1" "Released,Held"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_2_0,Host1X Sync MLOCK_2_0"
|
|
bitfld.long 0x00 0. " MLOCK_2 ,Mlock_2" "Released,Held"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_3_0,Host1X Sync MLOCK_3_0"
|
|
bitfld.long 0x00 0. " MLOCK_3 ,Mlock_3" "Released,Held"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_4_0,Host1X Sync MLOCK_4_0"
|
|
bitfld.long 0x00 0. " MLOCK_4 ,Mlock_4" "Released,Held"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_5_0,Host1X Sync MLOCK_5_0"
|
|
bitfld.long 0x00 0. " MLOCK_5 ,Mlock_5" "Released,Held"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_6_0,Host1X Sync MLOCK_6_0"
|
|
bitfld.long 0x00 0. " MLOCK_6 ,Mlock_6" "Released,Held"
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_7_0,Host1X Sync MLOCK_7_0"
|
|
bitfld.long 0x00 0. " MLOCK_7 ,Mlock_7" "Released,Held"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_8_0,Host1X Sync MLOCK_8_0"
|
|
bitfld.long 0x00 0. " MLOCK_8 ,Mlock_8" "Released,Held"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_9_0,Host1X Sync MLOCK_9_0"
|
|
bitfld.long 0x00 0. " MLOCK_9 ,Mlock_9" "Released,Held"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_10_0,Host1X Sync MLOCK_10_0"
|
|
bitfld.long 0x00 0. " MLOCK_10 ,Mlock_10" "Released,Held"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_11_0,Host1X Sync MLOCK_11_0"
|
|
bitfld.long 0x00 0. " MLOCK_11 ,Mlock_11" "Released,Held"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_12_0,Host1X Sync MLOCK_12_0"
|
|
bitfld.long 0x00 0. " MLOCK_12 ,Mlock_12" "Released,Held"
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_13_0,Host1X Sync MLOCK_13_0"
|
|
bitfld.long 0x00 0. " MLOCK_13 ,Mlock_13" "Released,Held"
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_14_0,Host1X Sync MLOCK_14_0"
|
|
bitfld.long 0x00 0. " MLOCK_14 ,Mlock_14" "Released,Held"
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_15_0,Host1X Sync MLOCK_15_0"
|
|
bitfld.long 0x00 0. " MLOCK_15 ,Mlock_15" "Released,Held"
|
|
textline " "
|
|
rgroup.long 0x340++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_0_0,Host1X Sync MLOCK Owner 0_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_0 ,Mlock owner chid 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_0 ,MLOCK CPU owns 0" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_0 ,MLOCK CH owns 0" "Not owned,Owned"
|
|
rgroup.long 0x344++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_1_0,Host1X Sync MLOCK Owner 1_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_1 ,Mlock owner chid 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_1 ,MLOCK CPU owns 1" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_1 ,MLOCK CH owns 1" "Not owned,Owned"
|
|
rgroup.long 0x348++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_2_0,Host1X Sync MLOCK Owner 2_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_2 ,Mlock owner chid 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_2 ,MLOCK CPU owns 2" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_2 ,MLOCK CH owns 2" "Not owned,Owned"
|
|
rgroup.long 0x34C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_3_0,Host1X Sync MLOCK Owner 3_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_3 ,Mlock owner chid 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_3 ,MLOCK CPU owns 3" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_3 ,MLOCK CH owns 3" "Not owned,Owned"
|
|
rgroup.long 0x350++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_4_0,Host1X Sync MLOCK Owner 4_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_4 ,Mlock owner chid 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_4 ,MLOCK CPU owns 4" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_4 ,MLOCK CH owns 4" "Not owned,Owned"
|
|
rgroup.long 0x354++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_5_0,Host1X Sync MLOCK Owner 5_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_5 ,Mlock owner chid 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_5 ,MLOCK CPU owns 5" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_5 ,MLOCK CH owns 5" "Not owned,Owned"
|
|
rgroup.long 0x358++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_6_0,Host1X Sync MLOCK Owner 6_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_6 ,Mlock owner chid 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_6 ,MLOCK CPU owns 6" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_6 ,MLOCK CH owns 6" "Not owned,Owned"
|
|
rgroup.long 0x35C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_7_0,Host1X Sync MLOCK Owner 7_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_7 ,Mlock owner chid 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_7 ,MLOCK CPU owns 7" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_7 ,MLOCK CH owns 7" "Not owned,Owned"
|
|
rgroup.long 0x360++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_8_0,Host1X Sync MLOCK Owner 8_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_8 ,Mlock owner chid 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_8 ,MLOCK CPU owns 8" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_8 ,MLOCK CH owns 8" "Not owned,Owned"
|
|
rgroup.long 0x364++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_9_0,Host1X Sync MLOCK Owner 9_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_9 ,Mlock owner chid 9" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_9 ,MLOCK CPU owns 9" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_9 ,MLOCK CH owns 9" "Not owned,Owned"
|
|
rgroup.long 0x368++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_10_0,Host1X Sync MLOCK Owner 10_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_10 ,Mlock owner chid 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_10 ,MLOCK CPU owns 10" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_10 ,MLOCK CH owns 10" "Not owned,Owned"
|
|
rgroup.long 0x36C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_11_0,Host1X Sync MLOCK Owner 11_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_11 ,Mlock owner chid 11" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_11 ,MLOCK CPU owns 11" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_11 ,MLOCK CH owns 11" "Not owned,Owned"
|
|
rgroup.long 0x370++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_12_0,Host1X Sync MLOCK Owner 12_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_12 ,Mlock owner chid 12" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_12 ,MLOCK CPU owns 12" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_12 ,MLOCK CH owns 12" "Not owned,Owned"
|
|
rgroup.long 0x374++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_13_0,Host1X Sync MLOCK Owner 13_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_13 ,Mlock owner chid 13" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_13 ,MLOCK CPU owns 13" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_13 ,MLOCK CH owns 13" "Not owned,Owned"
|
|
rgroup.long 0x378++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_14_0,Host1X Sync MLOCK Owner 14_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_14 ,Mlock owner chid 14" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_14 ,MLOCK CPU owns 14" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_14 ,MLOCK CH owns 14" "Not owned,Owned"
|
|
rgroup.long 0x37C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_15_0,Host1X Sync MLOCK Owner 15_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_15 ,Mlock owner chid 15" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_15 ,MLOCK CPU owns 15" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_15 ,MLOCK CH owns 15" "Not owned,Owned"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_ERROR_0_0,Host1X Sync Mlock Error 0_0"
|
|
bitfld.long 0x00 15. " MLOCK_ERROR_15 ,Mlock error 15" "No error,Error"
|
|
bitfld.long 0x00 14. " MLOCK_ERROR_14 ,Mlock error 14" "No error,Error"
|
|
bitfld.long 0x00 13. " MLOCK_ERROR_13 ,Mlock error 13" "No error,Error"
|
|
bitfld.long 0x00 12. " MLOCK_ERROR_12 ,Mlock error 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MLOCK_ERROR_11 ,Mlock error 11" "No error,Error"
|
|
bitfld.long 0x00 10. " MLOCK_ERROR_10 ,Mlock error 10" "No error,Error"
|
|
bitfld.long 0x00 9. " MLOCK_ERROR_9 ,Mlock error 9" "No error,Error"
|
|
bitfld.long 0x00 8. " MLOCK_ERROR_8 ,Mlock error 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MLOCK_ERROR_7 ,Mlock error 7" "No error,Error"
|
|
bitfld.long 0x00 6. " MLOCK_ERROR_6 ,Mlock error 6" "No error,Error"
|
|
bitfld.long 0x00 5. " MLOCK_ERROR_5 ,Mlock error 5" "No error,Error"
|
|
bitfld.long 0x00 4. " MLOCK_ERROR_4 ,Mlock error 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MLOCK_ERROR_3 ,Mlock error 3" "No error,Error"
|
|
bitfld.long 0x00 2. " MLOCK_ERROR_2 ,Mlock error 2" "No error,Error"
|
|
bitfld.long 0x00 1. " MLOCK_ERROR_1 ,Mlock error 1" "No error,Error"
|
|
bitfld.long 0x00 0. " MLOCK_ERROR_0 ,Mlock error 0" "No error,Error"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_0_0,Host1X Sync Syncpt Base 0_0"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_1_0,Host1X Sync Syncpt Base 1_0"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_2_0,Host1X Sync Syncpt Base 2_0"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_3_0,Host1X Sync Syncpt Base 3_0"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_4_0,Host1X Sync Syncpt Base 4_0"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_5_0,Host1X Sync Syncpt Base 5_0"
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_6_0,Host1X Sync Syncpt Base 6_0"
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_7_0,Host1X Sync Syncpt Base 7_0"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_8_0,Host1X Sync Syncpt Base 8_0"
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_9_0,Host1X Sync Syncpt Base 9_0"
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_10_0,Host1X Sync Syncpt Base 10_0"
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_11_0,Host1X Sync Syncpt Base 11_0"
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_12_0,Host1X Sync Syncpt Base 12_0"
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_13_0,Host1X Sync Syncpt Base 13_0"
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_14_0,Host1X Sync Syncpt Base 14_0"
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_15_0,Host1X Sync Syncpt Base 15_0"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_16_0,Host1X Sync Syncpt Base 16_0"
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_17_0,Host1X Sync Syncpt Base 17_0"
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_18_0,Host1X Sync Syncpt Base 18_0"
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_19_0,Host1X Sync Syncpt Base 19_0"
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_20_0,Host1X Sync Syncpt Base 20_0"
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_21_0,Host1X Sync Syncpt Base 21_0"
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_22_0,Host1X Sync Syncpt Base 22_0"
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_23_0,Host1X Sync Syncpt Base 23_0"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_24_0,Host1X Sync Syncpt Base 24_0"
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_25_0,Host1X Sync Syncpt Base 25_0"
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_26_0,Host1X Sync Syncpt Base 26_0"
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_27_0,Host1X Sync Syncpt Base 27_0"
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_28_0,Host1X Sync Syncpt Base 28_0"
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_29_0,Host1X Sync Syncpt Base 29_0"
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_30_0,Host1X Sync Syncpt Base 30_0"
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_31_0,Host1X Sync Syncpt Base 31_0"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_32_0,Host1X Sync Syncpt Base 32_0"
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_33_0,Host1X Sync Syncpt Base 33_0"
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_34_0,Host1X Sync Syncpt Base 34_0"
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_35_0,Host1X Sync Syncpt Base 35_0"
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_36_0,Host1X Sync Syncpt Base 36_0"
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_37_0,Host1X Sync Syncpt Base 37_0"
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_38_0,Host1X Sync Syncpt Base 38_0"
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_39_0,Host1X Sync Syncpt Base 39_0"
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_40_0,Host1X Sync Syncpt Base 40_0"
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_41_0,Host1X Sync Syncpt Base 41_0"
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_42_0,Host1X Sync Syncpt Base 42_0"
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_43_0,Host1X Sync Syncpt Base 43_0"
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_44_0,Host1X Sync Syncpt Base 44_0"
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_45_0,Host1X Sync Syncpt Base 45_0"
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_46_0,Host1X Sync Syncpt Base 46_0"
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_47_0,Host1X Sync Syncpt Base 47_0"
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_48_0,Host1X Sync Syncpt Base 48_0"
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_49_0,Host1X Sync Syncpt Base 49_0"
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_50_0,Host1X Sync Syncpt Base 50_0"
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_51_0,Host1X Sync Syncpt Base 51_0"
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_52_0,Host1X Sync Syncpt Base 52_0"
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_53_0,Host1X Sync Syncpt Base 53_0"
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_54_0,Host1X Sync Syncpt Base 54_0"
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_55_0,Host1X Sync Syncpt Base 55_0"
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_56_0,Host1X Sync Syncpt Base 56_0"
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_57_0,Host1X Sync Syncpt Base 57_0"
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_58_0,Host1X Sync Syncpt Base 58_0"
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_59_0,Host1X Sync Syncpt Base 59_0"
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_60_0,Host1X Sync Syncpt Base 60_0"
|
|
group.long 0x6F4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_61_0,Host1X Sync Syncpt Base 61_0"
|
|
group.long 0x6F8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_62_0,Host1X Sync Syncpt Base 62_0"
|
|
group.long 0x6FC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_63_0,Host1X Sync Syncpt Base 63_0"
|
|
tree.end
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0x50008000
|
|
width 27.
|
|
tree "Channel Registers"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CHANNEL_FIFOSTAT_0,Host1X Channel FIFOSTAT_0"
|
|
bitfld.long 0x00 31. " INDRDY ,Indicates that INDCOUNT == 0 so it should be OK to issue another read" "0,1"
|
|
bitfld.long 0x00 24.--28. " OUTFENTRIES ,Number of entries available for reading in this channel's output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " REGNUMEMPTY ,Register write/read FIFO free count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CFGATHER ,Indicates whether GATHER is active" "Idle,Busy"
|
|
bitfld.long 0x00 11. " CFEMPTY ,Indicates whether the command FIFO is empty" "Not empty,Empty"
|
|
hexmask.long.word 0x00 0.--10. 1. " CFNUMEMPTY ,Command FIFO free count"
|
|
if (((per.l(ad:0x50008000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type: Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long 0x00 2.--25. 0x04 " INDOFFSET ,Frame buffer address"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type:Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET ,Register offset"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
endif
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "CHANNEL_INDICT_0,Indirect Register Access Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDCOUNT ,Indcount"
|
|
line.long 0x04 "CHANNEL_IDDATA_0,Host1X Channel INDDATA_0"
|
|
line.long 0x08 "CHANNEL_RAISE_0,DMA And RAISE/REFCOUNT Functionality"
|
|
hexmask.long 0x08 2.--31. 1. " RAISE ,Channel's RAISE vector"
|
|
line.long 0x0C "CHANNEL_DMASTART_0,Host1X Channel DMSTART_0"
|
|
hexmask.long 0x0C 2.--31. 0x04 " DMASTART ,Cmdbuf frame buffer ofset"
|
|
line.long 0x10 "CHANNEL_DMAPUT_0, Host1X Channel DMAPUT_0"
|
|
hexmask.long 0x10 2.--31. 0x04 " DMAPUT ,Cmdbuf frame buffer offset"
|
|
rgroup.long 0x1C++0x0B
|
|
line.long 0x00 "CHANNEL_DMAGET_0,Host1X Channel DMAGET_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " DMAGET ,Cmdbuf frame buffer offset"
|
|
line.long 0x04 "CHANNEL_DMAEND_0 ,Host1X Channel DMAEND_0"
|
|
hexmask.long 0x04 2.--31. 0x04 " DMAEND ,Cmdbuf frame buffer offset"
|
|
line.long 0x08 "CHANNEL_DMACTRL_0,DMA Control Register"
|
|
bitfld.long 0x08 2. " DMAINITGET ,Reset GET pointer to the value of DMAPUT when DMAGETRST is asserted" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " DMAGETRST ,Reset GET pointer to 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " DMASTOP ,Stop DMA from fetching on this channel" "Run,Stop"
|
|
if (((per.l(ad:0x50008000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " INDOFFSET2 ,Frame buffer address"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID2 ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET2 ,Register offset"
|
|
endif
|
|
group.long 0x90++0x2B
|
|
line.long 0x00 "CHANNEL_TICKCOUNT_HI_0,Host1X Channel TICKCOUNT HI 0"
|
|
line.long 0x04 "CHANNEL_TICKCOUNT_LO_0,Host1X Channel TICKCOUNT LO 0"
|
|
line.long 0x08 "CHANNEL_CHANNELCTRL_0,Host1X Channel CHANNELCTRL_0"
|
|
bitfld.long 0x08 2. " KERNEL_FILTER_GBUFFER ,Enable setclass command filter for gather buffers" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ENABLETICKCNT ,Enable tick counter" "Disabled,Enabled"
|
|
line.long 0x0C "CHANNEL_PAYLOAD_0,Host1X Channel PAYLOAD_0"
|
|
line.long 0x10 "CHANNEL_STALLCTRL_0,Host1X Channel STALLCTRL_0"
|
|
bitfld.long 0x10 0. " ENABLE_CHANNEL_STALL ,Enable channel STALL" "Disabled,Enabled"
|
|
line.long 0x14 "CHANNEL_STALLCOUNT_HI_0,Host1X Channel STALLCOUNT Hi 0"
|
|
line.long 0x18 "CHANNEL_STALLCOUNT_LO_0,Host1X Channel STALLCOUNT Lo 0"
|
|
line.long 0x1C "CHANNEL_XFERCTRL_0,Host1X Channel XFERCTRL 0"
|
|
bitfld.long 0x1C 0. " ENABLE_CHANNEL_XFER ,Enable channel XFER" "Disabled,Enabled"
|
|
line.long 0x20 "CHANNEL_CHANNEL_XFER_HI_0,Host1X Channel XFER Hi 0"
|
|
line.long 0x24 "CHANNEL_CHANNEL_XFER_LO_0,Host1X Channel XFER Lo 0"
|
|
line.long 0x28 "CHANNEL_CHANNEL_SPARE_0,Host1x Channel SPARE 0"
|
|
hexmask.long.word 0x28 16.--31. 1. " CHANNEL_SPARE_HI ,Channel SPARE Hi"
|
|
hexmask.long.word 0x28 0.--15. 1. " CHANNEL_SPARE_LO ,CHannel SPARE Lo"
|
|
tree.end
|
|
; base (ad:0x50008000+0x2000) - ACTMON1(MSENC)
|
|
; base (ad:0x50008000+0x2040) - ACTMON2(VIC)
|
|
width 23.
|
|
base (ad:0x50008000+0x2100)
|
|
tree "SYNC (Synchronous Registers)"
|
|
sif CPUIS("TEGRAX1")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " VII2C_INT , VII2C interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOR1_INT ,SOR1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NVENC_INT ,NVENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " NVDEC_INT ,NVDEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 14. " NVJPG_INT ,NVJPG interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " TSECB_INT ,TSECB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " DPAUX1_INT ,DPAUX1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 4. " CPU_TZ_ILLEGAL_TZ_ACCESS_MASK ,Mask CPU_TZ_ILLEGAL_TZ_ACCESS" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 27. " VII2C_INT_C0MASK ,Interrupt mask for VII2C interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SOR1_INT_C0MASK ,Interrupt mask for SOR1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " NVENC_INT_C0MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " NVDEC_INT_C0MASK ,Interrupt mask for NVDEC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NVJPG_INT_C0MASK ,Interrupt mask for NVJPG interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " TSECB_INT_C0MASK ,Interrupt mask for TSECB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " DPAUX1_INT_C0MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 27. " VII2C_INT_C1MASK ,Interrupt mask for VII2C interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 22. " SOR1_INT_C1MASK ,Interrupt mask for SOR1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NVENC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " NVDEC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 14. " NVJPG_INT_C1MASK ,Interrupt mask for NVJPG interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " TSECB_INT_C1MASK ,Interrupt mask for TSECB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " DPAUX1_INT_C1MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " XBAR_TSEC_TIMEOUT_ID ,Id of the CPU which timed out and updated" "TSEC,XBAR"
|
|
eventfld.long 0x00 21. " WAIT_INT13 ,WAIT has completed on channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " WAIT_INT12 ,WAIT has completed on channel 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,Invalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " WAIT_INT13 ,WAIT interrupt mask 13" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " WAIT_INT12 ,WAIT interrupt mask 12" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 ACTMON interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 13. " CMDPP_ILLEGAL_OPCODE_INT13 ,CMPP 13 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 12. " CMDPP_ILLEGAL_OPCODE_INT12 ,CMPP 12 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " CMDPP_ILLEGAL_OPCODE_INTMASK13 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 12. " CMDPP_ILLEGAL_OPCODE_INTMASK12 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--13. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
wgroup.long 0xB0++0x0B
|
|
line.long 0x00 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x00 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x04 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x04 27. " VII2C_TEARDOWN ,VII2C teardown" "No action,Teardown"
|
|
bitfld.long 0x04 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x04 22. " SOR1_TEARDOWN ,SOR1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x04 19. " NVENC_TEARDOWN ,NVENC teardown" "No action,Teardown"
|
|
bitfld.long 0x04 18. " NVDEC_TEARDOWN ,NVEDC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 14. " NVJPG_TEARDOWN ,JVJPG teardown" "No action,Teardown"
|
|
bitfld.long 0x04 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " TSECB_TEARDOWN ,TSECB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DPAUX1_TEARDOWN ,DPAUX1 teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x47
|
|
line.long 0x00 "SYNC_DISPLAY_STATUS_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_STATUS_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_STATUS_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_STATUS_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_SOR1_STATUS_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,SOR1 currcl"
|
|
line.long 0x14 "SYNC_SOR_STATUS,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_STATUS_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_STATUS_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_STATUS_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_STATUS_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_NVENC_STATUS_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,NVENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_STATUS_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
line.long 0x34 "SYNC_NVDEC_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x34 16.--25. 1. " ISPB_CURRCL ,NVDEC currcl"
|
|
line.long 0x38 "SYNC_NVJPG_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x38 16.--25. 1. " ISPB_CURRCL ,NVJPG currcl"
|
|
line.long 0x3C "SYNC_VII2C_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x3C 16.--25. 1. " ISPB_CURRCL ,VII2C currcl"
|
|
line.long 0x40 "SYNC_DPAUX1_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x40 16.--25. 1. " ISPB_CURRCL ,DPAUX1 currcl"
|
|
line.long 0x44 "SYNC_TSECB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x44 16.--25. 1. " ISPB_CURRCL ,TSECB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 13. " HIPRI_CH13 ,HIPRI ch 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " HIPRI_CH12 ,HIPRI ch 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " MSENC_INT ,MSENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " HDMI_INT ,HDMi int " "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " MSENC_INT_C0MASK ,Interrupt mask for MSENC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " HDMI_INT_C0MASK ,Interrupt mask for HDMI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 19. " MSENC_INT_C1MASK ,Interrupt mask for MSENC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HDMI_INT_C1MASK ,Interrupt mask for HDMI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,INvalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " XBAR_TSEC_TIMEOUT_ID ,ID of the CPU which timed out and updated the timeout address" "Tsec,Xbar"
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 actmon interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 actmon interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--11. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
line.long 0x04 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x04 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x08 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x08 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
bitfld.long 0x08 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x08 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x08 19. " MSENC_TEARDOWN ,MSENC teardown" "No action,Teardown"
|
|
bitfld.long 0x08 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 10. " HDMI_TEARDOWN ,HDMI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x33
|
|
line.long 0x00 "SYNC_DISPLAY_Status_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_Status_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_Status_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_Status_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_HDMI_Status_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,HDMI currcl"
|
|
line.long 0x14 "SYNC_SOR_Status,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_Status_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_Status_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_Status_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_Status_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_MSENC_Status_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,MSENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_Status_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_Status_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
endif
|
|
width 23.
|
|
tree "MLOCK registers"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_0_0,Host1X Sync MLOCK_0_0"
|
|
bitfld.long 0x00 0. " MLOCK_0 ,Mlock_0" "Released,Held"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_1_0,Host1X Sync MLOCK_1_0"
|
|
bitfld.long 0x00 0. " MLOCK_1 ,Mlock_1" "Released,Held"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_2_0,Host1X Sync MLOCK_2_0"
|
|
bitfld.long 0x00 0. " MLOCK_2 ,Mlock_2" "Released,Held"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_3_0,Host1X Sync MLOCK_3_0"
|
|
bitfld.long 0x00 0. " MLOCK_3 ,Mlock_3" "Released,Held"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_4_0,Host1X Sync MLOCK_4_0"
|
|
bitfld.long 0x00 0. " MLOCK_4 ,Mlock_4" "Released,Held"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_5_0,Host1X Sync MLOCK_5_0"
|
|
bitfld.long 0x00 0. " MLOCK_5 ,Mlock_5" "Released,Held"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_6_0,Host1X Sync MLOCK_6_0"
|
|
bitfld.long 0x00 0. " MLOCK_6 ,Mlock_6" "Released,Held"
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_7_0,Host1X Sync MLOCK_7_0"
|
|
bitfld.long 0x00 0. " MLOCK_7 ,Mlock_7" "Released,Held"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_8_0,Host1X Sync MLOCK_8_0"
|
|
bitfld.long 0x00 0. " MLOCK_8 ,Mlock_8" "Released,Held"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_9_0,Host1X Sync MLOCK_9_0"
|
|
bitfld.long 0x00 0. " MLOCK_9 ,Mlock_9" "Released,Held"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_10_0,Host1X Sync MLOCK_10_0"
|
|
bitfld.long 0x00 0. " MLOCK_10 ,Mlock_10" "Released,Held"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_11_0,Host1X Sync MLOCK_11_0"
|
|
bitfld.long 0x00 0. " MLOCK_11 ,Mlock_11" "Released,Held"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_12_0,Host1X Sync MLOCK_12_0"
|
|
bitfld.long 0x00 0. " MLOCK_12 ,Mlock_12" "Released,Held"
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_13_0,Host1X Sync MLOCK_13_0"
|
|
bitfld.long 0x00 0. " MLOCK_13 ,Mlock_13" "Released,Held"
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_14_0,Host1X Sync MLOCK_14_0"
|
|
bitfld.long 0x00 0. " MLOCK_14 ,Mlock_14" "Released,Held"
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_15_0,Host1X Sync MLOCK_15_0"
|
|
bitfld.long 0x00 0. " MLOCK_15 ,Mlock_15" "Released,Held"
|
|
textline " "
|
|
rgroup.long 0x340++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_0_0,Host1X Sync MLOCK Owner 0_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_0 ,Mlock owner chid 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_0 ,MLOCK CPU owns 0" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_0 ,MLOCK CH owns 0" "Not owned,Owned"
|
|
rgroup.long 0x344++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_1_0,Host1X Sync MLOCK Owner 1_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_1 ,Mlock owner chid 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_1 ,MLOCK CPU owns 1" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_1 ,MLOCK CH owns 1" "Not owned,Owned"
|
|
rgroup.long 0x348++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_2_0,Host1X Sync MLOCK Owner 2_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_2 ,Mlock owner chid 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_2 ,MLOCK CPU owns 2" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_2 ,MLOCK CH owns 2" "Not owned,Owned"
|
|
rgroup.long 0x34C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_3_0,Host1X Sync MLOCK Owner 3_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_3 ,Mlock owner chid 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_3 ,MLOCK CPU owns 3" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_3 ,MLOCK CH owns 3" "Not owned,Owned"
|
|
rgroup.long 0x350++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_4_0,Host1X Sync MLOCK Owner 4_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_4 ,Mlock owner chid 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_4 ,MLOCK CPU owns 4" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_4 ,MLOCK CH owns 4" "Not owned,Owned"
|
|
rgroup.long 0x354++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_5_0,Host1X Sync MLOCK Owner 5_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_5 ,Mlock owner chid 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_5 ,MLOCK CPU owns 5" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_5 ,MLOCK CH owns 5" "Not owned,Owned"
|
|
rgroup.long 0x358++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_6_0,Host1X Sync MLOCK Owner 6_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_6 ,Mlock owner chid 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_6 ,MLOCK CPU owns 6" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_6 ,MLOCK CH owns 6" "Not owned,Owned"
|
|
rgroup.long 0x35C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_7_0,Host1X Sync MLOCK Owner 7_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_7 ,Mlock owner chid 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_7 ,MLOCK CPU owns 7" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_7 ,MLOCK CH owns 7" "Not owned,Owned"
|
|
rgroup.long 0x360++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_8_0,Host1X Sync MLOCK Owner 8_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_8 ,Mlock owner chid 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_8 ,MLOCK CPU owns 8" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_8 ,MLOCK CH owns 8" "Not owned,Owned"
|
|
rgroup.long 0x364++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_9_0,Host1X Sync MLOCK Owner 9_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_9 ,Mlock owner chid 9" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_9 ,MLOCK CPU owns 9" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_9 ,MLOCK CH owns 9" "Not owned,Owned"
|
|
rgroup.long 0x368++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_10_0,Host1X Sync MLOCK Owner 10_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_10 ,Mlock owner chid 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_10 ,MLOCK CPU owns 10" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_10 ,MLOCK CH owns 10" "Not owned,Owned"
|
|
rgroup.long 0x36C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_11_0,Host1X Sync MLOCK Owner 11_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_11 ,Mlock owner chid 11" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_11 ,MLOCK CPU owns 11" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_11 ,MLOCK CH owns 11" "Not owned,Owned"
|
|
rgroup.long 0x370++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_12_0,Host1X Sync MLOCK Owner 12_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_12 ,Mlock owner chid 12" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_12 ,MLOCK CPU owns 12" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_12 ,MLOCK CH owns 12" "Not owned,Owned"
|
|
rgroup.long 0x374++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_13_0,Host1X Sync MLOCK Owner 13_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_13 ,Mlock owner chid 13" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_13 ,MLOCK CPU owns 13" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_13 ,MLOCK CH owns 13" "Not owned,Owned"
|
|
rgroup.long 0x378++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_14_0,Host1X Sync MLOCK Owner 14_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_14 ,Mlock owner chid 14" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_14 ,MLOCK CPU owns 14" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_14 ,MLOCK CH owns 14" "Not owned,Owned"
|
|
rgroup.long 0x37C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_15_0,Host1X Sync MLOCK Owner 15_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_15 ,Mlock owner chid 15" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_15 ,MLOCK CPU owns 15" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_15 ,MLOCK CH owns 15" "Not owned,Owned"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_ERROR_0_0,Host1X Sync Mlock Error 0_0"
|
|
bitfld.long 0x00 15. " MLOCK_ERROR_15 ,Mlock error 15" "No error,Error"
|
|
bitfld.long 0x00 14. " MLOCK_ERROR_14 ,Mlock error 14" "No error,Error"
|
|
bitfld.long 0x00 13. " MLOCK_ERROR_13 ,Mlock error 13" "No error,Error"
|
|
bitfld.long 0x00 12. " MLOCK_ERROR_12 ,Mlock error 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MLOCK_ERROR_11 ,Mlock error 11" "No error,Error"
|
|
bitfld.long 0x00 10. " MLOCK_ERROR_10 ,Mlock error 10" "No error,Error"
|
|
bitfld.long 0x00 9. " MLOCK_ERROR_9 ,Mlock error 9" "No error,Error"
|
|
bitfld.long 0x00 8. " MLOCK_ERROR_8 ,Mlock error 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MLOCK_ERROR_7 ,Mlock error 7" "No error,Error"
|
|
bitfld.long 0x00 6. " MLOCK_ERROR_6 ,Mlock error 6" "No error,Error"
|
|
bitfld.long 0x00 5. " MLOCK_ERROR_5 ,Mlock error 5" "No error,Error"
|
|
bitfld.long 0x00 4. " MLOCK_ERROR_4 ,Mlock error 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MLOCK_ERROR_3 ,Mlock error 3" "No error,Error"
|
|
bitfld.long 0x00 2. " MLOCK_ERROR_2 ,Mlock error 2" "No error,Error"
|
|
bitfld.long 0x00 1. " MLOCK_ERROR_1 ,Mlock error 1" "No error,Error"
|
|
bitfld.long 0x00 0. " MLOCK_ERROR_0 ,Mlock error 0" "No error,Error"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_0_0,Host1X Sync Syncpt Base 0_0"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_1_0,Host1X Sync Syncpt Base 1_0"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_2_0,Host1X Sync Syncpt Base 2_0"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_3_0,Host1X Sync Syncpt Base 3_0"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_4_0,Host1X Sync Syncpt Base 4_0"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_5_0,Host1X Sync Syncpt Base 5_0"
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_6_0,Host1X Sync Syncpt Base 6_0"
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_7_0,Host1X Sync Syncpt Base 7_0"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_8_0,Host1X Sync Syncpt Base 8_0"
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_9_0,Host1X Sync Syncpt Base 9_0"
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_10_0,Host1X Sync Syncpt Base 10_0"
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_11_0,Host1X Sync Syncpt Base 11_0"
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_12_0,Host1X Sync Syncpt Base 12_0"
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_13_0,Host1X Sync Syncpt Base 13_0"
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_14_0,Host1X Sync Syncpt Base 14_0"
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_15_0,Host1X Sync Syncpt Base 15_0"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_16_0,Host1X Sync Syncpt Base 16_0"
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_17_0,Host1X Sync Syncpt Base 17_0"
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_18_0,Host1X Sync Syncpt Base 18_0"
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_19_0,Host1X Sync Syncpt Base 19_0"
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_20_0,Host1X Sync Syncpt Base 20_0"
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_21_0,Host1X Sync Syncpt Base 21_0"
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_22_0,Host1X Sync Syncpt Base 22_0"
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_23_0,Host1X Sync Syncpt Base 23_0"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_24_0,Host1X Sync Syncpt Base 24_0"
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_25_0,Host1X Sync Syncpt Base 25_0"
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_26_0,Host1X Sync Syncpt Base 26_0"
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_27_0,Host1X Sync Syncpt Base 27_0"
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_28_0,Host1X Sync Syncpt Base 28_0"
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_29_0,Host1X Sync Syncpt Base 29_0"
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_30_0,Host1X Sync Syncpt Base 30_0"
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_31_0,Host1X Sync Syncpt Base 31_0"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_32_0,Host1X Sync Syncpt Base 32_0"
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_33_0,Host1X Sync Syncpt Base 33_0"
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_34_0,Host1X Sync Syncpt Base 34_0"
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_35_0,Host1X Sync Syncpt Base 35_0"
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_36_0,Host1X Sync Syncpt Base 36_0"
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_37_0,Host1X Sync Syncpt Base 37_0"
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_38_0,Host1X Sync Syncpt Base 38_0"
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_39_0,Host1X Sync Syncpt Base 39_0"
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_40_0,Host1X Sync Syncpt Base 40_0"
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_41_0,Host1X Sync Syncpt Base 41_0"
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_42_0,Host1X Sync Syncpt Base 42_0"
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_43_0,Host1X Sync Syncpt Base 43_0"
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_44_0,Host1X Sync Syncpt Base 44_0"
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_45_0,Host1X Sync Syncpt Base 45_0"
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_46_0,Host1X Sync Syncpt Base 46_0"
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_47_0,Host1X Sync Syncpt Base 47_0"
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_48_0,Host1X Sync Syncpt Base 48_0"
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_49_0,Host1X Sync Syncpt Base 49_0"
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_50_0,Host1X Sync Syncpt Base 50_0"
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_51_0,Host1X Sync Syncpt Base 51_0"
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_52_0,Host1X Sync Syncpt Base 52_0"
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_53_0,Host1X Sync Syncpt Base 53_0"
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_54_0,Host1X Sync Syncpt Base 54_0"
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_55_0,Host1X Sync Syncpt Base 55_0"
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_56_0,Host1X Sync Syncpt Base 56_0"
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_57_0,Host1X Sync Syncpt Base 57_0"
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_58_0,Host1X Sync Syncpt Base 58_0"
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_59_0,Host1X Sync Syncpt Base 59_0"
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_60_0,Host1X Sync Syncpt Base 60_0"
|
|
group.long 0x6F4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_61_0,Host1X Sync Syncpt Base 61_0"
|
|
group.long 0x6F8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_62_0,Host1X Sync Syncpt Base 62_0"
|
|
group.long 0x6FC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_63_0,Host1X Sync Syncpt Base 63_0"
|
|
tree.end
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 3"
|
|
base ad:0x5000E000
|
|
width 27.
|
|
tree "Channel Registers"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CHANNEL_FIFOSTAT_0,Host1X Channel FIFOSTAT_0"
|
|
bitfld.long 0x00 31. " INDRDY ,Indicates that INDCOUNT == 0 so it should be OK to issue another read" "0,1"
|
|
bitfld.long 0x00 24.--28. " OUTFENTRIES ,Number of entries available for reading in this channel's output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " REGNUMEMPTY ,Register write/read FIFO free count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CFGATHER ,Indicates whether GATHER is active" "Idle,Busy"
|
|
bitfld.long 0x00 11. " CFEMPTY ,Indicates whether the command FIFO is empty" "Not empty,Empty"
|
|
hexmask.long.word 0x00 0.--10. 1. " CFNUMEMPTY ,Command FIFO free count"
|
|
if (((per.l(ad:0x5000E000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type: Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long 0x00 2.--25. 0x04 " INDOFFSET ,Frame buffer address"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type:Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET ,Register offset"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
endif
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "CHANNEL_INDICT_0,Indirect Register Access Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDCOUNT ,Indcount"
|
|
line.long 0x04 "CHANNEL_IDDATA_0,Host1X Channel INDDATA_0"
|
|
line.long 0x08 "CHANNEL_RAISE_0,DMA And RAISE/REFCOUNT Functionality"
|
|
hexmask.long 0x08 2.--31. 1. " RAISE ,Channel's RAISE vector"
|
|
line.long 0x0C "CHANNEL_DMASTART_0,Host1X Channel DMSTART_0"
|
|
hexmask.long 0x0C 2.--31. 0x04 " DMASTART ,Cmdbuf frame buffer ofset"
|
|
line.long 0x10 "CHANNEL_DMAPUT_0, Host1X Channel DMAPUT_0"
|
|
hexmask.long 0x10 2.--31. 0x04 " DMAPUT ,Cmdbuf frame buffer offset"
|
|
rgroup.long 0x1C++0x0B
|
|
line.long 0x00 "CHANNEL_DMAGET_0,Host1X Channel DMAGET_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " DMAGET ,Cmdbuf frame buffer offset"
|
|
line.long 0x04 "CHANNEL_DMAEND_0 ,Host1X Channel DMAEND_0"
|
|
hexmask.long 0x04 2.--31. 0x04 " DMAEND ,Cmdbuf frame buffer offset"
|
|
line.long 0x08 "CHANNEL_DMACTRL_0,DMA Control Register"
|
|
bitfld.long 0x08 2. " DMAINITGET ,Reset GET pointer to the value of DMAPUT when DMAGETRST is asserted" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " DMAGETRST ,Reset GET pointer to 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " DMASTOP ,Stop DMA from fetching on this channel" "Run,Stop"
|
|
if (((per.l(ad:0x5000E000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " INDOFFSET2 ,Frame buffer address"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID2 ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET2 ,Register offset"
|
|
endif
|
|
group.long 0x90++0x2B
|
|
line.long 0x00 "CHANNEL_TICKCOUNT_HI_0,Host1X Channel TICKCOUNT HI 0"
|
|
line.long 0x04 "CHANNEL_TICKCOUNT_LO_0,Host1X Channel TICKCOUNT LO 0"
|
|
line.long 0x08 "CHANNEL_CHANNELCTRL_0,Host1X Channel CHANNELCTRL_0"
|
|
bitfld.long 0x08 2. " KERNEL_FILTER_GBUFFER ,Enable setclass command filter for gather buffers" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ENABLETICKCNT ,Enable tick counter" "Disabled,Enabled"
|
|
line.long 0x0C "CHANNEL_PAYLOAD_0,Host1X Channel PAYLOAD_0"
|
|
line.long 0x10 "CHANNEL_STALLCTRL_0,Host1X Channel STALLCTRL_0"
|
|
bitfld.long 0x10 0. " ENABLE_CHANNEL_STALL ,Enable channel STALL" "Disabled,Enabled"
|
|
line.long 0x14 "CHANNEL_STALLCOUNT_HI_0,Host1X Channel STALLCOUNT Hi 0"
|
|
line.long 0x18 "CHANNEL_STALLCOUNT_LO_0,Host1X Channel STALLCOUNT Lo 0"
|
|
line.long 0x1C "CHANNEL_XFERCTRL_0,Host1X Channel XFERCTRL 0"
|
|
bitfld.long 0x1C 0. " ENABLE_CHANNEL_XFER ,Enable channel XFER" "Disabled,Enabled"
|
|
line.long 0x20 "CHANNEL_CHANNEL_XFER_HI_0,Host1X Channel XFER Hi 0"
|
|
line.long 0x24 "CHANNEL_CHANNEL_XFER_LO_0,Host1X Channel XFER Lo 0"
|
|
line.long 0x28 "CHANNEL_CHANNEL_SPARE_0,Host1x Channel SPARE 0"
|
|
hexmask.long.word 0x28 16.--31. 1. " CHANNEL_SPARE_HI ,Channel SPARE Hi"
|
|
hexmask.long.word 0x28 0.--15. 1. " CHANNEL_SPARE_LO ,CHannel SPARE Lo"
|
|
tree.end
|
|
; base (ad:0x5000E000+0x2000) - ACTMON1(MSENC)
|
|
; base (ad:0x5000E000+0x2040) - ACTMON2(VIC)
|
|
width 23.
|
|
base (ad:0x5000E000+0x2100)
|
|
tree "SYNC (Synchronous Registers)"
|
|
sif CPUIS("TEGRAX1")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " VII2C_INT , VII2C interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOR1_INT ,SOR1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NVENC_INT ,NVENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " NVDEC_INT ,NVDEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 14. " NVJPG_INT ,NVJPG interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " TSECB_INT ,TSECB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " DPAUX1_INT ,DPAUX1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 4. " CPU_TZ_ILLEGAL_TZ_ACCESS_MASK ,Mask CPU_TZ_ILLEGAL_TZ_ACCESS" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 27. " VII2C_INT_C0MASK ,Interrupt mask for VII2C interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SOR1_INT_C0MASK ,Interrupt mask for SOR1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " NVENC_INT_C0MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " NVDEC_INT_C0MASK ,Interrupt mask for NVDEC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NVJPG_INT_C0MASK ,Interrupt mask for NVJPG interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " TSECB_INT_C0MASK ,Interrupt mask for TSECB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " DPAUX1_INT_C0MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 27. " VII2C_INT_C1MASK ,Interrupt mask for VII2C interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 22. " SOR1_INT_C1MASK ,Interrupt mask for SOR1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NVENC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " NVDEC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 14. " NVJPG_INT_C1MASK ,Interrupt mask for NVJPG interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " TSECB_INT_C1MASK ,Interrupt mask for TSECB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " DPAUX1_INT_C1MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " XBAR_TSEC_TIMEOUT_ID ,Id of the CPU which timed out and updated" "TSEC,XBAR"
|
|
eventfld.long 0x00 21. " WAIT_INT13 ,WAIT has completed on channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " WAIT_INT12 ,WAIT has completed on channel 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,Invalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " WAIT_INT13 ,WAIT interrupt mask 13" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " WAIT_INT12 ,WAIT interrupt mask 12" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 ACTMON interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 13. " CMDPP_ILLEGAL_OPCODE_INT13 ,CMPP 13 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 12. " CMDPP_ILLEGAL_OPCODE_INT12 ,CMPP 12 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " CMDPP_ILLEGAL_OPCODE_INTMASK13 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 12. " CMDPP_ILLEGAL_OPCODE_INTMASK12 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--13. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
wgroup.long 0xB0++0x0B
|
|
line.long 0x00 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x00 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x04 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x04 27. " VII2C_TEARDOWN ,VII2C teardown" "No action,Teardown"
|
|
bitfld.long 0x04 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x04 22. " SOR1_TEARDOWN ,SOR1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x04 19. " NVENC_TEARDOWN ,NVENC teardown" "No action,Teardown"
|
|
bitfld.long 0x04 18. " NVDEC_TEARDOWN ,NVEDC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 14. " NVJPG_TEARDOWN ,JVJPG teardown" "No action,Teardown"
|
|
bitfld.long 0x04 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " TSECB_TEARDOWN ,TSECB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DPAUX1_TEARDOWN ,DPAUX1 teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x47
|
|
line.long 0x00 "SYNC_DISPLAY_STATUS_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_STATUS_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_STATUS_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_STATUS_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_SOR1_STATUS_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,SOR1 currcl"
|
|
line.long 0x14 "SYNC_SOR_STATUS,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_STATUS_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_STATUS_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_STATUS_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_STATUS_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_NVENC_STATUS_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,NVENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_STATUS_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
line.long 0x34 "SYNC_NVDEC_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x34 16.--25. 1. " ISPB_CURRCL ,NVDEC currcl"
|
|
line.long 0x38 "SYNC_NVJPG_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x38 16.--25. 1. " ISPB_CURRCL ,NVJPG currcl"
|
|
line.long 0x3C "SYNC_VII2C_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x3C 16.--25. 1. " ISPB_CURRCL ,VII2C currcl"
|
|
line.long 0x40 "SYNC_DPAUX1_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x40 16.--25. 1. " ISPB_CURRCL ,DPAUX1 currcl"
|
|
line.long 0x44 "SYNC_TSECB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x44 16.--25. 1. " ISPB_CURRCL ,TSECB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 13. " HIPRI_CH13 ,HIPRI ch 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " HIPRI_CH12 ,HIPRI ch 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " MSENC_INT ,MSENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " HDMI_INT ,HDMi int " "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " MSENC_INT_C0MASK ,Interrupt mask for MSENC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " HDMI_INT_C0MASK ,Interrupt mask for HDMI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 19. " MSENC_INT_C1MASK ,Interrupt mask for MSENC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HDMI_INT_C1MASK ,Interrupt mask for HDMI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,INvalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " XBAR_TSEC_TIMEOUT_ID ,ID of the CPU which timed out and updated the timeout address" "Tsec,Xbar"
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 actmon interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 actmon interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--11. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
line.long 0x04 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x04 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x08 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x08 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
bitfld.long 0x08 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x08 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x08 19. " MSENC_TEARDOWN ,MSENC teardown" "No action,Teardown"
|
|
bitfld.long 0x08 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 10. " HDMI_TEARDOWN ,HDMI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x33
|
|
line.long 0x00 "SYNC_DISPLAY_Status_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_Status_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_Status_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_Status_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_HDMI_Status_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,HDMI currcl"
|
|
line.long 0x14 "SYNC_SOR_Status,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_Status_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_Status_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_Status_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_Status_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_MSENC_Status_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,MSENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_Status_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_Status_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
endif
|
|
width 23.
|
|
tree "MLOCK registers"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_0_0,Host1X Sync MLOCK_0_0"
|
|
bitfld.long 0x00 0. " MLOCK_0 ,Mlock_0" "Released,Held"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_1_0,Host1X Sync MLOCK_1_0"
|
|
bitfld.long 0x00 0. " MLOCK_1 ,Mlock_1" "Released,Held"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_2_0,Host1X Sync MLOCK_2_0"
|
|
bitfld.long 0x00 0. " MLOCK_2 ,Mlock_2" "Released,Held"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_3_0,Host1X Sync MLOCK_3_0"
|
|
bitfld.long 0x00 0. " MLOCK_3 ,Mlock_3" "Released,Held"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_4_0,Host1X Sync MLOCK_4_0"
|
|
bitfld.long 0x00 0. " MLOCK_4 ,Mlock_4" "Released,Held"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_5_0,Host1X Sync MLOCK_5_0"
|
|
bitfld.long 0x00 0. " MLOCK_5 ,Mlock_5" "Released,Held"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_6_0,Host1X Sync MLOCK_6_0"
|
|
bitfld.long 0x00 0. " MLOCK_6 ,Mlock_6" "Released,Held"
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_7_0,Host1X Sync MLOCK_7_0"
|
|
bitfld.long 0x00 0. " MLOCK_7 ,Mlock_7" "Released,Held"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_8_0,Host1X Sync MLOCK_8_0"
|
|
bitfld.long 0x00 0. " MLOCK_8 ,Mlock_8" "Released,Held"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_9_0,Host1X Sync MLOCK_9_0"
|
|
bitfld.long 0x00 0. " MLOCK_9 ,Mlock_9" "Released,Held"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_10_0,Host1X Sync MLOCK_10_0"
|
|
bitfld.long 0x00 0. " MLOCK_10 ,Mlock_10" "Released,Held"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_11_0,Host1X Sync MLOCK_11_0"
|
|
bitfld.long 0x00 0. " MLOCK_11 ,Mlock_11" "Released,Held"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_12_0,Host1X Sync MLOCK_12_0"
|
|
bitfld.long 0x00 0. " MLOCK_12 ,Mlock_12" "Released,Held"
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_13_0,Host1X Sync MLOCK_13_0"
|
|
bitfld.long 0x00 0. " MLOCK_13 ,Mlock_13" "Released,Held"
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_14_0,Host1X Sync MLOCK_14_0"
|
|
bitfld.long 0x00 0. " MLOCK_14 ,Mlock_14" "Released,Held"
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_15_0,Host1X Sync MLOCK_15_0"
|
|
bitfld.long 0x00 0. " MLOCK_15 ,Mlock_15" "Released,Held"
|
|
textline " "
|
|
rgroup.long 0x340++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_0_0,Host1X Sync MLOCK Owner 0_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_0 ,Mlock owner chid 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_0 ,MLOCK CPU owns 0" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_0 ,MLOCK CH owns 0" "Not owned,Owned"
|
|
rgroup.long 0x344++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_1_0,Host1X Sync MLOCK Owner 1_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_1 ,Mlock owner chid 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_1 ,MLOCK CPU owns 1" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_1 ,MLOCK CH owns 1" "Not owned,Owned"
|
|
rgroup.long 0x348++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_2_0,Host1X Sync MLOCK Owner 2_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_2 ,Mlock owner chid 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_2 ,MLOCK CPU owns 2" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_2 ,MLOCK CH owns 2" "Not owned,Owned"
|
|
rgroup.long 0x34C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_3_0,Host1X Sync MLOCK Owner 3_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_3 ,Mlock owner chid 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_3 ,MLOCK CPU owns 3" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_3 ,MLOCK CH owns 3" "Not owned,Owned"
|
|
rgroup.long 0x350++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_4_0,Host1X Sync MLOCK Owner 4_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_4 ,Mlock owner chid 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_4 ,MLOCK CPU owns 4" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_4 ,MLOCK CH owns 4" "Not owned,Owned"
|
|
rgroup.long 0x354++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_5_0,Host1X Sync MLOCK Owner 5_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_5 ,Mlock owner chid 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_5 ,MLOCK CPU owns 5" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_5 ,MLOCK CH owns 5" "Not owned,Owned"
|
|
rgroup.long 0x358++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_6_0,Host1X Sync MLOCK Owner 6_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_6 ,Mlock owner chid 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_6 ,MLOCK CPU owns 6" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_6 ,MLOCK CH owns 6" "Not owned,Owned"
|
|
rgroup.long 0x35C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_7_0,Host1X Sync MLOCK Owner 7_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_7 ,Mlock owner chid 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_7 ,MLOCK CPU owns 7" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_7 ,MLOCK CH owns 7" "Not owned,Owned"
|
|
rgroup.long 0x360++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_8_0,Host1X Sync MLOCK Owner 8_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_8 ,Mlock owner chid 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_8 ,MLOCK CPU owns 8" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_8 ,MLOCK CH owns 8" "Not owned,Owned"
|
|
rgroup.long 0x364++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_9_0,Host1X Sync MLOCK Owner 9_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_9 ,Mlock owner chid 9" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_9 ,MLOCK CPU owns 9" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_9 ,MLOCK CH owns 9" "Not owned,Owned"
|
|
rgroup.long 0x368++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_10_0,Host1X Sync MLOCK Owner 10_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_10 ,Mlock owner chid 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_10 ,MLOCK CPU owns 10" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_10 ,MLOCK CH owns 10" "Not owned,Owned"
|
|
rgroup.long 0x36C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_11_0,Host1X Sync MLOCK Owner 11_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_11 ,Mlock owner chid 11" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_11 ,MLOCK CPU owns 11" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_11 ,MLOCK CH owns 11" "Not owned,Owned"
|
|
rgroup.long 0x370++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_12_0,Host1X Sync MLOCK Owner 12_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_12 ,Mlock owner chid 12" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_12 ,MLOCK CPU owns 12" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_12 ,MLOCK CH owns 12" "Not owned,Owned"
|
|
rgroup.long 0x374++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_13_0,Host1X Sync MLOCK Owner 13_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_13 ,Mlock owner chid 13" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_13 ,MLOCK CPU owns 13" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_13 ,MLOCK CH owns 13" "Not owned,Owned"
|
|
rgroup.long 0x378++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_14_0,Host1X Sync MLOCK Owner 14_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_14 ,Mlock owner chid 14" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_14 ,MLOCK CPU owns 14" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_14 ,MLOCK CH owns 14" "Not owned,Owned"
|
|
rgroup.long 0x37C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_15_0,Host1X Sync MLOCK Owner 15_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_15 ,Mlock owner chid 15" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_15 ,MLOCK CPU owns 15" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_15 ,MLOCK CH owns 15" "Not owned,Owned"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_ERROR_0_0,Host1X Sync Mlock Error 0_0"
|
|
bitfld.long 0x00 15. " MLOCK_ERROR_15 ,Mlock error 15" "No error,Error"
|
|
bitfld.long 0x00 14. " MLOCK_ERROR_14 ,Mlock error 14" "No error,Error"
|
|
bitfld.long 0x00 13. " MLOCK_ERROR_13 ,Mlock error 13" "No error,Error"
|
|
bitfld.long 0x00 12. " MLOCK_ERROR_12 ,Mlock error 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MLOCK_ERROR_11 ,Mlock error 11" "No error,Error"
|
|
bitfld.long 0x00 10. " MLOCK_ERROR_10 ,Mlock error 10" "No error,Error"
|
|
bitfld.long 0x00 9. " MLOCK_ERROR_9 ,Mlock error 9" "No error,Error"
|
|
bitfld.long 0x00 8. " MLOCK_ERROR_8 ,Mlock error 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MLOCK_ERROR_7 ,Mlock error 7" "No error,Error"
|
|
bitfld.long 0x00 6. " MLOCK_ERROR_6 ,Mlock error 6" "No error,Error"
|
|
bitfld.long 0x00 5. " MLOCK_ERROR_5 ,Mlock error 5" "No error,Error"
|
|
bitfld.long 0x00 4. " MLOCK_ERROR_4 ,Mlock error 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MLOCK_ERROR_3 ,Mlock error 3" "No error,Error"
|
|
bitfld.long 0x00 2. " MLOCK_ERROR_2 ,Mlock error 2" "No error,Error"
|
|
bitfld.long 0x00 1. " MLOCK_ERROR_1 ,Mlock error 1" "No error,Error"
|
|
bitfld.long 0x00 0. " MLOCK_ERROR_0 ,Mlock error 0" "No error,Error"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_0_0,Host1X Sync Syncpt Base 0_0"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_1_0,Host1X Sync Syncpt Base 1_0"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_2_0,Host1X Sync Syncpt Base 2_0"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_3_0,Host1X Sync Syncpt Base 3_0"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_4_0,Host1X Sync Syncpt Base 4_0"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_5_0,Host1X Sync Syncpt Base 5_0"
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_6_0,Host1X Sync Syncpt Base 6_0"
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_7_0,Host1X Sync Syncpt Base 7_0"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_8_0,Host1X Sync Syncpt Base 8_0"
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_9_0,Host1X Sync Syncpt Base 9_0"
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_10_0,Host1X Sync Syncpt Base 10_0"
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_11_0,Host1X Sync Syncpt Base 11_0"
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_12_0,Host1X Sync Syncpt Base 12_0"
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_13_0,Host1X Sync Syncpt Base 13_0"
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_14_0,Host1X Sync Syncpt Base 14_0"
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_15_0,Host1X Sync Syncpt Base 15_0"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_16_0,Host1X Sync Syncpt Base 16_0"
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_17_0,Host1X Sync Syncpt Base 17_0"
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_18_0,Host1X Sync Syncpt Base 18_0"
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_19_0,Host1X Sync Syncpt Base 19_0"
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_20_0,Host1X Sync Syncpt Base 20_0"
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_21_0,Host1X Sync Syncpt Base 21_0"
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_22_0,Host1X Sync Syncpt Base 22_0"
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_23_0,Host1X Sync Syncpt Base 23_0"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_24_0,Host1X Sync Syncpt Base 24_0"
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_25_0,Host1X Sync Syncpt Base 25_0"
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_26_0,Host1X Sync Syncpt Base 26_0"
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_27_0,Host1X Sync Syncpt Base 27_0"
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_28_0,Host1X Sync Syncpt Base 28_0"
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_29_0,Host1X Sync Syncpt Base 29_0"
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_30_0,Host1X Sync Syncpt Base 30_0"
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_31_0,Host1X Sync Syncpt Base 31_0"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_32_0,Host1X Sync Syncpt Base 32_0"
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_33_0,Host1X Sync Syncpt Base 33_0"
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_34_0,Host1X Sync Syncpt Base 34_0"
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_35_0,Host1X Sync Syncpt Base 35_0"
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_36_0,Host1X Sync Syncpt Base 36_0"
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_37_0,Host1X Sync Syncpt Base 37_0"
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_38_0,Host1X Sync Syncpt Base 38_0"
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_39_0,Host1X Sync Syncpt Base 39_0"
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_40_0,Host1X Sync Syncpt Base 40_0"
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_41_0,Host1X Sync Syncpt Base 41_0"
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_42_0,Host1X Sync Syncpt Base 42_0"
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_43_0,Host1X Sync Syncpt Base 43_0"
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_44_0,Host1X Sync Syncpt Base 44_0"
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_45_0,Host1X Sync Syncpt Base 45_0"
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_46_0,Host1X Sync Syncpt Base 46_0"
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_47_0,Host1X Sync Syncpt Base 47_0"
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_48_0,Host1X Sync Syncpt Base 48_0"
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_49_0,Host1X Sync Syncpt Base 49_0"
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_50_0,Host1X Sync Syncpt Base 50_0"
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_51_0,Host1X Sync Syncpt Base 51_0"
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_52_0,Host1X Sync Syncpt Base 52_0"
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_53_0,Host1X Sync Syncpt Base 53_0"
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_54_0,Host1X Sync Syncpt Base 54_0"
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_55_0,Host1X Sync Syncpt Base 55_0"
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_56_0,Host1X Sync Syncpt Base 56_0"
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_57_0,Host1X Sync Syncpt Base 57_0"
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_58_0,Host1X Sync Syncpt Base 58_0"
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_59_0,Host1X Sync Syncpt Base 59_0"
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_60_0,Host1X Sync Syncpt Base 60_0"
|
|
group.long 0x6F4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_61_0,Host1X Sync Syncpt Base 61_0"
|
|
group.long 0x6F8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_62_0,Host1X Sync Syncpt Base 62_0"
|
|
group.long 0x6FC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_63_0,Host1X Sync Syncpt Base 63_0"
|
|
tree.end
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 4"
|
|
base ad:0x50013000
|
|
width 27.
|
|
tree "Channel Registers"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CHANNEL_FIFOSTAT_0,Host1X Channel FIFOSTAT_0"
|
|
bitfld.long 0x00 31. " INDRDY ,Indicates that INDCOUNT == 0 so it should be OK to issue another read" "0,1"
|
|
bitfld.long 0x00 24.--28. " OUTFENTRIES ,Number of entries available for reading in this channel's output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " REGNUMEMPTY ,Register write/read FIFO free count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CFGATHER ,Indicates whether GATHER is active" "Idle,Busy"
|
|
bitfld.long 0x00 11. " CFEMPTY ,Indicates whether the command FIFO is empty" "Not empty,Empty"
|
|
hexmask.long.word 0x00 0.--10. 1. " CFNUMEMPTY ,Command FIFO free count"
|
|
if (((per.l(ad:0x50013000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type: Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long 0x00 2.--25. 0x04 " INDOFFSET ,Frame buffer address"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type:Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET ,Register offset"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
endif
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "CHANNEL_INDICT_0,Indirect Register Access Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDCOUNT ,Indcount"
|
|
line.long 0x04 "CHANNEL_IDDATA_0,Host1X Channel INDDATA_0"
|
|
line.long 0x08 "CHANNEL_RAISE_0,DMA And RAISE/REFCOUNT Functionality"
|
|
hexmask.long 0x08 2.--31. 1. " RAISE ,Channel's RAISE vector"
|
|
line.long 0x0C "CHANNEL_DMASTART_0,Host1X Channel DMSTART_0"
|
|
hexmask.long 0x0C 2.--31. 0x04 " DMASTART ,Cmdbuf frame buffer ofset"
|
|
line.long 0x10 "CHANNEL_DMAPUT_0, Host1X Channel DMAPUT_0"
|
|
hexmask.long 0x10 2.--31. 0x04 " DMAPUT ,Cmdbuf frame buffer offset"
|
|
rgroup.long 0x1C++0x0B
|
|
line.long 0x00 "CHANNEL_DMAGET_0,Host1X Channel DMAGET_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " DMAGET ,Cmdbuf frame buffer offset"
|
|
line.long 0x04 "CHANNEL_DMAEND_0 ,Host1X Channel DMAEND_0"
|
|
hexmask.long 0x04 2.--31. 0x04 " DMAEND ,Cmdbuf frame buffer offset"
|
|
line.long 0x08 "CHANNEL_DMACTRL_0,DMA Control Register"
|
|
bitfld.long 0x08 2. " DMAINITGET ,Reset GET pointer to the value of DMAPUT when DMAGETRST is asserted" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " DMAGETRST ,Reset GET pointer to 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " DMASTOP ,Stop DMA from fetching on this channel" "Run,Stop"
|
|
if (((per.l(ad:0x50013000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " INDOFFSET2 ,Frame buffer address"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID2 ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET2 ,Register offset"
|
|
endif
|
|
group.long 0x90++0x2B
|
|
line.long 0x00 "CHANNEL_TICKCOUNT_HI_0,Host1X Channel TICKCOUNT HI 0"
|
|
line.long 0x04 "CHANNEL_TICKCOUNT_LO_0,Host1X Channel TICKCOUNT LO 0"
|
|
line.long 0x08 "CHANNEL_CHANNELCTRL_0,Host1X Channel CHANNELCTRL_0"
|
|
bitfld.long 0x08 2. " KERNEL_FILTER_GBUFFER ,Enable setclass command filter for gather buffers" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ENABLETICKCNT ,Enable tick counter" "Disabled,Enabled"
|
|
line.long 0x0C "CHANNEL_PAYLOAD_0,Host1X Channel PAYLOAD_0"
|
|
line.long 0x10 "CHANNEL_STALLCTRL_0,Host1X Channel STALLCTRL_0"
|
|
bitfld.long 0x10 0. " ENABLE_CHANNEL_STALL ,Enable channel STALL" "Disabled,Enabled"
|
|
line.long 0x14 "CHANNEL_STALLCOUNT_HI_0,Host1X Channel STALLCOUNT Hi 0"
|
|
line.long 0x18 "CHANNEL_STALLCOUNT_LO_0,Host1X Channel STALLCOUNT Lo 0"
|
|
line.long 0x1C "CHANNEL_XFERCTRL_0,Host1X Channel XFERCTRL 0"
|
|
bitfld.long 0x1C 0. " ENABLE_CHANNEL_XFER ,Enable channel XFER" "Disabled,Enabled"
|
|
line.long 0x20 "CHANNEL_CHANNEL_XFER_HI_0,Host1X Channel XFER Hi 0"
|
|
line.long 0x24 "CHANNEL_CHANNEL_XFER_LO_0,Host1X Channel XFER Lo 0"
|
|
line.long 0x28 "CHANNEL_CHANNEL_SPARE_0,Host1x Channel SPARE 0"
|
|
hexmask.long.word 0x28 16.--31. 1. " CHANNEL_SPARE_HI ,Channel SPARE Hi"
|
|
hexmask.long.word 0x28 0.--15. 1. " CHANNEL_SPARE_LO ,CHannel SPARE Lo"
|
|
tree.end
|
|
; base (ad:0x50013000+0x2000) - ACTMON1(MSENC)
|
|
; base (ad:0x50013000+0x2040) - ACTMON2(VIC)
|
|
width 23.
|
|
base (ad:0x50013000+0x2100)
|
|
tree "SYNC (Synchronous Registers)"
|
|
sif CPUIS("TEGRAX1")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " VII2C_INT , VII2C interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOR1_INT ,SOR1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NVENC_INT ,NVENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " NVDEC_INT ,NVDEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 14. " NVJPG_INT ,NVJPG interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " TSECB_INT ,TSECB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " DPAUX1_INT ,DPAUX1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 4. " CPU_TZ_ILLEGAL_TZ_ACCESS_MASK ,Mask CPU_TZ_ILLEGAL_TZ_ACCESS" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 27. " VII2C_INT_C0MASK ,Interrupt mask for VII2C interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SOR1_INT_C0MASK ,Interrupt mask for SOR1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " NVENC_INT_C0MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " NVDEC_INT_C0MASK ,Interrupt mask for NVDEC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NVJPG_INT_C0MASK ,Interrupt mask for NVJPG interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " TSECB_INT_C0MASK ,Interrupt mask for TSECB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " DPAUX1_INT_C0MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 27. " VII2C_INT_C1MASK ,Interrupt mask for VII2C interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 22. " SOR1_INT_C1MASK ,Interrupt mask for SOR1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NVENC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " NVDEC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 14. " NVJPG_INT_C1MASK ,Interrupt mask for NVJPG interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " TSECB_INT_C1MASK ,Interrupt mask for TSECB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " DPAUX1_INT_C1MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " XBAR_TSEC_TIMEOUT_ID ,Id of the CPU which timed out and updated" "TSEC,XBAR"
|
|
eventfld.long 0x00 21. " WAIT_INT13 ,WAIT has completed on channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " WAIT_INT12 ,WAIT has completed on channel 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,Invalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " WAIT_INT13 ,WAIT interrupt mask 13" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " WAIT_INT12 ,WAIT interrupt mask 12" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 ACTMON interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 13. " CMDPP_ILLEGAL_OPCODE_INT13 ,CMPP 13 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 12. " CMDPP_ILLEGAL_OPCODE_INT12 ,CMPP 12 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " CMDPP_ILLEGAL_OPCODE_INTMASK13 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 12. " CMDPP_ILLEGAL_OPCODE_INTMASK12 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--13. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
wgroup.long 0xB0++0x0B
|
|
line.long 0x00 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x00 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x04 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x04 27. " VII2C_TEARDOWN ,VII2C teardown" "No action,Teardown"
|
|
bitfld.long 0x04 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x04 22. " SOR1_TEARDOWN ,SOR1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x04 19. " NVENC_TEARDOWN ,NVENC teardown" "No action,Teardown"
|
|
bitfld.long 0x04 18. " NVDEC_TEARDOWN ,NVEDC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 14. " NVJPG_TEARDOWN ,JVJPG teardown" "No action,Teardown"
|
|
bitfld.long 0x04 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " TSECB_TEARDOWN ,TSECB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DPAUX1_TEARDOWN ,DPAUX1 teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x47
|
|
line.long 0x00 "SYNC_DISPLAY_STATUS_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_STATUS_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_STATUS_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_STATUS_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_SOR1_STATUS_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,SOR1 currcl"
|
|
line.long 0x14 "SYNC_SOR_STATUS,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_STATUS_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_STATUS_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_STATUS_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_STATUS_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_NVENC_STATUS_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,NVENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_STATUS_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
line.long 0x34 "SYNC_NVDEC_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x34 16.--25. 1. " ISPB_CURRCL ,NVDEC currcl"
|
|
line.long 0x38 "SYNC_NVJPG_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x38 16.--25. 1. " ISPB_CURRCL ,NVJPG currcl"
|
|
line.long 0x3C "SYNC_VII2C_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x3C 16.--25. 1. " ISPB_CURRCL ,VII2C currcl"
|
|
line.long 0x40 "SYNC_DPAUX1_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x40 16.--25. 1. " ISPB_CURRCL ,DPAUX1 currcl"
|
|
line.long 0x44 "SYNC_TSECB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x44 16.--25. 1. " ISPB_CURRCL ,TSECB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 13. " HIPRI_CH13 ,HIPRI ch 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " HIPRI_CH12 ,HIPRI ch 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " MSENC_INT ,MSENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " HDMI_INT ,HDMi int " "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " MSENC_INT_C0MASK ,Interrupt mask for MSENC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " HDMI_INT_C0MASK ,Interrupt mask for HDMI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 19. " MSENC_INT_C1MASK ,Interrupt mask for MSENC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HDMI_INT_C1MASK ,Interrupt mask for HDMI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,INvalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " XBAR_TSEC_TIMEOUT_ID ,ID of the CPU which timed out and updated the timeout address" "Tsec,Xbar"
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 actmon interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 actmon interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--11. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
line.long 0x04 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x04 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x08 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x08 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
bitfld.long 0x08 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x08 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x08 19. " MSENC_TEARDOWN ,MSENC teardown" "No action,Teardown"
|
|
bitfld.long 0x08 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 10. " HDMI_TEARDOWN ,HDMI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x33
|
|
line.long 0x00 "SYNC_DISPLAY_Status_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_Status_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_Status_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_Status_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_HDMI_Status_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,HDMI currcl"
|
|
line.long 0x14 "SYNC_SOR_Status,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_Status_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_Status_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_Status_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_Status_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_MSENC_Status_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,MSENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_Status_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_Status_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
endif
|
|
width 23.
|
|
tree "MLOCK registers"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_0_0,Host1X Sync MLOCK_0_0"
|
|
bitfld.long 0x00 0. " MLOCK_0 ,Mlock_0" "Released,Held"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_1_0,Host1X Sync MLOCK_1_0"
|
|
bitfld.long 0x00 0. " MLOCK_1 ,Mlock_1" "Released,Held"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_2_0,Host1X Sync MLOCK_2_0"
|
|
bitfld.long 0x00 0. " MLOCK_2 ,Mlock_2" "Released,Held"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_3_0,Host1X Sync MLOCK_3_0"
|
|
bitfld.long 0x00 0. " MLOCK_3 ,Mlock_3" "Released,Held"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_4_0,Host1X Sync MLOCK_4_0"
|
|
bitfld.long 0x00 0. " MLOCK_4 ,Mlock_4" "Released,Held"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_5_0,Host1X Sync MLOCK_5_0"
|
|
bitfld.long 0x00 0. " MLOCK_5 ,Mlock_5" "Released,Held"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_6_0,Host1X Sync MLOCK_6_0"
|
|
bitfld.long 0x00 0. " MLOCK_6 ,Mlock_6" "Released,Held"
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_7_0,Host1X Sync MLOCK_7_0"
|
|
bitfld.long 0x00 0. " MLOCK_7 ,Mlock_7" "Released,Held"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_8_0,Host1X Sync MLOCK_8_0"
|
|
bitfld.long 0x00 0. " MLOCK_8 ,Mlock_8" "Released,Held"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_9_0,Host1X Sync MLOCK_9_0"
|
|
bitfld.long 0x00 0. " MLOCK_9 ,Mlock_9" "Released,Held"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_10_0,Host1X Sync MLOCK_10_0"
|
|
bitfld.long 0x00 0. " MLOCK_10 ,Mlock_10" "Released,Held"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_11_0,Host1X Sync MLOCK_11_0"
|
|
bitfld.long 0x00 0. " MLOCK_11 ,Mlock_11" "Released,Held"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_12_0,Host1X Sync MLOCK_12_0"
|
|
bitfld.long 0x00 0. " MLOCK_12 ,Mlock_12" "Released,Held"
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_13_0,Host1X Sync MLOCK_13_0"
|
|
bitfld.long 0x00 0. " MLOCK_13 ,Mlock_13" "Released,Held"
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_14_0,Host1X Sync MLOCK_14_0"
|
|
bitfld.long 0x00 0. " MLOCK_14 ,Mlock_14" "Released,Held"
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_15_0,Host1X Sync MLOCK_15_0"
|
|
bitfld.long 0x00 0. " MLOCK_15 ,Mlock_15" "Released,Held"
|
|
textline " "
|
|
rgroup.long 0x340++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_0_0,Host1X Sync MLOCK Owner 0_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_0 ,Mlock owner chid 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_0 ,MLOCK CPU owns 0" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_0 ,MLOCK CH owns 0" "Not owned,Owned"
|
|
rgroup.long 0x344++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_1_0,Host1X Sync MLOCK Owner 1_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_1 ,Mlock owner chid 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_1 ,MLOCK CPU owns 1" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_1 ,MLOCK CH owns 1" "Not owned,Owned"
|
|
rgroup.long 0x348++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_2_0,Host1X Sync MLOCK Owner 2_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_2 ,Mlock owner chid 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_2 ,MLOCK CPU owns 2" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_2 ,MLOCK CH owns 2" "Not owned,Owned"
|
|
rgroup.long 0x34C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_3_0,Host1X Sync MLOCK Owner 3_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_3 ,Mlock owner chid 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_3 ,MLOCK CPU owns 3" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_3 ,MLOCK CH owns 3" "Not owned,Owned"
|
|
rgroup.long 0x350++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_4_0,Host1X Sync MLOCK Owner 4_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_4 ,Mlock owner chid 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_4 ,MLOCK CPU owns 4" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_4 ,MLOCK CH owns 4" "Not owned,Owned"
|
|
rgroup.long 0x354++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_5_0,Host1X Sync MLOCK Owner 5_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_5 ,Mlock owner chid 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_5 ,MLOCK CPU owns 5" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_5 ,MLOCK CH owns 5" "Not owned,Owned"
|
|
rgroup.long 0x358++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_6_0,Host1X Sync MLOCK Owner 6_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_6 ,Mlock owner chid 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_6 ,MLOCK CPU owns 6" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_6 ,MLOCK CH owns 6" "Not owned,Owned"
|
|
rgroup.long 0x35C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_7_0,Host1X Sync MLOCK Owner 7_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_7 ,Mlock owner chid 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_7 ,MLOCK CPU owns 7" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_7 ,MLOCK CH owns 7" "Not owned,Owned"
|
|
rgroup.long 0x360++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_8_0,Host1X Sync MLOCK Owner 8_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_8 ,Mlock owner chid 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_8 ,MLOCK CPU owns 8" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_8 ,MLOCK CH owns 8" "Not owned,Owned"
|
|
rgroup.long 0x364++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_9_0,Host1X Sync MLOCK Owner 9_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_9 ,Mlock owner chid 9" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_9 ,MLOCK CPU owns 9" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_9 ,MLOCK CH owns 9" "Not owned,Owned"
|
|
rgroup.long 0x368++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_10_0,Host1X Sync MLOCK Owner 10_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_10 ,Mlock owner chid 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_10 ,MLOCK CPU owns 10" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_10 ,MLOCK CH owns 10" "Not owned,Owned"
|
|
rgroup.long 0x36C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_11_0,Host1X Sync MLOCK Owner 11_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_11 ,Mlock owner chid 11" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_11 ,MLOCK CPU owns 11" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_11 ,MLOCK CH owns 11" "Not owned,Owned"
|
|
rgroup.long 0x370++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_12_0,Host1X Sync MLOCK Owner 12_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_12 ,Mlock owner chid 12" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_12 ,MLOCK CPU owns 12" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_12 ,MLOCK CH owns 12" "Not owned,Owned"
|
|
rgroup.long 0x374++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_13_0,Host1X Sync MLOCK Owner 13_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_13 ,Mlock owner chid 13" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_13 ,MLOCK CPU owns 13" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_13 ,MLOCK CH owns 13" "Not owned,Owned"
|
|
rgroup.long 0x378++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_14_0,Host1X Sync MLOCK Owner 14_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_14 ,Mlock owner chid 14" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_14 ,MLOCK CPU owns 14" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_14 ,MLOCK CH owns 14" "Not owned,Owned"
|
|
rgroup.long 0x37C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_15_0,Host1X Sync MLOCK Owner 15_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_15 ,Mlock owner chid 15" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_15 ,MLOCK CPU owns 15" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_15 ,MLOCK CH owns 15" "Not owned,Owned"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_ERROR_0_0,Host1X Sync Mlock Error 0_0"
|
|
bitfld.long 0x00 15. " MLOCK_ERROR_15 ,Mlock error 15" "No error,Error"
|
|
bitfld.long 0x00 14. " MLOCK_ERROR_14 ,Mlock error 14" "No error,Error"
|
|
bitfld.long 0x00 13. " MLOCK_ERROR_13 ,Mlock error 13" "No error,Error"
|
|
bitfld.long 0x00 12. " MLOCK_ERROR_12 ,Mlock error 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MLOCK_ERROR_11 ,Mlock error 11" "No error,Error"
|
|
bitfld.long 0x00 10. " MLOCK_ERROR_10 ,Mlock error 10" "No error,Error"
|
|
bitfld.long 0x00 9. " MLOCK_ERROR_9 ,Mlock error 9" "No error,Error"
|
|
bitfld.long 0x00 8. " MLOCK_ERROR_8 ,Mlock error 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MLOCK_ERROR_7 ,Mlock error 7" "No error,Error"
|
|
bitfld.long 0x00 6. " MLOCK_ERROR_6 ,Mlock error 6" "No error,Error"
|
|
bitfld.long 0x00 5. " MLOCK_ERROR_5 ,Mlock error 5" "No error,Error"
|
|
bitfld.long 0x00 4. " MLOCK_ERROR_4 ,Mlock error 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MLOCK_ERROR_3 ,Mlock error 3" "No error,Error"
|
|
bitfld.long 0x00 2. " MLOCK_ERROR_2 ,Mlock error 2" "No error,Error"
|
|
bitfld.long 0x00 1. " MLOCK_ERROR_1 ,Mlock error 1" "No error,Error"
|
|
bitfld.long 0x00 0. " MLOCK_ERROR_0 ,Mlock error 0" "No error,Error"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_0_0,Host1X Sync Syncpt Base 0_0"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_1_0,Host1X Sync Syncpt Base 1_0"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_2_0,Host1X Sync Syncpt Base 2_0"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_3_0,Host1X Sync Syncpt Base 3_0"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_4_0,Host1X Sync Syncpt Base 4_0"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_5_0,Host1X Sync Syncpt Base 5_0"
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_6_0,Host1X Sync Syncpt Base 6_0"
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_7_0,Host1X Sync Syncpt Base 7_0"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_8_0,Host1X Sync Syncpt Base 8_0"
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_9_0,Host1X Sync Syncpt Base 9_0"
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_10_0,Host1X Sync Syncpt Base 10_0"
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_11_0,Host1X Sync Syncpt Base 11_0"
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_12_0,Host1X Sync Syncpt Base 12_0"
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_13_0,Host1X Sync Syncpt Base 13_0"
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_14_0,Host1X Sync Syncpt Base 14_0"
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_15_0,Host1X Sync Syncpt Base 15_0"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_16_0,Host1X Sync Syncpt Base 16_0"
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_17_0,Host1X Sync Syncpt Base 17_0"
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_18_0,Host1X Sync Syncpt Base 18_0"
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_19_0,Host1X Sync Syncpt Base 19_0"
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_20_0,Host1X Sync Syncpt Base 20_0"
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_21_0,Host1X Sync Syncpt Base 21_0"
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_22_0,Host1X Sync Syncpt Base 22_0"
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_23_0,Host1X Sync Syncpt Base 23_0"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_24_0,Host1X Sync Syncpt Base 24_0"
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_25_0,Host1X Sync Syncpt Base 25_0"
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_26_0,Host1X Sync Syncpt Base 26_0"
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_27_0,Host1X Sync Syncpt Base 27_0"
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_28_0,Host1X Sync Syncpt Base 28_0"
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_29_0,Host1X Sync Syncpt Base 29_0"
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_30_0,Host1X Sync Syncpt Base 30_0"
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_31_0,Host1X Sync Syncpt Base 31_0"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_32_0,Host1X Sync Syncpt Base 32_0"
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_33_0,Host1X Sync Syncpt Base 33_0"
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_34_0,Host1X Sync Syncpt Base 34_0"
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_35_0,Host1X Sync Syncpt Base 35_0"
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_36_0,Host1X Sync Syncpt Base 36_0"
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_37_0,Host1X Sync Syncpt Base 37_0"
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_38_0,Host1X Sync Syncpt Base 38_0"
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_39_0,Host1X Sync Syncpt Base 39_0"
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_40_0,Host1X Sync Syncpt Base 40_0"
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_41_0,Host1X Sync Syncpt Base 41_0"
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_42_0,Host1X Sync Syncpt Base 42_0"
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_43_0,Host1X Sync Syncpt Base 43_0"
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_44_0,Host1X Sync Syncpt Base 44_0"
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_45_0,Host1X Sync Syncpt Base 45_0"
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_46_0,Host1X Sync Syncpt Base 46_0"
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_47_0,Host1X Sync Syncpt Base 47_0"
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_48_0,Host1X Sync Syncpt Base 48_0"
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_49_0,Host1X Sync Syncpt Base 49_0"
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_50_0,Host1X Sync Syncpt Base 50_0"
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_51_0,Host1X Sync Syncpt Base 51_0"
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_52_0,Host1X Sync Syncpt Base 52_0"
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_53_0,Host1X Sync Syncpt Base 53_0"
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_54_0,Host1X Sync Syncpt Base 54_0"
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_55_0,Host1X Sync Syncpt Base 55_0"
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_56_0,Host1X Sync Syncpt Base 56_0"
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_57_0,Host1X Sync Syncpt Base 57_0"
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_58_0,Host1X Sync Syncpt Base 58_0"
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_59_0,Host1X Sync Syncpt Base 59_0"
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_60_0,Host1X Sync Syncpt Base 60_0"
|
|
group.long 0x6F4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_61_0,Host1X Sync Syncpt Base 61_0"
|
|
group.long 0x6F8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_62_0,Host1X Sync Syncpt Base 62_0"
|
|
group.long 0x6FC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_63_0,Host1X Sync Syncpt Base 63_0"
|
|
tree.end
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 5"
|
|
base ad:0x50017000
|
|
width 27.
|
|
tree "Channel Registers"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CHANNEL_FIFOSTAT_0,Host1X Channel FIFOSTAT_0"
|
|
bitfld.long 0x00 31. " INDRDY ,Indicates that INDCOUNT == 0 so it should be OK to issue another read" "0,1"
|
|
bitfld.long 0x00 24.--28. " OUTFENTRIES ,Number of entries available for reading in this channel's output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " REGNUMEMPTY ,Register write/read FIFO free count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CFGATHER ,Indicates whether GATHER is active" "Idle,Busy"
|
|
bitfld.long 0x00 11. " CFEMPTY ,Indicates whether the command FIFO is empty" "Not empty,Empty"
|
|
hexmask.long.word 0x00 0.--10. 1. " CFNUMEMPTY ,Command FIFO free count"
|
|
if (((per.l(ad:0x50017000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type: Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long 0x00 2.--25. 0x04 " INDOFFSET ,Frame buffer address"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type:Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET ,Register offset"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
endif
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "CHANNEL_INDICT_0,Indirect Register Access Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDCOUNT ,Indcount"
|
|
line.long 0x04 "CHANNEL_IDDATA_0,Host1X Channel INDDATA_0"
|
|
line.long 0x08 "CHANNEL_RAISE_0,DMA And RAISE/REFCOUNT Functionality"
|
|
hexmask.long 0x08 2.--31. 1. " RAISE ,Channel's RAISE vector"
|
|
line.long 0x0C "CHANNEL_DMASTART_0,Host1X Channel DMSTART_0"
|
|
hexmask.long 0x0C 2.--31. 0x04 " DMASTART ,Cmdbuf frame buffer ofset"
|
|
line.long 0x10 "CHANNEL_DMAPUT_0, Host1X Channel DMAPUT_0"
|
|
hexmask.long 0x10 2.--31. 0x04 " DMAPUT ,Cmdbuf frame buffer offset"
|
|
rgroup.long 0x1C++0x0B
|
|
line.long 0x00 "CHANNEL_DMAGET_0,Host1X Channel DMAGET_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " DMAGET ,Cmdbuf frame buffer offset"
|
|
line.long 0x04 "CHANNEL_DMAEND_0 ,Host1X Channel DMAEND_0"
|
|
hexmask.long 0x04 2.--31. 0x04 " DMAEND ,Cmdbuf frame buffer offset"
|
|
line.long 0x08 "CHANNEL_DMACTRL_0,DMA Control Register"
|
|
bitfld.long 0x08 2. " DMAINITGET ,Reset GET pointer to the value of DMAPUT when DMAGETRST is asserted" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " DMAGETRST ,Reset GET pointer to 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " DMASTOP ,Stop DMA from fetching on this channel" "Run,Stop"
|
|
if (((per.l(ad:0x50017000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " INDOFFSET2 ,Frame buffer address"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID2 ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET2 ,Register offset"
|
|
endif
|
|
group.long 0x90++0x2B
|
|
line.long 0x00 "CHANNEL_TICKCOUNT_HI_0,Host1X Channel TICKCOUNT HI 0"
|
|
line.long 0x04 "CHANNEL_TICKCOUNT_LO_0,Host1X Channel TICKCOUNT LO 0"
|
|
line.long 0x08 "CHANNEL_CHANNELCTRL_0,Host1X Channel CHANNELCTRL_0"
|
|
bitfld.long 0x08 2. " KERNEL_FILTER_GBUFFER ,Enable setclass command filter for gather buffers" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ENABLETICKCNT ,Enable tick counter" "Disabled,Enabled"
|
|
line.long 0x0C "CHANNEL_PAYLOAD_0,Host1X Channel PAYLOAD_0"
|
|
line.long 0x10 "CHANNEL_STALLCTRL_0,Host1X Channel STALLCTRL_0"
|
|
bitfld.long 0x10 0. " ENABLE_CHANNEL_STALL ,Enable channel STALL" "Disabled,Enabled"
|
|
line.long 0x14 "CHANNEL_STALLCOUNT_HI_0,Host1X Channel STALLCOUNT Hi 0"
|
|
line.long 0x18 "CHANNEL_STALLCOUNT_LO_0,Host1X Channel STALLCOUNT Lo 0"
|
|
line.long 0x1C "CHANNEL_XFERCTRL_0,Host1X Channel XFERCTRL 0"
|
|
bitfld.long 0x1C 0. " ENABLE_CHANNEL_XFER ,Enable channel XFER" "Disabled,Enabled"
|
|
line.long 0x20 "CHANNEL_CHANNEL_XFER_HI_0,Host1X Channel XFER Hi 0"
|
|
line.long 0x24 "CHANNEL_CHANNEL_XFER_LO_0,Host1X Channel XFER Lo 0"
|
|
line.long 0x28 "CHANNEL_CHANNEL_SPARE_0,Host1x Channel SPARE 0"
|
|
hexmask.long.word 0x28 16.--31. 1. " CHANNEL_SPARE_HI ,Channel SPARE Hi"
|
|
hexmask.long.word 0x28 0.--15. 1. " CHANNEL_SPARE_LO ,CHannel SPARE Lo"
|
|
tree.end
|
|
; base (ad:0x50017000+0x2000) - ACTMON1(MSENC)
|
|
; base (ad:0x50017000+0x2040) - ACTMON2(VIC)
|
|
width 23.
|
|
base (ad:0x50017000+0x2100)
|
|
tree "SYNC (Synchronous Registers)"
|
|
sif CPUIS("TEGRAX1")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " VII2C_INT , VII2C interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOR1_INT ,SOR1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NVENC_INT ,NVENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " NVDEC_INT ,NVDEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 14. " NVJPG_INT ,NVJPG interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " TSECB_INT ,TSECB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " DPAUX1_INT ,DPAUX1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 4. " CPU_TZ_ILLEGAL_TZ_ACCESS_MASK ,Mask CPU_TZ_ILLEGAL_TZ_ACCESS" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 27. " VII2C_INT_C0MASK ,Interrupt mask for VII2C interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SOR1_INT_C0MASK ,Interrupt mask for SOR1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " NVENC_INT_C0MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " NVDEC_INT_C0MASK ,Interrupt mask for NVDEC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NVJPG_INT_C0MASK ,Interrupt mask for NVJPG interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " TSECB_INT_C0MASK ,Interrupt mask for TSECB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " DPAUX1_INT_C0MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 27. " VII2C_INT_C1MASK ,Interrupt mask for VII2C interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 22. " SOR1_INT_C1MASK ,Interrupt mask for SOR1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NVENC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " NVDEC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 14. " NVJPG_INT_C1MASK ,Interrupt mask for NVJPG interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " TSECB_INT_C1MASK ,Interrupt mask for TSECB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " DPAUX1_INT_C1MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " XBAR_TSEC_TIMEOUT_ID ,Id of the CPU which timed out and updated" "TSEC,XBAR"
|
|
eventfld.long 0x00 21. " WAIT_INT13 ,WAIT has completed on channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " WAIT_INT12 ,WAIT has completed on channel 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,Invalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " WAIT_INT13 ,WAIT interrupt mask 13" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " WAIT_INT12 ,WAIT interrupt mask 12" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 ACTMON interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 13. " CMDPP_ILLEGAL_OPCODE_INT13 ,CMPP 13 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 12. " CMDPP_ILLEGAL_OPCODE_INT12 ,CMPP 12 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " CMDPP_ILLEGAL_OPCODE_INTMASK13 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 12. " CMDPP_ILLEGAL_OPCODE_INTMASK12 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--13. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
wgroup.long 0xB0++0x0B
|
|
line.long 0x00 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x00 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x04 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x04 27. " VII2C_TEARDOWN ,VII2C teardown" "No action,Teardown"
|
|
bitfld.long 0x04 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x04 22. " SOR1_TEARDOWN ,SOR1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x04 19. " NVENC_TEARDOWN ,NVENC teardown" "No action,Teardown"
|
|
bitfld.long 0x04 18. " NVDEC_TEARDOWN ,NVEDC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 14. " NVJPG_TEARDOWN ,JVJPG teardown" "No action,Teardown"
|
|
bitfld.long 0x04 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " TSECB_TEARDOWN ,TSECB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DPAUX1_TEARDOWN ,DPAUX1 teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x47
|
|
line.long 0x00 "SYNC_DISPLAY_STATUS_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_STATUS_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_STATUS_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_STATUS_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_SOR1_STATUS_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,SOR1 currcl"
|
|
line.long 0x14 "SYNC_SOR_STATUS,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_STATUS_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_STATUS_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_STATUS_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_STATUS_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_NVENC_STATUS_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,NVENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_STATUS_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
line.long 0x34 "SYNC_NVDEC_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x34 16.--25. 1. " ISPB_CURRCL ,NVDEC currcl"
|
|
line.long 0x38 "SYNC_NVJPG_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x38 16.--25. 1. " ISPB_CURRCL ,NVJPG currcl"
|
|
line.long 0x3C "SYNC_VII2C_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x3C 16.--25. 1. " ISPB_CURRCL ,VII2C currcl"
|
|
line.long 0x40 "SYNC_DPAUX1_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x40 16.--25. 1. " ISPB_CURRCL ,DPAUX1 currcl"
|
|
line.long 0x44 "SYNC_TSECB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x44 16.--25. 1. " ISPB_CURRCL ,TSECB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 13. " HIPRI_CH13 ,HIPRI ch 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " HIPRI_CH12 ,HIPRI ch 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " MSENC_INT ,MSENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " HDMI_INT ,HDMi int " "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " MSENC_INT_C0MASK ,Interrupt mask for MSENC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " HDMI_INT_C0MASK ,Interrupt mask for HDMI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 19. " MSENC_INT_C1MASK ,Interrupt mask for MSENC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HDMI_INT_C1MASK ,Interrupt mask for HDMI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,INvalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " XBAR_TSEC_TIMEOUT_ID ,ID of the CPU which timed out and updated the timeout address" "Tsec,Xbar"
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 actmon interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 actmon interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--11. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
line.long 0x04 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x04 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x08 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x08 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
bitfld.long 0x08 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x08 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x08 19. " MSENC_TEARDOWN ,MSENC teardown" "No action,Teardown"
|
|
bitfld.long 0x08 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 10. " HDMI_TEARDOWN ,HDMI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x33
|
|
line.long 0x00 "SYNC_DISPLAY_Status_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_Status_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_Status_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_Status_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_HDMI_Status_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,HDMI currcl"
|
|
line.long 0x14 "SYNC_SOR_Status,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_Status_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_Status_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_Status_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_Status_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_MSENC_Status_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,MSENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_Status_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_Status_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
endif
|
|
width 23.
|
|
tree "MLOCK registers"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_0_0,Host1X Sync MLOCK_0_0"
|
|
bitfld.long 0x00 0. " MLOCK_0 ,Mlock_0" "Released,Held"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_1_0,Host1X Sync MLOCK_1_0"
|
|
bitfld.long 0x00 0. " MLOCK_1 ,Mlock_1" "Released,Held"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_2_0,Host1X Sync MLOCK_2_0"
|
|
bitfld.long 0x00 0. " MLOCK_2 ,Mlock_2" "Released,Held"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_3_0,Host1X Sync MLOCK_3_0"
|
|
bitfld.long 0x00 0. " MLOCK_3 ,Mlock_3" "Released,Held"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_4_0,Host1X Sync MLOCK_4_0"
|
|
bitfld.long 0x00 0. " MLOCK_4 ,Mlock_4" "Released,Held"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_5_0,Host1X Sync MLOCK_5_0"
|
|
bitfld.long 0x00 0. " MLOCK_5 ,Mlock_5" "Released,Held"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_6_0,Host1X Sync MLOCK_6_0"
|
|
bitfld.long 0x00 0. " MLOCK_6 ,Mlock_6" "Released,Held"
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_7_0,Host1X Sync MLOCK_7_0"
|
|
bitfld.long 0x00 0. " MLOCK_7 ,Mlock_7" "Released,Held"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_8_0,Host1X Sync MLOCK_8_0"
|
|
bitfld.long 0x00 0. " MLOCK_8 ,Mlock_8" "Released,Held"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_9_0,Host1X Sync MLOCK_9_0"
|
|
bitfld.long 0x00 0. " MLOCK_9 ,Mlock_9" "Released,Held"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_10_0,Host1X Sync MLOCK_10_0"
|
|
bitfld.long 0x00 0. " MLOCK_10 ,Mlock_10" "Released,Held"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_11_0,Host1X Sync MLOCK_11_0"
|
|
bitfld.long 0x00 0. " MLOCK_11 ,Mlock_11" "Released,Held"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_12_0,Host1X Sync MLOCK_12_0"
|
|
bitfld.long 0x00 0. " MLOCK_12 ,Mlock_12" "Released,Held"
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_13_0,Host1X Sync MLOCK_13_0"
|
|
bitfld.long 0x00 0. " MLOCK_13 ,Mlock_13" "Released,Held"
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_14_0,Host1X Sync MLOCK_14_0"
|
|
bitfld.long 0x00 0. " MLOCK_14 ,Mlock_14" "Released,Held"
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_15_0,Host1X Sync MLOCK_15_0"
|
|
bitfld.long 0x00 0. " MLOCK_15 ,Mlock_15" "Released,Held"
|
|
textline " "
|
|
rgroup.long 0x340++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_0_0,Host1X Sync MLOCK Owner 0_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_0 ,Mlock owner chid 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_0 ,MLOCK CPU owns 0" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_0 ,MLOCK CH owns 0" "Not owned,Owned"
|
|
rgroup.long 0x344++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_1_0,Host1X Sync MLOCK Owner 1_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_1 ,Mlock owner chid 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_1 ,MLOCK CPU owns 1" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_1 ,MLOCK CH owns 1" "Not owned,Owned"
|
|
rgroup.long 0x348++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_2_0,Host1X Sync MLOCK Owner 2_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_2 ,Mlock owner chid 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_2 ,MLOCK CPU owns 2" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_2 ,MLOCK CH owns 2" "Not owned,Owned"
|
|
rgroup.long 0x34C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_3_0,Host1X Sync MLOCK Owner 3_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_3 ,Mlock owner chid 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_3 ,MLOCK CPU owns 3" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_3 ,MLOCK CH owns 3" "Not owned,Owned"
|
|
rgroup.long 0x350++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_4_0,Host1X Sync MLOCK Owner 4_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_4 ,Mlock owner chid 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_4 ,MLOCK CPU owns 4" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_4 ,MLOCK CH owns 4" "Not owned,Owned"
|
|
rgroup.long 0x354++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_5_0,Host1X Sync MLOCK Owner 5_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_5 ,Mlock owner chid 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_5 ,MLOCK CPU owns 5" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_5 ,MLOCK CH owns 5" "Not owned,Owned"
|
|
rgroup.long 0x358++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_6_0,Host1X Sync MLOCK Owner 6_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_6 ,Mlock owner chid 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_6 ,MLOCK CPU owns 6" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_6 ,MLOCK CH owns 6" "Not owned,Owned"
|
|
rgroup.long 0x35C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_7_0,Host1X Sync MLOCK Owner 7_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_7 ,Mlock owner chid 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_7 ,MLOCK CPU owns 7" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_7 ,MLOCK CH owns 7" "Not owned,Owned"
|
|
rgroup.long 0x360++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_8_0,Host1X Sync MLOCK Owner 8_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_8 ,Mlock owner chid 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_8 ,MLOCK CPU owns 8" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_8 ,MLOCK CH owns 8" "Not owned,Owned"
|
|
rgroup.long 0x364++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_9_0,Host1X Sync MLOCK Owner 9_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_9 ,Mlock owner chid 9" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_9 ,MLOCK CPU owns 9" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_9 ,MLOCK CH owns 9" "Not owned,Owned"
|
|
rgroup.long 0x368++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_10_0,Host1X Sync MLOCK Owner 10_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_10 ,Mlock owner chid 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_10 ,MLOCK CPU owns 10" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_10 ,MLOCK CH owns 10" "Not owned,Owned"
|
|
rgroup.long 0x36C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_11_0,Host1X Sync MLOCK Owner 11_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_11 ,Mlock owner chid 11" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_11 ,MLOCK CPU owns 11" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_11 ,MLOCK CH owns 11" "Not owned,Owned"
|
|
rgroup.long 0x370++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_12_0,Host1X Sync MLOCK Owner 12_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_12 ,Mlock owner chid 12" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_12 ,MLOCK CPU owns 12" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_12 ,MLOCK CH owns 12" "Not owned,Owned"
|
|
rgroup.long 0x374++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_13_0,Host1X Sync MLOCK Owner 13_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_13 ,Mlock owner chid 13" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_13 ,MLOCK CPU owns 13" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_13 ,MLOCK CH owns 13" "Not owned,Owned"
|
|
rgroup.long 0x378++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_14_0,Host1X Sync MLOCK Owner 14_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_14 ,Mlock owner chid 14" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_14 ,MLOCK CPU owns 14" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_14 ,MLOCK CH owns 14" "Not owned,Owned"
|
|
rgroup.long 0x37C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_15_0,Host1X Sync MLOCK Owner 15_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_15 ,Mlock owner chid 15" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_15 ,MLOCK CPU owns 15" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_15 ,MLOCK CH owns 15" "Not owned,Owned"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_ERROR_0_0,Host1X Sync Mlock Error 0_0"
|
|
bitfld.long 0x00 15. " MLOCK_ERROR_15 ,Mlock error 15" "No error,Error"
|
|
bitfld.long 0x00 14. " MLOCK_ERROR_14 ,Mlock error 14" "No error,Error"
|
|
bitfld.long 0x00 13. " MLOCK_ERROR_13 ,Mlock error 13" "No error,Error"
|
|
bitfld.long 0x00 12. " MLOCK_ERROR_12 ,Mlock error 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MLOCK_ERROR_11 ,Mlock error 11" "No error,Error"
|
|
bitfld.long 0x00 10. " MLOCK_ERROR_10 ,Mlock error 10" "No error,Error"
|
|
bitfld.long 0x00 9. " MLOCK_ERROR_9 ,Mlock error 9" "No error,Error"
|
|
bitfld.long 0x00 8. " MLOCK_ERROR_8 ,Mlock error 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MLOCK_ERROR_7 ,Mlock error 7" "No error,Error"
|
|
bitfld.long 0x00 6. " MLOCK_ERROR_6 ,Mlock error 6" "No error,Error"
|
|
bitfld.long 0x00 5. " MLOCK_ERROR_5 ,Mlock error 5" "No error,Error"
|
|
bitfld.long 0x00 4. " MLOCK_ERROR_4 ,Mlock error 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MLOCK_ERROR_3 ,Mlock error 3" "No error,Error"
|
|
bitfld.long 0x00 2. " MLOCK_ERROR_2 ,Mlock error 2" "No error,Error"
|
|
bitfld.long 0x00 1. " MLOCK_ERROR_1 ,Mlock error 1" "No error,Error"
|
|
bitfld.long 0x00 0. " MLOCK_ERROR_0 ,Mlock error 0" "No error,Error"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_0_0,Host1X Sync Syncpt Base 0_0"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_1_0,Host1X Sync Syncpt Base 1_0"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_2_0,Host1X Sync Syncpt Base 2_0"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_3_0,Host1X Sync Syncpt Base 3_0"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_4_0,Host1X Sync Syncpt Base 4_0"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_5_0,Host1X Sync Syncpt Base 5_0"
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_6_0,Host1X Sync Syncpt Base 6_0"
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_7_0,Host1X Sync Syncpt Base 7_0"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_8_0,Host1X Sync Syncpt Base 8_0"
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_9_0,Host1X Sync Syncpt Base 9_0"
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_10_0,Host1X Sync Syncpt Base 10_0"
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_11_0,Host1X Sync Syncpt Base 11_0"
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_12_0,Host1X Sync Syncpt Base 12_0"
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_13_0,Host1X Sync Syncpt Base 13_0"
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_14_0,Host1X Sync Syncpt Base 14_0"
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_15_0,Host1X Sync Syncpt Base 15_0"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_16_0,Host1X Sync Syncpt Base 16_0"
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_17_0,Host1X Sync Syncpt Base 17_0"
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_18_0,Host1X Sync Syncpt Base 18_0"
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_19_0,Host1X Sync Syncpt Base 19_0"
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_20_0,Host1X Sync Syncpt Base 20_0"
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_21_0,Host1X Sync Syncpt Base 21_0"
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_22_0,Host1X Sync Syncpt Base 22_0"
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_23_0,Host1X Sync Syncpt Base 23_0"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_24_0,Host1X Sync Syncpt Base 24_0"
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_25_0,Host1X Sync Syncpt Base 25_0"
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_26_0,Host1X Sync Syncpt Base 26_0"
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_27_0,Host1X Sync Syncpt Base 27_0"
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_28_0,Host1X Sync Syncpt Base 28_0"
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_29_0,Host1X Sync Syncpt Base 29_0"
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_30_0,Host1X Sync Syncpt Base 30_0"
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_31_0,Host1X Sync Syncpt Base 31_0"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_32_0,Host1X Sync Syncpt Base 32_0"
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_33_0,Host1X Sync Syncpt Base 33_0"
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_34_0,Host1X Sync Syncpt Base 34_0"
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_35_0,Host1X Sync Syncpt Base 35_0"
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_36_0,Host1X Sync Syncpt Base 36_0"
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_37_0,Host1X Sync Syncpt Base 37_0"
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_38_0,Host1X Sync Syncpt Base 38_0"
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_39_0,Host1X Sync Syncpt Base 39_0"
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_40_0,Host1X Sync Syncpt Base 40_0"
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_41_0,Host1X Sync Syncpt Base 41_0"
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_42_0,Host1X Sync Syncpt Base 42_0"
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_43_0,Host1X Sync Syncpt Base 43_0"
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_44_0,Host1X Sync Syncpt Base 44_0"
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_45_0,Host1X Sync Syncpt Base 45_0"
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_46_0,Host1X Sync Syncpt Base 46_0"
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_47_0,Host1X Sync Syncpt Base 47_0"
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_48_0,Host1X Sync Syncpt Base 48_0"
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_49_0,Host1X Sync Syncpt Base 49_0"
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_50_0,Host1X Sync Syncpt Base 50_0"
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_51_0,Host1X Sync Syncpt Base 51_0"
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_52_0,Host1X Sync Syncpt Base 52_0"
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_53_0,Host1X Sync Syncpt Base 53_0"
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_54_0,Host1X Sync Syncpt Base 54_0"
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_55_0,Host1X Sync Syncpt Base 55_0"
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_56_0,Host1X Sync Syncpt Base 56_0"
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_57_0,Host1X Sync Syncpt Base 57_0"
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_58_0,Host1X Sync Syncpt Base 58_0"
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_59_0,Host1X Sync Syncpt Base 59_0"
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_60_0,Host1X Sync Syncpt Base 60_0"
|
|
group.long 0x6F4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_61_0,Host1X Sync Syncpt Base 61_0"
|
|
group.long 0x6F8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_62_0,Host1X Sync Syncpt Base 62_0"
|
|
group.long 0x6FC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_63_0,Host1X Sync Syncpt Base 63_0"
|
|
tree.end
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 6"
|
|
base ad:0x5001B000
|
|
width 27.
|
|
tree "Channel Registers"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CHANNEL_FIFOSTAT_0,Host1X Channel FIFOSTAT_0"
|
|
bitfld.long 0x00 31. " INDRDY ,Indicates that INDCOUNT == 0 so it should be OK to issue another read" "0,1"
|
|
bitfld.long 0x00 24.--28. " OUTFENTRIES ,Number of entries available for reading in this channel's output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " REGNUMEMPTY ,Register write/read FIFO free count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CFGATHER ,Indicates whether GATHER is active" "Idle,Busy"
|
|
bitfld.long 0x00 11. " CFEMPTY ,Indicates whether the command FIFO is empty" "Not empty,Empty"
|
|
hexmask.long.word 0x00 0.--10. 1. " CFNUMEMPTY ,Command FIFO free count"
|
|
if (((per.l(ad:0x5001B000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type: Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long 0x00 2.--25. 0x04 " INDOFFSET ,Frame buffer address"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type:Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET ,Register offset"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
endif
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "CHANNEL_INDICT_0,Indirect Register Access Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDCOUNT ,Indcount"
|
|
line.long 0x04 "CHANNEL_IDDATA_0,Host1X Channel INDDATA_0"
|
|
line.long 0x08 "CHANNEL_RAISE_0,DMA And RAISE/REFCOUNT Functionality"
|
|
hexmask.long 0x08 2.--31. 1. " RAISE ,Channel's RAISE vector"
|
|
line.long 0x0C "CHANNEL_DMASTART_0,Host1X Channel DMSTART_0"
|
|
hexmask.long 0x0C 2.--31. 0x04 " DMASTART ,Cmdbuf frame buffer ofset"
|
|
line.long 0x10 "CHANNEL_DMAPUT_0, Host1X Channel DMAPUT_0"
|
|
hexmask.long 0x10 2.--31. 0x04 " DMAPUT ,Cmdbuf frame buffer offset"
|
|
rgroup.long 0x1C++0x0B
|
|
line.long 0x00 "CHANNEL_DMAGET_0,Host1X Channel DMAGET_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " DMAGET ,Cmdbuf frame buffer offset"
|
|
line.long 0x04 "CHANNEL_DMAEND_0 ,Host1X Channel DMAEND_0"
|
|
hexmask.long 0x04 2.--31. 0x04 " DMAEND ,Cmdbuf frame buffer offset"
|
|
line.long 0x08 "CHANNEL_DMACTRL_0,DMA Control Register"
|
|
bitfld.long 0x08 2. " DMAINITGET ,Reset GET pointer to the value of DMAPUT when DMAGETRST is asserted" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " DMAGETRST ,Reset GET pointer to 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " DMASTOP ,Stop DMA from fetching on this channel" "Run,Stop"
|
|
if (((per.l(ad:0x5001B000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " INDOFFSET2 ,Frame buffer address"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID2 ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET2 ,Register offset"
|
|
endif
|
|
group.long 0x90++0x2B
|
|
line.long 0x00 "CHANNEL_TICKCOUNT_HI_0,Host1X Channel TICKCOUNT HI 0"
|
|
line.long 0x04 "CHANNEL_TICKCOUNT_LO_0,Host1X Channel TICKCOUNT LO 0"
|
|
line.long 0x08 "CHANNEL_CHANNELCTRL_0,Host1X Channel CHANNELCTRL_0"
|
|
bitfld.long 0x08 2. " KERNEL_FILTER_GBUFFER ,Enable setclass command filter for gather buffers" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ENABLETICKCNT ,Enable tick counter" "Disabled,Enabled"
|
|
line.long 0x0C "CHANNEL_PAYLOAD_0,Host1X Channel PAYLOAD_0"
|
|
line.long 0x10 "CHANNEL_STALLCTRL_0,Host1X Channel STALLCTRL_0"
|
|
bitfld.long 0x10 0. " ENABLE_CHANNEL_STALL ,Enable channel STALL" "Disabled,Enabled"
|
|
line.long 0x14 "CHANNEL_STALLCOUNT_HI_0,Host1X Channel STALLCOUNT Hi 0"
|
|
line.long 0x18 "CHANNEL_STALLCOUNT_LO_0,Host1X Channel STALLCOUNT Lo 0"
|
|
line.long 0x1C "CHANNEL_XFERCTRL_0,Host1X Channel XFERCTRL 0"
|
|
bitfld.long 0x1C 0. " ENABLE_CHANNEL_XFER ,Enable channel XFER" "Disabled,Enabled"
|
|
line.long 0x20 "CHANNEL_CHANNEL_XFER_HI_0,Host1X Channel XFER Hi 0"
|
|
line.long 0x24 "CHANNEL_CHANNEL_XFER_LO_0,Host1X Channel XFER Lo 0"
|
|
line.long 0x28 "CHANNEL_CHANNEL_SPARE_0,Host1x Channel SPARE 0"
|
|
hexmask.long.word 0x28 16.--31. 1. " CHANNEL_SPARE_HI ,Channel SPARE Hi"
|
|
hexmask.long.word 0x28 0.--15. 1. " CHANNEL_SPARE_LO ,CHannel SPARE Lo"
|
|
tree.end
|
|
; base (ad:0x5001B000+0x2000) - ACTMON1(MSENC)
|
|
; base (ad:0x5001B000+0x2040) - ACTMON2(VIC)
|
|
width 23.
|
|
base (ad:0x5001B000+0x2100)
|
|
tree "SYNC (Synchronous Registers)"
|
|
sif CPUIS("TEGRAX1")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " VII2C_INT , VII2C interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOR1_INT ,SOR1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NVENC_INT ,NVENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " NVDEC_INT ,NVDEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 14. " NVJPG_INT ,NVJPG interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " TSECB_INT ,TSECB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " DPAUX1_INT ,DPAUX1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 4. " CPU_TZ_ILLEGAL_TZ_ACCESS_MASK ,Mask CPU_TZ_ILLEGAL_TZ_ACCESS" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 27. " VII2C_INT_C0MASK ,Interrupt mask for VII2C interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SOR1_INT_C0MASK ,Interrupt mask for SOR1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " NVENC_INT_C0MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " NVDEC_INT_C0MASK ,Interrupt mask for NVDEC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NVJPG_INT_C0MASK ,Interrupt mask for NVJPG interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " TSECB_INT_C0MASK ,Interrupt mask for TSECB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " DPAUX1_INT_C0MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 27. " VII2C_INT_C1MASK ,Interrupt mask for VII2C interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 22. " SOR1_INT_C1MASK ,Interrupt mask for SOR1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NVENC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " NVDEC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 14. " NVJPG_INT_C1MASK ,Interrupt mask for NVJPG interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " TSECB_INT_C1MASK ,Interrupt mask for TSECB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " DPAUX1_INT_C1MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " XBAR_TSEC_TIMEOUT_ID ,Id of the CPU which timed out and updated" "TSEC,XBAR"
|
|
eventfld.long 0x00 21. " WAIT_INT13 ,WAIT has completed on channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " WAIT_INT12 ,WAIT has completed on channel 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,Invalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " WAIT_INT13 ,WAIT interrupt mask 13" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " WAIT_INT12 ,WAIT interrupt mask 12" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 ACTMON interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 13. " CMDPP_ILLEGAL_OPCODE_INT13 ,CMPP 13 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 12. " CMDPP_ILLEGAL_OPCODE_INT12 ,CMPP 12 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " CMDPP_ILLEGAL_OPCODE_INTMASK13 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 12. " CMDPP_ILLEGAL_OPCODE_INTMASK12 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--13. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
wgroup.long 0xB0++0x0B
|
|
line.long 0x00 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x00 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x04 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x04 27. " VII2C_TEARDOWN ,VII2C teardown" "No action,Teardown"
|
|
bitfld.long 0x04 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x04 22. " SOR1_TEARDOWN ,SOR1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x04 19. " NVENC_TEARDOWN ,NVENC teardown" "No action,Teardown"
|
|
bitfld.long 0x04 18. " NVDEC_TEARDOWN ,NVEDC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 14. " NVJPG_TEARDOWN ,JVJPG teardown" "No action,Teardown"
|
|
bitfld.long 0x04 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " TSECB_TEARDOWN ,TSECB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DPAUX1_TEARDOWN ,DPAUX1 teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x47
|
|
line.long 0x00 "SYNC_DISPLAY_STATUS_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_STATUS_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_STATUS_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_STATUS_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_SOR1_STATUS_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,SOR1 currcl"
|
|
line.long 0x14 "SYNC_SOR_STATUS,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_STATUS_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_STATUS_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_STATUS_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_STATUS_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_NVENC_STATUS_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,NVENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_STATUS_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
line.long 0x34 "SYNC_NVDEC_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x34 16.--25. 1. " ISPB_CURRCL ,NVDEC currcl"
|
|
line.long 0x38 "SYNC_NVJPG_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x38 16.--25. 1. " ISPB_CURRCL ,NVJPG currcl"
|
|
line.long 0x3C "SYNC_VII2C_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x3C 16.--25. 1. " ISPB_CURRCL ,VII2C currcl"
|
|
line.long 0x40 "SYNC_DPAUX1_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x40 16.--25. 1. " ISPB_CURRCL ,DPAUX1 currcl"
|
|
line.long 0x44 "SYNC_TSECB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x44 16.--25. 1. " ISPB_CURRCL ,TSECB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
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|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
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|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 13. " HIPRI_CH13 ,HIPRI ch 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " HIPRI_CH12 ,HIPRI ch 12" "Disabled,Enabled"
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|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " MSENC_INT ,MSENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " HDMI_INT ,HDMi int " "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " MSENC_INT_C0MASK ,Interrupt mask for MSENC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " HDMI_INT_C0MASK ,Interrupt mask for HDMI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 19. " MSENC_INT_C1MASK ,Interrupt mask for MSENC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HDMI_INT_C1MASK ,Interrupt mask for HDMI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,INvalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " XBAR_TSEC_TIMEOUT_ID ,ID of the CPU which timed out and updated the timeout address" "Tsec,Xbar"
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 actmon interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 actmon interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--11. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
line.long 0x04 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x04 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x08 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x08 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
bitfld.long 0x08 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x08 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x08 19. " MSENC_TEARDOWN ,MSENC teardown" "No action,Teardown"
|
|
bitfld.long 0x08 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 10. " HDMI_TEARDOWN ,HDMI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x33
|
|
line.long 0x00 "SYNC_DISPLAY_Status_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_Status_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_Status_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_Status_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_HDMI_Status_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,HDMI currcl"
|
|
line.long 0x14 "SYNC_SOR_Status,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_Status_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_Status_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_Status_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_Status_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_MSENC_Status_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,MSENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_Status_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_Status_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
endif
|
|
width 23.
|
|
tree "MLOCK registers"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_0_0,Host1X Sync MLOCK_0_0"
|
|
bitfld.long 0x00 0. " MLOCK_0 ,Mlock_0" "Released,Held"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_1_0,Host1X Sync MLOCK_1_0"
|
|
bitfld.long 0x00 0. " MLOCK_1 ,Mlock_1" "Released,Held"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_2_0,Host1X Sync MLOCK_2_0"
|
|
bitfld.long 0x00 0. " MLOCK_2 ,Mlock_2" "Released,Held"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_3_0,Host1X Sync MLOCK_3_0"
|
|
bitfld.long 0x00 0. " MLOCK_3 ,Mlock_3" "Released,Held"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_4_0,Host1X Sync MLOCK_4_0"
|
|
bitfld.long 0x00 0. " MLOCK_4 ,Mlock_4" "Released,Held"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_5_0,Host1X Sync MLOCK_5_0"
|
|
bitfld.long 0x00 0. " MLOCK_5 ,Mlock_5" "Released,Held"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_6_0,Host1X Sync MLOCK_6_0"
|
|
bitfld.long 0x00 0. " MLOCK_6 ,Mlock_6" "Released,Held"
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_7_0,Host1X Sync MLOCK_7_0"
|
|
bitfld.long 0x00 0. " MLOCK_7 ,Mlock_7" "Released,Held"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_8_0,Host1X Sync MLOCK_8_0"
|
|
bitfld.long 0x00 0. " MLOCK_8 ,Mlock_8" "Released,Held"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_9_0,Host1X Sync MLOCK_9_0"
|
|
bitfld.long 0x00 0. " MLOCK_9 ,Mlock_9" "Released,Held"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_10_0,Host1X Sync MLOCK_10_0"
|
|
bitfld.long 0x00 0. " MLOCK_10 ,Mlock_10" "Released,Held"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_11_0,Host1X Sync MLOCK_11_0"
|
|
bitfld.long 0x00 0. " MLOCK_11 ,Mlock_11" "Released,Held"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_12_0,Host1X Sync MLOCK_12_0"
|
|
bitfld.long 0x00 0. " MLOCK_12 ,Mlock_12" "Released,Held"
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_13_0,Host1X Sync MLOCK_13_0"
|
|
bitfld.long 0x00 0. " MLOCK_13 ,Mlock_13" "Released,Held"
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_14_0,Host1X Sync MLOCK_14_0"
|
|
bitfld.long 0x00 0. " MLOCK_14 ,Mlock_14" "Released,Held"
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_15_0,Host1X Sync MLOCK_15_0"
|
|
bitfld.long 0x00 0. " MLOCK_15 ,Mlock_15" "Released,Held"
|
|
textline " "
|
|
rgroup.long 0x340++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_0_0,Host1X Sync MLOCK Owner 0_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_0 ,Mlock owner chid 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_0 ,MLOCK CPU owns 0" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_0 ,MLOCK CH owns 0" "Not owned,Owned"
|
|
rgroup.long 0x344++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_1_0,Host1X Sync MLOCK Owner 1_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_1 ,Mlock owner chid 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_1 ,MLOCK CPU owns 1" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_1 ,MLOCK CH owns 1" "Not owned,Owned"
|
|
rgroup.long 0x348++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_2_0,Host1X Sync MLOCK Owner 2_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_2 ,Mlock owner chid 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_2 ,MLOCK CPU owns 2" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_2 ,MLOCK CH owns 2" "Not owned,Owned"
|
|
rgroup.long 0x34C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_3_0,Host1X Sync MLOCK Owner 3_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_3 ,Mlock owner chid 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_3 ,MLOCK CPU owns 3" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_3 ,MLOCK CH owns 3" "Not owned,Owned"
|
|
rgroup.long 0x350++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_4_0,Host1X Sync MLOCK Owner 4_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_4 ,Mlock owner chid 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_4 ,MLOCK CPU owns 4" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_4 ,MLOCK CH owns 4" "Not owned,Owned"
|
|
rgroup.long 0x354++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_5_0,Host1X Sync MLOCK Owner 5_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_5 ,Mlock owner chid 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_5 ,MLOCK CPU owns 5" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_5 ,MLOCK CH owns 5" "Not owned,Owned"
|
|
rgroup.long 0x358++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_6_0,Host1X Sync MLOCK Owner 6_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_6 ,Mlock owner chid 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_6 ,MLOCK CPU owns 6" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_6 ,MLOCK CH owns 6" "Not owned,Owned"
|
|
rgroup.long 0x35C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_7_0,Host1X Sync MLOCK Owner 7_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_7 ,Mlock owner chid 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_7 ,MLOCK CPU owns 7" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_7 ,MLOCK CH owns 7" "Not owned,Owned"
|
|
rgroup.long 0x360++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_8_0,Host1X Sync MLOCK Owner 8_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_8 ,Mlock owner chid 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_8 ,MLOCK CPU owns 8" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_8 ,MLOCK CH owns 8" "Not owned,Owned"
|
|
rgroup.long 0x364++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_9_0,Host1X Sync MLOCK Owner 9_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_9 ,Mlock owner chid 9" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_9 ,MLOCK CPU owns 9" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_9 ,MLOCK CH owns 9" "Not owned,Owned"
|
|
rgroup.long 0x368++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_10_0,Host1X Sync MLOCK Owner 10_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_10 ,Mlock owner chid 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_10 ,MLOCK CPU owns 10" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_10 ,MLOCK CH owns 10" "Not owned,Owned"
|
|
rgroup.long 0x36C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_11_0,Host1X Sync MLOCK Owner 11_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_11 ,Mlock owner chid 11" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_11 ,MLOCK CPU owns 11" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_11 ,MLOCK CH owns 11" "Not owned,Owned"
|
|
rgroup.long 0x370++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_12_0,Host1X Sync MLOCK Owner 12_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_12 ,Mlock owner chid 12" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_12 ,MLOCK CPU owns 12" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_12 ,MLOCK CH owns 12" "Not owned,Owned"
|
|
rgroup.long 0x374++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_13_0,Host1X Sync MLOCK Owner 13_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_13 ,Mlock owner chid 13" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_13 ,MLOCK CPU owns 13" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_13 ,MLOCK CH owns 13" "Not owned,Owned"
|
|
rgroup.long 0x378++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_14_0,Host1X Sync MLOCK Owner 14_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_14 ,Mlock owner chid 14" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_14 ,MLOCK CPU owns 14" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_14 ,MLOCK CH owns 14" "Not owned,Owned"
|
|
rgroup.long 0x37C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_15_0,Host1X Sync MLOCK Owner 15_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_15 ,Mlock owner chid 15" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_15 ,MLOCK CPU owns 15" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_15 ,MLOCK CH owns 15" "Not owned,Owned"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_ERROR_0_0,Host1X Sync Mlock Error 0_0"
|
|
bitfld.long 0x00 15. " MLOCK_ERROR_15 ,Mlock error 15" "No error,Error"
|
|
bitfld.long 0x00 14. " MLOCK_ERROR_14 ,Mlock error 14" "No error,Error"
|
|
bitfld.long 0x00 13. " MLOCK_ERROR_13 ,Mlock error 13" "No error,Error"
|
|
bitfld.long 0x00 12. " MLOCK_ERROR_12 ,Mlock error 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MLOCK_ERROR_11 ,Mlock error 11" "No error,Error"
|
|
bitfld.long 0x00 10. " MLOCK_ERROR_10 ,Mlock error 10" "No error,Error"
|
|
bitfld.long 0x00 9. " MLOCK_ERROR_9 ,Mlock error 9" "No error,Error"
|
|
bitfld.long 0x00 8. " MLOCK_ERROR_8 ,Mlock error 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MLOCK_ERROR_7 ,Mlock error 7" "No error,Error"
|
|
bitfld.long 0x00 6. " MLOCK_ERROR_6 ,Mlock error 6" "No error,Error"
|
|
bitfld.long 0x00 5. " MLOCK_ERROR_5 ,Mlock error 5" "No error,Error"
|
|
bitfld.long 0x00 4. " MLOCK_ERROR_4 ,Mlock error 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MLOCK_ERROR_3 ,Mlock error 3" "No error,Error"
|
|
bitfld.long 0x00 2. " MLOCK_ERROR_2 ,Mlock error 2" "No error,Error"
|
|
bitfld.long 0x00 1. " MLOCK_ERROR_1 ,Mlock error 1" "No error,Error"
|
|
bitfld.long 0x00 0. " MLOCK_ERROR_0 ,Mlock error 0" "No error,Error"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_0_0,Host1X Sync Syncpt Base 0_0"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_1_0,Host1X Sync Syncpt Base 1_0"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_2_0,Host1X Sync Syncpt Base 2_0"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_3_0,Host1X Sync Syncpt Base 3_0"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_4_0,Host1X Sync Syncpt Base 4_0"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_5_0,Host1X Sync Syncpt Base 5_0"
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_6_0,Host1X Sync Syncpt Base 6_0"
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_7_0,Host1X Sync Syncpt Base 7_0"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_8_0,Host1X Sync Syncpt Base 8_0"
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_9_0,Host1X Sync Syncpt Base 9_0"
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_10_0,Host1X Sync Syncpt Base 10_0"
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_11_0,Host1X Sync Syncpt Base 11_0"
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_12_0,Host1X Sync Syncpt Base 12_0"
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_13_0,Host1X Sync Syncpt Base 13_0"
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_14_0,Host1X Sync Syncpt Base 14_0"
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_15_0,Host1X Sync Syncpt Base 15_0"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_16_0,Host1X Sync Syncpt Base 16_0"
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_17_0,Host1X Sync Syncpt Base 17_0"
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_18_0,Host1X Sync Syncpt Base 18_0"
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_19_0,Host1X Sync Syncpt Base 19_0"
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_20_0,Host1X Sync Syncpt Base 20_0"
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_21_0,Host1X Sync Syncpt Base 21_0"
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_22_0,Host1X Sync Syncpt Base 22_0"
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_23_0,Host1X Sync Syncpt Base 23_0"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_24_0,Host1X Sync Syncpt Base 24_0"
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_25_0,Host1X Sync Syncpt Base 25_0"
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_26_0,Host1X Sync Syncpt Base 26_0"
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_27_0,Host1X Sync Syncpt Base 27_0"
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_28_0,Host1X Sync Syncpt Base 28_0"
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_29_0,Host1X Sync Syncpt Base 29_0"
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_30_0,Host1X Sync Syncpt Base 30_0"
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_31_0,Host1X Sync Syncpt Base 31_0"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_32_0,Host1X Sync Syncpt Base 32_0"
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_33_0,Host1X Sync Syncpt Base 33_0"
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_34_0,Host1X Sync Syncpt Base 34_0"
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_35_0,Host1X Sync Syncpt Base 35_0"
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_36_0,Host1X Sync Syncpt Base 36_0"
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_37_0,Host1X Sync Syncpt Base 37_0"
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_38_0,Host1X Sync Syncpt Base 38_0"
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_39_0,Host1X Sync Syncpt Base 39_0"
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_40_0,Host1X Sync Syncpt Base 40_0"
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_41_0,Host1X Sync Syncpt Base 41_0"
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_42_0,Host1X Sync Syncpt Base 42_0"
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_43_0,Host1X Sync Syncpt Base 43_0"
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_44_0,Host1X Sync Syncpt Base 44_0"
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_45_0,Host1X Sync Syncpt Base 45_0"
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_46_0,Host1X Sync Syncpt Base 46_0"
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_47_0,Host1X Sync Syncpt Base 47_0"
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_48_0,Host1X Sync Syncpt Base 48_0"
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_49_0,Host1X Sync Syncpt Base 49_0"
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_50_0,Host1X Sync Syncpt Base 50_0"
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_51_0,Host1X Sync Syncpt Base 51_0"
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_52_0,Host1X Sync Syncpt Base 52_0"
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_53_0,Host1X Sync Syncpt Base 53_0"
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_54_0,Host1X Sync Syncpt Base 54_0"
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_55_0,Host1X Sync Syncpt Base 55_0"
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_56_0,Host1X Sync Syncpt Base 56_0"
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_57_0,Host1X Sync Syncpt Base 57_0"
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_58_0,Host1X Sync Syncpt Base 58_0"
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_59_0,Host1X Sync Syncpt Base 59_0"
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_60_0,Host1X Sync Syncpt Base 60_0"
|
|
group.long 0x6F4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_61_0,Host1X Sync Syncpt Base 61_0"
|
|
group.long 0x6F8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_62_0,Host1X Sync Syncpt Base 62_0"
|
|
group.long 0x6FC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_63_0,Host1X Sync Syncpt Base 63_0"
|
|
tree.end
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 7"
|
|
base ad:0x5001C0000
|
|
width 27.
|
|
tree "Channel Registers"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CHANNEL_FIFOSTAT_0,Host1X Channel FIFOSTAT_0"
|
|
bitfld.long 0x00 31. " INDRDY ,Indicates that INDCOUNT == 0 so it should be OK to issue another read" "0,1"
|
|
bitfld.long 0x00 24.--28. " OUTFENTRIES ,Number of entries available for reading in this channel's output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " REGNUMEMPTY ,Register write/read FIFO free count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CFGATHER ,Indicates whether GATHER is active" "Idle,Busy"
|
|
bitfld.long 0x00 11. " CFEMPTY ,Indicates whether the command FIFO is empty" "Not empty,Empty"
|
|
hexmask.long.word 0x00 0.--10. 1. " CFNUMEMPTY ,Command FIFO free count"
|
|
if (((per.l(ad:0x5001C0000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type: Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long 0x00 2.--25. 0x04 " INDOFFSET ,Frame buffer address"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type:Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET ,Register offset"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
endif
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "CHANNEL_INDICT_0,Indirect Register Access Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDCOUNT ,Indcount"
|
|
line.long 0x04 "CHANNEL_IDDATA_0,Host1X Channel INDDATA_0"
|
|
line.long 0x08 "CHANNEL_RAISE_0,DMA And RAISE/REFCOUNT Functionality"
|
|
hexmask.long 0x08 2.--31. 1. " RAISE ,Channel's RAISE vector"
|
|
line.long 0x0C "CHANNEL_DMASTART_0,Host1X Channel DMSTART_0"
|
|
hexmask.long 0x0C 2.--31. 0x04 " DMASTART ,Cmdbuf frame buffer ofset"
|
|
line.long 0x10 "CHANNEL_DMAPUT_0, Host1X Channel DMAPUT_0"
|
|
hexmask.long 0x10 2.--31. 0x04 " DMAPUT ,Cmdbuf frame buffer offset"
|
|
rgroup.long 0x1C++0x0B
|
|
line.long 0x00 "CHANNEL_DMAGET_0,Host1X Channel DMAGET_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " DMAGET ,Cmdbuf frame buffer offset"
|
|
line.long 0x04 "CHANNEL_DMAEND_0 ,Host1X Channel DMAEND_0"
|
|
hexmask.long 0x04 2.--31. 0x04 " DMAEND ,Cmdbuf frame buffer offset"
|
|
line.long 0x08 "CHANNEL_DMACTRL_0,DMA Control Register"
|
|
bitfld.long 0x08 2. " DMAINITGET ,Reset GET pointer to the value of DMAPUT when DMAGETRST is asserted" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " DMAGETRST ,Reset GET pointer to 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " DMASTOP ,Stop DMA from fetching on this channel" "Run,Stop"
|
|
if (((per.l(ad:0x5001C0000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " INDOFFSET2 ,Frame buffer address"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID2 ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET2 ,Register offset"
|
|
endif
|
|
group.long 0x90++0x2B
|
|
line.long 0x00 "CHANNEL_TICKCOUNT_HI_0,Host1X Channel TICKCOUNT HI 0"
|
|
line.long 0x04 "CHANNEL_TICKCOUNT_LO_0,Host1X Channel TICKCOUNT LO 0"
|
|
line.long 0x08 "CHANNEL_CHANNELCTRL_0,Host1X Channel CHANNELCTRL_0"
|
|
bitfld.long 0x08 2. " KERNEL_FILTER_GBUFFER ,Enable setclass command filter for gather buffers" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ENABLETICKCNT ,Enable tick counter" "Disabled,Enabled"
|
|
line.long 0x0C "CHANNEL_PAYLOAD_0,Host1X Channel PAYLOAD_0"
|
|
line.long 0x10 "CHANNEL_STALLCTRL_0,Host1X Channel STALLCTRL_0"
|
|
bitfld.long 0x10 0. " ENABLE_CHANNEL_STALL ,Enable channel STALL" "Disabled,Enabled"
|
|
line.long 0x14 "CHANNEL_STALLCOUNT_HI_0,Host1X Channel STALLCOUNT Hi 0"
|
|
line.long 0x18 "CHANNEL_STALLCOUNT_LO_0,Host1X Channel STALLCOUNT Lo 0"
|
|
line.long 0x1C "CHANNEL_XFERCTRL_0,Host1X Channel XFERCTRL 0"
|
|
bitfld.long 0x1C 0. " ENABLE_CHANNEL_XFER ,Enable channel XFER" "Disabled,Enabled"
|
|
line.long 0x20 "CHANNEL_CHANNEL_XFER_HI_0,Host1X Channel XFER Hi 0"
|
|
line.long 0x24 "CHANNEL_CHANNEL_XFER_LO_0,Host1X Channel XFER Lo 0"
|
|
line.long 0x28 "CHANNEL_CHANNEL_SPARE_0,Host1x Channel SPARE 0"
|
|
hexmask.long.word 0x28 16.--31. 1. " CHANNEL_SPARE_HI ,Channel SPARE Hi"
|
|
hexmask.long.word 0x28 0.--15. 1. " CHANNEL_SPARE_LO ,CHannel SPARE Lo"
|
|
tree.end
|
|
; base (ad:0x5001C0000+0x2000) - ACTMON1(MSENC)
|
|
; base (ad:0x5001C0000+0x2040) - ACTMON2(VIC)
|
|
width 23.
|
|
base (ad:0x5001C0000+0x2100)
|
|
tree "SYNC (Synchronous Registers)"
|
|
sif CPUIS("TEGRAX1")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " VII2C_INT , VII2C interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOR1_INT ,SOR1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NVENC_INT ,NVENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " NVDEC_INT ,NVDEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 14. " NVJPG_INT ,NVJPG interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " TSECB_INT ,TSECB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " DPAUX1_INT ,DPAUX1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 4. " CPU_TZ_ILLEGAL_TZ_ACCESS_MASK ,Mask CPU_TZ_ILLEGAL_TZ_ACCESS" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 27. " VII2C_INT_C0MASK ,Interrupt mask for VII2C interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SOR1_INT_C0MASK ,Interrupt mask for SOR1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " NVENC_INT_C0MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " NVDEC_INT_C0MASK ,Interrupt mask for NVDEC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NVJPG_INT_C0MASK ,Interrupt mask for NVJPG interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " TSECB_INT_C0MASK ,Interrupt mask for TSECB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " DPAUX1_INT_C0MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 27. " VII2C_INT_C1MASK ,Interrupt mask for VII2C interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 22. " SOR1_INT_C1MASK ,Interrupt mask for SOR1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NVENC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " NVDEC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 14. " NVJPG_INT_C1MASK ,Interrupt mask for NVJPG interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " TSECB_INT_C1MASK ,Interrupt mask for TSECB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " DPAUX1_INT_C1MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " XBAR_TSEC_TIMEOUT_ID ,Id of the CPU which timed out and updated" "TSEC,XBAR"
|
|
eventfld.long 0x00 21. " WAIT_INT13 ,WAIT has completed on channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " WAIT_INT12 ,WAIT has completed on channel 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,Invalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " WAIT_INT13 ,WAIT interrupt mask 13" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " WAIT_INT12 ,WAIT interrupt mask 12" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 ACTMON interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 13. " CMDPP_ILLEGAL_OPCODE_INT13 ,CMPP 13 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 12. " CMDPP_ILLEGAL_OPCODE_INT12 ,CMPP 12 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " CMDPP_ILLEGAL_OPCODE_INTMASK13 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 12. " CMDPP_ILLEGAL_OPCODE_INTMASK12 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--13. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
wgroup.long 0xB0++0x0B
|
|
line.long 0x00 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x00 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x04 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x04 27. " VII2C_TEARDOWN ,VII2C teardown" "No action,Teardown"
|
|
bitfld.long 0x04 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x04 22. " SOR1_TEARDOWN ,SOR1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x04 19. " NVENC_TEARDOWN ,NVENC teardown" "No action,Teardown"
|
|
bitfld.long 0x04 18. " NVDEC_TEARDOWN ,NVEDC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 14. " NVJPG_TEARDOWN ,JVJPG teardown" "No action,Teardown"
|
|
bitfld.long 0x04 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " TSECB_TEARDOWN ,TSECB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DPAUX1_TEARDOWN ,DPAUX1 teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x47
|
|
line.long 0x00 "SYNC_DISPLAY_STATUS_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_STATUS_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_STATUS_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_STATUS_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_SOR1_STATUS_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,SOR1 currcl"
|
|
line.long 0x14 "SYNC_SOR_STATUS,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_STATUS_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_STATUS_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_STATUS_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_STATUS_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_NVENC_STATUS_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,NVENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_STATUS_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
line.long 0x34 "SYNC_NVDEC_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x34 16.--25. 1. " ISPB_CURRCL ,NVDEC currcl"
|
|
line.long 0x38 "SYNC_NVJPG_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x38 16.--25. 1. " ISPB_CURRCL ,NVJPG currcl"
|
|
line.long 0x3C "SYNC_VII2C_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x3C 16.--25. 1. " ISPB_CURRCL ,VII2C currcl"
|
|
line.long 0x40 "SYNC_DPAUX1_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x40 16.--25. 1. " ISPB_CURRCL ,DPAUX1 currcl"
|
|
line.long 0x44 "SYNC_TSECB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x44 16.--25. 1. " ISPB_CURRCL ,TSECB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 13. " HIPRI_CH13 ,HIPRI ch 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " HIPRI_CH12 ,HIPRI ch 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " MSENC_INT ,MSENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " HDMI_INT ,HDMi int " "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " MSENC_INT_C0MASK ,Interrupt mask for MSENC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " HDMI_INT_C0MASK ,Interrupt mask for HDMI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 19. " MSENC_INT_C1MASK ,Interrupt mask for MSENC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HDMI_INT_C1MASK ,Interrupt mask for HDMI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,INvalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " XBAR_TSEC_TIMEOUT_ID ,ID of the CPU which timed out and updated the timeout address" "Tsec,Xbar"
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 actmon interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 actmon interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--11. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
line.long 0x04 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x04 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x08 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x08 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
bitfld.long 0x08 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x08 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x08 19. " MSENC_TEARDOWN ,MSENC teardown" "No action,Teardown"
|
|
bitfld.long 0x08 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 10. " HDMI_TEARDOWN ,HDMI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x33
|
|
line.long 0x00 "SYNC_DISPLAY_Status_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_Status_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_Status_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_Status_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_HDMI_Status_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,HDMI currcl"
|
|
line.long 0x14 "SYNC_SOR_Status,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_Status_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_Status_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_Status_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_Status_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_MSENC_Status_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,MSENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_Status_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_Status_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
endif
|
|
width 23.
|
|
tree "MLOCK registers"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_0_0,Host1X Sync MLOCK_0_0"
|
|
bitfld.long 0x00 0. " MLOCK_0 ,Mlock_0" "Released,Held"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_1_0,Host1X Sync MLOCK_1_0"
|
|
bitfld.long 0x00 0. " MLOCK_1 ,Mlock_1" "Released,Held"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_2_0,Host1X Sync MLOCK_2_0"
|
|
bitfld.long 0x00 0. " MLOCK_2 ,Mlock_2" "Released,Held"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_3_0,Host1X Sync MLOCK_3_0"
|
|
bitfld.long 0x00 0. " MLOCK_3 ,Mlock_3" "Released,Held"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_4_0,Host1X Sync MLOCK_4_0"
|
|
bitfld.long 0x00 0. " MLOCK_4 ,Mlock_4" "Released,Held"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_5_0,Host1X Sync MLOCK_5_0"
|
|
bitfld.long 0x00 0. " MLOCK_5 ,Mlock_5" "Released,Held"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_6_0,Host1X Sync MLOCK_6_0"
|
|
bitfld.long 0x00 0. " MLOCK_6 ,Mlock_6" "Released,Held"
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_7_0,Host1X Sync MLOCK_7_0"
|
|
bitfld.long 0x00 0. " MLOCK_7 ,Mlock_7" "Released,Held"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_8_0,Host1X Sync MLOCK_8_0"
|
|
bitfld.long 0x00 0. " MLOCK_8 ,Mlock_8" "Released,Held"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_9_0,Host1X Sync MLOCK_9_0"
|
|
bitfld.long 0x00 0. " MLOCK_9 ,Mlock_9" "Released,Held"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_10_0,Host1X Sync MLOCK_10_0"
|
|
bitfld.long 0x00 0. " MLOCK_10 ,Mlock_10" "Released,Held"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_11_0,Host1X Sync MLOCK_11_0"
|
|
bitfld.long 0x00 0. " MLOCK_11 ,Mlock_11" "Released,Held"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_12_0,Host1X Sync MLOCK_12_0"
|
|
bitfld.long 0x00 0. " MLOCK_12 ,Mlock_12" "Released,Held"
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_13_0,Host1X Sync MLOCK_13_0"
|
|
bitfld.long 0x00 0. " MLOCK_13 ,Mlock_13" "Released,Held"
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_14_0,Host1X Sync MLOCK_14_0"
|
|
bitfld.long 0x00 0. " MLOCK_14 ,Mlock_14" "Released,Held"
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_15_0,Host1X Sync MLOCK_15_0"
|
|
bitfld.long 0x00 0. " MLOCK_15 ,Mlock_15" "Released,Held"
|
|
textline " "
|
|
rgroup.long 0x340++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_0_0,Host1X Sync MLOCK Owner 0_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_0 ,Mlock owner chid 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_0 ,MLOCK CPU owns 0" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_0 ,MLOCK CH owns 0" "Not owned,Owned"
|
|
rgroup.long 0x344++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_1_0,Host1X Sync MLOCK Owner 1_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_1 ,Mlock owner chid 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_1 ,MLOCK CPU owns 1" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_1 ,MLOCK CH owns 1" "Not owned,Owned"
|
|
rgroup.long 0x348++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_2_0,Host1X Sync MLOCK Owner 2_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_2 ,Mlock owner chid 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_2 ,MLOCK CPU owns 2" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_2 ,MLOCK CH owns 2" "Not owned,Owned"
|
|
rgroup.long 0x34C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_3_0,Host1X Sync MLOCK Owner 3_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_3 ,Mlock owner chid 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_3 ,MLOCK CPU owns 3" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_3 ,MLOCK CH owns 3" "Not owned,Owned"
|
|
rgroup.long 0x350++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_4_0,Host1X Sync MLOCK Owner 4_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_4 ,Mlock owner chid 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_4 ,MLOCK CPU owns 4" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_4 ,MLOCK CH owns 4" "Not owned,Owned"
|
|
rgroup.long 0x354++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_5_0,Host1X Sync MLOCK Owner 5_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_5 ,Mlock owner chid 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_5 ,MLOCK CPU owns 5" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_5 ,MLOCK CH owns 5" "Not owned,Owned"
|
|
rgroup.long 0x358++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_6_0,Host1X Sync MLOCK Owner 6_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_6 ,Mlock owner chid 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_6 ,MLOCK CPU owns 6" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_6 ,MLOCK CH owns 6" "Not owned,Owned"
|
|
rgroup.long 0x35C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_7_0,Host1X Sync MLOCK Owner 7_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_7 ,Mlock owner chid 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_7 ,MLOCK CPU owns 7" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_7 ,MLOCK CH owns 7" "Not owned,Owned"
|
|
rgroup.long 0x360++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_8_0,Host1X Sync MLOCK Owner 8_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_8 ,Mlock owner chid 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_8 ,MLOCK CPU owns 8" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_8 ,MLOCK CH owns 8" "Not owned,Owned"
|
|
rgroup.long 0x364++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_9_0,Host1X Sync MLOCK Owner 9_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_9 ,Mlock owner chid 9" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_9 ,MLOCK CPU owns 9" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_9 ,MLOCK CH owns 9" "Not owned,Owned"
|
|
rgroup.long 0x368++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_10_0,Host1X Sync MLOCK Owner 10_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_10 ,Mlock owner chid 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_10 ,MLOCK CPU owns 10" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_10 ,MLOCK CH owns 10" "Not owned,Owned"
|
|
rgroup.long 0x36C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_11_0,Host1X Sync MLOCK Owner 11_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_11 ,Mlock owner chid 11" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_11 ,MLOCK CPU owns 11" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_11 ,MLOCK CH owns 11" "Not owned,Owned"
|
|
rgroup.long 0x370++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_12_0,Host1X Sync MLOCK Owner 12_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_12 ,Mlock owner chid 12" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_12 ,MLOCK CPU owns 12" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_12 ,MLOCK CH owns 12" "Not owned,Owned"
|
|
rgroup.long 0x374++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_13_0,Host1X Sync MLOCK Owner 13_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_13 ,Mlock owner chid 13" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_13 ,MLOCK CPU owns 13" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_13 ,MLOCK CH owns 13" "Not owned,Owned"
|
|
rgroup.long 0x378++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_14_0,Host1X Sync MLOCK Owner 14_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_14 ,Mlock owner chid 14" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_14 ,MLOCK CPU owns 14" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_14 ,MLOCK CH owns 14" "Not owned,Owned"
|
|
rgroup.long 0x37C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_15_0,Host1X Sync MLOCK Owner 15_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_15 ,Mlock owner chid 15" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_15 ,MLOCK CPU owns 15" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_15 ,MLOCK CH owns 15" "Not owned,Owned"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_ERROR_0_0,Host1X Sync Mlock Error 0_0"
|
|
bitfld.long 0x00 15. " MLOCK_ERROR_15 ,Mlock error 15" "No error,Error"
|
|
bitfld.long 0x00 14. " MLOCK_ERROR_14 ,Mlock error 14" "No error,Error"
|
|
bitfld.long 0x00 13. " MLOCK_ERROR_13 ,Mlock error 13" "No error,Error"
|
|
bitfld.long 0x00 12. " MLOCK_ERROR_12 ,Mlock error 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MLOCK_ERROR_11 ,Mlock error 11" "No error,Error"
|
|
bitfld.long 0x00 10. " MLOCK_ERROR_10 ,Mlock error 10" "No error,Error"
|
|
bitfld.long 0x00 9. " MLOCK_ERROR_9 ,Mlock error 9" "No error,Error"
|
|
bitfld.long 0x00 8. " MLOCK_ERROR_8 ,Mlock error 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MLOCK_ERROR_7 ,Mlock error 7" "No error,Error"
|
|
bitfld.long 0x00 6. " MLOCK_ERROR_6 ,Mlock error 6" "No error,Error"
|
|
bitfld.long 0x00 5. " MLOCK_ERROR_5 ,Mlock error 5" "No error,Error"
|
|
bitfld.long 0x00 4. " MLOCK_ERROR_4 ,Mlock error 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MLOCK_ERROR_3 ,Mlock error 3" "No error,Error"
|
|
bitfld.long 0x00 2. " MLOCK_ERROR_2 ,Mlock error 2" "No error,Error"
|
|
bitfld.long 0x00 1. " MLOCK_ERROR_1 ,Mlock error 1" "No error,Error"
|
|
bitfld.long 0x00 0. " MLOCK_ERROR_0 ,Mlock error 0" "No error,Error"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_0_0,Host1X Sync Syncpt Base 0_0"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_1_0,Host1X Sync Syncpt Base 1_0"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_2_0,Host1X Sync Syncpt Base 2_0"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_3_0,Host1X Sync Syncpt Base 3_0"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_4_0,Host1X Sync Syncpt Base 4_0"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_5_0,Host1X Sync Syncpt Base 5_0"
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_6_0,Host1X Sync Syncpt Base 6_0"
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_7_0,Host1X Sync Syncpt Base 7_0"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_8_0,Host1X Sync Syncpt Base 8_0"
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_9_0,Host1X Sync Syncpt Base 9_0"
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_10_0,Host1X Sync Syncpt Base 10_0"
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_11_0,Host1X Sync Syncpt Base 11_0"
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_12_0,Host1X Sync Syncpt Base 12_0"
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_13_0,Host1X Sync Syncpt Base 13_0"
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_14_0,Host1X Sync Syncpt Base 14_0"
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_15_0,Host1X Sync Syncpt Base 15_0"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_16_0,Host1X Sync Syncpt Base 16_0"
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_17_0,Host1X Sync Syncpt Base 17_0"
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_18_0,Host1X Sync Syncpt Base 18_0"
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_19_0,Host1X Sync Syncpt Base 19_0"
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_20_0,Host1X Sync Syncpt Base 20_0"
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_21_0,Host1X Sync Syncpt Base 21_0"
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_22_0,Host1X Sync Syncpt Base 22_0"
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_23_0,Host1X Sync Syncpt Base 23_0"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_24_0,Host1X Sync Syncpt Base 24_0"
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_25_0,Host1X Sync Syncpt Base 25_0"
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_26_0,Host1X Sync Syncpt Base 26_0"
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_27_0,Host1X Sync Syncpt Base 27_0"
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_28_0,Host1X Sync Syncpt Base 28_0"
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_29_0,Host1X Sync Syncpt Base 29_0"
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_30_0,Host1X Sync Syncpt Base 30_0"
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_31_0,Host1X Sync Syncpt Base 31_0"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_32_0,Host1X Sync Syncpt Base 32_0"
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_33_0,Host1X Sync Syncpt Base 33_0"
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_34_0,Host1X Sync Syncpt Base 34_0"
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_35_0,Host1X Sync Syncpt Base 35_0"
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_36_0,Host1X Sync Syncpt Base 36_0"
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_37_0,Host1X Sync Syncpt Base 37_0"
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_38_0,Host1X Sync Syncpt Base 38_0"
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_39_0,Host1X Sync Syncpt Base 39_0"
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_40_0,Host1X Sync Syncpt Base 40_0"
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_41_0,Host1X Sync Syncpt Base 41_0"
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_42_0,Host1X Sync Syncpt Base 42_0"
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_43_0,Host1X Sync Syncpt Base 43_0"
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_44_0,Host1X Sync Syncpt Base 44_0"
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_45_0,Host1X Sync Syncpt Base 45_0"
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_46_0,Host1X Sync Syncpt Base 46_0"
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_47_0,Host1X Sync Syncpt Base 47_0"
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_48_0,Host1X Sync Syncpt Base 48_0"
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_49_0,Host1X Sync Syncpt Base 49_0"
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_50_0,Host1X Sync Syncpt Base 50_0"
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_51_0,Host1X Sync Syncpt Base 51_0"
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_52_0,Host1X Sync Syncpt Base 52_0"
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_53_0,Host1X Sync Syncpt Base 53_0"
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_54_0,Host1X Sync Syncpt Base 54_0"
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_55_0,Host1X Sync Syncpt Base 55_0"
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_56_0,Host1X Sync Syncpt Base 56_0"
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_57_0,Host1X Sync Syncpt Base 57_0"
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_58_0,Host1X Sync Syncpt Base 58_0"
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_59_0,Host1X Sync Syncpt Base 59_0"
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_60_0,Host1X Sync Syncpt Base 60_0"
|
|
group.long 0x6F4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_61_0,Host1X Sync Syncpt Base 61_0"
|
|
group.long 0x6F8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_62_0,Host1X Sync Syncpt Base 62_0"
|
|
group.long 0x6FC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_63_0,Host1X Sync Syncpt Base 63_0"
|
|
tree.end
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 8"
|
|
base ad:0x50020000
|
|
width 27.
|
|
tree "Channel Registers"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CHANNEL_FIFOSTAT_0,Host1X Channel FIFOSTAT_0"
|
|
bitfld.long 0x00 31. " INDRDY ,Indicates that INDCOUNT == 0 so it should be OK to issue another read" "0,1"
|
|
bitfld.long 0x00 24.--28. " OUTFENTRIES ,Number of entries available for reading in this channel's output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " REGNUMEMPTY ,Register write/read FIFO free count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CFGATHER ,Indicates whether GATHER is active" "Idle,Busy"
|
|
bitfld.long 0x00 11. " CFEMPTY ,Indicates whether the command FIFO is empty" "Not empty,Empty"
|
|
hexmask.long.word 0x00 0.--10. 1. " CFNUMEMPTY ,Command FIFO free count"
|
|
if (((per.l(ad:0x50020000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type: Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long 0x00 2.--25. 0x04 " INDOFFSET ,Frame buffer address"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type:Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET ,Register offset"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
endif
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "CHANNEL_INDICT_0,Indirect Register Access Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDCOUNT ,Indcount"
|
|
line.long 0x04 "CHANNEL_IDDATA_0,Host1X Channel INDDATA_0"
|
|
line.long 0x08 "CHANNEL_RAISE_0,DMA And RAISE/REFCOUNT Functionality"
|
|
hexmask.long 0x08 2.--31. 1. " RAISE ,Channel's RAISE vector"
|
|
line.long 0x0C "CHANNEL_DMASTART_0,Host1X Channel DMSTART_0"
|
|
hexmask.long 0x0C 2.--31. 0x04 " DMASTART ,Cmdbuf frame buffer ofset"
|
|
line.long 0x10 "CHANNEL_DMAPUT_0, Host1X Channel DMAPUT_0"
|
|
hexmask.long 0x10 2.--31. 0x04 " DMAPUT ,Cmdbuf frame buffer offset"
|
|
rgroup.long 0x1C++0x0B
|
|
line.long 0x00 "CHANNEL_DMAGET_0,Host1X Channel DMAGET_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " DMAGET ,Cmdbuf frame buffer offset"
|
|
line.long 0x04 "CHANNEL_DMAEND_0 ,Host1X Channel DMAEND_0"
|
|
hexmask.long 0x04 2.--31. 0x04 " DMAEND ,Cmdbuf frame buffer offset"
|
|
line.long 0x08 "CHANNEL_DMACTRL_0,DMA Control Register"
|
|
bitfld.long 0x08 2. " DMAINITGET ,Reset GET pointer to the value of DMAPUT when DMAGETRST is asserted" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " DMAGETRST ,Reset GET pointer to 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " DMASTOP ,Stop DMA from fetching on this channel" "Run,Stop"
|
|
if (((per.l(ad:0x50020000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " INDOFFSET2 ,Frame buffer address"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID2 ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET2 ,Register offset"
|
|
endif
|
|
group.long 0x90++0x2B
|
|
line.long 0x00 "CHANNEL_TICKCOUNT_HI_0,Host1X Channel TICKCOUNT HI 0"
|
|
line.long 0x04 "CHANNEL_TICKCOUNT_LO_0,Host1X Channel TICKCOUNT LO 0"
|
|
line.long 0x08 "CHANNEL_CHANNELCTRL_0,Host1X Channel CHANNELCTRL_0"
|
|
bitfld.long 0x08 2. " KERNEL_FILTER_GBUFFER ,Enable setclass command filter for gather buffers" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ENABLETICKCNT ,Enable tick counter" "Disabled,Enabled"
|
|
line.long 0x0C "CHANNEL_PAYLOAD_0,Host1X Channel PAYLOAD_0"
|
|
line.long 0x10 "CHANNEL_STALLCTRL_0,Host1X Channel STALLCTRL_0"
|
|
bitfld.long 0x10 0. " ENABLE_CHANNEL_STALL ,Enable channel STALL" "Disabled,Enabled"
|
|
line.long 0x14 "CHANNEL_STALLCOUNT_HI_0,Host1X Channel STALLCOUNT Hi 0"
|
|
line.long 0x18 "CHANNEL_STALLCOUNT_LO_0,Host1X Channel STALLCOUNT Lo 0"
|
|
line.long 0x1C "CHANNEL_XFERCTRL_0,Host1X Channel XFERCTRL 0"
|
|
bitfld.long 0x1C 0. " ENABLE_CHANNEL_XFER ,Enable channel XFER" "Disabled,Enabled"
|
|
line.long 0x20 "CHANNEL_CHANNEL_XFER_HI_0,Host1X Channel XFER Hi 0"
|
|
line.long 0x24 "CHANNEL_CHANNEL_XFER_LO_0,Host1X Channel XFER Lo 0"
|
|
line.long 0x28 "CHANNEL_CHANNEL_SPARE_0,Host1x Channel SPARE 0"
|
|
hexmask.long.word 0x28 16.--31. 1. " CHANNEL_SPARE_HI ,Channel SPARE Hi"
|
|
hexmask.long.word 0x28 0.--15. 1. " CHANNEL_SPARE_LO ,CHannel SPARE Lo"
|
|
tree.end
|
|
; base (ad:0x50020000+0x2000) - ACTMON1(MSENC)
|
|
; base (ad:0x50020000+0x2040) - ACTMON2(VIC)
|
|
width 23.
|
|
base (ad:0x50020000+0x2100)
|
|
tree "SYNC (Synchronous Registers)"
|
|
sif CPUIS("TEGRAX1")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " VII2C_INT , VII2C interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOR1_INT ,SOR1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NVENC_INT ,NVENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " NVDEC_INT ,NVDEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 14. " NVJPG_INT ,NVJPG interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " TSECB_INT ,TSECB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " DPAUX1_INT ,DPAUX1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 4. " CPU_TZ_ILLEGAL_TZ_ACCESS_MASK ,Mask CPU_TZ_ILLEGAL_TZ_ACCESS" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 27. " VII2C_INT_C0MASK ,Interrupt mask for VII2C interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SOR1_INT_C0MASK ,Interrupt mask for SOR1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " NVENC_INT_C0MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " NVDEC_INT_C0MASK ,Interrupt mask for NVDEC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NVJPG_INT_C0MASK ,Interrupt mask for NVJPG interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " TSECB_INT_C0MASK ,Interrupt mask for TSECB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " DPAUX1_INT_C0MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 27. " VII2C_INT_C1MASK ,Interrupt mask for VII2C interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 22. " SOR1_INT_C1MASK ,Interrupt mask for SOR1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NVENC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " NVDEC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 14. " NVJPG_INT_C1MASK ,Interrupt mask for NVJPG interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " TSECB_INT_C1MASK ,Interrupt mask for TSECB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " DPAUX1_INT_C1MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " XBAR_TSEC_TIMEOUT_ID ,Id of the CPU which timed out and updated" "TSEC,XBAR"
|
|
eventfld.long 0x00 21. " WAIT_INT13 ,WAIT has completed on channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " WAIT_INT12 ,WAIT has completed on channel 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,Invalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " WAIT_INT13 ,WAIT interrupt mask 13" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " WAIT_INT12 ,WAIT interrupt mask 12" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 ACTMON interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 13. " CMDPP_ILLEGAL_OPCODE_INT13 ,CMPP 13 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 12. " CMDPP_ILLEGAL_OPCODE_INT12 ,CMPP 12 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " CMDPP_ILLEGAL_OPCODE_INTMASK13 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 12. " CMDPP_ILLEGAL_OPCODE_INTMASK12 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--13. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
wgroup.long 0xB0++0x0B
|
|
line.long 0x00 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x00 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x04 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x04 27. " VII2C_TEARDOWN ,VII2C teardown" "No action,Teardown"
|
|
bitfld.long 0x04 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x04 22. " SOR1_TEARDOWN ,SOR1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x04 19. " NVENC_TEARDOWN ,NVENC teardown" "No action,Teardown"
|
|
bitfld.long 0x04 18. " NVDEC_TEARDOWN ,NVEDC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 14. " NVJPG_TEARDOWN ,JVJPG teardown" "No action,Teardown"
|
|
bitfld.long 0x04 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " TSECB_TEARDOWN ,TSECB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DPAUX1_TEARDOWN ,DPAUX1 teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x47
|
|
line.long 0x00 "SYNC_DISPLAY_STATUS_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_STATUS_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_STATUS_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_STATUS_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_SOR1_STATUS_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,SOR1 currcl"
|
|
line.long 0x14 "SYNC_SOR_STATUS,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_STATUS_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_STATUS_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_STATUS_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_STATUS_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_NVENC_STATUS_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,NVENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_STATUS_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
line.long 0x34 "SYNC_NVDEC_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x34 16.--25. 1. " ISPB_CURRCL ,NVDEC currcl"
|
|
line.long 0x38 "SYNC_NVJPG_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x38 16.--25. 1. " ISPB_CURRCL ,NVJPG currcl"
|
|
line.long 0x3C "SYNC_VII2C_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x3C 16.--25. 1. " ISPB_CURRCL ,VII2C currcl"
|
|
line.long 0x40 "SYNC_DPAUX1_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x40 16.--25. 1. " ISPB_CURRCL ,DPAUX1 currcl"
|
|
line.long 0x44 "SYNC_TSECB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x44 16.--25. 1. " ISPB_CURRCL ,TSECB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 13. " HIPRI_CH13 ,HIPRI ch 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " HIPRI_CH12 ,HIPRI ch 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " MSENC_INT ,MSENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " HDMI_INT ,HDMi int " "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " MSENC_INT_C0MASK ,Interrupt mask for MSENC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " HDMI_INT_C0MASK ,Interrupt mask for HDMI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 19. " MSENC_INT_C1MASK ,Interrupt mask for MSENC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HDMI_INT_C1MASK ,Interrupt mask for HDMI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,INvalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " XBAR_TSEC_TIMEOUT_ID ,ID of the CPU which timed out and updated the timeout address" "Tsec,Xbar"
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 actmon interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 actmon interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--11. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
line.long 0x04 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x04 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x08 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x08 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
bitfld.long 0x08 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x08 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x08 19. " MSENC_TEARDOWN ,MSENC teardown" "No action,Teardown"
|
|
bitfld.long 0x08 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 10. " HDMI_TEARDOWN ,HDMI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x33
|
|
line.long 0x00 "SYNC_DISPLAY_Status_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_Status_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_Status_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_Status_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_HDMI_Status_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,HDMI currcl"
|
|
line.long 0x14 "SYNC_SOR_Status,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_Status_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_Status_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_Status_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_Status_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_MSENC_Status_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,MSENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_Status_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_Status_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
endif
|
|
width 23.
|
|
tree "MLOCK registers"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_0_0,Host1X Sync MLOCK_0_0"
|
|
bitfld.long 0x00 0. " MLOCK_0 ,Mlock_0" "Released,Held"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_1_0,Host1X Sync MLOCK_1_0"
|
|
bitfld.long 0x00 0. " MLOCK_1 ,Mlock_1" "Released,Held"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_2_0,Host1X Sync MLOCK_2_0"
|
|
bitfld.long 0x00 0. " MLOCK_2 ,Mlock_2" "Released,Held"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_3_0,Host1X Sync MLOCK_3_0"
|
|
bitfld.long 0x00 0. " MLOCK_3 ,Mlock_3" "Released,Held"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_4_0,Host1X Sync MLOCK_4_0"
|
|
bitfld.long 0x00 0. " MLOCK_4 ,Mlock_4" "Released,Held"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_5_0,Host1X Sync MLOCK_5_0"
|
|
bitfld.long 0x00 0. " MLOCK_5 ,Mlock_5" "Released,Held"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_6_0,Host1X Sync MLOCK_6_0"
|
|
bitfld.long 0x00 0. " MLOCK_6 ,Mlock_6" "Released,Held"
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_7_0,Host1X Sync MLOCK_7_0"
|
|
bitfld.long 0x00 0. " MLOCK_7 ,Mlock_7" "Released,Held"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_8_0,Host1X Sync MLOCK_8_0"
|
|
bitfld.long 0x00 0. " MLOCK_8 ,Mlock_8" "Released,Held"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_9_0,Host1X Sync MLOCK_9_0"
|
|
bitfld.long 0x00 0. " MLOCK_9 ,Mlock_9" "Released,Held"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_10_0,Host1X Sync MLOCK_10_0"
|
|
bitfld.long 0x00 0. " MLOCK_10 ,Mlock_10" "Released,Held"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_11_0,Host1X Sync MLOCK_11_0"
|
|
bitfld.long 0x00 0. " MLOCK_11 ,Mlock_11" "Released,Held"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_12_0,Host1X Sync MLOCK_12_0"
|
|
bitfld.long 0x00 0. " MLOCK_12 ,Mlock_12" "Released,Held"
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_13_0,Host1X Sync MLOCK_13_0"
|
|
bitfld.long 0x00 0. " MLOCK_13 ,Mlock_13" "Released,Held"
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_14_0,Host1X Sync MLOCK_14_0"
|
|
bitfld.long 0x00 0. " MLOCK_14 ,Mlock_14" "Released,Held"
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_15_0,Host1X Sync MLOCK_15_0"
|
|
bitfld.long 0x00 0. " MLOCK_15 ,Mlock_15" "Released,Held"
|
|
textline " "
|
|
rgroup.long 0x340++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_0_0,Host1X Sync MLOCK Owner 0_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_0 ,Mlock owner chid 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_0 ,MLOCK CPU owns 0" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_0 ,MLOCK CH owns 0" "Not owned,Owned"
|
|
rgroup.long 0x344++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_1_0,Host1X Sync MLOCK Owner 1_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_1 ,Mlock owner chid 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_1 ,MLOCK CPU owns 1" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_1 ,MLOCK CH owns 1" "Not owned,Owned"
|
|
rgroup.long 0x348++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_2_0,Host1X Sync MLOCK Owner 2_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_2 ,Mlock owner chid 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_2 ,MLOCK CPU owns 2" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_2 ,MLOCK CH owns 2" "Not owned,Owned"
|
|
rgroup.long 0x34C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_3_0,Host1X Sync MLOCK Owner 3_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_3 ,Mlock owner chid 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_3 ,MLOCK CPU owns 3" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_3 ,MLOCK CH owns 3" "Not owned,Owned"
|
|
rgroup.long 0x350++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_4_0,Host1X Sync MLOCK Owner 4_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_4 ,Mlock owner chid 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_4 ,MLOCK CPU owns 4" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_4 ,MLOCK CH owns 4" "Not owned,Owned"
|
|
rgroup.long 0x354++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_5_0,Host1X Sync MLOCK Owner 5_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_5 ,Mlock owner chid 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_5 ,MLOCK CPU owns 5" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_5 ,MLOCK CH owns 5" "Not owned,Owned"
|
|
rgroup.long 0x358++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_6_0,Host1X Sync MLOCK Owner 6_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_6 ,Mlock owner chid 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_6 ,MLOCK CPU owns 6" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_6 ,MLOCK CH owns 6" "Not owned,Owned"
|
|
rgroup.long 0x35C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_7_0,Host1X Sync MLOCK Owner 7_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_7 ,Mlock owner chid 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_7 ,MLOCK CPU owns 7" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_7 ,MLOCK CH owns 7" "Not owned,Owned"
|
|
rgroup.long 0x360++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_8_0,Host1X Sync MLOCK Owner 8_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_8 ,Mlock owner chid 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_8 ,MLOCK CPU owns 8" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_8 ,MLOCK CH owns 8" "Not owned,Owned"
|
|
rgroup.long 0x364++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_9_0,Host1X Sync MLOCK Owner 9_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_9 ,Mlock owner chid 9" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_9 ,MLOCK CPU owns 9" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_9 ,MLOCK CH owns 9" "Not owned,Owned"
|
|
rgroup.long 0x368++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_10_0,Host1X Sync MLOCK Owner 10_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_10 ,Mlock owner chid 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_10 ,MLOCK CPU owns 10" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_10 ,MLOCK CH owns 10" "Not owned,Owned"
|
|
rgroup.long 0x36C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_11_0,Host1X Sync MLOCK Owner 11_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_11 ,Mlock owner chid 11" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_11 ,MLOCK CPU owns 11" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_11 ,MLOCK CH owns 11" "Not owned,Owned"
|
|
rgroup.long 0x370++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_12_0,Host1X Sync MLOCK Owner 12_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_12 ,Mlock owner chid 12" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_12 ,MLOCK CPU owns 12" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_12 ,MLOCK CH owns 12" "Not owned,Owned"
|
|
rgroup.long 0x374++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_13_0,Host1X Sync MLOCK Owner 13_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_13 ,Mlock owner chid 13" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_13 ,MLOCK CPU owns 13" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_13 ,MLOCK CH owns 13" "Not owned,Owned"
|
|
rgroup.long 0x378++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_14_0,Host1X Sync MLOCK Owner 14_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_14 ,Mlock owner chid 14" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_14 ,MLOCK CPU owns 14" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_14 ,MLOCK CH owns 14" "Not owned,Owned"
|
|
rgroup.long 0x37C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_15_0,Host1X Sync MLOCK Owner 15_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_15 ,Mlock owner chid 15" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_15 ,MLOCK CPU owns 15" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_15 ,MLOCK CH owns 15" "Not owned,Owned"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_ERROR_0_0,Host1X Sync Mlock Error 0_0"
|
|
bitfld.long 0x00 15. " MLOCK_ERROR_15 ,Mlock error 15" "No error,Error"
|
|
bitfld.long 0x00 14. " MLOCK_ERROR_14 ,Mlock error 14" "No error,Error"
|
|
bitfld.long 0x00 13. " MLOCK_ERROR_13 ,Mlock error 13" "No error,Error"
|
|
bitfld.long 0x00 12. " MLOCK_ERROR_12 ,Mlock error 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MLOCK_ERROR_11 ,Mlock error 11" "No error,Error"
|
|
bitfld.long 0x00 10. " MLOCK_ERROR_10 ,Mlock error 10" "No error,Error"
|
|
bitfld.long 0x00 9. " MLOCK_ERROR_9 ,Mlock error 9" "No error,Error"
|
|
bitfld.long 0x00 8. " MLOCK_ERROR_8 ,Mlock error 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MLOCK_ERROR_7 ,Mlock error 7" "No error,Error"
|
|
bitfld.long 0x00 6. " MLOCK_ERROR_6 ,Mlock error 6" "No error,Error"
|
|
bitfld.long 0x00 5. " MLOCK_ERROR_5 ,Mlock error 5" "No error,Error"
|
|
bitfld.long 0x00 4. " MLOCK_ERROR_4 ,Mlock error 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MLOCK_ERROR_3 ,Mlock error 3" "No error,Error"
|
|
bitfld.long 0x00 2. " MLOCK_ERROR_2 ,Mlock error 2" "No error,Error"
|
|
bitfld.long 0x00 1. " MLOCK_ERROR_1 ,Mlock error 1" "No error,Error"
|
|
bitfld.long 0x00 0. " MLOCK_ERROR_0 ,Mlock error 0" "No error,Error"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_0_0,Host1X Sync Syncpt Base 0_0"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_1_0,Host1X Sync Syncpt Base 1_0"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_2_0,Host1X Sync Syncpt Base 2_0"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_3_0,Host1X Sync Syncpt Base 3_0"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_4_0,Host1X Sync Syncpt Base 4_0"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_5_0,Host1X Sync Syncpt Base 5_0"
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_6_0,Host1X Sync Syncpt Base 6_0"
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_7_0,Host1X Sync Syncpt Base 7_0"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_8_0,Host1X Sync Syncpt Base 8_0"
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_9_0,Host1X Sync Syncpt Base 9_0"
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_10_0,Host1X Sync Syncpt Base 10_0"
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_11_0,Host1X Sync Syncpt Base 11_0"
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_12_0,Host1X Sync Syncpt Base 12_0"
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_13_0,Host1X Sync Syncpt Base 13_0"
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_14_0,Host1X Sync Syncpt Base 14_0"
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_15_0,Host1X Sync Syncpt Base 15_0"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_16_0,Host1X Sync Syncpt Base 16_0"
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_17_0,Host1X Sync Syncpt Base 17_0"
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_18_0,Host1X Sync Syncpt Base 18_0"
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_19_0,Host1X Sync Syncpt Base 19_0"
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_20_0,Host1X Sync Syncpt Base 20_0"
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_21_0,Host1X Sync Syncpt Base 21_0"
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_22_0,Host1X Sync Syncpt Base 22_0"
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_23_0,Host1X Sync Syncpt Base 23_0"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_24_0,Host1X Sync Syncpt Base 24_0"
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_25_0,Host1X Sync Syncpt Base 25_0"
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_26_0,Host1X Sync Syncpt Base 26_0"
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_27_0,Host1X Sync Syncpt Base 27_0"
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_28_0,Host1X Sync Syncpt Base 28_0"
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_29_0,Host1X Sync Syncpt Base 29_0"
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_30_0,Host1X Sync Syncpt Base 30_0"
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_31_0,Host1X Sync Syncpt Base 31_0"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_32_0,Host1X Sync Syncpt Base 32_0"
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_33_0,Host1X Sync Syncpt Base 33_0"
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_34_0,Host1X Sync Syncpt Base 34_0"
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_35_0,Host1X Sync Syncpt Base 35_0"
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_36_0,Host1X Sync Syncpt Base 36_0"
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_37_0,Host1X Sync Syncpt Base 37_0"
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_38_0,Host1X Sync Syncpt Base 38_0"
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_39_0,Host1X Sync Syncpt Base 39_0"
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_40_0,Host1X Sync Syncpt Base 40_0"
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_41_0,Host1X Sync Syncpt Base 41_0"
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_42_0,Host1X Sync Syncpt Base 42_0"
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_43_0,Host1X Sync Syncpt Base 43_0"
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_44_0,Host1X Sync Syncpt Base 44_0"
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_45_0,Host1X Sync Syncpt Base 45_0"
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_46_0,Host1X Sync Syncpt Base 46_0"
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_47_0,Host1X Sync Syncpt Base 47_0"
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_48_0,Host1X Sync Syncpt Base 48_0"
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_49_0,Host1X Sync Syncpt Base 49_0"
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_50_0,Host1X Sync Syncpt Base 50_0"
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_51_0,Host1X Sync Syncpt Base 51_0"
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_52_0,Host1X Sync Syncpt Base 52_0"
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_53_0,Host1X Sync Syncpt Base 53_0"
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_54_0,Host1X Sync Syncpt Base 54_0"
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_55_0,Host1X Sync Syncpt Base 55_0"
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_56_0,Host1X Sync Syncpt Base 56_0"
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_57_0,Host1X Sync Syncpt Base 57_0"
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_58_0,Host1X Sync Syncpt Base 58_0"
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_59_0,Host1X Sync Syncpt Base 59_0"
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_60_0,Host1X Sync Syncpt Base 60_0"
|
|
group.long 0x6F4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_61_0,Host1X Sync Syncpt Base 61_0"
|
|
group.long 0x6F8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_62_0,Host1X Sync Syncpt Base 62_0"
|
|
group.long 0x6FC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_63_0,Host1X Sync Syncpt Base 63_0"
|
|
tree.end
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 9"
|
|
base ad:0x50024000
|
|
width 27.
|
|
tree "Channel Registers"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CHANNEL_FIFOSTAT_0,Host1X Channel FIFOSTAT_0"
|
|
bitfld.long 0x00 31. " INDRDY ,Indicates that INDCOUNT == 0 so it should be OK to issue another read" "0,1"
|
|
bitfld.long 0x00 24.--28. " OUTFENTRIES ,Number of entries available for reading in this channel's output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " REGNUMEMPTY ,Register write/read FIFO free count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CFGATHER ,Indicates whether GATHER is active" "Idle,Busy"
|
|
bitfld.long 0x00 11. " CFEMPTY ,Indicates whether the command FIFO is empty" "Not empty,Empty"
|
|
hexmask.long.word 0x00 0.--10. 1. " CFNUMEMPTY ,Command FIFO free count"
|
|
if (((per.l(ad:0x50024000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type: Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long 0x00 2.--25. 0x04 " INDOFFSET ,Frame buffer address"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type:Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET ,Register offset"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
endif
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "CHANNEL_INDICT_0,Indirect Register Access Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDCOUNT ,Indcount"
|
|
line.long 0x04 "CHANNEL_IDDATA_0,Host1X Channel INDDATA_0"
|
|
line.long 0x08 "CHANNEL_RAISE_0,DMA And RAISE/REFCOUNT Functionality"
|
|
hexmask.long 0x08 2.--31. 1. " RAISE ,Channel's RAISE vector"
|
|
line.long 0x0C "CHANNEL_DMASTART_0,Host1X Channel DMSTART_0"
|
|
hexmask.long 0x0C 2.--31. 0x04 " DMASTART ,Cmdbuf frame buffer ofset"
|
|
line.long 0x10 "CHANNEL_DMAPUT_0, Host1X Channel DMAPUT_0"
|
|
hexmask.long 0x10 2.--31. 0x04 " DMAPUT ,Cmdbuf frame buffer offset"
|
|
rgroup.long 0x1C++0x0B
|
|
line.long 0x00 "CHANNEL_DMAGET_0,Host1X Channel DMAGET_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " DMAGET ,Cmdbuf frame buffer offset"
|
|
line.long 0x04 "CHANNEL_DMAEND_0 ,Host1X Channel DMAEND_0"
|
|
hexmask.long 0x04 2.--31. 0x04 " DMAEND ,Cmdbuf frame buffer offset"
|
|
line.long 0x08 "CHANNEL_DMACTRL_0,DMA Control Register"
|
|
bitfld.long 0x08 2. " DMAINITGET ,Reset GET pointer to the value of DMAPUT when DMAGETRST is asserted" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " DMAGETRST ,Reset GET pointer to 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " DMASTOP ,Stop DMA from fetching on this channel" "Run,Stop"
|
|
if (((per.l(ad:0x50024000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " INDOFFSET2 ,Frame buffer address"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID2 ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET2 ,Register offset"
|
|
endif
|
|
group.long 0x90++0x2B
|
|
line.long 0x00 "CHANNEL_TICKCOUNT_HI_0,Host1X Channel TICKCOUNT HI 0"
|
|
line.long 0x04 "CHANNEL_TICKCOUNT_LO_0,Host1X Channel TICKCOUNT LO 0"
|
|
line.long 0x08 "CHANNEL_CHANNELCTRL_0,Host1X Channel CHANNELCTRL_0"
|
|
bitfld.long 0x08 2. " KERNEL_FILTER_GBUFFER ,Enable setclass command filter for gather buffers" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ENABLETICKCNT ,Enable tick counter" "Disabled,Enabled"
|
|
line.long 0x0C "CHANNEL_PAYLOAD_0,Host1X Channel PAYLOAD_0"
|
|
line.long 0x10 "CHANNEL_STALLCTRL_0,Host1X Channel STALLCTRL_0"
|
|
bitfld.long 0x10 0. " ENABLE_CHANNEL_STALL ,Enable channel STALL" "Disabled,Enabled"
|
|
line.long 0x14 "CHANNEL_STALLCOUNT_HI_0,Host1X Channel STALLCOUNT Hi 0"
|
|
line.long 0x18 "CHANNEL_STALLCOUNT_LO_0,Host1X Channel STALLCOUNT Lo 0"
|
|
line.long 0x1C "CHANNEL_XFERCTRL_0,Host1X Channel XFERCTRL 0"
|
|
bitfld.long 0x1C 0. " ENABLE_CHANNEL_XFER ,Enable channel XFER" "Disabled,Enabled"
|
|
line.long 0x20 "CHANNEL_CHANNEL_XFER_HI_0,Host1X Channel XFER Hi 0"
|
|
line.long 0x24 "CHANNEL_CHANNEL_XFER_LO_0,Host1X Channel XFER Lo 0"
|
|
line.long 0x28 "CHANNEL_CHANNEL_SPARE_0,Host1x Channel SPARE 0"
|
|
hexmask.long.word 0x28 16.--31. 1. " CHANNEL_SPARE_HI ,Channel SPARE Hi"
|
|
hexmask.long.word 0x28 0.--15. 1. " CHANNEL_SPARE_LO ,CHannel SPARE Lo"
|
|
tree.end
|
|
; base (ad:0x50024000+0x2000) - ACTMON1(MSENC)
|
|
; base (ad:0x50024000+0x2040) - ACTMON2(VIC)
|
|
width 23.
|
|
base (ad:0x50024000+0x2100)
|
|
tree "SYNC (Synchronous Registers)"
|
|
sif CPUIS("TEGRAX1")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " VII2C_INT , VII2C interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOR1_INT ,SOR1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NVENC_INT ,NVENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " NVDEC_INT ,NVDEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 14. " NVJPG_INT ,NVJPG interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " TSECB_INT ,TSECB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " DPAUX1_INT ,DPAUX1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 4. " CPU_TZ_ILLEGAL_TZ_ACCESS_MASK ,Mask CPU_TZ_ILLEGAL_TZ_ACCESS" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 27. " VII2C_INT_C0MASK ,Interrupt mask for VII2C interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SOR1_INT_C0MASK ,Interrupt mask for SOR1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " NVENC_INT_C0MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " NVDEC_INT_C0MASK ,Interrupt mask for NVDEC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NVJPG_INT_C0MASK ,Interrupt mask for NVJPG interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " TSECB_INT_C0MASK ,Interrupt mask for TSECB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " DPAUX1_INT_C0MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 27. " VII2C_INT_C1MASK ,Interrupt mask for VII2C interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 22. " SOR1_INT_C1MASK ,Interrupt mask for SOR1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NVENC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " NVDEC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 14. " NVJPG_INT_C1MASK ,Interrupt mask for NVJPG interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " TSECB_INT_C1MASK ,Interrupt mask for TSECB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " DPAUX1_INT_C1MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " XBAR_TSEC_TIMEOUT_ID ,Id of the CPU which timed out and updated" "TSEC,XBAR"
|
|
eventfld.long 0x00 21. " WAIT_INT13 ,WAIT has completed on channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " WAIT_INT12 ,WAIT has completed on channel 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,Invalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " WAIT_INT13 ,WAIT interrupt mask 13" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " WAIT_INT12 ,WAIT interrupt mask 12" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 ACTMON interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 13. " CMDPP_ILLEGAL_OPCODE_INT13 ,CMPP 13 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 12. " CMDPP_ILLEGAL_OPCODE_INT12 ,CMPP 12 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " CMDPP_ILLEGAL_OPCODE_INTMASK13 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 12. " CMDPP_ILLEGAL_OPCODE_INTMASK12 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--13. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
wgroup.long 0xB0++0x0B
|
|
line.long 0x00 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x00 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x04 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x04 27. " VII2C_TEARDOWN ,VII2C teardown" "No action,Teardown"
|
|
bitfld.long 0x04 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x04 22. " SOR1_TEARDOWN ,SOR1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x04 19. " NVENC_TEARDOWN ,NVENC teardown" "No action,Teardown"
|
|
bitfld.long 0x04 18. " NVDEC_TEARDOWN ,NVEDC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 14. " NVJPG_TEARDOWN ,JVJPG teardown" "No action,Teardown"
|
|
bitfld.long 0x04 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " TSECB_TEARDOWN ,TSECB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DPAUX1_TEARDOWN ,DPAUX1 teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x47
|
|
line.long 0x00 "SYNC_DISPLAY_STATUS_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_STATUS_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_STATUS_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_STATUS_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_SOR1_STATUS_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,SOR1 currcl"
|
|
line.long 0x14 "SYNC_SOR_STATUS,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_STATUS_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_STATUS_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_STATUS_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_STATUS_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_NVENC_STATUS_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,NVENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_STATUS_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
line.long 0x34 "SYNC_NVDEC_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x34 16.--25. 1. " ISPB_CURRCL ,NVDEC currcl"
|
|
line.long 0x38 "SYNC_NVJPG_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x38 16.--25. 1. " ISPB_CURRCL ,NVJPG currcl"
|
|
line.long 0x3C "SYNC_VII2C_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x3C 16.--25. 1. " ISPB_CURRCL ,VII2C currcl"
|
|
line.long 0x40 "SYNC_DPAUX1_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x40 16.--25. 1. " ISPB_CURRCL ,DPAUX1 currcl"
|
|
line.long 0x44 "SYNC_TSECB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x44 16.--25. 1. " ISPB_CURRCL ,TSECB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
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|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
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|
group.long 0x1B0++0x0F
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|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
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|
bitfld.long 0x00 13. " HIPRI_CH13 ,HIPRI ch 13" "Disabled,Enabled"
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|
bitfld.long 0x00 12. " HIPRI_CH12 ,HIPRI ch 12" "Disabled,Enabled"
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|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
textline " "
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|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
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|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
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|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
textline " "
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|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
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|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
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|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
textline " "
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|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
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|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
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|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
textline " "
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|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
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|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
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|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
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|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
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|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
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|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
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|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
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|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
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|
rgroup.long 0x1C0++0x07
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|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
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|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
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|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
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|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
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|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
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|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
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bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
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|
bitfld.long 0x00 19. " MSENC_INT ,MSENC interrupt status" "Not pending,Pending"
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|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " HDMI_INT ,HDMi int " "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
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|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " MSENC_INT_C0MASK ,Interrupt mask for MSENC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " HDMI_INT_C0MASK ,Interrupt mask for HDMI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 19. " MSENC_INT_C1MASK ,Interrupt mask for MSENC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HDMI_INT_C1MASK ,Interrupt mask for HDMI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,INvalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " XBAR_TSEC_TIMEOUT_ID ,ID of the CPU which timed out and updated the timeout address" "Tsec,Xbar"
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 actmon interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 actmon interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--11. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
line.long 0x04 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x04 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x08 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x08 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
bitfld.long 0x08 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x08 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x08 19. " MSENC_TEARDOWN ,MSENC teardown" "No action,Teardown"
|
|
bitfld.long 0x08 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 10. " HDMI_TEARDOWN ,HDMI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x33
|
|
line.long 0x00 "SYNC_DISPLAY_Status_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_Status_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_Status_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_Status_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_HDMI_Status_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,HDMI currcl"
|
|
line.long 0x14 "SYNC_SOR_Status,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_Status_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_Status_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_Status_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_Status_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_MSENC_Status_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,MSENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_Status_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_Status_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
endif
|
|
width 23.
|
|
tree "MLOCK registers"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_0_0,Host1X Sync MLOCK_0_0"
|
|
bitfld.long 0x00 0. " MLOCK_0 ,Mlock_0" "Released,Held"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_1_0,Host1X Sync MLOCK_1_0"
|
|
bitfld.long 0x00 0. " MLOCK_1 ,Mlock_1" "Released,Held"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_2_0,Host1X Sync MLOCK_2_0"
|
|
bitfld.long 0x00 0. " MLOCK_2 ,Mlock_2" "Released,Held"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_3_0,Host1X Sync MLOCK_3_0"
|
|
bitfld.long 0x00 0. " MLOCK_3 ,Mlock_3" "Released,Held"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_4_0,Host1X Sync MLOCK_4_0"
|
|
bitfld.long 0x00 0. " MLOCK_4 ,Mlock_4" "Released,Held"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_5_0,Host1X Sync MLOCK_5_0"
|
|
bitfld.long 0x00 0. " MLOCK_5 ,Mlock_5" "Released,Held"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_6_0,Host1X Sync MLOCK_6_0"
|
|
bitfld.long 0x00 0. " MLOCK_6 ,Mlock_6" "Released,Held"
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_7_0,Host1X Sync MLOCK_7_0"
|
|
bitfld.long 0x00 0. " MLOCK_7 ,Mlock_7" "Released,Held"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_8_0,Host1X Sync MLOCK_8_0"
|
|
bitfld.long 0x00 0. " MLOCK_8 ,Mlock_8" "Released,Held"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_9_0,Host1X Sync MLOCK_9_0"
|
|
bitfld.long 0x00 0. " MLOCK_9 ,Mlock_9" "Released,Held"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_10_0,Host1X Sync MLOCK_10_0"
|
|
bitfld.long 0x00 0. " MLOCK_10 ,Mlock_10" "Released,Held"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_11_0,Host1X Sync MLOCK_11_0"
|
|
bitfld.long 0x00 0. " MLOCK_11 ,Mlock_11" "Released,Held"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_12_0,Host1X Sync MLOCK_12_0"
|
|
bitfld.long 0x00 0. " MLOCK_12 ,Mlock_12" "Released,Held"
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_13_0,Host1X Sync MLOCK_13_0"
|
|
bitfld.long 0x00 0. " MLOCK_13 ,Mlock_13" "Released,Held"
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_14_0,Host1X Sync MLOCK_14_0"
|
|
bitfld.long 0x00 0. " MLOCK_14 ,Mlock_14" "Released,Held"
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_15_0,Host1X Sync MLOCK_15_0"
|
|
bitfld.long 0x00 0. " MLOCK_15 ,Mlock_15" "Released,Held"
|
|
textline " "
|
|
rgroup.long 0x340++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_0_0,Host1X Sync MLOCK Owner 0_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_0 ,Mlock owner chid 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_0 ,MLOCK CPU owns 0" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_0 ,MLOCK CH owns 0" "Not owned,Owned"
|
|
rgroup.long 0x344++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_1_0,Host1X Sync MLOCK Owner 1_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_1 ,Mlock owner chid 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_1 ,MLOCK CPU owns 1" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_1 ,MLOCK CH owns 1" "Not owned,Owned"
|
|
rgroup.long 0x348++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_2_0,Host1X Sync MLOCK Owner 2_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_2 ,Mlock owner chid 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_2 ,MLOCK CPU owns 2" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_2 ,MLOCK CH owns 2" "Not owned,Owned"
|
|
rgroup.long 0x34C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_3_0,Host1X Sync MLOCK Owner 3_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_3 ,Mlock owner chid 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_3 ,MLOCK CPU owns 3" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_3 ,MLOCK CH owns 3" "Not owned,Owned"
|
|
rgroup.long 0x350++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_4_0,Host1X Sync MLOCK Owner 4_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_4 ,Mlock owner chid 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_4 ,MLOCK CPU owns 4" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_4 ,MLOCK CH owns 4" "Not owned,Owned"
|
|
rgroup.long 0x354++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_5_0,Host1X Sync MLOCK Owner 5_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_5 ,Mlock owner chid 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_5 ,MLOCK CPU owns 5" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_5 ,MLOCK CH owns 5" "Not owned,Owned"
|
|
rgroup.long 0x358++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_6_0,Host1X Sync MLOCK Owner 6_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_6 ,Mlock owner chid 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_6 ,MLOCK CPU owns 6" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_6 ,MLOCK CH owns 6" "Not owned,Owned"
|
|
rgroup.long 0x35C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_7_0,Host1X Sync MLOCK Owner 7_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_7 ,Mlock owner chid 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_7 ,MLOCK CPU owns 7" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_7 ,MLOCK CH owns 7" "Not owned,Owned"
|
|
rgroup.long 0x360++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_8_0,Host1X Sync MLOCK Owner 8_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_8 ,Mlock owner chid 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_8 ,MLOCK CPU owns 8" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_8 ,MLOCK CH owns 8" "Not owned,Owned"
|
|
rgroup.long 0x364++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_9_0,Host1X Sync MLOCK Owner 9_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_9 ,Mlock owner chid 9" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_9 ,MLOCK CPU owns 9" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_9 ,MLOCK CH owns 9" "Not owned,Owned"
|
|
rgroup.long 0x368++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_10_0,Host1X Sync MLOCK Owner 10_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_10 ,Mlock owner chid 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_10 ,MLOCK CPU owns 10" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_10 ,MLOCK CH owns 10" "Not owned,Owned"
|
|
rgroup.long 0x36C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_11_0,Host1X Sync MLOCK Owner 11_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_11 ,Mlock owner chid 11" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_11 ,MLOCK CPU owns 11" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_11 ,MLOCK CH owns 11" "Not owned,Owned"
|
|
rgroup.long 0x370++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_12_0,Host1X Sync MLOCK Owner 12_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_12 ,Mlock owner chid 12" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_12 ,MLOCK CPU owns 12" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_12 ,MLOCK CH owns 12" "Not owned,Owned"
|
|
rgroup.long 0x374++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_13_0,Host1X Sync MLOCK Owner 13_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_13 ,Mlock owner chid 13" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_13 ,MLOCK CPU owns 13" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_13 ,MLOCK CH owns 13" "Not owned,Owned"
|
|
rgroup.long 0x378++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_14_0,Host1X Sync MLOCK Owner 14_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_14 ,Mlock owner chid 14" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_14 ,MLOCK CPU owns 14" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_14 ,MLOCK CH owns 14" "Not owned,Owned"
|
|
rgroup.long 0x37C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_15_0,Host1X Sync MLOCK Owner 15_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_15 ,Mlock owner chid 15" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_15 ,MLOCK CPU owns 15" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_15 ,MLOCK CH owns 15" "Not owned,Owned"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_ERROR_0_0,Host1X Sync Mlock Error 0_0"
|
|
bitfld.long 0x00 15. " MLOCK_ERROR_15 ,Mlock error 15" "No error,Error"
|
|
bitfld.long 0x00 14. " MLOCK_ERROR_14 ,Mlock error 14" "No error,Error"
|
|
bitfld.long 0x00 13. " MLOCK_ERROR_13 ,Mlock error 13" "No error,Error"
|
|
bitfld.long 0x00 12. " MLOCK_ERROR_12 ,Mlock error 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MLOCK_ERROR_11 ,Mlock error 11" "No error,Error"
|
|
bitfld.long 0x00 10. " MLOCK_ERROR_10 ,Mlock error 10" "No error,Error"
|
|
bitfld.long 0x00 9. " MLOCK_ERROR_9 ,Mlock error 9" "No error,Error"
|
|
bitfld.long 0x00 8. " MLOCK_ERROR_8 ,Mlock error 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MLOCK_ERROR_7 ,Mlock error 7" "No error,Error"
|
|
bitfld.long 0x00 6. " MLOCK_ERROR_6 ,Mlock error 6" "No error,Error"
|
|
bitfld.long 0x00 5. " MLOCK_ERROR_5 ,Mlock error 5" "No error,Error"
|
|
bitfld.long 0x00 4. " MLOCK_ERROR_4 ,Mlock error 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MLOCK_ERROR_3 ,Mlock error 3" "No error,Error"
|
|
bitfld.long 0x00 2. " MLOCK_ERROR_2 ,Mlock error 2" "No error,Error"
|
|
bitfld.long 0x00 1. " MLOCK_ERROR_1 ,Mlock error 1" "No error,Error"
|
|
bitfld.long 0x00 0. " MLOCK_ERROR_0 ,Mlock error 0" "No error,Error"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_0_0,Host1X Sync Syncpt Base 0_0"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_1_0,Host1X Sync Syncpt Base 1_0"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_2_0,Host1X Sync Syncpt Base 2_0"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_3_0,Host1X Sync Syncpt Base 3_0"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_4_0,Host1X Sync Syncpt Base 4_0"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_5_0,Host1X Sync Syncpt Base 5_0"
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_6_0,Host1X Sync Syncpt Base 6_0"
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_7_0,Host1X Sync Syncpt Base 7_0"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_8_0,Host1X Sync Syncpt Base 8_0"
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_9_0,Host1X Sync Syncpt Base 9_0"
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_10_0,Host1X Sync Syncpt Base 10_0"
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_11_0,Host1X Sync Syncpt Base 11_0"
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_12_0,Host1X Sync Syncpt Base 12_0"
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_13_0,Host1X Sync Syncpt Base 13_0"
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_14_0,Host1X Sync Syncpt Base 14_0"
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_15_0,Host1X Sync Syncpt Base 15_0"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_16_0,Host1X Sync Syncpt Base 16_0"
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_17_0,Host1X Sync Syncpt Base 17_0"
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_18_0,Host1X Sync Syncpt Base 18_0"
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_19_0,Host1X Sync Syncpt Base 19_0"
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_20_0,Host1X Sync Syncpt Base 20_0"
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_21_0,Host1X Sync Syncpt Base 21_0"
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_22_0,Host1X Sync Syncpt Base 22_0"
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_23_0,Host1X Sync Syncpt Base 23_0"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_24_0,Host1X Sync Syncpt Base 24_0"
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_25_0,Host1X Sync Syncpt Base 25_0"
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_26_0,Host1X Sync Syncpt Base 26_0"
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_27_0,Host1X Sync Syncpt Base 27_0"
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_28_0,Host1X Sync Syncpt Base 28_0"
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_29_0,Host1X Sync Syncpt Base 29_0"
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_30_0,Host1X Sync Syncpt Base 30_0"
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_31_0,Host1X Sync Syncpt Base 31_0"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_32_0,Host1X Sync Syncpt Base 32_0"
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_33_0,Host1X Sync Syncpt Base 33_0"
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_34_0,Host1X Sync Syncpt Base 34_0"
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_35_0,Host1X Sync Syncpt Base 35_0"
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_36_0,Host1X Sync Syncpt Base 36_0"
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_37_0,Host1X Sync Syncpt Base 37_0"
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_38_0,Host1X Sync Syncpt Base 38_0"
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_39_0,Host1X Sync Syncpt Base 39_0"
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_40_0,Host1X Sync Syncpt Base 40_0"
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_41_0,Host1X Sync Syncpt Base 41_0"
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_42_0,Host1X Sync Syncpt Base 42_0"
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_43_0,Host1X Sync Syncpt Base 43_0"
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_44_0,Host1X Sync Syncpt Base 44_0"
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_45_0,Host1X Sync Syncpt Base 45_0"
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_46_0,Host1X Sync Syncpt Base 46_0"
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_47_0,Host1X Sync Syncpt Base 47_0"
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_48_0,Host1X Sync Syncpt Base 48_0"
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_49_0,Host1X Sync Syncpt Base 49_0"
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_50_0,Host1X Sync Syncpt Base 50_0"
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_51_0,Host1X Sync Syncpt Base 51_0"
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_52_0,Host1X Sync Syncpt Base 52_0"
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_53_0,Host1X Sync Syncpt Base 53_0"
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_54_0,Host1X Sync Syncpt Base 54_0"
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_55_0,Host1X Sync Syncpt Base 55_0"
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_56_0,Host1X Sync Syncpt Base 56_0"
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_57_0,Host1X Sync Syncpt Base 57_0"
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_58_0,Host1X Sync Syncpt Base 58_0"
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_59_0,Host1X Sync Syncpt Base 59_0"
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_60_0,Host1X Sync Syncpt Base 60_0"
|
|
group.long 0x6F4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_61_0,Host1X Sync Syncpt Base 61_0"
|
|
group.long 0x6F8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_62_0,Host1X Sync Syncpt Base 62_0"
|
|
group.long 0x6FC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_63_0,Host1X Sync Syncpt Base 63_0"
|
|
tree.end
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 10"
|
|
base ad:0x50024000
|
|
width 27.
|
|
tree "Channel Registers"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CHANNEL_FIFOSTAT_0,Host1X Channel FIFOSTAT_0"
|
|
bitfld.long 0x00 31. " INDRDY ,Indicates that INDCOUNT == 0 so it should be OK to issue another read" "0,1"
|
|
bitfld.long 0x00 24.--28. " OUTFENTRIES ,Number of entries available for reading in this channel's output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " REGNUMEMPTY ,Register write/read FIFO free count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CFGATHER ,Indicates whether GATHER is active" "Idle,Busy"
|
|
bitfld.long 0x00 11. " CFEMPTY ,Indicates whether the command FIFO is empty" "Not empty,Empty"
|
|
hexmask.long.word 0x00 0.--10. 1. " CFNUMEMPTY ,Command FIFO free count"
|
|
if (((per.l(ad:0x50028000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type: Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long 0x00 2.--25. 0x04 " INDOFFSET ,Frame buffer address"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type:Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET ,Register offset"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
endif
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "CHANNEL_INDICT_0,Indirect Register Access Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDCOUNT ,Indcount"
|
|
line.long 0x04 "CHANNEL_IDDATA_0,Host1X Channel INDDATA_0"
|
|
line.long 0x08 "CHANNEL_RAISE_0,DMA And RAISE/REFCOUNT Functionality"
|
|
hexmask.long 0x08 2.--31. 1. " RAISE ,Channel's RAISE vector"
|
|
line.long 0x0C "CHANNEL_DMASTART_0,Host1X Channel DMSTART_0"
|
|
hexmask.long 0x0C 2.--31. 0x04 " DMASTART ,Cmdbuf frame buffer ofset"
|
|
line.long 0x10 "CHANNEL_DMAPUT_0, Host1X Channel DMAPUT_0"
|
|
hexmask.long 0x10 2.--31. 0x04 " DMAPUT ,Cmdbuf frame buffer offset"
|
|
rgroup.long 0x1C++0x0B
|
|
line.long 0x00 "CHANNEL_DMAGET_0,Host1X Channel DMAGET_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " DMAGET ,Cmdbuf frame buffer offset"
|
|
line.long 0x04 "CHANNEL_DMAEND_0 ,Host1X Channel DMAEND_0"
|
|
hexmask.long 0x04 2.--31. 0x04 " DMAEND ,Cmdbuf frame buffer offset"
|
|
line.long 0x08 "CHANNEL_DMACTRL_0,DMA Control Register"
|
|
bitfld.long 0x08 2. " DMAINITGET ,Reset GET pointer to the value of DMAPUT when DMAGETRST is asserted" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " DMAGETRST ,Reset GET pointer to 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " DMASTOP ,Stop DMA from fetching on this channel" "Run,Stop"
|
|
if (((per.l(ad:0x50028000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " INDOFFSET2 ,Frame buffer address"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID2 ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET2 ,Register offset"
|
|
endif
|
|
group.long 0x90++0x2B
|
|
line.long 0x00 "CHANNEL_TICKCOUNT_HI_0,Host1X Channel TICKCOUNT HI 0"
|
|
line.long 0x04 "CHANNEL_TICKCOUNT_LO_0,Host1X Channel TICKCOUNT LO 0"
|
|
line.long 0x08 "CHANNEL_CHANNELCTRL_0,Host1X Channel CHANNELCTRL_0"
|
|
bitfld.long 0x08 2. " KERNEL_FILTER_GBUFFER ,Enable setclass command filter for gather buffers" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ENABLETICKCNT ,Enable tick counter" "Disabled,Enabled"
|
|
line.long 0x0C "CHANNEL_PAYLOAD_0,Host1X Channel PAYLOAD_0"
|
|
line.long 0x10 "CHANNEL_STALLCTRL_0,Host1X Channel STALLCTRL_0"
|
|
bitfld.long 0x10 0. " ENABLE_CHANNEL_STALL ,Enable channel STALL" "Disabled,Enabled"
|
|
line.long 0x14 "CHANNEL_STALLCOUNT_HI_0,Host1X Channel STALLCOUNT Hi 0"
|
|
line.long 0x18 "CHANNEL_STALLCOUNT_LO_0,Host1X Channel STALLCOUNT Lo 0"
|
|
line.long 0x1C "CHANNEL_XFERCTRL_0,Host1X Channel XFERCTRL 0"
|
|
bitfld.long 0x1C 0. " ENABLE_CHANNEL_XFER ,Enable channel XFER" "Disabled,Enabled"
|
|
line.long 0x20 "CHANNEL_CHANNEL_XFER_HI_0,Host1X Channel XFER Hi 0"
|
|
line.long 0x24 "CHANNEL_CHANNEL_XFER_LO_0,Host1X Channel XFER Lo 0"
|
|
line.long 0x28 "CHANNEL_CHANNEL_SPARE_0,Host1x Channel SPARE 0"
|
|
hexmask.long.word 0x28 16.--31. 1. " CHANNEL_SPARE_HI ,Channel SPARE Hi"
|
|
hexmask.long.word 0x28 0.--15. 1. " CHANNEL_SPARE_LO ,CHannel SPARE Lo"
|
|
tree.end
|
|
; base (ad:0x50028000+0x2000) - ACTMON1(MSENC)
|
|
; base (ad:0x50028000+0x2040) - ACTMON2(VIC)
|
|
width 23.
|
|
base (ad:0x50028000+0x2100)
|
|
tree "SYNC (Synchronous Registers)"
|
|
sif CPUIS("TEGRAX1")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " VII2C_INT , VII2C interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOR1_INT ,SOR1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NVENC_INT ,NVENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " NVDEC_INT ,NVDEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 14. " NVJPG_INT ,NVJPG interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " TSECB_INT ,TSECB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " DPAUX1_INT ,DPAUX1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 4. " CPU_TZ_ILLEGAL_TZ_ACCESS_MASK ,Mask CPU_TZ_ILLEGAL_TZ_ACCESS" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 27. " VII2C_INT_C0MASK ,Interrupt mask for VII2C interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SOR1_INT_C0MASK ,Interrupt mask for SOR1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " NVENC_INT_C0MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " NVDEC_INT_C0MASK ,Interrupt mask for NVDEC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NVJPG_INT_C0MASK ,Interrupt mask for NVJPG interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " TSECB_INT_C0MASK ,Interrupt mask for TSECB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " DPAUX1_INT_C0MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 27. " VII2C_INT_C1MASK ,Interrupt mask for VII2C interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 22. " SOR1_INT_C1MASK ,Interrupt mask for SOR1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NVENC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " NVDEC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 14. " NVJPG_INT_C1MASK ,Interrupt mask for NVJPG interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " TSECB_INT_C1MASK ,Interrupt mask for TSECB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " DPAUX1_INT_C1MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " XBAR_TSEC_TIMEOUT_ID ,Id of the CPU which timed out and updated" "TSEC,XBAR"
|
|
eventfld.long 0x00 21. " WAIT_INT13 ,WAIT has completed on channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " WAIT_INT12 ,WAIT has completed on channel 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,Invalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " WAIT_INT13 ,WAIT interrupt mask 13" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " WAIT_INT12 ,WAIT interrupt mask 12" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 ACTMON interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 13. " CMDPP_ILLEGAL_OPCODE_INT13 ,CMPP 13 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 12. " CMDPP_ILLEGAL_OPCODE_INT12 ,CMPP 12 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " CMDPP_ILLEGAL_OPCODE_INTMASK13 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 12. " CMDPP_ILLEGAL_OPCODE_INTMASK12 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--13. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
wgroup.long 0xB0++0x0B
|
|
line.long 0x00 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x00 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x04 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x04 27. " VII2C_TEARDOWN ,VII2C teardown" "No action,Teardown"
|
|
bitfld.long 0x04 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x04 22. " SOR1_TEARDOWN ,SOR1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x04 19. " NVENC_TEARDOWN ,NVENC teardown" "No action,Teardown"
|
|
bitfld.long 0x04 18. " NVDEC_TEARDOWN ,NVEDC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 14. " NVJPG_TEARDOWN ,JVJPG teardown" "No action,Teardown"
|
|
bitfld.long 0x04 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " TSECB_TEARDOWN ,TSECB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DPAUX1_TEARDOWN ,DPAUX1 teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x47
|
|
line.long 0x00 "SYNC_DISPLAY_STATUS_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_STATUS_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_STATUS_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_STATUS_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_SOR1_STATUS_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,SOR1 currcl"
|
|
line.long 0x14 "SYNC_SOR_STATUS,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_STATUS_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_STATUS_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_STATUS_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_STATUS_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_NVENC_STATUS_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,NVENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_STATUS_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
line.long 0x34 "SYNC_NVDEC_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x34 16.--25. 1. " ISPB_CURRCL ,NVDEC currcl"
|
|
line.long 0x38 "SYNC_NVJPG_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x38 16.--25. 1. " ISPB_CURRCL ,NVJPG currcl"
|
|
line.long 0x3C "SYNC_VII2C_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x3C 16.--25. 1. " ISPB_CURRCL ,VII2C currcl"
|
|
line.long 0x40 "SYNC_DPAUX1_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x40 16.--25. 1. " ISPB_CURRCL ,DPAUX1 currcl"
|
|
line.long 0x44 "SYNC_TSECB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x44 16.--25. 1. " ISPB_CURRCL ,TSECB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 13. " HIPRI_CH13 ,HIPRI ch 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " HIPRI_CH12 ,HIPRI ch 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " MSENC_INT ,MSENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " HDMI_INT ,HDMi int " "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " MSENC_INT_C0MASK ,Interrupt mask for MSENC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " HDMI_INT_C0MASK ,Interrupt mask for HDMI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 19. " MSENC_INT_C1MASK ,Interrupt mask for MSENC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HDMI_INT_C1MASK ,Interrupt mask for HDMI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,INvalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " XBAR_TSEC_TIMEOUT_ID ,ID of the CPU which timed out and updated the timeout address" "Tsec,Xbar"
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 actmon interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 actmon interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--11. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
line.long 0x04 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x04 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x08 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x08 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
bitfld.long 0x08 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x08 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x08 19. " MSENC_TEARDOWN ,MSENC teardown" "No action,Teardown"
|
|
bitfld.long 0x08 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 10. " HDMI_TEARDOWN ,HDMI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x33
|
|
line.long 0x00 "SYNC_DISPLAY_Status_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_Status_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_Status_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_Status_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_HDMI_Status_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,HDMI currcl"
|
|
line.long 0x14 "SYNC_SOR_Status,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_Status_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_Status_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_Status_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_Status_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_MSENC_Status_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,MSENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_Status_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_Status_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
endif
|
|
width 23.
|
|
tree "MLOCK registers"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_0_0,Host1X Sync MLOCK_0_0"
|
|
bitfld.long 0x00 0. " MLOCK_0 ,Mlock_0" "Released,Held"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_1_0,Host1X Sync MLOCK_1_0"
|
|
bitfld.long 0x00 0. " MLOCK_1 ,Mlock_1" "Released,Held"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_2_0,Host1X Sync MLOCK_2_0"
|
|
bitfld.long 0x00 0. " MLOCK_2 ,Mlock_2" "Released,Held"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_3_0,Host1X Sync MLOCK_3_0"
|
|
bitfld.long 0x00 0. " MLOCK_3 ,Mlock_3" "Released,Held"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_4_0,Host1X Sync MLOCK_4_0"
|
|
bitfld.long 0x00 0. " MLOCK_4 ,Mlock_4" "Released,Held"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_5_0,Host1X Sync MLOCK_5_0"
|
|
bitfld.long 0x00 0. " MLOCK_5 ,Mlock_5" "Released,Held"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_6_0,Host1X Sync MLOCK_6_0"
|
|
bitfld.long 0x00 0. " MLOCK_6 ,Mlock_6" "Released,Held"
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_7_0,Host1X Sync MLOCK_7_0"
|
|
bitfld.long 0x00 0. " MLOCK_7 ,Mlock_7" "Released,Held"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_8_0,Host1X Sync MLOCK_8_0"
|
|
bitfld.long 0x00 0. " MLOCK_8 ,Mlock_8" "Released,Held"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_9_0,Host1X Sync MLOCK_9_0"
|
|
bitfld.long 0x00 0. " MLOCK_9 ,Mlock_9" "Released,Held"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_10_0,Host1X Sync MLOCK_10_0"
|
|
bitfld.long 0x00 0. " MLOCK_10 ,Mlock_10" "Released,Held"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_11_0,Host1X Sync MLOCK_11_0"
|
|
bitfld.long 0x00 0. " MLOCK_11 ,Mlock_11" "Released,Held"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_12_0,Host1X Sync MLOCK_12_0"
|
|
bitfld.long 0x00 0. " MLOCK_12 ,Mlock_12" "Released,Held"
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_13_0,Host1X Sync MLOCK_13_0"
|
|
bitfld.long 0x00 0. " MLOCK_13 ,Mlock_13" "Released,Held"
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_14_0,Host1X Sync MLOCK_14_0"
|
|
bitfld.long 0x00 0. " MLOCK_14 ,Mlock_14" "Released,Held"
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_15_0,Host1X Sync MLOCK_15_0"
|
|
bitfld.long 0x00 0. " MLOCK_15 ,Mlock_15" "Released,Held"
|
|
textline " "
|
|
rgroup.long 0x340++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_0_0,Host1X Sync MLOCK Owner 0_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_0 ,Mlock owner chid 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_0 ,MLOCK CPU owns 0" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_0 ,MLOCK CH owns 0" "Not owned,Owned"
|
|
rgroup.long 0x344++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_1_0,Host1X Sync MLOCK Owner 1_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_1 ,Mlock owner chid 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_1 ,MLOCK CPU owns 1" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_1 ,MLOCK CH owns 1" "Not owned,Owned"
|
|
rgroup.long 0x348++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_2_0,Host1X Sync MLOCK Owner 2_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_2 ,Mlock owner chid 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_2 ,MLOCK CPU owns 2" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_2 ,MLOCK CH owns 2" "Not owned,Owned"
|
|
rgroup.long 0x34C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_3_0,Host1X Sync MLOCK Owner 3_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_3 ,Mlock owner chid 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_3 ,MLOCK CPU owns 3" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_3 ,MLOCK CH owns 3" "Not owned,Owned"
|
|
rgroup.long 0x350++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_4_0,Host1X Sync MLOCK Owner 4_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_4 ,Mlock owner chid 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_4 ,MLOCK CPU owns 4" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_4 ,MLOCK CH owns 4" "Not owned,Owned"
|
|
rgroup.long 0x354++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_5_0,Host1X Sync MLOCK Owner 5_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_5 ,Mlock owner chid 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_5 ,MLOCK CPU owns 5" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_5 ,MLOCK CH owns 5" "Not owned,Owned"
|
|
rgroup.long 0x358++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_6_0,Host1X Sync MLOCK Owner 6_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_6 ,Mlock owner chid 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_6 ,MLOCK CPU owns 6" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_6 ,MLOCK CH owns 6" "Not owned,Owned"
|
|
rgroup.long 0x35C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_7_0,Host1X Sync MLOCK Owner 7_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_7 ,Mlock owner chid 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_7 ,MLOCK CPU owns 7" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_7 ,MLOCK CH owns 7" "Not owned,Owned"
|
|
rgroup.long 0x360++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_8_0,Host1X Sync MLOCK Owner 8_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_8 ,Mlock owner chid 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_8 ,MLOCK CPU owns 8" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_8 ,MLOCK CH owns 8" "Not owned,Owned"
|
|
rgroup.long 0x364++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_9_0,Host1X Sync MLOCK Owner 9_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_9 ,Mlock owner chid 9" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_9 ,MLOCK CPU owns 9" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_9 ,MLOCK CH owns 9" "Not owned,Owned"
|
|
rgroup.long 0x368++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_10_0,Host1X Sync MLOCK Owner 10_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_10 ,Mlock owner chid 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_10 ,MLOCK CPU owns 10" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_10 ,MLOCK CH owns 10" "Not owned,Owned"
|
|
rgroup.long 0x36C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_11_0,Host1X Sync MLOCK Owner 11_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_11 ,Mlock owner chid 11" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_11 ,MLOCK CPU owns 11" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_11 ,MLOCK CH owns 11" "Not owned,Owned"
|
|
rgroup.long 0x370++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_12_0,Host1X Sync MLOCK Owner 12_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_12 ,Mlock owner chid 12" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_12 ,MLOCK CPU owns 12" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_12 ,MLOCK CH owns 12" "Not owned,Owned"
|
|
rgroup.long 0x374++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_13_0,Host1X Sync MLOCK Owner 13_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_13 ,Mlock owner chid 13" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_13 ,MLOCK CPU owns 13" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_13 ,MLOCK CH owns 13" "Not owned,Owned"
|
|
rgroup.long 0x378++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_14_0,Host1X Sync MLOCK Owner 14_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_14 ,Mlock owner chid 14" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_14 ,MLOCK CPU owns 14" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_14 ,MLOCK CH owns 14" "Not owned,Owned"
|
|
rgroup.long 0x37C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_15_0,Host1X Sync MLOCK Owner 15_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_15 ,Mlock owner chid 15" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_15 ,MLOCK CPU owns 15" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_15 ,MLOCK CH owns 15" "Not owned,Owned"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_ERROR_0_0,Host1X Sync Mlock Error 0_0"
|
|
bitfld.long 0x00 15. " MLOCK_ERROR_15 ,Mlock error 15" "No error,Error"
|
|
bitfld.long 0x00 14. " MLOCK_ERROR_14 ,Mlock error 14" "No error,Error"
|
|
bitfld.long 0x00 13. " MLOCK_ERROR_13 ,Mlock error 13" "No error,Error"
|
|
bitfld.long 0x00 12. " MLOCK_ERROR_12 ,Mlock error 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MLOCK_ERROR_11 ,Mlock error 11" "No error,Error"
|
|
bitfld.long 0x00 10. " MLOCK_ERROR_10 ,Mlock error 10" "No error,Error"
|
|
bitfld.long 0x00 9. " MLOCK_ERROR_9 ,Mlock error 9" "No error,Error"
|
|
bitfld.long 0x00 8. " MLOCK_ERROR_8 ,Mlock error 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MLOCK_ERROR_7 ,Mlock error 7" "No error,Error"
|
|
bitfld.long 0x00 6. " MLOCK_ERROR_6 ,Mlock error 6" "No error,Error"
|
|
bitfld.long 0x00 5. " MLOCK_ERROR_5 ,Mlock error 5" "No error,Error"
|
|
bitfld.long 0x00 4. " MLOCK_ERROR_4 ,Mlock error 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MLOCK_ERROR_3 ,Mlock error 3" "No error,Error"
|
|
bitfld.long 0x00 2. " MLOCK_ERROR_2 ,Mlock error 2" "No error,Error"
|
|
bitfld.long 0x00 1. " MLOCK_ERROR_1 ,Mlock error 1" "No error,Error"
|
|
bitfld.long 0x00 0. " MLOCK_ERROR_0 ,Mlock error 0" "No error,Error"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_0_0,Host1X Sync Syncpt Base 0_0"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_1_0,Host1X Sync Syncpt Base 1_0"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_2_0,Host1X Sync Syncpt Base 2_0"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_3_0,Host1X Sync Syncpt Base 3_0"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_4_0,Host1X Sync Syncpt Base 4_0"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_5_0,Host1X Sync Syncpt Base 5_0"
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_6_0,Host1X Sync Syncpt Base 6_0"
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_7_0,Host1X Sync Syncpt Base 7_0"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_8_0,Host1X Sync Syncpt Base 8_0"
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_9_0,Host1X Sync Syncpt Base 9_0"
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_10_0,Host1X Sync Syncpt Base 10_0"
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_11_0,Host1X Sync Syncpt Base 11_0"
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_12_0,Host1X Sync Syncpt Base 12_0"
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_13_0,Host1X Sync Syncpt Base 13_0"
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_14_0,Host1X Sync Syncpt Base 14_0"
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_15_0,Host1X Sync Syncpt Base 15_0"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_16_0,Host1X Sync Syncpt Base 16_0"
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_17_0,Host1X Sync Syncpt Base 17_0"
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_18_0,Host1X Sync Syncpt Base 18_0"
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_19_0,Host1X Sync Syncpt Base 19_0"
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_20_0,Host1X Sync Syncpt Base 20_0"
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_21_0,Host1X Sync Syncpt Base 21_0"
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_22_0,Host1X Sync Syncpt Base 22_0"
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_23_0,Host1X Sync Syncpt Base 23_0"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_24_0,Host1X Sync Syncpt Base 24_0"
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_25_0,Host1X Sync Syncpt Base 25_0"
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_26_0,Host1X Sync Syncpt Base 26_0"
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_27_0,Host1X Sync Syncpt Base 27_0"
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_28_0,Host1X Sync Syncpt Base 28_0"
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_29_0,Host1X Sync Syncpt Base 29_0"
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_30_0,Host1X Sync Syncpt Base 30_0"
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_31_0,Host1X Sync Syncpt Base 31_0"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_32_0,Host1X Sync Syncpt Base 32_0"
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_33_0,Host1X Sync Syncpt Base 33_0"
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_34_0,Host1X Sync Syncpt Base 34_0"
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_35_0,Host1X Sync Syncpt Base 35_0"
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_36_0,Host1X Sync Syncpt Base 36_0"
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_37_0,Host1X Sync Syncpt Base 37_0"
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_38_0,Host1X Sync Syncpt Base 38_0"
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_39_0,Host1X Sync Syncpt Base 39_0"
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_40_0,Host1X Sync Syncpt Base 40_0"
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_41_0,Host1X Sync Syncpt Base 41_0"
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_42_0,Host1X Sync Syncpt Base 42_0"
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_43_0,Host1X Sync Syncpt Base 43_0"
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_44_0,Host1X Sync Syncpt Base 44_0"
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_45_0,Host1X Sync Syncpt Base 45_0"
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_46_0,Host1X Sync Syncpt Base 46_0"
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_47_0,Host1X Sync Syncpt Base 47_0"
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_48_0,Host1X Sync Syncpt Base 48_0"
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_49_0,Host1X Sync Syncpt Base 49_0"
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_50_0,Host1X Sync Syncpt Base 50_0"
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_51_0,Host1X Sync Syncpt Base 51_0"
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_52_0,Host1X Sync Syncpt Base 52_0"
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_53_0,Host1X Sync Syncpt Base 53_0"
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_54_0,Host1X Sync Syncpt Base 54_0"
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_55_0,Host1X Sync Syncpt Base 55_0"
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_56_0,Host1X Sync Syncpt Base 56_0"
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_57_0,Host1X Sync Syncpt Base 57_0"
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_58_0,Host1X Sync Syncpt Base 58_0"
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_59_0,Host1X Sync Syncpt Base 59_0"
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_60_0,Host1X Sync Syncpt Base 60_0"
|
|
group.long 0x6F4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_61_0,Host1X Sync Syncpt Base 61_0"
|
|
group.long 0x6F8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_62_0,Host1X Sync Syncpt Base 62_0"
|
|
group.long 0x6FC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_63_0,Host1X Sync Syncpt Base 63_0"
|
|
tree.end
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 11"
|
|
base ad:0x50024000
|
|
width 27.
|
|
tree "Channel Registers"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CHANNEL_FIFOSTAT_0,Host1X Channel FIFOSTAT_0"
|
|
bitfld.long 0x00 31. " INDRDY ,Indicates that INDCOUNT == 0 so it should be OK to issue another read" "0,1"
|
|
bitfld.long 0x00 24.--28. " OUTFENTRIES ,Number of entries available for reading in this channel's output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " REGNUMEMPTY ,Register write/read FIFO free count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CFGATHER ,Indicates whether GATHER is active" "Idle,Busy"
|
|
bitfld.long 0x00 11. " CFEMPTY ,Indicates whether the command FIFO is empty" "Not empty,Empty"
|
|
hexmask.long.word 0x00 0.--10. 1. " CFNUMEMPTY ,Command FIFO free count"
|
|
if (((per.l(ad:0x5002C000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type: Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long 0x00 2.--25. 0x04 " INDOFFSET ,Frame buffer address"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF_0,Host1X Channel INDOFF_0"
|
|
bitfld.long 0x00 31. " AUTOINC ,Auto increment of read/write address" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ACCTYPE ,Access type:Indirect register or Indirect frame buffer" "Reg,FB"
|
|
bitfld.long 0x00 29. " BUF32B ,Buffer up 32 bits of register data before sending it" "NoBuf,Buf"
|
|
bitfld.long 0x00 27.--28. " INDSWAP ,Indirect frame buffer access swap control" "None,Byte16,Byte32,Word32"
|
|
textline " "
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET ,Register offset"
|
|
bitfld.long 0x00 0. " INDOFFUPD ,Optionally disable update of INDOFFSET" "Updated,Not updated"
|
|
endif
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "CHANNEL_INDICT_0,Indirect Register Access Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " INDCOUNT ,Indcount"
|
|
line.long 0x04 "CHANNEL_IDDATA_0,Host1X Channel INDDATA_0"
|
|
line.long 0x08 "CHANNEL_RAISE_0,DMA And RAISE/REFCOUNT Functionality"
|
|
hexmask.long 0x08 2.--31. 1. " RAISE ,Channel's RAISE vector"
|
|
line.long 0x0C "CHANNEL_DMASTART_0,Host1X Channel DMSTART_0"
|
|
hexmask.long 0x0C 2.--31. 0x04 " DMASTART ,Cmdbuf frame buffer ofset"
|
|
line.long 0x10 "CHANNEL_DMAPUT_0, Host1X Channel DMAPUT_0"
|
|
hexmask.long 0x10 2.--31. 0x04 " DMAPUT ,Cmdbuf frame buffer offset"
|
|
rgroup.long 0x1C++0x0B
|
|
line.long 0x00 "CHANNEL_DMAGET_0,Host1X Channel DMAGET_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " DMAGET ,Cmdbuf frame buffer offset"
|
|
line.long 0x04 "CHANNEL_DMAEND_0 ,Host1X Channel DMAEND_0"
|
|
hexmask.long 0x04 2.--31. 0x04 " DMAEND ,Cmdbuf frame buffer offset"
|
|
line.long 0x08 "CHANNEL_DMACTRL_0,DMA Control Register"
|
|
bitfld.long 0x08 2. " DMAINITGET ,Reset GET pointer to the value of DMAPUT when DMAGETRST is asserted" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " DMAGETRST ,Reset GET pointer to 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " DMASTOP ,Stop DMA from fetching on this channel" "Run,Stop"
|
|
if (((per.l(ad:0x5002C000+0x04))&0x40000000)==0x40000000)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long 0x00 2.--31. 0x04 " INDOFFSET2 ,Frame buffer address"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANNEL_INDOFF2_0,Host1X Channel INDOFF2_0"
|
|
hexmask.long.byte 0x00 18.--25. 1. " INDMODID2 ,Register module ID"
|
|
hexmask.long.word 0x00 2.--17. 1. " INDROFFSET2 ,Register offset"
|
|
endif
|
|
group.long 0x90++0x2B
|
|
line.long 0x00 "CHANNEL_TICKCOUNT_HI_0,Host1X Channel TICKCOUNT HI 0"
|
|
line.long 0x04 "CHANNEL_TICKCOUNT_LO_0,Host1X Channel TICKCOUNT LO 0"
|
|
line.long 0x08 "CHANNEL_CHANNELCTRL_0,Host1X Channel CHANNELCTRL_0"
|
|
bitfld.long 0x08 2. " KERNEL_FILTER_GBUFFER ,Enable setclass command filter for gather buffers" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ENABLETICKCNT ,Enable tick counter" "Disabled,Enabled"
|
|
line.long 0x0C "CHANNEL_PAYLOAD_0,Host1X Channel PAYLOAD_0"
|
|
line.long 0x10 "CHANNEL_STALLCTRL_0,Host1X Channel STALLCTRL_0"
|
|
bitfld.long 0x10 0. " ENABLE_CHANNEL_STALL ,Enable channel STALL" "Disabled,Enabled"
|
|
line.long 0x14 "CHANNEL_STALLCOUNT_HI_0,Host1X Channel STALLCOUNT Hi 0"
|
|
line.long 0x18 "CHANNEL_STALLCOUNT_LO_0,Host1X Channel STALLCOUNT Lo 0"
|
|
line.long 0x1C "CHANNEL_XFERCTRL_0,Host1X Channel XFERCTRL 0"
|
|
bitfld.long 0x1C 0. " ENABLE_CHANNEL_XFER ,Enable channel XFER" "Disabled,Enabled"
|
|
line.long 0x20 "CHANNEL_CHANNEL_XFER_HI_0,Host1X Channel XFER Hi 0"
|
|
line.long 0x24 "CHANNEL_CHANNEL_XFER_LO_0,Host1X Channel XFER Lo 0"
|
|
line.long 0x28 "CHANNEL_CHANNEL_SPARE_0,Host1x Channel SPARE 0"
|
|
hexmask.long.word 0x28 16.--31. 1. " CHANNEL_SPARE_HI ,Channel SPARE Hi"
|
|
hexmask.long.word 0x28 0.--15. 1. " CHANNEL_SPARE_LO ,CHannel SPARE Lo"
|
|
tree.end
|
|
; base (ad:0x5002C000+0x2000) - ACTMON1(MSENC)
|
|
; base (ad:0x5002C000+0x2040) - ACTMON2(VIC)
|
|
width 23.
|
|
base (ad:0x5002C000+0x2100)
|
|
tree "SYNC (Synchronous Registers)"
|
|
sif CPUIS("TEGRAX1")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " VII2C_INT , VII2C interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SOR1_INT ,SOR1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NVENC_INT ,NVENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " NVDEC_INT ,NVDEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 14. " NVJPG_INT ,NVJPG interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " TSECB_INT ,TSECB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " DPAUX1_INT ,DPAUX1 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 4. " CPU_TZ_ILLEGAL_TZ_ACCESS_MASK ,Mask CPU_TZ_ILLEGAL_TZ_ACCESS" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 27. " VII2C_INT_C0MASK ,Interrupt mask for VII2C interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SOR1_INT_C0MASK ,Interrupt mask for SOR1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " NVENC_INT_C0MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " NVDEC_INT_C0MASK ,Interrupt mask for NVDEC_INT interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " NVJPG_INT_C0MASK ,Interrupt mask for NVJPG interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " TSECB_INT_C0MASK ,Interrupt mask for TSECB interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " DPAUX1_INT_C0MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 27. " VII2C_INT_C1MASK ,Interrupt mask for VII2C interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 22. " SOR1_INT_C1MASK ,Interrupt mask for SOR1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NVENC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " NVDEC_INT_C1MASK ,Interrupt mask for NVENC_INT interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 14. " NVJPG_INT_C1MASK ,Interrupt mask for NVJPG interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " TSECB_INT_C1MASK ,Interrupt mask for TSECB interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " DPAUX1_INT_C1MASK ,Interrupt mask for DPAUX1 interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " XBAR_TSEC_TIMEOUT_ID ,Id of the CPU which timed out and updated" "TSEC,XBAR"
|
|
eventfld.long 0x00 21. " WAIT_INT13 ,WAIT has completed on channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " WAIT_INT12 ,WAIT has completed on channel 12" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,Invalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " WAIT_INT13 ,WAIT interrupt mask 13" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " WAIT_INT12 ,WAIT interrupt mask 12" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " UNIT4_ACTMON_INTR ,Unit4 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " UNIT3_ACTMON_INTR ,Unit3 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 ACTMON interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 ACTMON interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 13. " CMDPP_ILLEGAL_OPCODE_INT13 ,CMPP 13 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 12. " CMDPP_ILLEGAL_OPCODE_INT12 ,CMPP 12 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " CMDPP_ILLEGAL_OPCODE_INTMASK13 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 12. " CMDPP_ILLEGAL_OPCODE_INTMASK12 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--13. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
wgroup.long 0xB0++0x0B
|
|
line.long 0x00 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x00 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x00 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x04 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x04 27. " VII2C_TEARDOWN ,VII2C teardown" "No action,Teardown"
|
|
bitfld.long 0x04 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x04 22. " SOR1_TEARDOWN ,SOR1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x04 19. " NVENC_TEARDOWN ,NVENC teardown" "No action,Teardown"
|
|
bitfld.long 0x04 18. " NVDEC_TEARDOWN ,NVEDC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 14. " NVJPG_TEARDOWN ,JVJPG teardown" "No action,Teardown"
|
|
bitfld.long 0x04 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " TSECB_TEARDOWN ,TSECB teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DPAUX1_TEARDOWN ,DPAUX1 teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x47
|
|
line.long 0x00 "SYNC_DISPLAY_STATUS_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_STATUS_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_STATUS_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_STATUS_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_SOR1_STATUS_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,SOR1 currcl"
|
|
line.long 0x14 "SYNC_SOR_STATUS,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_STATUS_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_STATUS_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_STATUS_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_STATUS_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_NVENC_STATUS_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,NVENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_STATUS_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
line.long 0x34 "SYNC_NVDEC_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x34 16.--25. 1. " ISPB_CURRCL ,NVDEC currcl"
|
|
line.long 0x38 "SYNC_NVJPG_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x38 16.--25. 1. " ISPB_CURRCL ,NVJPG currcl"
|
|
line.long 0x3C "SYNC_VII2C_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x3C 16.--25. 1. " ISPB_CURRCL ,VII2C currcl"
|
|
line.long 0x40 "SYNC_DPAUX1_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x40 16.--25. 1. " ISPB_CURRCL ,DPAUX1 currcl"
|
|
line.long 0x44 "SYNC_TSECB_STATUS_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x44 16.--25. 1. " ISPB_CURRCL ,TSECB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 13. " HIPRI_CH13 ,HIPRI ch 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " HIPRI_CH12 ,HIPRI ch 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYNC_INTSTATUS_0,Host1X Sync Intstatus 0"
|
|
bitfld.long 0x00 31. " SYNCPT_CPU1_INT ,SYNCPT CPU1 interrupt status " "Not pending,Pending"
|
|
bitfld.long 0x00 30. " SYNCPT_CPU0_INT ,SYNCPT CPU0 interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " ISPB_INT ,ISPB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ISP_INT ,ISP interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " DPAUX_INT , DPAUX interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " SOR_INT ,SOR interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TSEC_INT ,TSEC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " MSENC_INT ,MSENC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " DSIB_INT ,DSIB interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " VIC_INT ,VIC interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " DSI_INT ,DSI interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " HDMI_INT ,HDMi int " "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISPLAYB_INT ,DISPLAYB interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " DISPLAY_INT ,DISPLAY interrupt status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " VI_INT ,VI interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HOST_INT ,HOST interrupt status" "Not pending,Pending"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SYNC_INTMASK_0,Master Interrupt Mask For All Interrupt Signals"
|
|
bitfld.long 0x00 1. " CPU1_INT_MASK_ALL ,Mask all interrupts on CPU1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " CPU0_INT_MASK_ALL ,Mask all interrupts on CPU0" "Masked,Not masked"
|
|
line.long 0x04 "SYNC_INTC0MASK_0,Interrupt Mask For CPU0"
|
|
bitfld.long 0x04 26. " ISPB_INT_C0MASK ,Interrupt mask for ISPB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " ISP_INT_C0MASK ,Interrupt mask for ISP interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " DPAUX_INT_C0MASK ,Interrupt mask for DPAUX interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SOR_INT_C0MASK ,Interrupt mask for SOR interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " TSEC_INT_C0MASK ,Interrupt mask for TSEC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 19. " MSENC_INT_C0MASK ,Interrupt mask for MSENC interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DSIB_INT_C0MASK ,Interrupt mask for DSIB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VIC_INT_C0MASK ,Interrupt mask for VIC interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " DSI_INT_C0MASK ,Interrupt mask for DSI interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " HDMI_INT_C0MASK ,Interrupt mask for HDMI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " DISPLAYB_INT_C0MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " DISPLAY_INT_C0MASK ,Interrupt mask for DISPLAY interrupt signal to CPU0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VI_INT_C0MASK ,Interrupt mask for VI interrupt signal to CPU0" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " HOST_INT_C0MASK ,Interrupt mask for HOST interrupt signal to CPU0" "Masked,Not masked"
|
|
line.long 0x08 "SYNC_INTC1MASK_0,Interrupt Mask For CPU1"
|
|
bitfld.long 0x08 26. " ISPB_INT_C1MASK ,Interrupt mask for ISPB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " ISP_INT_C1MASK ,Interrupt mask for ISP interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " DPAUX_INT_C1MASK ,Interrupt mask for DPAUX interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SOR_INT_C1MASK ,Interrupt mask for SOR interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " TSEC_INT_C1MASK ,Interrupt mask for TSEC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 19. " MSENC_INT_C1MASK ,Interrupt mask for MSENC interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 16. " DSIB_INT_C1MASK ,Interrupt mask for DSIB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 13. " VIC_INT_C1MASK ,Interrupt mask for VIC interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " DSI_INT_C1MASK ,Interrupt mask for DSI interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HDMI_INT_C1MASK ,Interrupt mask for HDMI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " DISPLAYB_INT_C1MASK ,Interrupt mask for DISPLAYB interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " DISPLAY_INT_C1MASK ,Interrupt mask for DISPLAY interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_INT_C1MASK ,Interrupt mask for VI interrupt signal to CPU1" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " HOST_INT_C1MASK ,Interrupt mask for HOST interrupt signal to CPU1" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SYNC_HINSTATUS_0,HOST Interrupt Status"
|
|
rbitfld.long 0x00 31. " HINTSTATUS_EXT_INT ,Additional interrupts pending in the HINSTATUS_EXT register" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " TIMER_INTP ,Timer interrupt from the Protected Channel" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " CSW_HOST1XW2MC_INT ,Host write client FIFO has filled up" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RDMA_DATABUF_THOLD_INT0 ,Read DMA data FIFO in port0" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " RDMA_BUF_THOLD_INT0 ,Buffer threshold reached in read DMA port0" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " RDMA_BUF_OFLOW_INT0 ,Buffer overflow in read DMA port0" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " RDMA_INVAL_CLREQ_INT ,INvalid client request to read DMA" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " XBAR_TSEC_TIMEOUT_ID ,ID of the CPU which timed out and updated the timeout address" "Tsec,Xbar"
|
|
eventfld.long 0x00 13. " UNIT2_ACTMON_INTR ,Unit2 ACTMON generates interrupt" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 12. " UNIT1_ACTMON_INTR ,Unit1 ACTMON generates interrupt" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " WAIT_INT11 ,WAIT has completed on channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " WAIT_INT10 ,WAIT has completed on channel 10" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 9. " WAIT_INT9 ,WAIT has completed on channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " WAIT_INT8 ,WAIT has completed on channel 8" "Not pending,Pending"
|
|
eventfld.long 0x00 7. " WAIT_INT7 ,WAIT has completed on channel 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 6. " WAIT_INT6 ,WAIT has completed on channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " WAIT_INT5 ,WAIT has completed on channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " WAIT_INT4 ,WAIT has completed on channel 4" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " WAIT_INT3 ,WAIT has completed on channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " WAIT_INT2 ,WAIT has completed on channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " WAIT_INT1 ,WAIT has completed on channel 1" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAIT_INT0 ,WAIT has completed on channel 0" "Not pending,Pending"
|
|
line.long 0x04 "SYNC_HINTMASK_0,Host Interrupt Mask"
|
|
bitfld.long 0x04 31. " HINTSTATUS_EXT_INTMASK , Hintstatus ext interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " TIMER_INTMASKP ,Timer Interrupt Mask for the Protected Channel" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " CSW_HOST1XW2MC_INTMASK ,Csw Host1xw2mc interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " RDMA_DATABUF_THOLD_INTMASK0 ,RDMA data buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " RDMA_BUF_THOLD_INTMASK0 , RDMA buf thold intmask0" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " RDMA_BUF_OFLOW_INTMASK0 ,RDMA buf oflow intmask0" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " RDMA_INVAL_CLREQ_INTMASK ,RDMA inval clreq interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " UNIT2_ACTMON_INTRMASK ,UNIT2 actmon interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " UNIT1_ACTMON_INTRMASK ,UNIT1 actmon interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " WAIT_INTMASK11 ,WAIT interrupt mask 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " WAIT_INTMASK10 ,WAIT interrupt mask 10" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " WAIT_INTMASK9 ,WAIT interrupt mask 9" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAIT_INTMASK8 ,WAIT interrupt mask 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " WAIT_INTMASK7 ,WAIT interrupt mask 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " WAIT_INTMASK6 ,WAIT interrupt mask 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WAIT_INTMASK5 ,WAIT interrupt mask 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " WAIT_INTMASK4 ,WAIT interrupt mask 4" "Masked,Not masked"
|
|
bitfld.long 0x04 3. " WAIT_INTMASK3 ,WAIT interrupt mask 3" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " WAIT_INTMASK2 ,WAIT interrupt mask 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " WAIT_INTMASK1 ,WAIT interrupt mask 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " WAIT_INTMASK0 ,WAIT interrupt mask 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "SYNC_HINTSTATUS_EXT_0,Extended Host Interrupt Status"
|
|
eventfld.long 0x08 31. " IP_WRITE_INT ,Offending address in IP_WRITE_TIMEOUT_ADDR" "Not pending,Pending"
|
|
eventfld.long 0x08 30. " IP_READ_INT ,OFFENDING address in IP_READ_TIMEOUT_ADDR" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 11. " CMDPP_ILLEGAL_OPCODE_INT11 ,CMDPP 11 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 10. " CMDPP_ILLEGAL_OPCODE_INT10 ,CMDPP 10 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 9. " CMDPP_ILLEGAL_OPCODE_INT9 ,CMDPP 9 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 8. " CMDPP_ILLEGAL_OPCODE_INT8 ,CMDPP 8 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 7. " CMDPP_ILLEGAL_OPCODE_INT7 ,CMDPP 7 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 6. " CMDPP_ILLEGAL_OPCODE_INT6 ,CMDPP 6 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 5. " CMDPP_ILLEGAL_OPCODE_INT5 ,CMDPP 5 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 4. " CMDPP_ILLEGAL_OPCODE_INT4 ,CMDPP 4 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 3. " CMDPP_ILLEGAL_OPCODE_INT3 ,CMDPP 3 has seen an illegal opcode" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 2. " CMDPP_ILLEGAL_OPCODE_INT2 ,CMDPP 2 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 1. " CMDPP_ILLEGAL_OPCODE_INT1 ,CMDPP 1 has seen an illegal opcode" "Not pending,Pending"
|
|
eventfld.long 0x08 0. " CMDPP_ILLEGAL_OPCODE_INT0 ,CMDPP 0 has seen an illegal opcode" "Not pending,Pending"
|
|
line.long 0x0C "SYNC_HINTMASK_EXT_0,Host1X Sync Hintmask Ext 0"
|
|
bitfld.long 0x0C 31. " IP_WRITE_INTMASK ,Ip write interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 30. " IP_READ_INTMASK ,Ip read interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CMDPP_ILLEGAL_OPCODE_INTMASK11 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 10. " CMDPP_ILLEGAL_OPCODE_INTMASK10 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 9. " CMDPP_ILLEGAL_OPCODE_INTMASK9 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " CMDPP_ILLEGAL_OPCODE_INTMASK8 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 7. " CMDPP_ILLEGAL_OPCODE_INTMASK7 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 6. " CMDPP_ILLEGAL_OPCODE_INTMASK6 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " CMDPP_ILLEGAL_OPCODE_INTMASK5 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 4. " CMDPP_ILLEGAL_OPCODE_INTMASK4 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 3. " CMDPP_ILLEGAL_OPCODE_INTMASK3 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " CMDPP_ILLEGAL_OPCODE_INTMASK2 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 1. " CMDPP_ILLEGAL_OPCODE_INTMASK1 ,CMDPP_ILLEGAL_OPCODE interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x0C 0. " CMDPP_ILLEGAL_OPCODE_INTMASK0 ,CMDPP_ILLEGAL_OPCODE_INT0 interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SYNC_CF_SETUPDONE_0,Host1X Sync CF Setup Done 0"
|
|
bitfld.long 0x00 0. " CF_SETUPDONE ,Dummy bit (Write to this register to trigger an update of the FIFO's pointers)" "No effect,Trigger"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_CTRL_0,Host1X Sync Cmdproc Ctrl 0"
|
|
bitfld.long 0x00 5. " INTFC_CLKEN_OVR ,Intfc clken ovr" "No,Yes"
|
|
bitfld.long 0x00 2. " GATHER_PARSE_DISABLED ,Gather parse disabled" "No,Yes"
|
|
bitfld.long 0x00 1. " DROP_ILLEGAL_OPCODES ,Drop illegal opcodes" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "SYNC_CMDPROC_STAT_0,Host1X Sync Cmdproc Stat 0"
|
|
hexmask.long.word 0x00 0.--11. 1. " ILLEGAL_OPCODE ,Illegal opcode"
|
|
group.long 0xAC++0x0B
|
|
line.long 0x00 "SYNC_CMDPROC_STOP_0,Stops Issuing Commands From The Command FIFO"
|
|
bitfld.long 0x00 13. " CH13_CMDPROC_STOP ,CH13 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 12. " CH12_CMDPROC_STOP ,CH12 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CH11_CMDPROC_STOP ,CH11 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 10. " CH10_CMDPROC_STOP ,CH10 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 9. " CH9_CMDPROC_STOP ,CH9 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 8. " CH8_CMDPROC_STOP ,CH8 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CMDPROC_STOP ,CH7 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 6. " CH6_CMDPROC_STOP ,CH6 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 5. " CH5_CMDPROC_STOP ,CH5 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 4. " CH4_CMDPROC_STOP ,CH4 cmdproc stop" "Run,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH3_CMDPROC_STOP ,CH3 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 2. " CH2_CMDPROC_STOP ,CH2 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 1. " CH1_CMDPROC_STOP ,CH1 cmdproc stop" "Run,Stop"
|
|
bitfld.long 0x00 0. " CH0_CMDPROC_STOP ,CH0 cmdproc stop" "Run,Stop"
|
|
line.long 0x04 "SYNC_CH_TEARDOWN_0,Channel Teardown Register"
|
|
bitfld.long 0x04 13. " CH13_TEARDOWN ,CH13 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 12. " CH12_TEARDOWN ,CH12 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH11_TEARDOWN ,CH11 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 10. " CH10_TEARDOWN ,CH10 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 9. " CH9_TEARDOWN ,CH9 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 8. " CH8_TEARDOWN ,CH8 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7_TEARDOWN ,CH7 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 6. " CH6_TEARDOWN ,CH6 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 5. " CH5_TEARDOWN ,CH5 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 4. " CH4_TEARDOWN ,CH4 teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3_TEARDOWN ,CH3 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 2. " CH2_TEARDOWN ,CH2 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 1. " CH1_TEARDOWN ,CH1 teardown" "No action,Teardown"
|
|
bitfld.long 0x04 0. " CH0_TEARDOWN ,CH0 teardown" "No action,Teardown"
|
|
line.long 0x08 "SYNC_MOD_TEARDOWN_0,Module Teardown Register"
|
|
bitfld.long 0x08 26. " ISPB_TEARDOWN ,ISPB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 24. " ISP_TEARDOWN ,ISP teardown" "No action,Teardown"
|
|
bitfld.long 0x08 23. " DPAUX_TEARDOWN ,DPAUX teardown" "No action,Teardown"
|
|
bitfld.long 0x08 21. " SOR_TEARDOWN ,SOR teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 20. " TSEC_TEARDOWN ,TSEC teardown" "No action,teardown"
|
|
bitfld.long 0x08 19. " MSENC_TEARDOWN ,MSENC teardown" "No action,Teardown"
|
|
bitfld.long 0x08 16. " DSIB_TEARDOWN ,DSIB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 13. " VIC_TEARDOWN ,VIC teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 12. " DSI_TEARDOWN ,DSI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 10. " HDMI_TEARDOWN ,HDMI teardown" "No action,Teardown"
|
|
bitfld.long 0x08 9. " DISPLAYB_TEARDOWN ,DISPLAYB teardown" "No action,Teardown"
|
|
bitfld.long 0x08 8. " DISPLAY_TEARDOWN ,DISPLAY teardown" "No action,Teardown"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VI_TEARDOWN ,VI teardown" "No action,Teardown"
|
|
textline " "
|
|
width 29.
|
|
rgroup.long 0xDC++0x33
|
|
line.long 0x00 "SYNC_DISPLAY_Status_0,Host1X Sync Display Status 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " DISPLAY_CURRCL ,Display currcl"
|
|
line.long 0x04 "SYNC_DISPLAYB_Status_0,Host1X Sync DisplayB Status 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " DISPLAYB_CURRCL ,Display currcl"
|
|
line.long 0x08 "SYNC_ISP_Status_0,Host1X Sync ISP Status 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " ISP_CURRCL ,ISP currcl"
|
|
line.long 0x0C "SYNC_DSI_Status_0,Host1X Sync DSI Status 0"
|
|
hexmask.long.word 0x0C 16.--25. 1. " DSI_CURRCL ,DSI currcl"
|
|
line.long 0x10 "SYNC_HDMI_Status_0,Host1X Sync HDMI Status 0"
|
|
hexmask.long.word 0x10 16.--25. 1. " HDMI_CURRCL ,HDMI currcl"
|
|
line.long 0x14 "SYNC_SOR_Status,Hosta1X Sync SOR Status 0"
|
|
hexmask.long.word 0x14 16.--25. 1. " SOR_CURRCL ,SOR currcl"
|
|
line.long 0x18 "SYNC_DPAUX_Status_0,Host1X Sync DPAUX Status 0"
|
|
hexmask.long.word 0x18 16.--25. 1. " DPAUX_CURRCL ,DPAUX currcl"
|
|
line.long 0x1C "SYNC_VI_Status_0,Host1X Sync VI Status 0"
|
|
hexmask.long.word 0x1C 16.--25. 1. " VI_CURRCL ,VI currcl"
|
|
line.long 0x20 "SYNC_DSIB_Status_0,Host1X Sync DSIB Status 0"
|
|
hexmask.long.word 0x20 16.--25. 1. " DSIB_CURRCL ,DSIB currcl"
|
|
line.long 0x24 "SYNC_VIC_Status_0,Host1X Sync Vic Status 0"
|
|
hexmask.long.word 0x24 16.--25. 1. " VIC_CURRCL ,VIC currcl"
|
|
line.long 0x28 "SYNC_MSENC_Status_0,Host1X Sync Msenc Status 0"
|
|
hexmask.long.word 0x28 16.--25. 1. " MSENC_CURRCL ,MSENC currcl"
|
|
line.long 0x2C "SYNC_TSEC_Status_0,Host1X Sync TSEC Status 0"
|
|
hexmask.long.word 0x2C 16.--25. 1. " TSEC_CURRCL ,TSEC currcl"
|
|
line.long 0x30 "SYNC_ISPB_Status_0,Host1X Sync ISPB Status 0"
|
|
hexmask.long.word 0x30 16.--25. 1. " ISPB_CURRCL ,ISPB currcl"
|
|
group.long 0x1A0++0x0F
|
|
line.long 0x00 "SYNC_DIRECT_MODULE_CONFIG_0,Host1X Sync Direct Module Config 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " BASE ,Base"
|
|
line.long 0x04 "SYNC_USEC_CLK_0,Number Of Host Clocks Needed To Make A Microsecond"
|
|
hexmask.long.word 0x04 0.--11. 1. " USEC_CLKS ,Number of host clocks needed to make a microsecond"
|
|
line.long 0x08 "SYNC_CTXSW_TIMEOUT_CFG_0,Host1X Sync CTXSW Timeout CFG 0"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WAIT_CTXSW_CNT ,Number of cycles to wait"
|
|
textline " "
|
|
line.long 0x0C "SYNC_INDREG_DMA_CTRL_0,Host1X Sync INDREG DMA CTRL"
|
|
bitfld.long 0x0C 7. " AHBDMA_ENABLE ,Enable generation of request to DMA engine" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5.--6. " AHBDMA_ATTN_LVL ,Number of entries to receive before sending DMA request " "1 slot,4 slots,8 slots,?..."
|
|
bitfld.long 0x0C 0.--3. " AHBDMA_CHID ,Channel being used by indirect read for DMA" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "SYNC_CHANNEL_PRIORITY_0,Host1X Sync Channel Priority For Dual Ring Arbitration"
|
|
bitfld.long 0x00 11. " HIPRI_CH11 ,HIPRI ch 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " HIPRI_CH10 ,HIPRI ch 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " HIPRI_CH9 ,HIPRI ch 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HIPRI_CH8 ,HIPRI ch 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " HIPRI_CH7 ,HIPRI ch 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HIPRI_CH6 ,HIPRI ch 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HIPRI_CH5 ,HIPRI ch 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " HIPRI_CH4 ,HIPRI ch 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HIPRI_CH3 ,HIPRI ch 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HIPRI_CH2 ,HIPRI ch 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HIPRI_CH1 ,HIPRI ch 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HIPRI_CH0 ,HIPRI ch 0" "Disabled,Enabled"
|
|
line.long 0x04 "SYNC_CDMA_ASM_TIMEOUT_0,Host1X Sync CDMA Asm Timeout Value "
|
|
bitfld.long 0x04 8.--12. " CDMA_ASM_GFIFO_TIMEOUT ,CDMA ASM GFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " CDMA_ASM_DFIFO_TIMEOUT ,CDMA ASM DFIFO timeout" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SYNC_CDMA_MISC_0,Host1X Sync Cdma Misc 0"
|
|
bitfld.long 0x08 12. " CDMA_EN_STATS ,CDMA enable statistics counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CDMA_CLKEN_OVR ,CDMA clken ovr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CDMA_PUT_SYNC_DISABLE ,CDMA put sync disable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " CDMA_SIMPLE_PREFETCH ,CDMA simple prefetch" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--5. 1. " CDMA_DELAY_PUT ,CDMA delay put"
|
|
line.long 0x0C "SYNC_IP_BUSY_TIMEOUT_0,Host1X Sync IP Busy Timeout"
|
|
rgroup.long 0x1C0++0x07
|
|
line.long 0x00 "SYNC_IP_READ_TIMEOUT_ADDR_0,Host1X Sync IP Read Timeout Addr 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " IP_READ_TIMEOUT_ADDR ,IP read timeout addr"
|
|
line.long 0x04 "SYNC_IP_WRITE_TIMEOUT_ADDR_0,Host1X Sync IP Write Timeout Addr"
|
|
hexmask.long 0x04 2.--31. 0x04 " IP_WRITE_TIMEOUT_ADDR ,Address of transaction that caused an AXI write timeout"
|
|
group.long 0x1D8++0x0B
|
|
line.long 0x00 "SYNC_MCCIF_THCTRL_0,Host1X Sync MCCIF Thctrl 0"
|
|
bitfld.long 0x00 8.--13. " CSW_HOST1XW2MC_HPTH ,CSW host1xw2mc hpth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " CSW_HOST1XW_FIFOSTAT ,CSW HOST1XW fifostat" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,333,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SYNC_HC_MCCIF_FIFOCTRL_O ,Memory Client Interface FIFO Control And Clock Gating Control"
|
|
bitfld.long 0x04 20. " HC_RCLK_OVR_MODE ,HC rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 19. " HC_WCLK_OVR_MODE ,HC wclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x04 18. " HC_CCLK_OVERRIDE ,HC cclk override" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HC_RCLK_OVERRIDE ,HC rclk override" "0,1"
|
|
bitfld.long 0x04 16. " HC_WCLK_OVERRIDE ,HC wclk override" "0,1"
|
|
bitfld.long 0x04 3. " HC_MCCIF_RDCL_RDFAST ,HC mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HC_MCCIF_WRMC_CLLE2X ,HC mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " HC_MCCIF_RDMC_RDFAST ,HC mccif rdmc rdfast" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " HC_MCCIF_WRCL_MCLE2X ,HC mccif wrcl mcle2x" "Disabled,Enabled"
|
|
line.long 0x08 "SSYNC_TIMEOUT_WCOAL_HC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HOST1XW_WCOAL_TMVAL ,HOST1XW_WCOAL_TMVAL"
|
|
endif
|
|
width 23.
|
|
tree "MLOCK registers"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_0_0,Host1X Sync MLOCK_0_0"
|
|
bitfld.long 0x00 0. " MLOCK_0 ,Mlock_0" "Released,Held"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_1_0,Host1X Sync MLOCK_1_0"
|
|
bitfld.long 0x00 0. " MLOCK_1 ,Mlock_1" "Released,Held"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_2_0,Host1X Sync MLOCK_2_0"
|
|
bitfld.long 0x00 0. " MLOCK_2 ,Mlock_2" "Released,Held"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_3_0,Host1X Sync MLOCK_3_0"
|
|
bitfld.long 0x00 0. " MLOCK_3 ,Mlock_3" "Released,Held"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_4_0,Host1X Sync MLOCK_4_0"
|
|
bitfld.long 0x00 0. " MLOCK_4 ,Mlock_4" "Released,Held"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_5_0,Host1X Sync MLOCK_5_0"
|
|
bitfld.long 0x00 0. " MLOCK_5 ,Mlock_5" "Released,Held"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_6_0,Host1X Sync MLOCK_6_0"
|
|
bitfld.long 0x00 0. " MLOCK_6 ,Mlock_6" "Released,Held"
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_7_0,Host1X Sync MLOCK_7_0"
|
|
bitfld.long 0x00 0. " MLOCK_7 ,Mlock_7" "Released,Held"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_8_0,Host1X Sync MLOCK_8_0"
|
|
bitfld.long 0x00 0. " MLOCK_8 ,Mlock_8" "Released,Held"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_9_0,Host1X Sync MLOCK_9_0"
|
|
bitfld.long 0x00 0. " MLOCK_9 ,Mlock_9" "Released,Held"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_10_0,Host1X Sync MLOCK_10_0"
|
|
bitfld.long 0x00 0. " MLOCK_10 ,Mlock_10" "Released,Held"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_11_0,Host1X Sync MLOCK_11_0"
|
|
bitfld.long 0x00 0. " MLOCK_11 ,Mlock_11" "Released,Held"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_12_0,Host1X Sync MLOCK_12_0"
|
|
bitfld.long 0x00 0. " MLOCK_12 ,Mlock_12" "Released,Held"
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "SYNC_MLOCK_13_0,Host1X Sync MLOCK_13_0"
|
|
bitfld.long 0x00 0. " MLOCK_13 ,Mlock_13" "Released,Held"
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "SYNC_MLOCK_14_0,Host1X Sync MLOCK_14_0"
|
|
bitfld.long 0x00 0. " MLOCK_14 ,Mlock_14" "Released,Held"
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "SYNC_MLOCK_15_0,Host1X Sync MLOCK_15_0"
|
|
bitfld.long 0x00 0. " MLOCK_15 ,Mlock_15" "Released,Held"
|
|
textline " "
|
|
rgroup.long 0x340++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_0_0,Host1X Sync MLOCK Owner 0_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_0 ,Mlock owner chid 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_0 ,MLOCK CPU owns 0" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_0 ,MLOCK CH owns 0" "Not owned,Owned"
|
|
rgroup.long 0x344++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_1_0,Host1X Sync MLOCK Owner 1_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_1 ,Mlock owner chid 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_1 ,MLOCK CPU owns 1" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_1 ,MLOCK CH owns 1" "Not owned,Owned"
|
|
rgroup.long 0x348++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_2_0,Host1X Sync MLOCK Owner 2_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_2 ,Mlock owner chid 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_2 ,MLOCK CPU owns 2" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_2 ,MLOCK CH owns 2" "Not owned,Owned"
|
|
rgroup.long 0x34C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_3_0,Host1X Sync MLOCK Owner 3_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_3 ,Mlock owner chid 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_3 ,MLOCK CPU owns 3" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_3 ,MLOCK CH owns 3" "Not owned,Owned"
|
|
rgroup.long 0x350++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_4_0,Host1X Sync MLOCK Owner 4_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_4 ,Mlock owner chid 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_4 ,MLOCK CPU owns 4" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_4 ,MLOCK CH owns 4" "Not owned,Owned"
|
|
rgroup.long 0x354++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_5_0,Host1X Sync MLOCK Owner 5_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_5 ,Mlock owner chid 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_5 ,MLOCK CPU owns 5" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_5 ,MLOCK CH owns 5" "Not owned,Owned"
|
|
rgroup.long 0x358++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_6_0,Host1X Sync MLOCK Owner 6_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_6 ,Mlock owner chid 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_6 ,MLOCK CPU owns 6" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_6 ,MLOCK CH owns 6" "Not owned,Owned"
|
|
rgroup.long 0x35C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_7_0,Host1X Sync MLOCK Owner 7_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_7 ,Mlock owner chid 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_7 ,MLOCK CPU owns 7" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_7 ,MLOCK CH owns 7" "Not owned,Owned"
|
|
rgroup.long 0x360++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_8_0,Host1X Sync MLOCK Owner 8_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_8 ,Mlock owner chid 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_8 ,MLOCK CPU owns 8" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_8 ,MLOCK CH owns 8" "Not owned,Owned"
|
|
rgroup.long 0x364++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_9_0,Host1X Sync MLOCK Owner 9_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_9 ,Mlock owner chid 9" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_9 ,MLOCK CPU owns 9" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_9 ,MLOCK CH owns 9" "Not owned,Owned"
|
|
rgroup.long 0x368++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_10_0,Host1X Sync MLOCK Owner 10_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_10 ,Mlock owner chid 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_10 ,MLOCK CPU owns 10" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_10 ,MLOCK CH owns 10" "Not owned,Owned"
|
|
rgroup.long 0x36C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_11_0,Host1X Sync MLOCK Owner 11_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_11 ,Mlock owner chid 11" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_11 ,MLOCK CPU owns 11" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_11 ,MLOCK CH owns 11" "Not owned,Owned"
|
|
rgroup.long 0x370++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_12_0,Host1X Sync MLOCK Owner 12_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_12 ,Mlock owner chid 12" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_12 ,MLOCK CPU owns 12" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_12 ,MLOCK CH owns 12" "Not owned,Owned"
|
|
rgroup.long 0x374++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_13_0,Host1X Sync MLOCK Owner 13_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_13 ,Mlock owner chid 13" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_13 ,MLOCK CPU owns 13" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_13 ,MLOCK CH owns 13" "Not owned,Owned"
|
|
rgroup.long 0x378++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_14_0,Host1X Sync MLOCK Owner 14_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_14 ,Mlock owner chid 14" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_14 ,MLOCK CPU owns 14" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_14 ,MLOCK CH owns 14" "Not owned,Owned"
|
|
rgroup.long 0x37C++0x03
|
|
line.long 0x00 "SYNC_MLOCK_OWNER_15_0,Host1X Sync MLOCK Owner 15_0"
|
|
bitfld.long 0x00 8.--11. " MLOCK_OWNER_CHID_15 ,Mlock owner chid 15" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 1. " MLOCK_CPU_OWNS_15 ,MLOCK CPU owns 15" "Not owned,Owned"
|
|
bitfld.long 0x00 0. " MLOCK_CH_OWNS_15 ,MLOCK CH owns 15" "Not owned,Owned"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "SYNC_MLOCK_ERROR_0_0,Host1X Sync Mlock Error 0_0"
|
|
bitfld.long 0x00 15. " MLOCK_ERROR_15 ,Mlock error 15" "No error,Error"
|
|
bitfld.long 0x00 14. " MLOCK_ERROR_14 ,Mlock error 14" "No error,Error"
|
|
bitfld.long 0x00 13. " MLOCK_ERROR_13 ,Mlock error 13" "No error,Error"
|
|
bitfld.long 0x00 12. " MLOCK_ERROR_12 ,Mlock error 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MLOCK_ERROR_11 ,Mlock error 11" "No error,Error"
|
|
bitfld.long 0x00 10. " MLOCK_ERROR_10 ,Mlock error 10" "No error,Error"
|
|
bitfld.long 0x00 9. " MLOCK_ERROR_9 ,Mlock error 9" "No error,Error"
|
|
bitfld.long 0x00 8. " MLOCK_ERROR_8 ,Mlock error 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MLOCK_ERROR_7 ,Mlock error 7" "No error,Error"
|
|
bitfld.long 0x00 6. " MLOCK_ERROR_6 ,Mlock error 6" "No error,Error"
|
|
bitfld.long 0x00 5. " MLOCK_ERROR_5 ,Mlock error 5" "No error,Error"
|
|
bitfld.long 0x00 4. " MLOCK_ERROR_4 ,Mlock error 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MLOCK_ERROR_3 ,Mlock error 3" "No error,Error"
|
|
bitfld.long 0x00 2. " MLOCK_ERROR_2 ,Mlock error 2" "No error,Error"
|
|
bitfld.long 0x00 1. " MLOCK_ERROR_1 ,Mlock error 1" "No error,Error"
|
|
bitfld.long 0x00 0. " MLOCK_ERROR_0 ,Mlock error 0" "No error,Error"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_0_0,Host1X Sync Syncpt Base 0_0"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_1_0,Host1X Sync Syncpt Base 1_0"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_2_0,Host1X Sync Syncpt Base 2_0"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_3_0,Host1X Sync Syncpt Base 3_0"
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_4_0,Host1X Sync Syncpt Base 4_0"
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_5_0,Host1X Sync Syncpt Base 5_0"
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_6_0,Host1X Sync Syncpt Base 6_0"
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_7_0,Host1X Sync Syncpt Base 7_0"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_8_0,Host1X Sync Syncpt Base 8_0"
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_9_0,Host1X Sync Syncpt Base 9_0"
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_10_0,Host1X Sync Syncpt Base 10_0"
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_11_0,Host1X Sync Syncpt Base 11_0"
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_12_0,Host1X Sync Syncpt Base 12_0"
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_13_0,Host1X Sync Syncpt Base 13_0"
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_14_0,Host1X Sync Syncpt Base 14_0"
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_15_0,Host1X Sync Syncpt Base 15_0"
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_16_0,Host1X Sync Syncpt Base 16_0"
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_17_0,Host1X Sync Syncpt Base 17_0"
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_18_0,Host1X Sync Syncpt Base 18_0"
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_19_0,Host1X Sync Syncpt Base 19_0"
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_20_0,Host1X Sync Syncpt Base 20_0"
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_21_0,Host1X Sync Syncpt Base 21_0"
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_22_0,Host1X Sync Syncpt Base 22_0"
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_23_0,Host1X Sync Syncpt Base 23_0"
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_24_0,Host1X Sync Syncpt Base 24_0"
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_25_0,Host1X Sync Syncpt Base 25_0"
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_26_0,Host1X Sync Syncpt Base 26_0"
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_27_0,Host1X Sync Syncpt Base 27_0"
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_28_0,Host1X Sync Syncpt Base 28_0"
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_29_0,Host1X Sync Syncpt Base 29_0"
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_30_0,Host1X Sync Syncpt Base 30_0"
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_31_0,Host1X Sync Syncpt Base 31_0"
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_32_0,Host1X Sync Syncpt Base 32_0"
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_33_0,Host1X Sync Syncpt Base 33_0"
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_34_0,Host1X Sync Syncpt Base 34_0"
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_35_0,Host1X Sync Syncpt Base 35_0"
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_36_0,Host1X Sync Syncpt Base 36_0"
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_37_0,Host1X Sync Syncpt Base 37_0"
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_38_0,Host1X Sync Syncpt Base 38_0"
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_39_0,Host1X Sync Syncpt Base 39_0"
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_40_0,Host1X Sync Syncpt Base 40_0"
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_41_0,Host1X Sync Syncpt Base 41_0"
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_42_0,Host1X Sync Syncpt Base 42_0"
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_43_0,Host1X Sync Syncpt Base 43_0"
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_44_0,Host1X Sync Syncpt Base 44_0"
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_45_0,Host1X Sync Syncpt Base 45_0"
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_46_0,Host1X Sync Syncpt Base 46_0"
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_47_0,Host1X Sync Syncpt Base 47_0"
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_48_0,Host1X Sync Syncpt Base 48_0"
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_49_0,Host1X Sync Syncpt Base 49_0"
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_50_0,Host1X Sync Syncpt Base 50_0"
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_51_0,Host1X Sync Syncpt Base 51_0"
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_52_0,Host1X Sync Syncpt Base 52_0"
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_53_0,Host1X Sync Syncpt Base 53_0"
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_54_0,Host1X Sync Syncpt Base 54_0"
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_55_0,Host1X Sync Syncpt Base 55_0"
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_56_0,Host1X Sync Syncpt Base 56_0"
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_57_0,Host1X Sync Syncpt Base 57_0"
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_58_0,Host1X Sync Syncpt Base 58_0"
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_59_0,Host1X Sync Syncpt Base 59_0"
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_60_0,Host1X Sync Syncpt Base 60_0"
|
|
group.long 0x6F4++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_61_0,Host1X Sync Syncpt Base 61_0"
|
|
group.long 0x6F8++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_62_0,Host1X Sync Syncpt Base 62_0"
|
|
group.long 0x6FC++0x03
|
|
line.long 0x00 "SYNC_SYNCPT_BASE_63_0,Host1X Sync Syncpt Base 63_0"
|
|
tree.end
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "Video Image Compositor (VIC)"
|
|
base ad:0x54340000
|
|
width 19.
|
|
group.long 0x00++0x03 "THI (Tegra Host Interface) Registers"
|
|
line.long 0x00 "INCR_SYNCPT,INCR_SYNCPT"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NV_PVIC_THI_INCR_SYNCPT_COND ,NV_PVIC_THI_INCR_SYNCPT_COND"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NV_PVIC_THI_INCR_SYNCPT_INDX ,NV_PVIC_THI_INCR_SYNCPT_INDX"
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "INCR_SYNCPT_ERR,INCR_SYNCPT_ERR"
|
|
eventfld.long 0x00 1. " NV_PVIC_THI_INCR_SYNCPT_ERR_COND_STS_OPDONE ,NV_PVIC_THI_INCR_SYNCPT_ERR_COND_STS_OPDONE" "Init,Cleared"
|
|
eventfld.long 0x00 0. " NV_PVIC_THI_INCR_SYNCPT_ERR_COND_STS_IMM ,NV_PVIC_THI_INCR_SYNCPT_ERR_COND_STS_IMM" "Init,Cleared"
|
|
line.long 0x04 "CTXSW_INCR_SYNCPT,CTXSW_INCR_SYNCPT"
|
|
hexmask.long.byte 0x04 0.--7. 1. " NV_PVIC_THI_CTXSW_INCR_SYNCPT_INDX ,NV_PVIC_THI_CTXSW_INCR_SYNCPT_INDX"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CTXSW,CTXSW"
|
|
bitfld.long 0x00 28.--31. " NV_PVIC_THI_CTXSW_NEXT_CHANNEL ,NV_PVIC_THI_CTXSW_NEXT_CHANNEL" "Next channel init,..."
|
|
hexmask.long.word 0x00 16.--25. 1. " NV_PVIC_THI_CTXSW_NEXT_CLASS ,NV_PVIC_THI_CTXSW_NEXT_CLASS"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " NV_PVIC_THI_CTXSW_CURR_CHANNEL ,NV_PVIC_THI_CTXSW_CURR_CHANNEL " ",,,,,,,,,,,,,,,Current channel init"
|
|
rbitfld.long 0x00 11. " NV_PVIC_THI_CTXSW_AUTO_ACK ,NV_PVIC_THI_CTXSW_AUTO_ACK" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " NV_PVIC_THI_CTXSW_CURR_CLASS ,NV_PVIC_THI_CTXSW_CURR_CLASS"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CONT_SYNCPT_EOF,CONT_SYNCPT_EOF"
|
|
bitfld.long 0x00 8. " NV_PVIC_THI_CONT_SYNCPT_EOF_COND ,NV_PVIC_THI_CONT_SYNCPT_EOF_COND" "Enabled,Disabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NV_PVIC_THI_CONT_SYNCPT_EOF_INDEX ,NV_PVIC_THI_CONT_SYNCPT_EOF_INDEX"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "METHOD0,METHOD0 - Offset"
|
|
hexmask.long.word 0x00 0.--11. 1. " NV_PVIC_THI_METHOD0_OFFSET ,NV_PVIC_THI_METHOD0_OFFSET "
|
|
line.long 0x04 "METHOD1,METHOD1 - Data"
|
|
group.long 0x78++0x07
|
|
line.long 0x00 "INT_STATUS,INT_STATUS"
|
|
eventfld.long 0x00 0. " NV_PVIC_THI_INT_STATUS_FALCON_INT ,NV_PVIC_THI_INT_STATUS_FALCON_INT" "Init,Cleared"
|
|
line.long 0x04 "INT_MASK,INT_MASK"
|
|
bitfld.long 0x04 0. " NV_PVIC_THI_INT_MASK_FALCON_INT ,NV_PVIC_THI_INT_MASK_FALCON_INT" "Cleared,Init"
|
|
width 13.
|
|
group.long 0x1048++0x03 "HOSTIF Miscellaneous Registers"
|
|
line.long 0x00 "ITFEN,ITFEN"
|
|
bitfld.long 0x00 2. " NV_PVIC_FALCON_ITFEN_PRIV_POSTWR ,Indicates whether to use a post write on the main priv interface" "No,Yes"
|
|
bitfld.long 0x00 1. " NV_PVIC_FALCON_ITFEN_MTHDEN ,Method interface enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NV_PVIC_FALCON_ITFEN_CTXEN ,Context switch interface enable" "Disabled,Enabled"
|
|
group.long 0x1100++0x07 "Falcon UCTL Registers"
|
|
line.long 0x00 "CPUCTL,CPUCTL"
|
|
rbitfld.long 0x00 5. " NV_PVIC_FALCON_CPUCTL_STOPPED ,CPU is currently in the stopped state" "Not stopped,Stopped"
|
|
rbitfld.long 0x00 4. " NV_PVIC_FALCON_CPUCTL_HALTED ,CPU is currently in the halted state" "Not stopped,Stopped"
|
|
textline " "
|
|
eventfld.long 0x00 3. " NV_PVIC_FALCON_CPUCTL_HRESET ,Hard reset" "No reset,Reset"
|
|
eventfld.long 0x00 2. " NV_PVIC_FALCON_CPUCTL_SRESET ,Soft reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 1. " NV_PVIC_FALCON_CPUCTL_STARTCPU ,Set STARTCPU to TRUE to start CPU execution while in a HALTED state" "False,True"
|
|
eventfld.long 0x00 0. " NV_PVIC_FALCON_CPUCTL_IINVAL ,Set to TRUE to mark all blocks in IMEM except block 0 as INVALID" "False,True"
|
|
line.long 0x04 "BOOTVEC,BOOTVEC"
|
|
group.long 0x110C++0x13 "Falcon DMA Registers"
|
|
line.long 0x00 "DMACTL,DMACTL"
|
|
rbitfld.long 0x00 3.--6. " NV_PVIC_FALCON_DMACTL_DMAQ_NUM ,Valid request number at DMA request queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " NV_PVIC_FALCON_DMACTL_REQUIRE_CTX ,Valid context loaded before any DMA request" "Not loaded,Loaded"
|
|
line.long 0x04 "DMATRFBASE,DMATRFBASE"
|
|
line.long 0x08 "DMATRFMOFFS,IMEM/DMEM Offset for the transfer"
|
|
hexmask.long.word 0x08 0.--15. 1. " NV_PVIC_FALCON_DMATRFMOFFS_OFFS ,IMEM/DMEM Offset for the transfer"
|
|
line.long 0x0C "DMATRFCMD,DMATRFCMD"
|
|
bitfld.long 0x0C 12.--14. " NV_PVIC_FALCON_DMATRFCMD_CTXDMA ,NV_PVIC_FALCON_DMATRFCMD_CTXDMA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 8.--10. " NV_PVIC_FALCON_DMATRFCMD_SIZE ,NV_PVIC_FALCON_DMATRFCMD_SIZE" "4B,8B,16B,32B,64B,128B,256B,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 5. " NV_PVIC_FALCON_DMATRFCMD_WRITE , NV_PVIC_FALCON_DMATRFCMD_WRITE" "False,True"
|
|
bitfld.long 0x0C 4. " NV_PVIC_FALCON_DMATRFCMD_IMEM , NV_PVIC_FALCON_DMATRFCMD_IMEM" "False,True"
|
|
textline " "
|
|
rbitfld.long 0x0C 1. " NV_PVIC_FALCON_DMATRFCMD_IDLE ,DMA engine is still busy with a transfer" "Idle,Busy"
|
|
rbitfld.long 0x0C 0. " NV_PVIC_FALCON_DMATRFCMD_FULL ,DMA request queue is full" "Not full,Full"
|
|
line.long 0x10 "DMATRFFBOFFS,Frame buffer offset for the transfer"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Flow Controller"
|
|
base ad:0x60007000
|
|
width 23.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "HALT_CPU_EVENTS_0,Halt Cpu Events"
|
|
bitfld.long 0x00 29.--31. " MODE ,Flow Mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. " JTAG ,Resume on JTAG activity" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SCLK ,Resume on Nth SYSCLK cycle ticks" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " X32K ,Resume on Nth X32K clock input ticks" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " uSEC ,Resume on Nth uSEC clock ticks" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MSEC ,Resume on Nth mSEC clock ticks" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SEC ,Resume on Nth second RTC clock ticks" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " X_RDY ,Resume on Nth XIO.RDY" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMP31 ,Semaphore set events" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMP30 ,Semaphore set events" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " XRQ_D ,External Trigger events" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " XRQ_C ,External Trigger events" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " XRQ_B ,External Trigger events" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " XRQ_A ,External Trigger events" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " OBE ,Resume OBE" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " OBF ,Resume OBF" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IBE ,Resume IBE" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " IBF ,Resume IBF" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " LIC_IRQ ,Resume on LIC_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LIC_FIQ ,Resume on LIC_FIQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GIC_IRQ ,Resume on GIC_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GIC_FIQ ,Resume on GIC_FIQ" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ZERO ,Initialized then decremented"
|
|
textline " "
|
|
line.long 0x04 "HALT_COP_EVENTS_0,Halt Cop Events"
|
|
bitfld.long 0x04 29.--31. " MODE ,Flow Mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 28. " JTAG ,Resume on JTAG activity" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " SCLK ,Resume on Nth SYSCLK cycle ticks" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " X32K ,Resume on Nth X32K clock input ticks" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " uSEC ,Resume on Nth uSEC clock ticks" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " MSEC ,Resume on Nth mSEC clock ticks" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " SEC ,Resume on Nth second RTC clock ticks" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " X_RDY ,Resume on Nth XIO.RDY" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SMP31 ,Semaphore set events" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " SMP30 ,Semaphore set events" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " XRQ_D ,External Trigger events" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " XRQ_C ,External Trigger events" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " XRQ_B ,External Trigger events" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " XRQ_A ,External Trigger events" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " OBE ,Resume OBE" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " OBF ,Resume OBF" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " IBE ,Resume IBE" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " IBF ,Resume IBF" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " LIC_IRQ ,Resume on LIC_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LIC_FIQ ,Resume on LIC_FIQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " GIC_IRQ ,Resume on GIC_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " GIC_FIQ ,Resume on GIC_FIQ" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ZERO ,Initialized then decremented"
|
|
textline " "
|
|
line.long 0x08 "CPU_CSR_0 ,CPU Control/Status Register 0"
|
|
rbitfld.long 0x08 24.--27. " PWR_STATE ,Current state of the PowerGate State Machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x08 23. " WAIT_EVENT ,CPU is waiting" "Disabled,Enabled"
|
|
rbitfld.long 0x08 22. " HALT ,CPU is halted" "Disabled,Enabled"
|
|
rbitfld.long 0x08 21. " P2F_ACK ,Pmc2flow_ack signal" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " F2P_PWRUP ,Flow2pmc_pwrup" "Disabled,Enabled"
|
|
rbitfld.long 0x08 19. " F2P_REQ ,Flow2pmc_req valid" "Disabled,Enabled"
|
|
rbitfld.long 0x08 17. " F2C_MPCORE_RST ,Requesting reset of MPCore" "Disabled,Enabled"
|
|
rbitfld.long 0x08 16. " PWR_OFF_STS ,CPU Power-Gated is OFF by Flow Controller" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 15. " INTR_FLAG ,TRUE when Interrupt is Active" "Disabled,Enabled"
|
|
eventfld.long 0x08 14. " EVENT_FLAG ,TRUE when Event is Active" "Disabled,Enabled"
|
|
bitfld.long 0x08 12.--13. " ENABLE_EXT ,specifies what to power off" "Power Gate CPU,Power Gate CPU/non-CPU,,PG Emulation"
|
|
bitfld.long 0x08 8.--11. " WAIT_WFI_BITMAP ,All cores indicated in bitmap must be in STANDBY_WFI before switching Cluster" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 3. " IMMEDIATE_WAKE ,CPU is powered up immediately" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SWITCH_CLUSTER ,The active cluster will be switched when all indicated CPU reach STANDBY_WFI" "0,1"
|
|
bitfld.long 0x08 1. " EVENT_ENABLE ,Generates an event when the flow controller exits the halted state" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ENABLE ,Halt or Event-wait causes CPU power-gating" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x0C "COP_CSR_0,COP Control/Status for Interrupts"
|
|
bitfld.long 0x0C 15. " INTR_FLAG ,Interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "XRQ_EVENTS_0,XRQ Event Detect Selector Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " XRQ_D7_XRQ_D0 ,XRQ_D7_XRQ_D0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " XRQ_C7_XRQ_C0 ,XRQ_C7_XRQ_C0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " XRQ_B7_XRQ_B0 ,XRQ_B7_XRQ_B0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " XRQ_A7_XRQ_A0 ,XRQ_A7_XRQ_A0"
|
|
textline " "
|
|
line.long 0x04 "HALT_CPU1_EVENTS_0,Halt Cpu Events"
|
|
bitfld.long 0x04 29.--31. " MODE ,Flow Mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 28. " JTAG ,Resume on JTAG activity" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " SCLK ,Resume on Nth SYSCLK cycle ticks" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " X32K ,Resume on Nth X32K clock input ticks" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " uSEC ,Resume on Nth uSEC clock ticks" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " MSEC ,Resume on Nth mSEC clock ticks" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " SEC ,Resume on Nth second RTC clock ticks" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " X_RDY ,Resume on Nth XIO.RDY" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SMP31 ,Semaphore set events" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " SMP30 ,Semaphore set events" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " XRQ_D ,External Trigger events" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " XRQ_C ,External Trigger events" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " XRQ_B ,External Trigger events" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " XRQ_A ,External Trigger events" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " OBE ,Resume OBE" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " OBF ,Resume OBF" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " IBE ,Resume IBE" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " IBF ,Resume IBF" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " LIC_IRQ ,Resume on LIC_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LIC_FIQ ,Resume on LIC_FIQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " GIC_IRQ ,Resume on GIC_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " GIC_FIQ ,Resume on GIC_FIQ" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ZERO ,Initialized then decremented"
|
|
textline " "
|
|
line.long 0x08 "CPU1_CSR_0 ,CPU Control/Status Register 0"
|
|
rbitfld.long 0x08 24.--27. " PWR_STATE ,Current state of the PowerGate State Machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x08 23. " WAIT_EVENT ,CPU is waiting" "Disabled,Enabled"
|
|
rbitfld.long 0x08 22. " HALT ,CPU is halted" "Disabled,Enabled"
|
|
rbitfld.long 0x08 21. " P2F_ACK ,Pmc2flow_ack signal" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " F2P_PWRUP ,Flow2pmc_pwrup" "Disabled,Enabled"
|
|
rbitfld.long 0x08 19. " F2P_REQ ,Flow2pmc_req valid" "Disabled,Enabled"
|
|
rbitfld.long 0x08 17. " F2C_MPCORE_RST ,Requesting reset of MPCore" "Disabled,Enabled"
|
|
rbitfld.long 0x08 16. " PWR_OFF_STS ,CPU Power-Gated is OFF by Flow Controller" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 15. " INTR_FLAG ,TRUE when Interrupt is Active" "Disabled,Enabled"
|
|
eventfld.long 0x08 14. " EVENT_FLAG ,TRUE when Event is Active" "Disabled,Enabled"
|
|
bitfld.long 0x08 12.--13. " ENABLE_EXT ,specifies what to power off" "Power Gate CPU,Power Gate CPU/non-CPU,,PG Emulation"
|
|
bitfld.long 0x08 8.--11. " WAIT_WFI_BITMAP ,All cores indicated in bitmap must be in STANDBY_WFI before switching Cluster" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 3. " IMMEDIATE_WAKE ,CPU is powered up immediately" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SWITCH_CLUSTER ,The active cluster will be switched when all indicated CPU reach STANDBY_WFI" "0,1"
|
|
bitfld.long 0x08 1. " EVENT_ENABLE ,Generates an event when the flow controller exits the halted state" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ENABLE ,Halt or Event-wait causes CPU power-gating" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x1C++0x0F
|
|
line.long 0x00 "HALT_CPU2_EVENTS_0,Halt Cpu Events"
|
|
bitfld.long 0x00 29.--31. " MODE ,Flow Mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. " JTAG ,Resume on JTAG activity" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SCLK ,Resume on Nth SYSCLK cycle ticks" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " X32K ,Resume on Nth X32K clock input ticks" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " uSEC ,Resume on Nth uSEC clock ticks" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MSEC ,Resume on Nth mSEC clock ticks" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SEC ,Resume on Nth second RTC clock ticks" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " X_RDY ,Resume on Nth XIO.RDY" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMP31 ,Semaphore set events" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMP30 ,Semaphore set events" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " XRQ_D ,External Trigger events" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " XRQ_C ,External Trigger events" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " XRQ_B ,External Trigger events" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " XRQ_A ,External Trigger events" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " OBE ,Resume OBE" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " OBF ,Resume OBF" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IBE ,Resume IBE" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " IBF ,Resume IBF" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " LIC_IRQ ,Resume on LIC_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " LIC_FIQ ,Resume on LIC_FIQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GIC_IRQ ,Resume on GIC_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GIC_FIQ ,Resume on GIC_FIQ" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ZERO ,Initialized then decremented"
|
|
textline " "
|
|
line.long 0x04 "CPU2_CSR_0 ,CPU Control/Status Register 0"
|
|
rbitfld.long 0x04 24.--27. " PWR_STATE ,Current state of the PowerGate State Machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 23. " WAIT_EVENT ,CPU is waiting" "Disabled,Enabled"
|
|
rbitfld.long 0x04 22. " HALT ,CPU is halted" "Disabled,Enabled"
|
|
rbitfld.long 0x04 21. " P2F_ACK ,Pmc2flow_ack signal" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 20. " F2P_PWRUP ,Flow2pmc_pwrup" "Disabled,Enabled"
|
|
rbitfld.long 0x04 19. " F2P_REQ ,Flow2pmc_req valid" "Disabled,Enabled"
|
|
rbitfld.long 0x04 17. " F2C_MPCORE_RST ,Requesting reset of MPCore" "Disabled,Enabled"
|
|
rbitfld.long 0x04 16. " PWR_OFF_STS ,CPU Power-Gated is OFF by Flow Controller" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x04 15. " INTR_FLAG ,TRUE when Interrupt is Active" "Disabled,Enabled"
|
|
eventfld.long 0x04 14. " EVENT_FLAG ,TRUE when Event is Active" "Disabled,Enabled"
|
|
bitfld.long 0x04 12.--13. " ENABLE_EXT ,specifies what to power off" "Power Gate CPU,Power Gate CPU/non-CPU,CPU Turn off/CPU Rail,PG Emulation"
|
|
bitfld.long 0x04 8.--11. " WAIT_WFI_BITMAP ,All cores indicated in bitmap must be in STANDBY_WFI before switching Cluster" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 3. " IMMEDIATE_WAKE ,CPU is powered up immediately" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SWITCH_CLUSTER ,The active cluster will be switched when all indicated CPU reach STANDBY_WFI" "0,1"
|
|
bitfld.long 0x04 1. " EVENT_ENABLE ,Generates an event when the flow controller exits the halted state" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " ENABLE ,Halt or Event-wait causes CPU power-gating" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x08 "HALT_CPU3_EVENTS_0,Halt Cpu Events"
|
|
bitfld.long 0x08 29.--31. " MODE ,Flow Mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 28. " JTAG ,Resume on JTAG activity" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " SCLK ,Resume on Nth SYSCLK cycle ticks" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " X32K ,Resume on Nth X32K clock input ticks" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " uSEC ,Resume on Nth uSEC clock ticks" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " MSEC ,Resume on Nth mSEC clock ticks" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " SEC ,Resume on Nth second RTC clock ticks" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " X_RDY ,Resume on Nth XIO.RDY" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SMP31 ,Semaphore set events" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " SMP30 ,Semaphore set events" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " XRQ_D ,External Trigger events" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " XRQ_C ,External Trigger events" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " XRQ_B ,External Trigger events" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " XRQ_A ,External Trigger events" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " OBE ,Resume OBE" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " OBF ,Resume OBF" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " IBE ,Resume IBE" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " IBF ,Resume IBF" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " LIC_IRQ ,Resume on LIC_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " LIC_FIQ ,Resume on LIC_FIQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " GIC_IRQ ,Resume on GIC_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " GIC_FIQ ,Resume on GIC_FIQ" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 0.--7. 1. " ZERO ,Initialized then decremented"
|
|
textline " "
|
|
group.long 0x28++0x0F
|
|
line.long 0x00 "CPU3_CSR_0 ,CPU Control/Status Register 0"
|
|
rbitfld.long 0x00 24.--27. " PWR_STATE ,Current state of the PowerGate State Machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 23. " WAIT_EVENT ,CPU is waiting" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " HALT ,CPU is halted" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21. " P2F_ACK ,Pmc2flow_ack signal" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 20. " F2P_PWRUP ,Flow2pmc_pwrup" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " F2P_REQ ,Flow2pmc_req valid" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " F2C_MPCORE_RST ,Requesting reset of MPCore" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16. " PWR_OFF_STS ,CPU Power-Gated is OFF by Flow Controller" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 15. " INTR_FLAG ,TRUE when Interrupt is Active" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " EVENT_FLAG ,TRUE when Event is Active" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " ENABLE_EXT ,specifies what to power off" "Power Gate CPU,Power Gate CPU/non-CPU,CPU Turn Off/CPU Rail,PG Emulation"
|
|
bitfld.long 0x00 8.--11. " WAIT_WFI_BITMAP ,All cores indicated in bitmap must be in STANDBY_WFI before switching Cluster" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IMMEDIATE_WAKE ,CPU is powered up immediately" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SWITCH_CLUSTER ,The active cluster will be switched when all indicated CPU reach STANDBY_WFI" "0,1"
|
|
bitfld.long 0x00 1. " EVENT_ENABLE ,Generates an event when the flow controller exits the halted state" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Halt or Event-wait causes CPU power-gating" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "CLUSTER_CONTROL_0,Cluster Control 0"
|
|
hexmask.long.word 0x04 20.--31. 1. " POST_SWITCH_DELAY ,Two delays on top of the built in pipeline delay when switching cluster"
|
|
hexmask.long.word 0x04 8.--19. 1. " PRE_SWITCH_DELAY ,Pre switch delay"
|
|
bitfld.long 0x04 0. " ACTIVE ,Active" "G,LP"
|
|
textline " "
|
|
line.long 0x08 "HALT_COP1_EVENTS_0,Halt Cop Events"
|
|
bitfld.long 0x08 29.--31. " MODE ,Flow Mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 28. " JTAG ,Resume on JTAG activity" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " SCLK ,Resume on Nth SYSCLK cycle ticks" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " X32K ,Resume on Nth X32K clock input ticks" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " uSEC ,Resume on Nth uSEC clock ticks" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " MSEC ,Resume on Nth mSEC clock ticks" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " SEC ,Resume on Nth second RTC clock ticks" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " X_RDY ,Resume on Nth XIO.RDY" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SMP31 ,Semaphore set events" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " SMP30 ,Semaphore set events" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " XRQ_D ,External Trigger events" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " XRQ_C ,External Trigger events" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " XRQ_B ,External Trigger events" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " XRQ_A ,External Trigger events" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " OBE ,Resume OBE" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " OBF ,Resume OBF" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " IBE ,Resume IBE" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " IBF ,Resume IBF" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " LIC_IRQ ,Resume on LIC_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " LIC_FIQ ,Resume on LIC_FIQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " GIC_IRQ ,Resume on GIC_IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " GIC_FIQ ,Resume on GIC_FIQ" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 0.--7. 1. " ZERO ,Initialized then decremented"
|
|
textline " "
|
|
line.long 0x0C "COP1_CSR_0 ,CPU Control/Status Register 0"
|
|
rbitfld.long 0x0C 24.--27. " PWR_STATE ,Current state of the PowerGate State Machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x0C 23. " WAIT_EVENT ,CPU is waiting" "Disabled,Enabled"
|
|
rbitfld.long 0x0C 22. " HALT ,CPU is halted" "Disabled,Enabled"
|
|
rbitfld.long 0x0C 21. " P2F_ACK ,Pmc2flow_ack signal" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0C 20. " F2P_PWRUP ,Flow2pmc_pwrup" "Disabled,Enabled"
|
|
rbitfld.long 0x0C 19. " F2P_REQ ,Flow2pmc_req valid" "Disabled,Enabled"
|
|
rbitfld.long 0x0C 17. " F2C_MPCORE_RST ,Requesting reset of MPCore" "Disabled,Enabled"
|
|
rbitfld.long 0x0C 16. " PWR_OFF_STS ,CPU Power-Gated is OFF by Flow Controller" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 15. " INTR_FLAG ,TRUE when Interrupt is Active" "Disabled,Enabled"
|
|
eventfld.long 0x0C 14. " EVENT_FLAG ,TRUE when Event is Active" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12.--13. " ENABLE_EXT ,specifies what to power off" "Power Gate CPU,Power Gate CPU/non-CPU,CPU Turn Off/CPU Rail,PG Emulation"
|
|
bitfld.long 0x0C 8.--11. " WAIT_WFI_BITMAP ,All cores indicated in bitmap must be in STANDBY_WFI before switching Cluster" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " IMMEDIATE_WAKE ,CPU is powered up immediately" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SWITCH_CLUSTER ,The active cluster will be switched when all indicated CPU reach STANDBY_WFI" "0,1"
|
|
bitfld.long 0x0C 1. " EVENT_ENABLE ,Generates an event when the flow controller exits the halted state" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " ENABLE ,Halt or Event-wait causes CPU power-gating" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x38++0x0F
|
|
line.long 0x00 "CPU_PWR_CSR_0,CPU PWR Control/Status Register 0"
|
|
bitfld.long 0x00 8. " CPU_RG_CFG ,Flow controller would initiate last CPU PG with CPU RG or non-CPU PG" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " C1NC_STS ,C1NC Status" "Partition_off,PG_in_progress,PU_in_progress,Partition_on"
|
|
bitfld.long 0x00 4.--5. " C0NC_STS ,C0NC Status" "Partition_off,PG_in_progress,PU_in_progress,Partition_on"
|
|
bitfld.long 0x00 3. " USE_FLOW_STS ,Use flow status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " RAIL_STS ,Hardware updates this register based on the current status of the CPU-rail" "Rail_off,RG_in_progress,RU_in_progress,Rail_on"
|
|
bitfld.long 0x00 0. " RAIL_ENABLE ,CPU rail power on request" "Disabled,Enabled"
|
|
line.long 0x04 "MPID_0,MPID 0"
|
|
bitfld.long 0x04 0.--1. " CPU_ID ,This ID is provided to MPCore_LP which is what is read when the OS reads MPIDR" "0,1,2,3"
|
|
line.long 0x08 "RAM_REPAIR_0,RAM_REPAIR_0"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DBG_STS ,Repair done from repair logic"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DBG_REQ ,Repair request for individual segments"
|
|
bitfld.long 0x08 3. " DBG_EN ,Debug enable to be able to repair of individual segments of the cluster0 repair chain" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " BYPASS_EN ,RAM repair bypass enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x08 1. " STS ,Indicates Cluster repair chain status" "0,1"
|
|
bitfld.long 0x08 0. " REQ ,Cluster0 RAM repair request" "Disabled,Enabled"
|
|
line.long 0x0C "FLOW_DBG_SEL_0 ,FLOW_DBG_SEL_0"
|
|
rbitfld.long 0x0C 18.--19. " RG_PWR_STATE ,Current state of Rail Gate state machine" "0,1,2,3"
|
|
rbitfld.long 0x0C 16.--17. " RU_PWR_STATE ,Current state of Rail Ungate state machine" "0,1,2,3"
|
|
rbitfld.long 0x0C 14.--15. " NC_PG_PWR_STATE ,Current state of Non CPU Power Gate state machine" "0,1,2,3"
|
|
rbitfld.long 0x0C 12.--13. " NC_PU_PWR_STATE ,Current state of Non CPU Power Ungate state machine" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--11. " CNT1_SEL ,Activity selection which would be counted by CNT1" "IDLE,CPU0_PG,CPU1_PG,CPU2_PG,CPU3_PG,CPU0123_PG,CPULP_PG,C0NC_PG,C1NC_PG,CRAIL_OFF,C0_TO_C1_SWITCH,C1_TO_C0_SWITCH,..."
|
|
bitfld.long 0x0C 0.--3. " CNT0_SEL ,Activity selection which would be counted by CNT0" "IDLE,CPU0_PG,CPU1_PG,CPU2_PG,CPU3_PG,CPU0123_PG,CPULP_PG,C0NC_PG,C1NC_PG,CRAIL_OFF,C0_TO_C1_SWITCH,C1_TO_C0_SWITCH,..."
|
|
group.long 0x48++0x0F
|
|
line.long 0x00 "FLOW_DBG_CNT0_0,FLOW_DBG_CNT0_0"
|
|
line.long 0x04 "FLOW_DBG_CNT1_0,FLOW_DBG_CNT1_0"
|
|
line.long 0x08 "FLOW_DBG_QUAL_0 ,Flow Ctlr Flow Dbg Qual 0"
|
|
bitfld.long 0x08 24.--27. " AXICIF_CG_DIS ,CCPLEX AXICIF/MCCIF clock gating disable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 16.--20. " PWRUPREQ_QUAL ,CPU DBGPWRUPREQ qualifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 8.--12. " NOPWRDWN_QUAL ,CPU DBGNOPPWRDN qualifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 0.--4. " PWRDNREQ_QUAL ,CPU DBGPWRDNREQ qualifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "FLOW_CTLR_SPARE_0,FLOW_CTLR_FLOW_CTLR_SPARE_0"
|
|
hexmask.long.word 0x0C 16.--31. 1. " SPARE_HI ,Spare high"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SPARE_LO ,Spare low"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "RAM_REPAIR_CLUSTER1_0,Ram Repair Cluster 1 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DBG_STS ,Repair done from repair logic"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DBG_REQ ,Repair request for individual segemnts"
|
|
bitfld.long 0x00 3. " DBG_EN ,Debug enable to be able to repair of individual segments of the cluster0 repair chain" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " STS ,Indicates Cluster repair chain status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " REQ ,Cluster1 RAM repair request" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "Memory Controller"
|
|
tree "MC"
|
|
base ad:0x70019000
|
|
width 21.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "INTSTATUS_0,MC Interrupt Status register"
|
|
bitfld.long 0x00 16. " DECERR_MTS_INT ,Access violation on MTS carveout region in the MC" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " SECERR_SEC_INT ,The request violated the SEC Carveout requirements" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " DECERR_VPR_INT ,The request violated the VPR requirements" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INVALID_APB_ASID_UPDATE_INT ,ASID Update through APB interface resulted in an error" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " INVALID_SMMU_PAGE_INT ,Address translation error" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " ARBITRATION_EMEM_INT ,Warning that a pending request has reached the deadlock-prevention slack threshold" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SECURITY_VIOLATION_INT ,Address translation error: Nonsecure access was attempted to a secured region" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " DECERR_EMEM_INT ,Address translation error: EMEM Address Decode Error" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTMASK_0,MC Interrupt Masks register"
|
|
bitfld.long 0x04 16. " DECERR_MTS_INTMASK ,DECERR_MTS (Access violation on MTS carveout region in the MC) Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 13. " SECERR_SEC_INTMASK ,SECERR_SEC (The request violated the SEC Carveout requirements) Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 12. " DECERR_VPR_INTMASK ,DECERR_VPR (The request violated the VPR requirements) Interrupt Mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INVALID_APB_ASID_UPDATE_INTMASK ,INVALID_APB_ASID_UPDATE (ASID Update through APB interface resulted in an error) Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 10. " INVALID_SMMU_PAGE_INTMASK ,INVALID_SMMU_PAGE (Address translation error) Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " ARBITRATION_EMEM_INTMASK , ARBITRATION_EMEM (Warning that a pending request has reached the deadlock-prevention slack threshold) Interrupt Mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " SECURITY_VIOLATION_INTMASK ,SECURITY_VIOLATION (Nonsecure access was attempted to a secured region) Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 6. " DECERR_EMEM_INTMASK ,DECERR_EMEM (EMEM Address Decode Error) Interrupt Mask" "Masked,Unmasked"
|
|
textline " "
|
|
if ((d.l(ad:0x70019000+0x08)&0x70000000)==0x60000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ERR_STATUS_0,MC Error Data Capture: Status"
|
|
bitfld.long 0x00 28.--30. " ERR_TYPE ,Type of the corresponding error" ",,DECERR_EMEM,SECURITY_TRUSTZONE,,,INVALID_SMMU_PAGE,?..."
|
|
bitfld.long 0x00 27. " ERR_INVALID_SMMU_PAGE_READABLE ,INVALID_SMMU_PAGE error: Page permission was readable" "Not readable,Readable"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ERR_INVALID_SMMU_PAGE_WRITABLE ,INVALID_SMMU_PAGE error: Page permission was writeable" "Not writeable,Writeable"
|
|
bitfld.long 0x00 25. " ERR_INVALID_SMMU_PAGE_NONSECURE ,INVALID_SMMU_PAGE error: Page permission was non-secure" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " ERR_ADR_HI ,Higher address bits of erring address whose lower bits are available in ERR_ADR register" "b00,b01,b10,b11"
|
|
bitfld.long 0x00 18. " ERR_SWAP ,Swap bit for transaction" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ERR_SECURITY ,Transaction security" "NONSECURE,SECURE"
|
|
bitfld.long 0x00 16. " ERR_RW ,Direction of the access that caused the error" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " ERR_ADR1 , Second subpartition unique address bits" "b000,b001,b010,b011,b100,b101,b110,b111"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_ID ,Client identifier of the access that caused the error"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ERR_STATUS_0,MC Error Data Capture: Status"
|
|
bitfld.long 0x00 28.--30. " ERR_TYPE ,Type of the corresponding error" ",,DECERR_EMEM,SECURITY_TRUSTZONE,,,INVALID_SMMU_PAGE,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " ERR_ADR_HI ,Higher address bits of erring address whose lower bits are available in ERR_ADR register" "b00,b01,b10,b11"
|
|
bitfld.long 0x00 18. " ERR_SWAP ,Swap bit for transaction" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ERR_SECURITY ,Transaction security" "NONSECURE,SECURE"
|
|
bitfld.long 0x00 16. " ERR_RW ,Direction of the access that caused the error" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " ERR_ADR1 , Second subpartition unique address bits" "b000,b001,b010,b011,b100,b101,b110,b111"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_ID ,Client identifier of the access that caused the error"
|
|
endif
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ERR_ADR_0,MC Error Data Capture: Address"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "SMMU_CONFIG_0,MC SMMU enable register"
|
|
bitfld.long 0x00 0. " SMMU_ENABLE ,SMMU Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SMMU_TLB_CONFIG_0,Translation lookaside buffer config register"
|
|
bitfld.long 0x04 31. " TLB_STATS_ENABLE ,Enable TLB Hit and Miss counters" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " TLB_STATS_TEST ,Set stats regs to all 1s" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " TLB_HIT_UNDER_MISS ,Allow hits to pass misses in the TLB" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " TLB_ROUND_ROBIN_ARBITRATION ,Forces round robin arbitration between TLB hit and miss FIFOs" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--4. " TLB_ACTIVE_LINES ,Set the number of active lines" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "SMMU_PTC_CONFIG_0,Page table cache config register"
|
|
bitfld.long 0x08 31. " PTC_STATS_ENABLE ,Enable PTC hit and miss counters" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " PTC_STATS_TEST ,Set stats regs to all 1s" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " PTC_CACHE_ENABLE ,Enable the PTC cache" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 24.--27. " PTC_REQ_LIMIT ,Limit outstanding PTC fill requests to the DRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x08 0.--5. 1. " PTC_INDEX_MAP ,XOR pattern for tag generation"
|
|
line.long 0x0C "SMMU_PTB_ASID_0,Page table base ASID register"
|
|
hexmask.long.byte 0x0C 0.--6. 1. " CURRENT_ASID ,ASID used to address SMMUT_PTB register"
|
|
line.long 0x10 "SMMU_PTB_DATA_0,Page table base data register"
|
|
bitfld.long 0x10 31. " ASID_READABLE ,Allow reads for this ASID" "Not allowed,Allowed"
|
|
bitfld.long 0x10 30. " ASID_WRITEABLE ,Allow writes for this ASID" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x10 29. " ASID_NONSECUR ,Allow non-secure access for this ASID" "Not allowed,Allowed"
|
|
hexmask.long.tbyte 0x10 0.--21. 1. " ASID_PDE_BASE ,Pointer to page of PDEs"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SMMU_TLB_FLUSH_0,Translation lookaside buffer flush register"
|
|
bitfld.long 0x00 31. " TLB_FLUSH_ASID_MATCH ,Only entries matching TLB_FLUSH_ASID are flushed" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " TLB_FLUSH_ASID ,ASID to match"
|
|
hexmask.long.tbyte 0x00 2.--19. 1. " TLB_FLUSH_VA_GROUP ,Virtual address to match for group flashes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TLB_FLUSH_VA_MATCH ,Flushing control" "All,,Section,Group"
|
|
line.long 0x04 "SMMU_PTC_FLUSH_0,Page table cache flush register"
|
|
hexmask.long 0x04 4.--31. 0x10 " PTC_FLUSH_ADR ,Physical address of PTE group"
|
|
bitfld.long 0x04 3. " PTC_NO_WAIT_IDLE_FLUSH ,Set bit to immediately flush without waiting for hit FIFO to go idle" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PTC_FLUSH_TYPE ,Flushing control (Flush entire PTC ADR, or only the one adressed by ADR)" "All,Adr"
|
|
textline " "
|
|
if (((d.l(ad:0x70019000+0x664))&0x01)==0x00)
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "EMEM_CFG_0,External memory aperture configuration"
|
|
bitfld.long 0x00 31. " EMEM_DOM ,Base of DRAM memory in GBs" "B2GB,B0GB"
|
|
hexmask.long.word 0x00 0.--13. 1. " EMEM_SIZE_MB ,External memory aperture size in megabytes"
|
|
line.long 0x04 "EMEM_ADR_CFG_0,External memory address configuration for system"
|
|
bitfld.long 0x04 0. " EMEM_NUMDEV ,Number of populated DRAM devices" "N1,N2"
|
|
line.long 0x08 "EMEM_ADR_CFG_DEV0_0,External memory address configuration for device 0"
|
|
bitfld.long 0x08 16.--19. " EMEM_DEV0_DEVSIZE ,Density of the first attached DRAM device" ",,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,768MB,?..."
|
|
bitfld.long 0x08 8.--9. " EMEM_DEV0_BANKWIDTH ,Width of bank address of the first attached DRAM device" ",,W2,W3"
|
|
bitfld.long 0x08 0.--2. " EMEM_DEV0_COLWIDTH ,Width of column address of the first attached DRAM device" ",W8,W9,W10,W11,W12,?..."
|
|
line.long 0x0C "EMEM_ADR_CFG_DEV1_0,External memory address configuration for device 1"
|
|
bitfld.long 0x0C 16.--19. " EMEM_DEV1_DEVSIZE ,Density of the first attached DRAM device" ",,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,768MB,?..."
|
|
bitfld.long 0x0C 8.--9. " EMEM_DEV1_BANKWIDTH ,Width of bank address of the first attached DRAM device" ",,W2,W3"
|
|
bitfld.long 0x0C 0.--2. " EMEM_DEV1_COLWIDTH ,Width of column address of the first attached DRAM device" ",W8,W9,W10,W11,W12,?..."
|
|
else
|
|
rgroup.long 0x50++0x0F
|
|
line.long 0x00 "EMEM_CFG_0,External memory aperture configuration"
|
|
bitfld.long 0x00 31. " EMEM_DOM ,Base of DRAM memory in GBs" "B2GB,B0GB"
|
|
hexmask.long.word 0x00 0.--13. 1. " EMEM_SIZE_MB ,External memory aperture size in megabytes"
|
|
line.long 0x04 "EMEM_ADR_CFG_0,External memory address configuration for system"
|
|
bitfld.long 0x04 0. " EMEM_NUMDEV ,Number of populated DRAM devices" "N1,N2"
|
|
line.long 0x08 "EMEM_ADR_CFG_DEV0_0,External memory address configuration for device 0"
|
|
bitfld.long 0x08 16.--19. " EMEM_DEV0_DEVSIZE ,Density of the first attached DRAM device" ",,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,768MB,?..."
|
|
bitfld.long 0x08 8.--9. " EMEM_DEV0_BANKWIDTH ,Width of bank address of the first attached DRAM device" ",,W2,W3"
|
|
bitfld.long 0x08 0.--2. " EMEM_DEV0_COLWIDTH ,Width of column address of the first attached DRAM device" ",W8,W9,W10,W11,W12,?..."
|
|
line.long 0x0C "EMEM_ADR_CFG_DEV1_0,External memory address configuration for device 1"
|
|
bitfld.long 0x0C 16.--19. " EMEM_DEV1_DEVSIZE ,Density of the first attached DRAM device" ",,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB,8GB,768MB,?..."
|
|
bitfld.long 0x0C 8.--9. " EMEM_DEV1_BANKWIDTH ,Width of bank address of the first attached DRAM device" ",,W2,W3"
|
|
bitfld.long 0x0C 0.--2. " EMEM_DEV1_COLWIDTH ,Width of column address of the first attached DRAM device" ",W8,W9,W10,W11,W12,?..."
|
|
endif
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "SECURITY_CFG0_0,Secure region configuration for base"
|
|
hexmask.long.word 0x00 20.--31. 0x10 " SECURITY_BOM ,Base of the secured region"
|
|
line.long 0x04 "SECURITY_CFG1_0,Secure region configuration for bound"
|
|
hexmask.long.word 0x04 0.--12. 1. " SECURITY_SIZE_MB ,Size in MB of the secured region"
|
|
width 28.
|
|
textline " "
|
|
group.long 0x90++0x37
|
|
line.long 0x00 "EMEM_ARB_CFG_0,External memory arbitration configuration"
|
|
hexmask.long.byte 0x00 16.--20. 1. " EXTRA_TICKS_PER_UPDATE ,Number of extra ticks to add every deadline timer update"
|
|
hexmask.long.word 0x00 0.--8. 1. " CYCLES_PER_UPDATE ,Number of mcclk cycles per deadline timer update"
|
|
line.long 0x04 "EMEM_ARB_OUTSTANDING_REQ_0,External memory arbitration configuration for Outstanding Request Limiter"
|
|
bitfld.long 0x04 31. " LIMIT_OUTSTANDING ,Total number of requests in the arbitration is limited to the value in ARB_MAX_OUTSTANDING" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " LIMIT_DURING_HOLDOFF_OVERRIDE ,Override the limiting of transactions" "Enabled,Disabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 16.--24. 1. " ARB_OUTSTANDING_COUNT ,Current number of outstanding requests"
|
|
hexmask.long.word 0x04 0.--8. 1. " ARB_MAX_OUTSTANDING ,Maximum number of requests"
|
|
textline " "
|
|
line.long 0x08 "EMEM_ARB_TIMING_RCD_0,External memory arbitration configuration for DRAM timing tRCD"
|
|
bitfld.long 0x08 0.--5. " RCD ,Minimum number of cycles between activate commands to the same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "EMEM_ARB_TIMING_RP_0,External memory arbitration configuration for DRAM timing tRP"
|
|
hexmask.long.byte 0x0C 0.--6. 1. " RP ,Minimum number of cycles between an internal precharge and activate command to the same bank"
|
|
line.long 0x10 "EMEM_ARB_TIMING_RC_0,External memory arbitration configuration for DRAM timing tRC"
|
|
hexmask.long.byte 0x10 0.--6. 1. " RP ,Minimum number of cycles between activate commands to the same bank"
|
|
line.long 0x14 "EMEM_ARB_TIMING_RAS_0,External memory arbitration configuration for DRAM timing tRAS"
|
|
bitfld.long 0x14 0.--5. " RAS ,Minimum number of cycles between activate and precharge command to the same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x18 "EMEM_ARB_TIMING_FAW_0,External memory arbitration configuration for DRAM timing tFAW"
|
|
bitfld.long 0x18 0.--5. " FAW ,tFAW setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x1C "EMEM_ARB_TIMING_RRD_0,External memory arbitration configuration for DRAM timing tRRD"
|
|
bitfld.long 0x1C 0.--3. " RRD ,Minimum number of cycles between activate command and activate command to a different bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x20 "EMEM_ARB_TIMING_RAP2PRE_0,External memory arbitration configuration for DRAM timing tRAP2PRE"
|
|
bitfld.long 0x20 0.--5. " RAP2PRE ,Minimum number of cycles between read and internal precharge commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x24 "EMEM_ARB_TIMING_WAP2PRE_0,External memory arbitration configuration for DRAM timing tWAP2PRE"
|
|
hexmask.long.byte 0x24 0.--6. 1. " WAP2PRE ,Minimum number of cycles between write and internal precharge commands"
|
|
line.long 0x28 "EMEM_ARB_TIMING_R2R_0,External memory arbitration configuration for DRAM timing tR2R"
|
|
bitfld.long 0x28 0.--4. " R2R ,Minimum number of cycles between consecutive read commands to different devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "EMEM_ARB_TIMING_W2W_0,External memory arbitration configuration for DRAM timing tW2W"
|
|
bitfld.long 0x2C 0.--4. " W2W ,Minimum number of cycles between consecutive write commands to different devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x30 "EMEM_ARB_TIMING_R2W_0,External memory arbitration configuration for DRAM timing tR2W"
|
|
bitfld.long 0x30 0.--5. " R2W ,Number of cycles to turn the bus from reads to writes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x34 "EMEM_ARB_TIMING_W2R_0,External memory arbitration configuration for DRAM timing tW2R"
|
|
bitfld.long 0x34 0.--5. " W2R ,Number of cycles to turn the bus from reads to writes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xD0++0x17
|
|
line.long 0x00 "EMEM_ARB_DA_TURNS_0,External memory arbitration configuration for direction arbiter [turns]"
|
|
hexmask.long.byte 0x00 24.--31. 1. " W2R_TURN ,Bubbles produced by a write to read bus turn"
|
|
hexmask.long.byte 0x00 16.--23. 1. " R2W_TURN ,Bubbles produced by a read to write bys turn"
|
|
hexmask.long.byte 0x00 8.--15. 1. " W2W_TURN ,Bubbles produced by a write to write (other device) bus torun"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R2R_TURN ,Bubbles produced by a read to read (other device) bus torun"
|
|
line.long 0x04 "EMEM_ARB_DA_COVERS_0,External memory arbitration configuration for direction arbiter [covers]"
|
|
hexmask.long.byte 0x04 16.--23. 1. " RCD_W_COVER ,Cost to cover the activate-to-write delay"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RCD_R_COVER ,Cost to cover the activate-to-read delay"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RC_COVER ,Cost to cover the activate-to-activate delay"
|
|
textline " "
|
|
line.long 0x08 "EMEM_ARB_MISC0_0,External Memory Arbitration Configuration for miscellaneous thresholds"
|
|
bitfld.long 0x08 28.--30. " ATOMS_PER_DVFS_PULSE ,Atoms per dvfs pulse setting" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 27. " MC_EMC_SAME_FREQ ,MC data request frequency is the half/same as EMC" "EMC/2,Same as EMC"
|
|
textline " "
|
|
bitfld.long 0x08 21.--26. " EXPIRING_SOON_SLACK_THRESHOLD ,Slack threshold below which an isochronous request is considered to be expiring soon" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 16.--20. " PRIORITY_INVERSION_ISO_THRESHOLD ,Maximum number of unexpired or expired and not isonchronous requests" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 15. " EMC_REQ_B2B_XFER ,Allow EMC transactions on back to back clocks regardless of EMC consumption bandwidth" "Disabled,Enabled"
|
|
hexmask.long.byte 0x08 8.--14. 1. " PRIORITY_INVERSION_THRESHOLD ,Maximum number of unexpired requests"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " B2AA_HOLDOFF_THRESHOLD ,Activation hold off threshold"
|
|
line.long 0x0C "EMEM_ARB_MISC1_0,External Memory Arbitration Configuration for miscellaneous threshold 1"
|
|
bitfld.long 0x0C 28.--31. " DEADLOCK_PREVENTATION_SLACK_THRESHOLD ,Deadlock prevention slack threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 24.--25. " REFRESH_ACK_THRESHOLD_USAGE ,Threshold's select for refresh-acknowledge signal" "Normal,ISO,None,"
|
|
textline " "
|
|
bitfld.long 0x0C 21.--23. " EXPIRING_SOON_SLACK_THRESHOLD_PD ,Slack threshold below which an isochronous request is considered to be expiring soon" "ZERO_TICKS,ONE_TICK,TWO_TICKS,FOUR_TICKS,EIGHT_TICKS,Use SLACK_THRESHOLD,?..."
|
|
hexmask.long.word 0x0C 4.--12. 1. " ALT_DEADLOCK_PREVENTION_SLACK_THRESHOLD ,Use the absolute value of deadlock prevention slack threshold instead of 2^n format"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " ALLOW_BCA_HOLDOFF_WHN_EXP ,Allows BCA holdoff to occur even when expired requests are present" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " BLOCK_LP_CPU_RD_IF_SMMU_INP_HP ,Low priority CPU reads get blocked" "Disabled,Enabled"
|
|
line.long 0x10 "EMEM_ARB_RING1_THROTTLE_0,External Memory Arbitration Configuration for snap arbiter throttle"
|
|
bitfld.long 0x10 16.--20. " RING1_THROTTLE_CYCLES_HIGH ,Cycles of throttle when transaction count is greater than or equal to threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 0.--4. " RING1-THROTTLE_CYCLES_LOW ,Cycles of throttle when transaction count is below threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "EMEM_ARB_RING3_THROTTLE,External memory arbitration configuration for snap arbiter throttle"
|
|
bitfld.long 0x14 0.--4. " RING3_THROTTLE_CYCLES ,Cycles of throttle after each request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
group.long 0xE8++0x07
|
|
line.long 0x00 "EMEM_ARB_OVERRIDE_0,External Memory Arbitration Configuration for feature overrides"
|
|
bitfld.long 0x00 31. " ARB_HUM_FIFO_DEADLOCK_CHECK_OVERRIDE ,FIFO deadlock check override" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " ARB_EMEM_SPO_OVERRIDE ,EMEM_SPO override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ARB_EMEM_AP_OVERRIDE ,EMEM_AP override" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ARB_HUM_FIFO_OVERRIDE ,Hum FIFO override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ISO_TA_OVERRIDE ,ISO_TA override" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ISO_DA_OVERRIDE ,ISO DA override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ISO_BC_INHERIT_ON_PRIINV_OVERRIDE ,ISO_BC inherit on priiv override" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ISO_BC_CAUSE_PRIINV_OVERRIDE ,ISO BC cause priinv override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ISO_BA_OVERRIDE ,ISO_BA override" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ISO_AA_OVERRIDE ,ISO AA override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ARB_EMEM_BUBBLECALC_OVERRIDE ,Emem bubblecalc override" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ALLOC_ONE_BQ_PER_CLIENT ,Allocate one BQ per client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PRIORITY_INVERSION_ISO_THRESHOLD_BUS_OVERRIDE ,Priority inversion iso threshold BUS override" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PRIORITY_INVERSION_ISO_THRESHOLD_BANK_OVERRIDE ,Priority inversion threshold bank override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PRIORITY_INVERSION_THRESHOLD_BUS_OVERRIDE ,Priority inversion threshold BUS override" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PRIORITY_INVERSION_THRESHOLD_BANK_OVERRIDE ,Priority inversion bank override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PRIORITY_INVERSION_EQ_PRI_LEN_LIMIT_OVERRIDE ,Priority inversion EQ_PRI_LEN limit override" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OBSERVED_DIRECTION_OVERRIDE ,Observed direction override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BC2AA_HOLDHOFF_OVERRIDE ,BC2AA holdhoff override" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TS2AA_HOLDHOFF_OVERRIDE ,TS2AA holdhoff override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EXPIRE_UPDATE_OVERRIDE ,Expire update override" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "EMEM_ARB_RSV_0,EMEM Arbiter Reserved"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EMEM_ARB_RESERVED_BYTE3 ,EMEM_ARB reserved byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " EMEM_ARB_RESERVED_BYTE3 ,EMEM_ARB reserved byte2"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " EMEM_ARB_RESERVED_BYTE3 ,EMEM_ARB reserved byte1 "
|
|
hexmask.long.byte 0x04 0.--7. 1. " EMEM_ARB_RESERVED_BYTE3 ,EMEM_ARB reserved byte0"
|
|
group.long 0x0F4++0x03
|
|
line.long 0x00 "CLKEN_OVERRIDE_0,Second-Level Clock Enable Overrides"
|
|
bitfld.long 0x00 9. " WCAM_CLKEN_OVR ,WCAM_CLKEN_OVR" "GATED,ALWAYS_ON"
|
|
bitfld.long 0x00 8. " PTC_CACHE_CLKEN_OVR ,PTC_CACHE_CLKEN_OVR" "GATED,ALWAYS_ON"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PTC_CLKEN_OVR ,PTC_CLKEN_OVR" "GATED,ALWAYS_ON"
|
|
bitfld.long 0x00 6. " TLB_CLKEN_OVR ,TLB_CLKEN_OVR" "GATED,ALWAYS_ON"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WB_CLKEN_OVR ,WB_CLKEN_OVR" "GATED,ALWAYS_ON"
|
|
bitfld.long 0x00 3. " REGS_CLKEN_OVR ,REGS_CLKEN_OVR" "GATED,ALWAYS_ON"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EARB_CLKEN_OVR ,EARB_CLKEN_OVR" "GATED,ALWAYS_ON"
|
|
bitfld.long 0x00 0. " CIF_CLKEN_OVR ,CIF_CLKEN_OVR" "GATED,ALWAYS_ON"
|
|
group.long 0x0FC++0x07
|
|
line.long 0x00 "TIMING_CONTROL_0 ,Shadowed registers update trigger"
|
|
bitfld.long 0x00 0. " TIMING_UPDATE ,Trigger a timing update event" "No trigger,Trigger"
|
|
textline " "
|
|
line.long 0x04 "STAT_CONTROL_0,Statistic control"
|
|
bitfld.long 0x04 3. " EMC_PM_STOP_TRIGGER ,EMC_PM stop trigger" "No trigger,Trigger"
|
|
bitfld.long 0x04 2. " EMC_PM_START_TRIGGER ,EEMC_PM start trigger" "No trigger,Trigger"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " EMC_GATHER ,EMC gather" "RST,,Disabled,Enabled"
|
|
width 26.
|
|
tree "Hot Reset Control"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "CLIENT_HOTRESET_CTRL_0,Memory client hot reset control register"
|
|
bitfld.long 0x00 31. " SDMMC3A_FLUSH_ENABLE ,SDMMC3A flush enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SDMMC2A_FLUSH_ENABLE ,SDMMC2A flush enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SDMMCA1_FLUSH_ENABLE ,SDMMCA1 flush enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TSEC_FLUSH_ENABLE ,TSEC flush enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " XUSB_DEV_FLUSH_ENABLE ,XUSB dev flush enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " XUSB_HOST_FLUSH_ENABLE ,XUSB host flush enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " VIC_FLUSH_ENABLE ,VIC flush enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " VI_FLUSH_ENABLE ,VI flush enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " VDE_FLUSH_ENABLE ,VDE flush enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SATA_FLUSH_ENABLE ,SATA flush enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PPCS_FLUSH_ENABLE ,PPCS flush enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MSENC_FLUSH_ENABLE ,MSENC flush enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MPCORELP_FLUSH_ENABLE ,MPCORELP flush enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MPCORE_FLUSH_ENABLE ,MPCORE flush enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ISP2_FLUSH_ENABLE ,ISP2 flush enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HDA_FLUSH_ENABLE ,HDA flush enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HC_FLUSH_ENABLE ,HC flush enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DCB_FLUSH_ENABLE ,DCB flush enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DC_FLUSH_ENABLE ,DC flush enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AVPC_FLUSH_ENABLE ,AVPC flush enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AFI_FLUSH_ENABLE ,AFI flush enable" "Disabled,Enabled"
|
|
rgroup.long 0x204++0x03
|
|
line.long 0x00 "CLIENT_HOTRESET_STATUS_0,Memory client hot reset status register"
|
|
bitfld.long 0x00 31. " SDMMC3A_HOTRESET_STATUS ,SDMMC3A flush status" "In progress,Done"
|
|
bitfld.long 0x00 30. " SDMMC2A_HOTRESET_STATUS ,SDMMC2A flush status" "In progress,Done"
|
|
bitfld.long 0x00 29. " SDMMC1A_HOTRESET_STATUS ,SDMMC1A flush status" "In progress,Done"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TSEC_HOTRESET_STATUS ,TSEC flush status" "In progress,Done"
|
|
bitfld.long 0x00 20. " XUSB_DEV_HOTRESET_STATUS ,XUSB DEV flush status" "In progress,Done"
|
|
bitfld.long 0x00 19. " XUSB_HOST_HOTRESET_STATUS ,XUSB Host flush status" "In progress,Done"
|
|
textline " "
|
|
bitfld.long 0x00 18. " VIC_HOTRESET_STATUS , VIC flush status" "In progress,Done"
|
|
bitfld.long 0x00 17. " VI_HOTRESET_STATUS ,VI flush status" "In progress,Done"
|
|
bitfld.long 0x00 16. " VDE_HOTRESET_STATUS ,VDE flush status" "In progress,Done"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SATA_HOTRESET_STATUS ,SATA flush status" "In progress,Done"
|
|
bitfld.long 0x00 14. " PPCS_HOTRESET_STATUS ,PPCS flush status" "In progress,Done"
|
|
bitfld.long 0x00 11. " MSENC_HOTRESET_STATUS ,MSENC flush status" "In progress,Done"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MPCORELP_HOTRESET_STATUS ,MPCORELP flush status" "In progress,Done"
|
|
bitfld.long 0x00 9. " MPCORE_HOTRESET_STATUS ,MPCORE flush status" "In progress,Done"
|
|
bitfld.long 0x00 8. " ISP2_HOTRESET_STATUS ,ISP flush status" "In progress,Done"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HDA_HOTRESET_STATUS ,HDA flush status" "In progress,Done"
|
|
bitfld.long 0x00 6. " HC_HOTRESET_STATUS ,HC flush status" "In progress,Done"
|
|
bitfld.long 0x00 3. " DCB_HOTRESET_STATUS ,DCB flush status" "In progress,Done"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DC_HOTRESET_STATUS ,DC flush status" "In progress,Done"
|
|
bitfld.long 0x00 1. " AVPC_HOTRESET_STATUS ,AVPC flush status" "In progress,Done"
|
|
bitfld.long 0x00 0. " AFI_HOTRESET_STATUS ,AFI flush status" "In progress,Done"
|
|
tree.end
|
|
width 26.
|
|
tree "Per-Client Isochronous Settings"
|
|
group.long 0x208++0x0F
|
|
line.long 0x00 "EMEM_ARB_ISOCHRONOUS_0_0,Per-client isochronous settings"
|
|
bitfld.long 0x00 31. " ISO_SATAR ,Client SATAR is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ISO_PPCSAHBSLVR ,Client PPCSAHBSLVR is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ISO_PPCSAHBDMAR ,Client PPCSAHBDMAR is treated as an isochronous client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ISO_MSENCSRD ,Client MSENCSRD is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ISO_HOST1XR ,Client HOST1XR is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ISO_HOST1XDMAR ,Client HOST1XDMAR is treated as an isochronous client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ISO_HDAR ,Client HDAR is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ISO_DISPLAYHCB ,Client DISPLAYHCB is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ISO_DISPLAYHC ,Client DISPLAYHC is treated as an isochronous client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ISO_AVPCARM7R ,Client AVPCARM7R is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISO_AFIR ,Client AFIR is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ISO_DISPLAY0CB ,Client DISPLAY0CB is treated as an isochronous client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ISO_DISPLAY0C ,Client DISPLAY0C is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ISO_DISPLAY0BB ,Client DISPLAY0BB is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ISO_DISPLAY0B ,Client DISPLAY0B is treated as an isochronous client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ISO_DISPLAY0AB ,Client DISPLAY0AB is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ISO_DISPLAY0A ,Client DISPLAY0A is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ISO_PTCR ,Client PTCR is treated as an isochronous client" "Disabled,Enabled"
|
|
line.long 0x04 "EMEM_ARB_ISOCHRONOUS_1_0,Per-client isochronous settings"
|
|
bitfld.long 0x04 31. " ISO_VDEDBGW ,Client VDEDBGW is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " ISO_VDEBSEVW ,Client VDEBSEVW is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " ISO_SATAW ,Client SATAW is treated as an isochronous client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " ISO_PPCSAHBSLVW ,Client PPCSAHBSLVW is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " ISO_PPCSAHBDMAW ,Client PPCSAHBDMAW is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " ISO_MPCOREW ,Client MPCOREW is treated as an isochronous client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " ISO_HOST1XW ,Client HOST1XW is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " ISO_HDAW ,Client HDAW is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " ISO_FDCDWR2 ,Client FDCDWR2 is treated as an isochronous client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " ISO_AVPCARM7W ,Client AVPCARM7W is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " ISO_AFIW ,Client AFIW is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " ISO_MSENCSWR ,Client MSENCSWR is treated as an isochronous client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ISO_MPCORER ,Client MPCORER is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " ISO_MPCORELPR ,Client MPCORELPR is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " ISO_VDETPER ,Client VDETPER is treated as an isochronous client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ISO_VDEMCER ,Client vdemcer is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " ISO_VDEMBER ,Client VDEMBER is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " ISO_VDEBSEVR ,Client VDEBSEVR is treated as an isochronous client" "Disabled,Enabled"
|
|
line.long 0x08 "EMEM_ARB_ISOCHRONOUS_2_0,Per-client isochronous settings"
|
|
bitfld.long 0x08 26. " ISO_DISPLAYT ,Client DISPLAYT is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " ISO_GPUSWR ,Client GPUSWR is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " ISO_GPUSRD ,Client GPUSRD is treated as an isochronous client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " ISO_TSECSWR ,Client TSECSWR is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " ISO_TSECSRD ,Client TSECSRD is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " ISO_ISPWBB ,Client ISPWBB is treated as an isochronous client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " ISO_ISPWAB ,Client ISPWAB is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " ISO_ISPRAB ,Client ISPRAB is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " ISO_XUSB_DEVW ,Client XUSB devw is treated as an isochronous client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " ISO_XUSB_DEVR ,Client XUSB devr is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " ISO_XUSB_HOSTW ,Client XUSB hostw is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " ISO_XUSB_HOSTR ,Client XUSB hostr is treated as an isochronous client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ISO_ISPWB ,Client ISPWB is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " ISO_ISPWA ,Client ISPWA is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " ISO_ISPRA ,Client ISPRA is treated as an isochronous client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ISO_VDETPMW ,Client VDETPMW is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ISO_VDEMBEW ,Client VDEMBEW is treated as an isochronous client" "Disabled,Enabled"
|
|
line.long 0x0C "EMEM_ARB_ISOCHRONOUS_3_0,Per-client isochronous settings"
|
|
bitfld.long 0x0C 19. " ISO_DISPLAYD ,Client DISPLAYD is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " ISO_VIW ,Client VIW is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " ISO_VICSWR ,Client VICSWR is treated as an isochronous client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " ISO_VICSRD ,Client VICSRD is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " ISO_SDMMCWAB ,Client SDMMCWAB is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " ISO_SDMMCW ,Client SDMMCW is treated as an isochronous client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ISO_SDMMCWAA ,Client SDMMCWAA is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " ISO_SDMMCWA ,Client SDMMCWA is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " ISO_SDMMCRAB ,Client SDMMCRAB is treated as an isochronous client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " ISO_SDMMCR ,Client SDMMCR is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " ISO_SDMMCRAA ,Client SDMMCRAA is treated as an isochronous client" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " ISO_SDMMCCRA ,Client SDMMCRA is treated as an isochronous client" "Disabled,Enabled"
|
|
tree.end
|
|
width 25.
|
|
tree "Per-Client Hysteresis Settings"
|
|
group.long 0x218++0x0F
|
|
line.long 0x00 "EMEM_ARB_HYSTERESIS_0_0,Per-client hysteresis settings"
|
|
bitfld.long 0x00 31. " HYST_SATAR ,Client SATAR is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " HYST_PPCSAHBSLVR ,Client PPCSAHBSLVR is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HYST_PPCSAHBDMAR ,Client PPCSAHBDMAR is treated as an hysteresis client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " HYST_MSENCSRD ,Client MSENCSRD is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " HYST_HOST1XR ,Client HOST1XR is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " HYST_HOST1XDMAR ,Client HOST1XDMAR is treated as an hysteresis client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " HYST_HDAR ,Client HDAR is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " HYST_DISPLAYHCB ,Client DISPLAYHCB is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " HYST_DISPLAYHC ,Client DISPLAYHC is treated as an hysteresis client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " HYST_AVPCARM7R ,Client AVPCARM7R is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " HYST_AFIR ,Client AFIR is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HYST_DISPLAY0CB ,Client DISPLAY0CB is treated as an hysteresis client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HYST_DISPLAY0C ,Client DISPLAY0C is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " HYST_DISPLAY0BB ,Client DISPLAY0BB is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HYST_DISPLAY0B ,Client DISPLAY0B is treated as an hysteresis client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HYST_DISPLAY0AB ,Client DISPLAY0AB is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HYST_DISPLAY0A ,Client DISPLAY0A is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " HYST_PTCR ,Client PTCR is treated as an hysteresis client" "Disabled,Enabled"
|
|
line.long 0x04 "EMEM_ARB_HYSTERESIS_1_0,Per-client hysteresis settings"
|
|
bitfld.long 0x04 31. " HYST_VDEDBGW ,Client VDEDBGW is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " HYST_VDEBSEVW ,Client VDEBSEVW is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " HYST_SATAW ,Client SATAW is treated as an hysteresis client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " HYST_PPCSAHBSLVW ,Client PPCSAHBSLVW is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " HYST_PPCSAHBDMAW ,Client PPCSAHBDMAW is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " HYST_MPECSWR ,Client MPECSWR is treated as an hysteresis client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " HYST_MPCOREW ,Client MPCOREW is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " HYST_MPCORELPW ,Client MPCORELPW is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " HYST_HOST1XW ,Client HOST1XW is treated as an hysteresis client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " HYST_HDAW ,Client HDAW is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " HYST_AVPCARM7W ,Client AVPCARM7W is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " HYST_AFIW ,Client AFIW is treated as an hysteresis client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " HYST_MSENCSWR ,Client MSENCSWR is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " HYST_MPCORER ,Client MPCORER is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " HYST_MPCORELPR ,Client MPCORELPR is treated as an hysteresis client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " HYST_VDETPER ,Client VDETPER is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " HYST_VDEMCER ,Client VDEMCER is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " HYST_VDEMBER ,Client VDEMBER is treated as an hysteresis client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " HYST_VDEBSEVR ,Client VDEBSEVR is treated as an hysteresis client" "Disabled,Enabled"
|
|
line.long 0x08 "EMEM_ARB_HYSTERESIS_2_0,Per-client hysteresis settings"
|
|
bitfld.long 0x08 26. " HYST_DISPLAYT ,Client DISPLAYT is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " HYST_GPUSWR ,Client GPUSWR is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " HYST_GPUSRD ,Client GPSURD is treated as an hysteresis client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " HYST_TSECSWR ,Client TSECSWR is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " HYST_TSECSRD ,Client TSECSRD is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " HYST_ISPWBB ,Client ISPWBB is treated as an hysteresis client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " HYST_ISPWAB ,Client ISPWAB is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " HYST_ISPRAB ,Client ISPRAB is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " HYST_XUSB_DEVW ,Client XUSB devw is treated as an hysteresis client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " HYST_XUSB_DEVR ,Client XUSB devr is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " HYST_XUSB_HOSTW ,Client XUSB hostw is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " HYST_XUSB_HOSTR ,Client XUSB hostr is treated as an hysteresis client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HYST_ISPWB ,Client ISPWB is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " HYST_ISPWA ,Client ISPWA is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " HYST_ISPRA ,Client ISPRA is treated as an hysteresis client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " HYST_VDETPMW ,Client VDETPMW is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " HYST_VDEMBEW ,Client VDEMBEW is treated as an hysteresis client" "Disabled,Enabled"
|
|
line.long 0x0C "EMEM_ARB_HYSTERESIS_3_0,Per-client hysteresis settings"
|
|
bitfld.long 0x0C 19. " HYST_DISPLAYD ,Client DISPLAYD is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " HYST_VIW ,Client VIW is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " HYST_VICSWR ,Client VICSWR is treated as an hysteresis client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " HYST_VICSRD ,Client VICSRD is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " HYST_SDMMCWAB ,Client SDMMCWAB is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " HYST_SDMMCW ,Client SDMMCW is treated as an hysteresis client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " HYST_SDMMCWAA ,Client SDMMCWAA is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " HYST_SDMMCWA ,Client SDMMCWA is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " HYST_SDMMCRAB ,Client SDMMCRAB is treated as an hysteresis client" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " HYST_SDMMCR ,Client SDMMCR is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " HYST_SDMMCRAA ,Client SDMMCRAA is treated as an hysteresis client" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " HYST_SDMCRA ,Client SDMCRA is treated as an hysteresis client" "Disabled,Enabled"
|
|
tree.end
|
|
width 29.
|
|
tree "Per-client SMMU translation enables"
|
|
group.long 0x228++0x0F
|
|
line.long 0x00 "SMMU_TRANSLATION_ENABLE_0_0,Per-client SMMU translation enables"
|
|
bitfld.long 0x00 31. " SMMU_SATAR_ENABLE ,Enable client SATAR to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SMMU_PPCSAHBSLVR_ENABLE ,Enable client PPCSAHBSLVR to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SMMU_PPCSAHBDMAR_ENABLE ,Enable client PPCSAHBDMAR to be translated by SMMU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SMMU_MSENCSRD_ENABLE ,Enable client MSENCSRD to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SMMU_HOST1XR_ENABLE ,Enable client HOST1XR to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " SMMU_HOST1XDMAR_ENABLE ,Enable client HOST1XDMAR to be translated by SMMU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMMU_HDAR_ENABLE ,Enable client HDAR to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SMMU_DISPLAYHCB_ENABLE ,Enable client DISPLAYHCB to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SMMU_DISPLAYHC_ENABLE ,Enable client DISPLAYHC to be translated by SMMU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SMMU_AVPCARM7R_ENABLE ,Enable client AVPCARM7R to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SMMU_AFIR_ENABLE ,Enable client AFIR to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SMMU_DISPLAY0CB_ENABLE ,Enable client DISPLAY0CB to be translated by SMMU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SMMU_DISPLAY0C_ENABLE ,Enable client DISPLAY0C to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SMMU_DISPLAY0BB_ENABLE ,Enable client DISPLAY0BB to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SMMU_DISPLAY0B_ENABLE ,Enable client DISPLAY0B to be translated by SMMU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SMMU_DISPLAY0AB_ENABLE ,Enable client DISPLAY0AB to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SMMU_DISPLAY0A_ENABLE ,Enable client DISPLAY0A to be translated by SMMU" "Disabled,Enabled"
|
|
line.long 0x04 "SMMU_TRANSLATION_ENABLE_1_0,Per-client SMMU translation enables"
|
|
bitfld.long 0x04 31. " SMMU_VDEDBGW_ENABLE ,Enable client VDEDBGW to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " SMMU_VDEBSEVW_ENABLE ,Enable client VDEBSEVW to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " SMMU_SATAW_ENABLE ,Enable client SATAW to be translated by SMMU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " SMMU_PPCSAHBSLVW_ENABLE ,Enable client PPCSAHBSLVW to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " SMMU_PPCSAHBDMAW_ENABLE ,Enable client PPCSAHBDMAW to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " SMMU_HOST1XW_ENABLE ,Enable client HOST1XW to be translated by SMMU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SMMU_HDAW_ENABLE ,Enable client HDAW to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " SMMU_AVPCARM7W_ENABLE ,Enable client AVPCARM7W to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " SMMU_AFIW_ENABLE ,Enable client AFIW to be translated by SMMU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " SMMU_MSENCSWR_ENABLE ,Enable client MSENCSWR to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " SMMU_VDETPER_ENABLE ,Enable client VDETPER to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " SMMU_VDEMCER_ENABLE ,Enable client VDEMCER to be translated by SMMU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SMMU_VDEMBER_ENABLE ,Enable client VDEMBER to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SMMU_VDEBSEVR_ENABLE ,Enable client VDEBSEVR to be translated by SMMU" "Disabled,Enabled"
|
|
line.long 0x08 "SMMU_TRANSLATION_ENABLE_2_0,Per-client SMMU translation enables"
|
|
bitfld.long 0x08 26. " SMMU_DISPLAYT_ENABLE ,Enable client DISPLAYT to be translated by SMMU" "Disabled,Enabled"
|
|
rbitfld.long 0x08 25. " SMMU_GPUSWR_ENABLE , GPU translation is handled by SWID" "Disabled,Enabled"
|
|
rbitfld.long 0x08 24. " SMMU_GPUSRD_ENABLE ,GPU translation is handled by SWID" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SMMU_TSECSWR_ENABLE ,Enable client TSECSWR to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " MMU_TSECSRD_ENABLE ,Enable client TSECSRD to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " SMMU_ISPWBB_ENABLE ,Enable client ISPWBB to be translated by SMMU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " SMMU_ISPWAB_ENABLE ,Enable client ISPWAB to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " SMMU_ISPRAB_ENABLE ,Enable client ISPRAB to be ranslated by SMMU" "DIsabled,Enabled"
|
|
bitfld.long 0x08 13. " SMMU_XUSB_DEVW_ENABLE ,Enable client XUSB devw to be translated by SMMU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " SMMU_XUSB_DEVR_ENABLE ,Enable client XUSB devr to be translated by SMMU" "DIsabled,Enabled"
|
|
bitfld.long 0x08 11. " SMMU_XUSB_HOSTW_ENABLE ,Enable client XUSB hostw to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " SMMU_XUSB_HOSTR_ENABLE ,Enable client XUSB hostr to be translated by SMMU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SMMU_ISPWB_ENABLE ,Enable client ISPWB to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " SMMU_ISPWA_ENABLE ,Enable client ISPWA to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " SMMU_ISPRA_ENABLE ,Enable client ISPRA to be translated by SMMU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SMMU_VDETPMW_ENABLE ,Enable client VDETPMW to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " SMMU_VDEMBEW_ENABLE ,Enable client VDEMBEW to be translated by SMMU" "Disabled,Enabled"
|
|
line.long 0x0C "SMMU_TRANSLATION_ENABLE_3_0,Per-client SMMU translation enables"
|
|
bitfld.long 0x0C 19. " SMMU_DISPLAYD_ENABLE ,Enable client DISPLAYD to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " SMMU_VIW_ENABLE , Client VIW translation to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " SMMU_VICSWR_ENABLE ,Enable client VICSWR to be translated by SMMU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " SMMU_VICSRD_ENABLE ,Enable client VICSRD to be translated by SMMU" "DIsabled,Enabled"
|
|
bitfld.long 0x0C 7. " SMMU_SDMMCWAB_ENABLE ,Enable client SDMMCWAB to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " SMMU_SDMMCW_ENABLE ,Enable client SDMMCW to be translated by SMMU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " SMMU_SDMMWAA_ENABLE ,Enable client SDMMCWAA to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " SMMU_SDMMCWA_ENABLE ,Enable client SDMMCWA to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " SMMU_SDMMCRAB_ENABLE ,Enable client SDMMCRAB to be translated by SMMU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SMMU_SDMMCR_ENABLE ,Enable client SDMMCR to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " SMMU_SDMMCRAA_ENABLE ,Enable client SDMMCRAA to be translated by SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " SMMU_SDMMCRA_ENABLE ,Enable client SDMMCRA to be translated by SMMU" "Disabled,Enabled"
|
|
tree.end
|
|
width 23.
|
|
tree "SMMU AFI Assigment Registers"
|
|
if (((d.l(ad:0x70019000+0x238))&0x80000000)==0x80000000)
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "SMMU_AFI_ASID_0,SMMU AFI ASID assignment register"
|
|
bitfld.long 0x00 31. " AFI_SMMU_ENABLE ,AFI Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " AFI_ASID ,ASID to use for AFI translation"
|
|
else
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "SMMU_AFI_ASID_0,SMMU AFI ASID assignment register"
|
|
bitfld.long 0x00 31. " AFI_SMMU_ENABLE ,AFI Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0x23C))&0x80000000)==0x80000000)
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "SMMU_AVPC_ASID_0,SMMU AVPC ASID assignment register"
|
|
bitfld.long 0x00 31. " AVPC_SMMU_ENABLE ,AVPC Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " AVPC_ASID ,ASID to use for AVPC translation"
|
|
else
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "SMMU_AVPC_ASID_0,SMMU AVPC ASID assignment register"
|
|
bitfld.long 0x00 31. " AVPC_SMMU_ENABLE ,AVPC Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0x240))&0x80000000)==0x80000000)
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "SMMU_DC_ASID_0,SMMU DC ASID assignment register"
|
|
bitfld.long 0x00 31. " DC_SMMU_ENABLE ,DC Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " DC_ASID ,ASID to use for DC translation"
|
|
else
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "SMMU_DC_ASID_0,SMMU DC ASID assignment register"
|
|
bitfld.long 0x00 31. " DC_SMMU_ENABLE ,DC Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0x244))&0x80000000)==0x80000000)
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "SMMU_DCB_ASID_0,SMMU DCB ASID assignment register"
|
|
bitfld.long 0x00 31. " DCB_SMMU_ENABLE ,DCB Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " DCB_ASID ,ASID to use for DCB translation"
|
|
else
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "SMMU_DCB_ASID_0,SMMU DCB ASID assignment register"
|
|
bitfld.long 0x00 31. " DCB_SMMU_ENABLE ,DCB Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0x250))&0x80000000)==0x80000000)
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "SMMU_HC_ASID_0,SMMU HC ASID assignment register"
|
|
bitfld.long 0x00 31. " HC_SMMU_ENABLE ,HC Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " HC_ASID ,ASID to use for HC translation"
|
|
else
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "SMMU_HC_ASID_0,SMMU HC ASID assignment register"
|
|
bitfld.long 0x00 31. " HC_SMMU_ENABLE ,HC Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0x254))&0x80000000)==0x80000000)
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "SMMU_HDA_ASID_0,SMMU HDA ASID assignment register"
|
|
bitfld.long 0x00 31. " HDA_SMMU_ENABLE ,HDA Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " HDA_ASID ,ASID to use for HDA translation"
|
|
else
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "SMMU_HDA_ASID_0,SMMU HDA ASID assignment register"
|
|
bitfld.long 0x00 31. " HDA_SMMU_ENABLE ,HDA Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0x258))&0x80000000)==0x80000000)
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "SMMU_ISP2_ASID_0,SMMU ISP2 ASID assignment register"
|
|
bitfld.long 0x00 31. " ISP2_SMMU_ENABLE ,ISP2 Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ISP2_ASID ,ASID to use for ISP2 translation"
|
|
else
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "SMMU_ISP2_ASID_0,SMMU ISP2 ASID assignment register"
|
|
bitfld.long 0x00 31. " ISP2_SMMU_ENABLE ,ISP2 Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0x264))&0x80000000)==0x80000000)
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "SMMU_MSENC_ASID_0,SMMU MSENC ASID assignment register"
|
|
bitfld.long 0x00 31. " MSENC_SMMU_ENABLE ,MSENC Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " MSENC_ASID ,ASID to use for MSENC translation"
|
|
else
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "SMMU_MSENC_ASID_0,SMMU MSENC ASID assignment register"
|
|
bitfld.long 0x00 31. " MSENC_SMMU_ENABLE ,MSENC Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0x268))&0x80000000)==0x80000000)
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "SMMU_NV_ASID_0,SMMU NV ASID assignment register"
|
|
bitfld.long 0x00 31. " NV_SMMU_ENABLE ,NV Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " NV_ASID ,ASID to use for NV translation"
|
|
else
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "SMMU_NV_ASID_0,SMMU NV ASID assignment register"
|
|
bitfld.long 0x00 31. " NV_SMMU_ENABLE ,NV Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0x26C))&0x80000000)==0x80000000)
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "SMMU_NV2_ASID_0,SMMU NV2 ASID assignment register"
|
|
bitfld.long 0x00 31. " NV2_SMMU_ENABLE ,NV2 Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " NV2_ASID ,ASID to use for NV2 translation"
|
|
else
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "SMMU_NV2_ASID_0,SMMU NV2 ASID assignment register"
|
|
bitfld.long 0x00 31. " NV2_SMMU_ENABLE ,NV2 Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0x270))&0x80000000)==0x80000000)
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "SMMU_PPCS_ASID_0,SMMU PPCS ASID assignment register"
|
|
bitfld.long 0x00 31. " PPCS_SMMU_ENABLE ,PPCS Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PPCS_ASID ,ASID to use for PPCS translation"
|
|
else
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "SMMU_PPCS_ASID_0,SMMU PPCS ASID assignment register"
|
|
bitfld.long 0x00 31. " PPCS_SMMU_ENABLE ,PPCS Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0x274))&0x80000000)==0x80000000)
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "SMMU_SATA_ASID_0,SMMU SATA ASID assignment register"
|
|
bitfld.long 0x00 31. " SATA_SMMU_ENABLE ,SATA Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SATA_ASID ,ASID to use for SATA translation"
|
|
else
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "SMMU_SATA_ASID_0,SMMU SATA ASID assignment register"
|
|
bitfld.long 0x00 31. " SATA_SMMU_ENABLE ,SATA Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0x27C))&0x80000000)==0x80000000)
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "SMMU_VDE_ASID_0,SMMU VDE ASID assignment register"
|
|
bitfld.long 0x00 31. " VDE_SMMU_ENABLE ,VDE Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VDE_ASID ,ASID to use for VDE translation"
|
|
else
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "SMMU_VDE_ASID_0,SMMU VDE ASID assignment register"
|
|
bitfld.long 0x00 31. " VDE_SMMU_ENABLE ,VDE Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0x280))&0x80000000)==0x80000000)
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "SMMU_VI_ASID_0,SMMU VI ASID assignment register"
|
|
bitfld.long 0x00 31. " VI_SMMU_ENABLE ,VI Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VI_ASID ,ASID to use for VI translation"
|
|
else
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "SMMU_VI_ASID_0,SMMU VI ASID assignment register"
|
|
bitfld.long 0x00 31. " VI_SMMU_ENABLE ,VI Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0x284))&0x80000000)==0x80000000)
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "SMMU_VIC_ASID_0,SMMU VIC ASID assignment register"
|
|
bitfld.long 0x00 31. " VIC_SMMU_ENABLE ,VIC Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VIC_ASID ,ASID to use for VIC translation"
|
|
else
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "SMMU_VIC_ASID_0,SMMU VIC ASID assignment register"
|
|
bitfld.long 0x00 31. " VIC_SMMU_ENABLE ,VIC Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0x288))&0x80000000)==0x80000000)
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "SMMU_XUSB_HOST_ASID_0,SMMU XUSB_HOST ASID assignment register"
|
|
bitfld.long 0x00 31. " XUSB_HOST_SMMU_ENABLE ,XUSB_HOST Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XUSB_HOST_ASID ,ASID to use for XUSB_HOST translation"
|
|
else
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "SMMU_XUSB_HOST_ASID_0,SMMU XUSB_HOST ASID assignment register"
|
|
bitfld.long 0x00 31. " XUSB_HOST_SMMU_ENABLE ,XUSB_HOST Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0x28C))&0x80000000)==0x80000000)
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "SMMU_XUSB_DEV_ASID_0,SMMU XUSB_DEV ASID assignment register"
|
|
bitfld.long 0x00 31. " XUSB_DEV_SMMU_ENABLE ,XUSB_DEV Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " XUSB_DEV_ASID ,ASID to use for XUSB_DEV translation"
|
|
else
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "SMMU_XUSB_DEV_ASID_0,SMMU XUSB_DEV ASID assignment register"
|
|
bitfld.long 0x00 31. " XUSB_DEV_SMMU_ENABLE ,XUSB_DEV Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0x294))&0x80000000)==0x80000000)
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "SMMU_TSEC_ASID_0,SMMU TSEC ASID assignment register"
|
|
bitfld.long 0x00 31. " TSEC_DEV_SMMU_ENABLE ,TSEC Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TSEC_DEV_ASID ,ASID to use for TSEC translation"
|
|
else
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "SMMU_TSEC_ASID_0,SMMU TSEC ASID assignment register"
|
|
bitfld.long 0x00 31. " TSEC_SMMU_ENABLE ,TSEC Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0x298))&0x80000000)==0x80000000)
|
|
group.long 0x298++0x03
|
|
line.long 0x00 "SMMU_PPCS1_ASID_0,SMMU PPCS1 ASID assignment register"
|
|
bitfld.long 0x00 31. " SMMU_ENABLE ,PPCS1 Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ASID ,ASID to use for PPCS1 translation"
|
|
else
|
|
group.long 0x298++0x03
|
|
line.long 0x00 "SMMU_PPCS1_ASID_0,SMMU PPCS1 ASID assignment register"
|
|
bitfld.long 0x00 31. " PPCS1_SMMU_ENABLE ,PPCS1 Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0xA88))&0x80000000)==0x80000000)
|
|
group.long 0xA88++0x03
|
|
line.long 0x00 "SMMU_DC1_ASID_0,SMMU DC1 ASID assignment register"
|
|
bitfld.long 0x00 31. " DC1_SMMU_ENABLE ,PPCS Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " DC1_ASID ,ASID to use for AFI translation"
|
|
else
|
|
group.long 0xA88++0x03
|
|
line.long 0x00 "SMMU_DC1_ASID_0,SMMU DC1 ASID assignment register"
|
|
bitfld.long 0x00 31. " DC1_SMMU_ENABLE ,PPCS Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0xA94))&0x80000000)==0x80000000)
|
|
group.long 0xA94++0x03
|
|
line.long 0x00 "SMMU_SDMMC1A_ASID_0,SMMU SDMMC1A ASID assignment register"
|
|
bitfld.long 0x00 31. " SDMMC1A_SMMU_ENABLE ,SDMMC1A Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SDMMC1A_ASID ,ASID to use for SDMMC1A translation"
|
|
else
|
|
group.long 0xA94++0x03
|
|
line.long 0x00 "SMMU_SDMMC1A_ASID_0,SMMU SDMMC1A ASID assignment register"
|
|
bitfld.long 0x00 31. " SDMMC1A_SMMU_ENABLE ,SDMMC1A Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0xA98))&0x80000000)==0x80000000)
|
|
group.long 0xA98++0x03
|
|
line.long 0x00 "SMMU_SDMMC2A_ASID_0,SMMU SDMMC2A ASID assignment register"
|
|
bitfld.long 0x00 31. " SDMMC2A_SMMU_ENABLE ,SDMMC2A Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SDMMC2A_ASID ,ASID to use for SDMMC2A translation"
|
|
else
|
|
group.long 0xA98++0x03
|
|
line.long 0x00 "SMMU_SDMMC2A_ASID_0,SMMU SDMMC2A ASID assignment register"
|
|
bitfld.long 0x00 31. " SDMMC2A_SMMU_ENABLE ,SDMMC2A Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0xA9C))&0x80000000)==0x80000000)
|
|
group.long 0xA9C++0x03
|
|
line.long 0x00 "SMMU_SDMMC3A_ASID_0,SMMU SDMMC3A ASID assignment register"
|
|
bitfld.long 0x00 31. " SDMMC3A_SMMU_ENABLE ,SDMMC3A Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SDMMC3A_ASID ,ASID to use for SDMMC3A translation"
|
|
else
|
|
group.long 0xA9C++0x03
|
|
line.long 0x00 "SMMU_SDMMC3A_ASID_0,SMMU SDMMC3A ASID assignment register"
|
|
bitfld.long 0x00 31. " SDMMC3A_SMMU_ENABLE ,SDMMC3A Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0xAA0))&0x80000000)==0x80000000)
|
|
group.long 0xAA0++0x03
|
|
line.long 0x00 "SMMU_SDMMC4A_ASID_0,SMMU SDMMC4A ASID assignment register"
|
|
bitfld.long 0x00 31. " SDMMC4A_SMMU_ENABLE ,SDMMC4A Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SDMMC4A_ASID ,ASID to use for SDMMC4A translation"
|
|
else
|
|
group.long 0xAA0++0x03
|
|
line.long 0x00 "SMMU_SDMMC4A_ASID_0,SMMU SDMMC4A ASID assignment register"
|
|
bitfld.long 0x00 31. " SDMMC4A_SMMU_ENABLE ,SDMMC4A Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0xAA4))&0x80000000)==0x80000000)
|
|
group.long 0xAA4++0x03
|
|
line.long 0x00 "SMMU_ISP2B_ASID_0,SMMU ISP2B ASID assignment register"
|
|
bitfld.long 0x00 31. " ISP2B_SMMU_ENABLE ,ISP2B Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ISP2B_ASID ,ASID to use for ISP2B translation"
|
|
else
|
|
group.long 0xAA4++0x03
|
|
line.long 0x00 "SMMU_ISP2B_ASID_0,SMMU ISP2B ASID assignment register"
|
|
bitfld.long 0x00 31. " ISP2B_SMMU_ENABLE ,ISP2B Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0xAA8))&0x80000000)==0x80000000)
|
|
group.long 0xAA8++0x03
|
|
line.long 0x00 "SMMU_GPU_ASID_0,SMMU GPU ASID assignment register"
|
|
bitfld.long 0x00 31. " GPU_SMMU_ENABLE ,GPU Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " GPU_ASID ,ASID to use for GPU translation"
|
|
else
|
|
group.long 0xAA8++0x03
|
|
line.long 0x00 "SMMU_GPU_ASID_0,SMMU GPU ASID assignment register"
|
|
bitfld.long 0x00 31. " GPU_SMMU_ENABLE ,GPU Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0xAAC))&0x80000000)==0x80000000)
|
|
group.long 0xAAC++0x03
|
|
line.long 0x00 "SMMU_GPUB_ASID_0,SMMU GPUB ASID assignment register"
|
|
bitfld.long 0x00 31. " GPUB_SMMU_ENABLE ,GPUB Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " GPUB_ASID ,ASID to use for GPUB translation"
|
|
else
|
|
group.long 0xAAC++0x03
|
|
line.long 0x00 "SMMU_GPUB_ASID_0,SMMU GPUB ASID assignment register"
|
|
bitfld.long 0x00 31. " GPUB_SMMU_ENABLE ,GPUB Translation enable" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(ad:0x70019000+0xAB0))&0x80000000)==0x80000000)
|
|
group.long 0xAB0++0x03
|
|
line.long 0x00 "SMMU_PPCS2_ASID_0,SMMU PPCS2 ASID assignment register"
|
|
bitfld.long 0x00 31. " PPCS2_SMMU_ENABLE ,PPCS2 Translation enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PPCS2_ASID ,ASID to use for PPCS2 translation"
|
|
else
|
|
group.long 0xAB0++0x03
|
|
line.long 0x00 "SMMU_PPCS2_ASID_0,SMMU PPCS2 ASID assignment register"
|
|
bitfld.long 0x00 31. " PPCS2_SMMU_ENABLE ,PPCS2 Translation enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
width 34.
|
|
textline " "
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "VIDEO_PROTECT_VPR_OVERRIDE_0,MC VPR override register"
|
|
bitfld.long 0x00 31. " SDMMC3A_VPR_OVERRIDE ,SDMMC3A VPR override" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SDMMC2A_VPR_OVERRIDE ,SDMMC2A VPR override" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SDMMC1A_VPR_OVERRIDE ,SDMMC1A VPR override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " DC1_VPR_OVERRIDE ,DC1 VPR override" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PPCS1_VPR_OVERRIDE ,PPCS1 VPR override" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TSEC_VPR_OVERRIDE ,TSEC VPR override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " XUSB_DEV_VPR_OVERRIDE ,XUSB SEV VPR override" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " XUSB_HOST_VPR_OVERRIDE ,XUSB HOST VPR override" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " VIC_VPR_OVERRIDE ,VIC VPR override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " VI_VPR_OVERRIDE ,VI VPR override" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " VDE_VPR_OVERRIDE ,VDE VPR override" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SATA_VPR_OVERRIDE ,SATA VPR override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PPCS_VPR_OVERRIDE ,PPCS VPR override" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MSENC_VPR_OVERRIDE ,MSENC VPR override" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MPCORELP_VPR_OVERRIDE ,MPCORELP VPR override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MPCORE_VPR_OVERRIDE ,MPCORE VPR override" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ISP2_VPR_OVERRIDE ,ISP2 VPR override" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " HDA_VPR_OVERRIDE ,HDA VPR override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " HC_VPR_OVERRIDE ,HC VPR override" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DCB_VPR_OVERRIDE ,DCB VPR override" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DC_VPR_OVERRIDE , DC VPR override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AVPC_VPR_OVERRIDE ,AVPC VPR override" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AFI_VPR_OVERRIDE ,AFI VPR override" "Disabled,Enabled"
|
|
group.long 0x590++0x03
|
|
line.long 0x00 "VIDEO_PROTECT_VPR_OVERRIDE1_0,MC VPR OVERRIDE Register"
|
|
bitfld.long 0x00 4. " PPCS2_VPR_OVERRIDE ,PPCS2 VPR override" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " GPUB_VPR_OVERRIDE ,GBUP VPR override" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " GPU_VPR_OVERRIDE ,GPU VPR override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ISP2B_VPR_OVERRIDE ,ISP2B VPR override" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SDMMC4A_VPR_OVERRIDE ,SDMMC4A VPR override" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SMMUTLB_SET_SELECTION_MASK_0_0,TLB Set Selection Mask"
|
|
hexmask.long.word 0x00 15.--23. 1. " TLB_SET_SELECTION_MASK_0 ,TLB set selection mask 0"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "DISPLAY_SNAP_RING_0,Display Arbiter Ring Selection"
|
|
bitfld.long 0x00 31. " DISPLAY_SNAP_RING_WRITE_ACCESS ,Display snap ring write access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DISB_SNAP_RING ,Disb snap ring" "RING0,RING1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DIS_SNAP_RING ,Dis snap ring" "RING0,RING1"
|
|
rgroup.long 0x654++0x03
|
|
line.long 0x00 "ERR_VPR_STATUS_0,MC ERR_VPR_STATUS_0"
|
|
bitfld.long 0x00 20.--21. " ERR_VPR_ADR_HI ,Higher address bits of Erring Address whose lower bits are available in the ERR_VPR_ADR register" "b00,b01,b10,b11"
|
|
bitfld.long 0x00 18. " ERR_VPR_SWAP ,ERR_VPR_SWAP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ERR_VPR_SECURITY ,ERR vpr security" "Non secure,Secure"
|
|
bitfld.long 0x00 16. " ERR_VPR_RW ,Direction of the access that caused the error" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " ERR_VPR_ADR1 ,Second subpartition unique address bits" "b000,b001,b010,b011,b100,b101,b110,b111"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_VPR_ID ,Client indentifier"
|
|
rgroup.long 0x658++0x03
|
|
line.long 0x00 "ERR_VPR_ADR_0,MC Lower bits of Erring Address"
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "EMEM_CFG_ACCESS_CTRL_0 ,Access Control Bit for EMEM_CFG Registers"
|
|
bitfld.long 0x00 0. " EMEM_CFG_WRITE_ACCESS ,EMEM cfg write access disable (This bit is sticky: reset to enable)" "No,Yes"
|
|
group.long 0x668++0x07
|
|
line.long 0x00 "TZ_SECURITY_CTRL_0,Trustzone Security Control Register"
|
|
bitfld.long 0x00 0. " CPU_STRICT_TZ_APERTURE_CHECK ,CPU strict TrustZone aperture check enable (This bit is sticky: Reset to disable)" "Disabled,Enabled"
|
|
line.long 0x04 "EMEM_ARB_OUTSTANDING_REQ_RING3_0,External Memory Arbitration Configuration"
|
|
bitfld.long 0x04 31. " LIMIT_OUTSTANDING_RING3 ,Limit outstanding RING3" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " LIMIT_DURING_HOLDHOFF_OVERRIDE_RING3 ,Limit holdhoff override RING3" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 16.--24. 1. " ARB_OUTSTANDING_COUNT_RING3 ,Current number of outstanding requests"
|
|
hexmask.long.word 0x04 0.--8. 1. " ARB_MAX_OUTSTANDING_RING3 ,Maximum number of requests allowed in the arbiter when limit is enabled"
|
|
group.long 0x670++0x0B
|
|
line.long 0x00 "SEC_CARVEOUT_BOM_0,MC sec carveout bom 0"
|
|
hexmask.long.word 0x00 20.--31. 1. " SEC_CARVEOUT_BOM ,Base address for the SEC carveout address space"
|
|
line.long 0x04 "SEC_CARVEOUT_SIZE_MB_0,MC sec carveout size MB 0"
|
|
hexmask.long.word 0x04 0.--11. 1. " SEC_CARVEOUT_SIZEE_MB ,Size of the SEC carveout region"
|
|
line.long 0x08 "SEC_CARVEOUT_REG_CTRL_0,MC sec carveout reg ctrl 0"
|
|
bitfld.long 0x08 0. " SEC_CARVEOUT_WRITE_ACCESS ,Sticky bit to control the writes to the other SEC Carveout registers" "Enabled,Disabled"
|
|
rgroup.long 0x67C++0x07
|
|
line.long 0x00 "ERR_SEC_STATUS_0,MC error sec status 0"
|
|
bitfld.long 0x00 20.--21. " ERR_SEC_ADR_HI ,Higher address bits of Erring address whose lower bits are available in the ERR_ADR register" "b00,b01,b10,b11"
|
|
bitfld.long 0x00 18. " ERR_SEC_SWAP ,ERR_SEC_SWAP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ERR_SEC_SECURITY ,Set if transaction was secure" "Non secure,Secure"
|
|
bitfld.long 0x00 16. " ERR_SEC_RW ,Direction of the access that caused the error" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " ERR_SEC_ADR1 ,Second subpartition unique address bits" "b000,b001,b010,b011,b100,b101,b110,b111"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERR_SEC_ID ,Client identifier of the access that caused the error"
|
|
line.long 0x04 "ERR_SEC_ADR_0,MC Lower address bits of Erring address"
|
|
group.long 0x684++0x07
|
|
line.long 0x00 "PC_IDLE_CLOCK_GATE_CONFIG_0,Partition Idle Clock Gate Config"
|
|
bitfld.long 0x00 0.--4. " CLOCK_GATE_IDLE_TICKS ,Number of idle ticks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "STUTTER_CONTROL_0,MC stutter control 0"
|
|
bitfld.long 0x04 0. " SLOW_EMCCLK_DURING_DSR ,The clock to the EMC will be slowed during dynamic self refresh" "Disabled,Enabled"
|
|
group.long 0x6B0++0x0F
|
|
line.long 0x00 "EMEM_ARB_NISO_THROTTLE_0,Snap Arbiter Throttle"
|
|
bitfld.long 0x00 16.--20. " NISO_THROTTLE_CYCLES_HIGH ,Cycles of throttle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " MC_EMEM_ARB_OUTSTANDING_REQ_NISO_0 ,Cycles of throttle after each requesn" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "EMEM_ARB_OUTSTANDING_REQ_NISO_0,Highest Ring Input NISO Outstanding Request Limiter"
|
|
bitfld.long 0x04 31. " LIMIT_OUTSTANDING_NISO ,Requests into NISO" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " LIMIT_DURING_HOLDOFF_OVERRIDE_NISO ,Overrides the limiting of NISO transactions" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 16.--24. 1. " ARB_OUTSTANDING_COUNT_NISO ,Current number of outstanding requests"
|
|
hexmask.long.word 0x04 0.--8. 1. " ARB_MAX_OUTSTANDING_NISO ,The maximum number of requests allowed in the arbiter when limit is enabled"
|
|
line.long 0x08 "EMEM_ARB_NISO_THROTTLE_MASK_0,Highest Ring Input NISO Throttle Mask"
|
|
bitfld.long 0x08 29. " NISO_THROTTLE_MASK_VICPC ,Include VICPC in the NISO meta-client group for throttling" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " NISO_THROTTLE_MASK_USBD ,Include USBD in the NISO meta-clent group for throttling" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " NISO_THROTTLE_MASK_HOST ,Include HOST in the NISO meta-client group for throttling" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " NISO_THROTTLE_MASK_AUD ,Include AUD in the NISO meta-client group for throttling" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " NISO_THROTTLE_MASK_SD ,Include SD in the NISO meta client group for throttling" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " NISO_THROTTLE_MASK_GK ,IncludeGK in the NISO meta-client group for throttling" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " NISO_THROTTLE_MASK_MSE ,Include MSE in the NISO meta-client group for throttling" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " NISO_THROTTLE_MASK_USBX ,Include USBX in the NISO meta-client group for throttling" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 14. " NISO_THROTTLE_MASK_VD ,Include in the NISO meta-client group for throttling" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " NISO_THROTTLE_MASK_SAX ,Include SAX in the NISO meta-client group for throttling" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " NISO_THROTTLE_MASK_FTOP ,Include FTOP in the NISO meta-client group for throttling" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " NISO_THROTTLE_MASK_PCX ,Include PCX in the NISO meta-client group for throttling" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " NISO_THROTTLE_MASK_AVP ,Include AVP in the NISO meta-client group for throttling" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " NISO_THROTTLE_MASK_APB ,Include APB in the NISO meta-client group for throttling" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " NISO_THROTTLE_MASK_AHB ,Include AHB in the NISO meta-client group for throttling" "Disabled,Enabled"
|
|
line.long 0x0C "EMEM_ARB_RING0_THROTTLE_MASK_0,Ring0 Input Throttle Mask"
|
|
bitfld.long 0x0C 31. " ARB_OUTSTANDING_COUNT_ABOVE_SMMU , Enable ARB_OUTSTANDING count includes requests in SMMU" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " RING0_THROTTLE_MASK_RING1_OUTPUT ,Include the RING1 output in the ring0 meta-client group throttling" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " RING0_THROTTLE_MASK_R0_DISB ,Include R0_DISB in the ring0 meta-client group for throttling" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " RING0_THROTTLE_MASK_R0_DIS ,Include R0_DIS in the ring0 meta-client group for throttling" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " RING0_THROTTLE_MASK_R0_MEM ,Include MEM in the ring0 meta-client group for throttling" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " RING0_THROTTLE_MASK_PTC ,Include MEM in the ring0 mea-client group for throttling" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " RING0_THROTTLE_MASK_MMU , Include MMU in the ring0 meta-client group for throttling" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " RING0_THROTTLE_MASK_MPCORER ,Include MPCORER in the ring0 meta-client group for throttling" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x954++0x03
|
|
line.long 0x00 "PC_IDLE_CLOCK_GATE_0 ,Partition Idle Clock Gate"
|
|
bitfld.long 0x00 29. " VICPC_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the VICPC partition" "Not gated,Gated on idle"
|
|
bitfld.long 0x00 28. " USBD_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the USBD partition" "Not gated,Gated on idle"
|
|
textline " "
|
|
bitfld.long 0x00 27. " HOST_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the HOST partition" "Not gated,Gated on idle"
|
|
bitfld.long 0x00 26. " AUD_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the AUD partition" "Not gated,Gated on idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ISP_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the ISP partition" "Not gated,Gated on idle"
|
|
bitfld.long 0x00 23. " SD_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the SD partition" "Not gated,Gated on idle"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GK_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the GK partition" "Not gated,Gated on idle"
|
|
bitfld.long 0x00 20. " VE2_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the VE2 partition" "Not gated,Gated on idle"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MSE_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the MSE partition" "Not gated,Gated on idle"
|
|
bitfld.long 0x00 18. " DISB_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the DISB partition" "Not gated,Gated on idle"
|
|
textline " "
|
|
bitfld.long 0x00 17. " USBX_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the USBX partition" "Not gated,Gated on idle"
|
|
bitfld.long 0x00 15. " VE_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the VE partition" "Not gated,Gated on idle"
|
|
textline " "
|
|
bitfld.long 0x00 14. " VD_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the VD partition" "Not gated,Gated on idle"
|
|
bitfld.long 0x00 9. " SAX_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the SAX partition" "Not gated,Gated on idle"
|
|
textline " "
|
|
bitfld.long 0x00 8. " FTOP_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the FTOP partition" "Not gated,Gated on idle"
|
|
bitfld.long 0x00 7. " PCX_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the PCX partition" "Not gated,Gated on idle"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DIS_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the DIS partition" "Not gated,Gated on idle"
|
|
bitfld.long 0x00 3. " AVP_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the AVP partition" "Not gated,Gated on idle"
|
|
textline " "
|
|
bitfld.long 0x00 2. " APB_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the APB partition" "Not gated,Gated on idle"
|
|
bitfld.long 0x00 1. " AHB_IDLE_CLOCK_GATE_ENABLE ,Idle clock gate control for the AHB partition" "Not gated,Gated on idle"
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "EMEM_ARB_OVERRIDE_1_0,MC emem arb override 1_0"
|
|
bitfld.long 0x00 5. " EXPIRE_UPDATE_DEADLOCK_OVERRIDE ,Expire update deadlock override" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--4. " CPU_READ_PAGE_OPEN_POLICY ,CPU read page open policy" "Disabled,All,Eack_active,Early_ack_enable,Po_hint,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CPU_WRITE_PAGE_OPEN_POLICY ,Cpu write page open policy" "Disabled,All,Eack_hint,?..."
|
|
group.long 0x970++0x07
|
|
line.long 0x00 "CLIENT_HOTRESET_CTRL_1_0,Memory Client Hot Reset Control Registe"
|
|
bitfld.long 0x00 2. " GPU_FLUSH_ENABLE ,GPU flush enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ISP2B_FLUSH_ENABLE ,ISP2B flush enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SDMMC4A_FLUSH_ENABLE ,SDMMC4A flush enable" "Disabled,Enabled"
|
|
line.long 0x04 "CLIENT_HOTRESET_STATUS_1_0,Memory Client Hot Reset Status Register"
|
|
bitfld.long 0x04 2. " GPU_HOTRESET_STATUS ,GPU hotreset status" "Done,In progress"
|
|
bitfld.long 0x04 1. " ISP2B_HOTRESET_STATUS ,ISP2B hotreset status" "Done,In progress"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SDMMC4A_HOTRESET_STATUS ,SDMMC4A hotreset status" "Done,In progress"
|
|
group.long 0x984++0x07
|
|
line.long 0x00 "VIDEO_PROTECT_GPU_OVERRIDE_0_0,MC Video Protect GPU override 0 0"
|
|
line.long 0x04 "VIDEO_PROTECT_GPU_OVERRIDE_1_0,MC Video Protect GPU override 1 0"
|
|
hexmask.long.word 0x04 0.--15. 1. " VIDEO_PROTECT_GPU_OVERRIDE_1 ,Video protect GPU override 1"
|
|
group.long 0x9A0++0x0F
|
|
line.long 0x00 "MTS_CARVEOUT_BOM_0,MC mts carveout bom 0"
|
|
hexmask.long.word 0x00 20.--31. 1. " MTS_CARVEOUT_BOM ,MTS carveout BOM"
|
|
line.long 0x04 "MTS_CARVEOUT_SIZE_MB_0,MC MTS carveout size MB 0"
|
|
hexmask.long.word 0x04 0.--11. 1. " MTS_CARVEOUT_SIZE_MB ,MTS carveout size MB"
|
|
line.long 0x08 "MTS_CARVEOUT_ADR_HI_0,MC mts carveout address hi 0"
|
|
bitfld.long 0x08 0.--1. " MTS_CARVEOUT_BOM_HI ,MTS carveout BOM Hi" "0,1,2,3"
|
|
line.long 0x0C "MTS_CARVEOUT_REG_CTRL_0,MC MTS carveout reg control 0"
|
|
bitfld.long 0x0C 0. " MTS_CARVEOUT_WRITE_ACCESS , MTS carveout write access" "Enabled,Disabled"
|
|
group.long 0x9B8++0x07
|
|
line.long 0x00 "SMMU_PTC_FLUSH_1_0,Page Table Cache Flush Address Register"
|
|
bitfld.long 0x00 0.--1. " PTC_FLUSH_ADR_HI ,Physical address of PTE group to match for address flushes" "b00,b01,b10,b11"
|
|
line.long 0x04 "SECURITY_CFG3_0,Secure/Carveout Region Configuration"
|
|
bitfld.long 0x04 0.--1. " SECURITY_BOM_HI ,Higher address bits beyond 32 bits of the base of the secured region" "b00,b01,b10,b11"
|
|
textline " "
|
|
if (((d.l(ad:0x70019000+0x664))&0x01)==0x00)
|
|
group.long 0x9C0++0x0F
|
|
line.long 0x00 "EMEM_BANK_SWIZZLE_CFG0_0,Bank Swizzling Register CFG0"
|
|
hexmask.long.word 0x00 0.--15. 1. " EMEM_BANK_MASK0 ,Emem bank mask 0"
|
|
line.long 0x04 "EMEM_BANK_SWIZZLE_CFG1_0,Bank Swizzling Register CFG1"
|
|
hexmask.long.word 0x04 0.--15. 1. " EMEM_BANK_MASK1 ,Emem bank mask 1"
|
|
line.long 0x08 "EMEM_BANK_SWIZZLE_CFG2_0,Bank Swizzling Register CFG2"
|
|
hexmask.long.word 0x08 0.--15. 1. " EMEM_BANK_MASK2 ,Emem bank mask 2"
|
|
line.long 0x0C "EMEM_BANK_SWIZZLE_CFG3_0,Bank Swizzling Register CFG3"
|
|
bitfld.long 0x0C 0.--2. " EMEM_BANK_SWIZCOL ,Emem Bank Swizcol" "None,1Kb,2Kb,2Kb_offset_2,2Kb_offset_4,?..."
|
|
else
|
|
rgroup.long 0x9C0++0x0F
|
|
line.long 0x00 "EMEM_BANK_SWIZZLE_CFG0_0,Bank Swizzling Register CFG0"
|
|
hexmask.long.word 0x00 0.--15. 1. " EMEM_BANK_MASK0 ,Emem bank mask 0"
|
|
line.long 0x04 "EMEM_BANK_SWIZZLE_CFG1_0,Bank Swizzling Register CFG1"
|
|
hexmask.long.word 0x04 0.--15. 1. " EMEM_BANK_MASK1 ,Emem bank mask 1"
|
|
line.long 0x08 "EMEM_BANK_SWIZZLE_CFG2_0,Bank Swizzling Register CFG2"
|
|
hexmask.long.word 0x08 0.--15. 1. " EMEM_BANK_MASK2 ,Emem bank mask 2"
|
|
line.long 0x0C "EMEM_BANK_SWIZZLE_CFG3_0,Bank Swizzling Register CFG3"
|
|
bitfld.long 0x0C 0.--2. " EMEM_BANK_SWIZCOL ,Emem Bank Swizcol" "None,1Kb,2Kb,2Kb_offset_2,2Kb_offset_4,?..."
|
|
endif
|
|
group.long 0x9D4++0x03
|
|
line.long 0x00 "MC_SEC_CARVEOUT_ADR_HI_0,MC sec carveout adr hi 0"
|
|
bitfld.long 0x00 0.--1. " SEC_CARVEOUT_BOM_HI ,Higher address bits beyond 32 bits of the base address of the SEC carveout space" "b00,b01,b10,b11"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EMC"
|
|
base ad:0x7001B000
|
|
width 12.
|
|
group.long 0x00++0x07 "Interrupt Status & Mask"
|
|
line.long 0x00 "INSTATUS_0,Interrupt status register"
|
|
eventfld.long 0x00 9. " DLL_LOCK_TIMEOUT_INT ,Indicate a DLL lock timeout has occured" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " CCFIFO_OVERFLOW_INT ,Clock change FIFO overflow" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " DLL_ALARM_INT ,Indicate DLL alarm has been set" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 6. " ACCESS_TO_SR_DPD_DEV_INT ,Indicate system attempt to access a self-refresh/deep-powered-down device" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " MRR_DIVLD_INT ,LPDDR2 MRR data is available to be read" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " CLKCHANGE_COMPLETE_INT ,CAR/EMC clock-change handshake complete" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " REFRESH_OVERFLOW_INT ,Refresh request overflow timeout" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTMASK_0,Interrupt mask register"
|
|
bitfld.long 0x04 9. " DLL_LOCK_TIMEOUT_INTMASK ,Mask for DLL lock timeout interrupt" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " CCFIFO_OVERFLOW_INTMASK ,Mask for clock change FIFO overflow" "Masked,Unmasked"
|
|
bitfld.long 0x04 7. " DLL_ALARM_INT ,Indicate DLL alarm has been set" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " ACCESS_TO_SR_DPD_DEV_INTMASK ,Mask for access a self-refresh/deep-powered-down device interrupt" "Masked,Unmasked"
|
|
bitfld.long 0x04 5. " MRR_DIVLD_INTMASK ,Mask for MRR data available" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " CLKCHANGE_COMPLETE_INTMASK ,Mask for CAR/EMC clock-change handshake complete" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " REFRESH_OVERFLOW_INTMASK ,Mask for refresh request overflow timeout" "Masked,Unmasked"
|
|
width 11.
|
|
group.long 0x08++0x0B "EMC Configuration"
|
|
line.long 0x00 "DBG_0,Debug register"
|
|
bitfld.long 0x00 24. " CFG_PRIORITY ,Priority of cfg accesses to the DRAM" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SUPPRESS_WRITE_CMD ,Suppress write command sent to DRAM" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SUPPRESS_READ_CMD ,Suppress read command sent to DRAM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STRETCH_MRW_RESET ,Stretch MRW RESET command to three clocks" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " AP_REQ_BUSY_CTRL ,APC fifo busy signal enable to stall requests to the EMC" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " READ_DQM_CTRL ,DQM signal control" "Managed,Always on"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FORCE_UPDATE ,Active state update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WRITE_MUX ,Controls state of the writes to the configuration registers" "Assembly,Active"
|
|
bitfld.long 0x00 0. " READ_MUX ,Controls state of the reads to the configuration registers" "Active,Assembly"
|
|
textline " "
|
|
line.long 0x04 "CFG_0,Configuration register"
|
|
bitfld.long 0x04 31. " DRAM_CLKSTOP_PD ,DRAM clockstop (powerdown)" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " DRAM_CLKSTOP_SR ,DRAM clockstop (self-refresh)" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " DRAM_ACPD ,Opportunistic active powerdown for DRAM controller" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " DYN_SELF_REF ,DYN_SELF_REF" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " REQACT_ASYNC ,Transfers of activates and transactions from the MC to EMC" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " AUTO_PRE_WR ,MC auto-precharge indication for writes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24. " AUTO_PRE_RD ,MC auto-precharge indication for reads" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " MAN_PRE_WR ,[PMC3] Explicit-precharge in the EMC for writes" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " MAN_PRE_RD ,[PMC3] Explicit-precharge in the EMC for reads" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " PERIODIC_QRST ,[PMC] Specifies periodic reset FBIO read-data fifo during normal operation" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " EN_DYNAMIC_PUTERM ,Enable dynamic puterm" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " DLY_WR_DQ_HALF_CLOCK ,Delay write data by 1/2 clock" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " DSR_VTTGEN_DRV_EN ,Enable VTTGEN controls during DSR" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--17. " EMC2MC_CLK_RATIO ,EMC to MC clock ratio" "2,1,4,"
|
|
bitfld.long 0x04 9. " WAIT_FOR_ISP2B_READY_B4_CC ,Wait for isp2b ready event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAIT_FOR_VI2_READY_B4_CC ,Wait for vi2 ready event" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " WAIT_FOR_ISP2_B4_CC ,Wait for isp2 ready event" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " INVERT_DQM ,invert DQM polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WAIT_FOR_DISPLAYB_READY_B4_CC ,Wait for displayb ready event" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " WAIT_FOR_DISPLAY_READY_B4_CC ,Wait for display ready event" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " EMC2PMACRO_CFG_BYPASS_DATAPIPE2 ,Bypass data pipeline stage2 between EMC and data pad macro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EMC2PMACRO_CFG_BYPASS_DATAPIPE1 ,Bypass data pipeline stage1 between EMC and data pad macro" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " EMC2MACRO_CFG_BYPASS_ADDRPIPE ,Bypass address pipeline stage between EMC and address pad-macro" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x08 "ADR_CFG_0,External memory address configuration [system]"
|
|
bitfld.long 0x08 0. " EMEM_NUMDEV ,Number of populated DRAM devises" "N1,N2"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "REFCTRL_0,Refresh control register"
|
|
bitfld.long 0x00 31. " REF_VALID ,Enable refresh controller" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " DEVICE_REFRESH_DISABLE ,Refresh disable to individual attached device" "0,1,2,3"
|
|
textline " "
|
|
line.long 0x04 "PIN_0,Controls state of selected DRAM pins"
|
|
bitfld.long 0x04 8. " PIN_RESET ,DDR3 RESET# pin level" "Active,Inactive"
|
|
bitfld.long 0x04 4. " PIN_DQM ,Used to always mask DRAM writes" "Normal,Inactive"
|
|
bitfld.long 0x04 0. " PIN_CKE ,Level of the CKE pin" "Power down,Normal"
|
|
textline " "
|
|
tree "Timing control"
|
|
width 18.
|
|
group.long 0x28++0x93
|
|
line.long 0x00 "TIMING_CONTROL_0,Triggers an update of the timing-related registers"
|
|
bitfld.long 0x00 0. " TIMING_UPDATE ,Timing update event" "Disabled,Enabled"
|
|
line.long 0x04 "RC_0,DRAM RC timing parameter"
|
|
hexmask.long.byte 0x04 0.--6. 1. " RC ,Row cycle time"
|
|
line.long 0x08 "RFC_0,DRAM RFC timing parameter"
|
|
hexmask.long.word 0x08 0.--8. 1. " RFC ,Auto refresh cycle time"
|
|
line.long 0x0C "RAS_0,DRAM RAS timing parameter"
|
|
bitfld.long 0x0C 0.--5. " RAS ,Row active time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "RP_0,DRAM RP timing parameter"
|
|
bitfld.long 0x10 0.--5. " RP ,Row precharge time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "EMP_R2W_0,DRAM R2W timing parameter"
|
|
bitfld.long 0x14 0.--4. " R2W ,Read to write commands number of cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "W2R_0,DRAM W2R timing parameter"
|
|
bitfld.long 0x18 0.--4. " W2R ,Write to read commands number of cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1C "R2P_0,DRAM R2P timing parameter"
|
|
bitfld.long 0x1C 0.--4. " R2P ,Read to precharge commands for the same bank number of cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x20 "W2P_0,DRAM W2P timing parameter"
|
|
bitfld.long 0x20 0.--5. " W2P ,Write to precharge commands for the same bank number of cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x24 "RD_RCD_0,DRAM RD_RCD timing parameter"
|
|
bitfld.long 0x24 0.--5. " RD_RCD ,Ras to cas delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x28 "WR_RCD_0,DRAM WR_RCD timing parameter"
|
|
bitfld.long 0x28 0.--5. " WR_RCD ,Minimum number of cycles between activate and write commands to the same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x2C "RRD_0,DRAM RRD timing parameter"
|
|
bitfld.long 0x2C 0.--3. " RRD ,Bank X Act to Bank Y Act command delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x30 "REXT_0,DRAM REXT timing parameter"
|
|
bitfld.long 0x30 0.--3. " REXT ,Read to read delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x34 "WDV_0,DRAM WDV timing parameter"
|
|
bitfld.long 0x34 0.--3. " WDV ,Write data assertion to the rams delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x38 "QUSE_0,DRAM QUSE timing parameter"
|
|
bitfld.long 0x38 0.--5. " QUSE ,Tells the chip when to look for read return data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x3C "QRST_0,DRAM QRST timing parameter"
|
|
bitfld.long 0x3C 0.--5. " QRST ,Time from expiration of QSAFE until reset is issued" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x40 "QSAFE_0,DRAM QSAFE timing parameter"
|
|
bitfld.long 0x40 0.--4. " QSAFE ,Time from a read command to when it is safe to issue a QRST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x44 "RDV_0,DRAM RDV timing parameter"
|
|
bitfld.long 0x44 0.--5. " RDV ,Time from read command to latching the read data from the pad macros" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x48 "REFRESH_0,DRAM REFRESH timing parameter"
|
|
hexmask.long.word 0x48 6.--15. 1. " REFRESH ,Interval between refresh requests"
|
|
bitfld.long 0x48 0.--5. " REFRESH_LO ,REFRESH_LO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x4C "BURST_REFRESH_NUM,Refresh burst count"
|
|
bitfld.long 0x4C 0.--3. " BURST_REFRESH_NUM ,Refresh burst count" "BR1,BR2,BR4,BR8,BR16,BR32,BR64,BR128,BR256,BR512,MAX,,,,,"
|
|
line.long 0x50 "PDEX2WR_0,DRAM PDEX2WR timing parameter"
|
|
bitfld.long 0x50 0.--5. " PDEX2WR ,Timing delay from exit of powerdown mode to a write command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x54 "PDEX2RD_0,DRAM PREX2RD timing parameter"
|
|
bitfld.long 0x54 0.--5. " PDEX2RD ,Timing delay from exit of powerdown mode to a read command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x58 "PCHG2PDEN_0,DRAM PCHG2PDEN timing parameter"
|
|
bitfld.long 0x58 0.--5. " PCHG2PDEN ,Timing delay from a precharge command to powerdown" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x5C "ACT2PDEN_0,DRAM ACT2PDEN timing parameter"
|
|
bitfld.long 0x5C 0.--5. " ACT2PDEN ,Timing delay from an activate,mrs or emrs command to powerdown entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x60 "AR2PDEN_0,DRAM AR2PDEN timing parameter"
|
|
hexmask.long.word 0x60 0.--8. 1. " AR2PDEN ,Timing delay from an autorefresh command to powerdown entry"
|
|
line.long 0x64 "RW2PDEN_0,DRAM RW2PDEN timing parameter"
|
|
bitfld.long 0x64 0.--5. " RW2PDEN ,Timing delay from a read/write command to powerdown entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x68 "TXSR_0,DRAM TXSR timing parameter"
|
|
hexmask.long.word 0x68 0.--9. 1. " TXSR ,Cycles between self-refresh exit & first DRAM command that doesn't require a locked DLL"
|
|
line.long 0x6C "TCKE_0,DRAM TCKE timing parameter"
|
|
bitfld.long 0x6C 0.--5. " TCKE ,Minimum CKE pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x70 "TFAW,DRAM TFAW timing parameter"
|
|
hexmask.long.byte 0x70 0.--6. 1. " TFAW ,Width of the FAW for 8-bank devices"
|
|
line.long 0x74 "TRPAB_0,DRAM TRPAB timing parameter"
|
|
bitfld.long 0x74 0.--5. " TRPAB ,Precharge-all tRP allowance for 8-bank devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x78 "TCLKSTABLE_0,DRAM TCLKSTABLE timing parameter"
|
|
bitfld.long 0x78 0.--4. " TCLKSTABLE ,Minimum number of cycles of a stable clock period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x7C "TCLKSTOP_0,DRAM TCLKSTOP timing parameter"
|
|
bitfld.long 0x7C 0.--4. " TCLKSTOP ,Delay from last command to stopping the external clock to DRAM devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x80 "TREFBW_0,DRAM TREFBW timing parameter"
|
|
hexmask.long.word 0x80 0.--13. 1. " TREFBW ,Width of the burst-refresh window"
|
|
line.long 0x84 "ODT_WRITE_0,ODT write control"
|
|
bitfld.long 0x84 31. " ENABLE_ODT_DURING_WRITE ,ODT enable during write" "Disabled,Enabled"
|
|
bitfld.long 0x84 30. " ODT_B4_WRITE ,ODT turn on timing according to dram write command" "Before,After"
|
|
bitfld.long 0x84 8.--11. " ODT_WR_DURATION ,Indicate how long to assert ODT by" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x84 5. " SHARE_ONE_ODT , Share one ODT" "Disabled,Enabled"
|
|
bitfld.long 0x84 4. " DRIVE_BOTH_ODT ,ODTs' assertion for the requested or both devices" "Requested,Both"
|
|
bitfld.long 0x84 0.--3. " ODT_WR_DELAY ,ODT write delay" "0,1,2,3,..."
|
|
line.long 0x88 "WEXT_0,DRAM WEXT timing parameter"
|
|
bitfld.long 0x88 0.--3. " WEXT ,Write to write delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x8C "CTT_0,DRAM CTT timing parameter"
|
|
hexmask.long.byte 0x8C 0.--4. 1. " CTT ,Time from read command to CTT turn-on on DDR3"
|
|
line.long 0x90 "EMC_RFC_SLR_0,DRAM RFC_SLR timing parameter"
|
|
hexmask.long.word 0x90 0.--8. 1. " RFS_SLR ,Stagger refresh cycle time between ranks"
|
|
tree.end
|
|
tree "Command Triggers Control"
|
|
width 17.
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "MRS_WAIT_CNT2_0,Delay between a MRS and the following DRAM commands"
|
|
hexmask.long.word 0x00 16.--25. 1. " MRS_LONG_WAIT_CNT ,Number of emc clocks to wait [MRS long command]"
|
|
hexmask.long.word 0x00 0.--9. 1. " MRS_SHORT_WAIT_CNT ,Number of emc clocks to wait [MRS short command]"
|
|
group.long 0xC8++0x1F
|
|
line.long 0x00 "MRS_WAIT_CNT_0,Delay between a MRS and the following DRAM commands"
|
|
hexmask.long.word 0x00 16.--25. 1. " MRS_LONG_WAIT_CNT ,Number of emc clocks to wait [MRS long command]"
|
|
hexmask.long.word 0x00 0.--9. 1. " MRS_SHORT_WAIT_CNT ,Number of emc clocks to wait [MRS short command]"
|
|
line.long 0x04 "MRS_0,Command trigger for MRS"
|
|
bitfld.long 0x04 30.--31. " MRS_DEV_SELECTN ,Active low chip-select" "Both devices,Dev1,Dev0,"
|
|
bitfld.long 0x04 27. " USE_MRS_EXT_CNT , Mrs ext cnt" "Short/Long,Ext1/Ext2"
|
|
bitfld.long 0x04 26. " USE_MRS_LONG_CNT ,Use short or long MRS wait count" "Short,Long"
|
|
textline " "
|
|
bitfld.long 0x04 20.--21. " MRS_BA ,Registers to be addressed in DRAM" "MRS,EMRS,EMRS2,EMRS3"
|
|
hexmask.long.word 0x04 0.--13. 1. " MRS_ADR ,Mode-register data to be written"
|
|
line.long 0x08 "EMRS_0,Command trigger for EMRS"
|
|
bitfld.long 0x08 30.--31. " EMRS_DEV_SELECTN ,Active low chip-select" "Both devices,Dev1,Dev0,..."
|
|
bitfld.long 0x08 27. " USE_EMRS_EXT_CNT , Mrs ext cnt" "Short/Long,Ext1/Ext2"
|
|
bitfld.long 0x08 26. " USE_EMRS_LONG_CNT ,Use short or long EMRS wait count" "Short,Long"
|
|
textline " "
|
|
bitfld.long 0x08 20.--21. " EMRS_BA ,Registers to be addressed in DRAM" "MRS,EMRS,EMRS2,EMRS3"
|
|
hexmask.long.word 0x08 0.--13. 1. " EMRS_ADR ,Mode-register data to be written"
|
|
line.long 0x0C "REF_0,Command trigger for refresh"
|
|
bitfld.long 0x0C 30.--31. " REF_DEV_SELECTN ,Active low chip-select" "Both devices,Dev1,Dev0,..."
|
|
hexmask.long.byte 0x0C 8.--15. 1. " REF_NUM ,Number of refresh cycles (REF_NUM+1)"
|
|
bitfld.long 0x0C 1. " REF_NORMAL ,Refresh execution mechanism" "Immediate,Normal"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " REF_CMD ,Refresh to all DRAM banks" "Disabled,Enabled"
|
|
line.long 0x10 "PRE_0,Command trigger for PRECHARGE-ALL"
|
|
bitfld.long 0x10 30.--31. " PRE_DEV_SELECTN ,Active low chip-select" "Both devices,Dev1,Dev0,..."
|
|
bitfld.long 0x10 0. " PRE_CMD ,PRECHARGE to all DRAM banks" "Disabled,Enabled"
|
|
line.long 0x14 "NOP_0,Command trigger for NOP"
|
|
bitfld.long 0x14 30.--31. " NOP_DEV_SELECTN ,Active low chip-select" "Both devices,Dev1,Dev0,..."
|
|
bitfld.long 0x14 0. " NOP_CMD ,NOP to all DRAM banks" "Disabled,Enabled"
|
|
line.long 0x18 "SELF_REF_0,Command trigger for self refresh"
|
|
bitfld.long 0x18 30.--31. " SREF_DEV_SELECTN ,Active low chip-select" "Both devices,Dev1,Dev0,..."
|
|
bitfld.long 0x18 0. " SREF_REF_CMD ,Issue a SELF_REFRESH command" "Disabled,Enabled"
|
|
line.long 0x1C "DPD_0,Comand trigger for DPD"
|
|
bitfld.long 0x1C 30.--31. " DPD_DEV_SELECTN ,Active low chip-select" "Both devices,Dev1,Dev0,..."
|
|
bitfld.long 0x1C 0. " DPD_CMD ,Issue a deep power down command" "Disabled,Enabled"
|
|
wgroup.long 0xE8++0x03
|
|
line.long 0x00 "MRW_0,Command trigger for MRW"
|
|
bitfld.long 0x00 30.--31. " MRW_DEV_SELECTN ,Active low chip-select" "Both devices,Dev1,Dev0,"
|
|
bitfld.long 0x00 27. " USE_MRW_EXT_CNT ,Select between short/long and ext1/ext2" "Short/Long,Ext1/Ext2"
|
|
bitfld.long 0x00 26. " USE_MRW_LONG_CNT ,Indicate to use MRS wait count" "Short,Long"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " MRW_MA ,Register address"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MRW_OP ,Data to be written"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "MRR_0,Command trigger for MRR"
|
|
bitfld.long 0x00 30.--31. " MRR_DEV_SELECTN ,Active-low chip-select" "Illegal,Dev1,Dev0,"
|
|
bitfld.long 0x00 27. " USE_MRR_EXT_CNT ,Select between short/long and ext1/ext2" "Short/Long,Ext1/Ext2"
|
|
bitfld.long 0x00 26. " USE_MRR_LONG_CNT ,Indicate to use MRS wait count" "Short,Long"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " MRR_MA ,Register address"
|
|
hexmask.long.word 0x00 0.--15. 1. " MRR_OP ,Data returned"
|
|
group.long 0xF0++0x07
|
|
line.long 0x00 "CMDQ_0,Command QUEUE Depth Register"
|
|
bitfld.long 0x00 24.--28. " RW_WD_DEPTH , Rw wd depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "MC2EMCQ_0,Command Queue Depth Register"
|
|
bitfld.long 0x04 24.--27. " MCWD_DEPTH ,Mcwd depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--10. " MCACT_DEPTH ,Mcact depth" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " MCREQ_DEPTH ,Mcreq depth" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "Pad and FBIO control"
|
|
width 18.
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "XM2DQSPADCTRL3_0,XM2DQS Pad Control"
|
|
bitfld.long 0x00 26.--30. " EMC2PMACRO_CFG_XM2DQS_BYTE3_VREF_DQS ,Emc2pmacro_cfg_xm2dqs_byte3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20.--24. " EMC2PMACRO_CFG_XM2DQS_BYTE2_VREF_DQS ,Emc2pmacro_cfg_xm2dqs_byte2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 14.--18. " EMC2PMACRO_CFG_XM2DQS_BYTE1_VREF_DQS ,Emc2pmacro_cfg_xm2dqs_byte1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " EMC2PMACRO_CFG_XM2DQS_BYTE0_VREF_DQS ,Emc2pmacro_cfg_xm2dqs_byte0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMC2PMACRO_CFG_XM2DQS_E_VREF_DQS ,EMC2PMACRO_CFG_XM2DQS_E_VREF_DQS" "0,1"
|
|
bitfld.long 0x00 0. " EMC2PMACRO_CFG_XM2DQS_E_STRPULL_DQS ,EMC2PMACRO_CFG_XM2DQS_E_STRPULL_DQS" "0,1"
|
|
textline " "
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FBIO_SPARE_0,FBIO Spare Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CFG_FBIO_SPARE_3 ,Cfg fbio spare 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CFG_FBIO_SPARE_2 ,Cfg fbio spare 2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CFG_FBIO_SPARE_1 ,Cfg fbio spare 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CFG_FBIO_SPARE_0 ,Cfg fbio spare 0"
|
|
textline " "
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "FBIO_CFG5_0,FBIO Configuration Register"
|
|
bitfld.long 0x00 28. " MASK_PUTERM_N_DQS_PULLD_DURING_ZQCAL ,Deasserts DQ/DQS" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " CMD_BUS_RETURN_TO_ONE ,Drives the cmd bus back to a one as resting stage" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LPDDR3_DRAM ,Enables differentiation between lpddr3/lpddr2 DRAM protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LPDDR3_WR_PREAMBLE_TOGGLE ,Enable LPDDR3 write preamble toggle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ERR_RD_BUBBLE ,Number of bubbles to be inserted in CMDQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CMD_MAPPING ,CMD mapping" "DDR3L_4X16,DSC_LPDDR3_1X64_253,DSC_LPDDR2_2X32_134,DSC_LPDDR3_2X32_178,DSC_DDR3L_2X32_136,DSC_DDR3L_4X16_96_2X2H,DSC_DDR3L_4X16_96_2X2V,DSC_DDR3L_4X16_96_2TBV,DSC_DDR3L_4X16_96_2TBH,DSC_DDR3L_4X16_96_1X4_2LYR,MID_DDR3L_4X16_96_4TOP,MID_DDR3L_2X32_136,MID_DDR3L_8X8_78_8TOP,MID_DDR3L_4X16_96_4BOT,MID_DDR3L_4X16_96_2T2B_SWONLY,..."
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. " EMC2PMACRO_CFG_QUSE_MODE ,Quse mode select" "Normal,Always on,Internal LPBK,Pulse_int,,Direct_quse,..."
|
|
bitfld.long 0x00 12. " CMD_2T_TIMING ,2T command timing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CFG_QUSE_EXTEND_HALF_CLK ,Extend rhe Quse windows by half clk in Direct_quse mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DISABLE_CONCURRENT_AUTOPRE ,Disable reads/writes to a device until precharge command" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DQS_PULLD ,Pulldowns on dqs lines enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CTT_TERMINATION ,CTT_TERMINATION mode in pads enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIFFERENTIAL_DQS ,Differential signalling on dqs strobes enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CFG_E_PUTERM_DQ ,Enables E_PUTERM_DQ mode in pads" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DRAM_DATA_SWZL ,Specifies which half of the data bytes are used in X32 mode" "Lower,Upper"
|
|
bitfld.long 0x00 4. " DRAM_WIDTH ,DRAM width specifies" "X32,X64"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DRAM_BURST ,Burst length to use for the attached device" "BURST4,BURST8,On the fly,"
|
|
bitfld.long 0x00 0.--1. " DRAM_TYPE ,DRAM protocol select for the attached device" "DDR3,DDR1,LPDDR2,DDR2"
|
|
textline " "
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FBIO_CFG6_0,FBIO configuration register"
|
|
bitfld.long 0x00 0.--2. " CFG_QUSE_LATE ,FBIO configuration register" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
group.long 0x120++0x07
|
|
line.long 0x00 "CFG_RSV_0,EMC Configuration Reserved"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CFG_RESERVED_BYTE3 ,Cfg reserved byte 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CFG_RESERVED_BYTE2 ,Cfg reserved byte 2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CFG_RESERVED_BYTE1 ,Cfg reserved byte 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CFG_RESERVED_BYTE0 ,Cfg reserved byte 0"
|
|
textline " "
|
|
line.long 0x04 "ACPD_CONTROL_0,Thereshold for ACPD"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACPD_THRESHOLD ,Number of idle cycles to wait before allowing power-down entry"
|
|
textline " "
|
|
group.long 0x12C++0x0F
|
|
line.long 0x00 "EMRS2_0,EMRS2 Command Trigger"
|
|
bitfld.long 0x00 30.--31. " EMRS2_DEV_SELECTN ,Active low chip select" "Both,Dev1,Dev2,"
|
|
bitfld.long 0x00 27. " USE_EMRS2_EXT_CNT ,Use mrs long cnt select" "Short/Long,Ext1/Ext2"
|
|
textline " "
|
|
bitfld.long 0x00 26. " USE_EMRS2_LONG_CNT ,Use long or short MRS wait count" "Short,Long"
|
|
bitfld.long 0x00 20.--21. " EMRS2_BA ,EMRS2 ba" ",EMRS,EMRS2,EMRS3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--13. 1. " EMRS2_ADR ,Mode register data to be written"
|
|
textline " "
|
|
line.long 0x04 "EMRS3_0,EMRS2 Command Trigger"
|
|
bitfld.long 0x04 30.--31. " EMRS3_DEV_SELECTN ,Active low chip select" "Both,Dev1,Dev0,"
|
|
bitfld.long 0x04 27. " USE_EMRS3_EXT_CNT ,Use mrs long cnt select between" "Short/Long,Ext1/Ext2"
|
|
textline " "
|
|
bitfld.long 0x04 26. " USE_EMRS3_LONG_CNT ,Indicate to use long or short MRS wait count" "Short,Long"
|
|
bitfld.long 0x04 20.--21. " EMRS3_BA ,EMRS3 ba" ",Emrs1,Emrs2,Emrs3"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--13. 1. " EMRS3_ADR ,Mode register data to be written"
|
|
textline " "
|
|
line.long 0x08 "MRW2_0,MRW2 Command trigger"
|
|
bitfld.long 0x08 30.--31. " MRW2_DEV_SELECTN ,Active low chip select" "Both,Dev1,Dev2,"
|
|
bitfld.long 0x08 27. " USE_MRW2_EXT_CNT ,Use mrs long cnt will select between" "Short/Long,Ext1/Ext2"
|
|
textline " "
|
|
bitfld.long 0x08 26. " USE_MRW2_LONG_CNT ,Indicate to use long or short MRS wait count" "Short,Long"
|
|
hexmask.long.byte 0x08 16.--23. 1. " MRW2_MA ,Register address"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " MRW2_OP ,Data to be written"
|
|
textline " "
|
|
line.long 0x0C "MRW3_0,MRW3 Command Trigger"
|
|
bitfld.long 0x0C 30.--31. " MRW3_DEV_SELECTN ,Active low chip select" "Both,Dev1,Dev2,"
|
|
bitfld.long 0x0C 27. " USE_MRW3_EXT_CNT ,Use mrs long cnt will select between" "Short/Long,Ext1/Ext2"
|
|
textline " "
|
|
bitfld.long 0x0C 26. " USE_MRW3_LONG_CNT ,Indicate to use long or short MRS wait count" "Short,Long"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " MRW3_MA ,Register address"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--7. 1. " MRW3_OP ,Data to be written"
|
|
textline " "
|
|
group.long 0x13C++0x07
|
|
line.long 0x00 "MRW4_0,MRW4 Command Trigger"
|
|
bitfld.long 0x00 30.--31. " MRW4_DEV_SELECTN ,Active low chip select" "Both,Dev1,Dev0,"
|
|
bitfld.long 0x00 27. " USE_MRW4_EXT_CNT ,Use mrs long cnt will select between" "Short/Long,Ext1/Ext2"
|
|
textline " "
|
|
bitfld.long 0x00 26. " USE_MRW4_LONG_CNT ,Indicate to use long or short MRS wait count" "Short,Long"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MRW4_MA ,Register address"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " MRW4_OP ,Data to be written"
|
|
textline " "
|
|
line.long 0x04 "CLKEN_OVERRIDE_0,Second Level Clock Enable Override Register"
|
|
bitfld.long 0x04 31. " OBS_BUS_CLKEN ,Obs bus clken" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " STATS_CLKEN_OVR ,Stats clken ovr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RR_CLKEN_OVR ,RR clken ovr" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " DRAMC_CLKEN_OVR ,Dramc clken ovr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CMDQ_CLKEN_OVR ,CMDQ clken ovr" "Disabled,Enabled"
|
|
textline " "
|
|
tree.end
|
|
width 23.
|
|
tree "Timing Parameter"
|
|
group.long 0x144++0x07
|
|
line.long 0x00 "EMC_R2R_0,EMC_R2R_0 Timing Parameter"
|
|
bitfld.long 0x00 0.--3. " R2R ,R2R" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "EMC_W2W_0 ,EMC_W2W_0 Timing Parameter"
|
|
bitfld.long 0x04 0.--3. " W2W ,W2W" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14C++0x013
|
|
line.long 0x00 "EMC_EINPUT_0,EMC_EINPUT_0 Timing Parameter"
|
|
bitfld.long 0x00 0.--5. " EINPUT ,Specifies when to assert EINPUT for a read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "EMC_EINPUT_DURATION_0,EMC_EINPUT_DURATION_0 Timing Parameter"
|
|
bitfld.long 0x04 0.--4. " EINPUT_DURATION ,Specifies how long the EINPUT should be asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "EMC_PUTERM_EXTRA_0,EMC_PUTERM EXTRA 0 Timing parameter"
|
|
bitfld.long 0x08 16.--21. " PUTERM ,Assert dynamic PUTERM for read return data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "EMC_TCKESR_0,EMC_TCKESR_0 Timing Parameter"
|
|
bitfld.long 0x0C 0.--5. " TCKESR ,Specify minimum low CKE pulse width for self-refresh mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "EMC_TPD_0,EMC_TPD_0 Timing Parameter"
|
|
bitfld.long 0x10 0.--5. " TPD ,Specify minimum low CKE pulse width for power-down mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
tree "Auto Calibration"
|
|
width 12.
|
|
group.long 0x2A4++0x07
|
|
line.long 0x00 "CONFIG_0,Auto-calibration settings for EMC pads"
|
|
rbitfld.long 0x00 31. " AUTO_CAL_START ,Start status of the calibration state machine" "Not started,Started"
|
|
bitfld.long 0x00 30. " AUTO_CAL_OVERRIDE ,Auto calibration override" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " AUTO_CAL_ENABLE ,Auto calibration enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " AUTOCAL_SLW_OVERRIDE ,Auto calibration SLW override" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 20.--25. 1. " AUTO_CAL_E_CAL_UPDATE ,Number of EMC clocks E_CAL_UPDATE is asserted"
|
|
bitfld.long 0x00 16.--18. " AUTO_CAL_STEP ,Calibration step interval (in microseconds" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " AUTO_CAL_PD_OFFSET ,2's complement offset for pull-down value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " AUTO_CAL_PU_OFFSET ,2's complement offset for pull-up value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "INTERVAL_0,EMC pad calibration interval"
|
|
hexmask.long.tbyte 0x04 0.--20. 1. " AUTO_CAL_INTERVAL ,Calibration interval value"
|
|
rgroup.long 0x2AC++0x03
|
|
line.long 0x00 "STATUS_0,EMC pad calibration status"
|
|
bitfld.long 0x00 31. " AUTO_CAL_ACTIVE ,Auto calibrate active status" "Not active,Active"
|
|
bitfld.long 0x00 24.--28. " AUTO_CAL_PULLDOWN_ADJ ,Pull-down code sent to pads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " AUTO_CAL_PULLup_ADJ ,Pull-up code sent to pads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " AUTO_CAL_PULLDOWN ,Pull-down code generated by auto-calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " AUTO_CAL_PULLUP ,Pull-up code generated by auto-calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
tree.end
|
|
tree "EMC Configuration 2"
|
|
width 14.
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "REQ_CTRL_0,Request status/control"
|
|
bitfld.long 0x00 1. " STALL_ALL_WRITES ,Stall incoming write transactions" "Not asserted,Asserted"
|
|
bitfld.long 0x00 0. " STALL_ALL_READS ,Stall incoming reads transactions" "Not asserted,Asserted"
|
|
rgroup.long 0x2B4++0x03
|
|
line.long 0x00 "EMC_STATUS_0,EMC state-machine status"
|
|
bitfld.long 0x00 26.--27. " ACPD_FSM_IDLE ,Indicate dev power-down FSM is die" "0,1,2,3"
|
|
bitfld.long 0x00 24.--25. " DSR_FSM_IDLE ,Indicate dev dynamic self refresh FSM is idle" "0,1,2,3"
|
|
bitfld.long 0x00 23. " TIMING_UPDATE_STALLED ,Indicate timing update" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ZQ_FSM_IDLE ,Indicate auto ZQ state machine is idle" "DIsabled,Enabled"
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|
bitfld.long 0x00 21. " CFG_ZQ_ACTIVE ,Indicates ZQ configuration access is active" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MRR_DIVLD ,Mrr data available for reading" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " MRR_FIFO_SPACE ,Mrr fifospace available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 13. " DRAM_IN_DPD_DEV1 ,Dev1 in deep powerdown state" "No,Yes"
|
|
bitfld.long 0x00 12. " DRAM_IN_DPD_DEV0 ,Dev0 in deep powerdown state" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DRAM_IN_SELF_REFRESH_DEV1 ,Dev1 in self-refresh" "No,Yes"
|
|
bitfld.long 0x00 8. " DRAM_IN_SELF_REFRESH_DEV0 ,Dev0 in self-refresh" "No,Yes"
|
|
bitfld.long 0x00 5. " DRAM_IN_POWERDOWN_DEV1 ,Dev1 in powerdown state" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DRAM_IN_POWERDOWN_DEV0 ,Dev0 in powerdown state" "No,Yes"
|
|
bitfld.long 0x00 2. " NO_OUTSTANDING_TRANSACTIONS ,All non-stalled requests complete status" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " EMC_REQ_FIFO_EMPTY ,Request fifo is empty" "Not empty,Empty"
|
|
group.long 0x2B8++0x03
|
|
line.long 0x00 "CFG_2_0,EMC configuration"
|
|
bitfld.long 0x00 31. " DRAMC_PRE_B4_ACT ,Gives priority to activates" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " USE_PER_DEVICE_DLY_TRIM_OB ,Allows using different outbound delay trim values" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " USE_PER_DEVICE_DLY_TRIM_IB ,REXT/RDV/Quse must be programmed to >=2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DIS_CNTR_WITH_CFG_TIMING_UPDATE ,Reset of timing parameter counters" "Enabled,Disabled"
|
|
bitfld.long 0x00 8.--9. " PIN_CONFIG ,Remaps address/command pins for LPDDR2 or LPDDR2_POP" "LPDDR2,LPDDR2_POP,,"
|
|
bitfld.long 0x00 7. " EARLY_TRFC_8_CLK ,Early TRFC 8 clk" "8,16"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DIS_STP_OB_CLK_DURING_NON_WR ,Stopping outbound data clock to I/O during non-write transactions" "Enabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ZQ_EXTRA_DELAY ,Additional delay to push out ZQCMD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " REF_AFTER_SREF ,Enables trigger of refresh after exiting self-refresh" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKCHANGE_PD_ENABLE ,Force DRAM into power-down during CLKCHANGE" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CLKCHANGE_REQ_ENABLE ,Allows EMC and CAR to handshake on PLL divider/source changes" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Digital DLL Configuration"
|
|
width 20.
|
|
group.long 0x2BC++0x07
|
|
line.long 0x00 "CFG_DIG_DLL_0,Configure digital DLL"
|
|
rbitfld.long 0x00 31. " CFG_DLL_USE_OVERRIDE_UNTIL_LOCK ,Override_val in use" "No,Yes"
|
|
rbitfld.long 0x00 30. " DLL_RESET ,Reset pulse sent to DLL's on next shadow update" "No,Yes"
|
|
bitfld.long 0x00 28.--29. " CFG_DLL_LOCK_LIMIT ,DLL treated as locked after LIMIT uSec" "16,64,128,512"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CFG_DLL_ALARM_DISABLE ,Disable override of DLL logic" "No,Yes"
|
|
rbitfld.long 0x00 26. " CFG_DLL_UPDATE_AT_NXT_REFRESH , Cause the DLCELL update to occur at the next rafresh interval" "No,Yes"
|
|
hexmask.long.word 0x00 16.--25. 1. " CFG_DLL_OVERRIDE_VAL ,Value to use in place of DLI output"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CFG_DLL_TESTEN ,Enable DLL test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CFG_DLL_QUSE_TESTOUT ,Enable DLL TESTOUT on Quse pads" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " CFG_DLL_TESTSEL ,Select DLL test output" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CFG_DLL_UDSET ,DLL Loop filter control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. " CFG_DLL_MODE ,Controls how frequently DLL runs" "Continuously,Till lock,Periodically,"
|
|
bitfld.long 0x00 5. " CFG_DLL_LOWSPEED ,Enable DLL for use with low-speed EMCCLK operation" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " CFG_DLL_STALL_RT_UNTIL_LOCK ,Stall all RW traffic until DLL locks by EMC" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CFG_DLL_STALL_ALL_TRAFFIC ,Enable stalling of all DRAM traffic" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CFG_DLL_OVERRIDE_EN ,Override DLL's DLI output with OVERRIDE_VAL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CFG_DLL_EN ,Enable digital DLL" "Disabled,Enabled"
|
|
line.long 0x04 "CFG_DIG_DLL_PERIOD,Interval between runs"
|
|
hexmask.long.word 0x04 0.--15. 1. " CFG_DLL_RUN_PERIOD ,Interval between runs in uSec"
|
|
rgroup.long 0x2C8++0x03
|
|
line.long 0x00 "DIG_DLL_STATUS_0,Digital DLL status"
|
|
bitfld.long 0x00 15. " DLL_LOCK ,DLL_LOCK" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " DLL_ALARM ,DLL_ALARM" "No alarm,Alarm"
|
|
bitfld.long 0x00 13. " DLL_LOCK_TIMEOUT ,DLL_LOCK_TIMEOUT" "No timeout,Timeout"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " DLL_OUT ,DLL_OUT"
|
|
group.long 0x2CC++0x07
|
|
line.long 0x00 "RDV_MASK_0,DRAM timing parameter"
|
|
bitfld.long 0x00 0.--5. " RDV_MASK ,Programmed to RDV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "WDV_MASK_0 ,DRAM timing parameter"
|
|
bitfld.long 0x04 0.--3. " WDV_MASK ,Programmed to WDV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2D8++0x07
|
|
line.long 0x00 "CTT_DURATION_0,DRAM timing parameter"
|
|
bitfld.long 0x00 0.--3. " CTT_DURATION ,Determines how long CTT remains enabled during reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
line.long 0x04 "CTT_TERM_CTRL_0,Configure CTT termination output drive strength"
|
|
bitfld.long 0x04 31. " TERM_OVERRIDE ,Forces us of EMC2TMC_CFG*_DRVDN_TERM and EMC2TMC_CFG*_DRVUP_TERM" "Disabled,Enabled"
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|
rbitfld.long 0x04 24.--28. " TERM_DRVUP ,TERM_DRVUP value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
rbitfld.long 0x04 15.--19. " TERM_DRVDN ,TERM_DRVDN value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 8.--12. " TERM_OFFSET ,TERM_OFFSET" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--2. " TERM_SLOPE ,TERM_SLOPE" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "ZQ Calibration"
|
|
width 17.
|
|
group.long 0x2E0++0x07
|
|
line.long 0x00 "ZCAL_INTERVAL_0,Configure ZQ calibration"
|
|
hexmask.long.word 0x00 10.--23. 1. " ZCAL_INTERVAL_HI ,Specifies the number of microseconds to wait issuance of ZCAL_MRW_CMD"
|
|
hexmask.long.word 0x00 0.--9. 1. " ZCAL_INTERVAL_LO ,ZCAL_INTERVAL_LO"
|
|
line.long 0x04 "ZCAL_WAIT_CNT_0,Configure ZQ calibration"
|
|
hexmask.long.word 0x04 0.--9. 1. " ZCAL_WAIT_CNT ,Number of EMC clocks to wait before issuing any commands"
|
|
wgroup.long 0x2E8++0x03
|
|
line.long 0x00 "ZCAL_MRW_CMD_0,Configure ZQ calibration"
|
|
bitfld.long 0x00 30.--31. " ZQ_MRW_DEV_SELECTN ,Active-low chip-select" "Both,Dev1,Dev0,"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ZQ_MRW_MA ,MRW MA field to be sent after ZCAL_INTERVAL"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ZQ_MRW_OP ,MRW OP field to be sent after ZCAL_INTERVAL"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "ZQ_CAL_0,Trigger a single ZQ calibration"
|
|
bitfld.long 0x00 30.--31. " ZQ_CAL_DEV_SELECTN ,Active-low chip-select" "Both,Dev1,Dev0,"
|
|
bitfld.long 0x00 4. " ZQ_CAL_LENGTH ,Indicate short or long ZQ calibration" "Short,Long"
|
|
bitfld.long 0x00 0. " ZQ_CAL_CMD ,Issues a ZQ calibration command" "0,1"
|
|
tree.end
|
|
tree "Pad control"
|
|
width 21.
|
|
group.long 0x2F0++0x2F
|
|
line.long 0x00 "XM2CMDPADCTRL_0,XM2CMD pad control register"
|
|
bitfld.long 0x00 28. " EMC2TMC_CFG_XM2RESET_E_PULLUP ,Select pullup mode on reset pad" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CFG_XM2CMD_CAL_SELECT ,Calibration select for CMD pads" "Normal,VREF"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EMC2TMC_CFG_XM2RESET_E_DDR3 ,Pad mode select" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EMC2PMACRO_CFG_XM2CMD_PHASESHIFT ,Shift cmd outputs by 1/2 cycle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EMC2TMC_CFG_XM2CMD_E_DDR3 ,Pad mode select" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EMC2TMC_CFG_XM2CMD_CLK_SEL ,Pad clk_sel" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMC2TMC_CFG_XM2CMD_E_PREEMP ,XM2CMD data pins preemp enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EMC2TMC_CFG_XM2CMD_E_BYPASS ,XM2CMD pins bypass outbound flop enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EMC2TMC_CFG_XM2CMD_E_PWRD ,X2CMD pins pad powerdown signal" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "XM2CMDPADCTRL2_0,XM2CMD pad control register 2"
|
|
bitfld.long 0x04 28.--31. " EMC2PMACRO_CFG_XM2CMD_DRVUP_SLWF ,EMC2PMACRO_CFG_XM2CMD_DRVUP_SLWF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. " EMC2PMACRO_CFG_XM2CMD_DRVDN_SLWR ,EMC2PMACRO_CFG_XM2CMD_DRVDN_SLWR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 19.--23. " EMC2PMACRO_CFG_XM2CMD_DRVUP ,EMC2PMACRO_CFG_XM2CMD_DRVUP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 14.--18. " EMC2PMACRO_CFG_XM2CMD_DRVDN ,EMC2PMACRO_CFG_XM2CMD_DRVDN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
line.long 0x08 "XM2DQSPADCTRL_0,XM2DQS pad control register"
|
|
bitfld.long 0x08 28.--31. " EMC2PMACRO_CFG_XM2DQS_DRVUP_SLWF ,EMC2PMACRO_CFG_XM2DQS_DRVUP_SLWF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 24.--27. " EMC2PMACRO_CFG_XM2DQS_DRVDN_SLWR ,EMC2PMACRO_CFG_XM2DQS_DRVDN_SLWR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 19.--23. " EMC2PMACRO_CFG_XM2DQS_DRVUP ,EMC2PMACRO_CFG_XM2DQS_DRVUP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 14.--18. " EMC2PMACRO_CFG_XM2DQS_DRVDN ,EMC2PMACRO_CFG_XM2DQS_DRVDN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 8.--12. " EMC2PMACRO_CFG_XM2DQS_DRVUP_TERM ,EMC2PMACRO_CFG_XM2DQS_DRVUP_TERM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 0.--4. " EMC2PMACRO_CFG_XM2DQS_DRVDN_TERM ,EMC2PMACRO_CFG_XM2DQS_DRVDN_TERM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
line.long 0x0C "XM2DQSPADCTRL2_0,XM2DQS pad control register 2"
|
|
bitfld.long 0x0C 24. " EMC2TMC_CFG_XM2DQS_QUSE_DLL_BYP ,XM2DQS quse dll byp" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20.--21. " EMC2TMC_CFG_XM2DQS_CONFIG ,IOBRICK rfu pinf" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " EMC2TMC_CFG_XM2DQS_RX_DQS_SEL ,IOBRICK rfu pins" "0,1,2,3"
|
|
bitfld.long 0x0C 16.--17. " EMC2TMC_CFG_XM2DQS_RX_DQ_SEL ,Select between legacy or LSSA mode" "Legacy,LSSA,..."
|
|
textline " "
|
|
bitfld.long 0x0C 15. " EMC2TMC_CFG_XM2DQS_E_SCHMT_DQ , XM2DQ DQ pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " EMC2TMC_CFG_XM2DQS_E_PWRD ,XMDQS pins pad powerdown signal" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " EMC2TMC_CFG_XM2DQS_E_SCHMT ,XM2DQS data pins schmidt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " EMC2TMC_CFG_XM2DQS_QUSE_DLI_EN ,QUSE DLI enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " EMC2TMC_CFG_XM2DQS_TXDQS_DLI_EN ,TXDQS DLI enable" "Enabled,Disabled"
|
|
bitfld.long 0x0C 10. " EMC2TMC_CFG_XM2DQS_TXDQ_DLI_EN ,TXDQ DLI enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " EMC2TMC_CFG_XM2DQS_RX_DLI_EN ,RX DLI enable" "Enabled,Disabled"
|
|
bitfld.long 0x0C 8. " EMC2TMC_CFG_XM2DQS_E_DDR3 ,Pad mode select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " EMC2TMC_CFG_XM2DQS_CLKSEL_DQS ,EMC2TMC_CFG_XM2DQS_CLKSEL_DQS" "0,1"
|
|
bitfld.long 0x0C 6. " EMC2TMC_CFG_XM2DQS_CLKSEL_DQ ,EMC2TMC_CFG_XM2DQS_CLKSEL_DQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " EMC2TMC_CFG_XM2DQS_E_VREF_DQ ,EMC2TMC_CFG_XM2DQS_E_VREF_DQ" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " EMC2TMC_CFG_XM2DQS_E_CTT_HIZ_DQS ,EMC2TMC_CFG_XM2DQS_E_CTT_HIZ_DQS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " EMC2TMC_CFG_XM2DQS_E_CTT_HIZ_DQ ,EMC2TMC_CFG_XM2DQS_E_CTT_HIZ_DQ" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " EMC2TMC_CFG_XM2DQS_E_PREEMP ,CFG_XM2DQ data pins preemp enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " EMC2TMC_CFG_XM2DQS_E_BYPASS ,CFG_XM2DQ data pins bypass outbound flop enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " EMC2TMC_CFG_XM2DQS_E_RX_FT_REC ,EMC2TMC_CFG_XM2DQS_E_RX_FT_REC" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x10 "XM2DQPADCTRL_0,CFG_XM2DQ pad control register"
|
|
bitfld.long 0x10 28.--31. " EMC2PMACRO_CFG_XM2DQ_DRVUP_SLWF ,EMC2PMACRO_CFG_XM2DQ_DRVUP_SLWF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 24.--27. " EMC2PMACRO_CFG_XM2DQ_DRVDN_SLWR ,EMC2PMACRO_CFG_XM2DQ_DRVDN_SLWR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x10 19.--23. " EMC2PMACRO_CFG_XM2DQ_DRVUP ,EMC2PMACRO_CFG_XM2DQ_DRVUP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 14.--18. " EMC2PMACRO_CFG_XM2DQ_DRVDN ,EMC2PMACRO_CFG_XM2DQ_DRVDN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x10 9.--13. " EMC2PMACRO_CFG_XM2DQ_DRVUP_TERM ,EMC2PMACRO_CFG_XM2DQ_DRVUP_TERM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 4.--8. " EMC2PMACRO_CFG_XM2DQ_DRVDN_TERM ,EMC2PMACRO_CFG_XM2DQ_DRVDN_TERM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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line.long 0x14 "XM2DQPADCTRL2_0,CFG_XM2DQ pad control register 2"
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bitfld.long 0x14 28.--30. " EMC2TMC_CFG_XM2DQ3_DLYIN_TRM ,Delay trim for byte 3" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 24.--26. " EMC2TMC_CFG_XM2DQ2_DLYIN_TRM ,Delay trim for byte 2" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x14 20.--22. " EMC2TMC_CFG_XM2DQ1_DLYIN_TRM ,Delay trim for byte 1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 16.--18. " EMC2TMC_CFG_XM2DQ0_DLYIN_TRM ,Delay trim for byte 0" "0,1,2,3,4,5,6,7"
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textline " "
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line.long 0x18 "XM2CLKPADCTRL_0,XM2CLK pad control register"
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bitfld.long 0x18 28.--31. " EMC2PMACRO_CFG_XM2CLK_DRVUP_SLWF ,EMC2PMACRO_CFG_XM2CLK_DRVUP_SLWF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 24.--27. " EMC2PMACRO_CFG_XM2CLK_DRVDN_SLWR ,EMC2PMACRO_CFG_XM2CLK_DRVDN_SLWR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x18 19.--23. " EMC2PMACRO_CFG_XM2CLK_DRVUP ,EMC2PMACRO_CFG_XM2CLK_DRVUP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 14.--18. " EMC2PMACRO_CFG_XM2CLK_DRVDN ,EMC2PMACRO_CFG_XM2CLK_DRVDN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x18 7. " EMC2TMC_CFG_XM2CLK_E_DDR3 ,Pad mode select" "Disabled,Enabled"
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bitfld.long 0x18 4. " EMC2TMC_CFG_XM2CLK_E_PWRD ,XM2CLK pins pad powerdown signal" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 3. " EMC2TMC_CFG_XM2CLK_E_CAL_BYPASS ,XM2CLK bypass drvdn/up calibration" "Disabled,Enabled"
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bitfld.long 0x18 2. " EMC2TMC_CFG_XM2CLK_E_PREEMP ,Preemp enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 0. " EMC2PMACRO_CFG_DYN_PULLS_ON_CLKDIS ,Enable pullup on clkp and pulldown on clkn when disabling clock" "Disabled,Enabled"
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textline " "
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line.long 0x1C "XM2COMPPADCTRL_0,MEM_COMP pad control register"
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bitfld.long 0x1C 28.--31. " EMC2TMC_CFG_XM2COMP_PU_VREF_SEL ,XM2COMP pu vref sel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 27. " EMC2TMC_CFG_XM2COMP_PU_VREF_SEL4 ,Bit 4 of the PU_VREF_SEL" "Disabled,Enabled"
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textline " "
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bitfld.long 0x1C 20.--24. " CFG_XM2COMP_DRVUP ,Used if AUTOCAL is disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 12.--16. " CFG_XM2COMP_DRVDN ,Used if AUTOCAL is disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x1C 11. " EMC2TMC_CFG_XM2COMP_E_TESTOUT ,EMC2TMC_CFG_XM2COMP_E_TESTOUT" "Disabled,Enabled"
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bitfld.long 0x1C 10. " CFG_XM2COMP_VREF_CAL_EN ,Enable generation of MCLK calibration" "Disabled,Enabled"
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textline " "
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bitfld.long 0x1C 9. " EMC2TMC_CFG_XM2COMP_E_PWRD ,XM2CLK pins pad powerdown signal" "Disabled,Enabled"
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bitfld.long 0x1C 8. " EMC2TMC_CFG_XM2COMP_E_DDR3 ,Pad mode select" "Disabled,Enabled"
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textline " "
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bitfld.long 0x1C 5.--7. " EMC2TMC_CFG_XM2COMP_BIAS_SEL ,BIAS select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 0.--4. " EMC2TMC_CFG_XM2COMP_VREF_SEL ,VREF select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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line.long 0x20 "XM2VTTGENPADCTRL_0,XM2 MISC/VTTGEN pad control register"
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bitfld.long 0x20 24.--26. " EMC2TMC_CFG_XM2VTTGEN_DRVUP ,EMC2TMC_CFG_XM2VTTGEN_DRVUP" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 16.--18. " EMC2TMC_CFG_XM2VTTGEN_DRVDN ,EMC2TMC_CFG_XM2VTTGEN_DRVDN" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x20 2. " EMC2TMC_CFG_XM2VTTGEN_E_DDR3 ,Select pad mode" "0,1"
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bitfld.long 0x20 0. " EMC2TMC_CFG_XM2VTTGEN_SHORT ,EMC2TMC_CFG_XM2VTTGEN_SHORT" "0,1"
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textline " "
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line.long 0x24 "XM2VTTGENPADCTRL2_0,XM2 MISC/VTTGEN pad control register 2"
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bitfld.long 0x24 30.--31. " EMC2TMC_CFG_XM2VTTGEN_MEM2_E_TEST_BIAS ,BIAS mode enable (DPD - MEM2 group)" "Disabled,Enabled,,"
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bitfld.long 0x24 28.--29. " EMC2TMC_CFG_XM2VTTGEN_MEM_E_TEST_BIAS ,BIAS mode enable (DP0 - MEM group)" "Disabled,Enabled,,"
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textline " "
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bitfld.long 0x24 0.--5. " EMC2TMC_CFG_XM2VTTGEN_E_NO_VTTGEN ,Disable optional VTTGEN pads" "ADDR0,ADDR1,ADDR2,DATA1,DATA2,DATA3,..."
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textline " "
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line.long 0x28 "XM2VTTGENPADCTRL3_0,XM2VTTGEN pad control 3"
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bitfld.long 0x28 24. " EMC2TMC_CFG_XM2VTTGEN_VAUXP_BACKUP_BYTE ,XM2VTTGEN vaux backup byte" "0,1"
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bitfld.long 0x28 20.--22. " EMC2TMC_CFG_XM2VTTGEN_VAUXP_LEVEL_BYTE ,XM2VTTGEN vauxp level byte" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x28 19. " EMC2TMC_CFG_XM2VTTGEN_CLAMP_BACKUP_BYTE ,XM2VTTGEN clamp backup byte" "0,1"
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bitfld.long 0x28 16.--18. " EMC2TMC_CFG_XM2VTTGEN_VCLAMP_LEVEL_BYTE ,XM2VTTGEN vclamp level byte" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x28 15. " EMC2TMC_CFG_XM2VTTGEN_VAUXP_BACKUP_CMD ,XM2VTTGEN vauxp backup cmd" "0,1"
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bitfld.long 0x28 12.--14. " EMC2TMC_CFG_XM2VTTGEN_VAUXP_LEVEL_CMD ,XM2VTTGEN vauxp level cmd" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x28 11. " EMC2TMC_CFG_XM2VTTGEN_VCLAMP_BACKUP_CMD ,XM2VTTGEN vclamp backup cmd" "0,1"
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bitfld.long 0x28 8.--10. " EMC2TMC_CFG_XM2VTTGEN_VCLAMP_LEVEL_CMD ,XM2VTTGEN vclamp level cmd" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x28 7. " EMC2TMC_CFG_XM2VTTGEN_VAUXP_BACKUP_CLK ,XM2VTTGEN vauxp backup clk" "0,1"
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bitfld.long 0x28 4.--6. " EMC2TMC_CFG_XM2VTTGEN_VAUXP_LEVEL_CLK ,XM2VTTGEN vauxp level clk" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x28 3. " EMC2TMC_CFG_XM2VTTGEN_VCLAMP_BACKUP_CLK ,XM2VTTGEN vclamp backup clk" "0,1"
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bitfld.long 0x28 0.--2. " EMC2TMC_CFG_XM2VTTGEN_VCLAMP_LEVEL_CLK ,XM2VTTGEN clamp level clk" "0,1,2,3,4,5,6,7"
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textline " "
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line.long 0x2C "EMC_EMCPADEN_0,EMC pad enable register"
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bitfld.long 0x2C 1. " EMC2PMACRO_CFG_PAD_INPUT_EN ,Inputs enable for EMC pads" "Disabled,Enabled"
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bitfld.long 0x2C 0. " EMC2PMACRO_CFG_PAD_OUTPUT_EN ,Outputs enable for EMC pads" "Disabled,Enabled"
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textline " "
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group.long 0x320++0x03
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line.long 0x00 "XM2DQSPADCTRL4_0,XM2 MISC/VTTGEN pad control register 4"
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bitfld.long 0x00 18.--22. " EMC2TMC_CFG_XM2DQS_BYTE3_VREF_DQ ,XM2DQS byte 3 vref dq" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 12.--16. " EMC2TMC_CFG_XM2DQS_BYTE2_VREF_DQ ,XM2DQS byte 2 vref dq" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 6.--10. " EMC2TMC_CFG_XM2DQS_BYTE1_VREF_DQ ,XM2DQS byte 1 vref dq" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. " EMC2TMC_CFG_XM2DQS_BYTE0_VREF_DQ ,XM2DQS byte 0 vref dq" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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tree.end
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width 15.
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group.long 0x324++0x03 "Scratch Register"
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line.long 0x00 "EMC_SCRATCH_0,Scratch register for general use"
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tree "Digital DLL Configuration 2"
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width 19.
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group.long 0x328++0x1F
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line.long 0x0 "DLL_XFORM_DQS0_0,DQS0 configuration"
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hexmask.long.word 0x00 12.--22. 1. " XFORM_DQS0_OFFS ,Offset"
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bitfld.long 0x00 0.--4. " XFORM_DQS0_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x4 "DLL_XFORM_DQS1_0,DQS1 configuration"
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hexmask.long.word 0x00 12.--22. 1. " XFORM_DQS1_OFFS ,Offset"
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bitfld.long 0x00 0.--4. " XFORM_DQS1_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x8 "DLL_XFORM_DQS2_0,DQS2 configuration"
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hexmask.long.word 0x00 12.--22. 1. " XFORM_DQS2_OFFS ,Offset"
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bitfld.long 0x00 0.--4. " XFORM_DQS2_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0xC "DLL_XFORM_DQS3_0,DQS3 configuration"
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hexmask.long.word 0x00 12.--22. 1. " XFORM_DQS3_OFFS ,Offset"
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bitfld.long 0x00 0.--4. " XFORM_DQS3_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x10 "DLL_XFORM_DQS4_0,DQS4 configuration"
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hexmask.long.word 0x00 12.--22. 1. " XFORM_DQS4_OFFS ,Offset"
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bitfld.long 0x00 0.--4. " XFORM_DQS4_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x14 "DLL_XFORM_DQS5_0,DQS5 configuration"
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hexmask.long.word 0x00 12.--22. 1. " XFORM_DQS5_OFFS ,Offset"
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bitfld.long 0x00 0.--4. " XFORM_DQS5_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x18 "DLL_XFORM_DQS6_0,DQS6 configuration"
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hexmask.long.word 0x00 12.--22. 1. " XFORM_DQS6_OFFS ,Offset"
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bitfld.long 0x00 0.--4. " XFORM_DQS6_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x1C "DLL_XFORM_DQS7_0,DQS7 configuration"
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hexmask.long.word 0x00 12.--22. 1. " XFORM_DQS7_OFFS ,Offset"
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bitfld.long 0x00 0.--4. " XFORM_DQS7_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x348++0x1F
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|
line.long 0x0 "DLL_XFORM_QUSE0_0,QUSE0 configuration"
|
|
hexmask.long.word 0x00 12.--22. 1. " XFORM_QUSE0_OFFS ,Offset"
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bitfld.long 0x00 0.--4. " XFORM_QUSE0_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x4 "DLL_XFORM_QUSE1_0,QUSE1 configuration"
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hexmask.long.word 0x00 12.--22. 1. " XFORM_QUSE1_OFFS ,Offset"
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bitfld.long 0x00 0.--4. " XFORM_QUSE1_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x8 "DLL_XFORM_QUSE2_0,QUSE2 configuration"
|
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hexmask.long.word 0x00 12.--22. 1. " XFORM_QUSE2_OFFS ,Offset"
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bitfld.long 0x00 0.--4. " XFORM_QUSE2_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0xC "DLL_XFORM_QUSE3_0,QUSE3 configuration"
|
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hexmask.long.word 0x00 12.--22. 1. " XFORM_QUSE3_OFFS ,Offset"
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|
bitfld.long 0x00 0.--4. " XFORM_QUSE3_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x10 "DLL_XFORM_QUSE4_0,QUSE4 configuration"
|
|
hexmask.long.word 0x00 12.--22. 1. " XFORM_QUSE4_OFFS ,Offset"
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|
bitfld.long 0x00 0.--4. " XFORM_QUSE4_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x14 "DLL_XFORM_QUSE5_0,QUSE5 configuration"
|
|
hexmask.long.word 0x00 12.--22. 1. " XFORM_QUSE5_OFFS ,Offset"
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bitfld.long 0x00 0.--4. " XFORM_QUSE5_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x18 "DLL_XFORM_QUSE6_0,QUSE6 configuration"
|
|
hexmask.long.word 0x00 12.--22. 1. " XFORM_QUSE6_OFFS ,Offset"
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|
bitfld.long 0x00 0.--4. " XFORM_QUSE6_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
line.long 0x1C "DLL_XFORM_QUSE7_0,QUSE7 configuration"
|
|
hexmask.long.word 0x00 12.--22. 1. " XFORM_QUSE7_OFFS ,Offset"
|
|
bitfld.long 0x00 0.--4. " XFORM_QUSE7_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long 0x368++0x0F
|
|
line.long 0x0 "DLL_XFORM_DQ0_0,TXDQ0 configuration"
|
|
hexmask.long.word 0x00 12.--22. 1. " XFORM_TXDQ0_OFFS ,Offset"
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|
bitfld.long 0x00 0.--4. " XFORM_TXDQ0_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x4 "DLL_XFORM_DQ1_0,TXDQ1 configuration"
|
|
hexmask.long.word 0x00 12.--22. 1. " XFORM_TXDQ1_OFFS ,Offset"
|
|
bitfld.long 0x00 0.--4. " XFORM_TXDQ1_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x8 "DLL_XFORM_DQ2_0,TXDQ2 configuration"
|
|
hexmask.long.word 0x00 12.--22. 1. " XFORM_TXDQ2_OFFS ,Offset"
|
|
bitfld.long 0x00 0.--4. " XFORM_TXDQ2_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
line.long 0xC "DLL_XFORM_DQ3_0,TXDQ3 configuration"
|
|
hexmask.long.word 0x00 12.--22. 1. " XFORM_TXDQ3_OFFS ,Offset"
|
|
bitfld.long 0x00 0.--4. " XFORM_TXDQ3_MULT ,Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x378++0x1F
|
|
line.long 0x0 "DLI_RX_TRIM0_0,RX_TRIM0 configuration"
|
|
hexmask.long.word 0x00 15.--24. 1. " QUSE_CURRENT_TRIM_VAL_BYTE_0 ,QUSE current trim value"
|
|
hexmask.long.word 0x00 0.--9. 1. " DQS_CURRENT_TRIM_VAL_BYTE_0 ,DQS current trim value"
|
|
line.long 0x4 "DLI_RX_TRIM1_0,RX_TRIM1 configuration"
|
|
hexmask.long.word 0x00 15.--24. 1. " QUSE_CURRENT_TRIM_VAL_BYTE_1 ,QUSE current trim value"
|
|
hexmask.long.word 0x00 0.--9. 1. " DQS_CURRENT_TRIM_VAL_BYTE_1 ,DQS current trim value"
|
|
line.long 0x8 "DLI_RX_TRIM2_0,RX_TRIM2 configuration"
|
|
hexmask.long.word 0x00 15.--24. 1. " QUSE_CURRENT_TRIM_VAL_BYTE_2 ,QUSE current trim value"
|
|
hexmask.long.word 0x00 0.--9. 1. " DQS_CURRENT_TRIM_VAL_BYTE_2 ,DQS current trim value"
|
|
line.long 0xC "DLI_RX_TRIM3_0,RX_TRIM3 configuration"
|
|
hexmask.long.word 0x00 15.--24. 1. " QUSE_CURRENT_TRIM_VAL_BYTE_3 ,QUSE current trim value"
|
|
hexmask.long.word 0x00 0.--9. 1. " DQS_CURRENT_TRIM_VAL_BYTE_3 ,DQS current trim value"
|
|
line.long 0x10 "DLI_RX_TRIM4_0,RX_TRIM4 configuration"
|
|
hexmask.long.word 0x00 15.--24. 1. " QUSE_CURRENT_TRIM_VAL_BYTE_4 ,QUSE current trim value"
|
|
hexmask.long.word 0x00 0.--9. 1. " DQS_CURRENT_TRIM_VAL_BYTE_4 ,DQS current trim value"
|
|
line.long 0x14 "DLI_RX_TRIM5_0,RX_TRIM5 configuration"
|
|
hexmask.long.word 0x00 15.--24. 1. " QUSE_CURRENT_TRIM_VAL_BYTE_5 ,QUSE current trim value"
|
|
hexmask.long.word 0x00 0.--9. 1. " DQS_CURRENT_TRIM_VAL_BYTE_5 ,DQS current trim value"
|
|
line.long 0x18 "DLI_RX_TRIM6_0,RX_TRIM6 configuration"
|
|
hexmask.long.word 0x00 15.--24. 1. " QUSE_CURRENT_TRIM_VAL_BYTE_6 ,QUSE current trim value"
|
|
hexmask.long.word 0x00 0.--9. 1. " DQS_CURRENT_TRIM_VAL_BYTE_6 ,DQS current trim value"
|
|
line.long 0x1C "DLI_RX_TRIM7_0,RX_TRIM7 configuration"
|
|
hexmask.long.word 0x00 15.--24. 1. " QUSE_CURRENT_TRIM_VAL_BYTE_7 ,QUSE current trim value"
|
|
hexmask.long.word 0x00 0.--9. 1. " DQS_CURRENT_TRIM_VAL_BYTE_7 ,DQS current trim value"
|
|
rgroup.long 0x398++0x0F
|
|
line.long 0x0 "DLI_TX_TRIM0_0,TX_TRIM0 configuration"
|
|
hexmask.long.word 0x00 0.--9. 1. " TXDQ_CURRENT_TRIM_VAL_BYTE_0 ,TXDQ current trim value"
|
|
line.long 0x4 "DLI_TX_TRIM1_0,TX_TRIM1 configuration"
|
|
hexmask.long.word 0x00 0.--9. 1. " TXDQ_CURRENT_TRIM_VAL_BYTE_1 ,TXDQ current trim value"
|
|
line.long 0x8 "DLI_TX_TRIM2_0,TX_TRIM2 configuration"
|
|
hexmask.long.word 0x00 0.--9. 1. " TXDQ_CURRENT_TRIM_VAL_BYTE_2 ,TXDQ current trim value"
|
|
line.long 0xC "DLI_TX_TRIM3_0,TX_TRIM3 configuration"
|
|
hexmask.long.word 0x00 0.--9. 1. " TXDQ_CURRENT_TRIM_VAL_BYTE_3 ,TXDQ current trim value"
|
|
group.long 0x3A8++0x1F
|
|
line.long 0x0 "DLI_TRIM_TXDQS0_0,Set DLI TRIM"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EMC2PMACRO_CFG_TXDQS0_DLI ,Trimmer control"
|
|
line.long 0x4 "DLI_TRIM_TXDQS1_0,Set DLI TRIM"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EMC2PMACRO_CFG_TXDQS1_DLI ,Trimmer control"
|
|
line.long 0x8 "DLI_TRIM_TXDQS2_0,Set DLI TRIM"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EMC2PMACRO_CFG_TXDQS2_DLI ,Trimmer control"
|
|
line.long 0xC "DLI_TRIM_TXDQS3_0,Set DLI TRIM"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EMC2PMACRO_CFG_TXDQS3_DLI ,Trimmer control"
|
|
line.long 0x10 "DLI_TRIM_TXDQS4_0,Set DLI TRIM"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EMC2PMACRO_CFG_TXDQS4_DLI ,Trimmer control"
|
|
line.long 0x14 "DLI_TRIM_TXDQS5_0,Set DLI TRIM"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EMC2PMACRO_CFG_TXDQS5_DLI ,Trimmer control"
|
|
line.long 0x18 "DLI_TRIM_TXDQS6_0,Set DLI TRIM"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EMC2PMACRO_CFG_TXDQS6_DLI ,Trimmer control"
|
|
line.long 0x1C "DLI_TRIM_TXDQS7_0,Set DLI TRIM"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EMC2PMACRO_CFG_TXDQS7_DLI ,Trimmer control"
|
|
tree.end
|
|
width 35.
|
|
rgroup.long 0x3C8++0x0F
|
|
line.long 0x00 "STALL_THEN_EXE_BEFORE_CLKCHANGE_0,Subsequent register access stall control"
|
|
bitfld.long 0x00 0. " STALL_THEN_EXE_BEFORE_CLKCHANGE ,Stall subsequent register access" "Disabled,Enabled"
|
|
line.long 0x04 "STALL_THEN_EXE_AFTER_CLKCHANGE_0,Subsequent register access stall control"
|
|
bitfld.long 0x04 0. " UNSTALL_RW_AFTER_CLKCHANGE ,Stall subsequent register access" "Disabled,Enabled"
|
|
line.long 0x08 "UNSTALL_RW_AFTER_CLKCHANGE_0,Subsequent register access stall control"
|
|
bitfld.long 0x08 0. " STALL_THEN_EXE_BEFORE_CLKCHANGE ,Unstall memory read/write after clock change" "Disabled,Enabled"
|
|
line.long 0x0C "AUTO_CAL_CLK_STATUS_0,EMC pad calibration status"
|
|
hexmask.long.byte 0x0C 24.--28. 1. " AUTO_CAL_CLK_PULLDOWN_ADJ ,Pulldown code sent to pads for MCLK pad"
|
|
hexmask.long.byte 0x0C 16.--20. 1. " AUTO_CAL_CLK_PULLUP_ADJ ,Pullup code sent to pads for MCLK pad"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 8.--12. 1. " AUTO_CAL_CLK_PULLDOWN ,Pulldown code generated by auto-calibration for MCLK pad"
|
|
hexmask.long.byte 0x0C 0.--4. 1. " AUTO_CAL_CLK_PULLUP ,Pullup code generated by auto-calibration for MCLK pad"
|
|
width 26.
|
|
group.long 0x3D8++0x0F
|
|
line.long 0x00 "SEL_DPD_CTRL_0,Configures functional SEL_DPD modes"
|
|
bitfld.long 0x00 16.--18. " SEL_DPD_DLY ,Number of cycles to wait before asserting SEL_DPD" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8. " DATA_SEL_DPD_EN ,Allow SEL_DPD assertion for data pads" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ODT_SEL_DPD_EN ,Tie SEL_DPD for odt pads to ENABLE_ODT_DURING_WRITE" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RESET_SEL_DPD_EN ,Assert SEL_DPD for reset pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CA_SEL_DPD_EN ,Allow SEL_DPD assertion for discrete command/address pads" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CLK_SEL_DPD_EN ,Allow SEL_DPD assertion for discrete clock pad" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "PRE_REFRESH_REQ_CNT_0,Pre refresh request count"
|
|
hexmask.long.word 0x04 0.--15. 1. " PRE_REF_REQ_CNT ,Pre-refresh request count"
|
|
line.long 0x08 "DYN_SELF_REF_CONTROL_0,Threshold for dynamic self-refresh entry"
|
|
bitfld.long 0x08 31. " DSR_PER_DEVICE ,Controls whether self-refresh is done on a per-device basis" "Disabled,Enabled"
|
|
hexmask.long.word 0x08 0.--15. 1. " DSR_THRESHOLD ,Number of idle cycles to wait before allowing dynamic self-refresh entry"
|
|
line.long 0x0C "TXSRDLL_0,DRAM timing parameter for TXSRDLL"
|
|
hexmask.long.word 0x0C 0.--11. 1. " TXSRDLL ,Cyckes between self-refresh exit & first DRAM command requiring a locked DLL"
|
|
group.long 0x3E8++0x07
|
|
line.long 0x00 "CCFIFO_ADDR_0,CCFIFO address offset"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCFIFO_ADDR ,Clock change FIFO address register"
|
|
line.long 0x04 "CCFIFO_DATA_0,CCFIFO Data"
|
|
rgroup.long 0x3F0++0x03
|
|
line.long 0x00 "CCFIFO_STATUS_0,CCFIFO Status"
|
|
bitfld.long 0x00 0.--5. " CCFIFO_COUNT ,CCFIFO count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x3F4++0x07
|
|
line.long 0x00 "CDB_CNTL_1_0,CDB Control Register"
|
|
bitfld.long 0x00 27.--29. " EMC2PMACRO_SEL_PI_TAP9 ,CLKBUF 3 controls channel 1 ddr/2T pins" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " EMC2PMACRO_SEL_PI_TAP8 ,MCLK_B" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " EMC2PMACRO_SEL_PI_TAP7 ,MCLK" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. " EMC2PMACRO_SEL_PI_TAP6 ,CLKBUF 2 controls channel 0 sdr pins" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " EMC2PMACRO_SEL_PI_TAP5 ,CLKBUF 1 controls channel 0 ddr/2T pins" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " EMC2PMACRO_SEL_PI_TAP4 ,CLKBUF 0 controls channel 0 ddr/2T pins" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " EMC2PMACRO_SEL_PI_TAP3 ,Data byte 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " EMC2PMACRO_SEL_PI_TAP2 ,Data byte 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " EMC2PMACRO_SEL_PI_TAP1 ,Data byte 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " EMC2PMACRO_SEL_PI_TAP0 ,Data byte 0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "CDB_CNTL_2_0, CDB Control Register"
|
|
bitfld.long 0x04 31. " EMC2PMACRO_CLKNIGATE_TAP15 ,Data brick 7" "0,1"
|
|
bitfld.long 0x04 30. " EMC2PMACRO_CLKNIGATE_TAP14 ,Data brick 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 29. " EMC2PMACRO_CLKNIGATE_TAP13 ,Data brick 6" "0,1"
|
|
bitfld.long 0x04 28. " EMC2PMACRO_CLKNIGATE_TAP12 ,Data brick 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 27. " EMC2PMACRO_CLKNIGATE_TAP11 ,CLKBUF 5 controls channel 1" "0,1"
|
|
bitfld.long 0x04 26. " EMC2PMACRO_CLKNIGATE_TAP10 ,CLKBUF 4 controls channel 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 25. " EMC2PMACRO_CLKNIGATE_TAP9 ,CLKBUF 3 controls channel 1" "0,1"
|
|
bitfld.long 0x04 24. " EMC2PMACRO_CLKNIGATE_TAP8 ,MCLK_B" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 23. " EMC2PMACRO_CLKNIGATE_TAP7 ,MCLK" "0,1"
|
|
bitfld.long 0x04 22. " EMC2PMACRO_CLKNIGATE_TAP6 ,CLKBUF 2 controls channel 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 21. " EMC2PMACRO_CLKNIGATE_TAP5 ,CLKBUF 1 controls channel 0" "0,1"
|
|
bitfld.long 0x04 20. " EMC2PMACRO_CLKNIGATE_TAP4 ,CLKBUF 0 controls channel 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 19. " EMC2PMACRO_CLKNIGATE_TAP3 ,Data byte 3" "0,1"
|
|
bitfld.long 0x04 18. " EMC2PMACRO_CLKNIGATE_TAP2 ,Data byte 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " EMC2PMACRO_CLKNIGATE_TAP1 ,Data byte 2" "0,1"
|
|
bitfld.long 0x04 16. " EMC2PMACRO_CLKNIGATE_TAP0 ,Data byte 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 15. " EMC2PMACRO_CLKPIGATE_TAP15 ,Data brick 7" "0,1"
|
|
bitfld.long 0x04 14. " EMC2PMACRO_CLKPIGATE_TAP14 ,Data brick 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 13. " EMC2PMACRO_CLKPIGATE_TAP13 ,Data brick 6" "0,1"
|
|
bitfld.long 0x04 12. " EMC2PMACRO_CLKPIGATE_TAP12 ,Data brick 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EMC2PMACRO_CLKPIGATE_TAP11 ,CLKBUF 5 control channel 1" "0,1"
|
|
bitfld.long 0x04 10. " EMC2PMACRO_CLKPIGATE_TAP10 ,CLKBUF 4 control channel 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EMC2PMACRO_CLKPIGATE_TAP9 ,CLKBUF 3 control channel 1" "0,1"
|
|
bitfld.long 0x04 8. " EMC2PMACRO_CLKPIGATE_TAP8 ,MCLK_B" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 7. " EMC2PMACRO_CLKPIGATE_TAP7 ,MCLK" "0,1"
|
|
bitfld.long 0x04 6. " EMC2PMACRO_CLKPIGATE_TAP6 ,CLKBUF 2 controls channel 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 5. " EMC2PMACRO_CLKPIGATE_TAP5 ,CLKBUF 1 controls channel 0" "0,1"
|
|
bitfld.long 0x04 4. " EMC2PMACRO_CLKPIGATE_TAP4 ,CLKBUF 0 controls channel 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EMC2PMACRO_CLKPIGATE_TAP3 ,Data byte 3" "0,1"
|
|
bitfld.long 0x04 2. " EMC2PMACRO_CLKPIGATE_TAP2 ,Data byte 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 1. " EMC2PMACRO_CLKPIGATE_TAP1 ,Data byte 2" "0,1"
|
|
bitfld.long 0x04 0. " EMC2PMACRO_CLKPIGATE_TAP0 ,Data byte 0" "0,1"
|
|
group.long 0x3FC++0x0F
|
|
line.long 0x00 "XM2CLKPADCTRL2_0,XM2CLK Pad Control Register"
|
|
bitfld.long 0x00 31. " EMC2PMACRO_CFG_FLIP_CKB_SENSE ,Flip the m2clk_b pad sense" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " EMC2PMACRO_CFG_PI_CLKB_TRIM ,Pi_clk to control the 32-tap timmer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EMC2MACRO_CFG_FLIP_CK_SENSE ,Flip the m2clk pad sense" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " EMC2PMACRO_CFG_PI_CLK_TRIM ,Pi_clk_trim to control the 32-tap trimmer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " EMC2TMC_CFG_XM2CLKB_DLY_TRM_P ,XM2CLKB dly trm p" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " EMC2TMC_CFG_XM2CLK_DLY_TRM_P ,XM2CLK dly trym p" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SWIZZLE_RANK0_BYTE_CFG_0 ,Swizzle rank 0 byte cfg 0"
|
|
bitfld.long 0x04 12.--13. " SWZ_RANK0_BYTE3_SEL , SWZ rank0 byte3 sel" "0,1,2,3"
|
|
bitfld.long 0x04 8.--9. " SWZ_RANK0_BYTE2_SEL ,SWZ rank0 byte3 sel" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " SWZ_RANK0_BYTE1_SEL ,SWZ rank0 byte1 sel" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. " SWZ_RANK0_BYTE0_SEL ,SWZ rank0 byte0 sel" "0,1,2,3"
|
|
line.long 0x08 "SWIZZLE_RANK0_BYTE0_0,Swizzle Rank0 Byte0_0"
|
|
bitfld.long 0x08 28.--30. " SWZ_RANK0_BYTE0_BIT7_SEL ,SWZ rank0 byte0 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 24.--26. " SWZ_RANK0_BYTE0_BIT6_SEL ,SWZ rank0 byte0 bit6 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 20.--22. " SWZ_RANK0_BYTE0_BIT5_SEL ,SWZ rank0 byte0 bit5 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 16.--18. " SWZ_RANK0_BYTE0_BIT4_SEL ,SWZ rank0 byte0 bit4 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " SWZ_RANK0_BYTE0_BIT3_SEL ,SWZ rank0 byte0 bit3 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 8.--10. " SWZ_RANK0_BYTE0_BIT2_SEL ,SWZ rank0 byte0 bit2 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " SWZ_RANK0_BYTE0_BIT1_SEL ,SWZ rank0 byte0 bit1 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 0.--2. " SWZ_RANK0_BYTE0_BIT0_SEL ,SWZ rank0 byte0 bit0 sel" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "SWIZZLE_RANK0_BYTE1_0,Swizzle Rank0 Byte1_0"
|
|
bitfld.long 0x0C 28.--30. " SWZ_RANK0_BYTE1_BIT7_SEL ,SWZ rank0 byte0 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 24.--26. " SWZ_RANK0_BYTE1_BIT6_SEL ,SWZ rank0 byte0 bit6 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 20.--22. " SWZ_RANK0_BYTE1_BIT5_SEL ,SWZ rank0 byte0 bit5 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 16.--18. " SWZ_RANK0_BYTE1_BIT4_SEL ,SWZ rank0 byte0 bit4 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 12.--14. " SWZ_RANK0_BYTE1_BIT3_SEL ,SWZ rank0 byte0 bit3 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 8.--10. " SWZ_RANK0_BYTE1_BIT2_SEL ,SWZ rank0 byte0 bit2 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 4.--6. " SWZ_RANK0_BYTE1_BIT1_SEL ,SWZ rank0 byte0 bit1 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 0.--2. " SWZ_RANK0_BYTE1_BIT0_SEL ,SWZ rank0 byte0 bit0 sel" "0,1,2,3,4,5,6,7"
|
|
group.long 0x40C++0x0B
|
|
line.long 0x00 "SWIZZLE_RANK0_BYTE2_0,Swizzle Rank0 Byte2_0"
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|
bitfld.long 0x00 28.--30. " SWZ_RANK0_BYTE2_BIT7_SEL ,SWZ rank0 byte0 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " SWZ_RANK0_BYTE2_BIT6_SEL ,SWZ rank0 byte0 bit6 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " SWZ_RANK0_BYTE2_BIT5_SEL ,SWZ rank0 byte0 bit5 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " SWZ_RANK0_BYTE2_BIT4_SEL ,SWZ rank0 byte0 bit4 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
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|
bitfld.long 0x00 12.--14. " SWZ_RANK0_BYTE2_BIT3_SEL ,SWZ rank0 byte0 bit3 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " SWZ_RANK0_BYTE2_BIT2_SEL ,SWZ rank0 byte0 bit2 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
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|
bitfld.long 0x00 4.--6. " SWZ_RANK0_BYTE2_BIT1_SEL ,SWZ rank0 byte0 bit1 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " SWZ_RANK0_BYTE2_BIT0_SEL ,SWZ rank0 byte0 bit0 sel" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "SWIZZLE_RANK0_BYTE3_0,Swizzle Rank0 Byte0_0"
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|
bitfld.long 0x04 28.--30. " SWZ_RANK0_BYTE3_BIT7_SEL ,SWZ rank0 byte0 bit7 sel" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x04 24.--26. " SWZ_RANK0_BYTE3_BIT6_SEL ,SWZ rank0 byte0 bit6 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
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|
bitfld.long 0x04 20.--22. " SWZ_RANK0_BYTE3_BIT5_SEL ,SWZ rank0 byte0 bit5 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--18. " SWZ_RANK0_BYTE3_BIT4_SEL ,SWZ rank0 byte0 bit4 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " SWZ_RANK0_BYTE3_BIT3_SEL ,SWZ rank0 byte0 bit3 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8.--10. " SWZ_RANK0_BYTE3_BIT2_SEL ,SWZ rank0 byte0 bit2 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " SWZ_RANK0_BYTE3_BIT1_SEL ,SWZ rank0 byte0 bit1 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " SWZ_RANK0_BYTE3_BIT0_SEL ,SWZ rank0 byte0 bit0 sel" "0,1,2,3,4,5,6,7"
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|
line.long 0x08 "SWIZZLE_RANK1_BYTE_CFG_0,Swizzle Rank1 Byte CFG 0"
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|
bitfld.long 0x08 12.--13. " SWZ_RANK1_BYTE3_SEL ,SWZ rank1 byte3 sel" "0,1,2,3"
|
|
bitfld.long 0x08 8.--9. " SWZ_RANK1_BYTE2_SEL ,SWZ rank1 byte2 sel" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " SWZ_RANK1_BYTE1_SEL ,SWZ rank1 byte1 sel" "0,1,2,3"
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|
bitfld.long 0x08 0.--1. " SWZ_RANK1_BYTE0_SEL ,SWZ rank1 byte0 sel" "0,1,2,3"
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|
group.long 0x418++0x03
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|
line.long 0x00 "SWIZZLE_RANK1_BYTE0_0,Swizzle Rank1 Byte0 0"
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|
bitfld.long 0x00 28.--30. " SWZ_RANK1_BYTE0_BIT7_SEL ,SWZ rank1 byte0 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " SWZ_RANK1_BYTE0_BIT7_SEL ,SWZ rank1 byte0 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " SWZ_RANK1_BYTE0_BIT7_SEL ,SWZ rank1 byte0 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " SWZ_RANK1_BYTE0_BIT7_SEL ,SWZ rank1 byte0 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " SWZ_RANK1_BYTE0_BIT7_SEL ,SWZ rank1 byte0 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " SWZ_RANK1_BYTE0_BIT7_SEL ,SWZ rank1 byte0 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " SWZ_RANK1_BYTE0_BIT7_SEL ,SWZ rank1 byte0 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " SWZ_RANK1_BYTE0_BIT7_SEL ,SWZ rank1 byte0 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "SWIZZLE_RANK1_BYTE1_0,Swizzle Rank1 Byte1 0"
|
|
bitfld.long 0x00 28.--30. " SWZ_RANK1_BYTE1_BIT7_SEL ,SWZ rank1 byte1 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " SWZ_RANK1_BYTE1_BIT7_SEL ,SWZ rank1 byte1 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " SWZ_RANK1_BYTE1_BIT7_SEL ,SWZ rank1 byte1 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " SWZ_RANK1_BYTE1_BIT7_SEL ,SWZ rank1 byte1 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " SWZ_RANK1_BYTE1_BIT7_SEL ,SWZ rank1 byte1 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " SWZ_RANK1_BYTE1_BIT7_SEL ,SWZ rank1 byte1 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " SWZ_RANK1_BYTE1_BIT7_SEL ,SWZ rank1 byte1 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " SWZ_RANK1_BYTE1_BIT7_SEL ,SWZ rank1 byte1 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "SWIZZLE_RANK1_BYTE2_0,Swizzle Rank1 Byte2 0"
|
|
bitfld.long 0x00 28.--30. " SWZ_RANK1_BYTE2_BIT7_SEL ,SWZ rank1 byte2 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " SWZ_RANK1_BYTE2_BIT7_SEL ,SWZ rank1 byte2 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " SWZ_RANK1_BYTE2_BIT7_SEL ,SWZ rank1 byte2 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " SWZ_RANK1_BYTE2_BIT7_SEL ,SWZ rank1 byte2 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " SWZ_RANK1_BYTE2_BIT7_SEL ,SWZ rank1 byte2 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " SWZ_RANK1_BYTE2_BIT7_SEL ,SWZ rank1 byte2 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " SWZ_RANK1_BYTE2_BIT7_SEL ,SWZ rank1 byte2 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " SWZ_RANK1_BYTE2_BIT7_SEL ,SWZ rank1 byte2 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "SWIZZLE_RANK1_BYTE3_0,Swizzle Rank1 Byte3 0"
|
|
bitfld.long 0x00 28.--30. " SWZ_RANK1_BYTE3_BIT7_SEL ,SWZ rank1 byte3 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " SWZ_RANK1_BYTE3_BIT7_SEL ,SWZ rank1 byte3 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " SWZ_RANK1_BYTE3_BIT7_SEL ,SWZ rank1 byte3 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " SWZ_RANK1_BYTE3_BIT7_SEL ,SWZ rank1 byte3 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " SWZ_RANK1_BYTE3_BIT7_SEL ,SWZ rank1 byte3 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " SWZ_RANK1_BYTE3_BIT7_SEL ,SWZ rank1 byte3 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " SWZ_RANK1_BYTE3_BIT7_SEL ,SWZ rank1 byte3 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " SWZ_RANK1_BYTE3_BIT7_SEL ,SWZ rank1 byte3 bit7 sel" "0,1,2,3,4,5,6,7"
|
|
tree "EMC Training"
|
|
width 16.
|
|
group.long 0x428++0x13
|
|
line.long 0x00 "START_0,Procedure for LPDDR3 CA Training"
|
|
bitfld.long 0x00 31. " CA_TRAIN_START ,Start training" "Not started,Started"
|
|
line.long 0x04 "BUSY_0,Training busy 0"
|
|
bitfld.long 0x04 0. " CA_TRAIN_BUSY , CA train busy" "Not progress,In progress"
|
|
line.long 0x08 "CFG_0,Training CFG 0"
|
|
bitfld.long 0x08 30. " CA_RANK ,Indicates which rank to do training on" "Rank0,Rank1"
|
|
bitfld.long 0x08 29. " CA_DRAM_X32 ,Using DRAM" "x16,x32"
|
|
bitfld.long 0x08 28. " CA_MR48 ,Training with MR41/48 mode" "MR41,MR48"
|
|
textline " "
|
|
hexmask.long.word 0x08 16.--25. 1. " CA_MRW_CA ,CA mrw ca"
|
|
hexmask.long.byte 0x08 8.--14. 1. " CA_START_TRIM_VAL ,Indicates the starting delay trim value to use for CA training"
|
|
hexmask.long.byte 0x08 0.--6. 1. " CA_END_TRIM_VAL ,Indicates the ending delay trim value to use for CA training"
|
|
line.long 0x0C "TIMING_CNTL1_0,EMC_ Ca training Timing CNTL 1 0"
|
|
bitfld.long 0x0C 24.--28. " CAEXT ,tCAEXT parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 18.--22. " CACKEH ,tCACKEH parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 12.--16. " CACD ,tCACD parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x0C 6.--10. " CAENT ,tCAENT parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 0.--4. " CACKEL ,tCACKEL parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "TIMING_CNTL2_0,EMC Ca Training Timing CNTL 2 0"
|
|
bitfld.long 0x10 0.--5. " CA_DQ_RDV ,Number of clocks to delay after CS is asserted before comparing CA/DQ" ",,,,,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,..."
|
|
group.long 0x43C++0x0B
|
|
line.long 0x00 "CA_LEAD_IN_0,EMC Ca Training Ca Lead In 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " CA_LEAD_IN_RISE ,CA rise value for the clock before CS is active"
|
|
hexmask.long.word 0x00 0.--9. 1. " CA_LEAD_IN_FALL ,CA fall value for the clock before CS is active"
|
|
line.long 0x04 "CA_0,EMC Ca Training Ca 0"
|
|
hexmask.long.word 0x04 16.--25. 1. " CA_RISE ,CA rise value for the clock CS is active"
|
|
hexmask.long.word 0x04 0.--9. 1. " CA_FALL ,CA fall value for the clock CS is active"
|
|
line.long 0x08 "CA_LEAD_OUT_0,EMC Ca Training ca Lead Out 0"
|
|
hexmask.long.word 0x08 16.--25. 1. " CA_LEAD_OUT_RISE ,CA rise value for the clock after CS is active"
|
|
hexmask.long.word 0x08 0.--9. 1. " CA_LEAD_OUT_FALL ,CA fall value for the clock after CS is active"
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "RESULT1_0,EMC Ca Training Result 1 0"
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "RESULT2_0,EMC Ca Training Result 2 0"
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "RESULT3_0,EMC Ca Training Result 3 0"
|
|
group.long 0x454++0x03
|
|
line.long 0x00 "RESULT4_0,EMC Ca Training Result 4 0"
|
|
tree.end
|
|
tree "EMC Pad Calibration"
|
|
width 15.
|
|
group.long 0x458++0x07
|
|
line.long 0x00 "CONFIG2_0,Auto-Calibration Settings for EMC Pads"
|
|
bitfld.long 0x00 24.--28. " AUTO_CAL_CNTL_PD_OFFSET ,2's complement offset for CS/ODT/CKE pull-down value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " AUTO_CAL_CNTL_PU_OFFSET ,2's complement offset for CS/ODT/CKE pull-up value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " AUTO_CAL_CMD_PD_OFFSET ,2's complement offset for ADDR/RAS/CAS/WE pull-down value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " AUTO_CAL_CMD_PU_OFFSET ,2's complement offset for ADDR/RAS/CAS/WE pull-up value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "CONFIG3_0,Auto-Calibration Settings for EMC Pads"
|
|
bitfld.long 0x04 8.--12. " AUTO_CAL_CLK_PD_OFFSET ,2's complement offset for CLK pull-down value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " AUTO_CAL_CLK_PU_OFFSET ,2's complement offset for CLK pull-up value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x460++0x03
|
|
line.long 0x00 "STATUS2_0,EMC Pad Calibration Status"
|
|
bitfld.long 0x00 24.--28. " AUTO_CAL_CNTL_PULLDOWN_ADJ ,Pullup/down code sent to pads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " AUTO_CAL_CNTL_PULLUP_ADJ ,Pullup/down code sent to pads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " AUTO_CAL_CMD_PULLDOWN_ADJ ,Pullup/down code sent to pads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " AUTO_CAL_CMD_PULLUP_ADJ , Pullup/down code sent to pads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree "DRAM timing parameter"
|
|
width 18.
|
|
group.long 0x468++0x0F
|
|
line.long 0x00 "IBDLY_0,DRAM Timing Parameter"
|
|
bitfld.long 0x00 0.--4. " IBDLY ,Tells the chip when to change IBDLY for DQ/DQS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DLL_XFORM_ADDR0_0,Configure Digital DLL for CMD/ADDR Group 0"
|
|
hexmask.long.word 0x04 12.--24. 1. " XFORM_ADDR0_OFFS ,Xform addr0 offs"
|
|
bitfld.long 0x04 0.--4. " XFORM_ADDR0_MULT , Xform addr0 mult" "a0,a1,,,,a5,,a7,,a9,..."
|
|
line.long 0x08 "DLL_XFORM_ADDR1_0,Configure Digital DLL for CMD/ADDR Group 1"
|
|
bitfld.long 0x08 12.--16. " XFORM_ADDR1_OFFS ,Xform addr1 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 0.--4. " XFORM_ADDR1_MULT , Xform addr1 mult" "a0,a1,,,,a5,,a7,,a9,..."
|
|
line.long 0x0C "DLL_XFORM_ADDR2_0,Configure Digital DLL for CMD/ADDR Group 2"
|
|
bitfld.long 0x0C 12.--16. " XFORM_ADDR2_OFFS ,Xform addr2 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 0.--4. " XFORM_ADDR2_MULT , Xform addr2 mult" "a0,a1,,,,a5,,a7,,a9,..."
|
|
rgroup.long 0x478++0x03
|
|
line.long 0x00 "DLI_ADDR_TRIM_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 20.--29. 1. " ADDR2_CURRENT_TRIM_VAL ,ADDR2 current trim val"
|
|
hexmask.long.word 0x00 10.--19. 1. " ADDR1_CURRENT_TRIM_VAL ,ADDR1 current trim val"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " ADDR0_CURRENT_TRIM_VAL ,ADDR0 current trim val"
|
|
group.long 0x47C++0x13
|
|
line.long 0x00 "DSR_VTTGEN_DRV_0, EMC Dsr Vttgen Drv 0"
|
|
bitfld.long 0x00 24.--26. " DSR_VTTGEN_DRVUP ,Indicates the VTTGEN VCLAMP regulator impedance" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " DSR_VTTGEN_DRVDN ,Indicates the VTTGEN VAUXP regulator impedance" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " DSR_VTTGEN_E_NO_VTTGEN ,Disables optional VTTGEN pads" "ADDR0,ADDR1,ADDR2,DATA1,DATA2,DATA3,..."
|
|
line.long 0x04 "TXDSRVTTGEN_0,DRAM timing parameter"
|
|
hexmask.long.word 0x04 0.--11. 1. " TXDSRVTTGEN ,Cycles to wait from DSR exit"
|
|
line.long 0x08 "XM2CMDPADCTRL4_0,XM2CMD Pad Control Register 4"
|
|
bitfld.long 0x08 10. " EMC2PMACRO_CFG_2T_PM_PHASE_SHIFT ,Enable 1/2 clocks of delay on OB 2T signals" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " EMC2PMACRO_CFG_2T_PM2PAD_FLOP_BYPASS ,Enables flop between NI-PI handoff structure and pad for OB 2T" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " EMC2PMACRO_CFG_1T_PM_PHASE_SHIFT ,Enables 1/2 clocks of delay on OB 1T signals" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " EMC2PMACRO_CFG_1T_PM2PAD_FLOP_BYPASS ,Enables flop between NI-PI handoff structure and pad for OB 1T" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " EMC2PMACRO_CFG_DAT_PM_PHASE_SHIFT ,Enables 1/2 clocks of delay on OB data signals" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " EMC2PMACRO_CFG_DAT_PM2PAD_FLOP_BYPASS ,enables flop between DQ/DQS NI-PI handoff structure and pad" "Disabled,Enabled"
|
|
line.long 0x0C "XM2CMDPADCTRL5_0,XM2CMD Pad Control 5"
|
|
bitfld.long 0x0C 20.--22. " EMC2TMC_CFG_XM2CMD_CLKBUF5_CONFIG ,CONFIG bit setting of CLKBUF5 pad" "DLCELL,TRIM/PDL,..."
|
|
bitfld.long 0x0C 16.--18. " EMC2TMC_CFG_XM2CMD_CLKBUF4_CONFIG ,CONFIG bit setting of CLKBUF4 pad" "DLCELL,TRIM/PDL,..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--14. " EMC2TMC_CFG_XM2CMD_CLKBUF3_CONFIG ,CONFIG bit setting of CLKBUF3 pad" "DLCELL,TRIM/PDL,..."
|
|
bitfld.long 0x0C 8.--10. " EMC2TMC_CFG_XM2CMD_CLKBUF2_CONFIG ,CONFIG bit setting of CLKBUF2 pad" "DLCELL,TRIM/PDL,..."
|
|
textline " "
|
|
bitfld.long 0x0C 4.--6. " EMC2TMC_CFG_XM2CMD_CLKBUF1_CONFIG ,CONFIG bit setting of CLKBUF1 pad" "DLCELL,TRIM/PDL,..."
|
|
bitfld.long 0x0C 0.--2. " EMC2TMC_CFG_XM2CMD_CLKBUF0_CONFIG ,CONFIG bit setting of CLKBUF0 pad" "DLCELL,TRIM/PDL,..."
|
|
line.long 0x10 "CFG_3_0,EMC Configuration"
|
|
bitfld.long 0x10 4.--6. " MRR_BYTESEL_X16 ,indicates to which byte lane the second DRAM's byte 0 is connected" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0.--2. " MRR_BYTESEL ,Indicates which AP byte lane is connected to DRAM byte 0" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "Configure Digital DLL"
|
|
width 27.
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "DLL_XFORM_DQS8_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 12.--20. 1. " XFORM_DQS8_OFFS ,Xform dqs8 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_DQS8_MULT ,Xform dqs8 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4A4++0x03
|
|
line.long 0x00 "DLL_XFORM_DQS9_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 12.--20. 1. " XFORM_DQS9_OFFS ,Xform dqs9 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_DQS9_MULT ,Xform dqs9 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4A8++0x03
|
|
line.long 0x00 "DLL_XFORM_DQS10_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 12.--20. 1. " XFORM_DQS10_OFFS ,Xform dqs10 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_DQS10_MULT ,Xform dqs10 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4AC++0x03
|
|
line.long 0x00 "DLL_XFORM_DQS11_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 12.--20. 1. " XFORM_DQS11_OFFS ,Xform dqs11 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_DQS11_MULT ,Xform dqs11 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "DLL_XFORM_DQS12_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 12.--20. 1. " XFORM_DQS12_OFFS ,Xform dqs12 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_DQS12_MULT ,Xform dqs12 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4B4++0x03
|
|
line.long 0x00 "DLL_XFORM_DQS13_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 12.--20. 1. " XFORM_DQS13_OFFS ,Xform dqs13 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_DQS13_MULT ,Xform dqs13 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4B8++0x03
|
|
line.long 0x00 "DLL_XFORM_DQS14_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 12.--20. 1. " XFORM_DQS14_OFFS ,Xform dqs14 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_DQS14_MULT ,Xform dqs14 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4BC++0x03
|
|
line.long 0x00 "DLL_XFORM_DQS15_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 12.--20. 1. " XFORM_DQS15_OFFS ,Xform dqs15 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_DQS15_MULT ,Xform dqs15 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "DLL_XFORM_QUSE8_0,Configure Digital DLL"
|
|
hexmask.long.byte 0x00 18.--22. 0x04 " XFORM_QUSE8_OFFS ,Xform quse8 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_QUSE8_MULT ,Xform quse8 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C4++0x03
|
|
line.long 0x00 "DLL_XFORM_QUSE9_0,Configure Digital DLL"
|
|
hexmask.long.byte 0x00 18.--22. 0x04 " XFORM_QUSE9_OFFS ,Xform quse9 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_QUSE9_MULT ,Xform quse9 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C8++0x03
|
|
line.long 0x00 "DLL_XFORM_QUSE10_0,Configure Digital DLL"
|
|
hexmask.long.byte 0x00 18.--22. 0x04 " XFORM_QUSE10_OFFS ,Xform quse10 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_QUSE10_MULT ,Xform quse10 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4CC++0x03
|
|
line.long 0x00 "DLL_XFORM_QUSE11_0,Configure Digital DLL"
|
|
hexmask.long.byte 0x00 18.--22. 0x04 " XFORM_QUSE11_OFFS ,Xform quse11 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_QUSE11_MULT ,Xform quse11 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "DLL_XFORM_QUSE12_0,Configure Digital DLL"
|
|
hexmask.long.byte 0x00 18.--22. 0x04 " XFORM_QUSE12_OFFS ,Xform quse12 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_QUSE12_MULT ,Xform quse12 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4D4++0x03
|
|
line.long 0x00 "DLL_XFORM_QUSE13_0,Configure Digital DLL"
|
|
hexmask.long.byte 0x00 18.--22. 0x04 " XFORM_QUSE13_OFFS ,Xform quse13 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_QUSE13_MULT ,Xform quse13 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4D8++0x03
|
|
line.long 0x00 "DLL_XFORM_QUSE14_0,Configure Digital DLL"
|
|
hexmask.long.byte 0x00 18.--22. 0x04 " XFORM_QUSE14_OFFS ,Xform quse14 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_QUSE14_MULT ,Xform quse14 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4DC++0x03
|
|
line.long 0x00 "DLL_XFORM_QUSE15_0,Configure Digital DLL"
|
|
hexmask.long.byte 0x00 18.--22. 0x04 " XFORM_QUSE15_OFFS ,Xform quse15 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_QUSE15_MULT ,Xform quse15 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "DLL_XFORM_DQ4_0,Configure Digital DLL"
|
|
hexmask.long.byte 0x00 18.--22. 0x04 " XFORM_TXDQ4_OFFS ,Xform txdq4 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_TXDQ4_MULT ,Xform txdq4 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4E4++0x03
|
|
line.long 0x00 "DLL_XFORM_DQ5_0,Configure Digital DLL"
|
|
hexmask.long.byte 0x00 18.--22. 0x04 " XFORM_TXDQ5_OFFS ,Xform txdq5 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_TXDQ5_MULT ,Xform txdq5 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4E8++0x03
|
|
line.long 0x00 "DLL_XFORM_DQ6_0,Configure Digital DLL"
|
|
hexmask.long.byte 0x00 18.--22. 0x04 " XFORM_TXDQ6_OFFS ,Xform txdq6 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_TXDQ6_MULT ,Xform txdq6 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4EC++0x03
|
|
line.long 0x00 "DLL_XFORM_DQ7_0,Configure Digital DLL"
|
|
hexmask.long.byte 0x00 18.--22. 0x04 " XFORM_TXDQ7_OFFS ,Xform txdq7 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_TXDQ7_MULT ,Xform txdq7 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x4F0++0x03
|
|
line.long 0x00 "DLI_RX_TRIM8_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 15.--24. 1. " QUSE_CURRENT_TRIM_VAL_BYTE_8 ,Quse current trim val byte 8"
|
|
hexmask.long.word 0x00 0.--9. 1. " DQS_CURRENT_TRIM_VAL_BYTE_8 ,Dqs current trim val byte 8"
|
|
rgroup.long 0x4F4++0x03
|
|
line.long 0x00 "DLI_RX_TRIM9_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 15.--24. 1. " QUSE_CURRENT_TRIM_VAL_BYTE_9 ,Quse current trim val byte 9"
|
|
hexmask.long.word 0x00 0.--9. 1. " DQS_CURRENT_TRIM_VAL_BYTE_9 ,Dqs current trim val byte 9"
|
|
rgroup.long 0x4F8++0x03
|
|
line.long 0x00 "DLI_RX_TRIM10_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 15.--24. 1. " QUSE_CURRENT_TRIM_VAL_BYTE_10 ,Quse current trim val byte 10"
|
|
hexmask.long.word 0x00 0.--9. 1. " DQS_CURRENT_TRIM_VAL_BYTE_10 ,Dqs current trim val byte 10"
|
|
rgroup.long 0x4FC++0x03
|
|
line.long 0x00 "DLI_RX_TRIM11_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 15.--24. 1. " QUSE_CURRENT_TRIM_VAL_BYTE_11 ,Quse current trim val byte 11"
|
|
hexmask.long.word 0x00 0.--9. 1. " DQS_CURRENT_TRIM_VAL_BYTE_11 ,Dqs current trim val byte 11"
|
|
rgroup.long 0x500++0x03
|
|
line.long 0x00 "DLI_RX_TRIM12_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 15.--24. 1. " QUSE_CURRENT_TRIM_VAL_BYTE_12 ,Quse current trim val byte 12"
|
|
hexmask.long.word 0x00 0.--9. 1. " DQS_CURRENT_TRIM_VAL_BYTE_12 ,Dqs current trim val byte 12"
|
|
rgroup.long 0x504++0x03
|
|
line.long 0x00 "DLI_RX_TRIM13_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 15.--24. 1. " QUSE_CURRENT_TRIM_VAL_BYTE_13 ,Quse current trim val byte 13"
|
|
hexmask.long.word 0x00 0.--9. 1. " DQS_CURRENT_TRIM_VAL_BYTE_13 ,Dqs current trim val byte 13"
|
|
rgroup.long 0x508++0x03
|
|
line.long 0x00 "DLI_RX_TRIM14_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 15.--24. 1. " QUSE_CURRENT_TRIM_VAL_BYTE_14 ,Quse current trim val byte 14"
|
|
hexmask.long.word 0x00 0.--9. 1. " DQS_CURRENT_TRIM_VAL_BYTE_14 ,Dqs current trim val byte 14"
|
|
rgroup.long 0x50C++0x03
|
|
line.long 0x00 "DLI_RX_TRIM15_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 15.--24. 1. " QUSE_CURRENT_TRIM_VAL_BYTE_15 ,Quse current trim val byte 15"
|
|
hexmask.long.word 0x00 0.--9. 1. " DQS_CURRENT_TRIM_VAL_BYTE_15 ,Dqs current trim val byte 15"
|
|
rgroup.long 0x510++0x03
|
|
line.long 0x00 "DLI_TX_TRIM4_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 0.--9. 1. " TXDQ_CURRENT_TRIM_VAL_BYTE_4 ,Dqs current trim val byte 4"
|
|
rgroup.long 0x514++0x03
|
|
line.long 0x00 "DLI_TX_TRIM5_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 0.--9. 1. " TXDQ_CURRENT_TRIM_VAL_BYTE_5 ,Dqs current trim val byte 5"
|
|
rgroup.long 0x518++0x03
|
|
line.long 0x00 "DLI_TX_TRIM6_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 0.--9. 1. " TXDQ_CURRENT_TRIM_VAL_BYTE_6 ,Dqs current trim val byte 6"
|
|
rgroup.long 0x51C++0x03
|
|
line.long 0x00 "DLI_TX_TRIM7_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 0.--9. 1. " TXDQ_CURRENT_TRIM_VAL_BYTE_7 ,Dqs current trim val byte 7"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "DLI_TRIM_TXDQS8_0,Set DLI TRIM"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EMC2PMACRO_CFG_TXDQS8_DLI ,Emc2macro configuration txdqs8 dli"
|
|
group.long 0x524++0x03
|
|
line.long 0x00 "DLI_TRIM_TXDQS9_0,Set DLI TRIM"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EMC2PMACRO_CFG_TXDQS9_DLI ,Emc2macro configuration txdqs9 dli"
|
|
group.long 0x528++0x03
|
|
line.long 0x00 "DLI_TRIM_TXDQS10_0,Set DLI TRIM"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EMC2PMACRO_CFG_TXDQS10_DLI ,Emc2macro configuration txdqs10 dli"
|
|
group.long 0x52C++0x03
|
|
line.long 0x00 "DLI_TRIM_TXDQS11_0,Set DLI TRIM"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EMC2PMACRO_CFG_TXDQS11_DLI ,Emc2macro configuration txdqs11 dli"
|
|
group.long 0x530++0x03
|
|
line.long 0x00 "DLI_TRIM_TXDQS12_0,Set DLI TRIM"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EMC2PMACRO_CFG_TXDQS12_DLI ,Emc2macro configuration txdqs12 dli"
|
|
group.long 0x534++0x03
|
|
line.long 0x00 "DLI_TRIM_TXDQS13_0,Set DLI TRIM"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EMC2PMACRO_CFG_TXDQS13_DLI ,Emc2macro configuration txdqs13 dli"
|
|
group.long 0x538++0x03
|
|
line.long 0x00 "DLI_TRIM_TXDQS14_0,Set DLI TRIM"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EMC2PMACRO_CFG_TXDQS14_DLI ,Emc2macro configuration txdqs14 dli"
|
|
group.long 0x53C++0x03
|
|
line.long 0x00 "DLI_TRIM_TXDQS15_0,Set DLI TRIM"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EMC2PMACRO_CFG_TXDQS15_DLI ,Emc2macro configuration txdqs15 dli"
|
|
group.long 0x540++0x0F
|
|
line.long 0x00 "CDB_CNTL_3_0,Emc Cdb Control 3"
|
|
bitfld.long 0x00 15.--17. " EMC2PMACRO_SEL_PI_TAP15 ,Emc2pmacro sel pi tap15" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " EMC2PMACRO_SEL_PI_TAP14 ,Emc2pmacro sel pi tap14" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " EMC2PMACRO_SEL_PI_TAP13 ,Emc2pmacro sel pi tap13" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " EMC2PMACRO_SEL_PI_TAP12 ,Emc2pmacro sel pi tap12" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " EMC2PMACRO_SEL_PI_TAP11 ,Emc2pmacro sel pi tap11" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " EMC2PMACRO_SEL_PI_TAP10 ,Emc2pmacro sel pi tap10" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "XM2DQSPADCTRL5_0 ,Emc Xm2dqspad Control 5_0"
|
|
bitfld.long 0x04 18.--22. " EMC2TMC_CFG_XM2DQS_BYTE7_VREF_DQ ,Emc2tmc cfg xm2dqs byte7 vref dq" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 12.--16. " EMC2TMC_CFG_XM2DQS_BYTE6_VREF_DQ ,Emc2tmc cfg xm2dqs byte6 vref dq" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " EMC2TMC_CFG_XM2DQS_BYTE5_VREF_DQ ,Emc2tmc cfg xm2dqs byte5 vref dq" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " EMC2TMC_CFG_XM2DQS_BYTE4_VREF_DQ ,Emc2tmc cfg xm2dqs byte4 vref dq" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "XM2DQSPADCTRL6_0,Emc Xm2dqspad Control 6-0"
|
|
bitfld.long 0x08 26.--30. " EMC2PMACRO_CFG_XM2DQS_BYTE7_VREF_DQS ,Emc2pmacro cfg xm2dqs byte7 vref dqs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 20.--24. " EMC2PMACRO_CFG_XM2DQS_BYTE6_VREF_DQS ,Emc2pmacro cfg xm2dqs byte6 vref dqs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 14.--18. " EMC2PMACRO_CFG_XM2DQS_BYTE5_VREF_DQS ,Emc2pmacro cfg xm2dqs byte5 vref dqs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 8.--12. " EMC2PMACRO_CFG_XM2DQS_BYTE4_VREF_DQS ,Emc2pmacro cfg xm2dqs byte4 vref dqs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "XM2DQPADCTRL3_0,Emc Xm2dqpad Control 3_0"
|
|
bitfld.long 0x0C 28.--30. " EMC2TMC_CFG_XM2DQ7_DLYIN_TRM ,Delay trim for byte 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 24.--26. " EMC2TMC_CFG_XM2DQ6_DLYIN_TRM ,Delay trim for byte 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 20.--22. " EMC2TMC_CFG_XM2DQ5_DLYIN_TRM ,Delay trim for byte 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 16.--18. " EMC2TMC_CFG_XM2DQ4_DLYIN_TRM ,Delay trim for byte 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x550++0x0B
|
|
line.long 0x00 "DLL_XFORM_ADDR3_0,Configure Digital DLL for CMD/ADDR group 3"
|
|
hexmask.long.word 0x00 12.--22. 1. " XFORM_ADDR3_OFFS ,Xform addr3 offs"
|
|
bitfld.long 0x00 0.--4. " XFORM_ADDR3_MULT ,Xform addr3 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "DLL_XFORM_ADDR4_0,Configure Digital DLL for CMD/ADDR group 4"
|
|
hexmask.long.word 0x04 12.--22. 1. " XFORM_ADDR4_OFFS ,Xform addr4 offs"
|
|
bitfld.long 0x04 0.--4. " XFORM_ADDR4_MULT ,Xform addr4 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "DLL_XFORM_ADDR5_0,Configure Digital DLL for CMD/ADDR group 5"
|
|
hexmask.long.word 0x08 12.--22. 1. " XFORM_ADDR5_OFFS ,Xform addr5 offs"
|
|
bitfld.long 0x08 0.--4. " XFORM_ADDR5_MULT ,Xform addr5 mult" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x55c++0x03
|
|
line.long 0x00 "DLI_ADDR_TRIM2_0,Configure Digital DLL"
|
|
hexmask.long.word 0x00 20.--29. 1. " ADDR5_CURRENT_TRIM_VAL ,Addr5 current trim val"
|
|
hexmask.long.word 0x00 10.--19. 1. " ADDR4_CURRENT_TRIM_VAL ,Addr4 current trim val"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " ADDR3_CURRENT_TRIM_VAL ,Addr3 current trim val"
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "CFG_PIPE_0,Datapipe Configuration Register"
|
|
bitfld.long 0x00 15. " EMC2PMACRO_CFG_BYPASS_OB_DATAPIPE4 ,Bypass data pipeline stage2 between E" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EMC2PMACRO_CFG_BYPASS_OB_DATAPIPE3 ,Bypass data pipeline stage2 between E" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EMC2PMACRO_CFG_BYPASS_OB_DATAPIPE2 ,Bypass data pipeline stage2 between E" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " EMC2PMACRO_CFG_BYPASS_OB_DATAPIPE1 ,Bypass data pipeline stage1 between EMC and data pad-macro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EMC2PMACRO_CFG_BYPASS_OB_ADDRPIPE2 ,Bypass data pipeline stage between EMC and address pad-macro" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EMC2PMACRO_CFG_BYPASS_OB_ADDRPIPE1 ,Bypass address pipeline stage between EMC and address pad-macro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EMC2PMACRO_CFG_BYPASS_IB_DATAPIPE4 ,Bypass data pipeline stage2 between E" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EMC2PMACRO_CFG_BYPASS_IB_DATAPIPE3 ,Bypass data pipeline stage2 between E" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMC2PMACRO_CFG_BYPASS_IB_DATAPIPE2 ,Bypass data pipeline stage2 between E" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EMC2PMACRO_CFG_BYPASS_IB_DATAPIPE1 ,Bypass data pipeline stage1 between EMC and data pad-macro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EMC2PMACRO_CFG_BYPASS_IB_ADDRPIPE2 ,Bypass address pipeline stage between EMC and address pad-macro" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EMC2PMACRO_CFG_BYPASS_IB_ADDRPIPE1 ,Bypass address pipeline stage between EMC and address pad-macro" "Disabled,Enabled"
|
|
group.long 0x564++0x13
|
|
line.long 0x00 "QPOP_0,DRAM timing parameter"
|
|
bitfld.long 0x00 0.--5. " QPOP ,Time from read command to pop data from the pad macro FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,..."
|
|
line.long 0x04 "QUSE_WIDTH_0,DRAM timing parameter"
|
|
bitfld.long 0x04 0.--3. " QUSE_DURATION ,Additional QUSE duration apart from default BL/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PUTERM_WIDTH_0,DRAM timing parameter"
|
|
bitfld.long 0x08 0.--3. " PUTERM_DURATION ,Additional PUTERM duration apart from default BL/2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "EMC_BGBIAS_CTL0_0,BGBIAS Pad controls"
|
|
bitfld.long 0x0C 3. " BIAS0_DSC_E_PWRD_IBIAS_RX ,Bias current going out to brick receiver" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " BIAS0_DSC_E_PWRD_IBIAS_VTTGEN ,Active High. Disables biasing current going out to VTTGEN cells" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " BIAS0_DSC_E_PWRD ,Disables all DC current paths within entire cell" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " BIAS0_DSC_BG_SEL_N ,Select BandGap reference current" "Enabled,Disabled"
|
|
line.long 0x10 "PUTERM_ADJ_0,PUTERM controls"
|
|
bitfld.long 0x10 7. " CFG_PUTERM_EXTEND_HALF_CLK ,Extend the PUTERM window by half a clock" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--1. " CFG_PUTERM_LATE ,Half-cycle increments" "0,1,2,3"
|
|
rgroup.long 0x5F0++0x0F
|
|
line.long 0x00 "CA_TRAINING_SP1_RESULT1_0,Emc Ca Training Sp1 Result1 0"
|
|
line.long 0x04 "CA_TRAINING_SP1_RESULT2_0,Emc Ca Training Sp1 Result2 0"
|
|
line.long 0x08 "CA_TRAINING_SP1_RESULT3_0,Emc Ca Training Sp1 Result3 0"
|
|
line.long 0x0C "CA_TRAINING_SP1_RESULT4_0,Emc Ca Training Sp1 Result4 0"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "AHB Controller"
|
|
base ad:0x6000C000
|
|
tree "AHB Arbiter Register"
|
|
width 17.
|
|
sif cpuis("TEGRAX1")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DISABLE_0,AHB Arbitration Controller"
|
|
bitfld.long 0x00 31. " DIS_BUS_PARK ,Disable bus parking" "No,Yes"
|
|
bitfld.long 0x00 30. " DIS_PENULTIMATE_ARB ,Disable arbitration on the second to last transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " USB2 ,Disable USB2 from arbitration" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SE ,Disable SE from arbitration" "No,Yes"
|
|
bitfld.long 0x00 7. " APBDMA ,Disable APB-DMA from arbitration" "No,Yes"
|
|
bitfld.long 0x00 6. " USB ,Disable USB from arbitration" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ARC ,Disable ARC from arbitration" "No,Yes"
|
|
bitfld.long 0x00 1. " COP ,Disable COP from arbitration" "No,Yes"
|
|
bitfld.long 0x00 0. " CPU ,Disable CPU from arbitration" "No,Yes"
|
|
textline " "
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DISABLE_0,AHB Arbitration Controller"
|
|
bitfld.long 0x00 31. " DIS_BUS_PARK ,Disable bus parking" "No,Yes"
|
|
bitfld.long 0x00 30. " DIS_PENULTIMATE_ARB ,Disable arbitration on the second to last transfer" "No,Yes"
|
|
bitfld.long 0x00 21. " MIPIHSI ,Disable MIPIHSI from arbitration" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 18. " USB2 ,Disable USB2 from arbitration" "No,Yes"
|
|
bitfld.long 0x00 17. " USB3 ,Disable USB3 from arbitration" "No,Yes"
|
|
bitfld.long 0x00 16. " BSEA ,Disable BSEA from arbitration" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DDS ,Disable DDS from arbitration" "No,Yes"
|
|
bitfld.long 0x00 14. " SE ,Disable SE from arbitration" "No,Yes"
|
|
bitfld.long 0x00 13. " BSEV ,Disable BSEV from arbitration" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SNOR ,Disable SNOR from arbitration" "No,Yes"
|
|
bitfld.long 0x00 7. " APBDMA ,Disable APB-DMA from arbitration" "No,Yes"
|
|
bitfld.long 0x00 6. " USB ,Disable USB from arbitration" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AHBDMA ,Disable AHB-DMA from arbitration" "No,Yes"
|
|
bitfld.long 0x00 4. " ARC ,Disable ARC from arbitration" "No,Yes"
|
|
bitfld.long 0x00 3. " CSITE ,Disable CoreSight from arbitration" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VCP ,Disable VCP from arbitration" "No,Yes"
|
|
bitfld.long 0x00 1. " COP ,Disable COP from arbitration" "No,Yes"
|
|
bitfld.long 0x00 0. " CPU ,Disable CPU from arbitration" "No,Yes"
|
|
textline " "
|
|
endif
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "PRIORITY_CTRL_0,AHB Arbitration Priority Control Register"
|
|
bitfld.long 0x00 29.--31. " AHB_PRIORITY_WEIGHT ,AHB priority weight count" "0,1,2,3,4,5,6,7"
|
|
hexmask.long 0x00 0.--28. 1. " AHB_PRIORITY_SELECT ,Priority group"
|
|
line.long 0x04 "USR_PROTECT_0,USR Protection Register"
|
|
bitfld.long 0x04 8. " CACHE ,Abort on USR mode access to Cache memory space" "ABT_DIS,ABT_EN"
|
|
bitfld.long 0x04 7. " ROM ,Abort on USR mode access to internal ROM memory space" "ABT_DIS,ABT_EN"
|
|
bitfld.long 0x04 6. " APB ,Abort on USR mode access to APB memory space" "ABT_DIS,ABT_EN"
|
|
textline " "
|
|
bitfld.long 0x04 5. " AHB ,Abort on USR mode access to AHB memory space" "ABT_DIS,ABT_EN"
|
|
bitfld.long 0x04 3. " IRAMD ,Abort on USR mode access to iRAMd memory space" "ABT_DIS,ABT_EN"
|
|
bitfld.long 0x04 2. " IRAMC ,Abort on USR mode access to iRAMc memory space" "ABT_DIS,ABT_EN"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IRAMB ,Abort on USR mode access to iRAMb memory space" "ABT_DIS,ABT_EN"
|
|
bitfld.long 0x04 0. " IRAMA ,Abort on USR mode access to iRAMa memory space" "ABT_DIS,ABT_EN"
|
|
textline " "
|
|
tree.end
|
|
tree "AHB GIZMO"
|
|
width 25.
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "GIZMO_AHB_DMA,Memory Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REQ_NEG_CNT ,AHB master request negate count"
|
|
bitfld.long 0x00 18. " IMMEDIATE ,Start AHB write immediately" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " MAX_AHB_BURSTSIZE ,Maximum allowed AHB burst size" "1,4,8,16"
|
|
textline " "
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 9. " EN_USB_WAIT_COMMIT_ON_XK_STALL ,En USB wait commit on XK stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " WR_WAIT_COMMIT_ON_XK ,Wr wait commit on XK" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 9. " EN_USB_WAIT_COMMIT_ON_1K_STALL ,En USB wait commit on 1K stall" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " WR_WAIT_COMMIT_ON_1K ,Wr wait commit on 1K" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 7. " DONT_SPLIT_AHB_WR ,Split AHB write transaction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACCEPT_AHB_WR_ALWAYS ,Accept AHB write request" "Accept on check,Accept on nocheck"
|
|
bitfld.long 0x00 2. " ENB_FAST_REARBITRATE ,Enable fast re-arbitration" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FORCE_TO_AHB_SINGLE ,Force all AHB transaction to single data request transaction" "Not single data,Single data"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLE_SPLIT ,Enable spliting AHB transaction" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "GIZMO_APB_DMA_0,AHB Gizmo APB-DMA Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " REQ_NEG_CNT ,AHB master request negate count"
|
|
bitfld.long 0x04 18. " IMMEDIATE ,Start AHB write immediately" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--17. " MAX_AHB_BURSTSIZE ,Maximum allowed AHB burst size" "1,4,8,16"
|
|
textline " "
|
|
sif cpuis("TEGRAX1")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MASTER_SWID_0,AHB Master SWID[0] Register"
|
|
bitfld.long 0x00 18. " USB2 ,SWID for USB2" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SE ,SWID for SE" "Disabled,ENabled"
|
|
bitfld.long 0x00 6. " USB1 ,SWID for USB1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ARC ,SWID for ARC" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COP ,SWID for COP" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CPU ,SWID for CPU" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MASTER_SWID_0,AHB Master SWID[0] Register"
|
|
bitfld.long 0x00 21. " MIPIHSI ,SWID for MIPIHSI" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " USB2 ,SWID for USB2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " USB3 ,SWID for USB3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BSEA ,SWID for BSEA" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " DDS ,SWID for DDS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SE ,SWID for SE" "Disabled,ENabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BSEV ,SWID for BSEV" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " NOR ,SWID for NOR" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " USB1 ,SWID for USB1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AHBDMA ,SWID for AHBDMA" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ARC ,SWID for ARC" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CORESIGHT ,SWID for CORESIGHT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VCP ,SWID for VCP" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COP ,SWID for COP" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CPU ,SWID for CPU" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
group.long 0x20++0x13
|
|
line.long 0x00 "GIZMO_USB_0,AHB Gizmo USB Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REQ_NEG_CNT ,AHB master request negate count"
|
|
bitfld.long 0x00 18. " IMMEDIATE ,Start AHB write request immediately" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " MAX_AHB_BURSTSIZE ,Maximum allowed AHB burst size" "1,4,8,16"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DONT_SPLIT_AHB_WR ,Split AHB write transaction" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " ACCEPT_AHB_WR_ALWAYS ,Accept AHB write request" "Accept on check,Accept on nocheck"
|
|
bitfld.long 0x00 2. " ENB_FAST_REARBITRATE ,Enable fast re-arbitration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FORCE_TO_AHB_SINGLE ,Force all AHB transaction to single data request transaction" "Not single data,Single data"
|
|
bitfld.long 0x00 0. " ENABLE_SPLIT ,Enable spliting AHB transactions" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "GIZMO_AHB_XBAR_BRIDGE_0,AHB Gizmo AHB XBAR Bridge Control Register"
|
|
bitfld.long 0x04 7. " DONT_SPLIT_AHB_WR ,Split AHB write transaction" "Enabled,Disabled"
|
|
bitfld.long 0x04 6. " ACCEPT_AHB_WR_ALWAYS ,Accept AHB write request" "Accept on check,Accept on nocheck"
|
|
bitfld.long 0x04 4.--5. " MAX_IP_BURSTSIZE ,Maximum allowed IP burst size" "1,4,8,16"
|
|
textline " "
|
|
bitfld.long 0x04 3. " IMMEDIATE ,Start write request to device immediately" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " ENB_FAST_REARBITRATE ,Enable fast re-arbitration" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " FORCE_TO_AHB_SINGLE ,Force all AHB transaction to single data request transaction" "Not single data,Single data"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE_SPLIT ,Enable splitting AHB transactions" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x08 "GIZMO_CPU_AHB_BRIDGE_0,AHB Gizmo CPU AHB Bridge Control Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " REQ_NEG_CNT ,AHB master request negate count."
|
|
bitfld.long 0x08 18. " IMMEDIATE ,Start AHB write request immediately" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--17. " MAX_AHB_BURSTSIZE ,Maximum allowed AHB burst size" "1,4,8,16"
|
|
line.long 0x0C "GIZMO_COP_AHB_BRIDGE_0,AHB Gizmo COP AHB Bridge Control Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " REQ_NEG_CNT ,AHB master request negate count"
|
|
bitfld.long 0x0C 18. " IMMEDIATE ,Start AHB write request immediately" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--17. " MAX_AHB_BURSTSIZE ,Maximum allowed AHB burst size" "1,4,8,16"
|
|
line.long 0x10 "GIZMO_XBAR_APB_CTLR_0,AHB Gizmo XBAR APB Control Register"
|
|
bitfld.long 0x10 4.--5. " MAX_IP_BURSTSIZE ,Maximum allowed IP burst size" "1,4,8,16"
|
|
bitfld.long 0x10 3. " IMMEDIATE ,Start write request to device immediately" "Disabled,Enabled"
|
|
sif cpuis("TEGRAX1")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "MASTER_SWID_1,AHB Master SWID[1] Register"
|
|
bitfld.long 0x00 18. " USB2 ,SWID for USB2" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SE ,SWID for SE" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " USB1 ,SWID for USB1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ARC ,SWID for ARC" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COP ,SWID for COP" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CPU ,SWID for CPU" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "GIZMO_VCP_AHB_BRIDGE_0,AHB Gizmo VCP AHB Bridge Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REQ_NEG_CNT ,AHB master request negate count"
|
|
bitfld.long 0x00 18. " IMMEDIATE ,AHB master gizmo" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " MAX_AHB_BURSTSIZE ,Maximum allowed AHB burst size" "1,4,8,16"
|
|
line.long 0x04 "MASTER_SWID_1,AHB Master SWID[1] Register"
|
|
bitfld.long 0x04 20. " MIPIHSI ,SWID for MIPIHSI" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " USB2 ,SWID for USB2" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " USB3 ,SWID for USB3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " BSEA ,SWID for BSEA" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " DDS ,SWID for DDS" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " SE ,SWID for SE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " BSEV ,SWID for BSEV" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " NOR ,SWID for NOR" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " USB1 ,SWID for USB1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " AHBDMA ,SWID for AHBDMA" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " ARC ,SWID for ARC" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CORESIGHT ,SWID for CORESIGHT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VCP ,SWID for VCP" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " COP ,SWID for COP" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CPU ,SWID for CPU" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "GIZMO_SE_0,AHB Gizmo SE Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REQ_NEG_CNT ,AHB master request negate count"
|
|
bitfld.long 0x00 18. " IMMEDIATE ,Start AHB write request immediately" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " MAX_AHB_BURSTSIZE ,Maximum allowed AHB burst size" "1,4,8,16"
|
|
textline " "
|
|
line.long 0x04 "GIZMO_TZRAM_0,AHB Gizmo AHB TZRAM Control Register"
|
|
bitfld.long 0x04 7. " DONT_SPLIT_AHB_WR ,Do not split AHB write transaction" "Enabled,Disabled"
|
|
bitfld.long 0x04 6. " ACCEPT_AHB_WR_ALWAYS ,Accept AHB write request always" "Accept on check,Accept on nocheck"
|
|
bitfld.long 0x04 2. " ENB_FAST_REARBITRATE ,Enable fast re-arbitration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FORCE_TO_AHB_SINGLE ,Force all AHB transaction to single data request transaction" "Not single data,Single data"
|
|
bitfld.long 0x04 0. " ENABLE_SPLIT ,Enable splitting AHB transactions" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("TEGRAX1")
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "GIZMO_BSEV_0,AHB Gizmo BSE Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REQ_NEG_CNT ,AHB master request negate count"
|
|
bitfld.long 0x00 18. " IMMEDIATE ,Start AHB write request immediately" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " MAX_AHB_BURSTSIZE ,Maximum allowed AHB burst size" "1,4,8,16"
|
|
textline " "
|
|
group.long 0x74++0x07
|
|
line.long 0x00 "GIZMO_BSEA_0 ,AHB Gizmo SCE Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REQ_NEG_CNT ,AHB master request negate count"
|
|
bitfld.long 0x00 18. " IMMEDIATE ,Start AHB write request immediately" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " MAX_AHB_BURSTSIZE ,Maximum allowed AHB burst size" "1,4,8,16"
|
|
textline " "
|
|
line.long 0x04 "GIZMO_NOR_0,AHB Gizmo AHB NOR Flash Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " REQ_NEG_CNT ,AHB master request negate count"
|
|
bitfld.long 0x04 18. " IMMEDIATE ,Start AHB write request immediately" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--17. " MAX_AHB_BURSTSIZE ,Maximum allowed AHB burst size" "1,4,8,16"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DONT_SPLIT_AHB_WR ,Do not split AHB write transaction" "Enabled,Disabled"
|
|
bitfld.long 0x04 6. " ACCEPT_AHB_WR_ALWAYS ,Always accept AHB write requests" "Accept on check,Accept on nocheck"
|
|
bitfld.long 0x04 2. " ENB_FAST_REARBITRATE ,Enable fast re-arbitration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FORCE_TO_AHB_SINGLE ,Force all AHB transactions to single data request transaction" "Not single data,Single data"
|
|
bitfld.long 0x04 0. " ENABLE_SPLIT ,Enable splitting AHB transactions" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "GIZMO_USB2_0,AHB Gizmo USB2 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REQ_NEG_CNT ,AHB master request negate count"
|
|
bitfld.long 0x00 18. " IMMEDIATE ,Start AHB write request immediately" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " MAX_AHB_BURSTSIZE ,Maximum allowed AHB burst size" "1,4,8,16"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DONT_SPLIT_AHB_WR ,Do not split AHB write transaction" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " ACCEPT_AHB_WR_ALWAYS ,Accept AHB write request always" "Accept on check,Accept on nocheck"
|
|
bitfld.long 0x00 2. " ENB_FAST_REARBITRATE ,Enable fast re-arbitration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FORCE_TO_AHB_SINGLE ,Force all AHB transaction to single data request transaction" "Not single data,Single data"
|
|
bitfld.long 0x00 0. " ENABLE_SPLIT ,Enable splitting AHB transactions" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("TEGRAX1")
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "GIZMO_USB3_0,AHB Gizmo USB3 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REQ_NEG_CNT ,AHB master request negate count"
|
|
bitfld.long 0x00 18. " IMMEDIATE ,Start AHB write request immediately" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " MAX_AHB_BURSTSIZE ,Maximum allowed AHB burst size" "1,4,8,16"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DONT_SPLIT_AHB_WR ,Do not split AHB write transaction" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " ACCEPT_AHB_WR_ALWAYS ,Accept AHB write request always" "Accept on check,Accept on nocheck"
|
|
bitfld.long 0x00 2. " ENB_FAST_REARBITRATE ,Enable fast re-arbitration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FORCE_TO_AHB_SINGLE ,Force all AHB transaction to single data request transaction" "Not single data,Single data"
|
|
bitfld.long 0x00 0. " ENABLE_SPLIT ,Enable splitting AHB transactions" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "GIZMO_DDS_0,AHB Gizmo DDS Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REQ_NEG_CNT ,AHB master request negate count"
|
|
bitfld.long 0x00 18. " IMMEDIATE ,Start AHB write request immediately" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " MAX_AHB_BURSTSIZE ,Maximum allowed AHB burst size" "1,4,8,16"
|
|
line.long 0x04 "GIZMO_MIPIHSI_0,AHB Gizmo MIPIHSI Control Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " REQ_NEG_CNT ,AHB master request negate count"
|
|
bitfld.long 0x04 18. " IMMEDIATE ,Start AHB write request immediately" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--17. " MAX_AHB_BURSTSIZE ,Maximum allowed AHB burst size" "1,4,8,16"
|
|
endif
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "GIZMO_ARC_0,AHB Gizmo ARC Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REQ_NEG_CNT ,AHB master request negate count"
|
|
bitfld.long 0x00 18. " IMMEDIATE ,Start AHB write request immediately" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " MAX_AHB_BURSTSIZE ,Maximum allowed AHB burst size" "1,4,8,16"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "AHB_WRQ_EMPTY_0 ,AHB WRQ Empty 0"
|
|
bitfld.long 0x00 1. " COP_AHB_WRQ_EMPTY ,COP ahb wrq empty" "0,1"
|
|
bitfld.long 0x00 0. " CPU_AHB_WRQ_EMPTY ,CPU ahb wrq empty" "0,1"
|
|
tree.end
|
|
tree "AHB Memory Controller Slave Registers"
|
|
width 26.
|
|
group.long 0xCC++0x0F
|
|
line.long 0x00 "AHB_MEM_PREFETCH_CFG5_0,AHB AHB Mem Prefetch CFG5 0"
|
|
bitfld.long 0x00 31. " ENABLE ,Enable" "Disabled,Enabled"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 26.--30. " AHB_MST_ID ,AHB mst ID USB" "CPU,COP,VCP,CSITE,IDE,AHBDMA,USB,APBDMA,,SDIO1,NAND_FLASH,,HSMMC,,SE,,BSEA,USB3,USB2,SDIO2,?..."
|
|
else
|
|
bitfld.long 0x00 26.--30. " AHB_MST_ID ,AHB mst ID USB" "CPU,COP,VCP,CSITE,IDE,AHBDMA,USB,APBDMA,,SDIO1,NAND_FLASH,SNOR,HSMMC,BSEV,SE,,BSEA,USB3,USB2,SDIO2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21.--25. " ADDR_BNDRY ,2^(n+6) byte boundary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--15. 1. " INACTIVITY_TIMEOUT ,Inactivity timeout"
|
|
line.long 0x04 "AHB_MEM_PREFETCH_CFG6_0 ,AHB AHB Mem Prefetch CFG6 0"
|
|
bitfld.long 0x04 31. " ENABLE ,Enable" "Disabled,Enabled"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x04 26.--30. " AHB_MST_ID ,AHB mst ID USB" "CPU,COP,VCP,CSITE,IDE,AHBDMA,USB,APBDMA,,SDIO1,NAND_FLASH,,HSMMC,,SE,,BSEA,USB3,USB2,SDIO2,?..."
|
|
else
|
|
bitfld.long 0x04 26.--30. " AHB_MST_ID ,AHB mst ID USB" "CPU,COP,VCP,CSITE,IDE,AHBDMA,USB,APBDMA,,SDIO1,NAND_FLASH,SNOR,HSMMC,BSEV,SE,,BSEA,USB3,USB2,SDIO2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 21.--25. " ADDR_BNDRY ,2^(n+6) byte boundary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x04 0.--15. 1. " INACTIVITY_TIMEOUT ,Inactivity timeout"
|
|
line.long 0x08 "AHB_MEM_PREFETCH_CFG7_0 ,AHB AHB Mem Prefetch CFG7 0"
|
|
bitfld.long 0x08 31. " ENABLE ,Enable" "Disabled,Enabled"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x08 26.--30. " AHB_MST_ID ,AHB mst ID USB" "CPU,COP,VCP,CSITE,IDE,AHBDMA,USB,APBDMA,,SDIO1,NAND_FLASH,,HSMMC,,SE,,BSEA,USB3,USB2,SDIO2,?..."
|
|
else
|
|
bitfld.long 0x08 26.--30. " AHB_MST_ID ,AHB mst ID USB" "CPU,COP,VCP,CSITE,IDE,AHBDMA,USB,APBDMA,,SDIO1,NAND_FLASH,SNOR,HSMMC,BSEV,SE,,BSEA,USB3,USB2,SDIO2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 21.--25. " ADDR_BNDRY ,2^(n+6) byte boundary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x08 0.--15. 1. " INACTIVITY_TIMEOUT ,Inactivity timeout"
|
|
line.long 0x0C "AHB_MEM_PREFETCH_CFG8_0 ,AHB AHB Mem Prefetch CFG8 0"
|
|
bitfld.long 0x0C 31. " ENABLE ,Enable" "Disabled,Enabled"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x0C 26.--30. " AHB_MST_ID ,AHB mst ID USB" "CPU,COP,VCP,CSITE,IDE,AHBDMA,USB,APBDMA,,SDIO1,NAND_FLASH,,HSMMC,,SE,,BSEA,USB3,USB2,SDIO2,?..."
|
|
else
|
|
bitfld.long 0x0C 26.--30. " AHB_MST_ID ,AHB mst ID USB" "CPU,COP,VCP,CSITE,IDE,AHBDMA,USB,APBDMA,,SDIO1,NAND_FLASH,SNOR,HSMMC,BSEV,SE,,BSEA,USB3,USB2,SDIO2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 21.--25. " ADDR_BNDRY ,2^(n+6) byte boundary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x0C 0.--15. 1. " INACTIVITY_TIMEOUT ,Inactivity timeout"
|
|
width 26.
|
|
group.long 0xDC++0x0F
|
|
line.long 0x00 "AHB_MEM_PREFETCH_CFG_X_0,AHB AHB Mem Prefetch Cfg X 0"
|
|
bitfld.long 0x00 15. " DISABLE_ADDR_BNDY_CHK_MST8 ,Disable addr bndy chk mst8" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DISABLE_ADDR_BNDY_CHK_MST7 ,Disable addr bndy chk mst 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DISABLE_ADDR_BNDY_CHK_MST6 ,Disable addr bndy chk mst 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DISABLE_ADDR_BNDY_CHK_MST5 , Disable addr bndy chk mst 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DISABLE_ADDR_BNDY_CHK_MST4 ,Disable addr bndy chk mst 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DISABLE_ADDR_BNDY_CHK_MST3 ,Disable addr bndy chk mst 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DISABLE_ADDR_BNDY_CHK_MST2 ,Disable addr bndy chk mst 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DISABLE_ADDR_BNDY_CHK_MST1 ,Disable addr bndy chk mst 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DISABLE_CHECK_SIZE_MASTER8 ,Disable check size master 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DISABLE_CHECK_SIZE_MASTER7 ,Disable check size master 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DISABLE_CHECK_SIZE_MASTER6 ,Disable check size master 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DISABLE_CHECK_SIZE_MASTER5 ,Disable check size master 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DISABLE_CHECK_SIZE_MASTER4 ,Disable check size master 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DISABLE_CHECK_SIZE_MASTER3 ,Disable check size master 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISABLE_CHECK_SIZE_MASTER2 ,Disable check size master 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DISABLE_CHECK_SIZE_MASTER1 ,Disable check size master 1" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "ARBITRATION_XBAR_CTRL_0,XBAR Control Register"
|
|
bitfld.long 0x04 16. " MEM_INIT_DONE ,Software should set this bit when memory has been initialized" "Not done,Done"
|
|
bitfld.long 0x04 1. " HOLD_DIS ,Software writes to modify" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 0. " POST_DIS ,Software writes to modify" "No,Yes"
|
|
textline " "
|
|
line.long 0x08 "AHB_MEM_PREFETCH_CFG3_0 ,AHB AHB Mem Prefetch CFG 3 0"
|
|
bitfld.long 0x08 31. " ENABLE ,Enable" "Disabled,Enabled"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x08 26.--30. " AHB_MST_ID ,AHBDMA master" "CPU,COP,VCP,CSITE,IDE,AHBDMA,USB,APBDMA,,,,,HSMMC,,SE,,BSEA,USB3,USB2,?..."
|
|
else
|
|
bitfld.long 0x08 26.--30. " AHB_MST_ID ,AHBDMA master" "CPU,COP,VCP,CSITE,IDE,AHBDMA,USB,APBDMA,,,,SNOR,HSMMC,BSEV,SE,,BSEA,USB3,USB2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 21.--25. " ADDR_BNDRY ,2^(n+6) byte boundary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x08 0.--15. 1. " INACTIVITY_TIMEOUT ,2048 cycles"
|
|
textline " "
|
|
line.long 0x0C "AHB_MEM_PREFETCH_CFG4_0 ,AHB AHB Mem Prefetch CFG 4 0"
|
|
bitfld.long 0x0C 31. " ENABLE ,Enable" "Disabled,Enabled"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x0C 26.--30. " AHB_MST_ID ,AHBDMA master" "CPU,COP,VCP,CSITE,IDE,AHBDMA,USB,APBDMA,,,,,HSMMC,,SE,,BSEA,USB3,USB2,?..."
|
|
else
|
|
bitfld.long 0x0C 26.--30. " AHB_MST_ID ,AHBDMA master" "CPU,COP,VCP,CSITE,IDE,AHBDMA,USB,APBDMA,,,,SNOR,HSMMC,BSEV,SE,,BSEA,USB3,USB2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 21.--25. " ADDR_BNDRY ,2^(n+6) byte boundary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x0C 0.--15. 1. " INACTIVITY_TIMEOUT ,2048 cycles"
|
|
textline " "
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "AVP_PPCS_RD_COH_STATUS_0,ARM7 outstanding rd/wr"
|
|
bitfld.long 0x00 16. " RDS_OUTSTANDING ,Rds outstanding" "0,1"
|
|
bitfld.long 0x00 0. " WRS_OUTSTANDING ,Wrs outstanding" "0,1"
|
|
textline " "
|
|
group.long 0x0F0++0x07
|
|
line.long 0x00 "AHB_MEM_PREFETCH_CFG1_0,NV_ahbslvmem prefetch cfg1"
|
|
bitfld.long 0x00 31. " ENABLE ,Enable" "Disabled,Enabled"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 26.--30. " AHB_MST_ID ,AHBDMA master" "CPU,COP,VCP,CSITE,IDE,AHBDMA,USB,APBDMA,,,,,HSMMC,,SE,,BSEA,USB3,USB2,?..."
|
|
else
|
|
bitfld.long 0x00 26.--30. " AHB_MST_ID ,AHBDMA master" "CPU,COP,VCP,CSITE,IDE,AHBDMA,USB,APBDMA,,,,SNOR,HSMMC,BSEV,SE,,BSEA,USB3,USB2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 21.--25. " ADDR_BNDRY ,2^(n+6) byte boundary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--15. 1. " INACTIVITY_TIMEOUT ,2048 cycles"
|
|
textline " "
|
|
line.long 0x04 "AHB_MEM_PREFETCH_CFG2_0,NV_ahbslvmem prefetch cfg2"
|
|
bitfld.long 0x04 31. " ENABLE ,Enable" "Disabled,Enabled"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x04 26.--30. " AHB_MST_ID ,AHBDMA master" "CPU,COP,VCP,CSITE,IDE,AHBDMA,USB,APBDMA,,,,,HSMMC,,SE,,BSEA,USB3,USB2,?..."
|
|
else
|
|
bitfld.long 0x04 26.--30. " AHB_MST_ID ,AHBDMA master" "CPU,COP,VCP,CSITE,IDE,AHBDMA,USB,APBDMA,,,,SNOR,HSMMC,BSEV,SE,,BSEA,USB3,USB2,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 21.--25. " ADDR_BNDRY ,2^(n+6) byte boundary" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x04 0.--15. 1. " INACTIVITY_TIMEOUT ,2048 cycles"
|
|
textline " "
|
|
width 36.
|
|
rgroup.long 0xF8++0x17
|
|
line.long 0x00 "AHBSLVMEM_STATUS_0,Ahbslv Outstanding rd"
|
|
bitfld.long 0x00 1. " PPCS_RDS_OUTSTANDING ,PPCS rds outstanding" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GIZMO_IP_RDQUE_EMPTY ,GIZMO IP rdque empty" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "ARBITRATION_AHB_MEM_WRQUE_MST_ID_0,AHB Memory Write Queue AHB Master ID Register"
|
|
line.long 0x08 "ARBITRATION_CPU_ABORT_ADDR_0,CPU Abort Address Register"
|
|
line.long 0x0C "ARBITRATION_CPU_ABORT_INFO_0,CPU Abort Info Register"
|
|
bitfld.long 0x0C 15. " IRAMA ,Abort occurred due to an iRAMa protection violation" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " IRAMB ,Abort occurred due to an iRAMb protection violation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " IRAMC ,Abort occurred due to an iRAMc protection violation" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " IRAMD ,Abort occurred due to an iRAMd protection violation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " INV_IRAM ,Abort occurred due to an access to invalid iRAM address space" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " PPSB ,Abort occurred due to a PPSB protection violation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " APB ,Abort occurred due to an APB protection violation" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " AHB ,Abort occurred due to an AHB protection violation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " CACHE ,Abort occurred due to a Cache protection violation" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " PROTECTION ,TRUE for any protection violation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ALIGN ,TRUE for abort caused by Misalignment" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " BADSIZE ,TRUE for abort caused by Bad Size" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " WRITE ,Aborted transaction was a Write" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " DATA ,Aborted transaction was a Data access" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " SIZE ,Aborted transaction Request Size" "Byte abort,Hword abort,Word abort,?..."
|
|
textline " "
|
|
line.long 0x10 "ARBITRATION_COP_ABORT_ADDR_0,CPU Abort Address Register"
|
|
line.long 0x14 "ARBITRATION_COP_ABORT_INFO_0,COP Abort Info Register"
|
|
bitfld.long 0x14 15. " IRAMA ,Abort occurred due to an iRAMa protection violation" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " IRAMB ,Abort occurred due to an iRAMb protection violation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " IRAMC ,Abort occurred due to an iRAMc protection violation" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " PPSB ,Abort occurred due to a PPSB protection violation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " APB ,Abort occurred due to an APB protection violation" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " AHB ,Abort occurred due to an AHB protection violation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " CACHE ,Abort occurred due to a Cache protection violation" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " PROTECTION ,TRUE for any protection violation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " ALIGN ,TRUE for abort caused by Misalignment" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " BADSIZE ,TRUE for abort caused by Bad Size" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " WRITE ,Aborted transaction was a Write" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " DATA ,Aborted transaction was a Data access" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--1. " SIZE ,Aborted transaction Request Size" "Byte abort,Hword abort,Word abort,"
|
|
textline " "
|
|
group.long 0x110++0x07
|
|
line.long 0x00 "AHB_SPARE_REG_0,AHB Spare Register Bits"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " AHB_SPARE_REG ,AHB Spare Register"
|
|
bitfld.long 0x00 0.--4. " CSITE_PADMACRO_TRIM_SEL ,Trimmer select register for CoreSight clock pad macro" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
line.long 0x04 "XBAR_SPARE_REG_0,XBAR Spare Register Bits"
|
|
sif !cpuis("TEGRAX1")
|
|
hexmask.long.tbyte 0x04 11.--31. 1. " UNUSED ,XBAR Diagnostic Register Spare Bits"
|
|
textline " "
|
|
else
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " UNUSED ,XBAR Diagnostic Register Spare Bits"
|
|
bitfld.long 0x04 11. " DISABLE_XBAR_ABORT_EXTENSION ,XBAR Diagnostic Register to disable one clock extension of u_abort" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 10. " DISABLE_COP_BYTE_WR ,XBAR Diagnostic Register to disable COP byte writes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " DISABLE_XUSB_DEV_BYTE_WR ,XBAR Diagnostic Register to disable XUSB dev byte writes" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " DISABLE_XUSB_HOST_BYTE_WR ,XBAR Diagnostic Register to disable XUSB host byte writes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DISABLE_SDMMC_BYTE_WR ,XBAR Diagnostic Register to disable SDMMC byte writes" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DISABLE_XBAR_APB_BYTE_WR ,XBAR Diagnostic Register to disable byte writes to APB slaves" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " MASK_PEND_IRAM_REQ ,XBAR Diagnostic Register to mask pending IRAM request while arbitration" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " KILL_NEXT_REQ_ON_ABORT_UCQ ,XBAR Diagnostic Register to kill next request on ABORT from UCQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " KILL_NEXT_REQ_ON_ABORT_AHB ,XBAR Diagnostic Register to kill next request on ABORT from AHB Bridge" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " KILL_NEXT_REQ_ON_ABORT_VCP2 ,XBAR Diagnostic Register to kill next request on ABORT from VCP2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " KILL_NEXT_REQ_ON_ABORT_COP ,XBAR Diagnostic Register to kill next request on ABORT from COP" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " KILL_NEXT_REQ_ON_ABORT_APC ,XBAR Diagnostic Register to kill next request on ABORT from APC" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x120++0x0B
|
|
line.long 0x00 "AVPC_MCCIF_FIFOCTRL_0,Memory Client Interface FIFO Control and Clock Gating Control Register"
|
|
bitfld.long 0x00 20. " AVPC_RCLK_OVR_MODE ,Avpc rclk override mode" "Legacy,On"
|
|
bitfld.long 0x00 19. " AVPC_WCLK_OVR_MODE ,Avcp wclk override mode" "Legacy,On"
|
|
textline " "
|
|
bitfld.long 0x00 18. " AVPC_CCLK_OVERRIDE ,Avpc cclk override" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " AVPC_RCLK_OVERRIDE ,Avpc rclk override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " AVPC_WCLK_OVERRIDE ,Avpc wclk override" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " AVPC_MCCIF_RDCL_RDFAST ,Avpc mccif rdcl rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AVPC_MCCIF_WRMC_CLLE2X ,Avpc mccif wrmc clle2x" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AVPC_MCCIF_RDMC_RDFAST ,Avpc mccif rdmc rdfast" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AVPC_MCCIF_WRCL_MCLE2X ,Avpc mccif wrcl mcle2x" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "TIMEOUT_WCOAL_AVPC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " AVPCARM7W_WCOAL_TMVAL ,Avpcarm7w wcoal tmval"
|
|
line.long 0x08 "AHB_MPCORELP_MCCIF_FIFOCTRL_0 ,Memory Client Interface FIFO Control and Clock Gating Control Register"
|
|
bitfld.long 0x08 20. " SYS_REGS_MPCORELP_RCLK_OVR_MODE ,Sys regs mpcorelp rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x08 19. " SYS_REGS_MPCORELP_WCLK_OVR_MODE ,Sys regs mpcorelp wclk ovr mode" "Legacy,On"
|
|
textline " "
|
|
bitfld.long 0x08 18. " SYS_REGS_MPCORELP_CCLK_OVERRIDE ,Sys regs mpcorelp cclk override" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " SYS_REGS_MPCORELP_RCLK_OVERRIDE ,Sys regs mpcorelp rclk override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " SYS_REGS_MPCORELP_WCLK_OVERRIDE ,Sys regs mpcorelp wclk override" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("TEGRAX1")
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "AHB_MPCORE_MCCIF_FIFOCTRL_0,Memory Client Interface FIFO Control and Clock Gating Control Register"
|
|
bitfld.long 0x00 20. " SYS_REGS_MPCORE_RCLK_OVR_MODE ,Sys regs mpcore rclk ovr mode" "Legacy,On"
|
|
bitfld.long 0x00 19. " SYS_REGS_MPCORE_WCLK_OVR_MODE ,Sys regs mpcore wclk ovr mode" "Legacy,On"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SYS_REGS_MPCORE_CCLK_OVERRIDE ,Sys regs mpcore cclk override" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SYS_REGS_MPCORE_RCLK_OVERRIDE ,Sys regs mpcore rclk override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SYS_REGS_MPCORE_WCLK_OVERRIDE ,Sys regs mpcore wclk override" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "APB Controller"
|
|
base ad:0x70000000
|
|
width 17.
|
|
tree "JTAG Configuration"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CONFIG_CTL_0,Configuration Control Register"
|
|
bitfld.long 0x00 7. " TBE ,Enable RTCK Daisy chaining" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " JTAG ,Enable JTAG DBGEN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XBAR_SO_DEFAULT ,Default SO bit for non-CPU XBAR clients" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CPU_XBAR_SO_ENABLE ,Enable CPU SO bit to propagate to XBAR" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PINMUX_GLOBAL_0_0,Global Pinmux Control Register"
|
|
bitfld.long 0x00 0. " CLAMP_INPUTS_WHEN_TRISTATED ,Clamp inputs when tristated" "Disabled,Enabled"
|
|
tree.end
|
|
width 26.
|
|
tree "PULL_UP/PULL_DOWN Control"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PP_PULLUPDOWN_REG_C_0,Apb Misc PP Pull up/down Reg C 0"
|
|
bitfld.long 0x00 30.--31. " XM2C_PU_PD ,Xm2c pull up/pull down" "Normal,Pull_Down,Pull_Up,"
|
|
bitfld.long 0x00 28.--29. " XM2D_PU_PD ,Xm2d pull up/pull down" "Normal,Pull_Down,Pull_Up,"
|
|
bitfld.long 0x00 26.--27. " DDRC_PU_PD ,Ddrc pull up/pull down" "Normal,Pull_Down,Pull_Up,"
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "SC1X_PADS_VIP_VCLKCTRL_0,VCLK Control Register"
|
|
bitfld.long 0x00 1. " INVERSION ,VCLK invert enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IE ,VCLK input enable" "Disabled,Enabled"
|
|
rgroup.long 0x804++0x03
|
|
line.long 0x00 "GP_HIDREV_0,Chip ID Revision Register"
|
|
bitfld.long 0x00 16.--19. " MINORREV ,Chip ID minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHIPID ,Chip ID"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MAJORREV ,Chip ID major revision" "Emulation,A01,?..."
|
|
bitfld.long 0x00 0.--3. " HIDFAM ,Chip ID family register" "GPU,Handheld,Br_Chips,Crush,Mcp,CK,Vaio,Handheld_Soc,?..."
|
|
tree.end
|
|
width 26.
|
|
tree "Pad Control"
|
|
group.long 0x868++0x03
|
|
line.long 0x00 "AOCFG1PADCTRL_0,AOCFG1 Pad Control Register"
|
|
bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,AOCFG1 Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,AOCFG1 Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 20.--24. " CAL_DRVUP ,AOCFG1 Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12.--16. " CAL_DRVDN ,AOCFG1 Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 3. " SCHMT_EN ,AOCFG1 data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,AOCFG1 data pins high speed mode enable" "Disabled,Enabled"
|
|
group.long 0x86C++0x03
|
|
line.long 0x00 "AOCFG2PADCTRL_0,AOCFG2 Pad Control Register"
|
|
bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,AOCFG2 Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,AOCFG2 Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 20.--24. " CAL_DRVUP ,AOCFG2 Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 12.--16. " CAL_DRVDN ,AOCFG2 Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 3. " SCHMT_EN ,AOCFG2 data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,AOCFG2 data pins high speed mode enable" "Disabled,Enabled"
|
|
group.long 0x870++0x03
|
|
line.long 0x00 "ATCFG1PADCTRL_0,ATCFG1 Pad Control Register"
|
|
bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,AOCFG1 Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,AOCFG1 Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 19.--23. " CAL_DRVUP ,AOCFG1 Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14.--18. " CAL_DRVDN ,AOCFG1 Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DRV_TYPE ,AOCFG1 Driver Type" "0,1,2,3"
|
|
bitfld.long 0x00 3. " SCHMT_EN ,ATCFG1 data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,ATCFG1 data pins high speed mode enable" "Disabled,Enabled"
|
|
group.long 0x874++0x03
|
|
line.long 0x00 "ATCFG2PADCTRL_0,ATCFG1 Pad Control Register"
|
|
bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,AOCFG2 Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,AOCFG2 Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 19.--23. " CAL_DRVUP ,AOCFG2 Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14.--18. " CAL_DRVDN ,AOCFG2 Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DRV_TYPE ,AOCFG2 Driver Type" "0,1,2,3"
|
|
bitfld.long 0x00 3. " SCHMT_EN ,ATCFG2 data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,ATCFG2 data pins high speed mode enable" "Disabled,Enabled"
|
|
group.long 0x878++0x03
|
|
line.long 0x00 "ATCFG3PADCTRL_0,ATCFG1 Pad Control Register"
|
|
bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,AOCFG3 Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,AOCFG3 Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 19.--23. " CAL_DRVUP ,AOCFG3 Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14.--18. " CAL_DRVDN ,AOCFG3 Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DRV_TYPE ,AOCFG3 Driver Type" "0,1,2,3"
|
|
bitfld.long 0x00 3. " SCHMT_EN ,ATCFG3 data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,ATCFG3 data pins high speed mode enable" "Disabled,Enabled"
|
|
group.long 0x87C++0x03
|
|
line.long 0x00 "ATCFG4PADCTRL_0,ATCFG1 Pad Control Register"
|
|
bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,AOCFG4 Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,AOCFG4 Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
textline " "
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bitfld.long 0x00 19.--23. " CAL_DRVUP ,AOCFG4 Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 14.--18. " CAL_DRVDN ,AOCFG4 Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 6.--7. " DRV_TYPE ,AOCFG4 Driver Type" "0,1,2,3"
|
|
bitfld.long 0x00 3. " SCHMT_EN ,ATCFG4 data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,ATCFG4 data pins high speed mode enable" "Disabled,Enabled"
|
|
group.long 0x880++0x03
|
|
line.long 0x00 "ATCFG5PADCTRL_0,ATCFG1 Pad Control Register"
|
|
bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,AOCFG5 Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,AOCFG5 Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
textline " "
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hexmask.long.byte 0x00 20.--26. 1. " CAL_DRVUP ,AOCFG5 Driver Output Pull-Up drive strength code"
|
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hexmask.long.byte 0x00 12.--18. 1. " CAL_DRVDN ,AOCFG5 Driver Output Pull-Down drive strength code"
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textline " "
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bitfld.long 0x00 6.--7. " DRV_TYPE ,AOCFG5 Driver Type" "0,1,2,3"
|
|
bitfld.long 0x00 3. " SCHMT_EN ,ATCFG5 data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,ATCFG5 data pins high speed mode enable" "Disabled,Enabled"
|
|
group.long 0x884++0x03
|
|
line.long 0x00 "CDEV1CFGCFGPADCTRL_0,CDEV1CFG Pad Control Register"
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bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,CDEV1CFG Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
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bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,CDEV1CFG Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 20.--24. " CAL_DRVUP ,CDEV1CFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 12.--16. " CAL_DRVDN ,CDEV1CFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 3. " SCHMT_EN ,CDEV1CFG data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,CDEV1CFG data pins high speed mode enable" "Disabled,Enabled"
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group.long 0x888++0x03
|
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line.long 0x00 "CDEV2CFGCFGPADCTRL_0,CDEV2CFG Pad Control Register"
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bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,CDEV2CFG Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
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bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,CDEV2CFG Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 20.--24. " CAL_DRVUP ,CDEV2CFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 12.--16. " CAL_DRVDN ,CDEV2CFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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bitfld.long 0x00 3. " SCHMT_EN ,CDEV2CFG data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,CDEV2CFG data pins high speed mode enable" "Disabled,Enabled"
|
|
group.long 0x890++0x03
|
|
line.long 0x00 "ATCFG1PADCTRL_0,ATCFG1 Pad Control Register"
|
|
bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,AOCFG1 Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
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bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,AOCFG1 Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 20.--24. " CAL_DRVUP ,AOCFG1 Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 12.--16. " CAL_DRVDN ,CCFG2RTMC AOCFG1 Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
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bitfld.long 0x00 6.--7. " DRV_TYPE ,AOCFG1 Driver Type" "0,1,2,3"
|
|
bitfld.long 0x00 3. " SCHMT_EN ,ATCFG1 data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,ATCFG1 data pins high speed mode enable" "Disabled,Enabled"
|
|
group.long 0x894++0x03
|
|
line.long 0x00 "ATCFG2PADCTRL_0,ATCFG2 Pad Control Register"
|
|
bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,AOCFG2 Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,AOCFG2 Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 20.--24. " CAL_DRVUP ,AOCFG2 Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 12.--16. " CAL_DRVDN ,CCFG2RTMC AOCFG2 Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
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bitfld.long 0x00 6.--7. " DRV_TYPE ,AOCFG2 Driver Type" "0,1,2,3"
|
|
bitfld.long 0x00 3. " SCHMT_EN ,ATCFG2 data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,ATCFG2 data pins high speed mode enable" "Disabled,Enabled"
|
|
group.long 0x898++0x03
|
|
line.long 0x00 "ATCFG3PADCTRL_0,ATCFG3 Pad Control Register"
|
|
bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,AOCFG3 Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,AOCFG3 Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 20.--24. " CAL_DRVUP ,AOCFG3 Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 12.--16. " CAL_DRVDN ,CCFG2RTMC AOCFG3 Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
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bitfld.long 0x00 6.--7. " DRV_TYPE ,AOCFG3 Driver Type" "0,1,2,3"
|
|
bitfld.long 0x00 3. " SCHMT_EN ,ATCFG3 data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,ATCFG3 data pins high speed mode enable" "Disabled,Enabled"
|
|
group.long 0x89C++0x03
|
|
line.long 0x00 "ATCFG4PADCTRL_0,ATCFG4 Pad Control Register"
|
|
bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,AOCFG4 Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,AOCFG4 Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 20.--24. " CAL_DRVUP ,AOCFG4 Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 12.--16. " CAL_DRVDN ,CCFG2RTMC AOCFG4 Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
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bitfld.long 0x00 6.--7. " DRV_TYPE ,AOCFG4 Driver Type" "0,1,2,3"
|
|
bitfld.long 0x00 3. " SCHMT_EN ,ATCFG4 data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,ATCFG4 data pins high speed mode enable" "Disabled,Enabled"
|
|
group.long 0x8A0++0x03
|
|
line.long 0x00 "ATCFG5PADCTRL_0,ATCFG5 Pad Control Register"
|
|
bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,AOCFG5 Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,AOCFG5 Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 20.--24. " CAL_DRVUP ,AOCFG5 Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 12.--16. " CAL_DRVDN ,CCFG2RTMC AOCFG5 Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 6.--7. " DRV_TYPE ,AOCFG5 Driver Type" "0,1,2,3"
|
|
bitfld.long 0x00 3. " SCHMT_EN ,ATCFG5 data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,ATCFG5 data pins high speed mode enable" "Disabled,Enabled"
|
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group.long 0x8A0++0x03
|
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line.long 0x00 "DBGCFGPADCTRL_0,DBGCFG Pad Control Register"
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bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,DBGCFG Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
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bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,DBGCFG Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
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bitfld.long 0x00 20.--24. " CAL_DRVUP ,DBGCFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 12.--16. " CAL_DRVDN ,DBGCFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 3. " SCHMT_EN ,DBGCFG data pins Schmitt enable" "Disabled,Enabled"
|
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bitfld.long 0x00 2. " HSM_EN ,DBGCFG data pins high speed mode enable" "Disabled,Enabled"
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group.long 0x8B0++0x0F
|
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line.long 0x00 "SDIO3CFGPADCTRL_0,SDIO3CFG Pad Control Register"
|
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bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,Maps to most significant bit of DRVDN[18:17]" "0,1,2,3"
|
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bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,Maps to most significant bit of DRVUP[26:25]" "0,1,2,3"
|
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hexmask.long.byte 0x00 20.--26. 1. " CAL_DRVUP ,3.3V 50 ohm driver for removable SD card"
|
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hexmask.long.byte 0x00 12.--18. 1. " CAL_DRVDN ,3.3V 50 ohm driver for removable SD card"
|
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textline " "
|
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bitfld.long 0x00 3. " SCHMT_EN ,SDIO3CFG data pins Schmitt enable" "Disabled,Enabled"
|
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bitfld.long 0x00 2. " HSM_EN ,SDIO3CFG data pins high speed mode enable" "Disabled,Enabled"
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line.long 0x04 "SPICFGPADCTRL_0 ,SPICFG Pad Control Register"
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bitfld.long 0x04 30.--31. " CAL_DRVUP_SLWF ,SPICFG Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
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bitfld.long 0x04 28.--29. " CAL_DRVDN_SLWR ,SPICFG Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
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bitfld.long 0x04 20.--24. " CAL_DRVUP ,SPICFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 12.--16. " CAL_DRVDN ,PICFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
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bitfld.long 0x04 3. " SCHMT_EN ,SPICFG data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " HSM_EN ,SPICFG data pins high-speed mode enable" "Disabled,Enabled"
|
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line.long 0x08 "UAACFGPADCTRL_0,UAACFG Pad Control Register"
|
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bitfld.long 0x08 30.--31. " CAL_DRVUP_SLWF ,UAACFG Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
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bitfld.long 0x08 28.--29. " CAL_DRVDN_SLWR ,UAACFG Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
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bitfld.long 0x08 20.--24. " CAL_DRVUP ,UAACFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 12.--16. " CAL_DRVDN ,UAACFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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textline " "
|
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bitfld.long 0x08 3. " SCHMT_EN ,UAACFG data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " HSM_EN ,UAACFG data pins high speed mode enable" "Disabled,Enabled"
|
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line.long 0x0C "UABCFGPADCTRL_0,UABCFG Pad Control Register"
|
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bitfld.long 0x0C 30.--31. " CAL_DRVUP_SLWF ,UABCFG Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
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bitfld.long 0x0C 28.--29. " CAL_DRVDN_SLWR ,UABCFG Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x0C 20.--24. " CAL_DRVUP ,UABCFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 12.--16. " CAL_DRVDN ,UABCFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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textline " "
|
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bitfld.long 0x0C 3. " SCHMT_EN ,UABCFG data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " HSM_EN ,UABCFG data pins high speed mode enable" "Disabled,Enabled"
|
|
group.long 0x8C0++0x07
|
|
line.long 0x00 "UART2CFGPADCTRL_0,UART2CFG Pad Control Register"
|
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bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,UART2CFG Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,UART2CFG Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 20.--24. " CAL_DRVUP ,UART2CFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 12.--16. " CAL_DRVDN ,UART2CFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
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bitfld.long 0x00 3. " SCHMT_EN ,UART2CFG data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,UART2CFG data pins high speed mode enable" "Disabled,Enabled"
|
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line.long 0x04 "UART3CFGPADCTRL_0,UART3CFG Pad Control Register"
|
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bitfld.long 0x04 30.--31. " CAL_DRVUP_SLWF ,UART3CFG Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x04 28.--29. " CAL_DRVDN_SLWR ,UART3CFG Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x04 20.--24. " CAL_DRVUP ,UART3CFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 12.--16. " CAL_DRVDN ,UART3CFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
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bitfld.long 0x04 3. " SCHMT_EN ,UART3CFG data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " HSM_EN ,UART3CFG data pins high speed mode enable" "Disabled,Enabled"
|
|
group.long 0x8EC++0x03
|
|
line.long 0x00 "SDIO1CFGPADCTRL_0,SDIO1CFG Pad Control Register"
|
|
bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,Maps to MSB of DRVDN[18:17]" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,Maps to MSB of DRVUP[26:25]" "0,1,2,3"
|
|
hexmask.long.byte 0x00 20.--26. 1. " CAL_DRVUP ,1.8V 50 ohm driver for wifi SDIO card"
|
|
hexmask.long.byte 0x00 12.--18. 1. " CAL_DRVDN ,1.8V 50 ohm driver for wifi SDIO card"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMT_EN ,SDIO1CFG data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,SDIO1CFG data pins high speed mode enable" "Disabled,Enabled"
|
|
group.long 0x8FC++0x07
|
|
line.long 0x00 "DDCCFGPADCTRL_0,CRTCFG and DDCCFG Pad Control Registers"
|
|
bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,DDCCFG Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,DDCCFG Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 20.--24. " CAL_DRVUP ,DDCCFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--16. " CAL_DRVDN ,DDCCFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMT_EN ,DDCCFG Data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,DDCCFG Data pins high speed mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "GMACFGPADCTRL_0,GMACFG Pad Control Register"
|
|
bitfld.long 0x04 30.--31. " CAL_DRVUP_SLWF ,Maps to MSB of DRVDN" "0,1,2,3"
|
|
bitfld.long 0x04 28.--29. " CAL_DRVDN_SLWR ,Maps to MSB of DRVUP" "0,1,2,3"
|
|
bitfld.long 0x04 20.--24. " CAL_DRVUP ,1.8V 50 ohm driver for eMMC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 14.--18. " CAL_DRVDN ,1.8V 50 ohm driver for eMMC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
textline " "
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bitfld.long 0x04 6.--7. " DRV_TYPE ,GMACFG Driver Type" "66-100 Ohm,33-50 Ohm,?..."
|
|
bitfld.long 0x04 3. " SCHMT_EN ,GMACFG Data pins Schmitt enable" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 2. " HSM_EN ,GMACFG Data pins high speed mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " GMACFG_E_PREEMP ,GMACFG Pre-emphasis enable" "Disabled,Enabled"
|
|
group.long 0x910++0x0F
|
|
line.long 0x00 "GMECFGPADCTRL_0,GMECFG Pad Control Register"
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bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,GMECFG Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
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bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,GMECFG Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
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|
bitfld.long 0x00 19.--23. " CAL_DRVUP ,GMECFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 14.--18. " CAL_DRVDN ,GMECFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
textline " "
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|
bitfld.long 0x00 3. " SCHMT_EN ,GMECFG Data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,GMECFG Data pins high speed mode enable" "Disabled,Enabled"
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|
line.long 0x04 "GMFCFGPADCTRL_0,GMFCFG Pad Control Register"
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|
bitfld.long 0x04 30.--31. " CAL_DRVUP_SLWF ,GMFCFG Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x04 28.--29. " CAL_DRVDN_SLWR ,GMFCFG Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x04 19.--23. " CAL_DRVUP ,GMFCFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 14.--18. " CAL_DRVDN ,GMFCFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x04 3. " SCHMT_EN ,GMFCFG Data pins Schmitt enable" "disabled,Enabled"
|
|
bitfld.long 0x04 2. " HSM_EN ,GMFCFG Data pins high speed mode enable" "Disabled,Enabled"
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|
line.long 0x08 "GMGCFGPADCTRL_0,GMGCFG Pad Control Register"
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|
bitfld.long 0x08 30.--31. " CAL_DRVUP_SLWF ,GMGCFG Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x08 28.--29. " CAL_DRVDN_SLWR ,GMGCFG Driver Output Pull-Down drive strength code" "0,1,2,3"
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|
bitfld.long 0x08 19.--23. " CAL_DRVUP ,GMGCFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 14.--18. " CAL_DRVDN ,GMGCFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x08 3. " SCHMT_EN ,GMGCFG Data pins Schmitt enable" "Disabled,Enabled"
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|
bitfld.long 0x08 2. " HSM_EN ,GMGCFG Data pins high speed mode enable" "Disabled,Enabled"
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|
line.long 0x0C "GMHCFGPADCTRL_0,GMHCFG Pad Control Register"
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bitfld.long 0x0C 30.--31. " CAL_DRVUP_SLWF ,GMHCFG Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
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bitfld.long 0x0C 28.--29. " CAL_DRVDN_SLWR ,GMHCFG Driver Output Pull-Down drive strength code" "0,1,2,3"
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bitfld.long 0x0C 19.--23. " CAL_DRVUP ,GMHCFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 14.--18. " CAL_DRVDN ,GMHCFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x0C 3. " SCHMT_EN ,GMHCFG Data pins Schmitt enable" "Disabled,Enabled"
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bitfld.long 0x0C 2. " HSM_EN ,GMHCFG Data pins high speed mode enable" "Disabled,Enabled"
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group.long 0x920++0x0F
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line.long 0x00 "OWRCFGPADCTRL_0,OWRCFG Pad Control Register"
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bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,OWRCFG Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
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bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,OWRCFG Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
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bitfld.long 0x00 20.--24. " CAL_DRVUP ,OWRCFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 12.--16. " CAL_DRVDN ,OWRCFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 3. " SCHMT_EN ,OWRCFG Data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,OWRCFG Data pins high speed mode enable" "Disabled,Enabled"
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|
line.long 0x04 "UADCFGPADCTRL_0,UDACFG Pad Control Register"
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bitfld.long 0x04 30.--31. " CAL_DRVUP_SLWF ,UDACFG Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
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bitfld.long 0x04 28.--29. " CAL_DRVDN_SLWR ,UDACFG Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
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bitfld.long 0x04 20.--24. " CAL_DRVUP ,UDACFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 12.--16. " CAL_DRVDN ,UDACFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
textline " "
|
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bitfld.long 0x04 3. " SCHMT_EN ,UDACFG Data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " HSM_EN ,UDACFG Data pins high speed mode enable" "Disabled,Enabled"
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|
line.long 0x08 "GPVCFGPADCTRL_0,GPV Pad Control Register"
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bitfld.long 0x08 30.--31. " CAL_DRVUP_SLWF ,GPVCFG Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
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bitfld.long 0x08 28.--29. " CAL_DRVDN_SLWR ,GPVCFG Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
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bitfld.long 0x08 20.--24. " CAL_DRVUP ,GPVCFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 12.--16. " CAL_DRVDN ,GPVCFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
textline " "
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bitfld.long 0x08 3. " SCHMT_EN ,GPVCFG data pins Schmitt enable" "Disabled,Enabled"
|
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bitfld.long 0x08 2. " HSM_EN ,GPVCFG data pins high speed mode enable" "Disabled,Enabled"
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line.long 0x0C "DEV3CFGPADCTRL_0,DEV3CFG Pad Control Register"
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bitfld.long 0x0C 30.--31. " CAL_DRVUP_SLWF ,Dev3cfg Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
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bitfld.long 0x0C 28.--29. " CAL_DRVDN_SLWR ,DEV3CFG Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
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bitfld.long 0x0C 20.--24. " CAL_DRVUP ,DEV3CFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 12.--16. " CAL_DRVDN ,Dev3cfg Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x0C 3. " SCHMT_EN ,DEV3CFG data pins Schmitt enable" "Disabled,Enabled"
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bitfld.long 0x0C 2. " HSM_EN ,DEV3CFG data pins high speed mode enable" "Disabled,Enabled"
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group.long 0x938++0x03
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line.long 0x00 "CECCFGPADCTRL_0,CECCFG Pad Control Register"
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bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,CECCFG Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
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bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,CECCFG Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
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bitfld.long 0x00 20.--24. " CAL_DRVUP ,CECCFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 12.--16. " CAL_DRVDN ,CECCFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x00 3. " SCHMT_EN ,CECCFG Data pins Schmitt enable" "Disabled,Enabled"
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bitfld.long 0x00 2. " HSM_EN ,CECCFG Data pins high speed mode enable" "Disabled,Enabled"
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group.long 0x994++0x0B
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line.long 0x00 "ATCFG6PADCTRL_0,ATCFG6 Pad Control Register"
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bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,ATCFG6 Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
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bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,ATCFG6 Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
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hexmask.long.byte 0x00 20.--26. 1. " CAL_DRVUP ,ATCFG6 Driver Output Pull-Up drive strength code"
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hexmask.long.byte 0x00 12.--18. 1. " CAL_DRVDN ,ATCFG6 Driver Output Pull-Down drive strength code"
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textline " "
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bitfld.long 0x00 6.--7. " DRV_TYPE ,ATCFG6 Driver type" "0,1,2,3"
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bitfld.long 0x00 3. " SCHMT_EN ,ATCFG6 data pins Schmitt enable" "Disabled,Enabled"
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|
bitfld.long 0x00 2. " HSM_EN ,ATCFG6 data pins high speed mode enable" "Disabled,Enabled"
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line.long 0x04 "DAP5CFGPADCTRL_0,DAP5CFG Pad Control Register"
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bitfld.long 0x04 30.--31. " CAL_DRVUP_SLWF ,Dap5cfg Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
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bitfld.long 0x04 28.--29. " CAL_DRVDN_SLWR ,DAP5CFG Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
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bitfld.long 0x04 20.--24. " CAL_DRVUP ,DAP5CFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 12.--16. " CAL_DRVDN ,DAP5CFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
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bitfld.long 0x04 3. " SCHMT_EN ,DAP5CFG data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " HSM_EN ,DAP5CFG data pins high speed mode enable" "Disabled,Enabled"
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line.long 0x08 "USB_VBUS_EN_CFGPADCTRL_0,USB_VBUS_EN_CFG Pad Control Register"
|
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bitfld.long 0x08 30.--31. " CAL_DRVUP_SLWF ,USB_VBUS_EN_CFG Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
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bitfld.long 0x08 28.--29. " CAL_DRVDN_SLWR ,USB_VBUS_EN_CFG Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
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bitfld.long 0x08 20.--24. " CAL_DRVUP ,USB_VBUS_EN_CFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 12.--16. " CAL_DRVDN ,USB_VBUS_EN_CFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SCHMT_EN ,USB_VBUS_EN_CFG Data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " HSM_EN ,USB_VBUS_EN_CFG Data pins high speed mode enable" "Disabled,Enabled"
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "AOCFG3PADCTRL_0,AOCFG3 Pad Control Register"
|
|
bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,AOCFG3 Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 12.--16. " CAL_DRVDN ,AOCFG3 Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 3. " SCHMT_EN ,AOCFG3 data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,AOCFG3 data pins high speed mode enable" "Disabled,Enabled"
|
|
group.long 0x9B0++0x07
|
|
line.long 0x00 "AOCFG0PADCTRL_0,AOCFG0 Pad Control Register"
|
|
bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,AOCFG0 Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,AOCFG0 Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 20.--24. " CAL_DRVUP ,AOCFG0 Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 12.--16. " CAL_DRVDN ,AOCFG0 Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMT_EN ,AOCFG0 data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,AOCFG0 data pins high speed mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "HVCFG0PADCTRL_0,HVCFG0 Pad Control Register"
|
|
bitfld.long 0x04 28.--29. " CAL_DRVDN_SLWR ,HVCFG0 Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x04 12.--16. " CAL_DRVDN ,HVCFG0 Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 3. " SCHMT_EN ,HVCFG0 data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " HSM_EN ,HVCFG0 data pins high speed mode enable" "Disabled,Enabled"
|
|
group.long 0x9C4++0x07
|
|
line.long 0x00 "SDIO4CFGPADCTRL_0,SDIO4CFG Pad Control Register"
|
|
bitfld.long 0x00 30.--31. " CAL_DRVUP_SLWF ,SDIO4CFG Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " CAL_DRVDN_SLWR ,SDIO4CFG Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x00 20.--24. " CAL_DRVUP ,SDIO4CFG Driver Output Pull-Up drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--16. " CAL_DRVDN ,SDIO4CFG Driver Output Pull-Down drive strength code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCHMT_EN ,SDIO4CFG data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HSM_EN ,SDIO4CFG data pins high speed mode enable" "Disabled,Enabled"
|
|
line.long 0x04 "AOCFG4PADCTRL_0,APB_MISC_GP_AOCFG4PADCTRL_0"
|
|
bitfld.long 0x04 30.--31. " CAL_DRVUP_SLWF ,AOCFG4 Driver Output Falling Edge Slew 2-bit control code" "0,1,2,3"
|
|
bitfld.long 0x04 28.--29. " CAL_DRVDN_SLWR ,AOCFG4 Driver Output Rising Edge Slew 2-bit control code" "0,1,2,3"
|
|
hexmask.long.byte 0x04 20.--26. 1. " CAL_DRVUP ,AOCFG4 Driver Output Pull-Up drive strength code"
|
|
hexmask.long.byte 0x04 12.--18. 1. " CAL_DRVDN ,AOCFG4 AOCFG4 Output Pull-Down drive strength code"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " DRV_TYPE ,AOCFG4 Driver type" "0,1,2,3"
|
|
bitfld.long 0x04 3. " SCHMT_EN ,AOCFG4 data pins Schmitt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " HSM_EN ,AOCFG4 data pins high speed mode enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 23.
|
|
tree "SATA Aux"
|
|
group.long 0x1108++0x0F
|
|
line.long 0x00 "MISC_CNTL_1_0,MISC_CNTL_1 Register"
|
|
bitfld.long 0x00 19. " AUX_RX_IDLE_STATUS_MASK ,Mask the aux_rx_idle_status input to the SATA core to 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " AUX_OR_CORE_IDLE_STATUS_SEL ,Select the rx_idle status from either AUX or CORE for interrupt generation" "Aux,Core"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DEVSLP_OVERRIDE ,Override the DEVSLP output from the SATA core" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DSP_SUPPORT ,Device sleep supported (Set the AHCI's PxDEVSLP.DSP register bit)" "Not supported,Supported"
|
|
bitfld.long 0x00 15. " DESO_SUPPORT ,Capability to enter DevSleep only from slumber link state (Set the AHCI's CAP2.DESO register bit)" "Any state,Slumber link only"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SADM_SUPPORT ,Hardware assertion of the DEVSLP supported (Set the AHCI's CAP2.SADM register bit)" "Not supported,Supported"
|
|
bitfld.long 0x00 13. " SDS_SUPPORT ,Device sleep support (Set the AHCI's CAP2.SAS register bit)" "Not supported,Supported"
|
|
bitfld.long 0x00 12. " RX_STAT_IDLE_MASK ,Mask the rx_stat_idle input to the SATA core to 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " SATA2IPSM_DEVSLP ,SATA link is in DEVSLP" "No,Yes"
|
|
rbitfld.long 0x00 9.--10. " SATA2IPSM_ST ,Indicates whether the SATA link is in partial/slumber modes" "0,1,2,3"
|
|
bitfld.long 0x00 8. " NVA2SATA_OOB_ON_SCONTROL_SPD_WR ,SATA controller will do an OOB sequence when SCONTROL_SPD register is written" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NVA2SATA_OOB_ON_POR ,SATA controllers do an OOB sequence automatically when they come out of reset" "No,Yes"
|
|
rbitfld.long 0x00 5.--6. " L0_RX_IDLE_T_SAX ,L0_RX_IDLE_T value from the SATA controller" "Normal,?..."
|
|
bitfld.long 0x00 3.--4. " L0_RX_IDLE_T_NPG ,Sets the L0_RX_IDLE_T value for the SATA PHY from apb_misc" "Normal,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " L0_RX_IDLE_T_MUX ,Select L0_RX_IDLE_T driving source for SATA PHY" "Sata,Apb_misc"
|
|
bitfld.long 0x00 1. " PMU2SATA_ACCLMTR_TRIG ,External accelerometer trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DEVICE_DIS_SATA0 ,Serial ATA Interface 0 Disable" "No,Yes"
|
|
line.long 0x04 "RX_STAT_INT_0,RX_STAT_INT Register"
|
|
bitfld.long 0x04 8. " SATA_DEVSLP_INT_DISABLE ,SATA DEVSLP interrupt disable" "No,Yes"
|
|
rbitfld.long 0x04 7. " SATA_DEVSLP ,SATA link is in the DEVSLP state" "No,Yes"
|
|
rbitfld.long 0x04 6. " SATA_DEVSLP_INT_STATUS ,DEVSLP interrupt status" "None,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SATA_DEV_ATTEN_INT_DISABLE ,SATA device attention interrupt disable" "No,Yes"
|
|
rbitfld.long 0x04 4. " SATA_DEVICE_ATTENTION ,SATA device attention status" "Cleared,Asserted"
|
|
rbitfld.long 0x04 3. " SATA_DEV_ATTEN_INT_STATUS ,SATA device attention interrupt status from GPIO" "None,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SATA_RX_STAT_INT_DISABLE ,SATA RX_STAT interrupt disable" "No,Yes"
|
|
rbitfld.long 0x04 1. " SATA_L0_RX_STAT_IDLE ,SATA pad L0 rx_stat_idle status" "Active,Idle"
|
|
rbitfld.long 0x04 0. " SATA_RX_STAT_INT_STATUS ,SATA RX_STAT interrupt status from the SATA pad" "None,Pending"
|
|
line.long 0x08 "RX_STAT_SET_0,RX_STAT_SET Register"
|
|
bitfld.long 0x08 2. " SATA_DEVSLP_INT_SET ,SATA DEVSLP interrupt is set" "No effect,Set"
|
|
bitfld.long 0x08 1. " SATA_DEV_ATTEN_INT_SET ,SATA DEV_ATTEN interrupt is set" "No effect,Set"
|
|
bitfld.long 0x08 0. " SATA_RX_STAT_INT_SET ,SATA RX_STAT interrupt is set" "No effect,Set"
|
|
line.long 0x0C "SATA_AUX_RX_STAT_CLR_0,RX_STAT_CLR Register"
|
|
bitfld.long 0x0C 2. " SATA_DEVSLP_INT_CLR ,SATA DEVSLP interrupt is cleared" "No effect,Clear"
|
|
bitfld.long 0x0C 1. " SATA_DEV_ATTEN_INT_CLR ,SATA DEV_ATTEN interrupt is cleared" "No effect,Clear"
|
|
bitfld.long 0x0C 0. " SATA_RX_STAT_INT_CLR ,SATA RX_STAT interrupt is cleared" "No effect,Clear"
|
|
group.long 0x1118++0x1B
|
|
line.long 0x00 "SPARE_CFG0_0,SPARE_CFG0 Register"
|
|
bitfld.long 0x00 14. " MDAT_TIMER_AFTER_PG_VALID ,MDAT timer value is to be loaded in the SATA register space" "Not valid,Valid"
|
|
bitfld.long 0x00 8.--13. " MDAT_TIMER_AFTER_PG ,MDAT timer value to be updated by the SW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " MDAT_TIMER_BEFORE_PG ,MDAT timer value loaded from the SATA register space before SATA is power-gated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SPARE_CFG1_0,SPARE_CFG1 Register"
|
|
line.long 0x08 "PAD_PLL_CTRL_0_0,SATA PAD PLL Control Register"
|
|
bitfld.long 0x08 28.--29. " PLL1_REFCLK_NDIV ,PLL1_REFCLK_NDIV" "0,1,2,3"
|
|
rbitfld.long 0x08 27. " PLL1_LOCKDET ,PLL1_LOCKDET" "0,1"
|
|
bitfld.long 0x08 24. " PLL1_MODE ,PLL1_MODE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 20.--21. " PLL0_REFCLK_NDIV ,Select feedback divider for PLL" "0,1,2,3"
|
|
rbitfld.long 0x08 19. " PLL0_LOCKDET ,PLL is locked within the desired resolution" "Not_locked,Locked"
|
|
bitfld.long 0x08 16. " PLL0_MODE ,PLL0_MODE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " REFCLK_SEL ,Reference clock" "Internal CML,Internal CMOS,External,?..."
|
|
bitfld.long 0x08 11. " REFCLK_TERM100 ,REFCLK_TERM100" "0,1"
|
|
bitfld.long 0x08 9. " PLL_CKBUFPD_OVRD ,PLL_CKBUFPD_OVRD" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 8. " PLL_CKBUFPD_M ,PLL_CKBUFPD_M" "0,1"
|
|
bitfld.long 0x08 7. " PLL_CKBUFPD_BL ,PLL_CKBUFPD_BL" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 6. " PLL_CKBUFPD_BR ,PLL_CKBUFPD_BR" "0,1"
|
|
bitfld.long 0x08 5. " PLL_CKBUFPD_TL ,PLL_CKBUFPD_TL" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PLL_CKBUFPD_TR ,PLL_CKBUFPD_TR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PLL_EMULATION_RSTN ,Digital reset for clock divider during emulation mode" "Assert,Deassert"
|
|
line.long 0x0C "PAD_PLL_CTRL_1_0,Sata_Aux_Pad_Pll_Ctrl_1_0"
|
|
bitfld.long 0x0C 20.--23. " PLL1_CP_CNTL ,Charge-pump current control for PLL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 16.--19. " PLL0_CP_CNTL ,Charge-pump current control for PLL0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 15. " PLL_BYPASS_EN ,Bypass PLL serial output clocks with input reference clock" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " PLL_EMULATION_ON ,Enable clock bypass for emulation mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " TCLKOUT_EN ,Enable test clock output pads" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8.--11. " TCLKOUT_SEL ,Select internal clock source to bring out through the TSTCLKP/N pads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " XDIGCLK4P5_EN ,Enable XDIGCLK4P5 clock output to core" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " REFCLKBUF_EN ,Enable REFCLKBUF clock output to core" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " TXCLKREF_EN ,Enable TXCLKREF clock to core" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " TXCLKREF_SEL ,Select the post divider for TXCLKREF clock" "0,1"
|
|
bitfld.long 0x0C 3. " XDIGCLK_EN ,Enable XDIGCLK output clock" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--2. " XDIGCLK_SEL ,Select the output frequency of XDIGCLK" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "PAD_PLL_CTRL_2_0,Sata_Aux_Pad_Pll_Ctrl_2_0"
|
|
bitfld.long 0x10 28.--31. " PLL_TEMP_CNTL ,PLL_TEMP_CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 18.--23. " PLL_BW_CNTL ,PLL_BW_CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x10 16.--17. " PLL_BGAP_CNTL ,BGAP_CNTL" "0,1,2,3"
|
|
textline " "
|
|
rbitfld.long 0x10 15. " RCAL_DONE ,Status signal to indicate calibration status" "Done,Not_done"
|
|
bitfld.long 0x10 14. " RCAL_RESET ,Reset the resistor calibration logic" "No reset,Reset"
|
|
rbitfld.long 0x10 8.--12. " RCAL_VAL ,Setting of current active resistor calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x10 7. " RCAL_BYPASS ,Bypass resistor calibration logic" "Disabled,Enabled"
|
|
bitfld.long 0x10 0.--4. " RCAL_CODE ,Sets resistor calibration code when logic is bypassed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "PAD_PLL_CTRL_3_0,Sata_Aux_Pad_Pll_Ctrl_3_0"
|
|
hexmask.long.word 0x14 0.--11. 1. " PLL_MISC_CNTL ,Pll Misc Cntl"
|
|
line.long 0x18 "PAD_L0_AUX_CTRL_0_0,Sata_Aux_Pad_L0_Aux_Ctrl_0_0"
|
|
rbitfld.long 0x18 9. " AUX_RX_IDLE_STATUS ,AUX_RX_IDLE status" "0,1"
|
|
rbitfld.long 0x18 8. " AUX_TX_RDET_STATUS ,AUX_TX_RDET status" "0,1"
|
|
bitfld.long 0x18 5. " AUX_HOLD_EN ,AUX_HOLD_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " AUX_RX_IDLE_MODE ,AUX_RX_IDLE MODE" "0,1"
|
|
bitfld.long 0x18 3. " AUX_RX_IDLE_EN ,AUX_RX_IDLE enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " AUX_RX_TERM_EN ,AUX_RX_TERM enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " AUX_TX_RDET_EN ,AUX_TX_RDET enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " AUX_TX_TERM_EN ,AUX_TX_TERM enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 27.
|
|
tree "DAC/DAP"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "DAP_CTRL_SEL_0,DAP Control Register"
|
|
bitfld.long 0x00 31. " DAP_MS_SEL ,Put a particular DAP in Slave/Master mode (when two or more DAP's are in bypass mode)" "Slave,Master"
|
|
bitfld.long 0x00 30. " DAP_SDATA1_TX_RX ,Program sdata1 in TX/RX mode (when two or more DAP's are in bypass mode)" "TX,RX"
|
|
bitfld.long 0x00 29. " DAP_SDATA2_RX_TX ,Program sdata2 in TX/RX mode (when two or more DAP's are in bypass mode)" "RX,TX"
|
|
bitfld.long 0x00 0.--4. " DAP_CTRL_SEL ,DAP selection bits to select one of the three DACs or one of the five DAPs" "DAC1,DAC2,DAC3,,,,,,,,,,,,,DAP1,DAP2,DAP3,DAP4,DAP5,?..."
|
|
group.long 0xC04++0x03
|
|
line.long 0x00 "DAP_CTRL_SEL_0,DAP Control Register"
|
|
bitfld.long 0x00 31. " DAP_MS_SEL ,Put a particular DAP in Slave/Master mode (when two or more DAP's are in bypass mode)" "Slave,Master"
|
|
bitfld.long 0x00 30. " DAP_SDATA1_TX_RX ,Program sdata1 in TX/RX mode (when two or more DAP's are in bypass mode)" "TX,RX"
|
|
bitfld.long 0x00 29. " DAP_SDATA2_RX_TX ,Program sdata2 in TX/RX mode (when two or more DAP's are in bypass mode)" "RX,TX"
|
|
bitfld.long 0x00 0.--4. " DAP_CTRL_SEL ,DAP selection bits to select one of the three DACs or one of the five DAPs" "DAC1,DAC2,DAC3,,,,,,,,,,,,,DAP1,DAP2,DAP3,DAP4,DAP5,?..."
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "DAP_CTRL_SEL_0,DAP Control Register"
|
|
bitfld.long 0x00 31. " DAP_MS_SEL ,Put a particular DAP in Slave/Master mode (when two or more DAP's are in bypass mode)" "Slave,Master"
|
|
bitfld.long 0x00 30. " DAP_SDATA1_TX_RX ,Program sdata1 in TX/RX mode (when two or more DAP's are in bypass mode)" "TX,RX"
|
|
bitfld.long 0x00 29. " DAP_SDATA2_RX_TX ,Program sdata2 in TX/RX mode (when two or more DAP's are in bypass mode)" "RX,TX"
|
|
bitfld.long 0x00 0.--4. " DAP_CTRL_SEL ,DAP selection bits to select one of the three DACs or one of the five DAPs" "DAC1,DAC2,DAC3,,,,,,,,,,,,,DAP1,DAP2,DAP3,DAP4,DAP5,?..."
|
|
group.long 0xC0C++0x03
|
|
line.long 0x00 "DAP_CTRL_SEL_0,DAP Control Register"
|
|
bitfld.long 0x00 31. " DAP_MS_SEL ,Put a particular DAP in Slave/Master mode (when two or more DAP's are in bypass mode)" "Slave,Master"
|
|
bitfld.long 0x00 30. " DAP_SDATA1_TX_RX ,Program sdata1 in TX/RX mode (when two or more DAP's are in bypass mode)" "TX,RX"
|
|
bitfld.long 0x00 29. " DAP_SDATA2_RX_TX ,Program sdata2 in TX/RX mode (when two or more DAP's are in bypass mode)" "RX,TX"
|
|
bitfld.long 0x00 0.--4. " DAP_CTRL_SEL ,DAP selection bits to select one of the three DACs or one of the five DAPs" "DAC1,DAC2,DAC3,,,,,,,,,,,,,DAP1,DAP2,DAP3,DAP4,DAP5,?..."
|
|
group.long 0xC10++0x03
|
|
line.long 0x00 "DAP_CTRL_SEL_0,DAP Control Register"
|
|
bitfld.long 0x00 31. " DAP_MS_SEL ,Put a particular DAP in Slave/Master mode (when two or more DAP's are in bypass mode)" "Slave,Master"
|
|
bitfld.long 0x00 30. " DAP_SDATA1_TX_RX ,Program sdata1 in TX/RX mode (when two or more DAP's are in bypass mode)" "TX,RX"
|
|
bitfld.long 0x00 29. " DAP_SDATA2_RX_TX ,Program sdata2 in TX/RX mode (when two or more DAP's are in bypass mode)" "RX,TX"
|
|
bitfld.long 0x00 0.--4. " DAP_CTRL_SEL ,DAP selection bits to select one of the three DACs or one of the five DAPs" "DAC1,DAC2,DAC3,,,,,,,,,,,,,DAP1,DAP2,DAP3,DAP4,DAP5,?..."
|
|
group.long 0xC40++0x03
|
|
line.long 0x00 "DAC_INPUT_DATA_CLK_SEL_0,DAC Input Data Selections"
|
|
bitfld.long 0x00 28.--31. " DAC_SDATA2_SEL ,These bits control the sdata2 input selection for DACs" "DAP1,DAP2,DAP3,DAP4,DAP5,?..."
|
|
bitfld.long 0x00 24.--27. " DAC_SDATA1_SEL ,These bits control the sdata1 input selection for DACs" "DAP1,DAP2,DAP3,DAP4,DAP5,?..."
|
|
bitfld.long 0x00 0.--3. " DAC_CLK_SEL ,These bits control the bit clock and fsync selection for DACs" "DAP1,DAP2,DAP3,DAP4,DAP5,?..."
|
|
group.long 0xC44++0x03
|
|
line.long 0x00 "DAC_INPUT_DATA_CLK_SEL_0,DAC Input Data Selections"
|
|
bitfld.long 0x00 28.--31. " DAC_SDATA2_SEL ,These bits control the sdata2 input selection for DACs" "DAP1,DAP2,DAP3,DAP4,DAP5,?..."
|
|
bitfld.long 0x00 24.--27. " DAC_SDATA1_SEL ,These bits control the sdata1 input selection for DACs" "DAP1,DAP2,DAP3,DAP4,DAP5,?..."
|
|
bitfld.long 0x00 0.--3. " DAC_CLK_SEL ,These bits control the bit clock and fsync selection for DACs" "DAP1,DAP2,DAP3,DAP4,DAP5,?..."
|
|
group.long 0xC48++0x03
|
|
line.long 0x00 "DAC_INPUT_DATA_CLK_SEL_0,DAC Input Data Selections"
|
|
bitfld.long 0x00 28.--31. " DAC_SDATA2_SEL ,These bits control the sdata2 input selection for DACs" "DAP1,DAP2,DAP3,DAP4,DAP5,?..."
|
|
bitfld.long 0x00 24.--27. " DAC_SDATA1_SEL ,These bits control the sdata1 input selection for DACs" "DAP1,DAP2,DAP3,DAP4,DAP5,?..."
|
|
bitfld.long 0x00 0.--3. " DAC_CLK_SEL ,These bits control the bit clock and fsync selection for DACs" "DAP1,DAP2,DAP3,DAP4,DAP5,?..."
|
|
tree.end
|
|
width 10.
|
|
tree "AP Control"
|
|
group.long 0xC00++0x0B
|
|
line.long 0x00 "REG0_0,APB Slave Security Enable Register 0"
|
|
bitfld.long 0x00 24. " CEC_SECURITY_EN ,Cec Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ATOMICS_SECURITY_EN ,Atomics Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " LA_SECURITY_EN ,LA Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " HDA_SECURITY_EN ,HDA Security Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SATA_SECURITY_EN ,SATA Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " OWR_SECURITY_EN ,OWR Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SNOR_SECURITY_EN ,SNOR Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " KFUSE_SECURITY_EN ,Kfuse Security Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FUSE_SECURITY_EN ,Fuse Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SE_SECURITY_EN ,Security Engine Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PMC_SECURITY_EN ,PMC Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RTC_SECURITY_EN ,RTC Security Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CSITE_SECURITY_EN ,COre Site Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MHS_SECURITY_EN ,MIPI HSI Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PWM_SECURITY_EN ,PWFM Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DTV_SECURITY_EN ,DTV Security Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VFIR_SECURITY_EN ,VFIR Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " AUDIO_SECURITY_EN ,Audio CLuster register Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PINMUX_AUX_SECURITY_EN ,Pinmux aux registers Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SATA_AUX_SECURITY_EN ,Sata aux registers Security Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MISC_REGS_SECURITY_EN ,SC1x pads and GP registers Security Enable" "Disabled,Enabled"
|
|
line.long 0x04 "REG1_0,APB Slave Security Enable Register 1"
|
|
bitfld.long 0x04 31. " I2C6_SECURITY_EN ,I2C6 Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " DVC_SECURITY_EN ,DVC - I2C5 Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " I2C4_SECURITY_EN ,I2C4 Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " I2C3_SECURITY_EN ,I2C3 Security Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " I2C2_SECURITY_EN ,I2C2 Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " I2C1_SECURITY_EN ,I2C1 Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " SPI6_SECURITY_EN ,SPI6 Security Enable" "DIsabled,Enabled"
|
|
bitfld.long 0x04 24. " SPI5_SECURITY_EN ,SPI5 Security Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " SPI4_SECURITY_EN ,SPI4 Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " SPI3_SECURITY_EN ,SPI3 Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " SPI2_SECURITY_EN ,SPI2 Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " SPI1_SECURITY_EN ,SPI1 Security Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " UART_D_SECURITY_EN ,UARTD Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " UART_C_SECURITY_EN ,UARTC Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " UART_B_SECURITY_EN ,UARTB Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " UART_A_SECURITY_EN ,UARTA Security Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " EMC_SECURITY_EN ,EMC Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " MC_SECURITY_EN ,MC Security Enable" "Disabled,Enabled"
|
|
line.long 0x08 "REG2_0,APB Slave Security Enable Register 2"
|
|
bitfld.long 0x08 16. " DVFS_SECURITY_EN ,DVFS Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " MIPI_CAL_SECURITY_EN ,MIPI cal Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " XUSB_PADCTL_SECURITY_EN ,XUSB_PADCTL Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " XUSB_DEV_SECURITY_EN ,XUSB_dev Security Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " XUSB_HOST_SECURITY_EN ,XUSB_host Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " APB2JTAG_SECURITY_EN ,APB2JTAG Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " SOC_THERM_SECURITY_EN ,SOC_THERM Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " DP2_SECURITY_EN ,DP2 Security Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " DDS_SECURITY_EN ,DDS Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " SDMMC4_SECURITY_EN ,SDMMC4 Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SDMMC3_SECURITY_EN ,SDMMC3 Security Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " SDMMC2_SECURITY_EN ,SDMMC2 Security Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SDMMC1_SECURITY_EN ,SDMMC1 Security Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "APB DMA Controller"
|
|
base ad:0x60020000
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND_0,APB-DMA Command Register"
|
|
bitfld.long 0x00 31. " GEN ,Global enable bit for APB-DMA" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "APBDMA_STATUS_0,APB-DMA Status Register"
|
|
bitfld.long 0x00 31. " BSY_31 ,DMA Channel 31 status" "Not busy,Busy"
|
|
bitfld.long 0x00 30. " BSY_30 ,DMA Channel 30 status" "Not busy,Busy"
|
|
bitfld.long 0x00 29. " BSY_29 ,DMA Channel 29 status" "Not busy,Busy"
|
|
bitfld.long 0x00 28. " BSY_28 ,DMA Channel 28 status" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BSY_27 ,DMA Channel 27 status" "Not busy,Busy"
|
|
bitfld.long 0x00 26. " BSY_26 ,DMA Channel 26 status" "Not busy,Busy"
|
|
bitfld.long 0x00 25. " BSY_25 ,DMA Channel 25 status" "Not busy,Busy"
|
|
bitfld.long 0x00 24. " BSY_24 ,DMA Channel 24 status" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 23. " BSY_23 ,DMA Channel 23 status" "Not busy,Busy"
|
|
bitfld.long 0x00 22. " BSY_22 ,DMA Channel 22 status" "Not busy,Busy"
|
|
bitfld.long 0x00 21. " BSY_21 ,DMA Channel 21 status" "Not busy,Busy"
|
|
bitfld.long 0x00 20. " BSY_20 ,DMA Channel 20 status" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 19. " BSY_19 ,DMA Channel 19 status" "Not busy,Busy"
|
|
bitfld.long 0x00 18. " BSY_18 ,DMA Channel 18 status" "Not busy,Busy"
|
|
bitfld.long 0x00 17. " BSY_17 ,DMA Channel 17 status" "Not busy,Busy"
|
|
bitfld.long 0x00 16. " BSY_16 ,DMA Channel 16 status" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSY_15 ,DMA Channel 15 status" "Not busy,Busy"
|
|
bitfld.long 0x00 14. " BSY_14 ,DMA Channel 14 status" "Not busy,Busy"
|
|
bitfld.long 0x00 13. " BSY_13 ,DMA Channel 13 status" "Not busy,Busy"
|
|
bitfld.long 0x00 12. " BSY_12 ,DMA Channel 12 status" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSY_11 ,DMA Channel 11 status" "Not busy,Busy"
|
|
bitfld.long 0x00 10. " BSY_10 ,DMA Channel 10 status" "Not busy,Busy"
|
|
bitfld.long 0x00 9. " BSY_9 ,DMA Channel 9 status" "Not busy,Busy"
|
|
bitfld.long 0x00 8. " BSY_8 ,DMA Channel 8 status" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BSY_7 ,DMA Channel 7 status" "Not busy,Busy"
|
|
bitfld.long 0x00 6. " BSY_6 ,DMA Channel 6 status" "Not busy,Busy"
|
|
bitfld.long 0x00 5. " BSY_5 ,DMA Channel 5 status" "Not busy,Busy"
|
|
bitfld.long 0x00 4. " BSY_4 ,DMA Channel 4 status" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSY_3 ,DMA Channel 3 status" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " BSY_2 ,DMA Channel 2 status" "Not busy,Busy"
|
|
bitfld.long 0x00 1. " BSY_1 ,DMA Channel 1 status" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " BSY_0 ,DMA Channel 0 status" "Not busy,Busy"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CNTRL_REG_0,APB-DMA Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT_VALUE ,DMA COUNT Value"
|
|
textline " "
|
|
rgroup.long 0x14++0x0B
|
|
line.long 0x00 "IRQ_STA_CPU_0,APB-DMA CPU IRQ STATUS Register"
|
|
bitfld.long 0x00 31. " CH31 ,Gathers all the after-masking CPU directed IRQ status bits from channel 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CH30 ,Gathers all the after-masking CPU directed IRQ status bits from channel 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CH29 ,Gathers all the after-masking CPU directed IRQ status bits from channel 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CH28 ,Gathers all the after-masking CPU directed IRQ status bits from channel 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CH27 ,Gathers all the after-masking CPU directed IRQ status bits from channel 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " CH26 ,Gathers all the after-masking CPU directed IRQ status bits from channel 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " CH25 ,Gathers all the after-masking CPU directed IRQ status bits from channel 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " CH24 ,Gathers all the after-masking CPU directed IRQ status bits from channel 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CH23 ,Gathers all the after-masking CPU directed IRQ status bits from channel 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " CH22 ,Gathers all the after-masking CPU directed IRQ status bits from channel 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CH21 ,Gathers all the after-masking CPU directed IRQ status bits from channel 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CH20 ,Gathers all the after-masking CPU directed IRQ status bits from channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CH19 ,Gathers all the after-masking CPU directed IRQ status bits from channel 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CH18 ,Gathers all the after-masking CPU directed IRQ status bits from channel 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CH17 ,Gathers all the after-masking CPU directed IRQ status bits from channel 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CH16 ,Gathers all the after-masking CPU directed IRQ status bits from channel 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CH15 ,Gathers all the after-masking CPU directed IRQ status bits from channel 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CH14 ,Gathers all the after-masking CPU directed IRQ status bits from channel 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CH13 ,Gathers all the after-masking CPU directed IRQ status bits from channel 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " CH12 ,Gathers all the after-masking CPU directed IRQ status bits from channel 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CH11 ,Gathers all the after-masking CPU directed IRQ status bits from channel 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CH10 ,Gathers all the after-masking CPU directed IRQ status bits from channel 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CH9 ,Gathers all the after-masking CPU directed IRQ status bits from channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CH8 ,Gathers all the after-masking CPU directed IRQ status bits from channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7 ,Gathers all the after-masking CPU directed IRQ status bits from channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CH6 ,Gathers all the after-masking CPU directed IRQ status bits from channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CH5 ,Gathers all the after-masking CPU directed IRQ status bits from channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CH4 ,Gathers all the after-masking CPU directed IRQ status bits from channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH3 ,Gathers all the after-masking CPU directed IRQ status bits from channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CH2 ,Gathers all the after-masking CPU directed IRQ status bits from channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CH1 ,Gathers all the after-masking CPU directed IRQ status bits from channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CH0 ,Gathers all the after-masking CPU directed IRQ status bits from channel 0" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ_STA_COP_0,APB-DMA COP IRQ STATUS Register"
|
|
bitfld.long 0x04 31. " CH31 ,Gathers all the after-masking COP directed IRQ status bits from channel 31" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " CH30 ,Gathers all the after-masking COP directed IRQ status bits from channel 30" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CH29 ,Gathers all the after-masking COP directed IRQ status bits from channel 29" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " CH28 ,Gathers all the after-masking COP directed IRQ status bits from channel 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " CH27 ,Gathers all the after-masking COP directed IRQ status bits from channel 27" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " CH26 ,Gathers all the after-masking COP directed IRQ status bits from channel 26" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " CH25 ,Gathers all the after-masking COP directed IRQ status bits from channel 25" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " CH24 ,Gathers all the after-masking COP directed IRQ status bits from channel 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " CH23 ,Gathers all the after-masking COP directed IRQ status bits from channel 23" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " CH22 ,Gathers all the after-masking COP directed IRQ status bits from channel 22" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " CH21 ,Gathers all the after-masking COP directed IRQ status bits from channel 21" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " CH20 ,Gathers all the after-masking COP directed IRQ status bits from channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " CH19 ,Gathers all the after-masking COP directed IRQ status bits from channel 19" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CH18 ,Gathers all the after-masking COP directed IRQ status bits from channel 18" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CH17 ,Gathers all the after-masking COP directed IRQ status bits from channel 17" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CH16 ,Gathers all the after-masking COP directed IRQ status bits from channel 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " CH15 ,Gathers all the after-masking COP directed IRQ status bits from channel 15" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " CH14 ,Gathers all the after-masking COP directed IRQ status bits from channel 14" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " CH13 ,Gathers all the after-masking COP directed IRQ status bits from channel 13" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " CH12 ,Gathers all the after-masking COP directed IRQ status bits from channel 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH11 ,Gathers all the after-masking COP directed IRQ status bits from channel 11" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " CH10 ,Gathers all the after-masking COP directed IRQ status bits from channel 10" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CH9 ,Gathers all the after-masking COP directed IRQ status bits from channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CH8 ,Gathers all the after-masking COP directed IRQ status bits from channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH7 ,Gathers all the after-masking COP directed IRQ status bits from channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CH6 ,Gathers all the after-masking COP directed IRQ status bits from channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CH5 ,Gathers all the after-masking COP directed IRQ status bits from channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CH4 ,Gathers all the after-masking COP directed IRQ status bits from channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3 ,Gathers all the after-masking COP directed IRQ status bits from channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2 ,Gathers all the after-masking COP directed IRQ status bits from channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1 ,Gathers all the after-masking COP directed IRQ status bits from channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0 ,Gathers all the after-masking COP directed IRQ status bits from channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IRQ_MASK_0,APB-DMA IRQ MASK Register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " CH31_set/clr ,Allow channel 31 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " CH30_set/clr ,Allow channel 30 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " CH29_set/clr ,Allow channel 29 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " CH28_set/clr ,Allow channel 28 IRQ to propagate" "Not allowed,Allowed"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " CH27_set/clr ,Allow channel 27 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " CH26_set/clr ,Allow channel 26 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " CH25_set/clr ,Allow channel 25 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " CH24_set/clr ,Allow channel 24 IRQ to propagate" "Not allowed,Allowed"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " CH23_set/clr ,Allow channel 23 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " CH22_set/clr ,Allow channel 22 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " CH21_set/clr ,Allow channel 21 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " CH20_set/clr ,Allow channel 20 IRQ to propagate" "Not allowed,Allowed"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " CH19_set/clr ,Allow channel 19 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " CH18_set/clr ,Allow channel 18 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " CH17_set/clr ,Allow channel 17 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " CH16_set/clr ,Allow channel 16 IRQ to propagate" "Not allowed,Allowed"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " CH15_set/clr ,Allow channel 15 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " CH14_set/clr ,Allow channel 14 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " CH13_set/clr ,Allow channel 13 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " CH12_set/clr ,Allow channel 12 IRQ to propagate" "Not allowed,Allowed"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " CH11_set/clr ,Allow channel 11 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " CH10_set/clr ,Allow channel 10 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " CH9_set/clr ,Allow channel 9 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " CH8_set/clr ,Allow channel 8 IRQ to propagate" "Not allowed,Allowed"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CH7_set/clr ,Allow channel 7 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CH6_set/clr ,Allow channel 6 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CH5_set/clr ,Allow channel 5 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CH4_set/clr ,Allow channel 4 IRQ to propagate" "Not allowed,Allowed"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " CH3_set/clr ,Allow channel 3 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " CH2_set/clr ,Allow channel 2 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CH1_set/clr ,Allow channel 1 IRQ to propagate" "Not allowed,Allowed"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CH0_set/clr ,Allow channel 0 IRQ to propagate" "Not allowed,Allowed"
|
|
textline " "
|
|
width 20.
|
|
rgroup.long 0x28++0x0B
|
|
line.long 0x00 "TRIG_REG_0,APB-DMA Trigger Register"
|
|
bitfld.long 0x00 8. " TMR2 ,Trigger select from Timer (Hardware initiated DMA request)" "Not active,Active"
|
|
bitfld.long 0x00 7. " TMR1 ,Trigger select from Timer (Hardware initiated DMA request)" "Not active,Active"
|
|
bitfld.long 0x00 6. " XRQ ,XRQ.B (GPIOB)(Hardware initiated DMA request)" "Not active,Active"
|
|
bitfld.long 0x00 5. " XRQ_A ,XRQ.A (GPIOA)(Hardware initiated DMA request)" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SMP_27 ,Semaphore requests software-initiated DMA request" "Not active,Active"
|
|
bitfld.long 0x00 3. " SMP_26 ,Semaphore requests software-initiated DMA request" "Not active,Active"
|
|
bitfld.long 0x00 2. " SMP_25 ,Semaphore requests software-initiated DMA request" "Not active,Active"
|
|
bitfld.long 0x00 1. " SMP_24 ,Semaphore requests software-initiated DMA request" "Not active,Active"
|
|
line.long 0x04 "CHANNEL_TRIG_REG_0,APB-DMA Channel Trigger Registers"
|
|
bitfld.long 0x04 31. " APB_31 ,EOC-31 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 30. " APB_30 ,EOC-30 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 29. " APB_29 ,EOC-29 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 28. " APB_28 ,EOC-28 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 27. " APB_27 ,EOC-27 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 26. " APB_26 ,EOC-26 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 25. " APB_25 ,EOC-25 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 24. " APB_24 ,EOC-24 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 23. " APB_23 ,EOC-23 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 22. " APB_22 ,EOC-22 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 21. " APB_21 ,EOC-21 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 20. " APB_20 ,EOC-20 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " APB_19 ,EOC-19 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 18. " APB_18 ,EOC-18 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 17. " APB_17 ,EOC-17 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 16. " APB_16 ,EOC-16 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 15. " APB_15 ,EOC-15 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 14. " APB_14 ,EOC-14 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 13. " APB_13 ,EOC-13 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 12. " APB_12 ,EOC-12 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 11. " APB_11 ,EOC-11 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 10. " APB_10 ,EOC-10 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 9. " APB_9 ,EOC-9 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 8. " APB_8 ,EOC-8 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " APB_7 ,EOC-7 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 6. " APB_6 ,EOC-6 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 5. " APB_5 ,EOC-5 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 4. " APB_4 ,EOC-4 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 3. " APB_3 ,EOC-3 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 2. " APB_2 ,EOC-2 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 1. " APB_1 ,EOC-1 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
bitfld.long 0x04 0. " APB_0 ,EOC-0 Initiated DMA Request after transfer completion" "Not active,Active"
|
|
textline " "
|
|
line.long 0x08 "DMA_STATUS_0,APB-DMA Interrupt Status"
|
|
bitfld.long 0x08 31. " ISE_EOC_31 ,DMA Channel 31 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 30. " ISE_EOC_30 ,DMA Channel 30 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 29. " ISE_EOC_29 ,DMA Channel 29 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 28. " ISE_EOC_28 ,DMA Channel 28 Interrupt Status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 27. " ISE_EOC_27 ,DMA Channel 27 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 26. " ISE_EOC_26 ,DMA Channel 26 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 25. " ISE_EOC_25 ,DMA Channel 25 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 24. " ISE_EOC_24 ,DMA Channel 24 Interrupt Status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 23. " ISE_EOC_23 ,DMA Channel 23 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 22. " ISE_EOC_22 ,DMA Channel 22 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 21. " ISE_EOC_21 ,DMA Channel 21 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 20. " ISE_EOC_20 ,DMA Channel 20 Interrupt Status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ISE_EOC_19 ,DMA Channel 19 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 18. " ISE_EOC_18 ,DMA Channel 18 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 17. " ISE_EOC_17 ,DMA Channel 17 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 16. " ISE_EOC_16 ,DMA Channel 16 Interrupt Status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 15. " ISE_EOC_15 ,DMA Channel 15 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 14. " ISE_EOC_14 ,DMA Channel 14 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 13. " ISE_EOC_13 ,DMA Channel 13 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 12. " ISE_EOC_12 ,DMA Channel 12 Interrupt Status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 11. " ISE_EOC_11 ,DMA Channel 11 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 10. " ISE_EOC_10 ,DMA Channel 10 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 9. " ISE_EOC_9 ,DMA Channel 9 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 8. " ISE_EOC_8 ,DMA Channel 8 Interrupt Status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ISE_EOC_7 ,DMA Channel 7 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 6. " ISE_EOC_6 ,DMA Channel 6 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 5. " ISE_EOC_5 ,DMA Channel 5 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 4. " ISE_EOC_4 ,DMA Channel 4 Interrupt Status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 3. " ISE_EOC_3 ,DMA Channel 3 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 2. " ISE_EOC_2 ,DMA Channel 2 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 1. " ISE_EOC_1 ,DMA Channel 1 Interrupt Status" "Not active,Active"
|
|
bitfld.long 0x08 0. " ISE_EOC_0 ,DMA Channel 0 Interrupt Status" "Not active,Active"
|
|
group.long 0x34++0x0B
|
|
line.long 0x00 "CHANNEL_EN_REG_0,APB-DMA Channel Counter Enable Registers"
|
|
bitfld.long 0x00 31. " CH31_CNT_EN ,Enable the Channel 31 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CH30_CNT_EN ,Enable the Channel 30 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CH29_CNT_EN ,Enable the Channel 29 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CH28_CNT_EN ,Enable the Channel 28 count" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CH27_CNT_EN ,Enable the Channel 27 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " CH26_CNT_EN ,Enable the Channel 26 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " CH25_CNT_EN ,Enable the Channel 25 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " CH24_CNT_EN ,Enable the Channel 24 count" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CH23_CNT_EN ,Enable the Channel 23 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " CH22_CNT_EN ,Enable the Channel 22 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CH21_CNT_EN ,Enable the Channel 21 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CH20_CNT_EN ,Enable the Channel 20 count" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CH19_CNT_EN ,Enable the Channel 19 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CH18_CNT_EN ,Enable the Channel 18 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CH17_CNT_EN ,Enable the Channel 17 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CH16_CNT_EN ,Enable the Channel 16 count" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CH15_CNT_EN ,Enable the Channel 15 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CH14_CNT_EN ,Enable the Channel 14 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CH13_CNT_EN ,Enable the Channel 13 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " CH12_CNT_EN ,Enable the Channel 12 count" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CH11_CNT_EN ,Enable the Channel 11 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CH10_CNT_EN ,Enable the Channel 10 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CH9_CNT_EN ,Enable the Channel 9 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CH8_CNT_EN ,Enable the Channel 8 count" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH7_CNT_EN ,Enable the Channel 7 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CH6_CNT_EN ,Enable the Channel 6 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CH5_CNT_EN ,Enable the Channel 5 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CH4_CNT_EN ,Enable the Channel 4 count" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH3_CNT_EN ,Enable the Channel 3 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CH2_CNT_EN ,Enable the Channel 2 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CH1_CNT_EN ,Enable the Channel 1 count" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CH0_CNT_EN ,Enable the Channel 0 count" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "SECURITY_REG_0,Security enables for each channel"
|
|
bitfld.long 0x04 31. " CH_31_SECURITY_EN ,Security enable for channel 31" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " CH_30_SECURITY_EN ,Security enable for channel 30" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " CH_29_SECURITY_EN ,Security enable for channel 29" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " CH_28_SECURITY_EN ,Security enable for channel 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " CH_27_SECURITY_EN ,Security enable for channel 27" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " CH_26_SECURITY_EN ,Security enable for channel 26" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " CH_25_SECURITY_EN ,Security enable for channel 25" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " CH_24_SECURITY_EN ,Security enable for channel 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " CH_23_SECURITY_EN ,Security enable for channel 23" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " CH_22_SECURITY_EN ,Security enable for channel 22" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " CH_21_SECURITY_EN ,Security enable for channel 21" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " CH_20_SECURITY_EN ,Security enable for channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " CH_19_SECURITY_EN ,Security enable for channel 19" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CH_18_SECURITY_EN ,Security enable for channel 18" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CH_17_SECURITY_EN ,Security enable for channel 17" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CH_16_SECURITY_EN ,Security enable for channel 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " CH_15_SECURITY_EN ,Security enable for channel 15" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " CH_14_SECURITY_EN ,Security enable for channel 14" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " CH_13_SECURITY_EN ,Security enable for channel 13" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " CH_12_SECURITY_EN ,Security enable for channel 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH_11_SECURITY_EN ,Security enable for channel 11" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " CH_10_SECURITY_EN ,Security enable for channel 10" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CH_9_SECURITY_EN ,Security enable for channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CH_8_SECURITY_EN ,Security enable for channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CH_7_SECURITY_EN ,Security enable for channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CH_6_SECURITY_EN ,Security enable for channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CH_5_SECURITY_EN ,Security enable for channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CH_4_SECURITY_EN ,Security enable for channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH_3_SECURITY_EN ,Security enable for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH_2_SECURITY_EN ,Security enable for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH_1_SECURITY_EN ,Security enable for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH_0_SECURITY_EN ,Security enable for channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x08 "CHANNEL_SWID_0,SWID[0] for each APBDMA channel"
|
|
bitfld.long 0x08 31. " CH_31_SWID ,SWID for Channel 31" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " CH_30_SWID ,SWID for Channel 30" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " CH_29_SWID ,SWID for Channel 29" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " CH_28_SWID ,SWID for Channel 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " CH_27_SWID ,SWID for Channel 27" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " CH_26_SWID ,SWID for Channel 26" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " CH_25_SWID ,SWID for Channel 25" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " CH_24_SWID ,SWID for Channel 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " CH_23_SWID ,SWID for Channel 23" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " CH_22_SWID ,SWID for Channel 22" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " CH_21_SWID ,SWID for Channel 21" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " CH_20_SWID ,SWID for Channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " CH_19_SWID ,SWID for Channel 19" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " CH_18_SWID ,SWID for Channel 18" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " CH_17_SWID ,SWID for Channel 17" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " CH_16_SWID ,SWID for Channel 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " CH_15_SWID ,SWID for Channel 15" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " CH_14_SWID ,SWID for Channel 14" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " CH_13_SWID ,SWID for Channel 13" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " CH_12_SWID ,SWID for Channel 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " CH_11_SWID ,SWID for Channel 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CH_10_SWID ,SWID for Channel 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CH_9_SWID ,SWID for Channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " CH_8_SWID ,SWID for Channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CH_7_SWID ,SWID for Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " CH_6_SWID ,SWID for Channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " CH_5_SWID ,SWID for Channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " CH_4_SWID ,SWID for Channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CH_3_SWID ,SWID for Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " CH_2_SWID ,SWID for Channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " CH_1_SWID ,SWID for Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CH_0_SWID ,SWID for Channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x44++0x0F
|
|
line.long 0x00 "CHAN_WT_REG0_0,Channel weights for weighted-round-robin arbitration"
|
|
bitfld.long 0x00 28.--31. " WT_CH31 ,Weight of channel 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " WT_CH30 ,Weight of channel 30" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " WT_CH29 ,Weight of channel 29" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " WT_CH28 ,Weight of channel 28" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " WT_CH27 ,Weight of channel 27" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " WT_CH26 ,Weight of channel 26" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " WT_CH25 ,Weight of channel 25" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " WT_CH24 ,Weight of channel 24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CHAN_WT_REG1_0,Channel weights for weighted-round-robin arbitration"
|
|
bitfld.long 0x04 28.--31. " WT_CH23 ,Weight of channel 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. " WT_CH22 ,Weight of channel 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--23. " WT_CH21 ,Weight of channel 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " WT_CH20 ,Weight of channel 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " WT_CH19 ,Weight of channel 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " WT_CH18 ,Weight of channel 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " WT_CH17 ,Weight of channel 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " WT_CH16 ,Weight of channel 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "CHAN_WT_REG2_0,Channel weights for weighted-round-robin arbitration"
|
|
bitfld.long 0x08 28.--31. " WT_CH15 ,Weight of channel 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 24.--27. " WT_CH14 ,Weight of channel 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 20.--23. " WT_CH13 ,Weight of channel 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 16.--19. " WT_CH12 ,Weight of channel 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " WT_CH11 ,Weight of channel 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--11. " WT_CH10 ,Weight of channel 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 4.--7. " WT_CH9 ,Weight of channel 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. " WT_Ch8 ,Weight of channel 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "CHAN_WT_REG3_0,Channel weights for weighted-round-robin arbitration"
|
|
bitfld.long 0x0C 28.--31. " WT_CH7 ,Weight of channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 24.--27. " WT_CH6 ,Weight of channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 20.--23. " WT_CH5 ,Weight of channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 16.--19. " WT_CH4 ,Weight of channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " WT_CH3 ,Weight of channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 8.--11. " WT_CH2 ,Weight of channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 4.--7. " WT_CH1 ,Weight of channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. " WT_CH0 ,Weight of channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CHANNEL_SWID1_0,SWID[1] indicating secure ASID. Supports secure writes"
|
|
bitfld.long 0x00 31. " CH_31_SWID_1 ,SWID for Channel 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CH_30_SWID_1 ,SWID for Channel 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CH_29_SWID_1 ,SWID for Channel 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CH_28_SWID_1 ,SWID for Channel 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CH_27_SWID_1 ,SWID for Channel 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " CH_26_SWID_1 ,SWID for Channel 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " CH_25_SWID_1 ,SWID for Channel 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " CH_24_SWID_1 ,SWID for Channel 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CH_23_SWID_1 ,SWID for Channel 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " CH_22_SWID_1 ,SWID for Channel 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CH_21_SWID_1 ,SWID for Channel 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CH_20_SWID_1 ,SWID for Channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CH_19_SWID_1 ,SWID for Channel 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CH_18_SWID_1 ,SWID for Channel 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CH_17_SWID_1 ,SWID for Channel 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CH_16_SWID_1 ,SWID for Channel 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CH_15_SWID_1 ,SWID for Channel 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CH_14_SWID_1 ,SWID for Channel 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CH_13_SWID_1 ,SWID for Channel 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " CH_12_SWID_1 ,SWID for Channel 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CH_11_SWID_1 ,SWID for Channel 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CH_10_SWID_1 ,SWID for Channel 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CH_9_SWID_1 ,SWID for Channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CH_8_SWID_1 ,SWID for Channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CH_7_SWID_1 ,SWID for Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CH_6_SWID_1 ,SWID for Channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CH_5_SWID_1 ,SWID for Channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CH_4_SWID_1 ,SWID for Channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CH_3_SWID_1 ,SWID for Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CH_2_SWID_1 ,SWID for Channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CH_1_SWID_1 ,SWID for Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CH_0_SWID_1 ,SWID for Channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
width 27.
|
|
tree "APB DMA Channel 0"
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "CHANNEL_0_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1000))&0x10000000)==0x00)
|
|
group.long (0x1000+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_0_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1000+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_0_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1000+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1000+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_0_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1000+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_0_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1000+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_0_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1000+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_0_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1000+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_0_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1000+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_0_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1000+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_0_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 1"
|
|
group.long 0x1040++0x03
|
|
line.long 0x00 "CHANNEL_1_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1040))&0x10000000)==0x00)
|
|
group.long (0x1040+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_1_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1040+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_1_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1040+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1040+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_1_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1040+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_1_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1040+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_1_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1040+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_1_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1040+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_1_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1040+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_1_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1040+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_1_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 2"
|
|
group.long 0x1080++0x03
|
|
line.long 0x00 "CHANNEL_2_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1080))&0x10000000)==0x00)
|
|
group.long (0x1080+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_2_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1080+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_2_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1080+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1080+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_2_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1080+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_2_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1080+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_2_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1080+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_2_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1080+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_2_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1080+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_2_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1080+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_2_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 3"
|
|
group.long 0x10C0++0x03
|
|
line.long 0x00 "CHANNEL_3_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x10C0))&0x10000000)==0x00)
|
|
group.long (0x10C0+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_3_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x10C0+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_3_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x10C0+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x10C0+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_3_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x10C0+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_3_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x10C0+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_3_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x10C0+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_3_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x10C0+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_3_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x10C0+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_3_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x10C0+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_3_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 4"
|
|
group.long 0x1100++0x03
|
|
line.long 0x00 "CHANNEL_4_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1100))&0x10000000)==0x00)
|
|
group.long (0x1100+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_4_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1100+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_4_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1100+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1100+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_4_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1100+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_4_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1100+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_4_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1100+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_4_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1100+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_4_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1100+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_4_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1100+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_4_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 5"
|
|
group.long 0x1140++0x03
|
|
line.long 0x00 "CHANNEL_5_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1140))&0x10000000)==0x00)
|
|
group.long (0x1140+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_5_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1140+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_5_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1140+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1140+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_5_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1140+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_5_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1140+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_5_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1140+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_5_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1140+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_5_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1140+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_5_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1140+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_5_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 6"
|
|
group.long 0x1180++0x03
|
|
line.long 0x00 "CHANNEL_6_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1180))&0x10000000)==0x00)
|
|
group.long (0x1180+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_6_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1180+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_6_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1180+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1180+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_6_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1180+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_6_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1180+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_6_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1180+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_6_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1180+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_6_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1180+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_6_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1180+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_6_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 7"
|
|
group.long 0x11C0++0x03
|
|
line.long 0x00 "CHANNEL_7_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x11C0))&0x10000000)==0x00)
|
|
group.long (0x11C0+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_7_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x11C0+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_7_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x11C0+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x11C0+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_7_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x11C0+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_7_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x11C0+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_7_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x11C0+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_7_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x11C0+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_7_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x11C0+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_7_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x11C0+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_7_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 8"
|
|
group.long 0x1200++0x03
|
|
line.long 0x00 "CHANNEL_8_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1200))&0x10000000)==0x00)
|
|
group.long (0x1200+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_8_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1200+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_8_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1200+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1200+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_8_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1200+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_8_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1200+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_8_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1200+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_8_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1200+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_8_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1200+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_8_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1200+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_8_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 9"
|
|
group.long 0x1240++0x03
|
|
line.long 0x00 "CHANNEL_9_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1240))&0x10000000)==0x00)
|
|
group.long (0x1240+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_9_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1240+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_9_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1240+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1240+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_9_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1240+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_9_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1240+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_9_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1240+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_9_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1240+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_9_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1240+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_9_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1240+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_9_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 10"
|
|
group.long 0x1280++0x03
|
|
line.long 0x00 "CHANNEL_10_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1280))&0x10000000)==0x00)
|
|
group.long (0x1280+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_10_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1280+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_10_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1280+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1280+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_10_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1280+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_10_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1280+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_10_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1280+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_10_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1280+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_10_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1280+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_10_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1280+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_10_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 11"
|
|
group.long 0x12C0++0x03
|
|
line.long 0x00 "CHANNEL_11_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x12C0))&0x10000000)==0x00)
|
|
group.long (0x12C0+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_11_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x12C0+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_11_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x12C0+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x12C0+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_11_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x12C0+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_11_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x12C0+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_11_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x12C0+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_11_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x12C0+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_11_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x12C0+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_11_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x12C0+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_11_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 12"
|
|
group.long 0x1300++0x03
|
|
line.long 0x00 "CHANNEL_12_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1300))&0x10000000)==0x00)
|
|
group.long (0x1300+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_12_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1300+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_12_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1300+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1300+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_12_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1300+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_12_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1300+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_12_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1300+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_12_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1300+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_12_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1300+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_12_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1300+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_12_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 13"
|
|
group.long 0x1340++0x03
|
|
line.long 0x00 "CHANNEL_13_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1340))&0x10000000)==0x00)
|
|
group.long (0x1340+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_13_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1340+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_13_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1340+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1340+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_13_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1340+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_13_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1340+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_13_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1340+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_13_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1340+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_13_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1340+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_13_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1340+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_13_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 14"
|
|
group.long 0x1380++0x03
|
|
line.long 0x00 "CHANNEL_14_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1380))&0x10000000)==0x00)
|
|
group.long (0x1380+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_14_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1380+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_14_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1380+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1380+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_14_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1380+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_14_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1380+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_14_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1380+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_14_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1380+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_14_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1380+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_14_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1380+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_14_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 15"
|
|
group.long 0x13C0++0x03
|
|
line.long 0x00 "CHANNEL_15_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x13C0))&0x10000000)==0x00)
|
|
group.long (0x13C0+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_15_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x13C0+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_15_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x13C0+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x13C0+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_15_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x13C0+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_15_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x13C0+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_15_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x13C0+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_15_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x13C0+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_15_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x13C0+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_15_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x13C0+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_15_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 16"
|
|
group.long 0x1400++0x03
|
|
line.long 0x00 "CHANNEL_16_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1400))&0x10000000)==0x00)
|
|
group.long (0x1400+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_16_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1400+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_16_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1400+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1400+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_16_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1400+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_16_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1400+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_16_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1400+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_16_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1400+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_16_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1400+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_16_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1400+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_16_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 17"
|
|
group.long 0x1440++0x03
|
|
line.long 0x00 "CHANNEL_17_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1440))&0x10000000)==0x00)
|
|
group.long (0x1440+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_17_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1440+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_17_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1440+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1440+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_17_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1440+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_17_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1440+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_17_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1440+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_17_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1440+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_17_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1440+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_17_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1440+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_17_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 18"
|
|
group.long 0x1480++0x03
|
|
line.long 0x00 "CHANNEL_18_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1480))&0x10000000)==0x00)
|
|
group.long (0x1480+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_18_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1480+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_18_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1480+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1480+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_18_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1480+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_18_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1480+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_18_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1480+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_18_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1480+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_18_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1480+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_18_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1480+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_18_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 19"
|
|
group.long 0x14C0++0x03
|
|
line.long 0x00 "CHANNEL_19_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x14C0))&0x10000000)==0x00)
|
|
group.long (0x14C0+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_19_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x14C0+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_19_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x14C0+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x14C0+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_19_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x14C0+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_19_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x14C0+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_19_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x14C0+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_19_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x14C0+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_19_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x14C0+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_19_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x14C0+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_19_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 20"
|
|
group.long 0x1500++0x03
|
|
line.long 0x00 "CHANNEL_20_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1500))&0x10000000)==0x00)
|
|
group.long (0x1500+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_20_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1500+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_20_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1500+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1500+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_20_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1500+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_20_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1500+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_20_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1500+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_20_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1500+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_20_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1500+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_20_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1500+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_20_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 21"
|
|
group.long 0x1540++0x03
|
|
line.long 0x00 "CHANNEL_21_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1540))&0x10000000)==0x00)
|
|
group.long (0x1540+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_21_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1540+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_21_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1540+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1540+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_21_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1540+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_21_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1540+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_21_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1540+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_21_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1540+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_21_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1540+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_21_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1540+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_21_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 22"
|
|
group.long 0x1580++0x03
|
|
line.long 0x00 "CHANNEL_22_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1580))&0x10000000)==0x00)
|
|
group.long (0x1580+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_22_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1580+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_22_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1580+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1580+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_22_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1580+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_22_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1580+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_22_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1580+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_22_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1580+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_22_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1580+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_22_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1580+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_22_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 23"
|
|
group.long 0x15C0++0x03
|
|
line.long 0x00 "CHANNEL_23_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x15C0))&0x10000000)==0x00)
|
|
group.long (0x15C0+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_23_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x15C0+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_23_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x15C0+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x15C0+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_23_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x15C0+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_23_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x15C0+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_23_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x15C0+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_23_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x15C0+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_23_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x15C0+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_23_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x15C0+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_23_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 24"
|
|
group.long 0x1600++0x03
|
|
line.long 0x00 "CHANNEL_24_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1600))&0x10000000)==0x00)
|
|
group.long (0x1600+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_24_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1600+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_24_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1600+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1600+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_24_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1600+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_24_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1600+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_24_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1600+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_24_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1600+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_24_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1600+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_24_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1600+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_24_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 25"
|
|
group.long 0x1640++0x03
|
|
line.long 0x00 "CHANNEL_25_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1640))&0x10000000)==0x00)
|
|
group.long (0x1640+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_25_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1640+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_25_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1640+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1640+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_25_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1640+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_25_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1640+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_25_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1640+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_25_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1640+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_25_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1640+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_25_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1640+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_25_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 26"
|
|
group.long 0x1680++0x03
|
|
line.long 0x00 "CHANNEL_26_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1680))&0x10000000)==0x00)
|
|
group.long (0x1680+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_26_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1680+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_26_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1680+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1680+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_26_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1680+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_26_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1680+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_26_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1680+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_26_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1680+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_26_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1680+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_26_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1680+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_26_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 27"
|
|
group.long 0x16C0++0x03
|
|
line.long 0x00 "CHANNEL_27_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x16C0))&0x10000000)==0x00)
|
|
group.long (0x16C0+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_27_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x16C0+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_27_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x16C0+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x16C0+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_27_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x16C0+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_27_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x16C0+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_27_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x16C0+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_27_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x16C0+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_27_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x16C0+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_27_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x16C0+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_27_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 28"
|
|
group.long 0x1700++0x03
|
|
line.long 0x00 "CHANNEL_28_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1700))&0x10000000)==0x00)
|
|
group.long (0x1700+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_28_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1700+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_28_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1700+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1700+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_28_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1700+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_28_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1700+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_28_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1700+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_28_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1700+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_28_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1700+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_28_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1700+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_28_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 29"
|
|
group.long 0x1740++0x03
|
|
line.long 0x00 "CHANNEL_29_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1740))&0x10000000)==0x00)
|
|
group.long (0x1740+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_29_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1740+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_29_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1740+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1740+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_29_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1740+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_29_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1740+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_29_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1740+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_29_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1740+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_29_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1740+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_29_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1740+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_29_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 30"
|
|
group.long 0x1780++0x03
|
|
line.long 0x00 "CHANNEL_30_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x1780))&0x10000000)==0x00)
|
|
group.long (0x1780+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_30_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x1780+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_30_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x1780+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x1780+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_30_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x1780+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_30_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x1780+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_30_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x1780+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_30_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x1780+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_30_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x1780+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_30_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x1780+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_30_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
tree "APB DMA Channel 31"
|
|
group.long 0x17C0++0x03
|
|
line.long 0x00 "CHANNEL_31_CSR_0,APB-DMA-n Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enables DMA channel transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " IE_EOC ,Interrupts when DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " HOLD ,Holds this Processor until DMA block transfer completes" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DIR ,DMA Transfer Direction" "AHB write,AHB read"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ONCE ,Run Once or Run Multiple mode (Allow Retriggering of this Channel)" "Multiple,Single"
|
|
bitfld.long 0x00 21. " FLOW ,Flow Control Enable (Synchronize Burst Transfers)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " REQ_SEL ,Req sel" "CNTR_REQ,APBIF_CH0,APBIF_CH1,APBIF_CH2,APBIF_CH3,HSI,APBIF_CH4,APBIF_CH5,UART_A,UART_B,UART_C,DTV,APBIF_CH6,APBIF_CH7,APBIF_CH8,SL2B1,SL2B2,SL2B3,SL2B4,UART_D,UART_E,I2C,I2C2,I2C3,DVC_I2C,OWR,I2C4,SL2B5,SL2B6,APBIF_CH9,I2C6,NA31"
|
|
if (((d.l(ad:0x60020000+0x17C0))&0x10000000)==0x00)
|
|
group.long (0x17C0+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_31_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Ping buffer transfer completed,Pong buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
else
|
|
group.long (0x17C0+0x04)++0x03
|
|
line.long 0x00 "CHANNEL_31_STA_0,APB-DMA-n Status Register"
|
|
rbitfld.long 0x00 31. " BSY ,Indicates whether DMA Channel Status is active or not" "Wait,Active"
|
|
bitfld.long 0x00 30. " ISE_EOC ,Write 1 to clear the flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " HALT ,Holding Status of Processor" "Not halted,Halted"
|
|
rbitfld.long 0x00 28. " PING_PONG_STA ,Ping pong status" "Pong buffer transfer completed,Ping buffer transfer completed"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " DMA_ACTIVITY ,Indicates current DMA channel is transfering data" "Idle,Busy"
|
|
rbitfld.long 0x00 26. " CHANNEL_PAUSE ,Indicates the status of channel pause" "Not paused,Paused"
|
|
endif
|
|
rgroup.long (0x17C0+0x00)++0x03
|
|
line.long 0x00 "DMA_COUNT,Indicates the actual DMA Data Transfer Count in bytes"
|
|
group.long (0x17C0+0x0C)++0x03
|
|
line.long 0x00 "CHANNEL_31_CSRE_0,APB-DMA-n Control-Extended Register"
|
|
bitfld.long 0x00 31. " CHANNEL_PAUSE ,Pause data transfer on the channel" "Resumed,Paused"
|
|
bitfld.long 0x00 14.--19. " TRIG_SEL ,Enable on Non_Zero Value" "NA1,SMP24,SMP25,SMP26,SMP27,XRQ_A,XRQ_B,TMR1,TMR2,APB_0,APB_1,APB_2,APB_3,APB_4,APB_5,APB_6,APB_7,APB_8,APB_9,APB_10,APB_11,APB_12,APB_13,APB_14,APB_15,APB_16,APB_17,APB_18,APB_19,APB_20,APB_21,APB_22,APB_23,APB_24,APB_25,APB_26,APB_27,APB_28,APB_29,APB_30,APB_31,?..."
|
|
group.long (0x17C0+0x10)++0x03
|
|
line.long 0x00 "CHANNEL_31_AHB_PTR_0,APB-DMA-n AHB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " AHB_BASE ,APB-DMA Starting Address for AHB bus"
|
|
group.long (0x17C0+0x14)++0x03
|
|
line.long 0x00 "CHANNEL_31_AHB_SEQ_0,APB-DMA-n AHB Address Sequencer Register"
|
|
bitfld.long 0x00 31. " INTR_ENB ,Send interrupt to COP" "CPU,COP"
|
|
bitfld.long 0x00 28.--30. " AHB_BUS_WIDTH ,AHB Bus Width" "Width_8,Width_16,Width_32,Width_64,Width_128,?..."
|
|
bitfld.long 0x00 27. " AHB_DATA_SWAP ,Data going to AHB gets swapped" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " AHB_BURST ,AHB Burst Size DMA Burst Length" ",,,,DMA burst 1 Word,DMA burst 4 Words,DMA burst 8 Words,?..."
|
|
bitfld.long 0x00 19. " DBL_BUF ,Double Buffering Mode" "Reload for 1x blocks,Reload for 2x blocks"
|
|
bitfld.long 0x00 16.--18. " WRAP ,AHB Address Wrap" "No wrap,32 Words,64 Words,128 Words,256 Words,512 Words,1024 Words,2048 Words"
|
|
group.long (0x17C0+0x18)++0x03
|
|
line.long 0x00 "CHANNEL_31_APB_PTR_0,APB-DMA-n APB Starting Address Pointer Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " APB_BASE ,APB-DMA Starting address for APB Bus"
|
|
group.long (0x17C0+0x1C)++0x03
|
|
line.long 0x00 "CHANNEL_31_APB_SEQ_0,APB-DMA-n APB Address Sequencer Assignments"
|
|
bitfld.long 0x00 28.--30. " APB_BUS_WIDTH ,APB bus width" "8 bit bus,16 bit bus,32 bit bus,64 bit bus,128 bit bus,?..."
|
|
bitfld.long 0x00 27. " APB_DATA_SWAP ,Data going to the APB gets swapped" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " APB_ADDR_WRAP ,Address Wrap around Window" "No wrap,1 words,2 words,4 words,8 words,16 words,32 words,64 words"
|
|
group.long (0x17C0+0x20)++0x03
|
|
line.long 0x00 "CHANNEL_31_WCOUNT_0,APB-DMA-n Word Count Register"
|
|
hexmask.long 0x00 2.--29. 1. " WCOUNT ,Number of 32-bit word cycles"
|
|
rgroup.long (0x17C0+0x24)++0x03
|
|
line.long 0x00 "CHANNEL_31_WORD_TRANSFER_0,APB-DMA-n Word Transfer Register"
|
|
hexmask.long 0x00 2.--29. 1. " COUNT ,APB Current 32-bit Word Cycles"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "USB"
|
|
tree "USB1 (2.0)"
|
|
base ad:0x7D000000
|
|
tree "USB 1 Controller"
|
|
tree "Status Registers"
|
|
width 35.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_ID_0,USB2D Identification Register"
|
|
bitfld.long 0x00 29.--31. " CIVERSION ,Identifies the CI version" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 25.--28. " VERSION ,Identifies the version of the core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21.--24. " REVISION ,Revision number of the USB controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. " TAG ,Identifies the tag of the core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " NID ,Ones complement version of ID"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ID ,Configuration number"
|
|
rgroup.long 0x08++0x0F
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_HW_HOST_0,USB2D Hardware Host Register"
|
|
bitfld.long 0x00 1.--3. " NPORT ,NPORT" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " HC ,Support for host mode" "Disabled,Enabled"
|
|
line.long 0x04 "USB1_CONTROLLER_USB2D_HW_DEVICE_0,USB2D Hardware Device Register"
|
|
bitfld.long 0x04 1.--5. " DEVEP ,Number of endpoints supported by this device controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0. " DC ,Support for device mode" "Disabled,Enabled"
|
|
line.long 0x08 "USB1_CONTROLLER_USB2D_HW_TXBUF_0,USB2D Hardware TX Buffer Register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " TXCHANADD ,Total number of address bits for the transmit buffer of each transmit endpoint"
|
|
hexmask.long.byte 0x08 8.--15. 1. " TXADD ,Total number of address bits for the transmit buffer"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TCBURST ,Maximum burst size supported by the transmit endpoints for data transfers"
|
|
line.long 0x0C "USB1_CONTROLLER_USB2D_HW_RXBUF_0,USB2D RX Buffer HW Parameters Register"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " RXADD ,Total number of address bits for the receive buffer"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " RXBURST ,Maximum burst size supported by the receive endpoints for data transfers"
|
|
textline " "
|
|
width 40.
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "USB1_CONTROLLER_USB_USB2D_GPTIMER0LD_0,Timer register 0"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " GPTIMER0LD ,Value loaded into the GPTCNT"
|
|
line.long 0x04 "USB1_CONTROLLER_USB2D_GPTIMER0CTRL_0,Timer register controller 0"
|
|
bitfld.long 0x04 31. " GTPRUN ,Enables the general-purpose timer to run" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " GPTRST ,Writing a one to this bit will reload the GPTCNT with the value in GPTL" "No effect,reload"
|
|
bitfld.long 0x04 24. " GPTMODE ,Selects timer mode" "One-shot,Repeat"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,Value of the running timer"
|
|
line.long 0x08 "USB1_CONTROLLER_USB2D_GPTIMER1LD_0,Timer register 1"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " GPTIMER1LD ,Value loaded into the GPTCNT"
|
|
line.long 0x0C "USB1_CONTROLLER_USB2D_GPTIMER1CTRL_0,Timer register controller 1"
|
|
bitfld.long 0x0C 31. " GTPRUN ,Enables the general-purpose timer to run" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " GPTRST ,Writing a one to this bit will reload the GPTCNT with the value in GPTL" "No effect,reload"
|
|
bitfld.long 0x0C 24. " GPTMODE ,Selects timer mode" "One-shot,Repeat"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,Value of the running timer"
|
|
textline " "
|
|
width 37.
|
|
rgroup.word 0x100++0x03
|
|
line.word 0x00 "USB1_CONTROLLER_USB2D_CAPLENGTH_0,USB2D Capability Register Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CAPLENGTH ,Indicates which offset to add to the register base address at the beginning of the operational register"
|
|
line.word 0x02 "USB1_CONTROLLER_USB2D_HCIVERSON_0,USB2D Host Interface Version Number Register"
|
|
hexmask.word 0x02 0.--15. 1. " HCIVERSION ,Contains a BCD encoding of the EHCI revision number supported by this host controller"
|
|
rgroup.long 0x104++0x07
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_HCSPARAMS_0,USB2D Host Control Structural Parameters Register"
|
|
bitfld.long 0x00 24.--27. " N_TT ,Number of transaction translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " N_PTT ,Number of ports per transaction translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " N_CC ,Number of companion controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " N_PCC ,Number of ports per companion controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " PPC ,Port power control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " N_PORTS ,Number of downstream ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "USB1_CONTROLLER_USB2D_HCCPARAMS_0,USB2D Host Control Capability Parameters Register"
|
|
bitfld.long 0x04 18. " PPC ,Per-port change event capability" "Not supported,Supported"
|
|
bitfld.long 0x04 17. " LEN ,Link power management capability" "Not supported,Supported"
|
|
hexmask.long.byte 0x04 8.--15. 1. " EECP ,EHCI extended capabilities pointer"
|
|
bitfld.long 0x04 4.--7. " IST ,Isochronous scheduling threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 2. " ASP ,Asynchronous schedule park capability" "Not supported,Supported"
|
|
bitfld.long 0x04 1. " PFL ,Programmable frame list flag (frame list length)" "1024 elements,USBCMD_0.FS"
|
|
rgroup.long 0x120++0x07
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_DCIVERSION_0,USB2D Device Interface Version Number Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DCIVERSION ,Interface version number for the two-byte BCD encoding"
|
|
line.long 0x04 "USB1_CONTROLLER_USB2D_DCCPARAMS_0,USB2D Device Control Capabilities Register"
|
|
bitfld.long 0x04 8. " HC ,Host capable" "Not capable,Capable"
|
|
bitfld.long 0x04 7. " DC ,Device capable" "Not capable,Capable"
|
|
bitfld.long 0x04 5. " LEN ,Link power management capability" "Not capable,Capable"
|
|
bitfld.long 0x04 0.--4. " DEN ,Device endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
width 37.
|
|
tree "Control Registers"
|
|
if (((d.l(ad:0x7D000000+0x1F8))&0x03)==0x02)
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_EXTSTS_0,USB2D EXTSTS Register"
|
|
eventfld.long 0x00 4. " TI1 ,General purpose timer interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TI0 ,General purpose timer interrupt 0" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 0. " NAKI ,NAK interrupt bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_EXTSTS_0,USB2D EXTSTS Register"
|
|
eventfld.long 0x00 4. " TI1 ,General purpose timer interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TI0 ,General purpose timer interrupt 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " UPA ,USB host periodic interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " UAI ,USB host asynchronous interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 0. " NAKI ,NAK interrupt bit" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_USBEXTINTR_0,USB2D EXTINTR Register"
|
|
bitfld.long 0x00 4. " TIE1 ,General purpose timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TIE0 ,General purpose timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " UPIE ,UPIE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UAIE ,UAIE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NAKE ,NAK interrupt enable" "Disabled,Enabled"
|
|
if (((d.l(ad:0x7D000000+0x108))&0x06)==0x00)&&(((d.l(ad:0x7D000000+0x1F8))&0x03)==0x03)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_USBCMD_0,USB2D USB Command Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control"
|
|
bitfld.long 0x00 14. " ATDTW ,ADD DTD tripwire" "Clear,Set"
|
|
bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Clear,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--9. " ASP1_ASP0 ,Asynchronous schedule park mode count" "0,1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. 15. " FS2_FS0 ,Frame list size (in bytes)" "4096,2048,1024,512,256,128,64,32"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop host/device controller" "Stop,Run"
|
|
elif (((d.l(ad:0x7D000000+0x108))&0x06)==0x02)&&(((d.l(ad:0x7D000000+0x1F8))&0x03)==0x03)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_USBCMD_0,USB2D USB Command Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control"
|
|
bitfld.long 0x00 14. " ATDTW ,ADD DTD tripwire" "Clear,Set"
|
|
bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Clear,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--9. " ASP1_ASP0 ,Asynchronous schedule park mode count" "0,1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. 15. " FS2_FS0 ,Frame list size (in bytes)" "4096,2048,1024,512,256,128,64,32"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop host/device controller" "Stop,Run"
|
|
elif (((d.l(ad:0x7D000000+0x108))&0x06)==0x04)&&(((d.l(ad:0x7D000000+0x1F8))&0x03)==0x03)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_USBCMD_0,USB2D USB Command Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control"
|
|
bitfld.long 0x00 14. " ATDTW ,ADD DTD tripwire" "Clear,Set"
|
|
bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Clear,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ASP1_ASP0 ,Asynchronous schedule park mode count" ",1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. 15. " FS2_FS0 ,Frame list size (in bytes)" "4096,2048,1024,512,256,128,64,32"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop host/device controller" "Stop,Run"
|
|
elif (((d.l(ad:0x7D000000+0x108))&0x06)==0x06)&&(((d.l(ad:0x7D000000+0x1F8))&0x03)==0x03)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_USBCMD_0,USB2D USB Command Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control"
|
|
bitfld.long 0x00 14. " ATDTW ,ADD DTD tripwire" "Clear,Set"
|
|
bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Clear,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ASP1_ASP0 ,Asynchronous schedule park mode count" ",1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. 15. " FS2_FS0 ,Frame list size (in bytes)" "4096,2048,1024,512,256,128,64,32"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop host/device controller" "Stop,Run"
|
|
elif (((d.l(ad:0x7D000000+0x108))&0x04)==0x00)&&(((d.l(ad:0x7D000000+0x1F8))&0x03)!=0x03)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_USBCMD_0,USB2D USB Command Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14. " ATDTW ,ADD DTD tripwire" "Clear,Set"
|
|
bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Clear,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " ASP1_ASP0 ,Asynchronous schedule park mode count" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. 15. " FS2_FS0 ,Frame list size (in bytes)" "4096,2048,1024,512,256,128,64,32"
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop host/device controller" "Stop,Run"
|
|
elif (((d.l(ad:0x7D000000+0x108))&0x04)==0x04)&&(((d.l(ad:0x7D000000+0x1F8))&0x03)!=0x03)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_USBCMD_0,USB2D USB Command Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control"
|
|
bitfld.long 0x00 14. " ATDTW ,ADD DTD tripwire" "Clear,Set"
|
|
bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Clear,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ASP1_ASP0 ,Asynchronous schedule park mode count" ",1,2,3"
|
|
bitfld.long 0x00 2.--3. 15. " FS2_FS0 ,Frame list size (in bytes)" "4096,2048,1024,512,256,128,64,32"
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop host/device controller" "Stop,Run"
|
|
endif
|
|
if (((d.l(ad:0x7D000000+0x1F8))&0x03)==0x03)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_USBSTS_0,USB2D USB Status Register"
|
|
bitfld.long 0x00 31. " PPCI16 ,Port 16 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " PPCI15 ,Port 15 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 29. " PPCI14 ,Port 14 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " PPCI13 ,Port 13 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 27. " PPCI12 ,Port 12 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPCI11 ,Port 11 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 25. " PPCI10 ,Port 10 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " PPCI9 ,Port 9 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 23. " PPCI8 ,Port 8 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " PPCI7 ,Port 7 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCI6 ,Port 6 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " PPCI5 ,Port 5 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 19. " PPCI4 ,Port 4 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " PPCI3 ,Port 3 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 17. " PPCI2 ,Port 2 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PPCI1 ,Port 1 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 15. " AS ,Asynchronous schedule status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PS ,Periodic schedule status" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " RCL ,Empty asynchronous schedule detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " HCH ,HCHalted" "Unhalted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " UALT_INT ,ULPI alt_int Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ULPI_INT ,ULPI interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " SRI ,SOF received" "Not received,Received"
|
|
bitfld.long 0x00 5. " AAI ,Interrupt and asynchronous advance" "Not advanced,Advanced"
|
|
rbitfld.long 0x00 4. " SEI ,System error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRI ,Frame list rollover" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCI ,Port change detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB error interrupt" "No error,Error"
|
|
bitfld.long 0x00 0. " UI ,USB interrupt" "No interrupt,Interrupt"
|
|
elif (((d.l(ad:0x7D000000+0x1F8))&0x03)==0x02)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_USBSTS_0,USB2D USB Status Register"
|
|
bitfld.long 0x00 31. " PPCI16 ,Port 16 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " PPCI15 ,Port 15 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 29. " PPCI14 ,Port 14 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " PPCI13 ,Port 13 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 27. " PPCI12 ,Port 12 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPCI11 ,Port 11 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 25. " PPCI10 ,Port 10 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " PPCI9 ,Port 9 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 23. " PPCI8 ,Port 8 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " PPCI7 ,Port 7 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCI6 ,Port 6 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " PPCI5 ,Port 5 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 19. " PPCI4 ,Port 4 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " PPCI3 ,Port 3 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 17. " PPCI2 ,Port 2 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PPCI1 ,Port 1 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 11. " UALT_INT ,ULPI alt_int Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ULPI_INT ,ULPI interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SLI ,DCSuspend" "Not suspended,Suspended"
|
|
eventfld.long 0x00 7. " SRI ,SOF received" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 6. " URI ,USB reset received" "No reset,Reset"
|
|
rbitfld.long 0x00 4. " SEI ,System error" "No error,Error"
|
|
bitfld.long 0x00 2. " PCI ,Port change detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB error interrupt" "No error,Error"
|
|
bitfld.long 0x00 0. " UI ,USB interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_USBSTS_0,USB2D USB Status Register"
|
|
bitfld.long 0x00 31. " PPCI16 ,Port 16 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " PPCI15 ,Port 15 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 29. " PPCI14 ,Port 14 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " PPCI13 ,Port 13 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 27. " PPCI12 ,Port 12 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPCI11 ,Port 11 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 25. " PPCI10 ,Port 10 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " PPCI9 ,Port 9 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 23. " PPCI8 ,Port 8 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " PPCI7 ,Port 7 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCI6 ,Port 6 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " PPCI5 ,Port 5 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 19. " PPCI4 ,Port 4 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " PPCI3 ,Port 3 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 17. " PPCI2 ,Port 2 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PPCI1 ,Port 1 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 11. " UALT_INT ,ULPI alt_int Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ULPI_INT ,ULPI interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " SRI ,SOF received" "Not received,Received"
|
|
rbitfld.long 0x00 4. " SEI ,System error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCI ,Port change detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB error interrupt" "No error,Error"
|
|
bitfld.long 0x00 0. " UI ,USB interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
if (((d.l(ad:0x7D000000+0x1F8))&0x03)==0x03)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_USBINTR_0,USB2D USB Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " PPCE16 ,Port 16 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PPCE15 ,Port 15 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PPCE14 ,Port 14 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PPCE13 ,Port 13 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PPCE12 ,Port 12 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPCE11 ,Port 11 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PPCE10 ,Port 10 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PPCE9 ,Port 9 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PPCE8 ,Port 8 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PPCE7 ,Port 7 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCE6 ,Port 6 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PPCE5 ,Port 5 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PPCE4 ,Port 4 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PPCE3 ,Port 3 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PPCE2 ,Port 2 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PPCE1 ,Port 1 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " UALTIE ,LPI alt_int Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ULPIE ,ULPI interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " SRE ,SOF received" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AAE ,Interrupt on asynchronous advance" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEE ,System error" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRE ,Frame list rollover" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCE ,Port change detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UEE ,USB error interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USB interrupt" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x7D000000+0x1F8))&0x03)==0x02)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_USBINTR_0,USB2D USB Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " PPCE16 ,Port 16 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PPCE15 ,Port 15 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PPCE14 ,Port 14 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PPCE13 ,Port 13 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PPCE12 ,Port 12 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPCE11 ,Port 11 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PPCE10 ,Port 10 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PPCE9 ,Port 9 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PPCE8 ,Port 8 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PPCE7 ,Port 7 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCE6 ,Port 6 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PPCE5 ,Port 5 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PPCE4 ,Port 4 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PPCE3 ,Port 3 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PPCE2 ,Port 2 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PPCE1 ,Port 1 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " UALTIE ,LPI alt_int Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ULPIE ,ULPI interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLE ,Sleep enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " SRE ,SOF received" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 6. " URE ,USB reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SEE ,System error" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCE ,Port change detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UEE ,USB error interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USB interrupt" "Disabled,Enabled"
|
|
else
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_USBINTR_0,USB2D USB Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " PPCE16 ,Port 16 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PPCE15 ,Port 15 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PPCE14 ,Port 14 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PPCE13 ,Port 13 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PPCE12 ,Port 12 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPCE11 ,Port 11 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PPCE10 ,Port 10 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PPCE9 ,Port 9 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PPCE8 ,Port 8 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PPCE7 ,Port 7 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCE6 ,Port 6 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PPCE5 ,Port 5 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PPCE4 ,Port 4 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PPCE3 ,Port 3 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PPCE2 ,Port 2 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PPCE1 ,Port 1 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " UALTIE ,LPI alt_int Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ULPIE ,ULPI interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " SRE ,SOF received" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SEE ,System error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCE ,Port change detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UEE ,USB error interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USB interrupt" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_FRINDEX_0,USB2D USB Frame Index Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame index"
|
|
textline " "
|
|
width 44.
|
|
if (((d.l(ad:0x7D000000+0x1F8))&0x03)==0x02)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_PERIODICLISTBASE_0,USB2D Host Controller Frame List Base Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 0x2 " USBADR ,Device address"
|
|
bitfld.long 0x00 24. " USBADRA ,Device address advance" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x7D000000+0x1F8))&0x03)==0x03)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_PERIODICLISTBASE_0,USB2D Host Controller Frame List Base Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Beginning address of the periodic frame list in the system memory"
|
|
else
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "USB1_CONTROLLER_USB2D_PERIODICLISTBASE_0,USB2D Host Controller Frame List Base Address Register"
|
|
endif
|
|
if (((d.l(ad:0x7D000000+0x1F8))&0x03)==0x02)
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_ASYNCLISTADDR_0,USB2D Next Asynchronous List Address Register"
|
|
hexmask.long.tbyte 0x00 11.--31. 0x08 " EPBASE ,Address of the top of the endpoint list in system memory"
|
|
elif (((d.l(ad:0x7D000000+0x1F8))&0x03)==0x03)
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_ASYNCLISTADDR_0,USB2D Next Asynchronous List Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " ASYBASE ,Address of the next asynchronous queue head to be executed by the host"
|
|
else
|
|
hgroup.long 0x148++0x03
|
|
hide.long 0x00 "USB1_CONTROLLER_USB2D_ASYNCLISTADDR_0,USB2D Next Asynchronous List Address Register"
|
|
endif
|
|
group.long 0x14C++0x0B
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_ASYNCTTSTS_0,USB2D Asynchronous Buffer Status for Embedded TT Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " TTHA ,Internal TT Hub Address representation"
|
|
bitfld.long 0x00 1. " TTAC ,Embedded TT async buffers clear" "No clear,Clear"
|
|
rbitfld.long 0x00 0. " TTAS ,Embedded TT async buffers status" "Empty,Not empty"
|
|
line.long 0x04 "USB1_CONTROLLER_USB2D_BURSTSIZE_0,USB2D Burst Size register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TXPBURST ,Programmable TX burst length"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RXPBURST ,Programmable RX burst length"
|
|
line.long 0x08 "USB1_CONTROLLER_USB2D_TXFILLTUNING_0,USB2D Transmit fill tuning register"
|
|
bitfld.long 0x08 16.--21. " TXFIFOTHRES ,FIFO burst threshold" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 8.--12. " TXSCHHEALTH ,Scheduler health counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TXSCHOH ,Scheduler overhead"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_ICUSB_CTRL_0,USB2D ICUSB control register"
|
|
bitfld.long 0x00 3. " IC_ENB1 ,ICUSB transceiver" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " IC_VDD1 ,ICUSB voltage select" "No voltage,,,,1.8V,3.0V,?..."
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_ULPI_VIEWPORT_0,USB2D ULPI viewport register"
|
|
bitfld.long 0x00 31. " ULPI_WAKEUP ,ULPI wakeup" "No effect,Wakeup"
|
|
bitfld.long 0x00 30. " ULPI_RUN ,ULPI read/write run (begin read/write operation)" "No effect,Run"
|
|
bitfld.long 0x00 29. " ULPI_RD_WR ,ULPI read/write control" "Read,Write"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " ULPI_SYNC_STATE ,ULPI sync state" "Normal,Not normal"
|
|
bitfld.long 0x00 24.--26. " ULPI_PORT ,ULPI PHY port number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ULPI_REG_ADDR ,ULPI PHY register address"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " ULPI_DATA_RD ,ULPI PHY data read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ULPI_DATA_WR ,ULPI PHY data write"
|
|
textline ""
|
|
width 41.
|
|
if (((d.l(ad:0x7D000000+0x1F8))&0x03)==0x03)
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_PORTSC1_0,USB2D Port Status/Control 1 Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " DA ,Device address"
|
|
rbitfld.long 0x00 23.--24. " SSTS ,Suspend status" "L1STATE_ENTERED,NYET_PERIPH,L1STATE_NOT_SUPPORTED,PERIPH_NORESP_ERR"
|
|
bitfld.long 0x00 22. " WKOC ,Wake on over-current" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKDS ,Wake on disconnect" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " WKCN ,Wake on connect" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port test control" "NORMAL_OP,TEST_J,TEST_K,TEST_SE0_NAK,TEST_PKT,TEST_FORCE_ENABLE,?..."
|
|
textline " "
|
|
eventfld.long 0x00 12. " PP ,Port power" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10.--11. " LS ,Line state" "SE0,J_STATE,K_STATE,Undefined"
|
|
bitfld.long 0x00 9. " SLP ,Suspend using L1" "L2,L1"
|
|
bitfld.long 0x00 8. " PR ,Port reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SUSP ,Port suspend" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FPR ,Force port resume" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEC ,Port enable/disable change" "No change,Change"
|
|
eventfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSC ,Connect status change" "No change,Change"
|
|
rbitfld.long 0x00 0. " CCS ,Current connect status" "Not connected,Connected"
|
|
elif (((d.l(ad:0x7D000000+0x1F8))&0x03)==0x02)
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_PORTSC1_0,USB2D Port Status/Control 1 Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " DA ,Device address"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port test control" "NORMAL_OP,TEST_J,TEST_K,TEST_SE0_NAK,TEST_PKT,TEST_FORCE_ENABLE,?..."
|
|
rbitfld.long 0x00 14.--15. " PIC ,Port indicator control" "0,1,2,3"
|
|
rbitfld.long 0x00 13. " PO ,Port owner" "0,1"
|
|
eventfld.long 0x00 12. " PP ,Port power" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10.--11. " LS ,Line state" "SE0,J_STATE,K_STATE,Undefined"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SLP ,Suspend using L1" "L2,L1"
|
|
rbitfld.long 0x00 8. " PR ,Port reset" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " SUSP ,Port suspend" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FPR ,Force port resume" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " OCC ,Over-current change" "No change,Change"
|
|
rbitfld.long 0x00 4. " OCA ,Over-current active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEC ,Port enable/disable change" "No change,Change"
|
|
eventfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,Current connect status" "Not connected,Connected"
|
|
else
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_PORTSC1_0,USB2D Port Status/Control 1 Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " DA ,Device address"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port test control" "NORMAL_OP,TEST_J,TEST_K,TEST_SE0_NAK,TEST_PKT,TEST_FORCE_ENABLE,?..."
|
|
rbitfld.long 0x00 14.--15. " PIC ,Port indicator control" "0,1,2,3"
|
|
rbitfld.long 0x00 13. " PO ,Port owner" "0,1"
|
|
eventfld.long 0x00 12. " PP ,Port power" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10.--11. " LS ,Line state" "SE0,J_STATE,K_STATE,Undefined"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SLP ,Suspend using L1" "L2,L1"
|
|
rbitfld.long 0x00 8. " PR ,Port reset" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " SUSP ,Port suspend" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FPR ,Force port resume" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " OCC ,Over-current change" "No change,Change"
|
|
rbitfld.long 0x00 4. " OCA ,Over-current active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEC ,Port enable/disable change" "No change,Change"
|
|
eventfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,Current connect status" "Not connected,Connected"
|
|
endif
|
|
textline ""
|
|
if (((d.l(ad:0x7D000000+0x1F8))&0x03)==0x03)
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_HOSTPC1_DEVLC_0,USB2D Host Mode LPM Behav and Control Register"
|
|
bitfld.long 0x00 29.--31. " PTS ,Parallel transceiver select" "UTMI,,ULPI,ICUSB_SER,HSIC,?..."
|
|
bitfld.long 0x00 28. " STS ,Serial transceiver" "PARALLEL_IF,SERIAL_IF"
|
|
rbitfld.long 0x00 27. " PTW ,Parallel transceiver width" "8-bit,?..."
|
|
rbitfld.long 0x00 25.--26. " PSPD ,Port operating speed" "Full,Low,High,?..."
|
|
bitfld.long 0x00 24. " ALPD ,Auto Low Power While Disconnect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PFSC ,Port force full speed connect" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PHCD ,PHY low power suspend - clock disable" "No,Yes"
|
|
bitfld.long 0x00 20.--21. " LPMX ,Auto LPM set" "Disabled,Set,Set without interrupt,?..."
|
|
bitfld.long 0x00 16.--19. " EPLPM ,Endpoint for LPM token" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " LPMFRM ,Auto LPM SOF threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 1.--11. 1. " BA ,BmAttrubuttes"
|
|
bitfld.long 0x00 0. " ASUS ,Auto low power" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x7D000000+0x1F8))&0x03)==0x02)
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_HOSTPC1_DEVLC_0,USB2D Device Mode LPM Behav and Control Register"
|
|
bitfld.long 0x00 29.--31. " PTS ,Parallel transceiver select" "UTMI,,ULPI,ICUSB_SER,HSIC,?..."
|
|
bitfld.long 0x00 28. " STS ,Serial transceiver" "PARALLEL_IF,SERIAL_IF"
|
|
rbitfld.long 0x00 27. " PTW ,Parallel transceiver width" "8-bit,?..."
|
|
rbitfld.long 0x00 25.--26. " PSPD ,Port operating speed" "Full,Low,High,?..."
|
|
bitfld.long 0x00 24. " ALPD ,Auto Low Power While Disconnect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PFSC ,Port force full speed connect" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PHCD ,PHY low power suspend - clock disable" "No,Yes"
|
|
bitfld.long 0x00 17. " ASUS ,Auto low power" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " STL ,STALL reply to LPM token" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 1.--11. 1. " BA ,BmAttrubuttes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NYT ,NYTE reply to LPM token" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_HOSTPC1_DEVLC_0,USB2D Device Mode LPM Behav and Control Register"
|
|
bitfld.long 0x00 29.--31. " PTS ,Parallel transceiver select" "UTMI,,ULPI,ICUSB_SER,HSIC,?..."
|
|
bitfld.long 0x00 28. " STS ,Serial transceiver" "PARALLEL_IF,SERIAL_IF"
|
|
rbitfld.long 0x00 27. " PTW ,Parallel transceiver width" "8-bit,?..."
|
|
rbitfld.long 0x00 25.--26. " PSPD ,Port operating speed" "Full,Low,High,?..."
|
|
bitfld.long 0x00 24. " ALPD ,Auto Low Power While Disconnect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PFSC ,Port force full speed connect" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PHCD ,PHY low power suspend - clock disable" "No,Yes"
|
|
hexmask.long.word 0x00 1.--11. 1. " BA ,BmAttrubuttes"
|
|
endif
|
|
textline ""
|
|
width 32.
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_OTGSC_0,USB2D On-The-Go (OTG) Status and Control Register"
|
|
bitfld.long 0x00 30. " DPIE ,Data pulse interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONEMSE ,1 millisecond timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " BSEIE ,B session end interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " BSVIE ,B session valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ASVIE ,A session valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " AVVIE ,A VBUS valid interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " IDIE ,USB ID interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 22. " DPIS ,Data pulse interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ONEMESS ,1 millisecond timer interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " BSEIS ,B session end interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " BSVIS ,B session valid interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ASVIS ,A session valid interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " AVVIS ,A VBUS valid interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IDIS ,USB ID interrupt toggle" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 14. " DPS ,Data pulse status" "Not detected,Detected"
|
|
rbitfld.long 0x00 13. " ONEMST ,1 millisecond timer toggle" "Low,High"
|
|
rbitfld.long 0x00 12. " BSE ,B session end threshold" "No,Yes"
|
|
rbitfld.long 0x00 11. " BSV ,B session valid threshold" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " ASV ,A session valid threshold" "No,Yes"
|
|
rbitfld.long 0x00 9. " AVV ,A VBUS valid threshold" "No,Yes"
|
|
rbitfld.long 0x00 8. " ID ,USB ID" "A-device,B-device"
|
|
bitfld.long 0x00 5. " IDPU ,USB ID pullup" "Clear,Set"
|
|
bitfld.long 0x00 4. " DP ,Data pulsing" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " OT ,OTG termination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " VC ,VBUS charge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VD ,VBUS discharge" "Disabled,Enabled"
|
|
tree.end
|
|
width 35.
|
|
if (((d.l(ad:0x7D000000+0x1F8))&0x03)==0x03)
|
|
group.long 0x1F8++0x03 "Device Mode Control"
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_USBMODE_0,USB2D USB Device Mode Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ALPDD ,Auto Low Power While Disconnect"
|
|
bitfld.long 0x00 15. " SRT ,Shorten USB reset time" "No,Yes"
|
|
rbitfld.long 0x00 4. " SDIS ,Stream disable" "No,Yes"
|
|
rbitfld.long 0x00 2. " ES ,Endian select" "Little endian,?..."
|
|
rbitfld.long 0x00 0.--1. " CM ,Controller mode" "Idle,,Device mode,Host mode"
|
|
elif (((d.l(ad:0x7D000000+0x1F8))&0x03)!=0x03)
|
|
group.long 0x1F8++0x03 "Device Mode Control"
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_USBMODE_0,USB2D USB Device Mode Register"
|
|
bitfld.long 0x00 15. " SRT ,Shorten USB reset time" "No,Yes"
|
|
rbitfld.long 0x00 4. " SDIS ,Stream disable" "No,Yes"
|
|
rbitfld.long 0x00 3. " SLOM ,Setup lockout mode" "On,Off"
|
|
rbitfld.long 0x00 2. " ES ,Endian select" "Little endian,?..."
|
|
rbitfld.long 0x00 0.--1. " CM ,Controller mode" "Idle,,Device mode,Host mode"
|
|
endif
|
|
width 42.
|
|
tree "Endpoint Setup"
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_ENDPTNAK_0,USB2D Endpoint NAK register"
|
|
bitfld.long 0x00 31. " EPTN15 ,TX endpoint NAK 15" "Clear,Set"
|
|
bitfld.long 0x00 30. " EPTN14 ,TX endpoint NAK 14" "Clear,Set"
|
|
bitfld.long 0x00 29. " EPTN13 ,TX endpoint NAK 13" "Clear,Set"
|
|
bitfld.long 0x00 28. " EPTN12 ,TX endpoint NAK 12" "Clear,Set"
|
|
bitfld.long 0x00 27. " EPTN11 ,TX endpoint NAK 11" "Clear,Set"
|
|
bitfld.long 0x00 26. " EPTN10 ,TX endpoint NAK 10" "Clear,Set"
|
|
bitfld.long 0x00 25. " EPTN9 ,TX endpoint NAK 9" "Clear,Set"
|
|
bitfld.long 0x00 24. " EPTN8 ,TX endpoint NAK 8" "Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EPTN7 ,TX endpoint NAK 7" "Clear,Set"
|
|
bitfld.long 0x00 22. " EPTN6 ,TX endpoint NAK 6" "Clear,Set"
|
|
bitfld.long 0x00 21. " EPTN5 ,TX endpoint NAK 5" "Clear,Set"
|
|
bitfld.long 0x00 20. " EPTN4 ,TX endpoint NAK 4" "Clear,Set"
|
|
bitfld.long 0x00 19. " EPTN3 ,TX endpoint NAK 3" "Clear,Set"
|
|
bitfld.long 0x00 18. " EPTN2 ,TX endpoint NAK 2" "Clear,Set"
|
|
bitfld.long 0x00 17. " EPTN1 ,TX endpoint NAK 1" "Clear,Set"
|
|
bitfld.long 0x00 16. " EPTN0 ,TX endpoint NAK 0" "Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPRN15 ,RX endpoint NAK 15" "Clear,Set"
|
|
bitfld.long 0x00 14. " EPRN14 ,RX endpoint NAK 14" "Clear,Set"
|
|
bitfld.long 0x00 13. " EPRN13 ,RX endpoint NAK 13" "Clear,Set"
|
|
bitfld.long 0x00 12. " EPRN12 ,RX endpoint NAK 12" "Clear,Set"
|
|
bitfld.long 0x00 11. " EPRN11 ,RX endpoint NAK 11" "Clear,Set"
|
|
bitfld.long 0x00 10. " EPRN10 ,RX endpoint NAK 10" "Clear,Set"
|
|
bitfld.long 0x00 9. " EPRN9 ,RX endpoint NAK 9" "Clear,Set"
|
|
bitfld.long 0x00 8. " EPRN8 ,RX endpoint NAK 8" "Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EPRN7 ,RX endpoint NAK 7" "Clear,Set"
|
|
bitfld.long 0x00 6. " EPRN6 ,RX endpoint NAK 6" "Clear,Set"
|
|
bitfld.long 0x00 5. " EPRN5 ,RX endpoint NAK 5" "Clear,Set"
|
|
bitfld.long 0x00 4. " EPRN4 ,RX endpoint NAK 4" "Clear,Set"
|
|
bitfld.long 0x00 3. " EPRN3 ,RX endpoint NAK 3" "Clear,Set"
|
|
bitfld.long 0x00 2. " EPRN2 ,RX endpoint NAK 2" "Clear,Set"
|
|
bitfld.long 0x00 1. " EPRN1 ,RX endpoint NAK 1" "Clear,Set"
|
|
bitfld.long 0x00 0. " EPRN0 ,RX endpoint NAK 0" "Clear,Set"
|
|
textline ""
|
|
line.long 0x04 "USB1_CONTROLLER_USB2D_ENDPTNAK_ENABLE_0,USB2D Endpoint NAK Enable register"
|
|
bitfld.long 0x04 31. " EPTN15 ,TX endpoint NAK enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " EPTN14 ,TX endpoint NAK enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " EPTN13 ,TX endpoint NAK enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " EPTN12 ,TX endpoint NAK enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " EPTN11 ,TX endpoint NAK enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " EPTN10 ,TX endpoint NAK enable 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " EPTN9 ,TX endpoint NAK enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " EPTN8 ,TX endpoint NAK enable 8" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " EPTN7 ,TX endpoint NAK enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " EPTN6 ,TX endpoint NAK enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " EPTN5 ,TX endpoint NAK enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " EPTN4 ,TX endpoint NAK enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " EPTN3 ,TX endpoint NAK enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " EPTN2 ,TX endpoint NAK enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " EPTN1 ,TX endpoint NAK enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " EPTN0 ,TX endpoint NAK enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " EPRN15 ,RX endpoint NAK enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " EPRN14 ,RX endpoint NAK enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " EPRN13 ,RX endpoint NAK enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " EPRN12 ,RX endpoint NAK enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " EPRN11 ,RX endpoint NAK enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " EPRN10 ,RX endpoint NAK enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " EPRN9 ,RX endpoint NAK enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EPRN8 ,RX endpoint NAK enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " EPRN7 ,RX endpoint NAK enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " EPRN6 ,RX endpoint NAK enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " EPRN5 ,RX endpoint NAK enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " EPRN4 ,RX endpoint NAK enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " EPRN3 ,RX endpoint NAK enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " EPRN2 ,RX endpoint NAK enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " EPRN1 ,RX endpoint NAK enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EPRN0 ,RX endpoint NAK enable 0" "Disabled,Enabled"
|
|
width 43.
|
|
if (((d.l(ad:0x7D000000+0x1F8))&0x03)==0x02)
|
|
group.long 0x208++0x0B
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_ENDPTSETUPSTAT_0,USB2D Endpoint Setup Status Register"
|
|
bitfld.long 0x00 15. " ENDPTSETUPSTAT15 ,Endpoint setup status 15" "Not received,Received"
|
|
bitfld.long 0x00 14. " ENDPTSETUPSTAT14 ,Endpoint setup status 14" "Not received,Received"
|
|
bitfld.long 0x00 13. " ENDPTSETUPSTAT13 ,Endpoint setup status 13" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENDPTSETUPSTAT12 ,Endpoint setup status 12" "Not received,Received"
|
|
bitfld.long 0x00 11. " ENDPTSETUPSTAT11 ,Endpoint setup status 11" "Not received,Received"
|
|
bitfld.long 0x00 10. " ENDPTSETUPSTAT10 ,Endpoint setup status 10" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ENDPTSETUPSTAT9 ,Endpoint setup status 9" "Not received,Received"
|
|
bitfld.long 0x00 8. " ENDPTSETUPSTAT8 ,Endpoint setup status 8" "Not received,Received"
|
|
bitfld.long 0x00 7. " ENDPTSETUPSTAT7 ,Endpoint setup status 7" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENDPTSETUPSTAT6 ,Endpoint setup status 6" "Not received,Received"
|
|
bitfld.long 0x00 5. " ENDPTSETUPSTAT5 ,Endpoint setup status 5" "Not received,Received"
|
|
bitfld.long 0x00 4. " ENDPTSETUPSTAT4 ,Endpoint setup status 4" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENDPTSETUPSTAT3 ,Endpoint setup status 3" "Not received,Received"
|
|
bitfld.long 0x00 2. " ENDPTSETUPSTAT2 ,Endpoint setup status 2" "Not received,Received"
|
|
bitfld.long 0x00 1. " ENDPTSETUPSTAT1 ,Endpoint setup status 1" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENDPTSETUPSTAT0 ,Endpoint setup status 0" "Not received,Received"
|
|
line.long 0x04 "USB1_CONTROLLER_USB2D_ENDPTPRIME_0,USB2D Endpoint Initialization Register"
|
|
bitfld.long 0x04 31. " PETB15 ,Prime endpoint transmit buffer 15" "Don't prime,Prime"
|
|
bitfld.long 0x04 30. " PETB14 ,Prime endpoint transmit buffer 14" "Don't prime,Prime"
|
|
bitfld.long 0x04 29. " PETB13 ,Prime endpoint transmit buffer 13" "Don't prime,Prime"
|
|
bitfld.long 0x04 28. " PETB12 ,Prime endpoint transmit buffer 12" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 27. " PETB11 ,Prime endpoint transmit buffer 11" "Don't prime,Prime"
|
|
bitfld.long 0x04 26. " PETB10 ,Prime endpoint transmit buffer 10" "Don't prime,Prime"
|
|
bitfld.long 0x04 25. " PETB9 ,Prime endpoint transmit buffer 9" "Don't prime,Prime"
|
|
bitfld.long 0x04 24. " PETB8 ,Prime endpoint transmit buffer 8" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 23. " PETB7 ,Prime endpoint transmit buffer 7" "Don't prime,Prime"
|
|
bitfld.long 0x04 22. " PETB6 ,Prime endpoint transmit buffer 6" "Don't prime,Prime"
|
|
bitfld.long 0x04 21. " PETB5 ,Prime endpoint transmit buffer 5" "Don't prime,Prime"
|
|
bitfld.long 0x04 20. " PETB4 ,Prime endpoint transmit buffer 4" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PETB3 ,Prime endpoint transmit buffer 3" "Don't prime,Prime"
|
|
bitfld.long 0x04 18. " PETB2 ,Prime endpoint transmit buffer 2" "Don't prime,Prime"
|
|
bitfld.long 0x04 17. " PETB1 ,Prime endpoint transmit buffer 1" "Don't prime,Prime"
|
|
bitfld.long 0x04 16. " PETB0 ,Prime endpoint transmit buffer 0" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 15. " PERB15 ,Prime endpoint receive buffer 15" "Don't prime,Prime"
|
|
bitfld.long 0x04 14. " PERB14 ,Prime endpoint receive buffer 14" "Don't prime,Prime"
|
|
bitfld.long 0x04 13. " PERB13 ,Prime endpoint receive buffer 13" "Don't prime,Prime"
|
|
bitfld.long 0x04 12. " PERB12 ,Prime endpoint receive buffer 12" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 11. " PERB11 ,Prime endpoint receive buffer 11" "Don't prime,Prime"
|
|
bitfld.long 0x04 10. " PERB10 ,Prime endpoint receive buffer 10" "Don't prime,Prime"
|
|
bitfld.long 0x04 9. " PERB9 ,Prime endpoint receive buffer 9" "Don't prime,Prime"
|
|
bitfld.long 0x04 8. " PERB8 ,Prime endpoint receive buffer 8" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 7. " PERB7 ,Prime endpoint receive buffer 7" "Don't prime,Prime"
|
|
bitfld.long 0x04 6. " PERB6 ,Prime endpoint receive buffer 6" "Don't prime,Prime"
|
|
bitfld.long 0x04 5. " PERB5 ,Prime endpoint receive buffer 5" "Don't prime,Prime"
|
|
bitfld.long 0x04 4. " PERB4 ,Prime endpoint receive buffer 4" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PERB3 ,Prime endpoint receive buffer 3" "Don't prime,Prime"
|
|
bitfld.long 0x04 2. " PERB2 ,Prime endpoint receive buffer 2" "Don't prime,Prime"
|
|
bitfld.long 0x04 1. " PERB1 ,Prime endpoint receive buffer 1" "Don't prime,Prime"
|
|
bitfld.long 0x04 0. " PERB0 ,Prime endpoint receive buffer 0" "Don't prime,Prime"
|
|
line.long 0x08 "USB1_CONTROLLER_USB2D_ENDPTFLUSH_0,USB2D Endpoint De-Initialization Register"
|
|
bitfld.long 0x08 31. " FETB15 ,Flush endpoint transmit buffer 15" "Don't flush,Flush"
|
|
bitfld.long 0x08 30. " FETB14 ,Flush endpoint transmit buffer 14" "Don't flush,Flush"
|
|
bitfld.long 0x08 29. " FETB13 ,Flush endpoint transmit buffer 13" "Don't flush,Flush"
|
|
bitfld.long 0x08 28. " FETB12 ,Flush endpoint transmit buffer 12" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 27. " FETB11 ,Flush endpoint transmit buffer 11" "Don't flush,Flush"
|
|
bitfld.long 0x08 26. " FETB10 ,Flush endpoint transmit buffer 10" "Don't flush,Flush"
|
|
bitfld.long 0x08 25. " FETB9 ,Flush endpoint transmit buffer 9" "Don't flush,Flush"
|
|
bitfld.long 0x08 24. " FETB8 ,Flush endpoint transmit buffer 8" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 23. " FETB7 ,Flush endpoint transmit buffer 7" "Don't flush,Flush"
|
|
bitfld.long 0x08 22. " FETB6 ,Flush endpoint transmit buffer 6" "Don't flush,Flush"
|
|
bitfld.long 0x08 21. " FETB5 ,Flush endpoint transmit buffer 5" "Don't flush,Flush"
|
|
bitfld.long 0x08 20. " FETB4 ,Flush endpoint transmit buffer 4" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 19. " FETB3 ,Flush endpoint transmit buffer 3" "Don't flush,Flush"
|
|
bitfld.long 0x08 18. " FETB2 ,Flush endpoint transmit buffer 2" "Don't flush,Flush"
|
|
bitfld.long 0x08 17. " FETB1 ,Flush endpoint transmit buffer 1" "Don't flush,Flush"
|
|
bitfld.long 0x08 16. " FETB0 ,Flush endpoint transmit buffer 0" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 15. " FERB15 ,Flush endpoint receive buffer 15" "Don't flush,Flush"
|
|
bitfld.long 0x08 14. " FERB14 ,Flush endpoint receive buffer 14" "Don't flush,Flush"
|
|
bitfld.long 0x08 13. " FERB13 ,Flush endpoint receive buffer 13" "Don't flush,Flush"
|
|
bitfld.long 0x08 12. " FERB12 ,Flush endpoint receive buffer 12" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 11. " FERB11 ,Flush endpoint receive buffer 11" "Don't flush,Flush"
|
|
bitfld.long 0x08 10. " FERB10 ,Flush endpoint receive buffer 10" "Don't flush,Flush"
|
|
bitfld.long 0x08 9. " FERB9 ,Flush endpoint receive buffer 9" "Don't flush,Flush"
|
|
bitfld.long 0x08 8. " FERB8 ,Flush endpoint receive buffer 8" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 7. " FERB7 ,Flush endpoint receive buffer 7" "Don't flush,Flush"
|
|
bitfld.long 0x08 6. " FERB6 ,Flush endpoint receive buffer 6" "Don't flush,Flush"
|
|
bitfld.long 0x08 5. " FERB5 ,Flush endpoint receive buffer 5" "Don't flush,Flush"
|
|
bitfld.long 0x08 4. " FERB4 ,Flush endpoint receive buffer 4" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 3. " FERB3 ,Flush endpoint receive buffer 3" "Don't flush,Flush"
|
|
bitfld.long 0x08 2. " FERB2 ,Flush endpoint receive buffer 2" "Don't flush,Flush"
|
|
bitfld.long 0x08 1. " FERB1 ,Flush endpoint receive buffer 1" "Don't flush,Flush"
|
|
bitfld.long 0x08 0. " FERB0 ,Flush endpoint receive buffer 0" "Don't flush,Flush"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_ENDPTSTATUS_0,USB2D Endpoint Status Register"
|
|
bitfld.long 0x00 31. " ETBR15 ,Endpoint transmit buffer ready 15" "Not ready,Ready"
|
|
bitfld.long 0x00 30. " ETBR14 ,Endpoint transmit buffer ready 14" "Not ready,Ready"
|
|
bitfld.long 0x00 29. " ETBR13 ,Endpoint transmit buffer ready 13" "Not ready,Ready"
|
|
bitfld.long 0x00 28. " ETBR12 ,Endpoint transmit buffer ready 12" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ETBR11 ,Endpoint transmit buffer ready 11" "Not ready,Ready"
|
|
bitfld.long 0x00 26. " ETBR10 ,Endpoint transmit buffer ready 10" "Not ready,Ready"
|
|
bitfld.long 0x00 25. " ETBR9 ,Endpoint transmit buffer ready 9" "Not ready,Ready"
|
|
bitfld.long 0x00 24. " ETBR8 ,Endpoint transmit buffer ready 8" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ETBR7 ,Endpoint transmit buffer ready 7" "Not ready,Ready"
|
|
bitfld.long 0x00 22. " ETBR6 ,Endpoint transmit buffer ready 6" "Not ready,Ready"
|
|
bitfld.long 0x00 21. " ETBR5 ,Endpoint transmit buffer ready 5" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " ETBR4 ,Endpoint transmit buffer ready 4" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ETBR3 ,Endpoint transmit buffer ready 3" "Not ready,Ready"
|
|
bitfld.long 0x00 18. " ETBR2 ,Endpoint transmit buffer ready 2" "Not ready,Ready"
|
|
bitfld.long 0x00 17. " ETBR1 ,Endpoint transmit buffer ready 1" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " ETBR0 ,Endpoint transmit buffer ready 0" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ERBR15 ,Endpoint receive buffer ready 15" "Not ready,Ready"
|
|
bitfld.long 0x00 14. " ERBR14 ,Endpoint receive buffer ready 14" "Not ready,Ready"
|
|
bitfld.long 0x00 13. " ERBR13 ,Endpoint receive buffer ready 13" "Not ready,Ready"
|
|
bitfld.long 0x00 12. " ERBR12 ,Endpoint receive buffer ready 12" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERBR11 ,Endpoint receive buffer ready 11" "Not ready,Ready"
|
|
bitfld.long 0x00 10. " ERBR10 ,Endpoint receive buffer ready 10" "Not ready,Ready"
|
|
bitfld.long 0x00 9. " ERBR9 ,Endpoint receive buffer ready 9" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " ERBR8 ,Endpoint receive buffer ready 8" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERBR7 ,Endpoint receive buffer ready 7" "Not ready,Ready"
|
|
bitfld.long 0x00 6. " ERBR6 ,Endpoint receive buffer ready 6" "Not ready,Ready"
|
|
bitfld.long 0x00 5. " ERBR5 ,Endpoint receive buffer ready 5" "Not ready,Ready"
|
|
bitfld.long 0x00 4. " ERBR4 ,Endpoint receive buffer ready 4" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERBR3 ,Endpoint receive buffer ready 3" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " ERBR2 ,Endpoint receive buffer ready 2" "Not ready,Ready"
|
|
bitfld.long 0x00 1. " ERBR1 ,Endpoint receive buffer ready 1" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " ERBR0 ,Endpoint receive buffer ready 0" "Not ready,Ready"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_ENDPTCOMPLETE_0,USB2D Endpoint Complete Register"
|
|
bitfld.long 0x00 31. " ETCE15 ,Endpoint transmit buffer complete event 15" "Not completed,Completed"
|
|
bitfld.long 0x00 30. " ETCE14 ,Endpoint transmit buffer complete event 14" "Not completed,Completed"
|
|
bitfld.long 0x00 29. " ETCE13 ,Endpoint transmit buffer complete event 13" "Not completed,Completed"
|
|
bitfld.long 0x00 28. " ETCE12 ,Endpoint transmit buffer complete event 12" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ETCE11 ,Endpoint transmit buffer complete event 11" "Not completed,Completed"
|
|
bitfld.long 0x00 26. " ETCE10 ,Endpoint transmit buffer complete event 10" "Not completed,Completed"
|
|
bitfld.long 0x00 25. " ETCE9 ,Endpoint transmit buffer complete event 9" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " ETCE8 ,Endpoint transmit buffer complete event 8" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ETCE7 ,Endpoint transmit buffer complete event 7" "Not completed,Completed"
|
|
bitfld.long 0x00 22. " ETCE6 ,Endpoint transmit buffer complete event 6" "Not completed,Completed"
|
|
bitfld.long 0x00 21. " ETCE5 ,Endpoint transmit buffer complete event 5" "Not completed,Completed"
|
|
bitfld.long 0x00 20. " ETCE4 ,Endpoint transmit buffer complete event 4" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ETCE3 ,Endpoint transmit buffer complete event 3" "Not completed,Completed"
|
|
bitfld.long 0x00 18. " ETCE2 ,Endpoint transmit buffer complete event 2" "Not completed,Completed"
|
|
bitfld.long 0x00 17. " ETCE1 ,Endpoint transmit buffer complete event 1" "Not completed,Completed"
|
|
bitfld.long 0x00 16. " ETCE0 ,Endpoint transmit buffer complete event 0" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ERCE15 ,Endpoint receive buffer complete event 15" "Not completed,Completed"
|
|
bitfld.long 0x00 14. " ERCE14 ,Endpoint receive buffer complete event 14" "Not completed,Completed"
|
|
bitfld.long 0x00 13. " ERCE13 ,Endpoint receive buffer complete event 13" "Not completed,Completed"
|
|
bitfld.long 0x00 12. " ERCE12 ,Endpoint receive buffer complete event 12" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERCE11 ,Endpoint receive buffer complete event 11" "Not completed,Completed"
|
|
bitfld.long 0x00 10. " ERCE10 ,Endpoint receive buffer complete event 10" "Not completed,Completed"
|
|
bitfld.long 0x00 9. " ERCE9 ,Endpoint receive buffer complete event 9" "Not completed,Completed"
|
|
bitfld.long 0x00 8. " ERCE8 ,Endpoint receive buffer complete event 8" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERCE7 ,Endpoint receive buffer complete event 7" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " ERCE6 ,Endpoint receive buffer complete event 6" "Not completed,Completed"
|
|
bitfld.long 0x00 5. " ERCE5 ,Endpoint receive buffer complete event 5" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " ERCE4 ,Endpoint receive buffer complete event 4" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERCE3 ,Endpoint receive buffer complete event 3" "Not completed,Completed"
|
|
bitfld.long 0x00 2. " ERCE2 ,Endpoint receive buffer complete event 2" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " ERCE1 ,Endpoint receive buffer complete event 1" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " ERCE0 ,Endpoint receive buffer complete event 0" "Not completed,Completed"
|
|
else
|
|
hgroup.long 0x208++0x13
|
|
hide.long 0x00 "USB1_CONTROLLER_USB2D_ENDPTSETUPSTAT_0,USB2D Endpoint Setup Status Register"
|
|
hide.long 0x04 "USB1_CONTROLLER_USB2D_ENDPTPRIME_0,USB2D Endpoint Initialization Register"
|
|
hide.long 0x08 "USB1_CONTROLLER_USB2D_ENDPTFLUSH_0,USB2D Endpoint De-Initialization Register"
|
|
hide.long 0x0C "USB1_CONTROLLER_USB2D_ENDPTSTATUS_0,USB2D Endpoint Status Register"
|
|
hide.long 0x10 "USB1_CONTROLLER_USB2D_ENDPTCOMPLETE_0,USB2D Endpoint Complete Register"
|
|
endif
|
|
tree.end
|
|
width 39.
|
|
tree "Endpoint Control"
|
|
rgroup.long 0x21C++0x03
|
|
line.long 0x00 "USB1_CONTROLLER_USB2D_ENDPTCTRL0_0,USB2D Endpoint Control 0 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
bitfld.long 0x00 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
bitfld.long 0x00 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
group.long 0x220++0x3B
|
|
line.long 0x0 "USB1_CONTROLLER_USB2D_ENDPTCTRL1_0,USB2D Endpoint Control 1 Register"
|
|
bitfld.long 0x0 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x0 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x0 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x0 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x0 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x0 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x0 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x0 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x4 "USB1_CONTROLLER_USB2D_ENDPTCTRL2_0,USB2D Endpoint Control 2 Register"
|
|
bitfld.long 0x4 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x4 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x4 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x4 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x4 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x4 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x4 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x4 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x8 "USB1_CONTROLLER_USB2D_ENDPTCTRL3_0,USB2D Endpoint Control 3 Register"
|
|
bitfld.long 0x8 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x8 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x8 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x8 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x8 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x8 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x8 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x8 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x8 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x8 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0xC "USB1_CONTROLLER_USB2D_ENDPTCTRL4_0,USB2D Endpoint Control 4 Register"
|
|
bitfld.long 0xC 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0xC 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0xC 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0xC 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0xC 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0xC 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0xC 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0xC 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0xC 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0xC 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x10 "USB1_CONTROLLER_USB2D_ENDPTCTRL5_0,USB2D Endpoint Control 5 Register"
|
|
bitfld.long 0x10 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x10 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x10 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x10 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x10 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x10 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x10 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x14 "USB1_CONTROLLER_USB2D_ENDPTCTRL6_0,USB2D Endpoint Control 6 Register"
|
|
bitfld.long 0x14 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x14 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x14 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x14 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x14 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x14 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x14 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x14 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x18 "USB1_CONTROLLER_USB2D_ENDPTCTRL7_0,USB2D Endpoint Control 7 Register"
|
|
bitfld.long 0x18 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x18 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x18 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x18 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x18 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x18 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x18 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x18 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x18 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x1C "USB1_CONTROLLER_USB2D_ENDPTCTRL8_0,USB2D Endpoint Control 8 Register"
|
|
bitfld.long 0x1C 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x1C 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x1C 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x1C 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x1C 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x1C 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x1C 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x20 "USB1_CONTROLLER_USB2D_ENDPTCTRL9_0,USB2D Endpoint Control 9 Register"
|
|
bitfld.long 0x20 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x20 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x20 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x20 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x20 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x20 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x20 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x20 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x20 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x24 "USB1_CONTROLLER_USB2D_ENDPTCTRL10_0,USB2D Endpoint Control 10 Register"
|
|
bitfld.long 0x24 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x24 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x24 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x24 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x24 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x24 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x24 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x24 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x24 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x28 "USB1_CONTROLLER_USB2D_ENDPTCTRL11_0,USB2D Endpoint Control 11 Register"
|
|
bitfld.long 0x28 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x28 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x28 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x28 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x28 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x28 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x28 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x28 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x28 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x2C "USB1_CONTROLLER_USB2D_ENDPTCTRL12_0,USB2D Endpoint Control 12 Register"
|
|
bitfld.long 0x2C 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x2C 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x2C 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x2C 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x2C 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x2C 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x2C 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x2C 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x30 "USB1_CONTROLLER_USB2D_ENDPTCTRL13_0,USB2D Endpoint Control 13 Register"
|
|
bitfld.long 0x30 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x30 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x30 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x30 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x30 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x30 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x30 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x30 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x30 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x34 "USB1_CONTROLLER_USB2D_ENDPTCTRL14_0,USB2D Endpoint Control 14 Register"
|
|
bitfld.long 0x34 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x34 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x34 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x34 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x34 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x34 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x34 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x34 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x34 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x38 "USB1_CONTROLLER_USB2D_ENDPTCTRL15_0,USB2D Endpoint Control 15 Register"
|
|
bitfld.long 0x38 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x38 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x38 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x38 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x38 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x38 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x38 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x38 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x38 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x38 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
tree.end
|
|
tree.end
|
|
width 28.
|
|
tree "USB 1 Controller Interface"
|
|
if (((d.l(ad:0x7D000000+0x1F8))&0x03)==0x02)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "USB1_IF_USB_SUSP_CTRL_0,USB suspend control register"
|
|
bitfld.long 0x00 25. " UTMIP_SUSPL1_SET ,Enable SuspendL1 for UTMIP PHY" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " USB_WAKEUP_DEBOUNCE_COUNT ,USB PHY wakeup debounce counter" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12. " UTMIP_PHY_ENB ,Enable UTMIP PHY mode" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " UTMIP_RESET ,Reset goint to UTMIP PHY" "Not reset,Reset"
|
|
bitfld.long 0x00 10. " USB_SUSUP_POL ,Polarity of the suspend signal going to USB PHY" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 9. " USB_PHY_CLK_VALID_INT_ENB ,USB PHY clock valid interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " USB_PHY_CLK_VALID_INT_STS ,USB PHY clock valid interrupt status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " USB_PHY_CLK_VALID ,USB PHY clock valid status" "Invalid,Valid"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " USB_CLKEN ,USB AHB clock enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " USB_SUSP_CLR ,PHY suspend mode control" "Suspended,Not suspended"
|
|
bitfld.long 0x00 4. " USB_WAKE_ON_DISCON_EN_DEV ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USB_WAKE_ON_CNNT_EN_DEV ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " USB_WAKE_ON_RESUME_EN ,Wake on resume" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " USB_WAKEUP_INT_ENB ,USB wakeup interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " USB_WAKEUP_INT_STS ,USB wakeup interrupt status" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "USB1_IF_USB_SUSP_CTRL_0,USB suspend control register"
|
|
bitfld.long 0x00 26. " FAST_WAKEUP_RESP ,Enable fast response from UTMIP PHY for a remote wakeup request from device" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " UTMIP_SUSPL1_SET ,Enable SuspendL1 for UTMIP PHY" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " USB_WAKEUP_DEBOUNCE_COUNT ,USB PHY wakeup debounce counter" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12. " UTMIP_PHY_ENB ,Enable UTMIP PHY mode" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " UTMIP_RESET ,Reset goint to UTMIP PHY" "Not reset,Reset"
|
|
bitfld.long 0x00 10. " USB_SUSUP_POL ,Polarity of the suspend signal going to USB PHY" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 9. " USB_PHY_CLK_VALID_INT_ENB ,USB PHY clock valid interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " USB_PHY_CLK_VALID_INT_STS ,USB PHY clock valid interrupt status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " USB_PHY_CLK_VALID ,USB PHY clock valid status" "Invalid,Valid"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " USB_CLKEN ,USB AHB clock enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " USB_SUSP_CLR ,PHY suspend mode control" "Suspended,Not suspended"
|
|
bitfld.long 0x00 2. " USB_WAKE_ON_RESUME_EN ,Wake on resume" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " USB_WAKEUP_INT_ENB ,USB wakeup interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " USB_WAKEUP_INT_STS ,USB wakeup interrupt status" "No interrupt,Interrupt"
|
|
endif
|
|
textline ""
|
|
width 34.
|
|
group.long 0x404++0x07
|
|
line.long 0x00 "USB1_IF_USB_PHY_VBUS_SENSORS_0,USB PHY VBUS SENSORS control register"
|
|
bitfld.long 0x00 30. " A_VBUS_VLD_WAKEUP_EN ,A_VBUS_VLD wakeup enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " A_VBUS_VLD_DEB_SEL_B ,A_VBUS_VLD debounce A/B select" "SEL_A,SEL_B"
|
|
bitfld.long 0x00 28. " A_VBUS_VLD_SW_VALUE ,A_VBUS_VLD software value (software enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " A_VBUS_VLD_SW_EN ,A_VBUS_VLD software enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " A_VBUS_VLD_STS ,A_VBUS_VLD status" "Low,High"
|
|
rbitfld.long 0x00 25. " A_VBUS_VLD_CHG_DET ,A_VBUS_VLD change detect" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 24. " A_VBUS_VLD_INT_EN ,A_VBUS_VLD interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " A_SESS_VLD_WAKEUP_EN ,A_SESS_VLD wakeup enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " A_SESS_VLD_DEB_SEL_B ,A_SESS_VLD debounce A/B select" "SEL_A,SEL_B"
|
|
textline " "
|
|
bitfld.long 0x00 20. " A_SESS_VLD_SW_VALUE ,A_SESS_VLD software value (software enabled)" "Low,High"
|
|
bitfld.long 0x00 19. " A_SESS_VLD_SW_EN ,A_SESS_VLD software enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 18. " A_SESS_VLD_STS ,A_SESS_VLD status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " A_SESS_VLD_CHG_DET ,A_SESS_VLD change detect" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " A_SESS_VLD_INT_EN ,A_SESS_VLD interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " B_SESS_VLD_WAKEUP_EN ,B_SESS_VLD wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B_SESS_VLD_DEB_SEL_B ,B_SESS_VLD debounce A/B select" "SEL_A,SEL_B"
|
|
bitfld.long 0x00 12. " B_SESS_VLD_SW_VALUE ,B_SESS_VLD software value (software enabled)" "Low,High"
|
|
bitfld.long 0x00 11. " B_SESS_VLD_SW_EN ,B_SESS_VLD software enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " B_SESS_VLD_STS ,B_SESS_VLD status" "Low,High"
|
|
rbitfld.long 0x00 9. " B_SESS_VLD_CHG_DET ,B_SESS_VLD change detect" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " B_SESS_VLD_INT_EN ,B_SESS_VLD interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " B_SESS_END_WAKEUP_EN ,B_SESS_END wakeup enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " B_SESS_END_DEB_SEL_B ,B_SESS_END debounce A/B select" "SEL_A,SEL_B"
|
|
bitfld.long 0x00 4. " B_SESS_END_SW_VALUE ,B_SESS_END software value (software enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B_SESS_END_SW_EN ,B_SESS_END software enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " B_SESS_END_STS ,B_SESS_END status" "Low,High"
|
|
rbitfld.long 0x00 1. " B_SESS_END_CHG_DET ,B_SESS_END change detect" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " B_SESS_END_INT_EN ,B_SESS_END interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0,USB PHY VBUS wakeup and ID control register"
|
|
bitfld.long 0x04 31. " DIV_DET_EN ,Battery charger divider detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " VBUS_WAKEUP_WAKEUP_EN ,VBUS_WAKEUP wakeup enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " VDCD_DET_DEB_SEL_B ,VCDT_DET debounce A/B select" "SEL_A,SEL_B"
|
|
textline " "
|
|
bitfld.long 0x04 28. " VDCD_DET_SW_VALUE ,VDCD_DET software value (software enabled)" "Low,High"
|
|
bitfld.long 0x04 27. " VDCD_DET_SW_EN ,VDCD_DET software enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 26. " VDCD_DET_STS ,VDCD_DET status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x04 25. " VDCD_DET_CHG_DET ,VDCD_DET change detect" "Not detected,Detected"
|
|
bitfld.long 0x04 24. " VDCD_DET_INT_EN ,VDCD_DET interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 23. " VOP_DIV2P7_DET ,Status bit is from the battery charging divider circuit of the USB2OTG pad" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x04 22. " VOP_DIV2P0_DET ,Status bit is from the battery charging divider circuit of the USB2OTG pad" "Low,High"
|
|
bitfld.long 0x04 21. " VDAT_DET_DEB_SEL_B ,VDAT_DET debounce A/B select" "SEL_A,SEL_B"
|
|
bitfld.long 0x04 20. " VDAT_DET_SW_VALUE ,VDAT_DET software value (software enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 19. " VDAT_DET_SW_EN ,VDAT_DET software enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 18. " VDAT_DET_STS ,VDAT_DET status" "Low,High"
|
|
rbitfld.long 0x04 17. " VDAT_DET_CHG_DET ,VDAT_DET change detect" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 16. " VDAT_DET_INT_EN ,VDAT_DET interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " VON_DIV2P7_DET ,Status bit is from the battery charging divider circuit of the USB2OTG pad" "Low,High"
|
|
bitfld.long 0x04 14. " VON_DIV2P0_DET ,Status bit is from the battery charging divider circuit of the USB2OTG pad" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 13. " VBUS_WAKEUP_DEB_SEL_B ,VBUS_WAKEUP debounce A/B select" "SEL_A,SEL_B"
|
|
bitfld.long 0x04 12. " VBUS_WAKEUP_SW_VALUE ,VBUS wakeup software value (software enabled)" "Low,High"
|
|
bitfld.long 0x04 11. " VBUS_WAKEUP_SW_EN ,VBUS wakeup software enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 10. " VBUS_WAKEUP_STS ,VBUS wakeup status" "Low,High"
|
|
rbitfld.long 0x04 9. " VBUS_WAKEUP_CHG_DET ,VBUS wakeup change detect" "Not detected,Detected"
|
|
bitfld.long 0x04 8. " VBUS_WAKEUP_INT_EN ,VBUS wakeup interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 7. " STATIC_GPI ,Static GPI status" "Low,High"
|
|
bitfld.long 0x04 6. " ID_PU ,ID pullup enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " ID_DEB_SEL_B ,ID debounce A/B select" "SEL_A,SEL_B"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ID_SW_VALUE ,ID software value (software enabled)" "Low,High"
|
|
bitfld.long 0x04 3. " ID_SW_EN ,ID software enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 2. " ID_STS ,ID status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " ID_CHG_DET ,ID change detect" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " ID_INT_EN ,ID interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "USB1_IF_USB_PHY_ALT_VBUS_STS_0,USB PHY Alternate VBUS status register"
|
|
bitfld.long 0x00 14. " ID_DIG_C_ALT ,IDDIG_C alternate status" "Low,High"
|
|
bitfld.long 0x00 13. " ID_DIG_C ,IDDIG_C status" "Low,High"
|
|
bitfld.long 0x00 12. " ID_DIG_B_ALT ,IDDIG_B alternate status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ID_DIG_B ,IDDIG_B status" "Low,High"
|
|
bitfld.long 0x00 10. " ID_DIG_A_ALT ,IDDIG_A alternate status" "Low,High"
|
|
bitfld.long 0x00 9. " ID_DIG_A ,IDDIG_A status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VDCD_DET_ALT ,VDCD_DET alternate status" "Low,High"
|
|
bitfld.long 0x00 7. " VDAT_DET_ALT ,VDAT_DET alternate status" "Low,High"
|
|
bitfld.long 0x00 6. " A_SESS_VLD_ALT ,A_SESS_VLD alternate status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B_SESS_VLD_ALT ,B_SESS_VLD alternate status" "Low,High"
|
|
bitfld.long 0x00 4. " ID_DIG_ALT ,ID alternate status" "Low,High"
|
|
bitfld.long 0x00 3. " B_SESS_END_ALT ,B_SESS_END alternate status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " STATIC_GPI_ALT ,Static GPI alternate status" "Low,High"
|
|
bitfld.long 0x00 1. " A_VBUS_VLD_ALT ,A_VBUS_VLD alternate status" "Low,High"
|
|
bitfld.long 0x00 0. " VBUS_WAKEUP_ALT ,Vbus wakeup alternate status" "Low,High"
|
|
textline ""
|
|
width 36.
|
|
if (((d.l(ad:0x7D000000+0x1F8))&0x03)==0x03)
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "USB1_IF_USB_INTER_PKT_DELAY_CTRL_0,Inter packet delay control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " IP_DELAY_TX2TX_HS ,HS Tx to Tx inter-packet delay"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "USB1_IF_USB_RSM_DLY_0,USB Controller Resume Signalling Delay"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIME_TO_RESUME ,Send the resume back in no. of 60 MHz cycles"
|
|
else
|
|
hgroup.long 0x420++0x03
|
|
hide.long 0x00 "USB1_IF_USB_INTER_PKT_DELAY_CTRL_0,Inter packet delay control"
|
|
hgroup.long 0x490++0x03
|
|
hide.long 0x00 "USB1_IF_USB_RSM_DLY_0,USB Controller Resume Signalling Delay"
|
|
endif
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "USB1_IF_SPARE_0,ICUSB PADCTLS Spare Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPARE_HI ,Spare register bits"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPARE_LO ,Spare register bits"
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "USB1_IF_USB1_NEW_CONTROL_0,USB Coherency and Memory Alignment Controls"
|
|
hexmask.long.byte 0x00 8.--15. 1. " REQUEST_EXPIRY_COUNTER ,Time to wait for coalescing the request"
|
|
bitfld.long 0x00 1. " MEM_ALIGNMENT_MUX_EN ,DMA request generation mechanism" "Tegra 3,Tegra K1"
|
|
bitfld.long 0x00 0. " COHERENCY_EN ,Enable fence mechanism" "Disabled,Enabled"
|
|
tree.end
|
|
width 28.
|
|
tree "USB 1 UTMIP Configuration"
|
|
group.long 0x808++0x37
|
|
line.long 0x00 "USB1_UTMIP_XCVR_CFG0_0,UTMIP transceiver cell configuration register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. " UTMIP_XCVR_HSSLEW_MSB ,Most significant bits of HS_SLEW"
|
|
bitfld.long 0x00 22.--24. " UTMIP_XCVR_SETUP_MSB ,Most significant bits of SETUP" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
eventfld.long 0x00 21. " UTMIP_XCVR_LSBIAS_SEL ,Low speed bias selection method for usb transceiver pad" "0,1"
|
|
bitfld.long 0x00 20. " UTMIP_XCVR_DISCON_METHOD ,Disconnect method on the usb transceiver pad" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " UTMIP_FORCE_PDZI_POWERUP ,Force PDZI input into power up" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " UTMIP_FORCE_PDZI_POWERDOWN ,Force PDZI input into power down" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " UTMIP_FORCE_PD2_POWERUP ,Force PD2 input into power up" "Disabled,Enabled"
|
|
eventfld.long 0x00 16. " UTMIP_FORCE_PD2_POWERDOWN ,Force PD2 input into power down" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " UTMIP_FORCE_PD_POWERUP ,Force PD input into power up" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " UTMIP_FORCE_PD_POWERDOWN ,Force PD input into power down" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 13. " UTMIP_XCVR_TERMEN ,Enable HS termination" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UTMIP_XCVR_HSLOOPBACK ,Internal loopback inside XCVR cell" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " UTMIP_XCVR_LSFSLEW ,LS falling slew rate control" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " UTMIP_XCVR_LSRSLEW ,LS rising slew rate control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " UTMIP_XCVR_FSSLEW ,FS slew rate control" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " UTMIP_XCVR_HSSLEW ,HS slew rate control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " UTMIP_XCVR_SETUP ,SETUP[3:0] input of XCVR cell" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "USB1_UTMIP_BIAS_CFG0_0,UTMIP Bias cell configuration register 0"
|
|
bitfld.long 0x04 30. " UTMIP_IDDIG_C_VAL ,UTMIP IDDIG C VAL" "0,1"
|
|
bitfld.long 0x04 29. " UTMIP_IDDIG_C_SEL ,UTMIP IDDIG C SEL" "IdDig_c,IDDIG_C_VAL"
|
|
textline " "
|
|
bitfld.long 0x04 28. " UTMIP_IDDIG_B_VAL ,UTMIP IDDIG B VAL" "0,1"
|
|
bitfld.long 0x04 27. " UTMIP_IDDIG_B_SEL ,UTMIP IDDIG B SEL" "IdDig_b,IDDIG_B_VAL"
|
|
textline " "
|
|
bitfld.long 0x04 26. " UTMIP_IDDIG_A_VAL ,UTMIP IDDIG A VAL" "0,1"
|
|
bitfld.long 0x04 25. " UTMIP_IDDIG_A_SEL ,UTMIP IDDIG A SEL" "IdDig_a,IDDIG_A_VAL"
|
|
textline " "
|
|
bitfld.long 0x04 24. " UTMIP_HSDISCON_LEVEL_MSB ,Most significant bit of UTMIP_HSDISCON_LEVEL" "0,1"
|
|
eventfld.long 0x04 23. " UTMIP_IDPD_VAL ,IDPD value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 21. " UTMIP_IDDIG_SEL ,IDDIG value" "0,1"
|
|
bitfld.long 0x04 20. " UTMIP_IDDIG_SEL ,IDDIG select" "IdDig,IDDIG_VAL"
|
|
textline " "
|
|
bitfld.long 0x04 19. " UTMIP_GPI_VAL ,GPI value" "0,1"
|
|
bitfld.long 0x04 18. " UTMIP_GPI_SEL ,GPI select" "IdDig,GPI_VAL"
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " UTMIP_ACTIVE_TERM_OFFSET ,Active termination control offset" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 12.--14. " UTMIP_ACTIVE_PULLUP_OFFSET ,Active 1.5K pullup control offset" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
eventfld.long 0x04 11. " UTMIP_OTGPD ,Power down OTG circuit" "Disabled,Enabled"
|
|
eventfld.long 0x04 10. " UTMIP_BIASPD ,Power down bias circuit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " UTMIP_VBUS_LEVEL_LEVEL ,Vbus detector level" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " UTMIP_SESS_LEVEL_LEVEL ,SessionEnd detector level" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " UTMIP_HSCHIRP_LEVEL ,HS chirp detector level" "0,1,2,3"
|
|
bitfld.long 0x04 2.--3. " UTMIP_HSDISCON_LEVEL ,HS disconnect detector level" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " UTMIP_HSSQUELCH_LEVEL ,HS squelch detector level" "0,1,2,3"
|
|
line.long 0x08 "USB1_UTMIP_HSRX_CFG0_0,UTMIP High speed receive config 0"
|
|
bitfld.long 0x08 30.--31. " UTMIP_KEEP_PATT_ON_ACTIVE ,Keep the stay alive pattern on active" "0,1,2,3"
|
|
bitfld.long 0x08 29. " UTMIP_ALLOW_CONSEC_UPDN ,Allow consecutive ups and downs on the bits" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 28. " UTMIP_REALIGN_ON_NEW_PKT ,Realign the inertia counters on a new packet" "Disabled,Enabled"
|
|
bitfld.long 0x08 24.--27. " UTMIP_PCOUNT_UPDN_DIV ,The number of (edges-1) needed to move the sampling point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 21.--23. " UTMIP_SQUELCH_EOP_DLY ,Limit the delay of the squelch at EOP time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 20. " UTMIP_NO_STRIPPING ,Do not strip incoming data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15.--19. " UTMIP_IDLE_WAIT ,Number of cycles of idle to declare IDLE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 10.--14. " UTMIP_ELASTIC_LIMIT ,Depth of elastic input store" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 9. " UTMIP_ELASTIC_OVERRUN_DISABLE ,Do not declare overrun errors until overflow of FIFO" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " UTMIP_ELASTIC_UNDERRUN_DISABLE ,Do not declare underrun errors" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " UTMIP_PASS_CHIRP ,When in Chirp Mode, allow chirp rx data through" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " UTMIP_PASS_FEEDBACK ,Pass through the feedback, do not block it" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " UTMIP_PCOUNT_INERTIA ,Retime the path" "0,1,2,3"
|
|
bitfld.long 0x08 2.--3. " UTMIP_PHASE_ADJUST ,Based on incoming edges and current sampling position phase adjust" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 1. " UTMIP_THREE_SYNCBITS ,Sync pattern detection needs 3 consecutive samples instead of 4" "No,Yes"
|
|
bitfld.long 0x08 0. " UTMIP_USE4SYNC_TRAN ,Require 4 sync pattern transitions (01) instead of 3" "No,Yes"
|
|
line.long 0x0C "USB1_UTMIP_HSRX_CFG1_0,UTMIP High speed receive config 1"
|
|
bitfld.long 0x0C 1.--5. " UTMIP_HS_SYNC_START_DLY ,How long to wait before start of sync launches RxActive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 0. " UTMIP_HS_ALLOW_KEEP_ALIVE ,Allow Keep Alive packets" "Disabled,Enabled"
|
|
line.long 0x10 "USB1_UTMIP_FSLSRX_CFG0_0,UTMIP full and Low speed receive config 0"
|
|
bitfld.long 0x10 31. " UTMIP_FSLS_SE1_DRIBBLE_FILTER ,Don't allow dribble" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " UTMIP_FSLS_SE1_FILTER ,Filter SE1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 29. " UTMIP_FSLS_SERIAL_SE0_RCV ,UTMIP_FSLS_SERIAL_SE0_RCV" "0,1"
|
|
bitfld.long 0x10 26.--28. " UTMIP_FSLS_UPR_DRIBBLE_SIZE ,Do not allow <= dribble bits" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 23.--25. " UTMIP_FSLS_LWR_DRIBBLE_SIZE ,Do not allow >= dribble bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 22. " UTMIP_FSLS_EOP_ENDS_AT_SE0 ,Only look for transitioning out of EOP" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x10 16.--21. " UTMIP_FSLS_KCOUNT_MAX ,Number of K bits in question" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 15. " UTMIP_FSLS_KCOUNT_LIMIT ,Limit the number of bit times a K can last" "No,Yes"
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textline " "
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bitfld.long 0x10 14. " UTMIP_FSLS_ACTIVE_ON_FULL_SYNC ,Require a full sync pattern to declare the data received" "No,Yes"
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bitfld.long 0x10 8.--13. " UTMIP_FSLS_IDLE_WAIT_MAX ,IDLE wait max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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textline " "
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bitfld.long 0x10 7. " UTMIP_FSLS_IDLE_WAIT_LIMIT ,Enable the reset of the state machine on extended SE0" "Disabled,Enabled"
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bitfld.long 0x10 1.--6. " UTMIP_FSLS_IDLE_COUNT_MAX ,Idle count max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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textline " "
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bitfld.long 0x10 0. " UTMIP_FSLS_IDLE_COUNT_LIMIT ,Give up on packet if a long sequence of J" "No,Yes"
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line.long 0x14 "USB1_UTMIP_FSLSRX_CFG1_0,UTMIP full and Low speed receive config 1"
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bitfld.long 0x14 26. " UTMIP_EARLY_LINE_STATE_FILTER ,Assumes line state filtering table is inclusive" "No,Yes"
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bitfld.long 0x14 23.--25. " UTMIP_LS_BOUNCE_LENGTH ,Number of clock cycle of LS stable" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x14 17.--22. " UTMIP_LS_EXTRACTION_COUNT ,Phase count on which LS bits are extracted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 11.--16. " UTMIP_LS_EOP_START_COUNT ,Number of SEO clock cycles to block bit extraction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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textline " "
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bitfld.long 0x14 5.--10. " UTMIP_LS_SE0_COUNT ,Only for this number of 60MHz of SEO and Idle to end packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 4. " UTMIP_LS_LENIENT_DRIBBLE ,Allow for large dribble in low speed mode" "Disabled,Enabled"
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textline " "
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bitfld.long 0x14 3. " UTMIP_FS_LENIENT_DRIBBLE ,Allow for large dribble in full speed mode" "Disabled,Enabled"
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bitfld.long 0x14 2. " UTMIP_FS_WEAK_SYNC ,Only look for a KK pattern instead of KJKK" "No,Yes"
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textline " "
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bitfld.long 0x14 1. " UTMIP_FS_DEBOUNCE ,Whether full speed uses debouncing" "No,Yes"
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bitfld.long 0x14 0. " UTMIP_FS_EOP_LENGTH ,Whether full speed EOP is determined within 3(0) or 4(1) 60MHz cycles" "3 cycles,4 cycles"
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line.long 0x18 "USB1_UTMIP_TX_CFG0_0,UTMIP transmit config signals"
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bitfld.long 0x18 19. " UTMIP_FS_PREAMBLE_J ,Output enable sends an initial J before sync pattern" "Disabled,Enabled"
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bitfld.long 0x18 18. " UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE ,Output enable turns off 1/2 cycle after" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 17. " UTMIP_FS_PREAMBLE_OUTPUT_ENABLE ,Output enable turns on 1/2 cycle before" "Disabled,Enabled"
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bitfld.long 0x18 16. " UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR ,Allow SOP to be source of transmit error stuffing" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 15. " UTMIP_HS_READY_WAIT_FOR_VALID ,UTMIP_HS_READY_WAIT_FOR_VALID" "0,1"
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bitfld.long 0x18 10.--14. " UTMIP_HS_TX_IPG_DLY ,UTMIP_HS_TX_IPG_DLY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x18 9. " UTMIP_HS_DISCON_EOP_ONLY ,Only check during EOP" "No,Yes"
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bitfld.long 0x18 8. " UTMIP_HS_DISCON_DISABLE ,Disable high speed disconnect" "Enabled,Disabled"
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textline " "
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bitfld.long 0x18 7. " UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE ,Output enable turns off 1 cycle after" "Disabled,Enabled"
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bitfld.long 0x18 6. " UTMIP_HS_PREAMBLE_OUTPUT_ENABLE ,Output enable turns on 1 cycle before" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 5. " UTMIP_SIE_RESUME_ON_LINESTATE ,SIE (not macrocell) detects LineState change to resume" "No,Yes"
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bitfld.long 0x18 4. " UTMIP_SOF_ON_NO_STUFF ,Sof when OpMode 3 -- perhaps, when sending controller made packets" "0,1"
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textline " "
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bitfld.long 0x18 3. " UTMIP_SOF_ON_NO_ENCODE ,Sof when OpMode 2 -- not likely, for Chirp" "0,1"
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bitfld.long 0x18 2. " UTMIP_NO_STUFFING ,No bit stuffing, static programming" "0,1"
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textline " "
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bitfld.long 0x18 1. " UTMIP_NO_ENCODING ,No encoding, static programming" "0,1"
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bitfld.long 0x18 0. " UTMIP_NO_SYNC_NO_EOP ,Do not sent SYNC or EOP" "Disabled,Enabled"
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line.long 0x1C "USB1_UTMIP_MISC_CFG0_0,UTMIP miscellaneous configurations"
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bitfld.long 0x1C 27.--30. " UTMIP_DPDM_OBSERVE_SEL ,Select DP/DM obs signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 26. " UTMIP_DPDM_OBSERVE ,Use DP/DM as obs bus" "0,1"
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textline " "
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bitfld.long 0x1C 25. " UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON ,UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON" "0,1"
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bitfld.long 0x1C 24. " UTMIP_ALLOW_LS_ON_SOFT_DISCON ,UTMIP_ALLOW_LS_ON_SOFT_DISCON" "0,1"
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textline " "
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bitfld.long 0x1C 23. " UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP ,UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP" "0,1"
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bitfld.long 0x1C 22. " UTMIP_SUSPEND_EXIT_ON_EDGE ,Suspend exit requires edge or simply a value" "0,1"
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textline " "
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bitfld.long 0x1C 21. " UTMIP_LS_TO_FS_SKIP_4MS ,Don't block changes for 4ms when going from LS to FS" "0,1"
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bitfld.long 0x1C 19.--20. " UTMIP_INJECT_ERROR_TYPE ,Force error insertion into RX path" "Disabled,BIT_ERR,RX_ERR,BIT_RX_ERR"
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textline " "
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bitfld.long 0x1C 18. " UTMIP_FORCE_HS_CLOCK_ON ,Force HS clock always on" "Disabled,Enabled"
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bitfld.long 0x1C 17. " UTMIP_DISABLE_HS_TERM ,Force HS termination inactive" "Disabled,Enabled"
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textline " "
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bitfld.long 0x1C 16. " UTMIP_FORCE_HS_TERM ,Force HS termination active" "Disabled,Enabled"
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bitfld.long 0x1C 15. " UTMIP_DISABLE_PULLUP_DP ,Force DP pullup inactive" "Disabled,Enabled"
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textline " "
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bitfld.long 0x1C 14. " UTMIP_DISABLE_PULLUP_DM ,Force DM pullup inactive" "Disabled,Enabled"
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bitfld.long 0x1C 13. " UTMIP_DISABLE_PULLDN_DP ,Force DP pulldown inactive" "Disabled,Enabled"
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textline " "
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bitfld.long 0x1C 12. " UTMIP_DISABLE_PULLDN_DM ,Force DM pulldown inactive" "Disabled,Enabled"
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bitfld.long 0x1C 11. " UTMIP_FORCE_PULLUP_DP ,Force DP pullup active" "Disabled,Enabled"
|
|
textline " "
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bitfld.long 0x1C 10. " UTMIP_FORCE_PULLUP_DM ,Force DM pullup active" "Disabled,Enabled"
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bitfld.long 0x1C 9. " UTMIP_FORCE_PULLDN_DP ,Force DP pulldown active" "Disabled,Enabled"
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textline " "
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bitfld.long 0x1C 8. " UTMIP_FORCE_PULLDN_DM ,Force DM pulldown active" "Disabled,Enabled"
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bitfld.long 0x1C 5.--7. " UTMIP_STABLE_COUNT ,Number of cycles of crystal clock of signal not changing to consider stable" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x1C 4. " UTMIP_STABLE_ALL ,Determines if all signal need to be stable to not change a config" "No,Yes"
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bitfld.long 0x1C 3. " UTMIP_NO_FREE_ON_SUSPEND ,Don't use free running terminations during suspend" "Disabled,Enabled"
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textline " "
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bitfld.long 0x1C 2. " UTMIP_NEVER_FREE_RUNNING_TERMS ,Ignore free running terminations, even when no clock" "Disabled,Enabled"
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bitfld.long 0x1C 1. " UTMIP_ALWAYS_FREE_RUNNING_TERMS ,Use free running terminations at all time" "Disabled,Enabled"
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textline " "
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bitfld.long 0x1C 0. " UTMIP_COMB_TERMS ,Use combinational terminations or synced through CLKXTAL" "Disabled,Enabled"
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line.long 0x20 "USB1_UTMIP_MISC_CFG1_0,UTMIP miscellaneous configurations"
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bitfld.long 0x20 30. " UTMIP_PHY_XTAL_CLOCKEN ,Selects whether to enable the crystal clock in the module" "Disabled,Enabled"
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bitfld.long 0x20 29. " UTMIP_LINESTATE_BYPASS ,Bypass LineState reclocking logic" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 28. " UTMIP_LINESTATE_NEG ,Use neg edge sync for linestate" "Disabled,Enabled"
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bitfld.long 0x20 27. " UTMIP_LINESTATE_XCVRSEL3 ,0 ,Use FS filtering on line state when XcvrSel=3" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 25.--26. " UTMIP_OBS_SEL ,UTMIP_OBS_SEL" "0,1,2,3"
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bitfld.long 0x20 24. " UTMIP_FSLS_TDM ,UTMIP_FSLS_TDM" "0,1"
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textline " "
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bitfld.long 0x20 23. " UTMIP_FORCE_IOBIST_CLK_ON ,UTMIP_FORCE_IOBIST_CLK_ON" "0,1"
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textline " "
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bitfld.long 0x20 5. " UTMIP_RX_ERROR_CNT_CLR ,UTMIP_RX_ERROR_CNT_CLR" "0,1"
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bitfld.long 0x20 4. " UTMIP_RX_ERROR_CNT_EN ,UTMIP_RX_ERROR_CNT_EN" "0,1"
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textline " "
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bitfld.long 0x20 3. " UTMIP_FLIP_FSLS_POLARITY ,UTMIP_FLIP_FSLS_POLARITY" "0,1"
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bitfld.long 0x20 2. " UTMIP_SUSPEND_TERMSEL ,UTMIP_SUSPEND_TERMSEL" "0,1"
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textline " "
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bitfld.long 0x20 1. " UTMIP_XCVRSEL3_1 ,EOP detection" "Enabled,Disabled"
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bitfld.long 0x20 0. " UTMIP_XCVRSEL3_0 ,UTMIP_XCVRSEL3_0" "KeepAlive,Regular"
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line.long 0x24 "USB1_UTMIP_DEBOUNCE_CFG0_0,UTMIP Avalid and Bvalid debounce"
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hexmask.long.word 0x24 16.--31. 1. " UTMIP_BIAS_DEBOUNCE_B ,Simulation value -- Used for interrupts"
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hexmask.long.word 0x24 0.--15. 1. " UTMIP_BIAS_DEBOUNCE_A ,Simulation value -- Used for interrupts"
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line.long 0x28 "USB1_UTMIP_BAT_CHRG_CFG0_0,UTMIP battery charger configuration"
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bitfld.long 0x28 8.--13. " UTMIP_CHRG_DEBOUNCE_TIMESCALE ,Debouncer time scaling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x28 5. " UTMIP_OP_I_SRC_EN ,UTMIP_OP_I_SRC_EN" "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x28 4. " UTMIP_ON_SRC_EN ,UTMIP_ON_SRC_EN" "Disabled,Enabled"
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bitfld.long 0x28 3. " UTMIP_OP_SRC_EN ,UTMIP_OP_SRC_EN" "Disabled,Enabled"
|
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textline " "
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bitfld.long 0x28 2. " UTMIP_ON_SINK_EN ,UTMIP_ON_SINK_EN" "Disabled,Enabled"
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bitfld.long 0x28 1. " UTMIP_OP_SINK_EN ,UTMIP_OP_SINK_EN" "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x28 0. " UTMIP_PD_CHRG ,Power down charger circuit" "0,1"
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line.long 0x2C "USB1_UTMIP_SPARE_CFG0_0,Utmip spare configuration bits"
|
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bitfld.long 0x2C 2. " HS_RX_LATE_SQUELCH ,Delay Squelch by 1 CLK480 cycle" "Disabled,Enabled"
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bitfld.long 0x2C 1. " HS_RX_FLUSH_ALAP ,Flush as late as possible" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x2C 0. " HS_RX_IPG_ERROR_ENABLE ,HS_RX_IPG_ERROR_ENABLE" "Disabled,Enabled"
|
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line.long 0x30 "USB1_UTMIP_XCVR_CFG1_0,UTMIP transceiver cell configuration register 1"
|
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bitfld.long 0x30 26.--27. " UTMIP_XCVR_RPU_RANGE_ADJ ,1.5k pull-up resistor range shift" "0,1,2,3"
|
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bitfld.long 0x30 24.--25. " UTMIP_XCVR_HS_IREF_CAP ,High-speed Iref cap control for bias current stability" "0,1,2,3"
|
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textline " "
|
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bitfld.long 0x30 22.--23. " UTMIP_XCVR_SPARE ,Spare bits for USB transceiver pad" "0,1,2,3"
|
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bitfld.long 0x30 18.--21. " UTMIP_XCVR_TERM_RANGE_ADJ ,Range adjustment on terminations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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textline " "
|
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bitfld.long 0x30 17. " UTMIP_RCTRL_SW_SET ,Use a software override on RCTRL instead of automatic bias control" "No,Yes"
|
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bitfld.long 0x30 12.--16. " UTMIP_RCTRL_SW_VAL ,Encoded value to use on RCTRL when software override is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
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textline " "
|
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bitfld.long 0x30 11. " UTMIP_TCTRL_SW_SET ,Use a software override on TCTRL instead of automatic bias control" "No,Yes"
|
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bitfld.long 0x30 6.--10. " UTMIP_TCTRL_SW_VAL ,Encoded value to use on TCTRL when software override is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
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textline " "
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bitfld.long 0x30 5. " UTMIP_FORCE_PDDR_POWERUP ,Force PDDR input into power up" "Not forced,Forced"
|
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bitfld.long 0x30 4. " UTMIP_FORCE_PDDR_POWERDOWN ,Force PDDR input input into power down" "Not forced,Forced"
|
|
textline " "
|
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bitfld.long 0x30 3. " UTMIP_FORCE_PDCHRP_POWERUP ,Force PDCHRP input into power up" "Not forced,Forced"
|
|
bitfld.long 0x30 2. " UTMIP_FORCE_PDCHRP_POWERDOWN ,Force PDCHRP input input into power down" "Not forced,Forced"
|
|
textline " "
|
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bitfld.long 0x30 1. " UTMIP_FORCE_PDDISC_POWERUP ,Force PDDISC input into power up" "Not forced,Forced"
|
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bitfld.long 0x30 0. " UTMIP_FORCE_PDDISC_POWERDOWN ,Force PDDISC input into power down" "Not forced,Forced"
|
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line.long 0x34 "USB1_UTMIP_BIAS_CFG1_0,UTMIP Bias cell configuration register 1"
|
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bitfld.long 0x34 8.--13. " UTMIP_BIAS_DEBOUNCE_TIMESCALE ,Debouncer time scaling - factor-1 to slow down debouncing by" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
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bitfld.long 0x34 3.--7. " UTMIP_BIAS_PDTRK_COUNT ,Control the BIAS cell power down lag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x34 1. " UTMIP_FORCE_PDTRK_POWERUP ,Force PDTRK input into power up" "Disabled,Enabled"
|
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bitfld.long 0x34 0. " UTMIP_FORCE_PDTRK_POWERDOWN ,Force PDTRK input into power down" "Disabled,Enabled"
|
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rgroup.long 0x840++0x03
|
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line.long 0x00 "USB1_UTMIP_BIAS_STS0_0,UTMIP Bias cell status register 0"
|
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hexmask.long.word 0x00 16.--31. 1. " UTMIP_TCTRL ,Thermal encoding output from USB bias pad"
|
|
hexmask.long.word 0x00 0.--15. 1. " UTMIP_RCTRL ,Thermal encoding output from USB bias pad"
|
|
group.long 0x844++0x03
|
|
line.long 0x00 "USB1_UTMIP_CHRG_DEB_CFG0_0,UTMIP VDcd_Det and VDat_Det debounce"
|
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hexmask.long.word 0x00 16.--31. 1. " UTMIP_CHRG_DEBOUNCE_PERIOD_B ,Simulation value -- Used for interrupts"
|
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hexmask.long.word 0x00 0.--15. 1. " UTMIP_CHRG_DEBOUNCE_PERIOD_A ,Simulation value -- Used for interrupts"
|
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rgroup.long 0x848++0x03
|
|
line.long 0x00 "USB1_UTMIP_PMC_WAKEUP0_0,UTMIP PMC Wakeup value"
|
|
bitfld.long 0x00 21. " UTMIP_FS_DRV_EN ,Indicates when the controller is driving on the bus" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " UTMIP_SPARE_FUSES ,Spare Fuses value, to keep the connections preserved"
|
|
group.long 0x84C++0x03
|
|
line.long 0x00 "USB1_UTMIP_PMC_WAKEUP0_0,UTMIP PMC Wakeup value"
|
|
rbitfld.long 0x00 1. " UTMIP_LINE_WAKEUP_EVENT_INT_STS ,Indicates the status of the pmc wakeup event" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 0. " UTMIP_LINE_WAKEUP_EVENT_INT_ENB ,Interrupt mask for the pmc wakeup event" "Disabled,Enabled"
|
|
width 30.
|
|
tree "Endpoint Queue Head"
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_0_OUT_0,USB2D Queue Head for OUT endpoint 0"
|
|
group.long (0x1000+0x40)++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_0_IN_0,USB2D Queue Head for IN endpoint 0"
|
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group.long 0x1080++0x03
|
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line.long 0x00 "USB1_QH_USB2D_QH_EP_1_OUT_0,USB2D Queue Head for OUT endpoint 1"
|
|
group.long (0x1080+0x40)++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_1_IN_0,USB2D Queue Head for IN endpoint 1"
|
|
group.long 0x1100++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_2_OUT_0,USB2D Queue Head for OUT endpoint 2"
|
|
group.long (0x1100+0x40)++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_2_IN_0,USB2D Queue Head for IN endpoint 2"
|
|
group.long 0x1180++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_3_OUT_0,USB2D Queue Head for OUT endpoint 3"
|
|
group.long (0x1180+0x40)++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_3_IN_0,USB2D Queue Head for IN endpoint 3"
|
|
group.long 0x1200++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_4_OUT_0,USB2D Queue Head for OUT endpoint 4"
|
|
group.long (0x1200+0x40)++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_4_IN_0,USB2D Queue Head for IN endpoint 4"
|
|
group.long 0x1280++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_5_OUT_0,USB2D Queue Head for OUT endpoint 5"
|
|
group.long (0x1280+0x40)++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_5_IN_0,USB2D Queue Head for IN endpoint 5"
|
|
group.long 0x1300++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_6_OUT_0,USB2D Queue Head for OUT endpoint 6"
|
|
group.long (0x1300+0x40)++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_6_IN_0,USB2D Queue Head for IN endpoint 6"
|
|
group.long 0x1380++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_7_OUT_0,USB2D Queue Head for OUT endpoint 7"
|
|
group.long (0x1380+0x40)++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_7_IN_0,USB2D Queue Head for IN endpoint 7"
|
|
group.long 0x1400++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_8_OUT_0,USB2D Queue Head for OUT endpoint 8"
|
|
group.long (0x1400+0x40)++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_8_IN_0,USB2D Queue Head for IN endpoint 8"
|
|
group.long 0x1480++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_9_OUT_0,USB2D Queue Head for OUT endpoint 9"
|
|
group.long (0x1480+0x40)++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_9_IN_0,USB2D Queue Head for IN endpoint 9"
|
|
group.long 0x1500++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_10_OUT_0,USB2D Queue Head for OUT endpoint 10"
|
|
group.long (0x1500+0x40)++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_10_IN_0,USB2D Queue Head for IN endpoint 10"
|
|
group.long 0x1580++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_11_OUT_0,USB2D Queue Head for OUT endpoint 11"
|
|
group.long (0x1580+0x40)++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_11_IN_0,USB2D Queue Head for IN endpoint 11"
|
|
group.long 0x1600++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_12_OUT_0,USB2D Queue Head for OUT endpoint 12"
|
|
group.long (0x1600+0x40)++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_12_IN_0,USB2D Queue Head for IN endpoint 12"
|
|
group.long 0x1680++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_13_OUT_0,USB2D Queue Head for OUT endpoint 13"
|
|
group.long (0x1680+0x40)++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_13_IN_0,USB2D Queue Head for IN endpoint 13"
|
|
group.long 0x1700++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_14_OUT_0,USB2D Queue Head for OUT endpoint 14"
|
|
group.long (0x1700+0x40)++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_14_IN_0,USB2D Queue Head for IN endpoint 14"
|
|
group.long 0x1780++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_15_OUT_0,USB2D Queue Head for OUT endpoint 15"
|
|
group.long (0x1780+0x40)++0x03
|
|
line.long 0x00 "USB1_QH_USB2D_QH_EP_15_IN_0,USB2D Queue Head for IN endpoint 15"
|
|
tree.end
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "USB2 (2.0)"
|
|
base ad:0x7D004000
|
|
tree "USB 2 Controller"
|
|
tree "Status Registers"
|
|
width 35.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_ID_0,USB2D Identification Register"
|
|
bitfld.long 0x00 29.--31. " CIVERSION ,Identifies the CI version" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 25.--28. " VERSION ,Identifies the version of the core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21.--24. " REVISION ,Revision number of the USB controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. " TAG ,Identifies the tag of the core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " NID ,Ones complement version of ID"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ID ,Configuration number"
|
|
rgroup.long 0x08++0x0F
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_HW_HOST_0,USB2D Hardware Host Register"
|
|
bitfld.long 0x00 1.--3. " NPORT ,NPORT" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " HC ,Support for host mode" "Disabled,Enabled"
|
|
line.long 0x04 "USB2_CONTROLLER_1_USB2D_HW_DEVICE_0,USB2D Hardware Device Register"
|
|
bitfld.long 0x04 1.--5. " DEVEP ,Number of endpoints supported by this device controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0. " DC ,Support for device mode" "Disabled,Enabled"
|
|
line.long 0x08 "USB2_CONTROLLER_1_USB2D_HW_TXBUF_0,USB2D Hardware TX Buffer Register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " TXCHANADD ,Total number of address bits for the transmit buffer of each transmit endpoint"
|
|
hexmask.long.byte 0x08 8.--15. 1. " TXADD ,Total number of address bits for the transmit buffer"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TCBURST ,Maximum burst size supported by the transmit endpoints for data transfers"
|
|
line.long 0x0C "USB2_CONTROLLER_1_USB2D_HW_RXBUF_0,USB2D RX Buffer HW Parameters Register"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " RXADD ,Total number of address bits for the receive buffer"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " RXBURST ,Maximum burst size supported by the receive endpoints for data transfers"
|
|
textline " "
|
|
width 40.
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "USB2_CONTROLLER_USB_1_USB2D_GPTIMER0LD_0,Timer register 0"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " GPTIMER0LD ,Value loaded into the GPTCNT"
|
|
line.long 0x04 "USB2_CONTROLLER_1_USB2D_GPTIMER0CTRL_0,Timer register controller 0"
|
|
bitfld.long 0x04 31. " GTPRUN ,Enables the general-purpose timer to run" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " GPTRST ,Writing a one to this bit will reload the GPTCNT with the value in GPTL" "No effect,reload"
|
|
bitfld.long 0x04 24. " GPTMODE ,Selects timer mode" "One-shot,Repeat"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,Value of the running timer"
|
|
line.long 0x08 "USB2_CONTROLLER_1_USB2D_GPTIMER1LD_0,Timer register 1"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " GPTIMER1LD ,Value loaded into the GPTCNT"
|
|
line.long 0x0C "USB2_CONTROLLER_1_USB2D_GPTIMER1CTRL_0,Timer register controller 1"
|
|
bitfld.long 0x0C 31. " GTPRUN ,Enables the general-purpose timer to run" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " GPTRST ,Writing a one to this bit will reload the GPTCNT with the value in GPTL" "No effect,reload"
|
|
bitfld.long 0x0C 24. " GPTMODE ,Selects timer mode" "One-shot,Repeat"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,Value of the running timer"
|
|
textline " "
|
|
width 37.
|
|
rgroup.word 0x100++0x03
|
|
line.word 0x00 "USB2_CONTROLLER_1_USB2D_CAPLENGTH_0,USB2D Capability Register Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CAPLENGTH ,Indicates which offset to add to the register base address at the beginning of the operational register"
|
|
line.word 0x02 "USB2_CONTROLLER_1_USB2D_HCIVERSON_0,USB2D Host Interface Version Number Register"
|
|
hexmask.word 0x02 0.--15. 1. " HCIVERSION ,Contains a BCD encoding of the EHCI revision number supported by this host controller"
|
|
rgroup.long 0x104++0x07
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_HCSPARAMS_0,USB2D Host Control Structural Parameters Register"
|
|
bitfld.long 0x00 24.--27. " N_TT ,Number of transaction translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " N_PTT ,Number of ports per transaction translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " N_CC ,Number of companion controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " N_PCC ,Number of ports per companion controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " PPC ,Port power control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " N_PORTS ,Number of downstream ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "USB2_CONTROLLER_1_USB2D_HCCPARAMS_0,USB2D Host Control Capability Parameters Register"
|
|
bitfld.long 0x04 18. " PPC ,Per-port change event capability" "Not supported,Supported"
|
|
bitfld.long 0x04 17. " LEN ,Link power management capability" "Not supported,Supported"
|
|
hexmask.long.byte 0x04 8.--15. 1. " EECP ,EHCI extended capabilities pointer"
|
|
bitfld.long 0x04 4.--7. " IST ,Isochronous scheduling threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 2. " ASP ,Asynchronous schedule park capability" "Not supported,Supported"
|
|
bitfld.long 0x04 1. " PFL ,Programmable frame list flag (frame list length)" "1024 elements,USBCMD_0.FS"
|
|
rgroup.long 0x120++0x07
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_DCIVERSION_0,USB2D Device Interface Version Number Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DCIVERSION ,Interface version number for the two-byte BCD encoding"
|
|
line.long 0x04 "USB2_CONTROLLER_1_USB2D_DCCPARAMS_0,USB2D Device Control Capabilities Register"
|
|
bitfld.long 0x04 8. " HC ,Host capable" "Not capable,Capable"
|
|
bitfld.long 0x04 7. " DC ,Device capable" "Not capable,Capable"
|
|
bitfld.long 0x04 5. " LEN ,Link power management capability" "Not capable,Capable"
|
|
bitfld.long 0x04 0.--4. " DEN ,Device endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
width 37.
|
|
tree "Control Registers"
|
|
if (((d.l(ad:0x7D004000+0x1F8))&0x03)==0x02)
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_EXTSTS_0,USB2D EXTSTS Register"
|
|
eventfld.long 0x00 4. " TI1 ,General purpose timer interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TI0 ,General purpose timer interrupt 0" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 0. " NAKI ,NAK interrupt bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_EXTSTS_0,USB2D EXTSTS Register"
|
|
eventfld.long 0x00 4. " TI1 ,General purpose timer interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TI0 ,General purpose timer interrupt 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " UPA ,USB host periodic interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " UAI ,USB host asynchronous interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 0. " NAKI ,NAK interrupt bit" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_USBEXTINTR_0,USB2D EXTINTR Register"
|
|
bitfld.long 0x00 4. " TIE1 ,General purpose timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TIE0 ,General purpose timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " UPIE ,UPIE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UAIE ,UAIE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NAKE ,NAK interrupt enable" "Disabled,Enabled"
|
|
if (((d.l(ad:0x7D004000+0x108))&0x06)==0x00)&&(((d.l(ad:0x7D004000+0x1F8))&0x03)==0x03)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_USBCMD_0,USB2D USB Command Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control"
|
|
bitfld.long 0x00 14. " ATDTW ,ADD DTD tripwire" "Clear,Set"
|
|
bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Clear,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--9. " ASP1_ASP0 ,Asynchronous schedule park mode count" "0,1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. 15. " FS2_FS0 ,Frame list size (in bytes)" "4096,2048,1024,512,256,128,64,32"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop host/device controller" "Stop,Run"
|
|
elif (((d.l(ad:0x7D004000+0x108))&0x06)==0x02)&&(((d.l(ad:0x7D004000+0x1F8))&0x03)==0x03)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_USBCMD_0,USB2D USB Command Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control"
|
|
bitfld.long 0x00 14. " ATDTW ,ADD DTD tripwire" "Clear,Set"
|
|
bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Clear,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--9. " ASP1_ASP0 ,Asynchronous schedule park mode count" "0,1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. 15. " FS2_FS0 ,Frame list size (in bytes)" "4096,2048,1024,512,256,128,64,32"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop host/device controller" "Stop,Run"
|
|
elif (((d.l(ad:0x7D004000+0x108))&0x06)==0x04)&&(((d.l(ad:0x7D004000+0x1F8))&0x03)==0x03)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_USBCMD_0,USB2D USB Command Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control"
|
|
bitfld.long 0x00 14. " ATDTW ,ADD DTD tripwire" "Clear,Set"
|
|
bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Clear,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ASP1_ASP0 ,Asynchronous schedule park mode count" ",1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. 15. " FS2_FS0 ,Frame list size (in bytes)" "4096,2048,1024,512,256,128,64,32"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop host/device controller" "Stop,Run"
|
|
elif (((d.l(ad:0x7D004000+0x108))&0x06)==0x06)&&(((d.l(ad:0x7D004000+0x1F8))&0x03)==0x03)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_USBCMD_0,USB2D USB Command Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control"
|
|
bitfld.long 0x00 14. " ATDTW ,ADD DTD tripwire" "Clear,Set"
|
|
bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Clear,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ASP1_ASP0 ,Asynchronous schedule park mode count" ",1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. 15. " FS2_FS0 ,Frame list size (in bytes)" "4096,2048,1024,512,256,128,64,32"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop host/device controller" "Stop,Run"
|
|
elif (((d.l(ad:0x7D004000+0x108))&0x04)==0x00)&&(((d.l(ad:0x7D004000+0x1F8))&0x03)!=0x03)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_USBCMD_0,USB2D USB Command Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14. " ATDTW ,ADD DTD tripwire" "Clear,Set"
|
|
bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Clear,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " ASP1_ASP0 ,Asynchronous schedule park mode count" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. 15. " FS2_FS0 ,Frame list size (in bytes)" "4096,2048,1024,512,256,128,64,32"
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop host/device controller" "Stop,Run"
|
|
elif (((d.l(ad:0x7D004000+0x108))&0x04)==0x04)&&(((d.l(ad:0x7D004000+0x1F8))&0x03)!=0x03)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_USBCMD_0,USB2D USB Command Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control"
|
|
bitfld.long 0x00 14. " ATDTW ,ADD DTD tripwire" "Clear,Set"
|
|
bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Clear,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ASP1_ASP0 ,Asynchronous schedule park mode count" ",1,2,3"
|
|
bitfld.long 0x00 2.--3. 15. " FS2_FS0 ,Frame list size (in bytes)" "4096,2048,1024,512,256,128,64,32"
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop host/device controller" "Stop,Run"
|
|
endif
|
|
if (((d.l(ad:0x7D004000+0x1F8))&0x03)==0x03)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_USBSTS_0,USB2D USB Status Register"
|
|
bitfld.long 0x00 31. " PPCI16 ,Port 16 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " PPCI15 ,Port 15 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 29. " PPCI14 ,Port 14 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " PPCI13 ,Port 13 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 27. " PPCI12 ,Port 12 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPCI11 ,Port 11 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 25. " PPCI10 ,Port 10 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " PPCI9 ,Port 9 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 23. " PPCI8 ,Port 8 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " PPCI7 ,Port 7 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCI6 ,Port 6 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " PPCI5 ,Port 5 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 19. " PPCI4 ,Port 4 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " PPCI3 ,Port 3 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 17. " PPCI2 ,Port 2 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PPCI1 ,Port 1 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 15. " AS ,Asynchronous schedule status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PS ,Periodic schedule status" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " RCL ,Empty asynchronous schedule detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " HCH ,HCHalted" "Unhalted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " UALT_INT ,ULPI alt_int Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ULPI_INT ,ULPI interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " SRI ,SOF received" "Not received,Received"
|
|
bitfld.long 0x00 5. " AAI ,Interrupt and asynchronous advance" "Not advanced,Advanced"
|
|
rbitfld.long 0x00 4. " SEI ,System error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRI ,Frame list rollover" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCI ,Port change detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB error interrupt" "No error,Error"
|
|
bitfld.long 0x00 0. " UI ,USB interrupt" "No interrupt,Interrupt"
|
|
elif (((d.l(ad:0x7D004000+0x1F8))&0x03)==0x02)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_USBSTS_0,USB2D USB Status Register"
|
|
bitfld.long 0x00 31. " PPCI16 ,Port 16 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " PPCI15 ,Port 15 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 29. " PPCI14 ,Port 14 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " PPCI13 ,Port 13 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 27. " PPCI12 ,Port 12 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPCI11 ,Port 11 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 25. " PPCI10 ,Port 10 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " PPCI9 ,Port 9 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 23. " PPCI8 ,Port 8 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " PPCI7 ,Port 7 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCI6 ,Port 6 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " PPCI5 ,Port 5 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 19. " PPCI4 ,Port 4 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " PPCI3 ,Port 3 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 17. " PPCI2 ,Port 2 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PPCI1 ,Port 1 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 11. " UALT_INT ,ULPI alt_int Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ULPI_INT ,ULPI interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SLI ,DCSuspend" "Not suspended,Suspended"
|
|
eventfld.long 0x00 7. " SRI ,SOF received" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 6. " URI ,USB reset received" "No reset,Reset"
|
|
rbitfld.long 0x00 4. " SEI ,System error" "No error,Error"
|
|
bitfld.long 0x00 2. " PCI ,Port change detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB error interrupt" "No error,Error"
|
|
bitfld.long 0x00 0. " UI ,USB interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_USBSTS_0,USB2D USB Status Register"
|
|
bitfld.long 0x00 31. " PPCI16 ,Port 16 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " PPCI15 ,Port 15 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 29. " PPCI14 ,Port 14 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " PPCI13 ,Port 13 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 27. " PPCI12 ,Port 12 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPCI11 ,Port 11 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 25. " PPCI10 ,Port 10 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " PPCI9 ,Port 9 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 23. " PPCI8 ,Port 8 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " PPCI7 ,Port 7 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCI6 ,Port 6 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " PPCI5 ,Port 5 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 19. " PPCI4 ,Port 4 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " PPCI3 ,Port 3 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 17. " PPCI2 ,Port 2 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PPCI1 ,Port 1 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 11. " UALT_INT ,ULPI alt_int Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ULPI_INT ,ULPI interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " SRI ,SOF received" "Not received,Received"
|
|
rbitfld.long 0x00 4. " SEI ,System error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCI ,Port change detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB error interrupt" "No error,Error"
|
|
bitfld.long 0x00 0. " UI ,USB interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
if (((d.l(ad:0x7D004000+0x1F8))&0x03)==0x03)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_USBINTR_0,USB2D USB Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " PPCE16 ,Port 16 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PPCE15 ,Port 15 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PPCE14 ,Port 14 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PPCE13 ,Port 13 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PPCE12 ,Port 12 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPCE11 ,Port 11 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PPCE10 ,Port 10 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PPCE9 ,Port 9 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PPCE8 ,Port 8 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PPCE7 ,Port 7 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCE6 ,Port 6 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PPCE5 ,Port 5 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PPCE4 ,Port 4 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PPCE3 ,Port 3 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PPCE2 ,Port 2 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PPCE1 ,Port 1 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " UALTIE ,LPI alt_int Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ULPIE ,ULPI interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " SRE ,SOF received" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AAE ,Interrupt on asynchronous advance" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEE ,System error" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRE ,Frame list rollover" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCE ,Port change detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UEE ,USB error interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USB interrupt" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x7D004000+0x1F8))&0x03)==0x02)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_USBINTR_0,USB2D USB Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " PPCE16 ,Port 16 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PPCE15 ,Port 15 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PPCE14 ,Port 14 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PPCE13 ,Port 13 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PPCE12 ,Port 12 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPCE11 ,Port 11 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PPCE10 ,Port 10 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PPCE9 ,Port 9 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PPCE8 ,Port 8 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PPCE7 ,Port 7 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCE6 ,Port 6 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PPCE5 ,Port 5 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PPCE4 ,Port 4 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PPCE3 ,Port 3 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PPCE2 ,Port 2 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PPCE1 ,Port 1 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " UALTIE ,LPI alt_int Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ULPIE ,ULPI interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLE ,Sleep enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " SRE ,SOF received" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 6. " URE ,USB reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SEE ,System error" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCE ,Port change detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UEE ,USB error interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USB interrupt" "Disabled,Enabled"
|
|
else
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_USBINTR_0,USB2D USB Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " PPCE16 ,Port 16 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PPCE15 ,Port 15 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PPCE14 ,Port 14 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PPCE13 ,Port 13 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PPCE12 ,Port 12 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPCE11 ,Port 11 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PPCE10 ,Port 10 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PPCE9 ,Port 9 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PPCE8 ,Port 8 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PPCE7 ,Port 7 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCE6 ,Port 6 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PPCE5 ,Port 5 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PPCE4 ,Port 4 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PPCE3 ,Port 3 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PPCE2 ,Port 2 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PPCE1 ,Port 1 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " UALTIE ,LPI alt_int Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ULPIE ,ULPI interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " SRE ,SOF received" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SEE ,System error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCE ,Port change detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UEE ,USB error interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USB interrupt" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_FRINDEX_0,USB2D USB Frame Index Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame index"
|
|
textline " "
|
|
width 44.
|
|
if (((d.l(ad:0x7D004000+0x1F8))&0x03)==0x02)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0,USB2D Host Controller Frame List Base Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 0x2 " USBADR ,Device address"
|
|
bitfld.long 0x00 24. " USBADRA ,Device address advance" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x7D004000+0x1F8))&0x03)==0x03)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0,USB2D Host Controller Frame List Base Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Beginning address of the periodic frame list in the system memory"
|
|
else
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0,USB2D Host Controller Frame List Base Address Register"
|
|
endif
|
|
if (((d.l(ad:0x7D004000+0x1F8))&0x03)==0x02)
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0,USB2D Next Asynchronous List Address Register"
|
|
hexmask.long.tbyte 0x00 11.--31. 0x08 " EPBASE ,Address of the top of the endpoint list in system memory"
|
|
elif (((d.l(ad:0x7D004000+0x1F8))&0x03)==0x03)
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0,USB2D Next Asynchronous List Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " ASYBASE ,Address of the next asynchronous queue head to be executed by the host"
|
|
else
|
|
hgroup.long 0x148++0x03
|
|
hide.long 0x00 "USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0,USB2D Next Asynchronous List Address Register"
|
|
endif
|
|
group.long 0x14C++0x0B
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0,USB2D Asynchronous Buffer Status for Embedded TT Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " TTHA ,Internal TT Hub Address representation"
|
|
bitfld.long 0x00 1. " TTAC ,Embedded TT async buffers clear" "No clear,Clear"
|
|
rbitfld.long 0x00 0. " TTAS ,Embedded TT async buffers status" "Empty,Not empty"
|
|
line.long 0x04 "USB2_CONTROLLER_1_USB2D_BURSTSIZE_0,USB2D Burst Size register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TXPBURST ,Programmable TX burst length"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RXPBURST ,Programmable RX burst length"
|
|
line.long 0x08 "USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0,USB2D Transmit fill tuning register"
|
|
bitfld.long 0x08 16.--21. " TXFIFOTHRES ,FIFO burst threshold" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 8.--12. " TXSCHHEALTH ,Scheduler health counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TXSCHOH ,Scheduler overhead"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0,USB2D ICUSB control register"
|
|
bitfld.long 0x00 3. " IC_ENB1 ,ICUSB transceiver" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " IC_VDD1 ,ICUSB voltage select" "No voltage,,,,1.8V,3.0V,?..."
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0,USB2D ULPI viewport register"
|
|
bitfld.long 0x00 31. " ULPI_WAKEUP ,ULPI wakeup" "No effect,Wakeup"
|
|
bitfld.long 0x00 30. " ULPI_RUN ,ULPI read/write run (begin read/write operation)" "No effect,Run"
|
|
bitfld.long 0x00 29. " ULPI_RD_WR ,ULPI read/write control" "Read,Write"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " ULPI_SYNC_STATE ,ULPI sync state" "Normal,Not normal"
|
|
bitfld.long 0x00 24.--26. " ULPI_PORT ,ULPI PHY port number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ULPI_REG_ADDR ,ULPI PHY register address"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " ULPI_DATA_RD ,ULPI PHY data read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ULPI_DATA_WR ,ULPI PHY data write"
|
|
textline ""
|
|
width 41.
|
|
if (((d.l(ad:0x7D004000+0x1F8))&0x03)==0x03)
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_PORTSC1_0,USB2D Port Status/Control 1 Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " DA ,Device address"
|
|
rbitfld.long 0x00 23.--24. " SSTS ,Suspend status" "L1STATE_ENTERED,NYET_PERIPH,L1STATE_NOT_SUPPORTED,PERIPH_NORESP_ERR"
|
|
bitfld.long 0x00 22. " WKOC ,Wake on over-current" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKDS ,Wake on disconnect" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " WKCN ,Wake on connect" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port test control" "NORMAL_OP,TEST_J,TEST_K,TEST_SE0_NAK,TEST_PKT,TEST_FORCE_ENABLE,?..."
|
|
textline " "
|
|
eventfld.long 0x00 12. " PP ,Port power" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10.--11. " LS ,Line state" "SE0,J_STATE,K_STATE,Undefined"
|
|
bitfld.long 0x00 9. " SLP ,Suspend using L1" "L2,L1"
|
|
bitfld.long 0x00 8. " PR ,Port reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SUSP ,Port suspend" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FPR ,Force port resume" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEC ,Port enable/disable change" "No change,Change"
|
|
eventfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSC ,Connect status change" "No change,Change"
|
|
rbitfld.long 0x00 0. " CCS ,Current connect status" "Not connected,Connected"
|
|
elif (((d.l(ad:0x7D004000+0x1F8))&0x03)==0x02)
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_PORTSC1_0,USB2D Port Status/Control 1 Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " DA ,Device address"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port test control" "NORMAL_OP,TEST_J,TEST_K,TEST_SE0_NAK,TEST_PKT,TEST_FORCE_ENABLE,?..."
|
|
rbitfld.long 0x00 14.--15. " PIC ,Port indicator control" "0,1,2,3"
|
|
rbitfld.long 0x00 13. " PO ,Port owner" "0,1"
|
|
eventfld.long 0x00 12. " PP ,Port power" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10.--11. " LS ,Line state" "SE0,J_STATE,K_STATE,Undefined"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SLP ,Suspend using L1" "L2,L1"
|
|
rbitfld.long 0x00 8. " PR ,Port reset" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " SUSP ,Port suspend" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FPR ,Force port resume" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " OCC ,Over-current change" "No change,Change"
|
|
rbitfld.long 0x00 4. " OCA ,Over-current active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEC ,Port enable/disable change" "No change,Change"
|
|
eventfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,Current connect status" "Not connected,Connected"
|
|
else
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_PORTSC1_0,USB2D Port Status/Control 1 Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " DA ,Device address"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port test control" "NORMAL_OP,TEST_J,TEST_K,TEST_SE0_NAK,TEST_PKT,TEST_FORCE_ENABLE,?..."
|
|
rbitfld.long 0x00 14.--15. " PIC ,Port indicator control" "0,1,2,3"
|
|
rbitfld.long 0x00 13. " PO ,Port owner" "0,1"
|
|
eventfld.long 0x00 12. " PP ,Port power" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10.--11. " LS ,Line state" "SE0,J_STATE,K_STATE,Undefined"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SLP ,Suspend using L1" "L2,L1"
|
|
rbitfld.long 0x00 8. " PR ,Port reset" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " SUSP ,Port suspend" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FPR ,Force port resume" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " OCC ,Over-current change" "No change,Change"
|
|
rbitfld.long 0x00 4. " OCA ,Over-current active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEC ,Port enable/disable change" "No change,Change"
|
|
eventfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,Current connect status" "Not connected,Connected"
|
|
endif
|
|
textline ""
|
|
if (((d.l(ad:0x7D004000+0x1F8))&0x03)==0x03)
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_HOSTPC1_DEVLC_0,USB2D Host Mode LPM Behav and Control Register"
|
|
bitfld.long 0x00 29.--31. " PTS ,Parallel transceiver select" "UTMI,,ULPI,ICUSB_SER,HSIC,?..."
|
|
bitfld.long 0x00 28. " STS ,Serial transceiver" "PARALLEL_IF,SERIAL_IF"
|
|
rbitfld.long 0x00 27. " PTW ,Parallel transceiver width" "8-bit,?..."
|
|
rbitfld.long 0x00 25.--26. " PSPD ,Port operating speed" "Full,Low,High,?..."
|
|
bitfld.long 0x00 24. " ALPD ,Auto Low Power While Disconnect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PFSC ,Port force full speed connect" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PHCD ,PHY low power suspend - clock disable" "No,Yes"
|
|
bitfld.long 0x00 20.--21. " LPMX ,Auto LPM set" "Disabled,Set,Set without interrupt,?..."
|
|
bitfld.long 0x00 16.--19. " EPLPM ,Endpoint for LPM token" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " LPMFRM ,Auto LPM SOF threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 1.--11. 1. " BA ,BmAttrubuttes"
|
|
bitfld.long 0x00 0. " ASUS ,Auto low power" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x7D004000+0x1F8))&0x03)==0x02)
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_HOSTPC1_DEVLC_0,USB2D Device Mode LPM Behav and Control Register"
|
|
bitfld.long 0x00 29.--31. " PTS ,Parallel transceiver select" "UTMI,,ULPI,ICUSB_SER,HSIC,?..."
|
|
bitfld.long 0x00 28. " STS ,Serial transceiver" "PARALLEL_IF,SERIAL_IF"
|
|
rbitfld.long 0x00 27. " PTW ,Parallel transceiver width" "8-bit,?..."
|
|
rbitfld.long 0x00 25.--26. " PSPD ,Port operating speed" "Full,Low,High,?..."
|
|
bitfld.long 0x00 24. " ALPD ,Auto Low Power While Disconnect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PFSC ,Port force full speed connect" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PHCD ,PHY low power suspend - clock disable" "No,Yes"
|
|
bitfld.long 0x00 17. " ASUS ,Auto low power" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " STL ,STALL reply to LPM token" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 1.--11. 1. " BA ,BmAttrubuttes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NYT ,NYTE reply to LPM token" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_HOSTPC1_DEVLC_0,USB2D Device Mode LPM Behav and Control Register"
|
|
bitfld.long 0x00 29.--31. " PTS ,Parallel transceiver select" "UTMI,,ULPI,ICUSB_SER,HSIC,?..."
|
|
bitfld.long 0x00 28. " STS ,Serial transceiver" "PARALLEL_IF,SERIAL_IF"
|
|
rbitfld.long 0x00 27. " PTW ,Parallel transceiver width" "8-bit,?..."
|
|
rbitfld.long 0x00 25.--26. " PSPD ,Port operating speed" "Full,Low,High,?..."
|
|
bitfld.long 0x00 24. " ALPD ,Auto Low Power While Disconnect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PFSC ,Port force full speed connect" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PHCD ,PHY low power suspend - clock disable" "No,Yes"
|
|
hexmask.long.word 0x00 1.--11. 1. " BA ,BmAttrubuttes"
|
|
endif
|
|
textline ""
|
|
width 32.
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_OTGSC_0,USB2D On-The-Go (OTG) Status and Control Register"
|
|
bitfld.long 0x00 30. " DPIE ,Data pulse interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONEMSE ,1 millisecond timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " BSEIE ,B session end interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " BSVIE ,B session valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ASVIE ,A session valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " AVVIE ,A VBUS valid interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " IDIE ,USB ID interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 22. " DPIS ,Data pulse interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ONEMESS ,1 millisecond timer interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " BSEIS ,B session end interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " BSVIS ,B session valid interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ASVIS ,A session valid interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " AVVIS ,A VBUS valid interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IDIS ,USB ID interrupt toggle" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 14. " DPS ,Data pulse status" "Not detected,Detected"
|
|
rbitfld.long 0x00 13. " ONEMST ,1 millisecond timer toggle" "Low,High"
|
|
rbitfld.long 0x00 12. " BSE ,B session end threshold" "No,Yes"
|
|
rbitfld.long 0x00 11. " BSV ,B session valid threshold" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " ASV ,A session valid threshold" "No,Yes"
|
|
rbitfld.long 0x00 9. " AVV ,A VBUS valid threshold" "No,Yes"
|
|
rbitfld.long 0x00 8. " ID ,USB ID" "A-device,B-device"
|
|
bitfld.long 0x00 5. " IDPU ,USB ID pullup" "Clear,Set"
|
|
bitfld.long 0x00 4. " DP ,Data pulsing" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " OT ,OTG termination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " VC ,VBUS charge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VD ,VBUS discharge" "Disabled,Enabled"
|
|
tree.end
|
|
width 35.
|
|
if (((d.l(ad:0x7D004000+0x1F8))&0x03)==0x03)
|
|
group.long 0x1F8++0x03 "Device Mode Control"
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_USBMODE_0,USB2D USB Device Mode Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ALPDD ,Auto Low Power While Disconnect"
|
|
bitfld.long 0x00 15. " SRT ,Shorten USB reset time" "No,Yes"
|
|
rbitfld.long 0x00 4. " SDIS ,Stream disable" "No,Yes"
|
|
rbitfld.long 0x00 2. " ES ,Endian select" "Little endian,?..."
|
|
rbitfld.long 0x00 0.--1. " CM ,Controller mode" "Idle,,Device mode,Host mode"
|
|
elif (((d.l(ad:0x7D004000+0x1F8))&0x03)!=0x03)
|
|
group.long 0x1F8++0x03 "Device Mode Control"
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_USBMODE_0,USB2D USB Device Mode Register"
|
|
bitfld.long 0x00 15. " SRT ,Shorten USB reset time" "No,Yes"
|
|
rbitfld.long 0x00 4. " SDIS ,Stream disable" "No,Yes"
|
|
rbitfld.long 0x00 3. " SLOM ,Setup lockout mode" "On,Off"
|
|
rbitfld.long 0x00 2. " ES ,Endian select" "Little endian,?..."
|
|
rbitfld.long 0x00 0.--1. " CM ,Controller mode" "Idle,,Device mode,Host mode"
|
|
endif
|
|
width 42.
|
|
tree "Endpoint Setup"
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_ENDPTNAK_0,USB2D Endpoint NAK register"
|
|
bitfld.long 0x00 31. " EPTN15 ,TX endpoint NAK 15" "Clear,Set"
|
|
bitfld.long 0x00 30. " EPTN14 ,TX endpoint NAK 14" "Clear,Set"
|
|
bitfld.long 0x00 29. " EPTN13 ,TX endpoint NAK 13" "Clear,Set"
|
|
bitfld.long 0x00 28. " EPTN12 ,TX endpoint NAK 12" "Clear,Set"
|
|
bitfld.long 0x00 27. " EPTN11 ,TX endpoint NAK 11" "Clear,Set"
|
|
bitfld.long 0x00 26. " EPTN10 ,TX endpoint NAK 10" "Clear,Set"
|
|
bitfld.long 0x00 25. " EPTN9 ,TX endpoint NAK 9" "Clear,Set"
|
|
bitfld.long 0x00 24. " EPTN8 ,TX endpoint NAK 8" "Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EPTN7 ,TX endpoint NAK 7" "Clear,Set"
|
|
bitfld.long 0x00 22. " EPTN6 ,TX endpoint NAK 6" "Clear,Set"
|
|
bitfld.long 0x00 21. " EPTN5 ,TX endpoint NAK 5" "Clear,Set"
|
|
bitfld.long 0x00 20. " EPTN4 ,TX endpoint NAK 4" "Clear,Set"
|
|
bitfld.long 0x00 19. " EPTN3 ,TX endpoint NAK 3" "Clear,Set"
|
|
bitfld.long 0x00 18. " EPTN2 ,TX endpoint NAK 2" "Clear,Set"
|
|
bitfld.long 0x00 17. " EPTN1 ,TX endpoint NAK 1" "Clear,Set"
|
|
bitfld.long 0x00 16. " EPTN0 ,TX endpoint NAK 0" "Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPRN15 ,RX endpoint NAK 15" "Clear,Set"
|
|
bitfld.long 0x00 14. " EPRN14 ,RX endpoint NAK 14" "Clear,Set"
|
|
bitfld.long 0x00 13. " EPRN13 ,RX endpoint NAK 13" "Clear,Set"
|
|
bitfld.long 0x00 12. " EPRN12 ,RX endpoint NAK 12" "Clear,Set"
|
|
bitfld.long 0x00 11. " EPRN11 ,RX endpoint NAK 11" "Clear,Set"
|
|
bitfld.long 0x00 10. " EPRN10 ,RX endpoint NAK 10" "Clear,Set"
|
|
bitfld.long 0x00 9. " EPRN9 ,RX endpoint NAK 9" "Clear,Set"
|
|
bitfld.long 0x00 8. " EPRN8 ,RX endpoint NAK 8" "Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EPRN7 ,RX endpoint NAK 7" "Clear,Set"
|
|
bitfld.long 0x00 6. " EPRN6 ,RX endpoint NAK 6" "Clear,Set"
|
|
bitfld.long 0x00 5. " EPRN5 ,RX endpoint NAK 5" "Clear,Set"
|
|
bitfld.long 0x00 4. " EPRN4 ,RX endpoint NAK 4" "Clear,Set"
|
|
bitfld.long 0x00 3. " EPRN3 ,RX endpoint NAK 3" "Clear,Set"
|
|
bitfld.long 0x00 2. " EPRN2 ,RX endpoint NAK 2" "Clear,Set"
|
|
bitfld.long 0x00 1. " EPRN1 ,RX endpoint NAK 1" "Clear,Set"
|
|
bitfld.long 0x00 0. " EPRN0 ,RX endpoint NAK 0" "Clear,Set"
|
|
textline ""
|
|
line.long 0x04 "USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0,USB2D Endpoint NAK Enable register"
|
|
bitfld.long 0x04 31. " EPTN15 ,TX endpoint NAK enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " EPTN14 ,TX endpoint NAK enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " EPTN13 ,TX endpoint NAK enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " EPTN12 ,TX endpoint NAK enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " EPTN11 ,TX endpoint NAK enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " EPTN10 ,TX endpoint NAK enable 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " EPTN9 ,TX endpoint NAK enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " EPTN8 ,TX endpoint NAK enable 8" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " EPTN7 ,TX endpoint NAK enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " EPTN6 ,TX endpoint NAK enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " EPTN5 ,TX endpoint NAK enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " EPTN4 ,TX endpoint NAK enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " EPTN3 ,TX endpoint NAK enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " EPTN2 ,TX endpoint NAK enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " EPTN1 ,TX endpoint NAK enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " EPTN0 ,TX endpoint NAK enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " EPRN15 ,RX endpoint NAK enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " EPRN14 ,RX endpoint NAK enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " EPRN13 ,RX endpoint NAK enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " EPRN12 ,RX endpoint NAK enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " EPRN11 ,RX endpoint NAK enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " EPRN10 ,RX endpoint NAK enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " EPRN9 ,RX endpoint NAK enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EPRN8 ,RX endpoint NAK enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " EPRN7 ,RX endpoint NAK enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " EPRN6 ,RX endpoint NAK enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " EPRN5 ,RX endpoint NAK enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " EPRN4 ,RX endpoint NAK enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " EPRN3 ,RX endpoint NAK enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " EPRN2 ,RX endpoint NAK enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " EPRN1 ,RX endpoint NAK enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EPRN0 ,RX endpoint NAK enable 0" "Disabled,Enabled"
|
|
width 43.
|
|
if (((d.l(ad:0x7D004000+0x1F8))&0x03)==0x02)
|
|
group.long 0x208++0x0B
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0,USB2D Endpoint Setup Status Register"
|
|
bitfld.long 0x00 15. " ENDPTSETUPSTAT15 ,Endpoint setup status 15" "Not received,Received"
|
|
bitfld.long 0x00 14. " ENDPTSETUPSTAT14 ,Endpoint setup status 14" "Not received,Received"
|
|
bitfld.long 0x00 13. " ENDPTSETUPSTAT13 ,Endpoint setup status 13" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENDPTSETUPSTAT12 ,Endpoint setup status 12" "Not received,Received"
|
|
bitfld.long 0x00 11. " ENDPTSETUPSTAT11 ,Endpoint setup status 11" "Not received,Received"
|
|
bitfld.long 0x00 10. " ENDPTSETUPSTAT10 ,Endpoint setup status 10" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ENDPTSETUPSTAT9 ,Endpoint setup status 9" "Not received,Received"
|
|
bitfld.long 0x00 8. " ENDPTSETUPSTAT8 ,Endpoint setup status 8" "Not received,Received"
|
|
bitfld.long 0x00 7. " ENDPTSETUPSTAT7 ,Endpoint setup status 7" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENDPTSETUPSTAT6 ,Endpoint setup status 6" "Not received,Received"
|
|
bitfld.long 0x00 5. " ENDPTSETUPSTAT5 ,Endpoint setup status 5" "Not received,Received"
|
|
bitfld.long 0x00 4. " ENDPTSETUPSTAT4 ,Endpoint setup status 4" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENDPTSETUPSTAT3 ,Endpoint setup status 3" "Not received,Received"
|
|
bitfld.long 0x00 2. " ENDPTSETUPSTAT2 ,Endpoint setup status 2" "Not received,Received"
|
|
bitfld.long 0x00 1. " ENDPTSETUPSTAT1 ,Endpoint setup status 1" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENDPTSETUPSTAT0 ,Endpoint setup status 0" "Not received,Received"
|
|
line.long 0x04 "USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0,USB2D Endpoint Initialization Register"
|
|
bitfld.long 0x04 31. " PETB15 ,Prime endpoint transmit buffer 15" "Don't prime,Prime"
|
|
bitfld.long 0x04 30. " PETB14 ,Prime endpoint transmit buffer 14" "Don't prime,Prime"
|
|
bitfld.long 0x04 29. " PETB13 ,Prime endpoint transmit buffer 13" "Don't prime,Prime"
|
|
bitfld.long 0x04 28. " PETB12 ,Prime endpoint transmit buffer 12" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 27. " PETB11 ,Prime endpoint transmit buffer 11" "Don't prime,Prime"
|
|
bitfld.long 0x04 26. " PETB10 ,Prime endpoint transmit buffer 10" "Don't prime,Prime"
|
|
bitfld.long 0x04 25. " PETB9 ,Prime endpoint transmit buffer 9" "Don't prime,Prime"
|
|
bitfld.long 0x04 24. " PETB8 ,Prime endpoint transmit buffer 8" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 23. " PETB7 ,Prime endpoint transmit buffer 7" "Don't prime,Prime"
|
|
bitfld.long 0x04 22. " PETB6 ,Prime endpoint transmit buffer 6" "Don't prime,Prime"
|
|
bitfld.long 0x04 21. " PETB5 ,Prime endpoint transmit buffer 5" "Don't prime,Prime"
|
|
bitfld.long 0x04 20. " PETB4 ,Prime endpoint transmit buffer 4" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PETB3 ,Prime endpoint transmit buffer 3" "Don't prime,Prime"
|
|
bitfld.long 0x04 18. " PETB2 ,Prime endpoint transmit buffer 2" "Don't prime,Prime"
|
|
bitfld.long 0x04 17. " PETB1 ,Prime endpoint transmit buffer 1" "Don't prime,Prime"
|
|
bitfld.long 0x04 16. " PETB0 ,Prime endpoint transmit buffer 0" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 15. " PERB15 ,Prime endpoint receive buffer 15" "Don't prime,Prime"
|
|
bitfld.long 0x04 14. " PERB14 ,Prime endpoint receive buffer 14" "Don't prime,Prime"
|
|
bitfld.long 0x04 13. " PERB13 ,Prime endpoint receive buffer 13" "Don't prime,Prime"
|
|
bitfld.long 0x04 12. " PERB12 ,Prime endpoint receive buffer 12" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 11. " PERB11 ,Prime endpoint receive buffer 11" "Don't prime,Prime"
|
|
bitfld.long 0x04 10. " PERB10 ,Prime endpoint receive buffer 10" "Don't prime,Prime"
|
|
bitfld.long 0x04 9. " PERB9 ,Prime endpoint receive buffer 9" "Don't prime,Prime"
|
|
bitfld.long 0x04 8. " PERB8 ,Prime endpoint receive buffer 8" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 7. " PERB7 ,Prime endpoint receive buffer 7" "Don't prime,Prime"
|
|
bitfld.long 0x04 6. " PERB6 ,Prime endpoint receive buffer 6" "Don't prime,Prime"
|
|
bitfld.long 0x04 5. " PERB5 ,Prime endpoint receive buffer 5" "Don't prime,Prime"
|
|
bitfld.long 0x04 4. " PERB4 ,Prime endpoint receive buffer 4" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PERB3 ,Prime endpoint receive buffer 3" "Don't prime,Prime"
|
|
bitfld.long 0x04 2. " PERB2 ,Prime endpoint receive buffer 2" "Don't prime,Prime"
|
|
bitfld.long 0x04 1. " PERB1 ,Prime endpoint receive buffer 1" "Don't prime,Prime"
|
|
bitfld.long 0x04 0. " PERB0 ,Prime endpoint receive buffer 0" "Don't prime,Prime"
|
|
line.long 0x08 "USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0,USB2D Endpoint De-Initialization Register"
|
|
bitfld.long 0x08 31. " FETB15 ,Flush endpoint transmit buffer 15" "Don't flush,Flush"
|
|
bitfld.long 0x08 30. " FETB14 ,Flush endpoint transmit buffer 14" "Don't flush,Flush"
|
|
bitfld.long 0x08 29. " FETB13 ,Flush endpoint transmit buffer 13" "Don't flush,Flush"
|
|
bitfld.long 0x08 28. " FETB12 ,Flush endpoint transmit buffer 12" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 27. " FETB11 ,Flush endpoint transmit buffer 11" "Don't flush,Flush"
|
|
bitfld.long 0x08 26. " FETB10 ,Flush endpoint transmit buffer 10" "Don't flush,Flush"
|
|
bitfld.long 0x08 25. " FETB9 ,Flush endpoint transmit buffer 9" "Don't flush,Flush"
|
|
bitfld.long 0x08 24. " FETB8 ,Flush endpoint transmit buffer 8" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 23. " FETB7 ,Flush endpoint transmit buffer 7" "Don't flush,Flush"
|
|
bitfld.long 0x08 22. " FETB6 ,Flush endpoint transmit buffer 6" "Don't flush,Flush"
|
|
bitfld.long 0x08 21. " FETB5 ,Flush endpoint transmit buffer 5" "Don't flush,Flush"
|
|
bitfld.long 0x08 20. " FETB4 ,Flush endpoint transmit buffer 4" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 19. " FETB3 ,Flush endpoint transmit buffer 3" "Don't flush,Flush"
|
|
bitfld.long 0x08 18. " FETB2 ,Flush endpoint transmit buffer 2" "Don't flush,Flush"
|
|
bitfld.long 0x08 17. " FETB1 ,Flush endpoint transmit buffer 1" "Don't flush,Flush"
|
|
bitfld.long 0x08 16. " FETB0 ,Flush endpoint transmit buffer 0" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 15. " FERB15 ,Flush endpoint receive buffer 15" "Don't flush,Flush"
|
|
bitfld.long 0x08 14. " FERB14 ,Flush endpoint receive buffer 14" "Don't flush,Flush"
|
|
bitfld.long 0x08 13. " FERB13 ,Flush endpoint receive buffer 13" "Don't flush,Flush"
|
|
bitfld.long 0x08 12. " FERB12 ,Flush endpoint receive buffer 12" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 11. " FERB11 ,Flush endpoint receive buffer 11" "Don't flush,Flush"
|
|
bitfld.long 0x08 10. " FERB10 ,Flush endpoint receive buffer 10" "Don't flush,Flush"
|
|
bitfld.long 0x08 9. " FERB9 ,Flush endpoint receive buffer 9" "Don't flush,Flush"
|
|
bitfld.long 0x08 8. " FERB8 ,Flush endpoint receive buffer 8" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 7. " FERB7 ,Flush endpoint receive buffer 7" "Don't flush,Flush"
|
|
bitfld.long 0x08 6. " FERB6 ,Flush endpoint receive buffer 6" "Don't flush,Flush"
|
|
bitfld.long 0x08 5. " FERB5 ,Flush endpoint receive buffer 5" "Don't flush,Flush"
|
|
bitfld.long 0x08 4. " FERB4 ,Flush endpoint receive buffer 4" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 3. " FERB3 ,Flush endpoint receive buffer 3" "Don't flush,Flush"
|
|
bitfld.long 0x08 2. " FERB2 ,Flush endpoint receive buffer 2" "Don't flush,Flush"
|
|
bitfld.long 0x08 1. " FERB1 ,Flush endpoint receive buffer 1" "Don't flush,Flush"
|
|
bitfld.long 0x08 0. " FERB0 ,Flush endpoint receive buffer 0" "Don't flush,Flush"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0,USB2D Endpoint Status Register"
|
|
bitfld.long 0x00 31. " ETBR15 ,Endpoint transmit buffer ready 15" "Not ready,Ready"
|
|
bitfld.long 0x00 30. " ETBR14 ,Endpoint transmit buffer ready 14" "Not ready,Ready"
|
|
bitfld.long 0x00 29. " ETBR13 ,Endpoint transmit buffer ready 13" "Not ready,Ready"
|
|
bitfld.long 0x00 28. " ETBR12 ,Endpoint transmit buffer ready 12" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ETBR11 ,Endpoint transmit buffer ready 11" "Not ready,Ready"
|
|
bitfld.long 0x00 26. " ETBR10 ,Endpoint transmit buffer ready 10" "Not ready,Ready"
|
|
bitfld.long 0x00 25. " ETBR9 ,Endpoint transmit buffer ready 9" "Not ready,Ready"
|
|
bitfld.long 0x00 24. " ETBR8 ,Endpoint transmit buffer ready 8" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ETBR7 ,Endpoint transmit buffer ready 7" "Not ready,Ready"
|
|
bitfld.long 0x00 22. " ETBR6 ,Endpoint transmit buffer ready 6" "Not ready,Ready"
|
|
bitfld.long 0x00 21. " ETBR5 ,Endpoint transmit buffer ready 5" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " ETBR4 ,Endpoint transmit buffer ready 4" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ETBR3 ,Endpoint transmit buffer ready 3" "Not ready,Ready"
|
|
bitfld.long 0x00 18. " ETBR2 ,Endpoint transmit buffer ready 2" "Not ready,Ready"
|
|
bitfld.long 0x00 17. " ETBR1 ,Endpoint transmit buffer ready 1" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " ETBR0 ,Endpoint transmit buffer ready 0" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ERBR15 ,Endpoint receive buffer ready 15" "Not ready,Ready"
|
|
bitfld.long 0x00 14. " ERBR14 ,Endpoint receive buffer ready 14" "Not ready,Ready"
|
|
bitfld.long 0x00 13. " ERBR13 ,Endpoint receive buffer ready 13" "Not ready,Ready"
|
|
bitfld.long 0x00 12. " ERBR12 ,Endpoint receive buffer ready 12" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERBR11 ,Endpoint receive buffer ready 11" "Not ready,Ready"
|
|
bitfld.long 0x00 10. " ERBR10 ,Endpoint receive buffer ready 10" "Not ready,Ready"
|
|
bitfld.long 0x00 9. " ERBR9 ,Endpoint receive buffer ready 9" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " ERBR8 ,Endpoint receive buffer ready 8" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERBR7 ,Endpoint receive buffer ready 7" "Not ready,Ready"
|
|
bitfld.long 0x00 6. " ERBR6 ,Endpoint receive buffer ready 6" "Not ready,Ready"
|
|
bitfld.long 0x00 5. " ERBR5 ,Endpoint receive buffer ready 5" "Not ready,Ready"
|
|
bitfld.long 0x00 4. " ERBR4 ,Endpoint receive buffer ready 4" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERBR3 ,Endpoint receive buffer ready 3" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " ERBR2 ,Endpoint receive buffer ready 2" "Not ready,Ready"
|
|
bitfld.long 0x00 1. " ERBR1 ,Endpoint receive buffer ready 1" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " ERBR0 ,Endpoint receive buffer ready 0" "Not ready,Ready"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0,USB2D Endpoint Complete Register"
|
|
bitfld.long 0x00 31. " ETCE15 ,Endpoint transmit buffer complete event 15" "Not completed,Completed"
|
|
bitfld.long 0x00 30. " ETCE14 ,Endpoint transmit buffer complete event 14" "Not completed,Completed"
|
|
bitfld.long 0x00 29. " ETCE13 ,Endpoint transmit buffer complete event 13" "Not completed,Completed"
|
|
bitfld.long 0x00 28. " ETCE12 ,Endpoint transmit buffer complete event 12" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ETCE11 ,Endpoint transmit buffer complete event 11" "Not completed,Completed"
|
|
bitfld.long 0x00 26. " ETCE10 ,Endpoint transmit buffer complete event 10" "Not completed,Completed"
|
|
bitfld.long 0x00 25. " ETCE9 ,Endpoint transmit buffer complete event 9" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " ETCE8 ,Endpoint transmit buffer complete event 8" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ETCE7 ,Endpoint transmit buffer complete event 7" "Not completed,Completed"
|
|
bitfld.long 0x00 22. " ETCE6 ,Endpoint transmit buffer complete event 6" "Not completed,Completed"
|
|
bitfld.long 0x00 21. " ETCE5 ,Endpoint transmit buffer complete event 5" "Not completed,Completed"
|
|
bitfld.long 0x00 20. " ETCE4 ,Endpoint transmit buffer complete event 4" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ETCE3 ,Endpoint transmit buffer complete event 3" "Not completed,Completed"
|
|
bitfld.long 0x00 18. " ETCE2 ,Endpoint transmit buffer complete event 2" "Not completed,Completed"
|
|
bitfld.long 0x00 17. " ETCE1 ,Endpoint transmit buffer complete event 1" "Not completed,Completed"
|
|
bitfld.long 0x00 16. " ETCE0 ,Endpoint transmit buffer complete event 0" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ERCE15 ,Endpoint receive buffer complete event 15" "Not completed,Completed"
|
|
bitfld.long 0x00 14. " ERCE14 ,Endpoint receive buffer complete event 14" "Not completed,Completed"
|
|
bitfld.long 0x00 13. " ERCE13 ,Endpoint receive buffer complete event 13" "Not completed,Completed"
|
|
bitfld.long 0x00 12. " ERCE12 ,Endpoint receive buffer complete event 12" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERCE11 ,Endpoint receive buffer complete event 11" "Not completed,Completed"
|
|
bitfld.long 0x00 10. " ERCE10 ,Endpoint receive buffer complete event 10" "Not completed,Completed"
|
|
bitfld.long 0x00 9. " ERCE9 ,Endpoint receive buffer complete event 9" "Not completed,Completed"
|
|
bitfld.long 0x00 8. " ERCE8 ,Endpoint receive buffer complete event 8" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERCE7 ,Endpoint receive buffer complete event 7" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " ERCE6 ,Endpoint receive buffer complete event 6" "Not completed,Completed"
|
|
bitfld.long 0x00 5. " ERCE5 ,Endpoint receive buffer complete event 5" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " ERCE4 ,Endpoint receive buffer complete event 4" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERCE3 ,Endpoint receive buffer complete event 3" "Not completed,Completed"
|
|
bitfld.long 0x00 2. " ERCE2 ,Endpoint receive buffer complete event 2" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " ERCE1 ,Endpoint receive buffer complete event 1" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " ERCE0 ,Endpoint receive buffer complete event 0" "Not completed,Completed"
|
|
else
|
|
hgroup.long 0x208++0x13
|
|
hide.long 0x00 "USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0,USB2D Endpoint Setup Status Register"
|
|
hide.long 0x04 "USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0,USB2D Endpoint Initialization Register"
|
|
hide.long 0x08 "USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0,USB2D Endpoint De-Initialization Register"
|
|
hide.long 0x0C "USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0,USB2D Endpoint Status Register"
|
|
hide.long 0x10 "USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0,USB2D Endpoint Complete Register"
|
|
endif
|
|
tree.end
|
|
width 39.
|
|
tree "Endpoint Control"
|
|
rgroup.long 0x21C++0x03
|
|
line.long 0x00 "USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0,USB2D Endpoint Control 0 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
bitfld.long 0x00 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
bitfld.long 0x00 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
group.long 0x220++0x3B
|
|
line.long 0x0 "USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0,USB2D Endpoint Control 1 Register"
|
|
bitfld.long 0x0 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x0 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x0 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x0 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x0 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x0 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x0 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x0 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x4 "USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0,USB2D Endpoint Control 2 Register"
|
|
bitfld.long 0x4 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x4 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x4 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x4 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x4 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x4 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x4 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x4 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x8 "USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0,USB2D Endpoint Control 3 Register"
|
|
bitfld.long 0x8 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x8 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x8 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x8 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x8 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x8 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x8 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x8 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x8 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x8 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0xC "USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0,USB2D Endpoint Control 4 Register"
|
|
bitfld.long 0xC 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0xC 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0xC 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0xC 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0xC 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0xC 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0xC 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0xC 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0xC 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0xC 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x10 "USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0,USB2D Endpoint Control 5 Register"
|
|
bitfld.long 0x10 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x10 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x10 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x10 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x10 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x10 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x10 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x14 "USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0,USB2D Endpoint Control 6 Register"
|
|
bitfld.long 0x14 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x14 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x14 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x14 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x14 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x14 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x14 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x14 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x18 "USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0,USB2D Endpoint Control 7 Register"
|
|
bitfld.long 0x18 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x18 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x18 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x18 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x18 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x18 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x18 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x18 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x18 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x1C "USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0,USB2D Endpoint Control 8 Register"
|
|
bitfld.long 0x1C 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x1C 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x1C 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x1C 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x1C 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x1C 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x1C 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x20 "USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0,USB2D Endpoint Control 9 Register"
|
|
bitfld.long 0x20 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x20 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x20 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x20 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x20 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x20 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x20 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x20 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x20 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x24 "USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0,USB2D Endpoint Control 10 Register"
|
|
bitfld.long 0x24 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x24 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x24 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x24 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x24 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x24 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x24 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x24 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x24 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x28 "USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0,USB2D Endpoint Control 11 Register"
|
|
bitfld.long 0x28 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x28 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x28 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x28 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x28 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x28 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x28 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x28 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x28 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x2C "USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0,USB2D Endpoint Control 12 Register"
|
|
bitfld.long 0x2C 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x2C 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x2C 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x2C 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x2C 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x2C 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x2C 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x2C 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x30 "USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0,USB2D Endpoint Control 13 Register"
|
|
bitfld.long 0x30 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x30 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x30 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x30 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x30 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x30 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x30 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x30 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x30 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x34 "USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0,USB2D Endpoint Control 14 Register"
|
|
bitfld.long 0x34 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x34 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x34 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x34 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x34 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x34 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x34 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x34 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x34 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x38 "USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0,USB2D Endpoint Control 15 Register"
|
|
bitfld.long 0x38 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x38 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x38 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x38 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x38 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x38 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x38 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x38 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x38 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x38 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
tree.end
|
|
tree.end
|
|
width 28.
|
|
tree "USB 2 Controller Interface"
|
|
if (((d.l(ad:0x7D004000+0x1F8))&0x03)==0x02)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "USB2_IF_USB_SUSP_CTRL_0,USB suspend control register"
|
|
bitfld.long 0x00 25. " UTMIP_SUSPL1_SET ,Enable SuspendL1 for UTMIP PHY" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 24. " ULPI_PADS_CLKEN_RESET ,Async reset for the synchronizers" "Disabled,Enabled"
|
|
eventfld.long 0x00 23. " ULPI_PADS_RESET ,Async reset for trimmers and line state logic" "Disabled,Enabled"
|
|
eventfld.long 0x00 22. " ULPIS2S_LINE_RESET ,Async reset of the line simulator logic" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 21. " ULPIS2S_SLV1_RESET ,Async reset of the SLV1 ULPI logic" "Disabled,Enabled"
|
|
eventfld.long 0x00 20. " ULPIS2S_SLV0_RESET ,Async reset of the SLV0 ULPI logic" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " UHSIC_PHY_ENB ,Enable UHSIC PHY mode (Set this to 0)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " USB_WAKEUP_DEBOUNCE_COUNT ,USB PHY wakeup debounce counter" "0,1,2,3,4,5,6,7"
|
|
eventfld.long 0x00 14. " UHSIC_RESET ,Reset going to UHSIC PHY" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ICUSB_PHY_ENB ,Enable ICUSB PHY mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " UTMIP_PHY_ENB ,Enable UTMIP PHY mode" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " UTMIP_RESET ,Reset goint to UTMIP PHY" "Not reset,Reset"
|
|
bitfld.long 0x00 10. " USB_SUSUP_POL ,Polarity of the suspend signal going to USB PHY" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 9. " USB_PHY_CLK_VALID_INT_ENB ,USB PHY clock valid interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " USB_PHY_CLK_VALID_INT_STS ,USB PHY clock valid interrupt status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " USB_PHY_CLK_VALID ,USB PHY clock valid status" "Invalid,Valid"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " USB_CLKEN ,USB AHB clock enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " USB_SUSP_CLR ,PHY suspend mode control" "Suspended,Not suspended"
|
|
bitfld.long 0x00 4. " USB_WAKE_ON_DISCON_EN_DEV ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USB_WAKE_ON_CNNT_EN_DEV ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " USB_WAKE_ON_RESUME_EN ,Wake on resume" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " USB_WAKEUP_INT_ENB ,USB wakeup interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " USB_WAKEUP_INT_STS ,USB wakeup interrupt status" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "USB2_IF_USB_SUSP_CTRL_0,USB suspend control register"
|
|
bitfld.long 0x00 26. " FAST_WAKEUP_RESP ,Enable fast response from UTMIP PHY for a remote wakeup request from device" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " UTMIP_SUSPL1_SET ,Enable SuspendL1 for UTMIP PHY" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 24. " ULPI_PADS_CLKEN_RESET ,Async reset for the synchronizers" "Disabled,Enabled"
|
|
eventfld.long 0x00 23. " ULPI_PADS_RESET ,Async reset for trimmers and line state logic" "Disabled,Enabled"
|
|
eventfld.long 0x00 22. " ULPIS2S_LINE_RESET ,Async reset of the line simulator logic" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 21. " ULPIS2S_SLV1_RESET ,Async reset of the SLV1 ULPI logic" "Disabled,Enabled"
|
|
eventfld.long 0x00 20. " ULPIS2S_SLV0_RESET ,Async reset of the SLV0 ULPI logic" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " UHSIC_PHY_ENB ,Enable UHSIC PHY mode (Set this to 0)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " USB_WAKEUP_DEBOUNCE_COUNT ,USB PHY wakeup debounce counter" "0,1,2,3,4,5,6,7"
|
|
eventfld.long 0x00 14. " UHSIC_RESET ,Reset going to UHSIC PHY" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ICUSB_PHY_ENB ,Enable ICUSB PHY mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " UTMIP_PHY_ENB ,Enable UTMIP PHY mode" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " UTMIP_RESET ,Reset goint to UTMIP PHY" "Not reset,Reset"
|
|
bitfld.long 0x00 10. " USB_SUSUP_POL ,Polarity of the suspend signal going to USB PHY" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 9. " USB_PHY_CLK_VALID_INT_ENB ,USB PHY clock valid interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " USB_PHY_CLK_VALID_INT_STS ,USB PHY clock valid interrupt status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " USB_PHY_CLK_VALID ,USB PHY clock valid status" "Invalid,Valid"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " USB_CLKEN ,USB AHB clock enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " USB_SUSP_CLR ,PHY suspend mode control" "Suspended,Not suspended"
|
|
bitfld.long 0x00 2. " USB_WAKE_ON_RESUME_EN ,Wake on resume" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " USB_WAKEUP_INT_ENB ,USB wakeup interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " USB_WAKEUP_INT_STS ,USB wakeup interrupt status" "No interrupt,Interrupt"
|
|
endif
|
|
textline ""
|
|
width 34.
|
|
group.long 0x404++0x07
|
|
line.long 0x00 "USB2_IF_USB_PHY_VBUS_SENSORS_0,USB PHY VBUS SENSORS control register"
|
|
bitfld.long 0x00 30. " A_VBUS_VLD_WAKEUP_EN ,A_VBUS_VLD wakeup enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " A_VBUS_VLD_DEB_SEL_B ,A_VBUS_VLD debounce A/B select" "SEL_A,SEL_B"
|
|
bitfld.long 0x00 28. " A_VBUS_VLD_SW_VALUE ,A_VBUS_VLD software value (software enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " A_VBUS_VLD_SW_EN ,A_VBUS_VLD software enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " A_VBUS_VLD_STS ,A_VBUS_VLD status" "Low,High"
|
|
rbitfld.long 0x00 25. " A_VBUS_VLD_CHG_DET ,A_VBUS_VLD change detect" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 24. " A_VBUS_VLD_INT_EN ,A_VBUS_VLD interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " A_SESS_VLD_WAKEUP_EN ,A_SESS_VLD wakeup enable" "Disabled,Enabled"
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|
bitfld.long 0x00 21. " A_SESS_VLD_DEB_SEL_B ,A_SESS_VLD debounce A/B select" "SEL_A,SEL_B"
|
|
textline " "
|
|
bitfld.long 0x00 20. " A_SESS_VLD_SW_VALUE ,A_SESS_VLD software value (software enabled)" "Low,High"
|
|
bitfld.long 0x00 19. " A_SESS_VLD_SW_EN ,A_SESS_VLD software enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 18. " A_SESS_VLD_STS ,A_SESS_VLD status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " A_SESS_VLD_CHG_DET ,A_SESS_VLD change detect" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " A_SESS_VLD_INT_EN ,A_SESS_VLD interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " B_SESS_VLD_WAKEUP_EN ,B_SESS_VLD wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B_SESS_VLD_DEB_SEL_B ,B_SESS_VLD debounce A/B select" "SEL_A,SEL_B"
|
|
bitfld.long 0x00 12. " B_SESS_VLD_SW_VALUE ,B_SESS_VLD software value (software enabled)" "Low,High"
|
|
bitfld.long 0x00 11. " B_SESS_VLD_SW_EN ,B_SESS_VLD software enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " B_SESS_VLD_STS ,B_SESS_VLD status" "Low,High"
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|
rbitfld.long 0x00 9. " B_SESS_VLD_CHG_DET ,B_SESS_VLD change detect" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " B_SESS_VLD_INT_EN ,B_SESS_VLD interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " B_SESS_END_WAKEUP_EN ,B_SESS_END wakeup enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " B_SESS_END_DEB_SEL_B ,B_SESS_END debounce A/B select" "SEL_A,SEL_B"
|
|
bitfld.long 0x00 4. " B_SESS_END_SW_VALUE ,B_SESS_END software value (software enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B_SESS_END_SW_EN ,B_SESS_END software enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " B_SESS_END_STS ,B_SESS_END status" "Low,High"
|
|
rbitfld.long 0x00 1. " B_SESS_END_CHG_DET ,B_SESS_END change detect" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " B_SESS_END_INT_EN ,B_SESS_END interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "USB2_IF_USB_PHY_VBUS_WAKEUP_ID_0,USB PHY VBUS wakeup and ID control register"
|
|
bitfld.long 0x04 31. " DIV_DET_EN ,Battery charger divider detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " VBUS_WAKEUP_WAKEUP_EN ,VBUS_WAKEUP wakeup enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " VDCD_DET_DEB_SEL_B ,VCDT_DET debounce A/B select" "SEL_A,SEL_B"
|
|
textline " "
|
|
bitfld.long 0x04 28. " VDCD_DET_SW_VALUE ,VDCD_DET software value (software enabled)" "Low,High"
|
|
bitfld.long 0x04 27. " VDCD_DET_SW_EN ,VDCD_DET software enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 26. " VDCD_DET_STS ,VDCD_DET status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x04 25. " VDCD_DET_CHG_DET ,VDCD_DET change detect" "Not detected,Detected"
|
|
bitfld.long 0x04 24. " VDCD_DET_INT_EN ,VDCD_DET interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 23. " VOP_DIV2P7_DET ,Status bit is from the battery charging divider circuit of the USB2OTG pad" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x04 22. " VOP_DIV2P0_DET ,Status bit is from the battery charging divider circuit of the USB2OTG pad" "Low,High"
|
|
bitfld.long 0x04 21. " VDAT_DET_DEB_SEL_B ,VDAT_DET debounce A/B select" "SEL_A,SEL_B"
|
|
bitfld.long 0x04 20. " VDAT_DET_SW_VALUE ,VDAT_DET software value (software enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 19. " VDAT_DET_SW_EN ,VDAT_DET software enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 18. " VDAT_DET_STS ,VDAT_DET status" "Low,High"
|
|
rbitfld.long 0x04 17. " VDAT_DET_CHG_DET ,VDAT_DET change detect" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 16. " VDAT_DET_INT_EN ,VDAT_DET interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " VON_DIV2P7_DET ,Status bit is from the battery charging divider circuit of the USB2OTG pad" "Low,High"
|
|
bitfld.long 0x04 14. " VON_DIV2P0_DET ,Status bit is from the battery charging divider circuit of the USB2OTG pad" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 13. " VBUS_WAKEUP_DEB_SEL_B ,VBUS_WAKEUP debounce A/B select" "SEL_A,SEL_B"
|
|
bitfld.long 0x04 12. " VBUS_WAKEUP_SW_VALUE ,VBUS wakeup software value (software enabled)" "Low,High"
|
|
bitfld.long 0x04 11. " VBUS_WAKEUP_SW_EN ,VBUS wakeup software enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 10. " VBUS_WAKEUP_STS ,VBUS wakeup status" "Low,High"
|
|
rbitfld.long 0x04 9. " VBUS_WAKEUP_CHG_DET ,VBUS wakeup change detect" "Not detected,Detected"
|
|
bitfld.long 0x04 8. " VBUS_WAKEUP_INT_EN ,VBUS wakeup interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 7. " STATIC_GPI ,Static GPI status" "Low,High"
|
|
bitfld.long 0x04 6. " ID_PU ,ID pullup enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " ID_DEB_SEL_B ,ID debounce A/B select" "SEL_A,SEL_B"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ID_SW_VALUE ,ID software value (software enabled)" "Low,High"
|
|
bitfld.long 0x04 3. " ID_SW_EN ,ID software enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 2. " ID_STS ,ID status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " ID_CHG_DET ,ID change detect" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " ID_INT_EN ,ID interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "USB2_IF_USB_PHY_ALT_VBUS_STS_0,USB PHY Alternate VBUS status register"
|
|
bitfld.long 0x00 8. " VDCD_DET_ALT ,VDCD_DET alternate status" "Low,High"
|
|
bitfld.long 0x00 7. " VDAT_DET_ALT ,VDAT_DET alternate status" "Low,High"
|
|
bitfld.long 0x00 6. " A_SESS_VLD_ALT ,A_SESS_VLD alternate status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B_SESS_VLD_ALT ,B_SESS_VLD alternate status" "Low,High"
|
|
bitfld.long 0x00 4. " ID_DIG_ALT ,ID alternate status" "Low,High"
|
|
bitfld.long 0x00 3. " B_SESS_END_ALT ,B_SESS_END alternate status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " STATIC_GPI_ALT ,Static GPI alternate status" "Low,High"
|
|
bitfld.long 0x00 1. " A_VBUS_VLD_ALT ,A_VBUS_VLD alternate status" "Low,High"
|
|
bitfld.long 0x00 0. " VBUS_WAKEUP_ALT ,Vbus wakeup alternate status" "Low,High"
|
|
textline ""
|
|
width 36.
|
|
group.long 0x418++0x07
|
|
line.long 0x00 "USB2_IF_USB_ULPIS2S_CTRL_0,ULPI NULL PHY control register"
|
|
bitfld.long 0x00 20.--23. " ULPIS2S_CLAMP_LINE_DRIVE ,The line drive value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 17. " ULPIS2S_SLV1_CLAMP_XMIT ,When set to 1, the outputs of the SLV1 xmit statemachine are clamped to 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ULPIS2S_SLV0_CLAMP_XMIT ,When set to 1, the outputs of the SLV0 xmit statemachine are clamped to 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ULPIS2S_DISABLE_STP_PU ,The pullup on the STP pin active status settings" "No,Yes"
|
|
bitfld.long 0x00 14. " ULPIS2S_SUPPORT_HS_KEEP_ALIVE ,When enabled, the PHY will support HS KeepAlive packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ULPIS2S_DISCON_DONT_CHECK_SE0 ,Disconnect detection logic will only check that that the other side is 'driving' tri-state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ULPIS2S_FORCE_ULPI_CLK_OUT ,The external ULPI_CLOCK pad will always carry the internal 60MHz clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ULPIS2S_PLLU_MASTER_BLASTER60 ,When enabled, the PLLU 60MHz clock will be forced on" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ULPIS2S_SUPPORT_DISCONNECT ,When disabled, the PHY will never detect a Disconnect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ULPIS2S_SLV1_FORCE_DEVICE ,Slave port host or device programming" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " ULPIS2S_ENA ,The ULPI link interface coming out of the usb2 controller enters a NULL phy with two slaves" "Disabled,Enabled"
|
|
line.long 0x04 "USB2_IF_USB_ULPIS2S_SLV1_ID_0,Control product and vendor ID fields"
|
|
hexmask.long.word 0x04 16.--31. 1. " ULPIS2S_SLV1_VENDOR_ID ,PHY vendor_id as seen by external ULPI master"
|
|
hexmask.long.word 0x04 0.--15. 1. " ULPIS2S_SLV1_PRODUCT_ID ,PHY product_id as seen by external ULPI master"
|
|
if (((d.l(ad:0x7D004000+0x1F8))&0x03)==0x03)
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "USB2_IF_USB_INTER_PKT_DELAY_CTRL_0,Inter packet delay control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " IP_DELAY_TX2TX_HS ,HS Tx to Tx inter-packet delay"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "USB2_IF_USB_RSM_DLY_0,USB Controller Resume Signalling Delay"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIME_TO_RESUME ,Send the resume back in no. of 60 MHz cycles"
|
|
else
|
|
hgroup.long 0x420++0x03
|
|
hide.long 0x00 "USB2_IF_USB_INTER_PKT_DELAY_CTRL_0,Inter packet delay control"
|
|
hgroup.long 0x490++0x03
|
|
hide.long 0x00 "USB2_IF_USB_RSM_DLY_0,USB Controller Resume Signalling Delay"
|
|
endif
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "USB2_IF_SPARE_0,ICUSB PADCTLS Spare Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPARE_HI ,Spare register bits"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPARE_LO ,Spare register bits"
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "USB2_IF_ULPI_DIR_OVERRIDE_0,ULPI Override"
|
|
bitfld.long 0x00 1. " ULPI_DIR_OVERRIDE ,ulpi_dir override" "No override,Override"
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "USB2_IF_USB1_NEW_CONTROL_0,USB Coherency and Memory Alignment Controls"
|
|
hexmask.long.byte 0x00 8.--15. 1. " REQUEST_EXPIRY_COUNTER ,Time to wait for coalescing the request"
|
|
bitfld.long 0x00 1. " MEM_ALIGNMENT_MUX_EN ,DMA request generation mechanism" "Tegra 3,Tegra K1"
|
|
bitfld.long 0x00 0. " COHERENCY_EN ,Enable fence mechanism" "Disabled,Enabled"
|
|
tree.end
|
|
width 28.
|
|
tree "USB 2 UTMIP Configuration"
|
|
group.long 0x808++0x37
|
|
line.long 0x00 "USB2_UTMIP_XCVR_CFG0_0,UTMIP transceiver cell configuration register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. " UTMIP_XCVR_HSSLEW_MSB ,Most significant bits of HS_SLEW"
|
|
bitfld.long 0x00 22.--24. " UTMIP_XCVR_SETUP_MSB ,Most significant bits of SETUP" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
eventfld.long 0x00 21. " UTMIP_XCVR_LSBIAS_SEL ,Low speed bias selection method for usb transceiver pad" "0,1"
|
|
bitfld.long 0x00 20. " UTMIP_XCVR_DISCON_METHOD ,Disconnect method on the usb transceiver pad" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " UTMIP_FORCE_PDZI_POWERUP ,Force PDZI input into power up" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " UTMIP_FORCE_PDZI_POWERDOWN ,Force PDZI input into power down" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " UTMIP_FORCE_PD2_POWERUP ,Force PD2 input into power up" "Disabled,Enabled"
|
|
eventfld.long 0x00 16. " UTMIP_FORCE_PD2_POWERDOWN ,Force PD2 input into power down" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " UTMIP_FORCE_PD_POWERUP ,Force PD input into power up" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " UTMIP_FORCE_PD_POWERDOWN ,Force PD input into power down" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 13. " UTMIP_XCVR_TERMEN ,Enable HS termination" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UTMIP_XCVR_HSLOOPBACK ,Internal loopback inside XCVR cell" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " UTMIP_XCVR_LSFSLEW ,LS falling slew rate control" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " UTMIP_XCVR_LSRSLEW ,LS rising slew rate control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " UTMIP_XCVR_FSSLEW ,FS slew rate control" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " UTMIP_XCVR_HSSLEW ,HS slew rate control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " UTMIP_XCVR_SETUP ,SETUP[3:0] input of XCVR cell" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "USB2_UTMIP_BIAS_CFG0_0,UTMIP Bias cell configuration register 0"
|
|
bitfld.long 0x04 30. " UTMIP_IDDIG_C_VAL ,UTMIP IDDIG C VAL" "0,1"
|
|
bitfld.long 0x04 29. " UTMIP_IDDIG_C_SEL ,UTMIP IDDIG C SEL" "IdDig_c,IDDIG_C_VAL"
|
|
textline " "
|
|
bitfld.long 0x04 28. " UTMIP_IDDIG_B_VAL ,UTMIP IDDIG B VAL" "0,1"
|
|
bitfld.long 0x04 27. " UTMIP_IDDIG_B_SEL ,UTMIP IDDIG B SEL" "IdDig_b,IDDIG_B_VAL"
|
|
textline " "
|
|
bitfld.long 0x04 26. " UTMIP_IDDIG_A_VAL ,UTMIP IDDIG A VAL" "0,1"
|
|
bitfld.long 0x04 25. " UTMIP_IDDIG_A_SEL ,UTMIP IDDIG A SEL" "IdDig_a,IDDIG_A_VAL"
|
|
textline " "
|
|
bitfld.long 0x04 24. " UTMIP_HSDISCON_LEVEL_MSB ,Most significant bit of UTMIP_HSDISCON_LEVEL" "0,1"
|
|
eventfld.long 0x04 23. " UTMIP_IDPD_VAL ,IDPD value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 21. " UTMIP_IDDIG_SEL ,IDDIG value" "0,1"
|
|
bitfld.long 0x04 20. " UTMIP_IDDIG_SEL ,IDDIG select" "IdDig,IDDIG_VAL"
|
|
textline " "
|
|
bitfld.long 0x04 19. " UTMIP_GPI_VAL ,GPI value" "0,1"
|
|
bitfld.long 0x04 18. " UTMIP_GPI_SEL ,GPI select" "IdDig,GPI_VAL"
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " UTMIP_ACTIVE_TERM_OFFSET ,Active termination control offset" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 12.--14. " UTMIP_ACTIVE_PULLUP_OFFSET ,Active 1.5K pullup control offset" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
eventfld.long 0x04 11. " UTMIP_OTGPD ,Power down OTG circuit" "Disabled,Enabled"
|
|
eventfld.long 0x04 10. " UTMIP_BIASPD ,Power down bias circuit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " UTMIP_VBUS_LEVEL_LEVEL ,Vbus detector level" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " UTMIP_SESS_LEVEL_LEVEL ,SessionEnd detector level" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " UTMIP_HSCHIRP_LEVEL ,HS chirp detector level" "0,1,2,3"
|
|
bitfld.long 0x04 2.--3. " UTMIP_HSDISCON_LEVEL ,HS disconnect detector level" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " UTMIP_HSSQUELCH_LEVEL ,HS squelch detector level" "0,1,2,3"
|
|
line.long 0x08 "USB2_UTMIP_HSRX_CFG0_0,UTMIP High speed receive config 0"
|
|
bitfld.long 0x08 30.--31. " UTMIP_KEEP_PATT_ON_ACTIVE ,Keep the stay alive pattern on active" "0,1,2,3"
|
|
bitfld.long 0x08 29. " UTMIP_ALLOW_CONSEC_UPDN ,Allow consecutive ups and downs on the bits" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 28. " UTMIP_REALIGN_ON_NEW_PKT ,Realign the inertia counters on a new packet" "Disabled,Enabled"
|
|
bitfld.long 0x08 24.--27. " UTMIP_PCOUNT_UPDN_DIV ,The number of (edges-1) needed to move the sampling point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 21.--23. " UTMIP_SQUELCH_EOP_DLY ,Limit the delay of the squelch at EOP time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 20. " UTMIP_NO_STRIPPING ,Do not strip incoming data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15.--19. " UTMIP_IDLE_WAIT ,Number of cycles of idle to declare IDLE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 10.--14. " UTMIP_ELASTIC_LIMIT ,Depth of elastic input store" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 9. " UTMIP_ELASTIC_OVERRUN_DISABLE ,Do not declare overrun errors until overflow of FIFO" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " UTMIP_ELASTIC_UNDERRUN_DISABLE ,Do not declare underrun errors" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " UTMIP_PASS_CHIRP ,When in Chirp Mode, allow chirp rx data through" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " UTMIP_PASS_FEEDBACK ,Pass through the feedback, do not block it" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " UTMIP_PCOUNT_INERTIA ,Retime the path" "0,1,2,3"
|
|
bitfld.long 0x08 2.--3. " UTMIP_PHASE_ADJUST ,Based on incoming edges and current sampling position phase adjust" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 1. " UTMIP_THREE_SYNCBITS ,Sync pattern detection needs 3 consecutive samples instead of 4" "No,Yes"
|
|
bitfld.long 0x08 0. " UTMIP_USE4SYNC_TRAN ,Require 4 sync pattern transitions (01) instead of 3" "No,Yes"
|
|
line.long 0x0C "USB2_UTMIP_HSRX_CFG1_0,UTMIP High speed receive config 1"
|
|
bitfld.long 0x0C 1.--5. " UTMIP_HS_SYNC_START_DLY ,How long to wait before start of sync launches RxActive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 0. " UTMIP_HS_ALLOW_KEEP_ALIVE ,Allow Keep Alive packets" "Disabled,Enabled"
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|
line.long 0x10 "USB2_UTMIP_FSLSRX_CFG0_0,UTMIP full and Low speed receive config 0"
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bitfld.long 0x10 31. " UTMIP_FSLS_SE1_DRIBBLE_FILTER ,Don't allow dribble" "Disabled,Enabled"
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bitfld.long 0x10 30. " UTMIP_FSLS_SE1_FILTER ,Filter SE1" "0,1"
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|
textline " "
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bitfld.long 0x10 29. " UTMIP_FSLS_SERIAL_SE0_RCV ,UTMIP_FSLS_SERIAL_SE0_RCV" "0,1"
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bitfld.long 0x10 26.--28. " UTMIP_FSLS_UPR_DRIBBLE_SIZE ,Do not allow <= dribble bits" "0,1,2,3,4,5,6,7"
|
|
textline " "
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bitfld.long 0x10 23.--25. " UTMIP_FSLS_LWR_DRIBBLE_SIZE ,Do not allow >= dribble bits" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x10 22. " UTMIP_FSLS_EOP_ENDS_AT_SE0 ,Only look for transitioning out of EOP" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x10 16.--21. " UTMIP_FSLS_KCOUNT_MAX ,Number of K bits in question" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x10 15. " UTMIP_FSLS_KCOUNT_LIMIT ,Limit the number of bit times a K can last" "No,Yes"
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|
textline " "
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|
bitfld.long 0x10 14. " UTMIP_FSLS_ACTIVE_ON_FULL_SYNC ,Require a full sync pattern to declare the data received" "No,Yes"
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|
bitfld.long 0x10 8.--13. " UTMIP_FSLS_IDLE_WAIT_MAX ,IDLE wait max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
textline " "
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bitfld.long 0x10 7. " UTMIP_FSLS_IDLE_WAIT_LIMIT ,Enable the reset of the state machine on extended SE0" "Disabled,Enabled"
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|
bitfld.long 0x10 1.--6. " UTMIP_FSLS_IDLE_COUNT_MAX ,Idle count max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
textline " "
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bitfld.long 0x10 0. " UTMIP_FSLS_IDLE_COUNT_LIMIT ,Give up on packet if a long sequence of J" "No,Yes"
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|
line.long 0x14 "USB2_UTMIP_FSLSRX_CFG1_0,UTMIP full and Low speed receive config 1"
|
|
bitfld.long 0x14 26. " UTMIP_EARLY_LINE_STATE_FILTER ,Assumes line state filtering table is inclusive" "No,Yes"
|
|
bitfld.long 0x14 23.--25. " UTMIP_LS_BOUNCE_LENGTH ,Number of clock cycle of LS stable" "0,1,2,3,4,5,6,7"
|
|
textline " "
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bitfld.long 0x14 17.--22. " UTMIP_LS_EXTRACTION_COUNT ,Phase count on which LS bits are extracted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 11.--16. " UTMIP_LS_EOP_START_COUNT ,Number of SEO clock cycles to block bit extraction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
textline " "
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bitfld.long 0x14 5.--10. " UTMIP_LS_SE0_COUNT ,Only for this number of 60MHz of SEO and Idle to end packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 4. " UTMIP_LS_LENIENT_DRIBBLE ,Allow for large dribble in low speed mode" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x14 3. " UTMIP_FS_LENIENT_DRIBBLE ,Allow for large dribble in full speed mode" "Disabled,Enabled"
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bitfld.long 0x14 2. " UTMIP_FS_WEAK_SYNC ,Only look for a KK pattern instead of KJKK" "No,Yes"
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|
textline " "
|
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bitfld.long 0x14 1. " UTMIP_FS_DEBOUNCE ,Whether full speed uses debouncing" "No,Yes"
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bitfld.long 0x14 0. " UTMIP_FS_EOP_LENGTH ,Whether full speed EOP is determined within 3(0) or 4(1) 60MHz cycles" "3 cycles,4 cycles"
|
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line.long 0x18 "USB2_UTMIP_TX_CFG0_0,UTMIP transmit config signals"
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bitfld.long 0x18 19. " UTMIP_FS_PREAMBLE_J ,Output enable sends an initial J before sync pattern" "Disabled,Enabled"
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bitfld.long 0x18 18. " UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE ,Output enable turns off 1/2 cycle after" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x18 17. " UTMIP_FS_PREAMBLE_OUTPUT_ENABLE ,Output enable turns on 1/2 cycle before" "Disabled,Enabled"
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bitfld.long 0x18 16. " UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR ,Allow SOP to be source of transmit error stuffing" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x18 15. " UTMIP_HS_READY_WAIT_FOR_VALID ,UTMIP_HS_READY_WAIT_FOR_VALID" "0,1"
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bitfld.long 0x18 10.--14. " UTMIP_HS_TX_IPG_DLY ,UTMIP_HS_TX_IPG_DLY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
textline " "
|
|
bitfld.long 0x18 9. " UTMIP_HS_DISCON_EOP_ONLY ,Only check during EOP" "No,Yes"
|
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bitfld.long 0x18 8. " UTMIP_HS_DISCON_DISABLE ,Disable high speed disconnect" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x18 7. " UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE ,Output enable turns off 1 cycle after" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " UTMIP_HS_PREAMBLE_OUTPUT_ENABLE ,Output enable turns on 1 cycle before" "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x18 5. " UTMIP_SIE_RESUME_ON_LINESTATE ,SIE (not macrocell) detects LineState change to resume" "No,Yes"
|
|
bitfld.long 0x18 4. " UTMIP_SOF_ON_NO_STUFF ,Sof when OpMode 3 -- perhaps, when sending controller made packets" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 3. " UTMIP_SOF_ON_NO_ENCODE ,Sof when OpMode 2 -- not likely, for Chirp" "0,1"
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|
bitfld.long 0x18 2. " UTMIP_NO_STUFFING ,No bit stuffing, static programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 1. " UTMIP_NO_ENCODING ,No encoding, static programming" "0,1"
|
|
bitfld.long 0x18 0. " UTMIP_NO_SYNC_NO_EOP ,Do not sent SYNC or EOP" "Disabled,Enabled"
|
|
line.long 0x1C "USB2_UTMIP_MISC_CFG0_0,UTMIP miscellaneous configurations"
|
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bitfld.long 0x1C 27.--30. " UTMIP_DPDM_OBSERVE_SEL ,Select DP/DM obs signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.long 0x1C 26. " UTMIP_DPDM_OBSERVE ,Use DP/DM as obs bus" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 25. " UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON ,UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON" "0,1"
|
|
bitfld.long 0x1C 24. " UTMIP_ALLOW_LS_ON_SOFT_DISCON ,UTMIP_ALLOW_LS_ON_SOFT_DISCON" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 23. " UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP ,UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP" "0,1"
|
|
bitfld.long 0x1C 22. " UTMIP_SUSPEND_EXIT_ON_EDGE ,Suspend exit requires edge or simply a value" "0,1"
|
|
textline " "
|
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bitfld.long 0x1C 21. " UTMIP_LS_TO_FS_SKIP_4MS ,Don't block changes for 4ms when going from LS to FS" "0,1"
|
|
bitfld.long 0x1C 19.--20. " UTMIP_INJECT_ERROR_TYPE ,Force error insertion into RX path" "Disabled,BIT_ERR,RX_ERR,BIT_RX_ERR"
|
|
textline " "
|
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bitfld.long 0x1C 18. " UTMIP_FORCE_HS_CLOCK_ON ,Force HS clock always on" "Disabled,Enabled"
|
|
bitfld.long 0x1C 17. " UTMIP_DISABLE_HS_TERM ,Force HS termination inactive" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 16. " UTMIP_FORCE_HS_TERM ,Force HS termination active" "Disabled,Enabled"
|
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bitfld.long 0x1C 15. " UTMIP_DISABLE_PULLUP_DP ,Force DP pullup inactive" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 14. " UTMIP_DISABLE_PULLUP_DM ,Force DM pullup inactive" "Disabled,Enabled"
|
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bitfld.long 0x1C 13. " UTMIP_DISABLE_PULLDN_DP ,Force DP pulldown inactive" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " UTMIP_DISABLE_PULLDN_DM ,Force DM pulldown inactive" "Disabled,Enabled"
|
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bitfld.long 0x1C 11. " UTMIP_FORCE_PULLUP_DP ,Force DP pullup active" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 10. " UTMIP_FORCE_PULLUP_DM ,Force DM pullup active" "Disabled,Enabled"
|
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bitfld.long 0x1C 9. " UTMIP_FORCE_PULLDN_DP ,Force DP pulldown active" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " UTMIP_FORCE_PULLDN_DM ,Force DM pulldown active" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5.--7. " UTMIP_STABLE_COUNT ,Number of cycles of crystal clock of signal not changing to consider stable" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " UTMIP_STABLE_ALL ,Determines if all signal need to be stable to not change a config" "No,Yes"
|
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bitfld.long 0x1C 3. " UTMIP_NO_FREE_ON_SUSPEND ,Don't use free running terminations during suspend" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 2. " UTMIP_NEVER_FREE_RUNNING_TERMS ,Ignore free running terminations, even when no clock" "Disabled,Enabled"
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bitfld.long 0x1C 1. " UTMIP_ALWAYS_FREE_RUNNING_TERMS ,Use free running terminations at all time" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " UTMIP_COMB_TERMS ,Use combinational terminations or synced through CLKXTAL" "Disabled,Enabled"
|
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line.long 0x20 "USB2_UTMIP_MISC_CFG1_0,UTMIP miscellaneous configurations"
|
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bitfld.long 0x20 30. " UTMIP_PHY_XTAL_CLOCKEN ,Selects whether to enable the crystal clock in the module" "Disabled,Enabled"
|
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bitfld.long 0x20 29. " UTMIP_LINESTATE_BYPASS ,Bypass LineState reclocking logic" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 28. " UTMIP_LINESTATE_NEG ,Use neg edge sync for linestate" "Disabled,Enabled"
|
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bitfld.long 0x20 27. " UTMIP_LINESTATE_XCVRSEL3 ,0 ,Use FS filtering on line state when XcvrSel=3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 25.--26. " UTMIP_OBS_SEL ,UTMIP_OBS_SEL" "0,1,2,3"
|
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bitfld.long 0x20 24. " UTMIP_FSLS_TDM ,UTMIP_FSLS_TDM" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 23. " UTMIP_FORCE_IOBIST_CLK_ON ,UTMIP_FORCE_IOBIST_CLK_ON" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 5. " UTMIP_RX_ERROR_CNT_CLR ,UTMIP_RX_ERROR_CNT_CLR" "0,1"
|
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bitfld.long 0x20 4. " UTMIP_RX_ERROR_CNT_EN ,UTMIP_RX_ERROR_CNT_EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 3. " UTMIP_FLIP_FSLS_POLARITY ,UTMIP_FLIP_FSLS_POLARITY" "0,1"
|
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bitfld.long 0x20 2. " UTMIP_SUSPEND_TERMSEL ,UTMIP_SUSPEND_TERMSEL" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 1. " UTMIP_XCVRSEL3_1 ,EOP detection" "Enabled,Disabled"
|
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bitfld.long 0x20 0. " UTMIP_XCVRSEL3_0 ,UTMIP_XCVRSEL3_0" "KeepAlive,Regular"
|
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line.long 0x24 "USB2_UTMIP_DEBOUNCE_CFG0_0,UTMIP Avalid and Bvalid debounce"
|
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hexmask.long.word 0x24 16.--31. 1. " UTMIP_BIAS_DEBOUNCE_B ,Simulation value -- Used for interrupts"
|
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hexmask.long.word 0x24 0.--15. 1. " UTMIP_BIAS_DEBOUNCE_A ,Simulation value -- Used for interrupts"
|
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line.long 0x28 "USB2_UTMIP_BAT_CHRG_CFG0_0,UTMIP battery charger configuration"
|
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bitfld.long 0x28 8.--13. " UTMIP_CHRG_DEBOUNCE_TIMESCALE ,Debouncer time scaling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
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bitfld.long 0x28 5. " UTMIP_OP_I_SRC_EN ,UTMIP_OP_I_SRC_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 4. " UTMIP_ON_SRC_EN ,UTMIP_ON_SRC_EN" "Disabled,Enabled"
|
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bitfld.long 0x28 3. " UTMIP_OP_SRC_EN ,UTMIP_OP_SRC_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 2. " UTMIP_ON_SINK_EN ,UTMIP_ON_SINK_EN" "Disabled,Enabled"
|
|
bitfld.long 0x28 1. " UTMIP_OP_SINK_EN ,UTMIP_OP_SINK_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 0. " UTMIP_PD_CHRG ,Power down charger circuit" "0,1"
|
|
line.long 0x2C "USB2_UTMIP_SPARE_CFG0_0,Utmip spare configuration bits"
|
|
bitfld.long 0x2C 2. " HS_RX_LATE_SQUELCH ,Delay Squelch by 1 CLK480 cycle" "Disabled,Enabled"
|
|
bitfld.long 0x2C 1. " HS_RX_FLUSH_ALAP ,Flush as late as possible" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 0. " HS_RX_IPG_ERROR_ENABLE ,HS_RX_IPG_ERROR_ENABLE" "Disabled,Enabled"
|
|
line.long 0x30 "USB2_UTMIP_XCVR_CFG1_0,UTMIP transceiver cell configuration register 1"
|
|
bitfld.long 0x30 26.--27. " UTMIP_XCVR_RPU_RANGE_ADJ ,1.5k pull-up resistor range shift" "0,1,2,3"
|
|
bitfld.long 0x30 24.--25. " UTMIP_XCVR_HS_IREF_CAP ,High-speed Iref cap control for bias current stability" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x30 22.--23. " UTMIP_XCVR_SPARE ,Spare bits for USB transceiver pad" "0,1,2,3"
|
|
bitfld.long 0x30 18.--21. " UTMIP_XCVR_TERM_RANGE_ADJ ,Range adjustment on terminations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x30 17. " UTMIP_RCTRL_SW_SET ,Use a software override on RCTRL instead of automatic bias control" "No,Yes"
|
|
bitfld.long 0x30 12.--16. " UTMIP_RCTRL_SW_VAL ,Encoded value to use on RCTRL when software override is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
textline " "
|
|
bitfld.long 0x30 11. " UTMIP_TCTRL_SW_SET ,Use a software override on TCTRL instead of automatic bias control" "No,Yes"
|
|
bitfld.long 0x30 6.--10. " UTMIP_TCTRL_SW_VAL ,Encoded value to use on TCTRL when software override is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
textline " "
|
|
bitfld.long 0x30 5. " UTMIP_FORCE_PDDR_POWERUP ,Force PDDR input into power up" "Not forced,Forced"
|
|
bitfld.long 0x30 4. " UTMIP_FORCE_PDDR_POWERDOWN ,Force PDDR input input into power down" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x30 3. " UTMIP_FORCE_PDCHRP_POWERUP ,Force PDCHRP input into power up" "Not forced,Forced"
|
|
bitfld.long 0x30 2. " UTMIP_FORCE_PDCHRP_POWERDOWN ,Force PDCHRP input input into power down" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x30 1. " UTMIP_FORCE_PDDISC_POWERUP ,Force PDDISC input into power up" "Not forced,Forced"
|
|
bitfld.long 0x30 0. " UTMIP_FORCE_PDDISC_POWERDOWN ,Force PDDISC input into power down" "Not forced,Forced"
|
|
line.long 0x34 "USB2_UTMIP_BIAS_CFG1_0,UTMIP Bias cell configuration register 1"
|
|
bitfld.long 0x34 8.--13. " UTMIP_BIAS_DEBOUNCE_TIMESCALE ,Debouncer time scaling - factor-1 to slow down debouncing by" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
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bitfld.long 0x34 3.--7. " UTMIP_BIAS_PDTRK_COUNT ,Control the BIAS cell power down lag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x34 1. " UTMIP_FORCE_PDTRK_POWERUP ,Force PDTRK input into power up" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " UTMIP_FORCE_PDTRK_POWERDOWN ,Force PDTRK input into power down" "Disabled,Enabled"
|
|
rgroup.long 0x840++0x03
|
|
line.long 0x00 "USB2_UTMIP_BIAS_STS0_0,UTMIP Bias cell status register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " UTMIP_TCTRL ,Thermal encoding output from USB bias pad"
|
|
hexmask.long.word 0x00 0.--15. 1. " UTMIP_RCTRL ,Thermal encoding output from USB bias pad"
|
|
group.long 0x844++0x03
|
|
line.long 0x00 "USB2_UTMIP_CHRG_DEB_CFG0_0,UTMIP VDcd_Det and VDat_Det debounce"
|
|
hexmask.long.word 0x00 16.--31. 1. " UTMIP_CHRG_DEBOUNCE_PERIOD_B ,Simulation value -- Used for interrupts"
|
|
hexmask.long.word 0x00 0.--15. 1. " UTMIP_CHRG_DEBOUNCE_PERIOD_A ,Simulation value -- Used for interrupts"
|
|
rgroup.long 0x848++0x03
|
|
line.long 0x00 "USB2_UTMIP_PMC_WAKEUP0_0,UTMIP PMC Wakeup value"
|
|
bitfld.long 0x00 21. " UTMIP_FS_DRV_EN ,Indicates when the controller is driving on the bus" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. " UTMIP_SPARE_FUSES ,Spare Fuses value, to keep the connections preserved"
|
|
group.long 0x84C++0x03
|
|
line.long 0x00 "USB2_UTMIP_PMC_WAKEUP0_0,UTMIP PMC Wakeup value"
|
|
rbitfld.long 0x00 1. " UTMIP_LINE_WAKEUP_EVENT_INT_STS ,Indicates the status of the pmc wakeup event" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 0. " UTMIP_LINE_WAKEUP_EVENT_INT_ENB ,Interrupt mask for the pmc wakeup event" "Disabled,Enabled"
|
|
tree.end
|
|
width 26.
|
|
tree "UHSIC Configuration"
|
|
rgroup.long 0xc30++0x03
|
|
line.long 0x00 "USB2_UHSIC_MISC_STS0_0,UHSIC SPARE Fuse Value"
|
|
bitfld.long 0x00 0. " UHSIC_TX_HS_VLD ,Indicates when the controller is driving on the bus" "0,1"
|
|
group.long 0xc34++0x03
|
|
line.long 0x00 "USB2_UHSIC_PMC_WAKEUP0_0,UHSIC PMC Wakeup Value"
|
|
rbitfld.long 0x00 1. " UHSIC_LINE_WAKEUP_EVENT_INT_STS ,Indicates the status of the PMC wakeup event" "0,1"
|
|
bitfld.long 0x00 0. " UHSIC_LINE_WAKEUP_EVENT_INT_ENB ,Interrupt mask for the PMC wakeup even" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "USB3 (2.0)"
|
|
base ad:0x7D008000
|
|
tree "USB 3 Controller"
|
|
tree "Status Registers"
|
|
width 35.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_ID_0,USB2D Identification Register"
|
|
bitfld.long 0x00 29.--31. " CIVERSION ,Identifies the CI version" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 25.--28. " VERSION ,Identifies the version of the core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 21.--24. " REVISION ,Revision number of the USB controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. " TAG ,Identifies the tag of the core" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " NID ,Ones complement version of ID"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ID ,Configuration number"
|
|
rgroup.long 0x08++0x0F
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_HW_HOST_0,USB2D Hardware Host Register"
|
|
bitfld.long 0x00 1.--3. " NPORT ,NPORT" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " HC ,Support for host mode" "Disabled,Enabled"
|
|
line.long 0x04 "USB3_CONTROLLER_2_USB2D_HW_DEVICE_0,USB2D Hardware Device Register"
|
|
bitfld.long 0x04 1.--5. " DEVEP ,Number of endpoints supported by this device controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0. " DC ,Support for device mode" "Disabled,Enabled"
|
|
line.long 0x08 "USB3_CONTROLLER_2_USB2D_HW_TXBUF_0,USB2D Hardware TX Buffer Register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " TXCHANADD ,Total number of address bits for the transmit buffer of each transmit endpoint"
|
|
hexmask.long.byte 0x08 8.--15. 1. " TXADD ,Total number of address bits for the transmit buffer"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TCBURST ,Maximum burst size supported by the transmit endpoints for data transfers"
|
|
line.long 0x0C "USB3_CONTROLLER_2_USB2D_HW_RXBUF_0,USB2D RX Buffer HW Parameters Register"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " RXADD ,Total number of address bits for the receive buffer"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " RXBURST ,Maximum burst size supported by the receive endpoints for data transfers"
|
|
textline " "
|
|
width 40.
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "USB3_CONTROLLER_USB_2_USB2D_GPTIMER0LD_0,Timer register 0"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " GPTIMER0LD ,Value loaded into the GPTCNT"
|
|
line.long 0x04 "USB3_CONTROLLER_2_USB2D_GPTIMER0CTRL_0,Timer register controller 0"
|
|
bitfld.long 0x04 31. " GTPRUN ,Enables the general-purpose timer to run" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " GPTRST ,Writing a one to this bit will reload the GPTCNT with the value in GPTL" "No effect,reload"
|
|
bitfld.long 0x04 24. " GPTMODE ,Selects timer mode" "One-shot,Repeat"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,Value of the running timer"
|
|
line.long 0x08 "USB3_CONTROLLER_2_USB2D_GPTIMER1LD_0,Timer register 1"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " GPTIMER1LD ,Value loaded into the GPTCNT"
|
|
line.long 0x0C "USB3_CONTROLLER_2_USB2D_GPTIMER1CTRL_0,Timer register controller 1"
|
|
bitfld.long 0x0C 31. " GTPRUN ,Enables the general-purpose timer to run" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " GPTRST ,Writing a one to this bit will reload the GPTCNT with the value in GPTL" "No effect,reload"
|
|
bitfld.long 0x0C 24. " GPTMODE ,Selects timer mode" "One-shot,Repeat"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,Value of the running timer"
|
|
textline " "
|
|
width 37.
|
|
rgroup.word 0x100++0x03
|
|
line.word 0x00 "USB3_CONTROLLER_2_USB2D_CAPLENGTH_0,USB2D Capability Register Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CAPLENGTH ,Indicates which offset to add to the register base address at the beginning of the operational register"
|
|
line.word 0x02 "USB3_CONTROLLER_2_USB2D_HCIVERSON_0,USB2D Host Interface Version Number Register"
|
|
hexmask.word 0x02 0.--15. 1. " HCIVERSION ,Contains a BCD encoding of the EHCI revision number supported by this host controller"
|
|
rgroup.long 0x104++0x07
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_HCSPARAMS_0,USB2D Host Control Structural Parameters Register"
|
|
bitfld.long 0x00 24.--27. " N_TT ,Number of transaction translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " N_PTT ,Number of ports per transaction translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " N_CC ,Number of companion controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " N_PCC ,Number of ports per companion controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " PPC ,Port power control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " N_PORTS ,Number of downstream ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "USB3_CONTROLLER_2_USB2D_HCCPARAMS_0,USB2D Host Control Capability Parameters Register"
|
|
bitfld.long 0x04 18. " PPC ,Per-port change event capability" "Not supported,Supported"
|
|
bitfld.long 0x04 17. " LEN ,Link power management capability" "Not supported,Supported"
|
|
hexmask.long.byte 0x04 8.--15. 1. " EECP ,EHCI extended capabilities pointer"
|
|
bitfld.long 0x04 4.--7. " IST ,Isochronous scheduling threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 2. " ASP ,Asynchronous schedule park capability" "Not supported,Supported"
|
|
bitfld.long 0x04 1. " PFL ,Programmable frame list flag (frame list length)" "1024 elements,USBCMD_0.FS"
|
|
rgroup.long 0x120++0x07
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_DCIVERSION_0,USB2D Device Interface Version Number Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DCIVERSION ,Interface version number for the two-byte BCD encoding"
|
|
line.long 0x04 "USB3_CONTROLLER_2_USB2D_DCCPARAMS_0,USB2D Device Control Capabilities Register"
|
|
bitfld.long 0x04 8. " HC ,Host capable" "Not capable,Capable"
|
|
bitfld.long 0x04 7. " DC ,Device capable" "Not capable,Capable"
|
|
bitfld.long 0x04 5. " LEN ,Link power management capability" "Not capable,Capable"
|
|
bitfld.long 0x04 0.--4. " DEN ,Device endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
width 37.
|
|
tree "Control Registers"
|
|
if (((d.l(ad:0x7D008000+0x1F8))&0x03)==0x02)
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_EXTSTS_0,USB2D EXTSTS Register"
|
|
eventfld.long 0x00 4. " TI1 ,General purpose timer interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TI0 ,General purpose timer interrupt 0" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 0. " NAKI ,NAK interrupt bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_EXTSTS_0,USB2D EXTSTS Register"
|
|
eventfld.long 0x00 4. " TI1 ,General purpose timer interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TI0 ,General purpose timer interrupt 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " UPA ,USB host periodic interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " UAI ,USB host asynchronous interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 0. " NAKI ,NAK interrupt bit" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_USBEXTINTR_0,USB2D EXTINTR Register"
|
|
bitfld.long 0x00 4. " TIE1 ,General purpose timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TIE0 ,General purpose timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " UPIE ,UPIE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UAIE ,UAIE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NAKE ,NAK interrupt enable" "Disabled,Enabled"
|
|
if (((d.l(ad:0x7D008000+0x108))&0x06)==0x00)&&(((d.l(ad:0x7D008000+0x1F8))&0x03)==0x03)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_USBCMD_0,USB2D USB Command Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control"
|
|
bitfld.long 0x00 14. " ATDTW ,ADD DTD tripwire" "Clear,Set"
|
|
bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Clear,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--9. " ASP1_ASP0 ,Asynchronous schedule park mode count" "0,1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. 15. " FS2_FS0 ,Frame list size (in bytes)" "4096,2048,1024,512,256,128,64,32"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop host/device controller" "Stop,Run"
|
|
elif (((d.l(ad:0x7D008000+0x108))&0x06)==0x02)&&(((d.l(ad:0x7D008000+0x1F8))&0x03)==0x03)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_USBCMD_0,USB2D USB Command Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control"
|
|
bitfld.long 0x00 14. " ATDTW ,ADD DTD tripwire" "Clear,Set"
|
|
bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Clear,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--9. " ASP1_ASP0 ,Asynchronous schedule park mode count" "0,1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. 15. " FS2_FS0 ,Frame list size (in bytes)" "4096,2048,1024,512,256,128,64,32"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop host/device controller" "Stop,Run"
|
|
elif (((d.l(ad:0x7D008000+0x108))&0x06)==0x04)&&(((d.l(ad:0x7D008000+0x1F8))&0x03)==0x03)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_USBCMD_0,USB2D USB Command Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control"
|
|
bitfld.long 0x00 14. " ATDTW ,ADD DTD tripwire" "Clear,Set"
|
|
bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Clear,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ASP1_ASP0 ,Asynchronous schedule park mode count" ",1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. 15. " FS2_FS0 ,Frame list size (in bytes)" "4096,2048,1024,512,256,128,64,32"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop host/device controller" "Stop,Run"
|
|
elif (((d.l(ad:0x7D008000+0x108))&0x06)==0x06)&&(((d.l(ad:0x7D008000+0x1F8))&0x03)==0x03)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_USBCMD_0,USB2D USB Command Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control"
|
|
bitfld.long 0x00 14. " ATDTW ,ADD DTD tripwire" "Clear,Set"
|
|
bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Clear,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ASP1_ASP0 ,Asynchronous schedule park mode count" ",1,2,3"
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. 15. " FS2_FS0 ,Frame list size (in bytes)" "4096,2048,1024,512,256,128,64,32"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop host/device controller" "Stop,Run"
|
|
elif (((d.l(ad:0x7D008000+0x108))&0x04)==0x00)&&(((d.l(ad:0x7D008000+0x1F8))&0x03)!=0x03)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_USBCMD_0,USB2D USB Command Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 14. " ATDTW ,ADD DTD tripwire" "Clear,Set"
|
|
bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Clear,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--9. " ASP1_ASP0 ,Asynchronous schedule park mode count" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. 15. " FS2_FS0 ,Frame list size (in bytes)" "4096,2048,1024,512,256,128,64,32"
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop host/device controller" "Stop,Run"
|
|
elif (((d.l(ad:0x7D008000+0x108))&0x04)==0x04)&&(((d.l(ad:0x7D008000+0x1F8))&0x03)!=0x03)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_USBCMD_0,USB2D USB Command Register"
|
|
bitfld.long 0x00 24.--27. " HIRD ,Host initiated resume duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control"
|
|
bitfld.long 0x00 14. " ATDTW ,ADD DTD tripwire" "Clear,Set"
|
|
bitfld.long 0x00 13. " SUTW ,Setup tripwire" "Clear,Set"
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ASP1_ASP0 ,Asynchronous schedule park mode count" ",1,2,3"
|
|
bitfld.long 0x00 2.--3. 15. " FS2_FS0 ,Frame list size (in bytes)" "4096,2048,1024,512,256,128,64,32"
|
|
bitfld.long 0x00 1. " RST ,Controller reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop host/device controller" "Stop,Run"
|
|
endif
|
|
if (((d.l(ad:0x7D008000+0x1F8))&0x03)==0x03)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_USBSTS_0,USB2D USB Status Register"
|
|
bitfld.long 0x00 31. " PPCI16 ,Port 16 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " PPCI15 ,Port 15 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 29. " PPCI14 ,Port 14 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " PPCI13 ,Port 13 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 27. " PPCI12 ,Port 12 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPCI11 ,Port 11 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 25. " PPCI10 ,Port 10 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " PPCI9 ,Port 9 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 23. " PPCI8 ,Port 8 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " PPCI7 ,Port 7 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCI6 ,Port 6 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " PPCI5 ,Port 5 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 19. " PPCI4 ,Port 4 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " PPCI3 ,Port 3 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 17. " PPCI2 ,Port 2 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PPCI1 ,Port 1 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 15. " AS ,Asynchronous schedule status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PS ,Periodic schedule status" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " RCL ,Empty asynchronous schedule detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " HCH ,HCHalted" "Unhalted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " UALT_INT ,ULPI alt_int Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ULPI_INT ,ULPI interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " SRI ,SOF received" "Not received,Received"
|
|
bitfld.long 0x00 5. " AAI ,Interrupt and asynchronous advance" "Not advanced,Advanced"
|
|
rbitfld.long 0x00 4. " SEI ,System error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRI ,Frame list rollover" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCI ,Port change detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB error interrupt" "No error,Error"
|
|
bitfld.long 0x00 0. " UI ,USB interrupt" "No interrupt,Interrupt"
|
|
elif (((d.l(ad:0x7D008000+0x1F8))&0x03)==0x02)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_USBSTS_0,USB2D USB Status Register"
|
|
bitfld.long 0x00 31. " PPCI16 ,Port 16 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " PPCI15 ,Port 15 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 29. " PPCI14 ,Port 14 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " PPCI13 ,Port 13 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 27. " PPCI12 ,Port 12 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPCI11 ,Port 11 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 25. " PPCI10 ,Port 10 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " PPCI9 ,Port 9 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 23. " PPCI8 ,Port 8 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " PPCI7 ,Port 7 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCI6 ,Port 6 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " PPCI5 ,Port 5 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 19. " PPCI4 ,Port 4 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " PPCI3 ,Port 3 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 17. " PPCI2 ,Port 2 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PPCI1 ,Port 1 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 11. " UALT_INT ,ULPI alt_int Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ULPI_INT ,ULPI interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SLI ,DCSuspend" "Not suspended,Suspended"
|
|
eventfld.long 0x00 7. " SRI ,SOF received" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 6. " URI ,USB reset received" "No reset,Reset"
|
|
rbitfld.long 0x00 4. " SEI ,System error" "No error,Error"
|
|
bitfld.long 0x00 2. " PCI ,Port change detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB error interrupt" "No error,Error"
|
|
bitfld.long 0x00 0. " UI ,USB interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_USBSTS_0,USB2D USB Status Register"
|
|
bitfld.long 0x00 31. " PPCI16 ,Port 16 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " PPCI15 ,Port 15 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 29. " PPCI14 ,Port 14 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " PPCI13 ,Port 13 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 27. " PPCI12 ,Port 12 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPCI11 ,Port 11 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 25. " PPCI10 ,Port 10 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " PPCI9 ,Port 9 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 23. " PPCI8 ,Port 8 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " PPCI7 ,Port 7 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCI6 ,Port 6 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " PPCI5 ,Port 5 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 19. " PPCI4 ,Port 4 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " PPCI3 ,Port 3 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 17. " PPCI2 ,Port 2 change detect status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PPCI1 ,Port 1 change detect status" "Not detected,Detected"
|
|
bitfld.long 0x00 11. " UALT_INT ,ULPI alt_int Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " ULPI_INT ,ULPI interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " SRI ,SOF received" "Not received,Received"
|
|
rbitfld.long 0x00 4. " SEI ,System error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCI ,Port change detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB error interrupt" "No error,Error"
|
|
bitfld.long 0x00 0. " UI ,USB interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
if (((d.l(ad:0x7D008000+0x1F8))&0x03)==0x03)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_USBINTR_0,USB2D USB Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " PPCE16 ,Port 16 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PPCE15 ,Port 15 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PPCE14 ,Port 14 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PPCE13 ,Port 13 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PPCE12 ,Port 12 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPCE11 ,Port 11 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PPCE10 ,Port 10 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PPCE9 ,Port 9 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PPCE8 ,Port 8 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PPCE7 ,Port 7 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCE6 ,Port 6 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PPCE5 ,Port 5 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PPCE4 ,Port 4 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PPCE3 ,Port 3 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PPCE2 ,Port 2 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PPCE1 ,Port 1 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " UALTIE ,LPI alt_int Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ULPIE ,ULPI interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " SRE ,SOF received" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AAE ,Interrupt on asynchronous advance" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEE ,System error" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRE ,Frame list rollover" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCE ,Port change detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UEE ,USB error interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USB interrupt" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x7D008000+0x1F8))&0x03)==0x02)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_USBINTR_0,USB2D USB Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " PPCE16 ,Port 16 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PPCE15 ,Port 15 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PPCE14 ,Port 14 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PPCE13 ,Port 13 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PPCE12 ,Port 12 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPCE11 ,Port 11 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PPCE10 ,Port 10 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PPCE9 ,Port 9 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PPCE8 ,Port 8 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PPCE7 ,Port 7 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCE6 ,Port 6 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PPCE5 ,Port 5 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PPCE4 ,Port 4 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PPCE3 ,Port 3 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PPCE2 ,Port 2 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PPCE1 ,Port 1 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " UALTIE ,LPI alt_int Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ULPIE ,ULPI interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLE ,Sleep enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " SRE ,SOF received" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 6. " URE ,USB reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SEE ,System error" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCE ,Port change detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UEE ,USB error interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USB interrupt" "Disabled,Enabled"
|
|
else
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_USBINTR_0,USB2D USB Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " PPCE16 ,Port 16 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PPCE15 ,Port 15 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PPCE14 ,Port 14 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PPCE13 ,Port 13 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PPCE12 ,Port 12 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PPCE11 ,Port 11 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PPCE10 ,Port 10 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PPCE9 ,Port 9 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PPCE8 ,Port 8 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PPCE7 ,Port 7 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PPCE6 ,Port 6 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PPCE5 ,Port 5 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PPCE4 ,Port 4 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PPCE3 ,Port 3 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PPCE2 ,Port 2 change detect enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PPCE1 ,Port 1 change detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " UALTIE ,LPI alt_int Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ULPIE ,ULPI interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " SRE ,SOF received" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SEE ,System error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PCE ,Port change detect" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UEE ,USB error interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USB interrupt" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_FRINDEX_0,USB2D USB Frame Index Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame index"
|
|
textline " "
|
|
width 44.
|
|
if (((d.l(ad:0x7D008000+0x1F8))&0x03)==0x02)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_PERIODICLISTBASE_0,USB2D Host Controller Frame List Base Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 0x2 " USBADR ,Device address"
|
|
bitfld.long 0x00 24. " USBADRA ,Device address advance" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x7D008000+0x1F8))&0x03)==0x03)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_PERIODICLISTBASE_0,USB2D Host Controller Frame List Base Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Beginning address of the periodic frame list in the system memory"
|
|
else
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "USB3_CONTROLLER_2_USB2D_PERIODICLISTBASE_0,USB2D Host Controller Frame List Base Address Register"
|
|
endif
|
|
if (((d.l(ad:0x7D008000+0x1F8))&0x03)==0x02)
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_ASYNCLISTADDR_0,USB2D Next Asynchronous List Address Register"
|
|
hexmask.long.tbyte 0x00 11.--31. 0x08 " EPBASE ,Address of the top of the endpoint list in system memory"
|
|
elif (((d.l(ad:0x7D008000+0x1F8))&0x03)==0x03)
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_ASYNCLISTADDR_0,USB2D Next Asynchronous List Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " ASYBASE ,Address of the next asynchronous queue head to be executed by the host"
|
|
else
|
|
hgroup.long 0x148++0x03
|
|
hide.long 0x00 "USB3_CONTROLLER_2_USB2D_ASYNCLISTADDR_0,USB2D Next Asynchronous List Address Register"
|
|
endif
|
|
group.long 0x14C++0x0B
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_ASYNCTTSTS_0,USB2D Asynchronous Buffer Status for Embedded TT Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " TTHA ,Internal TT Hub Address representation"
|
|
bitfld.long 0x00 1. " TTAC ,Embedded TT async buffers clear" "No clear,Clear"
|
|
rbitfld.long 0x00 0. " TTAS ,Embedded TT async buffers status" "Empty,Not empty"
|
|
line.long 0x04 "USB3_CONTROLLER_2_USB2D_BURSTSIZE_0,USB2D Burst Size register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TXPBURST ,Programmable TX burst length"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RXPBURST ,Programmable RX burst length"
|
|
line.long 0x08 "USB3_CONTROLLER_2_USB2D_TXFILLTUNING_0,USB2D Transmit fill tuning register"
|
|
bitfld.long 0x08 16.--21. " TXFIFOTHRES ,FIFO burst threshold" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 8.--12. " TXSCHHEALTH ,Scheduler health counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TXSCHOH ,Scheduler overhead"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_ICUSB_CTRL_0,USB2D ICUSB control register"
|
|
bitfld.long 0x00 3. " IC_ENB1 ,ICUSB transceiver" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " IC_VDD1 ,ICUSB voltage select" "No voltage,,,,1.8V,3.0V,?..."
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0,USB2D ULPI viewport register"
|
|
bitfld.long 0x00 31. " ULPI_WAKEUP ,ULPI wakeup" "No effect,Wakeup"
|
|
bitfld.long 0x00 30. " ULPI_RUN ,ULPI read/write run (begin read/write operation)" "No effect,Run"
|
|
bitfld.long 0x00 29. " ULPI_RD_WR ,ULPI read/write control" "Read,Write"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " ULPI_SYNC_STATE ,ULPI sync state" "Normal,Not normal"
|
|
bitfld.long 0x00 24.--26. " ULPI_PORT ,ULPI PHY port number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ULPI_REG_ADDR ,ULPI PHY register address"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " ULPI_DATA_RD ,ULPI PHY data read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ULPI_DATA_WR ,ULPI PHY data write"
|
|
textline ""
|
|
width 41.
|
|
if (((d.l(ad:0x7D008000+0x1F8))&0x03)==0x03)
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_PORTSC1_0,USB2D Port Status/Control 1 Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " DA ,Device address"
|
|
rbitfld.long 0x00 23.--24. " SSTS ,Suspend status" "L1STATE_ENTERED,NYET_PERIPH,L1STATE_NOT_SUPPORTED,PERIPH_NORESP_ERR"
|
|
bitfld.long 0x00 22. " WKOC ,Wake on over-current" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKDS ,Wake on disconnect" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " WKCN ,Wake on connect" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port test control" "NORMAL_OP,TEST_J,TEST_K,TEST_SE0_NAK,TEST_PKT,TEST_FORCE_ENABLE,?..."
|
|
textline " "
|
|
eventfld.long 0x00 12. " PP ,Port power" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10.--11. " LS ,Line state" "SE0,J_STATE,K_STATE,Undefined"
|
|
bitfld.long 0x00 9. " SLP ,Suspend using L1" "L2,L1"
|
|
bitfld.long 0x00 8. " PR ,Port reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SUSP ,Port suspend" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FPR ,Force port resume" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEC ,Port enable/disable change" "No change,Change"
|
|
eventfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSC ,Connect status change" "No change,Change"
|
|
rbitfld.long 0x00 0. " CCS ,Current connect status" "Not connected,Connected"
|
|
elif (((d.l(ad:0x7D008000+0x1F8))&0x03)==0x02)
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_PORTSC1_0,USB2D Port Status/Control 1 Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " DA ,Device address"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port test control" "NORMAL_OP,TEST_J,TEST_K,TEST_SE0_NAK,TEST_PKT,TEST_FORCE_ENABLE,?..."
|
|
rbitfld.long 0x00 14.--15. " PIC ,Port indicator control" "0,1,2,3"
|
|
rbitfld.long 0x00 13. " PO ,Port owner" "0,1"
|
|
eventfld.long 0x00 12. " PP ,Port power" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10.--11. " LS ,Line state" "SE0,J_STATE,K_STATE,Undefined"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SLP ,Suspend using L1" "L2,L1"
|
|
rbitfld.long 0x00 8. " PR ,Port reset" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " SUSP ,Port suspend" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FPR ,Force port resume" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " OCC ,Over-current change" "No change,Change"
|
|
rbitfld.long 0x00 4. " OCA ,Over-current active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEC ,Port enable/disable change" "No change,Change"
|
|
eventfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,Current connect status" "Not connected,Connected"
|
|
else
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_PORTSC1_0,USB2D Port Status/Control 1 Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " DA ,Device address"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port test control" "NORMAL_OP,TEST_J,TEST_K,TEST_SE0_NAK,TEST_PKT,TEST_FORCE_ENABLE,?..."
|
|
rbitfld.long 0x00 14.--15. " PIC ,Port indicator control" "0,1,2,3"
|
|
rbitfld.long 0x00 13. " PO ,Port owner" "0,1"
|
|
eventfld.long 0x00 12. " PP ,Port power" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10.--11. " LS ,Line state" "SE0,J_STATE,K_STATE,Undefined"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SLP ,Suspend using L1" "L2,L1"
|
|
rbitfld.long 0x00 8. " PR ,Port reset" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " SUSP ,Port suspend" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FPR ,Force port resume" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " OCC ,Over-current change" "No change,Change"
|
|
rbitfld.long 0x00 4. " OCA ,Over-current active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEC ,Port enable/disable change" "No change,Change"
|
|
eventfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,Current connect status" "Not connected,Connected"
|
|
endif
|
|
textline ""
|
|
if (((d.l(ad:0x7D008000+0x1F8))&0x03)==0x03)
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_HOSTPC1_DEVLC_0,USB2D Host Mode LPM Behav and Control Register"
|
|
bitfld.long 0x00 29.--31. " PTS ,Parallel transceiver select" "UTMI,,ULPI,ICUSB_SER,HSIC,?..."
|
|
bitfld.long 0x00 28. " STS ,Serial transceiver" "PARALLEL_IF,SERIAL_IF"
|
|
rbitfld.long 0x00 27. " PTW ,Parallel transceiver width" "8-bit,?..."
|
|
rbitfld.long 0x00 25.--26. " PSPD ,Port operating speed" "Full,Low,High,?..."
|
|
bitfld.long 0x00 24. " ALPD ,Auto Low Power While Disconnect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PFSC ,Port force full speed connect" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PHCD ,PHY low power suspend - clock disable" "No,Yes"
|
|
bitfld.long 0x00 20.--21. " LPMX ,Auto LPM set" "Disabled,Set,Set without interrupt,?..."
|
|
bitfld.long 0x00 16.--19. " EPLPM ,Endpoint for LPM token" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " LPMFRM ,Auto LPM SOF threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 1.--11. 1. " BA ,BmAttrubuttes"
|
|
bitfld.long 0x00 0. " ASUS ,Auto low power" "Disabled,Enabled"
|
|
elif (((d.l(ad:0x7D008000+0x1F8))&0x03)==0x02)
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_HOSTPC1_DEVLC_0,USB2D Device Mode LPM Behav and Control Register"
|
|
bitfld.long 0x00 29.--31. " PTS ,Parallel transceiver select" "UTMI,,ULPI,ICUSB_SER,HSIC,?..."
|
|
bitfld.long 0x00 28. " STS ,Serial transceiver" "PARALLEL_IF,SERIAL_IF"
|
|
rbitfld.long 0x00 27. " PTW ,Parallel transceiver width" "8-bit,?..."
|
|
rbitfld.long 0x00 25.--26. " PSPD ,Port operating speed" "Full,Low,High,?..."
|
|
bitfld.long 0x00 24. " ALPD ,Auto Low Power While Disconnect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PFSC ,Port force full speed connect" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PHCD ,PHY low power suspend - clock disable" "No,Yes"
|
|
bitfld.long 0x00 17. " ASUS ,Auto low power" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " STL ,STALL reply to LPM token" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 1.--11. 1. " BA ,BmAttrubuttes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NYT ,NYTE reply to LPM token" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_HOSTPC1_DEVLC_0,USB2D Device Mode LPM Behav and Control Register"
|
|
bitfld.long 0x00 29.--31. " PTS ,Parallel transceiver select" "UTMI,,ULPI,ICUSB_SER,HSIC,?..."
|
|
bitfld.long 0x00 28. " STS ,Serial transceiver" "PARALLEL_IF,SERIAL_IF"
|
|
rbitfld.long 0x00 27. " PTW ,Parallel transceiver width" "8-bit,?..."
|
|
rbitfld.long 0x00 25.--26. " PSPD ,Port operating speed" "Full,Low,High,?..."
|
|
bitfld.long 0x00 24. " ALPD ,Auto Low Power While Disconnect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PFSC ,Port force full speed connect" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PHCD ,PHY low power suspend - clock disable" "No,Yes"
|
|
hexmask.long.word 0x00 1.--11. 1. " BA ,BmAttrubuttes"
|
|
endif
|
|
textline ""
|
|
width 32.
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_OTGSC_0,USB2D On-The-Go (OTG) Status and Control Register"
|
|
bitfld.long 0x00 30. " DPIE ,Data pulse interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONEMSE ,1 millisecond timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " BSEIE ,B session end interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " BSVIE ,B session valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ASVIE ,A session valid interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " AVVIE ,A VBUS valid interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " IDIE ,USB ID interrupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 22. " DPIS ,Data pulse interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " ONEMESS ,1 millisecond timer interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " BSEIS ,B session end interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " BSVIS ,B session valid interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ASVIS ,A session valid interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " AVVIS ,A VBUS valid interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IDIS ,USB ID interrupt toggle" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 14. " DPS ,Data pulse status" "Not detected,Detected"
|
|
rbitfld.long 0x00 13. " ONEMST ,1 millisecond timer toggle" "Low,High"
|
|
rbitfld.long 0x00 12. " BSE ,B session end threshold" "No,Yes"
|
|
rbitfld.long 0x00 11. " BSV ,B session valid threshold" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " ASV ,A session valid threshold" "No,Yes"
|
|
rbitfld.long 0x00 9. " AVV ,A VBUS valid threshold" "No,Yes"
|
|
rbitfld.long 0x00 8. " ID ,USB ID" "A-device,B-device"
|
|
bitfld.long 0x00 5. " IDPU ,USB ID pullup" "Clear,Set"
|
|
bitfld.long 0x00 4. " DP ,Data pulsing" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " OT ,OTG termination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " VC ,VBUS charge" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VD ,VBUS discharge" "Disabled,Enabled"
|
|
tree.end
|
|
width 35.
|
|
if (((d.l(ad:0x7D008000+0x1F8))&0x03)==0x03)
|
|
group.long 0x1F8++0x03 "Device Mode Control"
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_USBMODE_0,USB2D USB Device Mode Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ALPDD ,Auto Low Power While Disconnect"
|
|
bitfld.long 0x00 15. " SRT ,Shorten USB reset time" "No,Yes"
|
|
rbitfld.long 0x00 4. " SDIS ,Stream disable" "No,Yes"
|
|
rbitfld.long 0x00 2. " ES ,Endian select" "Little endian,?..."
|
|
rbitfld.long 0x00 0.--1. " CM ,Controller mode" "Idle,,Device mode,Host mode"
|
|
elif (((d.l(ad:0x7D008000+0x1F8))&0x03)!=0x03)
|
|
group.long 0x1F8++0x03 "Device Mode Control"
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_USBMODE_0,USB2D USB Device Mode Register"
|
|
bitfld.long 0x00 15. " SRT ,Shorten USB reset time" "No,Yes"
|
|
rbitfld.long 0x00 4. " SDIS ,Stream disable" "No,Yes"
|
|
rbitfld.long 0x00 3. " SLOM ,Setup lockout mode" "On,Off"
|
|
rbitfld.long 0x00 2. " ES ,Endian select" "Little endian,?..."
|
|
rbitfld.long 0x00 0.--1. " CM ,Controller mode" "Idle,,Device mode,Host mode"
|
|
endif
|
|
width 42.
|
|
tree "Endpoint Setup"
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_ENDPTNAK_0,USB2D Endpoint NAK register"
|
|
bitfld.long 0x00 31. " EPTN15 ,TX endpoint NAK 15" "Clear,Set"
|
|
bitfld.long 0x00 30. " EPTN14 ,TX endpoint NAK 14" "Clear,Set"
|
|
bitfld.long 0x00 29. " EPTN13 ,TX endpoint NAK 13" "Clear,Set"
|
|
bitfld.long 0x00 28. " EPTN12 ,TX endpoint NAK 12" "Clear,Set"
|
|
bitfld.long 0x00 27. " EPTN11 ,TX endpoint NAK 11" "Clear,Set"
|
|
bitfld.long 0x00 26. " EPTN10 ,TX endpoint NAK 10" "Clear,Set"
|
|
bitfld.long 0x00 25. " EPTN9 ,TX endpoint NAK 9" "Clear,Set"
|
|
bitfld.long 0x00 24. " EPTN8 ,TX endpoint NAK 8" "Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EPTN7 ,TX endpoint NAK 7" "Clear,Set"
|
|
bitfld.long 0x00 22. " EPTN6 ,TX endpoint NAK 6" "Clear,Set"
|
|
bitfld.long 0x00 21. " EPTN5 ,TX endpoint NAK 5" "Clear,Set"
|
|
bitfld.long 0x00 20. " EPTN4 ,TX endpoint NAK 4" "Clear,Set"
|
|
bitfld.long 0x00 19. " EPTN3 ,TX endpoint NAK 3" "Clear,Set"
|
|
bitfld.long 0x00 18. " EPTN2 ,TX endpoint NAK 2" "Clear,Set"
|
|
bitfld.long 0x00 17. " EPTN1 ,TX endpoint NAK 1" "Clear,Set"
|
|
bitfld.long 0x00 16. " EPTN0 ,TX endpoint NAK 0" "Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EPRN15 ,RX endpoint NAK 15" "Clear,Set"
|
|
bitfld.long 0x00 14. " EPRN14 ,RX endpoint NAK 14" "Clear,Set"
|
|
bitfld.long 0x00 13. " EPRN13 ,RX endpoint NAK 13" "Clear,Set"
|
|
bitfld.long 0x00 12. " EPRN12 ,RX endpoint NAK 12" "Clear,Set"
|
|
bitfld.long 0x00 11. " EPRN11 ,RX endpoint NAK 11" "Clear,Set"
|
|
bitfld.long 0x00 10. " EPRN10 ,RX endpoint NAK 10" "Clear,Set"
|
|
bitfld.long 0x00 9. " EPRN9 ,RX endpoint NAK 9" "Clear,Set"
|
|
bitfld.long 0x00 8. " EPRN8 ,RX endpoint NAK 8" "Clear,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EPRN7 ,RX endpoint NAK 7" "Clear,Set"
|
|
bitfld.long 0x00 6. " EPRN6 ,RX endpoint NAK 6" "Clear,Set"
|
|
bitfld.long 0x00 5. " EPRN5 ,RX endpoint NAK 5" "Clear,Set"
|
|
bitfld.long 0x00 4. " EPRN4 ,RX endpoint NAK 4" "Clear,Set"
|
|
bitfld.long 0x00 3. " EPRN3 ,RX endpoint NAK 3" "Clear,Set"
|
|
bitfld.long 0x00 2. " EPRN2 ,RX endpoint NAK 2" "Clear,Set"
|
|
bitfld.long 0x00 1. " EPRN1 ,RX endpoint NAK 1" "Clear,Set"
|
|
bitfld.long 0x00 0. " EPRN0 ,RX endpoint NAK 0" "Clear,Set"
|
|
textline ""
|
|
line.long 0x04 "USB3_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0,USB2D Endpoint NAK Enable register"
|
|
bitfld.long 0x04 31. " EPTN15 ,TX endpoint NAK enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " EPTN14 ,TX endpoint NAK enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " EPTN13 ,TX endpoint NAK enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " EPTN12 ,TX endpoint NAK enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " EPTN11 ,TX endpoint NAK enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " EPTN10 ,TX endpoint NAK enable 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " EPTN9 ,TX endpoint NAK enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " EPTN8 ,TX endpoint NAK enable 8" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " EPTN7 ,TX endpoint NAK enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " EPTN6 ,TX endpoint NAK enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " EPTN5 ,TX endpoint NAK enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " EPTN4 ,TX endpoint NAK enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " EPTN3 ,TX endpoint NAK enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " EPTN2 ,TX endpoint NAK enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " EPTN1 ,TX endpoint NAK enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " EPTN0 ,TX endpoint NAK enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " EPRN15 ,RX endpoint NAK enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " EPRN14 ,RX endpoint NAK enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " EPRN13 ,RX endpoint NAK enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " EPRN12 ,RX endpoint NAK enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " EPRN11 ,RX endpoint NAK enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " EPRN10 ,RX endpoint NAK enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " EPRN9 ,RX endpoint NAK enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EPRN8 ,RX endpoint NAK enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " EPRN7 ,RX endpoint NAK enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " EPRN6 ,RX endpoint NAK enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " EPRN5 ,RX endpoint NAK enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " EPRN4 ,RX endpoint NAK enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " EPRN3 ,RX endpoint NAK enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " EPRN2 ,RX endpoint NAK enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " EPRN1 ,RX endpoint NAK enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EPRN0 ,RX endpoint NAK enable 0" "Disabled,Enabled"
|
|
width 43.
|
|
if (((d.l(ad:0x7D008000+0x1F8))&0x03)==0x02)
|
|
group.long 0x208++0x0B
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0,USB2D Endpoint Setup Status Register"
|
|
bitfld.long 0x00 15. " ENDPTSETUPSTAT15 ,Endpoint setup status 15" "Not received,Received"
|
|
bitfld.long 0x00 14. " ENDPTSETUPSTAT14 ,Endpoint setup status 14" "Not received,Received"
|
|
bitfld.long 0x00 13. " ENDPTSETUPSTAT13 ,Endpoint setup status 13" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ENDPTSETUPSTAT12 ,Endpoint setup status 12" "Not received,Received"
|
|
bitfld.long 0x00 11. " ENDPTSETUPSTAT11 ,Endpoint setup status 11" "Not received,Received"
|
|
bitfld.long 0x00 10. " ENDPTSETUPSTAT10 ,Endpoint setup status 10" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ENDPTSETUPSTAT9 ,Endpoint setup status 9" "Not received,Received"
|
|
bitfld.long 0x00 8. " ENDPTSETUPSTAT8 ,Endpoint setup status 8" "Not received,Received"
|
|
bitfld.long 0x00 7. " ENDPTSETUPSTAT7 ,Endpoint setup status 7" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENDPTSETUPSTAT6 ,Endpoint setup status 6" "Not received,Received"
|
|
bitfld.long 0x00 5. " ENDPTSETUPSTAT5 ,Endpoint setup status 5" "Not received,Received"
|
|
bitfld.long 0x00 4. " ENDPTSETUPSTAT4 ,Endpoint setup status 4" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENDPTSETUPSTAT3 ,Endpoint setup status 3" "Not received,Received"
|
|
bitfld.long 0x00 2. " ENDPTSETUPSTAT2 ,Endpoint setup status 2" "Not received,Received"
|
|
bitfld.long 0x00 1. " ENDPTSETUPSTAT1 ,Endpoint setup status 1" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENDPTSETUPSTAT0 ,Endpoint setup status 0" "Not received,Received"
|
|
line.long 0x04 "USB3_CONTROLLER_2_USB2D_ENDPTPRIME_0,USB2D Endpoint Initialization Register"
|
|
bitfld.long 0x04 31. " PETB15 ,Prime endpoint transmit buffer 15" "Don't prime,Prime"
|
|
bitfld.long 0x04 30. " PETB14 ,Prime endpoint transmit buffer 14" "Don't prime,Prime"
|
|
bitfld.long 0x04 29. " PETB13 ,Prime endpoint transmit buffer 13" "Don't prime,Prime"
|
|
bitfld.long 0x04 28. " PETB12 ,Prime endpoint transmit buffer 12" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 27. " PETB11 ,Prime endpoint transmit buffer 11" "Don't prime,Prime"
|
|
bitfld.long 0x04 26. " PETB10 ,Prime endpoint transmit buffer 10" "Don't prime,Prime"
|
|
bitfld.long 0x04 25. " PETB9 ,Prime endpoint transmit buffer 9" "Don't prime,Prime"
|
|
bitfld.long 0x04 24. " PETB8 ,Prime endpoint transmit buffer 8" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 23. " PETB7 ,Prime endpoint transmit buffer 7" "Don't prime,Prime"
|
|
bitfld.long 0x04 22. " PETB6 ,Prime endpoint transmit buffer 6" "Don't prime,Prime"
|
|
bitfld.long 0x04 21. " PETB5 ,Prime endpoint transmit buffer 5" "Don't prime,Prime"
|
|
bitfld.long 0x04 20. " PETB4 ,Prime endpoint transmit buffer 4" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PETB3 ,Prime endpoint transmit buffer 3" "Don't prime,Prime"
|
|
bitfld.long 0x04 18. " PETB2 ,Prime endpoint transmit buffer 2" "Don't prime,Prime"
|
|
bitfld.long 0x04 17. " PETB1 ,Prime endpoint transmit buffer 1" "Don't prime,Prime"
|
|
bitfld.long 0x04 16. " PETB0 ,Prime endpoint transmit buffer 0" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 15. " PERB15 ,Prime endpoint receive buffer 15" "Don't prime,Prime"
|
|
bitfld.long 0x04 14. " PERB14 ,Prime endpoint receive buffer 14" "Don't prime,Prime"
|
|
bitfld.long 0x04 13. " PERB13 ,Prime endpoint receive buffer 13" "Don't prime,Prime"
|
|
bitfld.long 0x04 12. " PERB12 ,Prime endpoint receive buffer 12" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 11. " PERB11 ,Prime endpoint receive buffer 11" "Don't prime,Prime"
|
|
bitfld.long 0x04 10. " PERB10 ,Prime endpoint receive buffer 10" "Don't prime,Prime"
|
|
bitfld.long 0x04 9. " PERB9 ,Prime endpoint receive buffer 9" "Don't prime,Prime"
|
|
bitfld.long 0x04 8. " PERB8 ,Prime endpoint receive buffer 8" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 7. " PERB7 ,Prime endpoint receive buffer 7" "Don't prime,Prime"
|
|
bitfld.long 0x04 6. " PERB6 ,Prime endpoint receive buffer 6" "Don't prime,Prime"
|
|
bitfld.long 0x04 5. " PERB5 ,Prime endpoint receive buffer 5" "Don't prime,Prime"
|
|
bitfld.long 0x04 4. " PERB4 ,Prime endpoint receive buffer 4" "Don't prime,Prime"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PERB3 ,Prime endpoint receive buffer 3" "Don't prime,Prime"
|
|
bitfld.long 0x04 2. " PERB2 ,Prime endpoint receive buffer 2" "Don't prime,Prime"
|
|
bitfld.long 0x04 1. " PERB1 ,Prime endpoint receive buffer 1" "Don't prime,Prime"
|
|
bitfld.long 0x04 0. " PERB0 ,Prime endpoint receive buffer 0" "Don't prime,Prime"
|
|
line.long 0x08 "USB3_CONTROLLER_2_USB2D_ENDPTFLUSH_0,USB2D Endpoint De-Initialization Register"
|
|
bitfld.long 0x08 31. " FETB15 ,Flush endpoint transmit buffer 15" "Don't flush,Flush"
|
|
bitfld.long 0x08 30. " FETB14 ,Flush endpoint transmit buffer 14" "Don't flush,Flush"
|
|
bitfld.long 0x08 29. " FETB13 ,Flush endpoint transmit buffer 13" "Don't flush,Flush"
|
|
bitfld.long 0x08 28. " FETB12 ,Flush endpoint transmit buffer 12" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 27. " FETB11 ,Flush endpoint transmit buffer 11" "Don't flush,Flush"
|
|
bitfld.long 0x08 26. " FETB10 ,Flush endpoint transmit buffer 10" "Don't flush,Flush"
|
|
bitfld.long 0x08 25. " FETB9 ,Flush endpoint transmit buffer 9" "Don't flush,Flush"
|
|
bitfld.long 0x08 24. " FETB8 ,Flush endpoint transmit buffer 8" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 23. " FETB7 ,Flush endpoint transmit buffer 7" "Don't flush,Flush"
|
|
bitfld.long 0x08 22. " FETB6 ,Flush endpoint transmit buffer 6" "Don't flush,Flush"
|
|
bitfld.long 0x08 21. " FETB5 ,Flush endpoint transmit buffer 5" "Don't flush,Flush"
|
|
bitfld.long 0x08 20. " FETB4 ,Flush endpoint transmit buffer 4" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 19. " FETB3 ,Flush endpoint transmit buffer 3" "Don't flush,Flush"
|
|
bitfld.long 0x08 18. " FETB2 ,Flush endpoint transmit buffer 2" "Don't flush,Flush"
|
|
bitfld.long 0x08 17. " FETB1 ,Flush endpoint transmit buffer 1" "Don't flush,Flush"
|
|
bitfld.long 0x08 16. " FETB0 ,Flush endpoint transmit buffer 0" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 15. " FERB15 ,Flush endpoint receive buffer 15" "Don't flush,Flush"
|
|
bitfld.long 0x08 14. " FERB14 ,Flush endpoint receive buffer 14" "Don't flush,Flush"
|
|
bitfld.long 0x08 13. " FERB13 ,Flush endpoint receive buffer 13" "Don't flush,Flush"
|
|
bitfld.long 0x08 12. " FERB12 ,Flush endpoint receive buffer 12" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 11. " FERB11 ,Flush endpoint receive buffer 11" "Don't flush,Flush"
|
|
bitfld.long 0x08 10. " FERB10 ,Flush endpoint receive buffer 10" "Don't flush,Flush"
|
|
bitfld.long 0x08 9. " FERB9 ,Flush endpoint receive buffer 9" "Don't flush,Flush"
|
|
bitfld.long 0x08 8. " FERB8 ,Flush endpoint receive buffer 8" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 7. " FERB7 ,Flush endpoint receive buffer 7" "Don't flush,Flush"
|
|
bitfld.long 0x08 6. " FERB6 ,Flush endpoint receive buffer 6" "Don't flush,Flush"
|
|
bitfld.long 0x08 5. " FERB5 ,Flush endpoint receive buffer 5" "Don't flush,Flush"
|
|
bitfld.long 0x08 4. " FERB4 ,Flush endpoint receive buffer 4" "Don't flush,Flush"
|
|
textline " "
|
|
bitfld.long 0x08 3. " FERB3 ,Flush endpoint receive buffer 3" "Don't flush,Flush"
|
|
bitfld.long 0x08 2. " FERB2 ,Flush endpoint receive buffer 2" "Don't flush,Flush"
|
|
bitfld.long 0x08 1. " FERB1 ,Flush endpoint receive buffer 1" "Don't flush,Flush"
|
|
bitfld.long 0x08 0. " FERB0 ,Flush endpoint receive buffer 0" "Don't flush,Flush"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_ENDPTSTATUS_0,USB2D Endpoint Status Register"
|
|
bitfld.long 0x00 31. " ETBR15 ,Endpoint transmit buffer ready 15" "Not ready,Ready"
|
|
bitfld.long 0x00 30. " ETBR14 ,Endpoint transmit buffer ready 14" "Not ready,Ready"
|
|
bitfld.long 0x00 29. " ETBR13 ,Endpoint transmit buffer ready 13" "Not ready,Ready"
|
|
bitfld.long 0x00 28. " ETBR12 ,Endpoint transmit buffer ready 12" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ETBR11 ,Endpoint transmit buffer ready 11" "Not ready,Ready"
|
|
bitfld.long 0x00 26. " ETBR10 ,Endpoint transmit buffer ready 10" "Not ready,Ready"
|
|
bitfld.long 0x00 25. " ETBR9 ,Endpoint transmit buffer ready 9" "Not ready,Ready"
|
|
bitfld.long 0x00 24. " ETBR8 ,Endpoint transmit buffer ready 8" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ETBR7 ,Endpoint transmit buffer ready 7" "Not ready,Ready"
|
|
bitfld.long 0x00 22. " ETBR6 ,Endpoint transmit buffer ready 6" "Not ready,Ready"
|
|
bitfld.long 0x00 21. " ETBR5 ,Endpoint transmit buffer ready 5" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " ETBR4 ,Endpoint transmit buffer ready 4" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ETBR3 ,Endpoint transmit buffer ready 3" "Not ready,Ready"
|
|
bitfld.long 0x00 18. " ETBR2 ,Endpoint transmit buffer ready 2" "Not ready,Ready"
|
|
bitfld.long 0x00 17. " ETBR1 ,Endpoint transmit buffer ready 1" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " ETBR0 ,Endpoint transmit buffer ready 0" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ERBR15 ,Endpoint receive buffer ready 15" "Not ready,Ready"
|
|
bitfld.long 0x00 14. " ERBR14 ,Endpoint receive buffer ready 14" "Not ready,Ready"
|
|
bitfld.long 0x00 13. " ERBR13 ,Endpoint receive buffer ready 13" "Not ready,Ready"
|
|
bitfld.long 0x00 12. " ERBR12 ,Endpoint receive buffer ready 12" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERBR11 ,Endpoint receive buffer ready 11" "Not ready,Ready"
|
|
bitfld.long 0x00 10. " ERBR10 ,Endpoint receive buffer ready 10" "Not ready,Ready"
|
|
bitfld.long 0x00 9. " ERBR9 ,Endpoint receive buffer ready 9" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " ERBR8 ,Endpoint receive buffer ready 8" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERBR7 ,Endpoint receive buffer ready 7" "Not ready,Ready"
|
|
bitfld.long 0x00 6. " ERBR6 ,Endpoint receive buffer ready 6" "Not ready,Ready"
|
|
bitfld.long 0x00 5. " ERBR5 ,Endpoint receive buffer ready 5" "Not ready,Ready"
|
|
bitfld.long 0x00 4. " ERBR4 ,Endpoint receive buffer ready 4" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERBR3 ,Endpoint receive buffer ready 3" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " ERBR2 ,Endpoint receive buffer ready 2" "Not ready,Ready"
|
|
bitfld.long 0x00 1. " ERBR1 ,Endpoint receive buffer ready 1" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " ERBR0 ,Endpoint receive buffer ready 0" "Not ready,Ready"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0,USB2D Endpoint Complete Register"
|
|
bitfld.long 0x00 31. " ETCE15 ,Endpoint transmit buffer complete event 15" "Not completed,Completed"
|
|
bitfld.long 0x00 30. " ETCE14 ,Endpoint transmit buffer complete event 14" "Not completed,Completed"
|
|
bitfld.long 0x00 29. " ETCE13 ,Endpoint transmit buffer complete event 13" "Not completed,Completed"
|
|
bitfld.long 0x00 28. " ETCE12 ,Endpoint transmit buffer complete event 12" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ETCE11 ,Endpoint transmit buffer complete event 11" "Not completed,Completed"
|
|
bitfld.long 0x00 26. " ETCE10 ,Endpoint transmit buffer complete event 10" "Not completed,Completed"
|
|
bitfld.long 0x00 25. " ETCE9 ,Endpoint transmit buffer complete event 9" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " ETCE8 ,Endpoint transmit buffer complete event 8" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ETCE7 ,Endpoint transmit buffer complete event 7" "Not completed,Completed"
|
|
bitfld.long 0x00 22. " ETCE6 ,Endpoint transmit buffer complete event 6" "Not completed,Completed"
|
|
bitfld.long 0x00 21. " ETCE5 ,Endpoint transmit buffer complete event 5" "Not completed,Completed"
|
|
bitfld.long 0x00 20. " ETCE4 ,Endpoint transmit buffer complete event 4" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ETCE3 ,Endpoint transmit buffer complete event 3" "Not completed,Completed"
|
|
bitfld.long 0x00 18. " ETCE2 ,Endpoint transmit buffer complete event 2" "Not completed,Completed"
|
|
bitfld.long 0x00 17. " ETCE1 ,Endpoint transmit buffer complete event 1" "Not completed,Completed"
|
|
bitfld.long 0x00 16. " ETCE0 ,Endpoint transmit buffer complete event 0" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ERCE15 ,Endpoint receive buffer complete event 15" "Not completed,Completed"
|
|
bitfld.long 0x00 14. " ERCE14 ,Endpoint receive buffer complete event 14" "Not completed,Completed"
|
|
bitfld.long 0x00 13. " ERCE13 ,Endpoint receive buffer complete event 13" "Not completed,Completed"
|
|
bitfld.long 0x00 12. " ERCE12 ,Endpoint receive buffer complete event 12" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERCE11 ,Endpoint receive buffer complete event 11" "Not completed,Completed"
|
|
bitfld.long 0x00 10. " ERCE10 ,Endpoint receive buffer complete event 10" "Not completed,Completed"
|
|
bitfld.long 0x00 9. " ERCE9 ,Endpoint receive buffer complete event 9" "Not completed,Completed"
|
|
bitfld.long 0x00 8. " ERCE8 ,Endpoint receive buffer complete event 8" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERCE7 ,Endpoint receive buffer complete event 7" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " ERCE6 ,Endpoint receive buffer complete event 6" "Not completed,Completed"
|
|
bitfld.long 0x00 5. " ERCE5 ,Endpoint receive buffer complete event 5" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " ERCE4 ,Endpoint receive buffer complete event 4" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERCE3 ,Endpoint receive buffer complete event 3" "Not completed,Completed"
|
|
bitfld.long 0x00 2. " ERCE2 ,Endpoint receive buffer complete event 2" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " ERCE1 ,Endpoint receive buffer complete event 1" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " ERCE0 ,Endpoint receive buffer complete event 0" "Not completed,Completed"
|
|
else
|
|
hgroup.long 0x208++0x13
|
|
hide.long 0x00 "USB3_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0,USB2D Endpoint Setup Status Register"
|
|
hide.long 0x04 "USB3_CONTROLLER_2_USB2D_ENDPTPRIME_0,USB2D Endpoint Initialization Register"
|
|
hide.long 0x08 "USB3_CONTROLLER_2_USB2D_ENDPTFLUSH_0,USB2D Endpoint De-Initialization Register"
|
|
hide.long 0x0C "USB3_CONTROLLER_2_USB2D_ENDPTSTATUS_0,USB2D Endpoint Status Register"
|
|
hide.long 0x10 "USB3_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0,USB2D Endpoint Complete Register"
|
|
endif
|
|
tree.end
|
|
width 39.
|
|
tree "Endpoint Control"
|
|
rgroup.long 0x21C++0x03
|
|
line.long 0x00 "USB3_CONTROLLER_2_USB2D_ENDPTCTRL0_0,USB2D Endpoint Control 0 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
bitfld.long 0x00 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
bitfld.long 0x00 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
group.long 0x220++0x3B
|
|
line.long 0x0 "USB3_CONTROLLER_2_USB2D_ENDPTCTRL1_0,USB2D Endpoint Control 1 Register"
|
|
bitfld.long 0x0 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x0 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x0 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x0 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x0 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x0 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x0 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x0 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x4 "USB3_CONTROLLER_2_USB2D_ENDPTCTRL2_0,USB2D Endpoint Control 2 Register"
|
|
bitfld.long 0x4 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x4 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x4 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x4 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x4 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x4 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x4 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x4 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x8 "USB3_CONTROLLER_2_USB2D_ENDPTCTRL3_0,USB2D Endpoint Control 3 Register"
|
|
bitfld.long 0x8 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x8 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x8 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x8 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x8 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x8 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x8 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x8 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x8 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x8 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0xC "USB3_CONTROLLER_2_USB2D_ENDPTCTRL4_0,USB2D Endpoint Control 4 Register"
|
|
bitfld.long 0xC 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0xC 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0xC 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0xC 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0xC 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0xC 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0xC 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0xC 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0xC 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0xC 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x10 "USB3_CONTROLLER_2_USB2D_ENDPTCTRL5_0,USB2D Endpoint Control 5 Register"
|
|
bitfld.long 0x10 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x10 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x10 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x10 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x10 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x10 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x10 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x14 "USB3_CONTROLLER_2_USB2D_ENDPTCTRL6_0,USB2D Endpoint Control 6 Register"
|
|
bitfld.long 0x14 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x14 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x14 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x14 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x14 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x14 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x14 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x14 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x18 "USB3_CONTROLLER_2_USB2D_ENDPTCTRL7_0,USB2D Endpoint Control 7 Register"
|
|
bitfld.long 0x18 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x18 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x18 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x18 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x18 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x18 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x18 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x18 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x18 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x1C "USB3_CONTROLLER_2_USB2D_ENDPTCTRL8_0,USB2D Endpoint Control 8 Register"
|
|
bitfld.long 0x1C 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x1C 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x1C 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x1C 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x1C 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x1C 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x1C 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x20 "USB3_CONTROLLER_2_USB2D_ENDPTCTRL9_0,USB2D Endpoint Control 9 Register"
|
|
bitfld.long 0x20 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x20 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x20 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x20 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x20 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x20 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x20 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x20 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x20 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x24 "USB3_CONTROLLER_2_USB2D_ENDPTCTRL10_0,USB2D Endpoint Control 10 Register"
|
|
bitfld.long 0x24 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x24 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x24 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x24 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x24 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x24 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x24 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x24 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x24 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x28 "USB3_CONTROLLER_2_USB2D_ENDPTCTRL11_0,USB2D Endpoint Control 11 Register"
|
|
bitfld.long 0x28 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x28 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x28 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x28 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x28 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x28 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x28 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x28 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x28 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x2C "USB3_CONTROLLER_2_USB2D_ENDPTCTRL12_0,USB2D Endpoint Control 12 Register"
|
|
bitfld.long 0x2C 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x2C 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x2C 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x2C 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x2C 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x2C 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x2C 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x2C 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x30 "USB3_CONTROLLER_2_USB2D_ENDPTCTRL13_0,USB2D Endpoint Control 13 Register"
|
|
bitfld.long 0x30 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x30 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x30 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x30 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x30 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x30 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x30 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x30 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x30 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x34 "USB3_CONTROLLER_2_USB2D_ENDPTCTRL14_0,USB2D Endpoint Control 14 Register"
|
|
bitfld.long 0x34 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x34 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x34 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x34 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x34 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x34 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x34 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x34 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x34 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
line.long 0x38 "USB3_CONTROLLER_2_USB2D_ENDPTCTRL15_0,USB2D Endpoint Control 15 Register"
|
|
bitfld.long 0x38 23. " TXE ,TX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 22. " TXR ,TX data toggle reset" "No reset,Reset"
|
|
bitfld.long 0x38 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x38 18.--19. " TXT ,TX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x38 17. " TXD ,TXD" "Disabled,Enabled"
|
|
bitfld.long 0x38 16. " TXS ,TX endpoint stall" "EP_OK,EP_STALL"
|
|
bitfld.long 0x38 7. " RXE ,RX endpoint enable" "Disabled,Enabled"
|
|
bitfld.long 0x38 6. " RXR ,RX data toggle reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x38 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x38 2.--3. " RXT ,RX endpoint type" "CTRL,ISO,BULK,INTR"
|
|
rbitfld.long 0x38 1. " RXD ,RXD" "Disabled,Enabled"
|
|
bitfld.long 0x38 0. " RXS ,RX endpoint stall" "EP_OK,EP_STALL"
|
|
tree.end
|
|
tree.end
|
|
width 28.
|
|
tree "USB 3 Controller Interface"
|
|
if (((d.l(ad:0x7D008000+0x1F8))&0x03)==0x02)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "USB3_IF_USB_SUSP_CTRL_0,USB suspend control register"
|
|
bitfld.long 0x00 25. " UTMIP_SUSPL1_SET ,Enable SuspendL1 for UTMIP PHY" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " UHSIC_PHY_ENB ,Enable UHSIC PHY mode (Set this to 0)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " USB_WAKEUP_DEBOUNCE_COUNT ,USB PHY wakeup debounce counter" "0,1,2,3,4,5,6,7"
|
|
eventfld.long 0x00 14. " UHSIC_RESET ,Reset going to UHSIC PHY" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ICUSB_PHY_ENB ,Enable ICUSB PHY mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " UTMIP_PHY_ENB ,Enable UTMIP PHY mode" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " UTMIP_RESET ,Reset goint to UTMIP PHY" "Not reset,Reset"
|
|
bitfld.long 0x00 10. " USB_SUSUP_POL ,Polarity of the suspend signal going to USB PHY" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 9. " USB_PHY_CLK_VALID_INT_ENB ,USB PHY clock valid interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " USB_PHY_CLK_VALID_INT_STS ,USB PHY clock valid interrupt status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " USB_PHY_CLK_VALID ,USB PHY clock valid status" "Invalid,Valid"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " USB_CLKEN ,USB AHB clock enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " USB_SUSP_CLR ,PHY suspend mode control" "Suspended,Not suspended"
|
|
bitfld.long 0x00 4. " USB_WAKE_ON_DISCON_EN_DEV ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USB_WAKE_ON_CNNT_EN_DEV ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " USB_WAKE_ON_RESUME_EN ,Wake on resume" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " USB_WAKEUP_INT_ENB ,USB wakeup interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " USB_WAKEUP_INT_STS ,USB wakeup interrupt status" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "USB3_IF_USB_SUSP_CTRL_0,USB suspend control register"
|
|
bitfld.long 0x00 26. " FAST_WAKEUP_RESP ,Enable fast response from UTMIP PHY for a remote wakeup request from device" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " UTMIP_SUSPL1_SET ,Enable SuspendL1 for UTMIP PHY" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " UHSIC_PHY_ENB ,Enable UHSIC PHY mode (Set this to 0)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " USB_WAKEUP_DEBOUNCE_COUNT ,USB PHY wakeup debounce counter" "0,1,2,3,4,5,6,7"
|
|
eventfld.long 0x00 14. " UHSIC_RESET ,Reset going to UHSIC PHY" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ICUSB_PHY_ENB ,Enable ICUSB PHY mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " UTMIP_PHY_ENB ,Enable UTMIP PHY mode" "Disabled,Enabled"
|
|
eventfld.long 0x00 11. " UTMIP_RESET ,Reset goint to UTMIP PHY" "Not reset,Reset"
|
|
bitfld.long 0x00 10. " USB_SUSUP_POL ,Polarity of the suspend signal going to USB PHY" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 9. " USB_PHY_CLK_VALID_INT_ENB ,USB PHY clock valid interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " USB_PHY_CLK_VALID_INT_STS ,USB PHY clock valid interrupt status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 7. " USB_PHY_CLK_VALID ,USB PHY clock valid status" "Invalid,Valid"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " USB_CLKEN ,USB AHB clock enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " USB_SUSP_CLR ,PHY suspend mode control" "Suspended,Not suspended"
|
|
bitfld.long 0x00 2. " USB_WAKE_ON_RESUME_EN ,Wake on resume" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " USB_WAKEUP_INT_ENB ,USB wakeup interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " USB_WAKEUP_INT_STS ,USB wakeup interrupt status" "No interrupt,Interrupt"
|
|
endif
|
|
textline ""
|
|
width 34.
|
|
group.long 0x404++0x07
|
|
line.long 0x00 "USB3_IF_USB_PHY_VBUS_SENSORS_0,USB PHY VBUS SENSORS control register"
|
|
bitfld.long 0x00 30. " A_VBUS_VLD_WAKEUP_EN ,A_VBUS_VLD wakeup enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " A_VBUS_VLD_DEB_SEL_B ,A_VBUS_VLD debounce A/B select" "SEL_A,SEL_B"
|
|
bitfld.long 0x00 28. " A_VBUS_VLD_SW_VALUE ,A_VBUS_VLD software value (software enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " A_VBUS_VLD_SW_EN ,A_VBUS_VLD software enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " A_VBUS_VLD_STS ,A_VBUS_VLD status" "Low,High"
|
|
rbitfld.long 0x00 25. " A_VBUS_VLD_CHG_DET ,A_VBUS_VLD change detect" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 24. " A_VBUS_VLD_INT_EN ,A_VBUS_VLD interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " A_SESS_VLD_WAKEUP_EN ,A_SESS_VLD wakeup enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " A_SESS_VLD_DEB_SEL_B ,A_SESS_VLD debounce A/B select" "SEL_A,SEL_B"
|
|
textline " "
|
|
bitfld.long 0x00 20. " A_SESS_VLD_SW_VALUE ,A_SESS_VLD software value (software enabled)" "Low,High"
|
|
bitfld.long 0x00 19. " A_SESS_VLD_SW_EN ,A_SESS_VLD software enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 18. " A_SESS_VLD_STS ,A_SESS_VLD status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " A_SESS_VLD_CHG_DET ,A_SESS_VLD change detect" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " A_SESS_VLD_INT_EN ,A_SESS_VLD interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " B_SESS_VLD_WAKEUP_EN ,B_SESS_VLD wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " B_SESS_VLD_DEB_SEL_B ,B_SESS_VLD debounce A/B select" "SEL_A,SEL_B"
|
|
bitfld.long 0x00 12. " B_SESS_VLD_SW_VALUE ,B_SESS_VLD software value (software enabled)" "Low,High"
|
|
bitfld.long 0x00 11. " B_SESS_VLD_SW_EN ,B_SESS_VLD software enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " B_SESS_VLD_STS ,B_SESS_VLD status" "Low,High"
|
|
rbitfld.long 0x00 9. " B_SESS_VLD_CHG_DET ,B_SESS_VLD change detect" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " B_SESS_VLD_INT_EN ,B_SESS_VLD interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " B_SESS_END_WAKEUP_EN ,B_SESS_END wakeup enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " B_SESS_END_DEB_SEL_B ,B_SESS_END debounce A/B select" "SEL_A,SEL_B"
|
|
bitfld.long 0x00 4. " B_SESS_END_SW_VALUE ,B_SESS_END software value (software enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " B_SESS_END_SW_EN ,B_SESS_END software enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " B_SESS_END_STS ,B_SESS_END status" "Low,High"
|
|
rbitfld.long 0x00 1. " B_SESS_END_CHG_DET ,B_SESS_END change detect" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " B_SESS_END_INT_EN ,B_SESS_END interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0,USB PHY VBUS wakeup and ID control register"
|
|
bitfld.long 0x04 31. " DIV_DET_EN ,Battery charger divider detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " VBUS_WAKEUP_WAKEUP_EN ,VBUS_WAKEUP wakeup enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " VDCD_DET_DEB_SEL_B ,VCDT_DET debounce A/B select" "SEL_A,SEL_B"
|
|
textline " "
|
|
bitfld.long 0x04 28. " VDCD_DET_SW_VALUE ,VDCD_DET software value (software enabled)" "Low,High"
|
|
bitfld.long 0x04 27. " VDCD_DET_SW_EN ,VDCD_DET software enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 26. " VDCD_DET_STS ,VDCD_DET status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x04 25. " VDCD_DET_CHG_DET ,VDCD_DET change detect" "Not detected,Detected"
|
|
bitfld.long 0x04 24. " VDCD_DET_INT_EN ,VDCD_DET interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 23. " VOP_DIV2P7_DET ,Status bit is from the battery charging divider circuit of the USB2OTG pad" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x04 22. " VOP_DIV2P0_DET ,Status bit is from the battery charging divider circuit of the USB2OTG pad" "Low,High"
|
|
bitfld.long 0x04 21. " VDAT_DET_DEB_SEL_B ,VDAT_DET debounce A/B select" "SEL_A,SEL_B"
|
|
bitfld.long 0x04 20. " VDAT_DET_SW_VALUE ,VDAT_DET software value (software enabled)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 19. " VDAT_DET_SW_EN ,VDAT_DET software enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 18. " VDAT_DET_STS ,VDAT_DET status" "Low,High"
|
|
rbitfld.long 0x04 17. " VDAT_DET_CHG_DET ,VDAT_DET change detect" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 16. " VDAT_DET_INT_EN ,VDAT_DET interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " VON_DIV2P7_DET ,Status bit is from the battery charging divider circuit of the USB2OTG pad" "Low,High"
|
|
bitfld.long 0x04 14. " VON_DIV2P0_DET ,Status bit is from the battery charging divider circuit of the USB2OTG pad" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 13. " VBUS_WAKEUP_DEB_SEL_B ,VBUS_WAKEUP debounce A/B select" "SEL_A,SEL_B"
|
|
bitfld.long 0x04 12. " VBUS_WAKEUP_SW_VALUE ,VBUS wakeup software value (software enabled)" "Low,High"
|
|
bitfld.long 0x04 11. " VBUS_WAKEUP_SW_EN ,VBUS wakeup software enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 10. " VBUS_WAKEUP_STS ,VBUS wakeup status" "Low,High"
|
|
rbitfld.long 0x04 9. " VBUS_WAKEUP_CHG_DET ,VBUS wakeup change detect" "Not detected,Detected"
|
|
bitfld.long 0x04 8. " VBUS_WAKEUP_INT_EN ,VBUS wakeup interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 7. " STATIC_GPI ,Static GPI status" "Low,High"
|
|
bitfld.long 0x04 6. " ID_PU ,ID pullup enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " ID_DEB_SEL_B ,ID debounce A/B select" "SEL_A,SEL_B"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ID_SW_VALUE ,ID software value (software enabled)" "Low,High"
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|
bitfld.long 0x04 3. " ID_SW_EN ,ID software enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 2. " ID_STS ,ID status" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " ID_CHG_DET ,ID change detect" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " ID_INT_EN ,ID interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "USB3_IF_USB_PHY_ALT_VBUS_STS_0,USB PHY Alternate VBUS status register"
|
|
bitfld.long 0x00 8. " VDCD_DET_ALT ,VDCD_DET alternate status" "Low,High"
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|
bitfld.long 0x00 7. " VDAT_DET_ALT ,VDAT_DET alternate status" "Low,High"
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|
bitfld.long 0x00 6. " A_SESS_VLD_ALT ,A_SESS_VLD alternate status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " B_SESS_VLD_ALT ,B_SESS_VLD alternate status" "Low,High"
|
|
bitfld.long 0x00 4. " ID_DIG_ALT ,ID alternate status" "Low,High"
|
|
bitfld.long 0x00 3. " B_SESS_END_ALT ,B_SESS_END alternate status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " STATIC_GPI_ALT ,Static GPI alternate status" "Low,High"
|
|
bitfld.long 0x00 1. " A_VBUS_VLD_ALT ,A_VBUS_VLD alternate status" "Low,High"
|
|
bitfld.long 0x00 0. " VBUS_WAKEUP_ALT ,Vbus wakeup alternate status" "Low,High"
|
|
textline ""
|
|
width 36.
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "USB3_IF_ICUSB_XCVR_CFG_0,ICUSB Transceiver Configuration register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ICUSB_CALOUT ,ICUSB PHY calibration code"
|
|
bitfld.long 0x00 20. " ICUSB_CALOUT_EN ,ICUSB PHY auto-calibration enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " ICUSB_DRV ,ICUSB PHY Drive strength offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " ICUSB_SLEW ,ICUSB PHY FS/LS slew rate control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 7. " ICUSB_SEL_DIFF_RCVR ,ICUSB differential receiver select" "Single,Diff"
|
|
bitfld.long 0x00 3. " ICUSB_IDDQ ,ICUSB PHY IDDQ shutdown mode" "Normal,Off"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ICUSB_PD_ZI ,ICUSB PHY Single-ended receiver power down" "Normal,Off"
|
|
bitfld.long 0x00 1. " ICUSB_PD_DR ,ICUSB PHY Differential receiver power down" "Normal,Off"
|
|
bitfld.long 0x00 0. " ICUSB_PD_TX ,ICUSB PHY Low/full-speed driver power down" "Normal,Off"
|
|
if (((d.l(ad:0x7D008000+0x1F8))&0x03)==0x03)
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "USB3_IF_USB_INTER_PKT_DELAY_CTRL_0,Inter packet delay control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " IP_DELAY_TX2TX_HS ,HS Tx to Tx inter-packet delay"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "USB3_IF_USB_RSM_DLY_0,USB Controller Resume Signalling Delay"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIME_TO_RESUME ,Send the resume back in no. of 60 MHz cycles"
|
|
else
|
|
hgroup.long 0x420++0x03
|
|
hide.long 0x00 "USB3_IF_USB_INTER_PKT_DELAY_CTRL_0,Inter packet delay control"
|
|
hgroup.long 0x490++0x03
|
|
hide.long 0x00 "USB3_IF_USB_RSM_DLY_0,USB Controller Resume Signalling Delay"
|
|
endif
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "USB3_IF_ICUSB_PADCTLS_0,ICUSB Pad Controls Config"
|
|
bitfld.long 0x00 8. " ICUSB_RPU2_EN ,Config RPU2_EN state" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ICUSB_DISABLE_PULLUP_DP ,Force DP pullup inactive" "No,Yes"
|
|
bitfld.long 0x00 6. " ICUSB_DISABLE_PULLUP_DM ,Force DM pullup inactive" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ICUSB_DISABLE_PULLDN_DP ,Force DP pulldown inactive" "No,Yes"
|
|
bitfld.long 0x00 4. " ICUSB_DISABLE_PULLDN_DM ,Force DM pulldown inactive" "No,Yes"
|
|
bitfld.long 0x00 3. " ICUSB_FORCE_PULLUP_DP ,Force DP pullup active" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ICUSB_FORCE_PULLUP_DM ,Force DM pullup active" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ICUSB_FORCE_PULLDN_DP ,Force DP pulldown active" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ICUSB_FORCE_PULLDN_DM ,Force DM PullDown active" "Disabled,Enabled"
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "USB3_IF_SPARE_0,ICUSB PADCTLS Spare Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPARE_HI ,Spare register bits"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPARE_LO ,Spare register bits"
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "USB3_IF_USB1_NEW_CONTROL_0,USB Coherency and Memory Alignment Controls"
|
|
hexmask.long.byte 0x00 8.--15. 1. " REQUEST_EXPIRY_COUNTER ,Time to wait for coalescing the request"
|
|
bitfld.long 0x00 1. " MEM_ALIGNMENT_MUX_EN ,DMA request generation mechanism" "Tegra 3,Tegra K1"
|
|
bitfld.long 0x00 0. " COHERENCY_EN ,Enable fence mechanism" "Disabled,Enabled"
|
|
tree.end
|
|
width 28.
|
|
tree "USB 3 UTMIP Configuration"
|
|
group.long 0x808++0x37
|
|
line.long 0x00 "USB3_UTMIP_XCVR_CFG0_0,UTMIP transceiver cell configuration register 0"
|
|
hexmask.long.byte 0x00 25.--31. 1. " UTMIP_XCVR_HSSLEW_MSB ,Most significant bits of HS_SLEW"
|
|
bitfld.long 0x00 22.--24. " UTMIP_XCVR_SETUP_MSB ,Most significant bits of SETUP" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
eventfld.long 0x00 21. " UTMIP_XCVR_LSBIAS_SEL ,Low speed bias selection method for usb transceiver pad" "0,1"
|
|
bitfld.long 0x00 20. " UTMIP_XCVR_DISCON_METHOD ,Disconnect method on the usb transceiver pad" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " UTMIP_FORCE_PDZI_POWERUP ,Force PDZI input into power up" "Disabled,Enabled"
|
|
eventfld.long 0x00 18. " UTMIP_FORCE_PDZI_POWERDOWN ,Force PDZI input into power down" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " UTMIP_FORCE_PD2_POWERUP ,Force PD2 input into power up" "Disabled,Enabled"
|
|
eventfld.long 0x00 16. " UTMIP_FORCE_PD2_POWERDOWN ,Force PD2 input into power down" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " UTMIP_FORCE_PD_POWERUP ,Force PD input into power up" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " UTMIP_FORCE_PD_POWERDOWN ,Force PD input into power down" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 13. " UTMIP_XCVR_TERMEN ,Enable HS termination" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UTMIP_XCVR_HSLOOPBACK ,Internal loopback inside XCVR cell" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " UTMIP_XCVR_LSFSLEW ,LS falling slew rate control" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " UTMIP_XCVR_LSRSLEW ,LS rising slew rate control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " UTMIP_XCVR_FSSLEW ,FS slew rate control" "0,1,2,3"
|
|
bitfld.long 0x00 4.--5. " UTMIP_XCVR_HSSLEW ,HS slew rate control" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " UTMIP_XCVR_SETUP ,SETUP[3:0] input of XCVR cell" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "USB3_UTMIP_BIAS_CFG0_0,UTMIP Bias cell configuration register 0"
|
|
bitfld.long 0x04 30. " UTMIP_IDDIG_C_VAL ,UTMIP IDDIG C VAL" "0,1"
|
|
bitfld.long 0x04 29. " UTMIP_IDDIG_C_SEL ,UTMIP IDDIG C SEL" "IdDig_c,IDDIG_C_VAL"
|
|
textline " "
|
|
bitfld.long 0x04 28. " UTMIP_IDDIG_B_VAL ,UTMIP IDDIG B VAL" "0,1"
|
|
bitfld.long 0x04 27. " UTMIP_IDDIG_B_SEL ,UTMIP IDDIG B SEL" "IdDig_b,IDDIG_B_VAL"
|
|
textline " "
|
|
bitfld.long 0x04 26. " UTMIP_IDDIG_A_VAL ,UTMIP IDDIG A VAL" "0,1"
|
|
bitfld.long 0x04 25. " UTMIP_IDDIG_A_SEL ,UTMIP IDDIG A SEL" "IdDig_a,IDDIG_A_VAL"
|
|
textline " "
|
|
bitfld.long 0x04 24. " UTMIP_HSDISCON_LEVEL_MSB ,Most significant bit of UTMIP_HSDISCON_LEVEL" "0,1"
|
|
eventfld.long 0x04 23. " UTMIP_IDPD_VAL ,IDPD value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 21. " UTMIP_IDDIG_SEL ,IDDIG value" "0,1"
|
|
bitfld.long 0x04 20. " UTMIP_IDDIG_SEL ,IDDIG select" "IdDig,IDDIG_VAL"
|
|
textline " "
|
|
bitfld.long 0x04 19. " UTMIP_GPI_VAL ,GPI value" "0,1"
|
|
bitfld.long 0x04 18. " UTMIP_GPI_SEL ,GPI select" "IdDig,GPI_VAL"
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " UTMIP_ACTIVE_TERM_OFFSET ,Active termination control offset" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 12.--14. " UTMIP_ACTIVE_PULLUP_OFFSET ,Active 1.5K pullup control offset" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
eventfld.long 0x04 11. " UTMIP_OTGPD ,Power down OTG circuit" "Disabled,Enabled"
|
|
eventfld.long 0x04 10. " UTMIP_BIASPD ,Power down bias circuit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " UTMIP_VBUS_LEVEL_LEVEL ,Vbus detector level" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " UTMIP_SESS_LEVEL_LEVEL ,SessionEnd detector level" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " UTMIP_HSCHIRP_LEVEL ,HS chirp detector level" "0,1,2,3"
|
|
bitfld.long 0x04 2.--3. " UTMIP_HSDISCON_LEVEL ,HS disconnect detector level" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " UTMIP_HSSQUELCH_LEVEL ,HS squelch detector level" "0,1,2,3"
|
|
line.long 0x08 "USB3_UTMIP_HSRX_CFG0_0,UTMIP High speed receive config 0"
|
|
bitfld.long 0x08 30.--31. " UTMIP_KEEP_PATT_ON_ACTIVE ,Keep the stay alive pattern on active" "0,1,2,3"
|
|
bitfld.long 0x08 29. " UTMIP_ALLOW_CONSEC_UPDN ,Allow consecutive ups and downs on the bits" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 28. " UTMIP_REALIGN_ON_NEW_PKT ,Realign the inertia counters on a new packet" "Disabled,Enabled"
|
|
bitfld.long 0x08 24.--27. " UTMIP_PCOUNT_UPDN_DIV ,The number of (edges-1) needed to move the sampling point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 21.--23. " UTMIP_SQUELCH_EOP_DLY ,Limit the delay of the squelch at EOP time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 20. " UTMIP_NO_STRIPPING ,Do not strip incoming data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15.--19. " UTMIP_IDLE_WAIT ,Number of cycles of idle to declare IDLE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 10.--14. " UTMIP_ELASTIC_LIMIT ,Depth of elastic input store" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 9. " UTMIP_ELASTIC_OVERRUN_DISABLE ,Do not declare overrun errors until overflow of FIFO" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " UTMIP_ELASTIC_UNDERRUN_DISABLE ,Do not declare underrun errors" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " UTMIP_PASS_CHIRP ,When in Chirp Mode, allow chirp rx data through" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " UTMIP_PASS_FEEDBACK ,Pass through the feedback, do not block it" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " UTMIP_PCOUNT_INERTIA ,Retime the path" "0,1,2,3"
|
|
bitfld.long 0x08 2.--3. " UTMIP_PHASE_ADJUST ,Based on incoming edges and current sampling position phase adjust" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 1. " UTMIP_THREE_SYNCBITS ,Sync pattern detection needs 3 consecutive samples instead of 4" "No,Yes"
|
|
bitfld.long 0x08 0. " UTMIP_USE4SYNC_TRAN ,Require 4 sync pattern transitions (01) instead of 3" "No,Yes"
|
|
line.long 0x0C "USB3_UTMIP_HSRX_CFG1_0,UTMIP High speed receive config 1"
|
|
bitfld.long 0x0C 1.--5. " UTMIP_HS_SYNC_START_DLY ,How long to wait before start of sync launches RxActive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 0. " UTMIP_HS_ALLOW_KEEP_ALIVE ,Allow Keep Alive packets" "Disabled,Enabled"
|
|
line.long 0x10 "USB3_UTMIP_FSLSRX_CFG0_0,UTMIP full and Low speed receive config 0"
|
|
bitfld.long 0x10 31. " UTMIP_FSLS_SE1_DRIBBLE_FILTER ,Don't allow dribble" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " UTMIP_FSLS_SE1_FILTER ,Filter SE1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 29. " UTMIP_FSLS_SERIAL_SE0_RCV ,UTMIP_FSLS_SERIAL_SE0_RCV" "0,1"
|
|
bitfld.long 0x10 26.--28. " UTMIP_FSLS_UPR_DRIBBLE_SIZE ,Do not allow <= dribble bits" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 23.--25. " UTMIP_FSLS_LWR_DRIBBLE_SIZE ,Do not allow >= dribble bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 22. " UTMIP_FSLS_EOP_ENDS_AT_SE0 ,Only look for transitioning out of EOP" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x10 16.--21. " UTMIP_FSLS_KCOUNT_MAX ,Number of K bits in question" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x10 15. " UTMIP_FSLS_KCOUNT_LIMIT ,Limit the number of bit times a K can last" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x10 14. " UTMIP_FSLS_ACTIVE_ON_FULL_SYNC ,Require a full sync pattern to declare the data received" "No,Yes"
|
|
bitfld.long 0x10 8.--13. " UTMIP_FSLS_IDLE_WAIT_MAX ,IDLE wait max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x10 7. " UTMIP_FSLS_IDLE_WAIT_LIMIT ,Enable the reset of the state machine on extended SE0" "Disabled,Enabled"
|
|
bitfld.long 0x10 1.--6. " UTMIP_FSLS_IDLE_COUNT_MAX ,Idle count max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x10 0. " UTMIP_FSLS_IDLE_COUNT_LIMIT ,Give up on packet if a long sequence of J" "No,Yes"
|
|
line.long 0x14 "USB3_UTMIP_FSLSRX_CFG1_0,UTMIP full and Low speed receive config 1"
|
|
bitfld.long 0x14 26. " UTMIP_EARLY_LINE_STATE_FILTER ,Assumes line state filtering table is inclusive" "No,Yes"
|
|
bitfld.long 0x14 23.--25. " UTMIP_LS_BOUNCE_LENGTH ,Number of clock cycle of LS stable" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 17.--22. " UTMIP_LS_EXTRACTION_COUNT ,Phase count on which LS bits are extracted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x14 11.--16. " UTMIP_LS_EOP_START_COUNT ,Number of SEO clock cycles to block bit extraction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x14 5.--10. " UTMIP_LS_SE0_COUNT ,Only for this number of 60MHz of SEO and Idle to end packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 4. " UTMIP_LS_LENIENT_DRIBBLE ,Allow for large dribble in low speed mode" "Disabled,Enabled"
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textline " "
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bitfld.long 0x14 3. " UTMIP_FS_LENIENT_DRIBBLE ,Allow for large dribble in full speed mode" "Disabled,Enabled"
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bitfld.long 0x14 2. " UTMIP_FS_WEAK_SYNC ,Only look for a KK pattern instead of KJKK" "No,Yes"
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textline " "
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bitfld.long 0x14 1. " UTMIP_FS_DEBOUNCE ,Whether full speed uses debouncing" "No,Yes"
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bitfld.long 0x14 0. " UTMIP_FS_EOP_LENGTH ,Whether full speed EOP is determined within 3(0) or 4(1) 60MHz cycles" "3 cycles,4 cycles"
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line.long 0x18 "USB3_UTMIP_TX_CFG0_0,UTMIP transmit config signals"
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bitfld.long 0x18 19. " UTMIP_FS_PREAMBLE_J ,Output enable sends an initial J before sync pattern" "Disabled,Enabled"
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bitfld.long 0x18 18. " UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE ,Output enable turns off 1/2 cycle after" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 17. " UTMIP_FS_PREAMBLE_OUTPUT_ENABLE ,Output enable turns on 1/2 cycle before" "Disabled,Enabled"
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bitfld.long 0x18 16. " UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR ,Allow SOP to be source of transmit error stuffing" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 15. " UTMIP_HS_READY_WAIT_FOR_VALID ,UTMIP_HS_READY_WAIT_FOR_VALID" "0,1"
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bitfld.long 0x18 10.--14. " UTMIP_HS_TX_IPG_DLY ,UTMIP_HS_TX_IPG_DLY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x18 9. " UTMIP_HS_DISCON_EOP_ONLY ,Only check during EOP" "No,Yes"
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bitfld.long 0x18 8. " UTMIP_HS_DISCON_DISABLE ,Disable high speed disconnect" "Enabled,Disabled"
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textline " "
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bitfld.long 0x18 7. " UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE ,Output enable turns off 1 cycle after" "Disabled,Enabled"
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bitfld.long 0x18 6. " UTMIP_HS_PREAMBLE_OUTPUT_ENABLE ,Output enable turns on 1 cycle before" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 5. " UTMIP_SIE_RESUME_ON_LINESTATE ,SIE (not macrocell) detects LineState change to resume" "No,Yes"
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bitfld.long 0x18 4. " UTMIP_SOF_ON_NO_STUFF ,Sof when OpMode 3 -- perhaps, when sending controller made packets" "0,1"
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textline " "
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bitfld.long 0x18 3. " UTMIP_SOF_ON_NO_ENCODE ,Sof when OpMode 2 -- not likely, for Chirp" "0,1"
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bitfld.long 0x18 2. " UTMIP_NO_STUFFING ,No bit stuffing, static programming" "0,1"
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textline " "
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bitfld.long 0x18 1. " UTMIP_NO_ENCODING ,No encoding, static programming" "0,1"
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bitfld.long 0x18 0. " UTMIP_NO_SYNC_NO_EOP ,Do not sent SYNC or EOP" "Disabled,Enabled"
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line.long 0x1C "USB3_UTMIP_MISC_CFG0_0,UTMIP miscellaneous configurations"
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bitfld.long 0x1C 27.--30. " UTMIP_DPDM_OBSERVE_SEL ,Select DP/DM obs signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 26. " UTMIP_DPDM_OBSERVE ,Use DP/DM as obs bus" "0,1"
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textline " "
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bitfld.long 0x1C 25. " UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON ,UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON" "0,1"
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bitfld.long 0x1C 24. " UTMIP_ALLOW_LS_ON_SOFT_DISCON ,UTMIP_ALLOW_LS_ON_SOFT_DISCON" "0,1"
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textline " "
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bitfld.long 0x1C 23. " UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP ,UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP" "0,1"
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bitfld.long 0x1C 22. " UTMIP_SUSPEND_EXIT_ON_EDGE ,Suspend exit requires edge or simply a value" "0,1"
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textline " "
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bitfld.long 0x1C 21. " UTMIP_LS_TO_FS_SKIP_4MS ,Don't block changes for 4ms when going from LS to FS" "0,1"
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bitfld.long 0x1C 19.--20. " UTMIP_INJECT_ERROR_TYPE ,Force error insertion into RX path" "Disabled,BIT_ERR,RX_ERR,BIT_RX_ERR"
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textline " "
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bitfld.long 0x1C 18. " UTMIP_FORCE_HS_CLOCK_ON ,Force HS clock always on" "Disabled,Enabled"
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bitfld.long 0x1C 17. " UTMIP_DISABLE_HS_TERM ,Force HS termination inactive" "Disabled,Enabled"
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textline " "
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bitfld.long 0x1C 16. " UTMIP_FORCE_HS_TERM ,Force HS termination active" "Disabled,Enabled"
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bitfld.long 0x1C 15. " UTMIP_DISABLE_PULLUP_DP ,Force DP pullup inactive" "Disabled,Enabled"
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textline " "
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bitfld.long 0x1C 14. " UTMIP_DISABLE_PULLUP_DM ,Force DM pullup inactive" "Disabled,Enabled"
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bitfld.long 0x1C 13. " UTMIP_DISABLE_PULLDN_DP ,Force DP pulldown inactive" "Disabled,Enabled"
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textline " "
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bitfld.long 0x1C 12. " UTMIP_DISABLE_PULLDN_DM ,Force DM pulldown inactive" "Disabled,Enabled"
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bitfld.long 0x1C 11. " UTMIP_FORCE_PULLUP_DP ,Force DP pullup active" "Disabled,Enabled"
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textline " "
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bitfld.long 0x1C 10. " UTMIP_FORCE_PULLUP_DM ,Force DM pullup active" "Disabled,Enabled"
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bitfld.long 0x1C 9. " UTMIP_FORCE_PULLDN_DP ,Force DP pulldown active" "Disabled,Enabled"
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textline " "
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bitfld.long 0x1C 8. " UTMIP_FORCE_PULLDN_DM ,Force DM pulldown active" "Disabled,Enabled"
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bitfld.long 0x1C 5.--7. " UTMIP_STABLE_COUNT ,Number of cycles of crystal clock of signal not changing to consider stable" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x1C 4. " UTMIP_STABLE_ALL ,Determines if all signal need to be stable to not change a config" "No,Yes"
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bitfld.long 0x1C 3. " UTMIP_NO_FREE_ON_SUSPEND ,Don't use free running terminations during suspend" "Disabled,Enabled"
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textline " "
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bitfld.long 0x1C 2. " UTMIP_NEVER_FREE_RUNNING_TERMS ,Ignore free running terminations, even when no clock" "Disabled,Enabled"
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bitfld.long 0x1C 1. " UTMIP_ALWAYS_FREE_RUNNING_TERMS ,Use free running terminations at all time" "Disabled,Enabled"
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textline " "
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bitfld.long 0x1C 0. " UTMIP_COMB_TERMS ,Use combinational terminations or synced through CLKXTAL" "Disabled,Enabled"
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line.long 0x20 "USB3_UTMIP_MISC_CFG1_0,UTMIP miscellaneous configurations"
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bitfld.long 0x20 30. " UTMIP_PHY_XTAL_CLOCKEN ,Selects whether to enable the crystal clock in the module" "Disabled,Enabled"
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bitfld.long 0x20 29. " UTMIP_LINESTATE_BYPASS ,Bypass LineState reclocking logic" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 28. " UTMIP_LINESTATE_NEG ,Use neg edge sync for linestate" "Disabled,Enabled"
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bitfld.long 0x20 27. " UTMIP_LINESTATE_XCVRSEL3 ,0 ,Use FS filtering on line state when XcvrSel=3" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 25.--26. " UTMIP_OBS_SEL ,UTMIP_OBS_SEL" "0,1,2,3"
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bitfld.long 0x20 24. " UTMIP_FSLS_TDM ,UTMIP_FSLS_TDM" "0,1"
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textline " "
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bitfld.long 0x20 23. " UTMIP_FORCE_IOBIST_CLK_ON ,UTMIP_FORCE_IOBIST_CLK_ON" "0,1"
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textline " "
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bitfld.long 0x20 5. " UTMIP_RX_ERROR_CNT_CLR ,UTMIP_RX_ERROR_CNT_CLR" "0,1"
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bitfld.long 0x20 4. " UTMIP_RX_ERROR_CNT_EN ,UTMIP_RX_ERROR_CNT_EN" "0,1"
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|
textline " "
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bitfld.long 0x20 3. " UTMIP_FLIP_FSLS_POLARITY ,UTMIP_FLIP_FSLS_POLARITY" "0,1"
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bitfld.long 0x20 2. " UTMIP_SUSPEND_TERMSEL ,UTMIP_SUSPEND_TERMSEL" "0,1"
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|
textline " "
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bitfld.long 0x20 1. " UTMIP_XCVRSEL3_1 ,EOP detection" "Enabled,Disabled"
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bitfld.long 0x20 0. " UTMIP_XCVRSEL3_0 ,UTMIP_XCVRSEL3_0" "KeepAlive,Regular"
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line.long 0x24 "USB3_UTMIP_DEBOUNCE_CFG0_0,UTMIP Avalid and Bvalid debounce"
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hexmask.long.word 0x24 16.--31. 1. " UTMIP_BIAS_DEBOUNCE_B ,Simulation value -- Used for interrupts"
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hexmask.long.word 0x24 0.--15. 1. " UTMIP_BIAS_DEBOUNCE_A ,Simulation value -- Used for interrupts"
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line.long 0x28 "USB3_UTMIP_BAT_CHRG_CFG0_0,UTMIP battery charger configuration"
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bitfld.long 0x28 8.--13. " UTMIP_CHRG_DEBOUNCE_TIMESCALE ,Debouncer time scaling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x28 5. " UTMIP_OP_I_SRC_EN ,UTMIP_OP_I_SRC_EN" "Disabled,Enabled"
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textline " "
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bitfld.long 0x28 4. " UTMIP_ON_SRC_EN ,UTMIP_ON_SRC_EN" "Disabled,Enabled"
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bitfld.long 0x28 3. " UTMIP_OP_SRC_EN ,UTMIP_OP_SRC_EN" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x28 2. " UTMIP_ON_SINK_EN ,UTMIP_ON_SINK_EN" "Disabled,Enabled"
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bitfld.long 0x28 1. " UTMIP_OP_SINK_EN ,UTMIP_OP_SINK_EN" "Disabled,Enabled"
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textline " "
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bitfld.long 0x28 0. " UTMIP_PD_CHRG ,Power down charger circuit" "0,1"
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line.long 0x2C "USB3_UTMIP_SPARE_CFG0_0,Utmip spare configuration bits"
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bitfld.long 0x2C 2. " HS_RX_LATE_SQUELCH ,Delay Squelch by 1 CLK480 cycle" "Disabled,Enabled"
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bitfld.long 0x2C 1. " HS_RX_FLUSH_ALAP ,Flush as late as possible" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x2C 0. " HS_RX_IPG_ERROR_ENABLE ,HS_RX_IPG_ERROR_ENABLE" "Disabled,Enabled"
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|
line.long 0x30 "USB3_UTMIP_XCVR_CFG1_0,UTMIP transceiver cell configuration register 1"
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bitfld.long 0x30 26.--27. " UTMIP_XCVR_RPU_RANGE_ADJ ,1.5k pull-up resistor range shift" "0,1,2,3"
|
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bitfld.long 0x30 24.--25. " UTMIP_XCVR_HS_IREF_CAP ,High-speed Iref cap control for bias current stability" "0,1,2,3"
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|
textline " "
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bitfld.long 0x30 22.--23. " UTMIP_XCVR_SPARE ,Spare bits for USB transceiver pad" "0,1,2,3"
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bitfld.long 0x30 18.--21. " UTMIP_XCVR_TERM_RANGE_ADJ ,Range adjustment on terminations" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x30 17. " UTMIP_RCTRL_SW_SET ,Use a software override on RCTRL instead of automatic bias control" "No,Yes"
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bitfld.long 0x30 12.--16. " UTMIP_RCTRL_SW_VAL ,Encoded value to use on RCTRL when software override is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
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textline " "
|
|
bitfld.long 0x30 11. " UTMIP_TCTRL_SW_SET ,Use a software override on TCTRL instead of automatic bias control" "No,Yes"
|
|
bitfld.long 0x30 6.--10. " UTMIP_TCTRL_SW_VAL ,Encoded value to use on TCTRL when software override is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
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textline " "
|
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bitfld.long 0x30 5. " UTMIP_FORCE_PDDR_POWERUP ,Force PDDR input into power up" "Not forced,Forced"
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bitfld.long 0x30 4. " UTMIP_FORCE_PDDR_POWERDOWN ,Force PDDR input input into power down" "Not forced,Forced"
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|
textline " "
|
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bitfld.long 0x30 3. " UTMIP_FORCE_PDCHRP_POWERUP ,Force PDCHRP input into power up" "Not forced,Forced"
|
|
bitfld.long 0x30 2. " UTMIP_FORCE_PDCHRP_POWERDOWN ,Force PDCHRP input input into power down" "Not forced,Forced"
|
|
textline " "
|
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bitfld.long 0x30 1. " UTMIP_FORCE_PDDISC_POWERUP ,Force PDDISC input into power up" "Not forced,Forced"
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bitfld.long 0x30 0. " UTMIP_FORCE_PDDISC_POWERDOWN ,Force PDDISC input into power down" "Not forced,Forced"
|
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line.long 0x34 "USB3_UTMIP_BIAS_CFG1_0,UTMIP Bias cell configuration register 1"
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bitfld.long 0x34 8.--13. " UTMIP_BIAS_DEBOUNCE_TIMESCALE ,Debouncer time scaling - factor-1 to slow down debouncing by" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
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bitfld.long 0x34 3.--7. " UTMIP_BIAS_PDTRK_COUNT ,Control the BIAS cell power down lag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x34 1. " UTMIP_FORCE_PDTRK_POWERUP ,Force PDTRK input into power up" "Disabled,Enabled"
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bitfld.long 0x34 0. " UTMIP_FORCE_PDTRK_POWERDOWN ,Force PDTRK input into power down" "Disabled,Enabled"
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rgroup.long 0x840++0x03
|
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line.long 0x00 "USB3_UTMIP_BIAS_STS0_0,UTMIP Bias cell status register 0"
|
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hexmask.long.word 0x00 16.--31. 1. " UTMIP_TCTRL ,Thermal encoding output from USB bias pad"
|
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hexmask.long.word 0x00 0.--15. 1. " UTMIP_RCTRL ,Thermal encoding output from USB bias pad"
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group.long 0x844++0x03
|
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line.long 0x00 "USB3_UTMIP_CHRG_DEB_CFG0_0,UTMIP VDcd_Det and VDat_Det debounce"
|
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hexmask.long.word 0x00 16.--31. 1. " UTMIP_CHRG_DEBOUNCE_PERIOD_B ,Simulation value -- Used for interrupts"
|
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hexmask.long.word 0x00 0.--15. 1. " UTMIP_CHRG_DEBOUNCE_PERIOD_A ,Simulation value -- Used for interrupts"
|
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rgroup.long 0x848++0x03
|
|
line.long 0x00 "USB3_UTMIP_PMC_WAKEUP0_0,UTMIP PMC Wakeup value"
|
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bitfld.long 0x00 21. " UTMIP_FS_DRV_EN ,Indicates when the controller is driving on the bus" "Disabled,Enabled"
|
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hexmask.long.tbyte 0x00 0.--20. 1. " UTMIP_SPARE_FUSES ,Spare Fuses value, to keep the connections preserved"
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group.long 0x84C++0x03
|
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line.long 0x00 "USB3_UTMIP_PMC_WAKEUP0_0,UTMIP PMC Wakeup value"
|
|
rbitfld.long 0x00 1. " UTMIP_LINE_WAKEUP_EVENT_INT_STS ,Indicates the status of the pmc wakeup event" "No wakeup,Wakeup"
|
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bitfld.long 0x00 0. " UTMIP_LINE_WAKEUP_EVENT_INT_ENB ,Interrupt mask for the pmc wakeup event" "Disabled,Enabled"
|
|
width 30.
|
|
tree "Endpoint Queue Head"
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group.long 0x1000++0x03
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line.long 0x00 "USB3_QH_USB2D_QH_EP_0_OUT_0,USB2D Queue Head for OUT endpoint 0"
|
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group.long (0x1000+0x40)++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_0_IN_0,USB2D Queue Head for IN endpoint 0"
|
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group.long 0x1080++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_1_OUT_0,USB2D Queue Head for OUT endpoint 1"
|
|
group.long (0x1080+0x40)++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_1_IN_0,USB2D Queue Head for IN endpoint 1"
|
|
group.long 0x1100++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_2_OUT_0,USB2D Queue Head for OUT endpoint 2"
|
|
group.long (0x1100+0x40)++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_2_IN_0,USB2D Queue Head for IN endpoint 2"
|
|
group.long 0x1180++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_3_OUT_0,USB2D Queue Head for OUT endpoint 3"
|
|
group.long (0x1180+0x40)++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_3_IN_0,USB2D Queue Head for IN endpoint 3"
|
|
group.long 0x1200++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_4_OUT_0,USB2D Queue Head for OUT endpoint 4"
|
|
group.long (0x1200+0x40)++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_4_IN_0,USB2D Queue Head for IN endpoint 4"
|
|
group.long 0x1280++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_5_OUT_0,USB2D Queue Head for OUT endpoint 5"
|
|
group.long (0x1280+0x40)++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_5_IN_0,USB2D Queue Head for IN endpoint 5"
|
|
group.long 0x1300++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_6_OUT_0,USB2D Queue Head for OUT endpoint 6"
|
|
group.long (0x1300+0x40)++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_6_IN_0,USB2D Queue Head for IN endpoint 6"
|
|
group.long 0x1380++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_7_OUT_0,USB2D Queue Head for OUT endpoint 7"
|
|
group.long (0x1380+0x40)++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_7_IN_0,USB2D Queue Head for IN endpoint 7"
|
|
group.long 0x1400++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_8_OUT_0,USB2D Queue Head for OUT endpoint 8"
|
|
group.long (0x1400+0x40)++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_8_IN_0,USB2D Queue Head for IN endpoint 8"
|
|
group.long 0x1480++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_9_OUT_0,USB2D Queue Head for OUT endpoint 9"
|
|
group.long (0x1480+0x40)++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_9_IN_0,USB2D Queue Head for IN endpoint 9"
|
|
group.long 0x1500++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_10_OUT_0,USB2D Queue Head for OUT endpoint 10"
|
|
group.long (0x1500+0x40)++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_10_IN_0,USB2D Queue Head for IN endpoint 10"
|
|
group.long 0x1580++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_11_OUT_0,USB2D Queue Head for OUT endpoint 11"
|
|
group.long (0x1580+0x40)++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_11_IN_0,USB2D Queue Head for IN endpoint 11"
|
|
group.long 0x1600++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_12_OUT_0,USB2D Queue Head for OUT endpoint 12"
|
|
group.long (0x1600+0x40)++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_12_IN_0,USB2D Queue Head for IN endpoint 12"
|
|
group.long 0x1680++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_13_OUT_0,USB2D Queue Head for OUT endpoint 13"
|
|
group.long (0x1680+0x40)++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_13_IN_0,USB2D Queue Head for IN endpoint 13"
|
|
group.long 0x1700++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_14_OUT_0,USB2D Queue Head for OUT endpoint 14"
|
|
group.long (0x1700+0x40)++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_14_IN_0,USB2D Queue Head for IN endpoint 14"
|
|
group.long 0x1780++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_15_OUT_0,USB2D Queue Head for OUT endpoint 15"
|
|
group.long (0x1780+0x40)++0x03
|
|
line.long 0x00 "USB3_QH_USB2D_QH_EP_15_IN_0,USB2D Queue Head for IN endpoint 15"
|
|
tree.end
|
|
tree.end
|
|
width 19.
|
|
tree "UHSIC Configuration"
|
|
group.long 0xc04++0x0F
|
|
line.long 0x00 "UHSIC_PLL_CFG1_0,UHSIC PLL and PLLU Configuration Register 1"
|
|
bitfld.long 0x00 14.--18. " PLLU_ENABLE_DLY_COUNT ,PLLU ENABLE DLY COUNT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13. " FORCE_PLLU_POWERUP ,FORCE PLLU POWERUP" "0,1"
|
|
bitfld.long 0x00 12. " FORCE_PLLU_POWERDOWN ,FORCE PLLU POWERDOWN" "0,1"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " XTAL_FREQ_COUNT ,XTAL FREQ COUNT"
|
|
line.long 0x04 "UHSIC_HSRX_CFG0_0,UHSIC High Speed Receive Config 0"
|
|
bitfld.long 0x04 18. " NO_STRIPPING ,Do not strip incoming data" "0,1"
|
|
bitfld.long 0x04 13.--17. " IDLE_WAIT ,Number of idle cycles to declare IDLE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 8.--12. " ELASTIC_OVERRUN_LIMIT ,ELASTIC OVERRUN LIMIT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ELASTIC_OVERRUN_DISABLE ,Do not declare overrun errors until overflow of FIFO" "0,1"
|
|
bitfld.long 0x04 2.--6. " ELASTIC_UNDERRUN_LIMIT ,ELASTIC UNDERRUN LIMIT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 1. " ELASTIC_UNDERRUN_DISABLE ,Do not declare underrun errors" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PASS_FEEDBACK ,Pass through the feedback do not block it" "0,1"
|
|
line.long 0x08 "UHSIC_HSRX_CFG1_0,UHSIC High Speed Receive Config 1"
|
|
bitfld.long 0x08 20.--23. " TX_BLOCK_CNT ,Controls how long after the end of transmission the receive path is blocked" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 14.--19. " RX_STROBE_DLY_TRIMMER ,Number of delays cells between UH_RX_STROBE and RxStrobeClk in zero cycle path" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 9.--13. " INPUT_FIFO_DEPTH ,Depth of the 2-bit wide input FIFO and maximum depth is 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 8. " LINE_STATE_RESUME_FAKE_SE0 ,When enabled send an SE0 for 2 LS symbols at the end of ResumeK" "0,1"
|
|
bitfld.long 0x08 7. " LINE_STATE_BYPASS ,Bypass Line State reclocking logic" "0,1"
|
|
bitfld.long 0x08 6. " EARLY_LINE_STATE_FILTER ,Assumes line state filtering table is inclusive not exclusive" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 1.--5. " HS_SYNC_START_DLY ,How long to wait before start of sync launches RxActive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 0. " HS_ALLOW_KEEP_ALIVE ,Allow Keep Alive packets" "0,1"
|
|
line.long 0x0C "UHSIC_TX_CFG0_0,UHSIC Transmit Config Signals"
|
|
bitfld.long 0x0C 9. " HS_READY_WAIT_FOR_VALID ,HS READY WAIT FOR VALID" "0,1"
|
|
bitfld.long 0x0C 8. " PACKET_INVERT_DATA ,Invert data during a regular packet" "0,1"
|
|
bitfld.long 0x0C 7. " PACKET_FORCE_STROBE_LOW ,Force STROBE low during a regular instead of toggling it" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " HS_POSTAMBLE_OUTPUT_ENABLE ,Output enable turns off 1 cycle after" "0,1"
|
|
bitfld.long 0x0C 5. " SIE_RESUME_ON_LINESTATE , SIE not macrocell detects Line State change to resume" "0,1"
|
|
bitfld.long 0x0C 4. " SOF_ON_NO_STUFF ,SOF when OpMode 3 perhaps when the sending controller made packets" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " SOF_ON_NO_ENCODE ,SOF when OpMode 2 not likely for Chirp" "0,1"
|
|
bitfld.long 0x0C 2. " NO_STUFFING ,No bit stuffing static programming" "0,1"
|
|
bitfld.long 0x0C 1. " NO_ENCODING ,No encoding static programming" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " NO_SYNC_NO_EOP ,Do not send SYNC or EOP" "0,1"
|
|
textline " "
|
|
width 19.
|
|
if (((d.l(ad:0x7D008000+0xc14))&0x8000)==0x8000)
|
|
// XCVR_MODE == 1
|
|
group.long 0xc14++0x03
|
|
line.long 0x00 "UHSIC_MISC_CFG0_0,UHSIC Miscellaneous Configurations"
|
|
bitfld.long 0x00 20. " DISABLE_BUSRESET ,PHY send out BusReset during XcvrSelect0 TermSelect0 and Opmode2" "Send,Not Send"
|
|
bitfld.long 0x00 19. " FORCE_TERMSEL ,Value to be forced on TermSelect when FORCE_XCVR_MODE is set" "0,1"
|
|
bitfld.long 0x00 18. " EXTEND_BK_ACTIVE ,Drive the bus keeper one cycle longer when going out of IDLE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FORCE_XCVRSEL ,Value to be forced on XcvrSelect when FORCE_XCVR_MODE is set" "0,1,2,3"
|
|
bitfld.long 0x00 15. " FORCE_XCVR_MODE ,Force the values of XcvrSelect and TermSelect via config bits instead of via the controller" "0,1"
|
|
bitfld.long 0x00 14. " SYMMETRIC_CONNECT_DATA ,DATA goes high before STROBE goes low and goes low before/after STROBE goes high" "Before,After"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASYNC_CONNECT_DATA ,Asynch connect Data behaviour" "Keeps setup,Moves with STROBE"
|
|
bitfld.long 0x00 12. " LONG_CONNECT_STROBE ,STROBE periods long during connect" "2,3"
|
|
bitfld.long 0x00 11. " ACTIVE_BK_DRIVE_RX ,Use RX state to determine starting time to drive bus keeper instead of waiting for IDLE detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ACTIVE_BK_DRIVE_TX ,Use TX state to determine starting time to drive bus keeper instead of waiting for IDLE detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DETECT_SHORT_IDLE ,Edges (negative and positive) to detect an idle state on the line" "3 edges,4 edges"
|
|
bitfld.long 0x00 8. " DETECT_SHORT_CONNECT ,Edges (negative and positive) to detect a connect state on the line" "3 edges,4 edges"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUSPEND_EXIT_ON_EDGE ,Suspend exit requires edge or simply a value" "0,1"
|
|
bitfld.long 0x00 5.--6. " INJECT_ERROR_TYPE ,Force error insertion into RX path" "Disabled,Bit error,Rx Error,Bit Rx error"
|
|
bitfld.long 0x00 2.--4. " STABLE_COUNT ,Number of crystal clock cycles of signal not changing to consider stable" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STABLE_ALL ,Determines if all signals need to be stable to not change a config" "0,1"
|
|
bitfld.long 0x00 0. " COMB_TERMS ,Use combinational terminations or synced through CLKXTAL" "0,1"
|
|
else
|
|
group.long 0xc14++0x03
|
|
line.long 0x00 "UHSIC_MISC_CFG0_0,UHSIC Miscellaneous Configurations"
|
|
bitfld.long 0x00 20. " DISABLE_BUSRESET ,PHY send out BusReset during XcvrSelect0 TermSelect0 and Opmode2" "Send,Not Send"
|
|
bitfld.long 0x00 18. " EXTEND_BK_ACTIVE ,Drive the bus keeper one cycle longer when going out of IDLE" "0,1"
|
|
bitfld.long 0x00 15. " FORCE_XCVR_MODE ,Force the values of XcvrSelect and TermSelect via config bits instead of via the controller" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SYMMETRIC_CONNECT_DATA ,DATA goes high before STROBE goes low and goes low before/after STROBE goes high" "Before,After"
|
|
bitfld.long 0x00 13. " ASYNC_CONNECT_DATA ,Asynch connect Data behaviour" "Keeps setup,Moves with STROBE"
|
|
bitfld.long 0x00 12. " LONG_CONNECT_STROBE ,STROBE periods long during connect" "2,3"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ACTIVE_BK_DRIVE_RX ,Use RX state to determine starting time to drive bus keeper instead of waiting for IDLE detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ACTIVE_BK_DRIVE_TX ,Use TX state to determine starting time to drive bus keeper instead of waiting for IDLE detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DETECT_SHORT_IDLE ,Edges (negative and positive) to detect an idle state on the line" "3 edges,4 edges"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DETECT_SHORT_CONNECT ,Edges (negative and positive) to detect a connect state on the line" "3 edges,4 edges"
|
|
bitfld.long 0x00 7. " SUSPEND_EXIT_ON_EDGE ,Suspend exit requires edge or simply a value" "0,1"
|
|
bitfld.long 0x00 5.--6. " INJECT_ERROR_TYPE ,Force error insertion into RX path" "Disabled,Bit error,Rx Error,Bit Rx error"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " STABLE_COUNT ,Number of crystal clock cycles of signal not changing to consider stable" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " STABLE_ALL ,Determines if all signals need to be stable to not change a config" "0,1"
|
|
bitfld.long 0x00 0. " COMB_TERMS ,Use combinational terminations or synced through CLKXTAL" "0,1"
|
|
endif
|
|
textline " "
|
|
group.long 0xC18++0x17
|
|
line.long 0x00 "UHSIC_MISC_CFG1_0,UHSIC Miscellaneous Configurations"
|
|
bitfld.long 0x00 17. " PHY_XTAL_CLOCKEN ,Selects whether to enable the crystal clock in the module" "Disabled,Enabled"
|
|
bitfld.long 0x00 15.--16. " OBS_SEL ,Select which one of 4 observation vectors is presented on the observation bus" "0,1,2,3"
|
|
bitfld.long 0x00 14. " FORCE_IOBIST_CLK_ON ,Always enable IoBist CLK60" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--13. 1. " PLLU_STABLE_COUNT ,PLLU frequency lock delay"
|
|
bitfld.long 0x00 1. " RX_ERROR_CNT_CLR ,Clear IOBST RxError counter" "Not clear,Clear"
|
|
bitfld.long 0x00 0. " RX_ERROR_CNT_EN ,Enable IOBIST RxError counter when not in IOBIST mode" "Disabled,Enabled"
|
|
line.long 0x04 "UHSIC_PADS_CFG0_0,UHSIC Pads Settings"
|
|
hexmask.long.byte 0x04 24.--31. 1. " HSIC_OPT ,Spare config bits"
|
|
bitfld.long 0x04 20.--23. " TX_SLEWN ,Output slew rate (fall time) adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " TX_SLEWP ,Output slew rate (rise time) adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " TX_RTUNEN ,Fine-tuned 50 Ohm termination resistor for NMOS driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " TX_RTUNEP ,Fine-tuned 50 Ohm termination resistor for PMOS driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " TX_RTERMN ,Output impedance adjustment for NMOS driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " TX_RTERMP ,Output impedance adjustment for PMOS driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "UHSIC_PADS_CFG1_0,UHSIC Pads Settings"
|
|
bitfld.long 0x08 12. " RPU_STROBE ,Enable pull up on IO_STROBE" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " RPU_DATA ,Enable pull up on IO_DATA" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " RPD_STROBE ,Enable pull down on IO_STROBE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " RPD_DATA ,Enable pull down on IO_DATA" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " LPBK ,Internal digital loopback" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " RX_SEL ,RX buffer Select" "Differential read,Single-ended"
|
|
textline " "
|
|
bitfld.long 0x08 6. " PD_ZI ,Power down single ended receiver" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " PD_RX ,Power down receiver" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " PD_TRK ,Power down tracking circuit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PD_TX ,Power down transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PD_BG ,Power down band-gap and bias generator" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " IDDQ ,Shut down analog blocks for IDDQ testing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " AUTO_RTERM_EN ,Enable auto-termination" "Disabled,Enabled"
|
|
line.long 0x0C "UHSIC_CMD_CFG0_0,UHSIC CMD CFG0 0"
|
|
bitfld.long 0x0C 6. " FORCE_ACTIVATED ,Force PHY into activated state without connect handshake" "Not activated,Activated"
|
|
bitfld.long 0x0C 5. " PRETEND_CONNECT_DETECT ,While in HOST mode act as if the input stage has seen a CONNECT pulse from the external PHY" "Not detected,Detected"
|
|
bitfld.long 0x0C 4. " FORCE_RESET ,While in HOST mode force global state machine into RESET state" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " FORCE_CONNECT ,Upon rising value of this bit force device to send connect" "No connected,Connected"
|
|
bitfld.long 0x0C 2. " AUTO_CONNECT ,As device automatically send Connect during activation" "No,Yes"
|
|
bitfld.long 0x0C 1. " FORCE_ACTIVATE ,Upon rising value of this bit instruct state machine to go into activation mode" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " AUTO_ACTIVATE ,Upon power up automatically move to activation mode and start going through connect procedure" "No,Yes"
|
|
line.long 0x10 "UHSIC_STAT_CFG0_0,UHSIC STAT CFG0 0"
|
|
hexmask.long.word 0x10 16.--31. 1. " CALIOUT ,CALIOUT"
|
|
hexmask.long.byte 0x10 8.--15. 1. " SPARE_STATUS ,SPARE STATUS"
|
|
rbitfld.long 0x10 1.--2. " BUS_STATE ,BUS STATE" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CONNECT_DETECT ,CONNECT DETECT" "No connected,Connected"
|
|
line.long 0x14 "UHSIC_SPARE_CFG0_0,UTMIP Spare Configurations"
|
|
textline " "
|
|
width 26.
|
|
rgroup.long 0xc30++0x03
|
|
line.long 0x00 "USB2_UHSIC_MISC_STS0_0,UHSIC SPARE Fuse Value"
|
|
bitfld.long 0x00 0. " UHSIC_TX_HS_VLD ,Indicates when the controller is driving on the bus" "0,1"
|
|
group.long 0xc34++0x03
|
|
line.long 0x00 "USB2_UHSIC_PMC_WAKEUP0_0,UHSIC PMC Wakeup Value"
|
|
rbitfld.long 0x00 1. " UHSIC_LINE_WAKEUP_EVENT_INT_STS ,Indicates the status of the PMC wakeup event" "0,1"
|
|
bitfld.long 0x00 0. " UHSIC_LINE_WAKEUP_EVENT_INT_ENB ,Interrupt mask for the PMC wakeup even" "No interrupt,Interrupt"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "USB (3.0)"
|
|
tree "XUSB HOST (IPFS) Registers"
|
|
base ad:0x70090000
|
|
width 19.
|
|
tree "Vectors"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "AXI_BAR0_SZ_0,The Size Of The Address Range Associated With BAR0"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR0_SIZE ,The size of the address range associated with BAR0 in 4K increments"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "AXI_BAR1_SZ_0,The Size Of The Address Range Associated With BAR1"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR1_SIZE ,The size of the address range associated with BAR1 in 4K increments"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "AXI_BAR2_SZ_0,The Size Of The Address Range Associated With BAR2"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR2_SIZE ,The size of the address range associated with BAR2 in 4K increments"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "AXI_BAR3_SZ_0,The Size Of The Address Range Associated With BAR3"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR3_SIZE ,The size of the address range associated with BAR3 in 4K increments"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "AXI_BAR0_START_0,The Start Of AXI Address Space For BAR0"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR0_START ,The start of the AXI address space for BAR0"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "AXI_BAR1_START_0,The Start Of AXI Address Space For BAR1"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR1_START ,The start of the AXI address space for BAR1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "AXI_BAR2_START_0,The Start Of AXI Address Space For BAR2"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR2_START ,The start of the AXI address space for BAR2"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "AXI_BAR3_START_0,The Start Of AXI Address Space For BAR3"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR3_START ,The start of the AXI address space for BAR3"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FPCI_BAR0_0,FPCI BAR0"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR0_START ,The start of FPCI address space mapped into the BAR0 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR0_ACCESS_TYPE ,Address region access type" "Memory-mapped,I/O or config"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FPCI_BAR1_0,FPCI BAR1"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR1_START ,The start of FPCI address space mapped into the BAR1 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR1_ACCESS_TYPE ,Address region access type" "Memory-mapped,I/O or config"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FPCI_BAR2_0,FPCI BAR2"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR2_START ,The start of FPCI address space mapped into the BAR2 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR2_ACCESS_TYPE ,Address region access type" "Memory-mapped,I/O or config"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "FPCI_BAR3_0,FPCI BAR3"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR3_START ,The start of FPCI address space mapped into the BAR3 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR3_ACCESS_TYPE ,Address region access type" "Memory-mapped,I/O or config"
|
|
group.long 0xC0++0x0B
|
|
line.long 0x00 "MSI_BAR_SZ_0,MSI BAR Size"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " MSI_BAR_SIZE ,The size of the address range associated with MSI BAR is in 4K increments"
|
|
line.long 0x04 "MSI_AXI_BAR_ST_0,MSI AXI BAR Start"
|
|
hexmask.long.tbyte 0x04 12.--31. 0x10 " MSI_AXI_BAR_START ,The start of the upstream AXI address space for MSI BAR"
|
|
line.long 0x08 "MSI_FPCI_BAR_ST_0,MSI FPCI BAR Start"
|
|
hexmask.long 0x08 4.--31. 0x10 " MSI_FPCI_BAR_START ,The start of the upstream FPCI address space for MSI BAR"
|
|
tree.end
|
|
width 12.
|
|
tree "MSI Vector registers"
|
|
width 12.
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "MSI_VEC0_0,XUSB_HOST MSI Vector Register 0"
|
|
eventfld.long 0x00 31. " MSI_VECTOR[31] ,MSI vector 31" "No MSI,MSI sent"
|
|
eventfld.long 0x00 30. " [30] ,MSI vector 30" "No MSI,MSI sent"
|
|
eventfld.long 0x00 29. " [29] ,MSI vector 29" "No MSI,MSI sent"
|
|
eventfld.long 0x00 28. " [28] ,MSI vector 28" "No MSI,MSI sent"
|
|
eventfld.long 0x00 27. " [27] ,MSI vector 27" "No MSI,MSI sent"
|
|
eventfld.long 0x00 26. " [26] ,MSI vector 26" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x00 25. " [25] ,MSI vector 25" "No MSI,MSI sent"
|
|
eventfld.long 0x00 24. " [24] ,MSI vector 24" "No MSI,MSI sent"
|
|
eventfld.long 0x00 23. " [23] ,MSI vector 23" "No MSI,MSI sent"
|
|
eventfld.long 0x00 22. " [22] ,MSI vector 22" "No MSI,MSI sent"
|
|
eventfld.long 0x00 21. " [21] ,MSI vector 21" "No MSI,MSI sent"
|
|
eventfld.long 0x00 20. " [20] ,MSI vector 20" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x00 19. " [19] ,MSI vector 19" "No MSI,MSI sent"
|
|
eventfld.long 0x00 18. " [18] ,MSI vector 18" "No MSI,MSI sent"
|
|
eventfld.long 0x00 17. " [17] ,MSI vector 17" "No MSI,MSI sent"
|
|
eventfld.long 0x00 16. " [16] ,MSI vector 16" "No MSI,MSI sent"
|
|
eventfld.long 0x00 15. " [15] ,MSI vector 15" "No MSI,MSI sent"
|
|
eventfld.long 0x00 14. " [14] ,MSI vector 14" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x00 13. " [13] ,MSI vector 13" "No MSI,MSI sent"
|
|
eventfld.long 0x00 12. " [12] ,MSI vector 12" "No MSI,MSI sent"
|
|
eventfld.long 0x00 11. " [11] ,MSI vector 11" "No MSI,MSI sent"
|
|
eventfld.long 0x00 10. " [10] ,MSI vector 10" "No MSI,MSI sent"
|
|
eventfld.long 0x00 9. " [9] ,MSI vector 9" "No MSI,MSI sent"
|
|
eventfld.long 0x00 8. " [8] ,MSI vector 8" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x00 7. " [7] ,MSI vector 7" "No MSI,MSI sent"
|
|
eventfld.long 0x00 6. " [6] ,MSI vector 6" "No MSI,MSI sent"
|
|
eventfld.long 0x00 5. " [5] ,MSI vector 5" "No MSI,MSI sent"
|
|
eventfld.long 0x00 4. " [4] ,MSI vector 4" "No MSI,MSI sent"
|
|
eventfld.long 0x00 3. " [3] ,MSI vector 3" "No MSI,MSI sent"
|
|
eventfld.long 0x00 2. " [2] ,MSI vector 2" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x00 1. " [1] ,MSI vector 1" "No MSI,MSI sent"
|
|
eventfld.long 0x00 0. " [0] ,MSI vector 0" "No MSI,MSI sent"
|
|
line.long 0x04 "MSI_VEC1_0,XUSB_HOST MSI Vector Register 1"
|
|
eventfld.long 0x04 31. " MSI_VECTOR[63] ,MSI vector 63" "No MSI,MSI sent"
|
|
eventfld.long 0x04 30. " [62] ,MSI vector 62" "No MSI,MSI sent"
|
|
eventfld.long 0x04 29. " [61] ,MSI vector 61" "No MSI,MSI sent"
|
|
eventfld.long 0x04 28. " [60] ,MSI vector 60" "No MSI,MSI sent"
|
|
eventfld.long 0x04 27. " [59] ,MSI vector 59" "No MSI,MSI sent"
|
|
eventfld.long 0x04 26. " [58] ,MSI vector 58" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x04 25. " [57] ,MSI vector 57" "No MSI,MSI sent"
|
|
eventfld.long 0x04 24. " [56] ,MSI vector 56" "No MSI,MSI sent"
|
|
eventfld.long 0x04 23. " [55] ,MSI vector 55" "No MSI,MSI sent"
|
|
eventfld.long 0x04 22. " [54] ,MSI vector 54" "No MSI,MSI sent"
|
|
eventfld.long 0x04 21. " [53] ,MSI vector 53" "No MSI,MSI sent"
|
|
eventfld.long 0x04 20. " [52] ,MSI vector 52" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x04 19. " [51] ,MSI vector 51" "No MSI,MSI sent"
|
|
eventfld.long 0x04 18. " [50] ,MSI vector 50" "No MSI,MSI sent"
|
|
eventfld.long 0x04 17. " [49] ,MSI vector 49" "No MSI,MSI sent"
|
|
eventfld.long 0x04 16. " [48] ,MSI vector 48" "No MSI,MSI sent"
|
|
eventfld.long 0x04 15. " [47] ,MSI vector 47" "No MSI,MSI sent"
|
|
eventfld.long 0x04 14. " [46] ,MSI vector 46" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x04 13. " [45] ,MSI vector 45" "No MSI,MSI sent"
|
|
eventfld.long 0x04 12. " [44] ,MSI vector 44" "No MSI,MSI sent"
|
|
eventfld.long 0x04 11. " [43] ,MSI vector 43" "No MSI,MSI sent"
|
|
eventfld.long 0x04 10. " [42] ,MSI vector 42" "No MSI,MSI sent"
|
|
eventfld.long 0x04 9. " [41] ,MSI vector 41" "No MSI,MSI sent"
|
|
eventfld.long 0x04 8. " [40] ,MSI vector 40" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x04 7. " [39] ,MSI vector 39" "No MSI,MSI sent"
|
|
eventfld.long 0x04 6. " [38] ,MSI vector 38" "No MSI,MSI sent"
|
|
eventfld.long 0x04 5. " [37] ,MSI vector 37" "No MSI,MSI sent"
|
|
eventfld.long 0x04 4. " [36] ,MSI vector 36" "No MSI,MSI sent"
|
|
eventfld.long 0x04 3. " [35] ,MSI vector 35" "No MSI,MSI sent"
|
|
eventfld.long 0x04 2. " [34] ,MSI vector 34" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x04 1. " [33] ,MSI vector 33" "No MSI,MSI sent"
|
|
eventfld.long 0x04 0. " [32] ,MSI vector 32" "No MSI,MSI sent"
|
|
line.long 0x08 "MSI_VEC2_0,XUSB_HOST MSI Vector Register 2"
|
|
eventfld.long 0x08 31. " MSI_VECTOR[95] ,MSI vector 95" "No MSI,MSI sent"
|
|
eventfld.long 0x08 30. " [94] ,MSI vector 94" "No MSI,MSI sent"
|
|
eventfld.long 0x08 29. " [93] ,MSI vector 93" "No MSI,MSI sent"
|
|
eventfld.long 0x08 28. " [92] ,MSI vector 92" "No MSI,MSI sent"
|
|
eventfld.long 0x08 27. " [91] ,MSI vector 91" "No MSI,MSI sent"
|
|
eventfld.long 0x08 26. " [90] ,MSI vector 90" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x08 25. " [89] ,MSI vector 89" "No MSI,MSI sent"
|
|
eventfld.long 0x08 24. " [88] ,MSI vector 88" "No MSI,MSI sent"
|
|
eventfld.long 0x08 23. " [87] ,MSI vector 87" "No MSI,MSI sent"
|
|
eventfld.long 0x08 22. " [86] ,MSI vector 86" "No MSI,MSI sent"
|
|
eventfld.long 0x08 21. " [85] ,MSI vector 85" "No MSI,MSI sent"
|
|
eventfld.long 0x08 20. " [84] ,MSI vector 84" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x08 19. " [83] ,MSI vector 83" "No MSI,MSI sent"
|
|
eventfld.long 0x08 18. " [82] ,MSI vector 82" "No MSI,MSI sent"
|
|
eventfld.long 0x08 17. " [81] ,MSI vector 81" "No MSI,MSI sent"
|
|
eventfld.long 0x08 16. " [80] ,MSI vector 80" "No MSI,MSI sent"
|
|
eventfld.long 0x08 15. " [79] ,MSI vector 79" "No MSI,MSI sent"
|
|
eventfld.long 0x08 14. " [78] ,MSI vector 78" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x08 13. " [77] ,MSI vector 77" "No MSI,MSI sent"
|
|
eventfld.long 0x08 12. " [76] ,MSI vector 76" "No MSI,MSI sent"
|
|
eventfld.long 0x08 11. " [75] ,MSI vector 75" "No MSI,MSI sent"
|
|
eventfld.long 0x08 10. " [74] ,MSI vector 74" "No MSI,MSI sent"
|
|
eventfld.long 0x08 9. " [73] ,MSI vector 73" "No MSI,MSI sent"
|
|
eventfld.long 0x08 8. " [72] ,MSI vector 72" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x08 7. " [71] ,MSI vector 71" "No MSI,MSI sent"
|
|
eventfld.long 0x08 6. " [70] ,MSI vector 70" "No MSI,MSI sent"
|
|
eventfld.long 0x08 5. " [69] ,MSI vector 69" "No MSI,MSI sent"
|
|
eventfld.long 0x08 4. " [68] ,MSI vector 68" "No MSI,MSI sent"
|
|
eventfld.long 0x08 3. " [67] ,MSI vector 67" "No MSI,MSI sent"
|
|
eventfld.long 0x08 2. " [66] ,MSI vector 66" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x08 1. " [65] ,MSI vector 65" "No MSI,MSI sent"
|
|
eventfld.long 0x08 0. " [64] ,MSI vector 64" "No MSI,MSI sent"
|
|
line.long 0x0C "MSI_VEC3_0,XUSB_HOST MSI Vector Register 3"
|
|
eventfld.long 0x0C 31. " MSI_VECTOR[127] ,MSI vector 127" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 30. " [126] ,MSI vector 126" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 29. " [125] ,MSI vector 125" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 28. " [124] ,MSI vector 124" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 27. " [123] ,MSI vector 123" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 26. " [122] ,MSI vector 122" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " [121] ,MSI vector 121" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 24. " [120] ,MSI vector 120" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 23. " [119] ,MSI vector 119" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 22. " [118] ,MSI vector 118" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 21. " [117] ,MSI vector 117" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 20. " [116] ,MSI vector 116" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " [115] ,MSI vector 115" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 18. " [114] ,MSI vector 114" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 17. " [113] ,MSI vector 113" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 16. " [112] ,MSI vector 112" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 15. " [111] ,MSI vector 111" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 14. " [110] ,MSI vector 110" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x0C 13. " [109] ,MSI vector 109" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 12. " [108] ,MSI vector 108" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 11. " [107] ,MSI vector 107" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 10. " [106] ,MSI vector 106" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 9. " [105] ,MSI vector 105" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 8. " [104] ,MSI vector 104" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " [103] ,MSI vector 103" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 6. " [102] ,MSI vector 102" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 5. " [101] ,MSI vector 101" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 4. " [100] ,MSI vector 100" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 3. " [99] ,MSI vector 99" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 2. " [98] ,MSI vector 98" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " [97] ,MSI vector 97" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 0. " [96] ,MSI vector 96" "No MSI,MSI sent"
|
|
line.long 0x10 "MSI_VEC4_0,XUSB_HOST MSI Vector Register 4"
|
|
eventfld.long 0x10 31. " MSI_VECTOR[159] ,MSI vector 159" "No MSI,MSI sent"
|
|
eventfld.long 0x10 30. " [158] ,MSI vector 158" "No MSI,MSI sent"
|
|
eventfld.long 0x10 29. " [157] ,MSI vector 157" "No MSI,MSI sent"
|
|
eventfld.long 0x10 28. " [156] ,MSI vector 156" "No MSI,MSI sent"
|
|
eventfld.long 0x10 27. " [155] ,MSI vector 155" "No MSI,MSI sent"
|
|
eventfld.long 0x10 26. " [154] ,MSI vector 154" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x10 25. " [153] ,MSI vector 153" "No MSI,MSI sent"
|
|
eventfld.long 0x10 24. " [152] ,MSI vector 152" "No MSI,MSI sent"
|
|
eventfld.long 0x10 23. " [151] ,MSI vector 151" "No MSI,MSI sent"
|
|
eventfld.long 0x10 22. " [150] ,MSI vector 150" "No MSI,MSI sent"
|
|
eventfld.long 0x10 21. " [149] ,MSI vector 149" "No MSI,MSI sent"
|
|
eventfld.long 0x10 20. " [148] ,MSI vector 148" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x10 19. " [147] ,MSI vector 147" "No MSI,MSI sent"
|
|
eventfld.long 0x10 18. " [146] ,MSI vector 146" "No MSI,MSI sent"
|
|
eventfld.long 0x10 17. " [145] ,MSI vector 145" "No MSI,MSI sent"
|
|
eventfld.long 0x10 16. " [144] ,MSI vector 144" "No MSI,MSI sent"
|
|
eventfld.long 0x10 15. " [143] ,MSI vector 143" "No MSI,MSI sent"
|
|
eventfld.long 0x10 14. " [142] ,MSI vector 142" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x10 13. " [141] ,MSI vector 141" "No MSI,MSI sent"
|
|
eventfld.long 0x10 12. " [140] ,MSI vector 140" "No MSI,MSI sent"
|
|
eventfld.long 0x10 11. " [139] ,MSI vector 139" "No MSI,MSI sent"
|
|
eventfld.long 0x10 10. " [138] ,MSI vector 138" "No MSI,MSI sent"
|
|
eventfld.long 0x10 9. " [137] ,MSI vector 137" "No MSI,MSI sent"
|
|
eventfld.long 0x10 8. " [136] ,MSI vector 136" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x10 7. " [135] ,MSI vector 135" "No MSI,MSI sent"
|
|
eventfld.long 0x10 6. " [134] ,MSI vector 134" "No MSI,MSI sent"
|
|
eventfld.long 0x10 5. " [133] ,MSI vector 133" "No MSI,MSI sent"
|
|
eventfld.long 0x10 4. " [132] ,MSI vector 132" "No MSI,MSI sent"
|
|
eventfld.long 0x10 3. " [131] ,MSI vector 131" "No MSI,MSI sent"
|
|
eventfld.long 0x10 2. " [130] ,MSI vector 130" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x10 1. " [129] ,MSI vector 129" "No MSI,MSI sent"
|
|
eventfld.long 0x10 0. " [128] ,MSI vector 128" "No MSI,MSI sent"
|
|
line.long 0x14 "MSI_VEC5_0,XUSB_HOST MSI Vector Register 5"
|
|
eventfld.long 0x14 31. " MSI_VECTOR[191] ,MSI vector 191" "No MSI,MSI sent"
|
|
eventfld.long 0x14 30. " [190] ,MSI vector 190" "No MSI,MSI sent"
|
|
eventfld.long 0x14 29. " [189] ,MSI vector 189" "No MSI,MSI sent"
|
|
eventfld.long 0x14 28. " [188] ,MSI vector 188" "No MSI,MSI sent"
|
|
eventfld.long 0x14 27. " [187] ,MSI vector 187" "No MSI,MSI sent"
|
|
eventfld.long 0x14 26. " [186] ,MSI vector 186" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x14 25. " [185] ,MSI vector 185" "No MSI,MSI sent"
|
|
eventfld.long 0x14 24. " [184] ,MSI vector 184" "No MSI,MSI sent"
|
|
eventfld.long 0x14 23. " [183] ,MSI vector 183" "No MSI,MSI sent"
|
|
eventfld.long 0x14 22. " [182] ,MSI vector 182" "No MSI,MSI sent"
|
|
eventfld.long 0x14 21. " [181] ,MSI vector 181" "No MSI,MSI sent"
|
|
eventfld.long 0x14 20. " [180] ,MSI vector 180" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x14 19. " [179] ,MSI vector 179" "No MSI,MSI sent"
|
|
eventfld.long 0x14 18. " [178] ,MSI vector 178" "No MSI,MSI sent"
|
|
eventfld.long 0x14 17. " [177] ,MSI vector 177" "No MSI,MSI sent"
|
|
eventfld.long 0x14 16. " [176] ,MSI vector 176" "No MSI,MSI sent"
|
|
eventfld.long 0x14 15. " [175] ,MSI vector 175" "No MSI,MSI sent"
|
|
eventfld.long 0x14 14. " [174] ,MSI vector 174" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x14 13. " [173] ,MSI vector 173" "No MSI,MSI sent"
|
|
eventfld.long 0x14 12. " [172] ,MSI vector 172" "No MSI,MSI sent"
|
|
eventfld.long 0x14 11. " [171] ,MSI vector 171" "No MSI,MSI sent"
|
|
eventfld.long 0x14 10. " [170] ,MSI vector 170" "No MSI,MSI sent"
|
|
eventfld.long 0x14 9. " [169] ,MSI vector 169" "No MSI,MSI sent"
|
|
eventfld.long 0x14 8. " [168] ,MSI vector 168" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x14 7. " [167] ,MSI vector 167" "No MSI,MSI sent"
|
|
eventfld.long 0x14 6. " [166] ,MSI vector 166" "No MSI,MSI sent"
|
|
eventfld.long 0x14 5. " [165] ,MSI vector 165" "No MSI,MSI sent"
|
|
eventfld.long 0x14 4. " [164] ,MSI vector 164" "No MSI,MSI sent"
|
|
eventfld.long 0x14 3. " [163] ,MSI vector 163" "No MSI,MSI sent"
|
|
eventfld.long 0x14 2. " [162] ,MSI vector 162" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x14 1. " [161] ,MSI vector 161" "No MSI,MSI sent"
|
|
eventfld.long 0x14 0. " [160] ,MSI vector 160" "No MSI,MSI sent"
|
|
line.long 0x18 "MSI_VEC6_0,XUSB_HOST MSI Vector Register 6"
|
|
eventfld.long 0x18 31. " MSI_VECTOR[223] ,MSI vector 223" "No MSI,MSI sent"
|
|
eventfld.long 0x18 30. " [222] ,MSI vector 222" "No MSI,MSI sent"
|
|
eventfld.long 0x18 29. " [221] ,MSI vector 221" "No MSI,MSI sent"
|
|
eventfld.long 0x18 28. " [220] ,MSI vector 220" "No MSI,MSI sent"
|
|
eventfld.long 0x18 27. " [219] ,MSI vector 219" "No MSI,MSI sent"
|
|
eventfld.long 0x18 26. " [218] ,MSI vector 218" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x18 25. " [217] ,MSI vector 217" "No MSI,MSI sent"
|
|
eventfld.long 0x18 24. " [216] ,MSI vector 216" "No MSI,MSI sent"
|
|
eventfld.long 0x18 23. " [215] ,MSI vector 215" "No MSI,MSI sent"
|
|
eventfld.long 0x18 22. " [214] ,MSI vector 214" "No MSI,MSI sent"
|
|
eventfld.long 0x18 21. " [213] ,MSI vector 213" "No MSI,MSI sent"
|
|
eventfld.long 0x18 20. " [212] ,MSI vector 212" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x18 19. " [211] ,MSI vector 211" "No MSI,MSI sent"
|
|
eventfld.long 0x18 18. " [210] ,MSI vector 210" "No MSI,MSI sent"
|
|
eventfld.long 0x18 17. " [209] ,MSI vector 209" "No MSI,MSI sent"
|
|
eventfld.long 0x18 16. " [208] ,MSI vector 208" "No MSI,MSI sent"
|
|
eventfld.long 0x18 15. " [207] ,MSI vector 207" "No MSI,MSI sent"
|
|
eventfld.long 0x18 14. " [206] ,MSI vector 206" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x18 13. " [205] ,MSI vector 205" "No MSI,MSI sent"
|
|
eventfld.long 0x18 12. " [204] ,MSI vector 204" "No MSI,MSI sent"
|
|
eventfld.long 0x18 11. " [203] ,MSI vector 203" "No MSI,MSI sent"
|
|
eventfld.long 0x18 10. " [202] ,MSI vector 202" "No MSI,MSI sent"
|
|
eventfld.long 0x18 9. " [201] ,MSI vector 201" "No MSI,MSI sent"
|
|
eventfld.long 0x18 8. " [200] ,MSI vector 200" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x18 7. " [199] ,MSI vector 199" "No MSI,MSI sent"
|
|
eventfld.long 0x18 6. " [198] ,MSI vector 198" "No MSI,MSI sent"
|
|
eventfld.long 0x18 5. " [197] ,MSI vector 197" "No MSI,MSI sent"
|
|
eventfld.long 0x18 4. " [196] ,MSI vector 196" "No MSI,MSI sent"
|
|
eventfld.long 0x18 3. " [195] ,MSI vector 195" "No MSI,MSI sent"
|
|
eventfld.long 0x18 2. " [194] ,MSI vector 194" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x18 1. " [193] ,MSI vector 193" "No MSI,MSI sent"
|
|
eventfld.long 0x18 0. " [192] ,MSI vector 192" "No MSI,MSI sent"
|
|
line.long 0x1C "MSI_VEC7_0,XUSB_HOST MSI Vector Register 7"
|
|
eventfld.long 0x1C 31. " MSI_VECTOR[255] ,MSI vector 255" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 30. " [254] ,MSI vector 254" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 29. " [253] ,MSI vector 253" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 28. " [252] ,MSI vector 252" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 27. " [251] ,MSI vector 251" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 26. " [250] ,MSI vector 250" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x1C 25. " [249] ,MSI vector 249" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 24. " [248] ,MSI vector 248" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 23. " [247] ,MSI vector 247" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 22. " [246] ,MSI vector 246" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 21. " [245] ,MSI vector 245" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 20. " [244] ,MSI vector 244" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x1C 19. " [243] ,MSI vector 243" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 18. " [242] ,MSI vector 242" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 17. " [241] ,MSI vector 241" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 16. " [240] ,MSI vector 240" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 15. " [239] ,MSI vector 239" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 14. " [238] ,MSI vector 238" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x1C 13. " [237] ,MSI vector 237" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 12. " [236] ,MSI vector 236" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 11. " [235] ,MSI vector 235" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 10. " [234] ,MSI vector 234" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 9. " [233] ,MSI vector 233" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 8. " [232] ,MSI vector 232" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x1C 7. " [231] ,MSI vector 231" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 6. " [230] ,MSI vector 230" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 5. " [229] ,MSI vector 229" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 4. " [228] ,MSI vector 228" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 3. " [227] ,MSI vector 227" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 2. " [226] ,MSI vector 226" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x1C 1. " [225] ,MSI vector 225" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 0. " [224] ,MSI vector 224" "No MSI,MSI sent"
|
|
textline " "
|
|
width 15.
|
|
group.long 0x140++0x1F
|
|
line.long 0x00 "MSI_EN_VEC0_0,XUSB_HOST MSI Vector Enable Register 0"
|
|
bitfld.long 0x00 31. " MSI_ENABLE_VECTOR[31] ,MSI vector enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,MSI vector enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,MSI vector enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,MSI vector enable 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,MSI vector enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,MSI vector enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [25] ,MSI vector enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,MSI vector enable 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,MSI vector enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,MSI vector enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,MSI vector enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,MSI vector enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,MSI vector enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,MSI vector enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,MSI vector enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,MSI vector enable 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,MSI vector enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,MSI vector enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,MSI vector enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,MSI vector enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,MSI vector enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,MSI vector enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,MSI vector enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,MSI vector enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,MSI vector enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,MSI vector enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,MSI vector enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,MSI vector enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,MSI vector enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,MSI vector enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,MSI vector enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,MSI vector enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "MSI_EN_VEC1_0,XUSB_HOST MSI Vector Enable Register 1"
|
|
bitfld.long 0x04 31. " MSI_ENABLE_VECTOR[63] ,MSI vector enable 63" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,MSI vector enable 62" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,MSI vector enable 61" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,MSI vector enable 60" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " [59] ,MSI vector enable 59" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [58] ,MSI vector enable 58" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " [57] ,MSI vector enable 57" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,MSI vector enable 56" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " [55] ,MSI vector enable 55" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,MSI vector enable 54" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,MSI vector enable 53" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,MSI vector enable 52" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [51] ,MSI vector enable 51" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,MSI vector enable 50" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,MSI vector enable 49" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,MSI vector enable 48" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " [47] ,MSI vector enable 47" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,MSI vector enable 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " [45] ,MSI vector enable 45" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,MSI vector enable 44" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " [43] ,MSI vector enable 43" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,MSI vector enable 42" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,MSI vector enable 41" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,MSI vector enable 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [39] ,MSI vector enable 39" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,MSI vector enable 38" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,MSI vector enable 37" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,MSI vector enable 36" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " [35] ,MSI vector enable 35" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,MSI vector enable 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " [33] ,MSI vector enable 33" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,MSI vector enable 32" "Disabled,Enabled"
|
|
line.long 0x08 "MSI_EN_VEC2_0,XUSB_HOST MSI Vector Enable Register 2"
|
|
bitfld.long 0x08 31. " MSI_ENABLE_VECTOR[95] ,MSI vector enable 95" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [94] ,MSI vector enable 94" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [93] ,MSI vector enable 93" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [92] ,MSI vector enable 92" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " [91] ,MSI vector enable 91" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [90] ,MSI vector enable 90" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " [89] ,MSI vector enable 89" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [88] ,MSI vector enable 88" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " [87] ,MSI vector enable 87" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,MSI vector enable 86" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,MSI vector enable 85" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,MSI vector enable 84" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [83] ,MSI vector enable 83" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [82] ,MSI vector enable 82" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [81] ,MSI vector enable 81" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [80] ,MSI vector enable 80" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " [79] ,MSI vector enable 79" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,MSI vector enable 78" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " [77] ,MSI vector enable 77" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,MSI vector enable 76" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " [75] ,MSI vector enable 75" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,MSI vector enable 74" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,MSI vector enable 73" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [72] ,MSI vector enable 72" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [71] ,MSI vector enable 71" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,MSI vector enable 70" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [69] ,MSI vector enable 69" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,MSI vector enable 68" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " [67] ,MSI vector enable 67" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,MSI vector enable 66" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " [65] ,MSI vector enable 65" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [64] ,MSI vector enable 64" "Disabled,Enabled"
|
|
line.long 0x0C "MSI_EN_VEC3_0,XUSB_HOST MSI Vector Enable Register 3"
|
|
bitfld.long 0x0C 31. " MSI_ENABLE_VECTOR[127] ,MSI vector enable 127" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,MSI vector enable 126" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,MSI vector enable 125" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,MSI vector enable 124" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " [123] ,MSI vector enable 123" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [122] ,MSI vector enable 122" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " [121] ,MSI vector enable 121" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,MSI vector enable 120" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " [119] ,MSI vector enable 119" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,MSI vector enable 118" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,MSI vector enable 117" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,MSI vector enable 116" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [115] ,MSI vector enable 115" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,MSI vector enable 114" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,MSI vector enable 113" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,MSI vector enable 112" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " [111] ,MSI vector enable 111" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [110] ,MSI vector enable 110" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " [109] ,MSI vector enable 109" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,MSI vector enable 108" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " [107] ,MSI vector enable 107" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,MSI vector enable 106" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [105] ,MSI vector enable 105" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,MSI vector enable 104" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [103] ,MSI vector enable 103" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [102] ,MSI vector enable 102" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,MSI vector enable 101" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,MSI vector enable 100" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " [99] ,MSI vector enable 99" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [98] ,MSI vector enable 98" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " [97] ,MSI vector enable 97" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,MSI vector enable 96" "Disabled,Enabled"
|
|
line.long 0x10 "MSI_EN_VEC4_0,XUSB_HOST MSI Vector Enable Register 4"
|
|
bitfld.long 0x10 31. " MSI_ENABLE_VECTOR[159] ,MSI vector enable 159" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " [158] ,MSI vector enable 158" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " [157] ,MSI vector enable 157" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " [156] ,MSI vector enable 156" "Disabled,Enabled"
|
|
bitfld.long 0x10 27. " [155] ,MSI vector enable 155" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " [154] ,MSI vector enable 154" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " [153] ,MSI vector enable 153" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " [152] ,MSI vector enable 152" "Disabled,Enabled"
|
|
bitfld.long 0x10 23. " [151] ,MSI vector enable 151" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " [150] ,MSI vector enable 150" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " [149] ,MSI vector enable 149" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " [148] ,MSI vector enable 148" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " [147] ,MSI vector enable 147" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " [146] ,MSI vector enable 146" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " [145] ,MSI vector enable 145" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " [144] ,MSI vector enable 144" "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " [143] ,MSI vector enable 143" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " [142] ,MSI vector enable 142" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " [141] ,MSI vector enable 141" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " [140] ,MSI vector enable 140" "Disabled,Enabled"
|
|
bitfld.long 0x10 11. " [139] ,MSI vector enable 139" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " [138] ,MSI vector enable 138" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " [137] ,MSI vector enable 137" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " [136] ,MSI vector enable 136" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " [135] ,MSI vector enable 135" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " [134] ,MSI vector enable 134" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " [133] ,MSI vector enable 133" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " [132] ,MSI vector enable 132" "Disabled,Enabled"
|
|
bitfld.long 0x10 3. " [131] ,MSI vector enable 131" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " [130] ,MSI vector enable 130" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " [129] ,MSI vector enable 129" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " [128] ,MSI vector enable 128" "Disabled,Enabled"
|
|
line.long 0x14 "MSI_EN_VEC5_0,XUSB_HOST MSI Vector Enable Register 5"
|
|
bitfld.long 0x14 31. " MSI_ENABLE_VECTOR[191] ,MSI vector enable 191" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " [190] ,MSI vector enable 190" "Disabled,Enabled"
|
|
bitfld.long 0x14 29. " [189] ,MSI vector enable 189" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " [188] ,MSI vector enable 188" "Disabled,Enabled"
|
|
bitfld.long 0x14 27. " [187] ,MSI vector enable 187" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " [186] ,MSI vector enable 186" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " [185] ,MSI vector enable 185" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " [184] ,MSI vector enable 184" "Disabled,Enabled"
|
|
bitfld.long 0x14 23. " [183] ,MSI vector enable 183" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " [182] ,MSI vector enable 182" "Disabled,Enabled"
|
|
bitfld.long 0x14 21. " [181] ,MSI vector enable 181" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " [180] ,MSI vector enable 180" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " [179] ,MSI vector enable 179" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " [178] ,MSI vector enable 178" "Disabled,Enabled"
|
|
bitfld.long 0x14 17. " [177] ,MSI vector enable 177" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " [176] ,MSI vector enable 176" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " [175] ,MSI vector enable 175" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " [174] ,MSI vector enable 174" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " [173] ,MSI vector enable 173" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " [172] ,MSI vector enable 172" "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " [171] ,MSI vector enable 171" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " [170] ,MSI vector enable 170" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " [169] ,MSI vector enable 169" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " [168] ,MSI vector enable 168" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " [167] ,MSI vector enable 167" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " [166] ,MSI vector enable 166" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " [165] ,MSI vector enable 165" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " [164] ,MSI vector enable 164" "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " [163] ,MSI vector enable 163" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " [162] ,MSI vector enable 162" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " [161] ,MSI vector enable 161" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " [160] ,MSI vector enable 160" "Disabled,Enabled"
|
|
line.long 0x18 "MSI_EN_VEC6_0,XUSB_HOST MSI Vector Enable Register 6"
|
|
bitfld.long 0x18 31. " MSI_ENABLE_VECTOR[223] ,MSI vector enable 223" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " [222] ,MSI vector enable 222" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " [221] ,MSI vector enable 221" "Disabled,Enabled"
|
|
bitfld.long 0x18 28. " [220] ,MSI vector enable 220" "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " [219] ,MSI vector enable 219" "Disabled,Enabled"
|
|
bitfld.long 0x18 26. " [218] ,MSI vector enable 218" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 25. " [217] ,MSI vector enable 217" "Disabled,Enabled"
|
|
bitfld.long 0x18 24. " [216] ,MSI vector enable 216" "Disabled,Enabled"
|
|
bitfld.long 0x18 23. " [215] ,MSI vector enable 215" "Disabled,Enabled"
|
|
bitfld.long 0x18 22. " [214] ,MSI vector enable 214" "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " [213] ,MSI vector enable 213" "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " [212] ,MSI vector enable 212" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 19. " [211] ,MSI vector enable 211" "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " [210] ,MSI vector enable 210" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " [209] ,MSI vector enable 209" "Disabled,Enabled"
|
|
bitfld.long 0x18 16. " [208] ,MSI vector enable 208" "Disabled,Enabled"
|
|
bitfld.long 0x18 15. " [207] ,MSI vector enable 207" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " [206] ,MSI vector enable 206" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 13. " [205] ,MSI vector enable 205" "Disabled,Enabled"
|
|
bitfld.long 0x18 12. " [204] ,MSI vector enable 204" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " [203] ,MSI vector enable 203" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " [202] ,MSI vector enable 202" "Disabled,Enabled"
|
|
bitfld.long 0x18 9. " [201] ,MSI vector enable 201" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " [200] ,MSI vector enable 200" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 7. " [199] ,MSI vector enable 199" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " [198] ,MSI vector enable 198" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " [197] ,MSI vector enable 197" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " [196] ,MSI vector enable 196" "Disabled,Enabled"
|
|
bitfld.long 0x18 3. " [195] ,MSI vector enable 195" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " [194] ,MSI vector enable 194" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " [193] ,MSI vector enable 193" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " [192] ,MSI vector enable 192" "Disabled,Enabled"
|
|
line.long 0x1C "MSI_EN_VEC7_0,XUSB_HOST MSI Vector Enable Register 7"
|
|
bitfld.long 0x1C 31. " MSI_ENABLE_VECTOR[255] ,MSI vector enable 255" "Disabled,Enabled"
|
|
bitfld.long 0x1C 30. " [254] ,MSI vector enable 254" "Disabled,Enabled"
|
|
bitfld.long 0x1C 29. " [253] ,MSI vector enable 253" "Disabled,Enabled"
|
|
bitfld.long 0x1C 28. " [252] ,MSI vector enable 252" "Disabled,Enabled"
|
|
bitfld.long 0x1C 27. " [251] ,MSI vector enable 251" "Disabled,Enabled"
|
|
bitfld.long 0x1C 26. " [250] ,MSI vector enable 250" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 25. " [249] ,MSI vector enable 249" "Disabled,Enabled"
|
|
bitfld.long 0x1C 24. " [248] ,MSI vector enable 248" "Disabled,Enabled"
|
|
bitfld.long 0x1C 23. " [247] ,MSI vector enable 247" "Disabled,Enabled"
|
|
bitfld.long 0x1C 22. " [246] ,MSI vector enable 246" "Disabled,Enabled"
|
|
bitfld.long 0x1C 21. " [245] ,MSI vector enable 245" "Disabled,Enabled"
|
|
bitfld.long 0x1C 20. " [244] ,MSI vector enable 244" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " [243] ,MSI vector enable 243" "Disabled,Enabled"
|
|
bitfld.long 0x1C 18. " [242] ,MSI vector enable 242" "Disabled,Enabled"
|
|
bitfld.long 0x1C 17. " [241] ,MSI vector enable 241" "Disabled,Enabled"
|
|
bitfld.long 0x1C 16. " [240] ,MSI vector enable 240" "Disabled,Enabled"
|
|
bitfld.long 0x1C 15. " [239] ,MSI vector enable 239" "Disabled,Enabled"
|
|
bitfld.long 0x1C 14. " [238] ,MSI vector enable 238" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 13. " [237] ,MSI vector enable 237" "Disabled,Enabled"
|
|
bitfld.long 0x1C 12. " [236] ,MSI vector enable 236" "Disabled,Enabled"
|
|
bitfld.long 0x1C 11. " [235] ,MSI vector enable 235" "Disabled,Enabled"
|
|
bitfld.long 0x1C 10. " [234] ,MSI vector enable 234" "Disabled,Enabled"
|
|
bitfld.long 0x1C 9. " [233] ,MSI vector enable 233" "Disabled,Enabled"
|
|
bitfld.long 0x1C 8. " [232] ,MSI vector enable 232" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " [231] ,MSI vector enable 231" "Disabled,Enabled"
|
|
bitfld.long 0x1C 6. " [230] ,MSI vector enable 230" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " [229] ,MSI vector enable 229" "Disabled,Enabled"
|
|
bitfld.long 0x1C 4. " [228] ,MSI vector enable 228" "Disabled,Enabled"
|
|
bitfld.long 0x1C 3. " [227] ,MSI vector enable 227" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " [226] ,MSI vector enable 226" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " [225] ,MSI vector enable 225" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " [224] ,MSI vector enable 224" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
width 20.
|
|
tree "Configuration registers"
|
|
group.long 0x180++0x1F
|
|
line.long 0x00 "CONFIGURATION_0,Configuration"
|
|
bitfld.long 0x00 31. " CLKEN_OVERRIDE ,Override the clock enable in case of a malfunction" "Disabled,Enabled"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 19. " PW_NO_DEVSEL_ERR_CYA ,Disable detection of DECERR due to no DEVSEL" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 19. " PW_NO_DEVSEL_ERR_CYA ,Disable detection of DECERR due to no DEVSEL" "No,Yes"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 18. " INITIATOR_READ_IDLE ,AFI upstream read status" "Busy,Idle"
|
|
rbitfld.long 0x00 17. " INITIATOR_WRITE_IDLE ,AFI upstream write status" "Busy,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WDATA_LEAD_CYA ,Enable the handling of write data ahead of requests on IPFS AXI" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WR_INTRLV_CYA ,Disable the handling of interleaved write requests on IPFS AXI" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " TARGET_READ_IDLE ,IPFS target read status" "Busy,Idle"
|
|
rbitfld.long 0x00 10. " TARGET_WRITE_IDLE ,IPFS target write status" "Busy,Idle"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " MSI_VEC_EMPTY ,MSI Vector registers status" "No empty,Empty"
|
|
bitfld.long 0x00 7. " UFPCI_MSIAW ,MSI After Write ordering rule" "Default behavior (MSIAW ordering),Interrupt whenever MSI is ready"
|
|
textline " "
|
|
bitfld.long 0x00 6. " UFPCI_PWPASSPW ,Send input to the upstream FPCI" "Whenever write is ready,Only when PW has retired"
|
|
bitfld.long 0x00 5. " UFPCI_PASSPW ,Allows the upstream FPCI reads to pass writes" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFPCI_PWPASSNPW ,Allows the upstream FPCI PWs to pass NPW" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " DFPCI_PWPASSNPW ,Allows the downstream FPCI PWs to pass NPW" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DFPCI_RSPPASSPW ,Allows the downstream FPCI responses to pass writes" "Not allowed,Allowed"
|
|
bitfld.long 0x00 1. " DFPCI_PASSPW ,Allow the downstream FPCI reads to pass writes" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN_FPCI ,Enable FPCI" "Disabled,Enabled"
|
|
line.long 0x04 "FPCI_ERROR_MASKS_0,XUSB_HOSTFPCI Error Masks"
|
|
bitfld.long 0x04 2. " MASK_FPCI_MASTER_ABORT ,Allows an FPCI error response indicates a Master Abort" "Return AXI OK,Forward error"
|
|
bitfld.long 0x04 1. " MASK_FPCI_DATA_ERROR ,Allows an FPCI error response indicates a Data Error" "Return AXI OK,Forward error"
|
|
bitfld.long 0x04 0. " MASK_FPCI_TARGET_ABORT ,Allows an FPCI error response indicates a Target Abort" "Return AXI OK,Forward error"
|
|
line.long 0x08 "INTR_MASK_0,Interrupt Masks"
|
|
bitfld.long 0x08 16. " IP_INT_MASK ,IP interrupt to the CPU complex gated by the mask" "0,1"
|
|
bitfld.long 0x08 8. " MSI_MASK ,MSI to the CPU complex gated by the mask" "0,1"
|
|
bitfld.long 0x08 0. " INT_MASK ,Interrupt to the CPU complex gated by the mask" "0,1"
|
|
line.long 0x0C "INTR_CODE_0,Interrupt Control"
|
|
bitfld.long 0x0C 0.--4. " INT_CODE ,Eight interrupt codes" "CLEAR,INI_SLVERR,INI_DECERR,TGT_SLVERR,TGT_DECERR,TGT_WRERR,,DFPCI_DECERR,AXI_DECERR,TIMEOUT,,,,,,SM_FATAL_ERROR,SM_NON_FATAL_ERROR,?..."
|
|
line.long 0x10 "INTR_SIGNATURE_0,Interrupt Signature"
|
|
hexmask.long 0x10 2.--31. 0x4 " INT_INFO ,Interrupt info (Address bits for interrupt codes)"
|
|
bitfld.long 0x10 0. " DIR ,Direction of the AXI/FPCI transaction" "Write,Read"
|
|
line.long 0x14 "UPPER_FPCI_ADDR_0,Upper FPCI Address"
|
|
hexmask.long.byte 0x14 0.--7. 0x01 " INT_INFO_UPPER ,Upper byte of the captured FPCI address (for interrupt code: 3, 4 or 7)"
|
|
line.long 0x18 "IPFS_INTR_ENABLE_0,IPFS Interrupt Enable"
|
|
bitfld.long 0x18 13. " EN_SM_NON_FATAL_ERROR ,Enable bit for interrupt code 15" "Disabled,Enabled"
|
|
bitfld.long 0x18 12. " EN_SM_FATAL_ERROR ,Enable bit for interrupt code 14" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " EN_FPCI_TIMEOUT ,Enable bit for interrupt code 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 6. " EN_AXI_DECERR ,Enable bit for interrupt code 8" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EN_DFPCI_DECERR ,Enable bit for interrupt code 7" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " EN_TGT_WRERR ,Enable bit for interrupt code 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 3. " EN_TGT_DECERR ,Enable bit for interrupt code 4" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " EN_TGT_SLVERR ,Enable bit for interrupt code 3" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " EN_INI_DECERR ,Enable bit for interrupt code 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0. " EN_INI_SLVERR ,Enable bit for interrupt code 1" "Disabled,Enabled"
|
|
line.long 0x1C "UFPCI_CONFIG_0,Upstream FPCI Configuration"
|
|
bitfld.long 0x1C 0.--4. " UNITID_T0C0 ,Upstream FPCI Unit ID for controller 0. HyperTransport (Upstream FPCI request)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x1A0++0x0B
|
|
line.long 0x00 "CFG_REVID_0,CFG_REVID Register"
|
|
rbitfld.long 0x00 19. " DEV2SM_NONISO_REQUEST_PEND ,There is a non-ISO request pending" "Not pending,Pending"
|
|
rbitfld.long 0x00 18. " DEV2SM_ISO_REQUEST_PEND ,There is an ISO request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12.--13. " STRAP_CPU_MODE ,MCP: Mode to send MSI" "NB_INTEL,NB_AMD,AMD,TMTA"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CFG_REVID_WRITE_ENABLE ,Enable to override the rev ID" "Clear,Set"
|
|
bitfld.long 0x00 10. " CFG_REVID_OVERRIDE ,Provides a way to override the current revision ID" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DEV2LEG_NONCOH_REQUEST_PEND ,Tells the leg block that a non-coherent request is pending" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " DEV2LEG_COH_REQUEST_PEND ,Tells the leg block that a coherent request is pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SM2DEV_FPCI_TIMEOUT_EN ,FPCI timeout enable bit for Controller" "Disabled,Enabled"
|
|
line.long 0x04 "FPCI_TIMEOUT_0,FPCI_TIMEOUT Register"
|
|
hexmask.long.tbyte 0x04 0.--19. 1. " SM2ALL_FPCI_TIMEOUT_THRESH ,Timeout threshold value for the FPCI bus"
|
|
line.long 0x08 "TOM_0,Top Of Memory Limit"
|
|
hexmask.long.word 0x08 16.--29. 1. " LEG2ALL_TOM2 ,Top of Memory Limit 2"
|
|
hexmask.long.word 0x08 0.--11. 1. " LEG2ALL_TOM1 ,Top of Memory Limit 1"
|
|
textline " "
|
|
width 33.
|
|
rgroup.long 0x1AC++0x0B
|
|
line.long 0x00 "INITIATOR_ISO_PW_RESP_PENDING_0,Initiator ISO PW Response Pending"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NUM_INITIATOR_ISO_PW_RESP_PEND ,Number of pending initiator ISO PW responses"
|
|
line.long 0x04 "INITIATOR_NISO_PW_RESP_PENDING_0,Initiator Non-ISO PW Response Pending"
|
|
hexmask.long.byte 0x04 0.--7. 1. " NUM_INITIATOR_NISO_PW_RESP_PEND ,Number of pending initiator NISO PW responses"
|
|
line.long 0x08 "INTR_STATUS_0,IPFS Interrupt Status"
|
|
bitfld.long 0x08 2. " IP_INTR_STATUS ,Status of IP interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 1. " MSI_INTR_STATUS ,Status of MSI interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " IPFS_INTR_STATUS ,Status of IPFS interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
width 22.
|
|
group.long 0x1B8++0x07
|
|
line.long 0x00 "DFPCI_BEN_0,Downstream FPCI Byte Enables"
|
|
bitfld.long 0x00 31. " EN_DFPCI_BEN ,Enable bit for BEN" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DFPCI_BYTE_ENABLE_N ,Active low byte enables" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CLKGATE_HYSTERESIS_0,CLKGATE HYSTERESIS 0"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CLK_DISABLE_CNT ,Number of IPFS clock cycles to wait after clock gating criteria is met to disable IPFS/FPCI clocks"
|
|
sif !cpuis("TEGRAX2")
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "MCCIF_FIFOCTRL_0,Memory Client Interface FIFO Control Register"
|
|
bitfld.long 0x00 20. " RCLK_OVR_MODE ,RCLK OVR MODE" "Legacy,On"
|
|
bitfld.long 0x00 19. " WCLK_OVR_MODE ,RCLK OVR MODE" "Legacy,On"
|
|
bitfld.long 0x00 18. " CCLK_OVERRIDE ,CCLK OVERRIDE" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RCLK_OVERRIDE ,RCLK OVERRIDE" "No override,Override"
|
|
bitfld.long 0x00 16. " WCLK_OVERRIDE ,WCLK OVERRIDE" "No override,Override"
|
|
bitfld.long 0x00 3. " MCCIF_RDCL_RDFAST ,MCCIF RDCL RDFAST" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MCCIF_WRMC_CLLE2X ,MCCIF WRMC CLLE2X" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MCCIF_RDMC_RDFAST ,MCCIF RDMC RDFAST" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MCCIF_WRCL_MCLE2X ,MCCIF WRCL MCLE2X" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
width 18.
|
|
group.long 0x1E0++0x0B
|
|
line.long 0x00 "ORDERING_RULES_0,ORDERING RULES"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 3. " UPSTREAM_MSIAW ,Modified Upstream MSIAW ordering" "Tegra X1,Tegra 3"
|
|
bitfld.long 0x00 2. " UPSTREAM_RESPAW ,Modified RespAW ordering." "Tegra X1,Tegra 3"
|
|
bitfld.long 0x00 1. " UPSTREAM_RAW ,Modified RAW ordering" "Tegra X1,Tegra 3"
|
|
elif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 3. " UPSTREAM_MSIAW ,Modified Upstream MSIAW ordering" "Parker,Parker 3"
|
|
bitfld.long 0x00 2. " UPSTREAM_RESPAW ,Modified RespAW ordering." "Parker,Parker 3"
|
|
bitfld.long 0x00 1. " UPSTREAM_RAW ,Modified RAW ordering" "Parker,Parker 3"
|
|
else
|
|
bitfld.long 0x00 3. " UPSTREAM_MSIAW ,Modified Upstream MSIAW ordering" "Tegra K1,Tegra 3"
|
|
bitfld.long 0x00 2. " UPSTREAM_RESPAW ,Modified RespAW ordering." "Tegra K1,Tegra 3"
|
|
bitfld.long 0x00 1. " UPSTREAM_RAW ,Modified RAW ordering" "Tegra K1,Tegra 3"
|
|
endif
|
|
line.long 0x04 "A2F_UFPCI_CFG0_0,A2F UFPCI CFG0"
|
|
hexmask.long.byte 0x04 24.--31. 1. " STATIC_WAIT_IDLE_CNTR ,Static wait idle control"
|
|
bitfld.long 0x04 16.--18. " STATIC_UFPCI_UFA_STARVE_CNTR_PRI1 ,Static UFPCI UFA starve Control PRI1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 12.--15. " STATIC_UFPCI_UFA_STARVE_CNTR_PRI0 ,Static UFPCI UFA starve control PRI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " STATIC_UFPCI_RR_BURST_SZ_PRI1 ,Static UFPCI RR burst SZ PRI1" "0,1,2,3"
|
|
bitfld.long 0x04 8.--9. " STATIC_UFPCI_RR_BURST_SZ_PRI0 ,Static UFPCI RR burst SZ PRI0" "0,1,2,3"
|
|
bitfld.long 0x04 7. " STATIC_WAIT_CLAMP_EN ,Static wait clamp enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " STATIC_UFPCI_UFA_DYN_BLOCK_EN ,Static UFPCI UFA DYN block enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " STATIC_UFPCI_UFA_BLK_COHERENT ,Static UFPCI UFA BLK coherent" "No coherent,Coherent"
|
|
bitfld.long 0x04 2.--4. " STATIC_UFPCI_BLOCK_CMD_THRESHOLD ,Static UFPCI block CMD threshold" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 1. " STATIC_CYA_UFA_ARB ,Static CYA UFA ARB" "0,1"
|
|
bitfld.long 0x04 0. " STATIC_CYA_BACK2BACK_UPSTREAM_BLOCK ,Static CYA back to back upstream block" "0,1"
|
|
line.long 0x08 "A2F_UFPCI_CFG1_0,A2F UFPCI CFG1"
|
|
hexmask.long.byte 0x08 0.--7. 1. " STATIC_WAIT_UNCLAMP_CNTR ,Static wait unclamp control"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "XUSB PADCTL Registers"
|
|
base ad:0x7009F000
|
|
width 16.
|
|
group.long 0x00++0x0b
|
|
line.long 0x00 "BOOT_MEDIA_0,XUSB PADCTL BOOT MEDIA"
|
|
bitfld.long 0x00 1.--4. " BOOT_PORT ,BOOT PORT" "OTG0,OTG1,OTG2,OTG3,OTG4,OTG5,OTG6,ULPI,,HSIC0,HSIC1,?..."
|
|
bitfld.long 0x00 0. " BOOT_MEDIA_ENABLE ,BOOT MEDIA ENABLE" "Disabled,Enabled"
|
|
line.long 0x04 "USB2_PAD_MUX_0,XUSB PADCTL USB2 PAD MUX 0"
|
|
bitfld.long 0x04 15. " USB2_HSIC_PAD_PORT1 ,USB2 HSIC PAD PORT1" "SNPS,XUSB"
|
|
bitfld.long 0x04 14. " USB2_HSIC_PAD_PORT0 ,USB2 HSIC PAD PORT0" "SNPS,XUSB"
|
|
bitfld.long 0x04 12. " USB2_ULPI_PAD_PORT ,USB2 ULPI PAD PORT" "SNPS,XUSB"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " USB2_OTG_PAD_PORT2 ,USB2 OTG PAD PORT2" "SNPS,XUSB,UART,?..."
|
|
bitfld.long 0x04 2.--3. " USB2_OTG_PAD_PORT1 ,USB2 OTG PAD PORT1" "SNPS,XUSB,UART,"
|
|
bitfld.long 0x04 0.--1. " USB2_OTG_PAD_PORT0 ,USB2 OTG PAD PORT0" "SNPS,XUSB,UART,?..."
|
|
line.long 0x08 "USB2_PORT_CAP_0,XUSB PADCTL USB2 PORT CAP 0"
|
|
bitfld.long 0x08 25. " ULPI_PORT_INTERNAL ,ULPI PORT INTERNAL" "No,Yes"
|
|
bitfld.long 0x08 24. " ULPI_PORT_CAP ,ULPI PORT CAP" "ULPI_MASTER,ULPI_PHY"
|
|
bitfld.long 0x08 11. " PORT2_REVERSE_ID ,PORT2 REVERSE ID" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 10. " PORT2_INTERNAL ,PORT2 INTERNAL" "No,Yes"
|
|
bitfld.long 0x08 8.--9. " PORT2_CAP ,PORT2 CAP" "Disabled,HOST_ONLY,DEVICE_ONLY,OTG_CAP"
|
|
bitfld.long 0x08 7. " PORT1_REVERSE_ID ,PORT1 REVERSE ID" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 6. " PORT1_INTERNAL ,PORT1 INTERNAL" "No,Yes"
|
|
bitfld.long 0x08 4.--5. " PORT1_CAP ,PORT1 CAP" "Disabled,HOST_ONLY,DEVICE_ONLY,OTG_CAP"
|
|
bitfld.long 0x08 3. " PORT0_REVERSE_ID ,PORT0 REVERSE ID" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 2. " PORT0_INTERNAL ,PORT0 INTERNAL" "No,Yes"
|
|
bitfld.long 0x08 0.--1. " PORT0_CAP ,PORT0 CAP" "Disabled,HOST_ONLY,DEVICE_ONLY,OTG_CAP"
|
|
group.long 0x0C++0xB
|
|
line.long 0x00 "SNPS_OC_MAP_0,XUSB PADCTL SNPS OC MAP"
|
|
bitfld.long 0x00 6.--8. " CONTROLLER3_OC_PIN ,CONTROLLER3 OC PIN" "DETECTED0,DETECTED1,DETECTED2,DETECTED3,DETECTED_VBUS_PAD0,DETECTED_VBUS_PAD1,DETECTED_VBUS_PAD2,Disabled"
|
|
bitfld.long 0x00 3.--5. " CONTROLLER2_OC_PIN ,CONTROLLER2 OC PIN" "DETECTED0,DETECTED1,DETECTED2,DETECTED3,DETECTED_VBUS_PAD0,DETECTED_VBUS_PAD1,DETECTED_VBUS_PAD2,Disabled"
|
|
bitfld.long 0x00 0.--2. " CONTROLLER1_OC_PIN ,CONTROLLER1 OC PIN" "DETECTED0,DETECTED1,DETECTED2,DETECTED3,DETECTED_VBUS_PAD0,DETECTED_VBUS_PAD1,DETECTED_VBUS_PAD2,Disabled"
|
|
line.long 0x04 "USB2_OC_MAP_0,XUSB PADCTL USB2 OC MAP 0"
|
|
bitfld.long 0x04 6.--8. " CONTROLLER3_OC_PIN ,CONTROLLER3 OC PIN" "DETECTED0,DETECTED1,DETECTED2,DETECTED3,DETECTED_VBUS_PAD0,DETECTED_VBUS_PAD1,DETECTED_VBUS_PAD2,Disabled"
|
|
bitfld.long 0x04 3.--5. " CONTROLLER2_OC_PIN ,CONTROLLER2 OC PIN" "DETECTED0,DETECTED1,DETECTED2,DETECTED3,DETECTED_VBUS_PAD0,DETECTED_VBUS_PAD1,DETECTED_VBUS_PAD2,Disabled"
|
|
bitfld.long 0x04 0.--2. " CONTROLLER1_OC_PIN ,CONTROLLER1 OC PIN" "DETECTED0,DETECTED1,DETECTED2,DETECTED3,DETECTED_VBUS_PAD0,DETECTED_VBUS_PAD1,DETECTED_VBUS_PAD2,Disabled"
|
|
line.long 0x08 "SS_PORT_MAP_0,XUSB PADCTL SS PORT MAP 0"
|
|
bitfld.long 0x08 7. " PORT1_INTERNAL ,PORT1 INTERNAL" "No,Yes"
|
|
bitfld.long 0x08 4.--6. " PORT1_MAP ,PORT1 MAP" "USB2_PORT0,USB2_PORT1,USB2_PORT2,,,,,INIT_DISABLED"
|
|
bitfld.long 0x08 3. " PORT0_INTERNAL ,PORT0 INTERNAL" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " PORT0_MAP ,PORT0 MAP" "USB2_PORT0,USB2_PORT1,USB2_PORT2,,,,,INIT_DISABLED"
|
|
textline " "
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "OC_DET_0,XUSB PADCTL OC DET 0"
|
|
bitfld.long 0x00 30. " OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD2 ,OC DETECTED INTERRUPT ENABLE VBUSPAD2" "No,Yes"
|
|
bitfld.long 0x00 29. " OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD1 ,OC DETECTED INTERRUPT ENABLE VBUSPAD1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " OC_DETECTED_INTERRUPT_ENABLE_VBUSPAD0 ,OC DETECTED INTERRUPT ENABLE VBUSPAD0" "No,Yes"
|
|
bitfld.long 0x00 27. " OC_DETECTED_INTERRUPT_ENABLE3 ,OC DETECTED INTERRUPT ENABLE 3" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OC_DETECTED_INTERRUPT_ENABLE2 ,OC DETECTED INTERRUPT ENABLE 2" "No,Yes"
|
|
bitfld.long 0x00 25. " OC_DETECTED_INTERRUPT_ENABLE1 ,OC DETECTED INTERRUPT ENABLE 1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24. " OC_DETECTED_INTERRUPT_ENABLE_0 ,OC DETECTED INTERRUPT ENABLE 0" "No,Yes"
|
|
bitfld.long 0x00 22. " OC_DETECTED_VBUS_PAD2 ,OC DETECTED VBUS PAD2" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 21. " OC_DETECTED_VBUS_PAD1 ,OC DETECTED VBUS PAD1" "No,Yes"
|
|
bitfld.long 0x00 20. " OC_DETECTED_VBUS_PAD0 ,OC DETECTED VBUS PAD0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " OC_DETECTED3 ,OC DETECTED 3" "No,Yes"
|
|
bitfld.long 0x00 18. " OC_DETECTED2 ,OC DETECTED 2" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " OC_DETECTED1 ,OC DETECTED 1" "No,Yes"
|
|
bitfld.long 0x00 16. " OC_DETECTED0 ,OC DETECTED 0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. " VBUS_ENABLE1_OC_MAP ,VBUS_ENABLE1_OC_MAP" "DETECTED0,DETECTED1,DETECTED2,DETECTED3,DETECTED_VBUS_PAD0,DETECTED_VBUS_PAD1,DETECTED_VBUS_PAD2,Disabled"
|
|
bitfld.long 0x00 10.--12. " VBUS_ENABLE0_OC_MAP ,VBUS_ENABLE0_OC_MAP" "DETECTED0,DETECTED1,DETECTED2,DETECTED3,DETECTED_VBUS_PAD0,DETECTED_VBUS_PAD1,DETECTED_VBUS_PAD2,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VBUS_ENABLE1 ,VBUS ENABLE 1" "No,Yes"
|
|
bitfld.long 0x00 8. " VBUS_ENABLE0 ,VBUS ENABLE 0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " VBUS_ENABLE2_OC_MAP ,VBUS_ENABLE1_OC_MAP" "DETECTED0,DETECTED1,DETECTED2,DETECTED3,DETECTED_VBUS_PAD0,DETECTED_VBUS_PAD1,DETECTED_VBUS_PAD2,Disabled"
|
|
bitfld.long 0x00 4. " VBUS_ENABLE2 ,VBUS ENABLE2" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SET_OC_DETECTED3 ,SET OC DETECTED3" "No,Yes"
|
|
bitfld.long 0x00 2. " SET_OC_DETECTED2 ,SET OC DETECTED2" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SET_OC_DETECTED1 ,SET OC DETECTED1" "No,Yes"
|
|
bitfld.long 0x00 0. " SET_OC_DETECTED0 ,SET OC DETECTED0" "No,Yes"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ELPG_PROGRAM_0,XUSB PADCTL ELPG PROGRAM 0"
|
|
bitfld.long 0x00 26. " AUX_MUX_LP0_VCORE_DOWN ,AUX MUX LP0 VCORE DOWN" "No,Yes"
|
|
bitfld.long 0x00 25. " AUX_MUX_LP0_CLAMP_EN_EARLY ,AUX MUX LP0 CLAMP EN EARLY" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24. " AUX_MUX_LP0_CLAMP_EN ,AUX MUX LP0 CLAMP EN" "No,Yes"
|
|
bitfld.long 0x00 22. " SSP1_ELPG_VCORE_DOWN ,SSP1 ELPG VCORE DOWN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SSP1_ELPG_CLAMP_EN_EARLY ,SSP1 ELPG CLAMP EN EARLY" "No,Yes"
|
|
bitfld.long 0x00 20. " SSP1_ELPG_CLAMP_EN ,SSP1 ELPG CLAMP EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SSP0_ELPG_VCORE_DOWN ,SSP0 ELPG VCORE DOWN" "No,Yes"
|
|
bitfld.long 0x00 17. " SSP0_ELPG_CLAMP_EN_EARLY ,SSP0 ELPG CLAMP EN EARLY" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSP0_ELPG_CLAMP_EN ,SSP0 ELPG CLAMP EN" "No,Yes"
|
|
bitfld.long 0x00 15. " SS_PORT1_WAKEUP_EVENT ,SS_PORT1_WAKEUP_EVENT" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SS_PORT0_WAKEUP_EVENT ,SS_PORT0_WAKEUP_EVENT" "No,Yes"
|
|
bitfld.long 0x00 12. " USB2_HSIC_PORT1_WAKEUP_EVENT ,USB2 HSIC PORT1 WAKEUP EVENT" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " USB2_HSIC_PORT0_WAKEUP_EVENT ,USB2 HSIC PORT0 WAKEUP EVENT" "No,Yes"
|
|
bitfld.long 0x00 10. " USB2_PORT2_WAKEUP_EVENT ,USB2 PORT2 WAKEUP EVENT" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " USB2_PORT1_WAKEUP_EVENT ,USB2 PORT1 WAKEUP EVENT" "No,Yes"
|
|
bitfld.long 0x00 8. " USB2_PORT0_WAKEUP_EVENT ,USB2 PORT0 WAKEUP EVENT" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SS_PORT1_WAKE_INTERRUPT_ENABLE ,SS PORT1 WAKE INTERRUPT ENABLE" "No,Yes"
|
|
bitfld.long 0x00 6. " SS_PORT0_WAKE_INTERRUPT_ENABLE ,SS PORT0 WAKE INTERRUPT ENABLE" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " USB2_HSIC_PORT1_WAKE_INTERRUPT_ENABLE ,USB2 HSIC PORT1 WAKE INTERRUPT ENABLE" "No,Yes"
|
|
bitfld.long 0x00 3. " USB2_HSIC_PORT0_WAKE_INTERRUPT_ENABLE ,USB2 HSIC PORT0 WAKE INTERRUPT ENABLE" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " USB2_PORT2_WAKE_INTERRUPT_ENABLE ,USB2 PORT2 WAKE INTERRUPT ENABLE" "No,Yes"
|
|
bitfld.long 0x00 1. " USB2_PORT1_WAKE_INTERRUPT_ENABLE ,USB2 PORT1 WAKE INTERRUPT ENABLE" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " USB2_PORT0_WAKE_INTERRUPT_ENABLE ,USB2 PORT0 WAKE INTERRUPT ENABLE" "No,Yes"
|
|
width 17.
|
|
tree "USB2_BATTERY_CHRG"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "OTGPAD0_CTL0_0,XUSB PADCTL USB2 BATTERY CHRG OTGPAD0 CTL0 0"
|
|
bitfld.long 0x00 31. " GENERATE_SRP ,GENERATE SRP" "No,Yes"
|
|
bitfld.long 0x00 30. " SRP_INTR_EN ,SRP INTR EN" "No,Yes"
|
|
bitfld.long 0x00 29. " SRP_DETECTED ,SRP DETECTED" "No,Yes"
|
|
bitfld.long 0x00 28. " SRP_DETECT_EN ,SRP DETECT EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DCD_INTR_EN ,DCD INTR EN" "No,Yes"
|
|
bitfld.long 0x00 26. " DCD_DETECTED ,DCD DETECTED" "No,Yes"
|
|
bitfld.long 0x00 25. " ZIN_FILTER_EN ,ZIN FILTER EN" "No,Yes"
|
|
bitfld.long 0x00 24. " ZIN_CHNG_INTR_EN ,ZIN CHNG INTR EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ZIN_ST_CHNG ,ZIN ST CHNG" "No,Yes"
|
|
rbitfld.long 0x00 22. " ZIN ,ZIN" "No,Yes"
|
|
bitfld.long 0x00 21. " ZIP_FILTER_EN ,ZIP FILTER EN" "No,Yes"
|
|
bitfld.long 0x00 20. " ZIP_CHNG_INTR_EN ,ZIP CHNG INTR EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ZIP_ST_CHNG ,ZIP ST CHNG" "No,Yes"
|
|
rbitfld.long 0x00 18. " ZIP ,ZIP" "No,Yes"
|
|
bitfld.long 0x00 17. " USBON_RPU ,USBON RPU" "No,Yes"
|
|
bitfld.long 0x00 16. " USBON_RPD ,USBON RPD" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBOP_RPU ,USBOP RPU" "No,Yes"
|
|
bitfld.long 0x00 14. " USBOP_RPD ,USBOP RPD" "No,Yes"
|
|
bitfld.long 0x00 13. " OP_I_SRC_EN ,OP I SRC EN" "No,Yes"
|
|
bitfld.long 0x00 12. " ON_SRC_EN ,ON SRC EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ON_SINK_EN ,ON SINK EN" "No,Yes"
|
|
bitfld.long 0x00 10. " OP_SRC_EN ,OP SRC EN" "No,Yes"
|
|
bitfld.long 0x00 9. " OP_SINK_EN ,OP SINK EN" "No,Yes"
|
|
bitfld.long 0x00 8. " VDAT_DET_FILTER_EN ,VDAT DET FILTER EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VDAT_DET_CHNG_INTR_EN ,VDAT DET CHNG INTR EN" "No,Yes"
|
|
bitfld.long 0x00 6. " VDAT_DET_ST_CHNG ,VDAT DET ST CHNG" "No,Yes"
|
|
rbitfld.long 0x00 5. " VDAT_DET ,VDAT DET" "No,Yes"
|
|
bitfld.long 0x00 4. " VDCD_DET_FILTER_EN ,VDCD DET FILTER EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VDCD_DET_CHNG_INTR_EN ,VDCD DET CHNG INTR EN" "No,Yes"
|
|
bitfld.long 0x00 2. " VDCD_DET_ST_CHNG ,VDCD DET ST CHNG" "No,Yes"
|
|
rbitfld.long 0x00 1. " VDCD_DET ,VDCD DET" "No,Yes"
|
|
bitfld.long 0x00 0. " PD_CHG ,PD CHG" "No,Yes"
|
|
group.long (0x20+0x04)++0x03
|
|
line.long 0x00 "OTGPAD0_CTL1_0,XUSB PADCTL USB2 BATTERY CHRG OTGPAD0 CTL1"
|
|
bitfld.long 0x00 4. " DIV_DET_EN ,DIV DET EN" "No,Yes"
|
|
rbitfld.long 0x00 3. " VOP_DIV2P7_DET ,VOP DIV2P7 DET" "No,Yes"
|
|
rbitfld.long 0x00 2. " VOP_DIV2P0_DET ,VOP DIV2P0 DET" "No,Yes"
|
|
rbitfld.long 0x00 1. " VON_DIV2P7_DET ,VON DIV2P7 DET" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " VON_DIV2P0_DET ,VON DIV2P0 DET" "No,Yes"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "OTGPAD1_CTL0_0,XUSB PADCTL USB2 BATTERY CHRG OTGPAD1 CTL0 0"
|
|
bitfld.long 0x00 31. " GENERATE_SRP ,GENERATE SRP" "No,Yes"
|
|
bitfld.long 0x00 30. " SRP_INTR_EN ,SRP INTR EN" "No,Yes"
|
|
bitfld.long 0x00 29. " SRP_DETECTED ,SRP DETECTED" "No,Yes"
|
|
bitfld.long 0x00 28. " SRP_DETECT_EN ,SRP DETECT EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DCD_INTR_EN ,DCD INTR EN" "No,Yes"
|
|
bitfld.long 0x00 26. " DCD_DETECTED ,DCD DETECTED" "No,Yes"
|
|
bitfld.long 0x00 25. " ZIN_FILTER_EN ,ZIN FILTER EN" "No,Yes"
|
|
bitfld.long 0x00 24. " ZIN_CHNG_INTR_EN ,ZIN CHNG INTR EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ZIN_ST_CHNG ,ZIN ST CHNG" "No,Yes"
|
|
rbitfld.long 0x00 22. " ZIN ,ZIN" "No,Yes"
|
|
bitfld.long 0x00 21. " ZIP_FILTER_EN ,ZIP FILTER EN" "No,Yes"
|
|
bitfld.long 0x00 20. " ZIP_CHNG_INTR_EN ,ZIP CHNG INTR EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ZIP_ST_CHNG ,ZIP ST CHNG" "No,Yes"
|
|
rbitfld.long 0x00 18. " ZIP ,ZIP" "No,Yes"
|
|
bitfld.long 0x00 17. " USBON_RPU ,USBON RPU" "No,Yes"
|
|
bitfld.long 0x00 16. " USBON_RPD ,USBON RPD" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBOP_RPU ,USBOP RPU" "No,Yes"
|
|
bitfld.long 0x00 14. " USBOP_RPD ,USBOP RPD" "No,Yes"
|
|
bitfld.long 0x00 13. " OP_I_SRC_EN ,OP I SRC EN" "No,Yes"
|
|
bitfld.long 0x00 12. " ON_SRC_EN ,ON SRC EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ON_SINK_EN ,ON SINK EN" "No,Yes"
|
|
bitfld.long 0x00 10. " OP_SRC_EN ,OP SRC EN" "No,Yes"
|
|
bitfld.long 0x00 9. " OP_SINK_EN ,OP SINK EN" "No,Yes"
|
|
bitfld.long 0x00 8. " VDAT_DET_FILTER_EN ,VDAT DET FILTER EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VDAT_DET_CHNG_INTR_EN ,VDAT DET CHNG INTR EN" "No,Yes"
|
|
bitfld.long 0x00 6. " VDAT_DET_ST_CHNG ,VDAT DET ST CHNG" "No,Yes"
|
|
rbitfld.long 0x00 5. " VDAT_DET ,VDAT DET" "No,Yes"
|
|
bitfld.long 0x00 4. " VDCD_DET_FILTER_EN ,VDCD DET FILTER EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VDCD_DET_CHNG_INTR_EN ,VDCD DET CHNG INTR EN" "No,Yes"
|
|
bitfld.long 0x00 2. " VDCD_DET_ST_CHNG ,VDCD DET ST CHNG" "No,Yes"
|
|
rbitfld.long 0x00 1. " VDCD_DET ,VDCD DET" "No,Yes"
|
|
bitfld.long 0x00 0. " PD_CHG ,PD CHG" "No,Yes"
|
|
group.long (0x28+0x04)++0x03
|
|
line.long 0x00 "OTGPAD1_CTL1_0,XUSB PADCTL USB2 BATTERY CHRG OTGPAD1 CTL1"
|
|
bitfld.long 0x00 4. " DIV_DET_EN ,DIV DET EN" "No,Yes"
|
|
rbitfld.long 0x00 3. " VOP_DIV2P7_DET ,VOP DIV2P7 DET" "No,Yes"
|
|
rbitfld.long 0x00 2. " VOP_DIV2P0_DET ,VOP DIV2P0 DET" "No,Yes"
|
|
rbitfld.long 0x00 1. " VON_DIV2P7_DET ,VON DIV2P7 DET" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " VON_DIV2P0_DET ,VON DIV2P0 DET" "No,Yes"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "OTGPAD2_CTL0_0,XUSB PADCTL USB2 BATTERY CHRG OTGPAD2 CTL0 0"
|
|
bitfld.long 0x00 31. " GENERATE_SRP ,GENERATE SRP" "No,Yes"
|
|
bitfld.long 0x00 30. " SRP_INTR_EN ,SRP INTR EN" "No,Yes"
|
|
bitfld.long 0x00 29. " SRP_DETECTED ,SRP DETECTED" "No,Yes"
|
|
bitfld.long 0x00 28. " SRP_DETECT_EN ,SRP DETECT EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DCD_INTR_EN ,DCD INTR EN" "No,Yes"
|
|
bitfld.long 0x00 26. " DCD_DETECTED ,DCD DETECTED" "No,Yes"
|
|
bitfld.long 0x00 25. " ZIN_FILTER_EN ,ZIN FILTER EN" "No,Yes"
|
|
bitfld.long 0x00 24. " ZIN_CHNG_INTR_EN ,ZIN CHNG INTR EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ZIN_ST_CHNG ,ZIN ST CHNG" "No,Yes"
|
|
rbitfld.long 0x00 22. " ZIN ,ZIN" "No,Yes"
|
|
bitfld.long 0x00 21. " ZIP_FILTER_EN ,ZIP FILTER EN" "No,Yes"
|
|
bitfld.long 0x00 20. " ZIP_CHNG_INTR_EN ,ZIP CHNG INTR EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ZIP_ST_CHNG ,ZIP ST CHNG" "No,Yes"
|
|
rbitfld.long 0x00 18. " ZIP ,ZIP" "No,Yes"
|
|
bitfld.long 0x00 17. " USBON_RPU ,USBON RPU" "No,Yes"
|
|
bitfld.long 0x00 16. " USBON_RPD ,USBON RPD" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USBOP_RPU ,USBOP RPU" "No,Yes"
|
|
bitfld.long 0x00 14. " USBOP_RPD ,USBOP RPD" "No,Yes"
|
|
bitfld.long 0x00 13. " OP_I_SRC_EN ,OP I SRC EN" "No,Yes"
|
|
bitfld.long 0x00 12. " ON_SRC_EN ,ON SRC EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ON_SINK_EN ,ON SINK EN" "No,Yes"
|
|
bitfld.long 0x00 10. " OP_SRC_EN ,OP SRC EN" "No,Yes"
|
|
bitfld.long 0x00 9. " OP_SINK_EN ,OP SINK EN" "No,Yes"
|
|
bitfld.long 0x00 8. " VDAT_DET_FILTER_EN ,VDAT DET FILTER EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VDAT_DET_CHNG_INTR_EN ,VDAT DET CHNG INTR EN" "No,Yes"
|
|
bitfld.long 0x00 6. " VDAT_DET_ST_CHNG ,VDAT DET ST CHNG" "No,Yes"
|
|
rbitfld.long 0x00 5. " VDAT_DET ,VDAT DET" "No,Yes"
|
|
bitfld.long 0x00 4. " VDCD_DET_FILTER_EN ,VDCD DET FILTER EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VDCD_DET_CHNG_INTR_EN ,VDCD DET CHNG INTR EN" "No,Yes"
|
|
bitfld.long 0x00 2. " VDCD_DET_ST_CHNG ,VDCD DET ST CHNG" "No,Yes"
|
|
rbitfld.long 0x00 1. " VDCD_DET ,VDCD DET" "No,Yes"
|
|
bitfld.long 0x00 0. " PD_CHG ,PD CHG" "No,Yes"
|
|
group.long (0x30+0x04)++0x03
|
|
line.long 0x00 "OTGPAD2_CTL1_0,XUSB PADCTL USB2 BATTERY CHRG OTGPAD2 CTL1"
|
|
bitfld.long 0x00 4. " DIV_DET_EN ,DIV DET EN" "No,Yes"
|
|
rbitfld.long 0x00 3. " VOP_DIV2P7_DET ,VOP DIV2P7 DET" "No,Yes"
|
|
rbitfld.long 0x00 2. " VOP_DIV2P0_DET ,VOP DIV2P0 DET" "No,Yes"
|
|
rbitfld.long 0x00 1. " VON_DIV2P7_DET ,VON DIV2P7 DET" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " VON_DIV2P0_DET ,VON DIV2P0 DET" "No,Yes"
|
|
textline " "
|
|
group.long 0x38++0x7
|
|
line.long 0x00 "BIASPAD_0,XUSB PADCTL USB2 BATTERY CHRG BIASPAD"
|
|
bitfld.long 0x00 20. " ID_OVERRIDE ,ID OVERRIDE" "No,Yes"
|
|
bitfld.long 0x00 18.--19. " ID_SOURCE_SELECT ,ID SOURCE SELECT" "NO_OVERRIDE,GPIO,VBUS_OVERRIDE,?..."
|
|
bitfld.long 0x00 17. " VBUS_OVERRIDE ,VBUS OVERRIDE" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15.--16. " VBUS_SOURCE_SELECT ,VBUS SOURCE SELECT" "NO_OVERRIDE,GPIO,VBUS_OVERRIDE,?..."
|
|
bitfld.long 0x00 14. " ID_CONNECT_CHNG_INTR_EN ,ID CONNECT CHNG INTR EN" "No,Yes"
|
|
bitfld.long 0x00 13. " ID_CONNECT_ST_CHNG ,ID CONNECT ST CHNG" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ID_CONNECT_STATUS ,ID CONNECT STATUS" "No,Yes"
|
|
rbitfld.long 0x00 11. " IDDIG_C ,IDDIG C" "No,Yes"
|
|
rbitfld.long 0x00 10. " IDDIG_B ,IDDIG B" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " IDDIG_A ,IDDIG A" "No,Yes"
|
|
rbitfld.long 0x00 8. " IDDIG ,IDDIG" "No,Yes"
|
|
bitfld.long 0x00 6. " VBUS_VLD_CHNG_INTR_EN ,VBUS_VLD_CHNG_INTR_EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VBUS_VLD_ST_CHNG ,VBUS_VLD_ST_CHNG" "No,Yes"
|
|
rbitfld.long 0x00 4. " VBUS_VLD ,VBUS VLD" "No,Yes"
|
|
bitfld.long 0x00 3. " OTG_VBUS_SESS_VLD_CHNG_INTR_EN ,OTG VBUS SESS VLD CHNG INTR EN" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OTG_VBUS_SESS_VLD_ST_CHNG ,OTG VBUS SESS VLD ST CHNG" "No,Yes"
|
|
rbitfld.long 0x00 1. " OTG_VBUS_SESS_VLD ,OTG VBUS SESS VLD" "No,Yes"
|
|
bitfld.long 0x00 0. " PD_OTG ,PD OTG" "No,Yes"
|
|
line.long 0x04 "TDCD_DBNC_TIMER_0,XUSB PADCTL USB2 BATTERY CHRG TDCD DBNC TIMER 0"
|
|
hexmask.long.word 0x04 0.--10. 1. " TDCD_DBNC ,TDCD DBNC"
|
|
tree.end
|
|
width 23.
|
|
tree "IOPHY_MISC_PAD_P(0..1)_CTL"
|
|
group.long 0x40++0x2F
|
|
line.long 0x00 "PLL_P0_CTL1_0,USB3/PCIE PLL0 control signals"
|
|
bitfld.long 0x00 28.--29. " PLL1_REFCLK_NDIV ,PLL1 REFCLK NDIV" "0,1,2,3"
|
|
rbitfld.long 0x00 27. " PLL1_LOCKDET ,PLL1 LOCKDET" "0,1"
|
|
bitfld.long 0x00 24. " PLL1_MODE ,PLL1 MODE" "0,1"
|
|
bitfld.long 0x00 20.--21. " PLL0_REFCLK_NDIV ,PLL0 REFCLK NDIV" "0,1,2,3"
|
|
rbitfld.long 0x00 19. " PLL0_LOCKDET ,PLL0 LOCKDET" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PLL0_MODE ,PLL0 MODE" "0,1"
|
|
bitfld.long 0x00 12.--15. " REFCLK_SEL ,REFCLK SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. " REFCLK_TERM100 ,REFCLK TERM100" "0,1"
|
|
bitfld.long 0x00 9. " PLL_CKBUFPD_OVR ,PLL CKBUFPD OVR" "0,1"
|
|
bitfld.long 0x00 8. " PLL_CKBUFPD_M ,PLL CKBUFPD M" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLL_CKBUFPD_BL ,PLL CKBUFPD BL" "0,1"
|
|
bitfld.long 0x00 6. " PLL_CKBUFPD_BR ,PLL CKBUFPD BR" "0,1"
|
|
bitfld.long 0x00 5. " PLL_CKBUFPD_TL ,PLL CKBUFPD TL" "0,1"
|
|
bitfld.long 0x00 4. " PLL_CKBUFPD_TR ,PLL CKBUFPD TR" "0,1"
|
|
bitfld.long 0x00 3. " PLL_PWR_OVRD ,PLL PWR OVRD" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PLL_EMULATION_RST ,PLL EMULATION RST" "0,1"
|
|
bitfld.long 0x00 1. " PLL_RST ,PLL RST" "0,1"
|
|
bitfld.long 0x00 0. " PLL_IDDQ ,PLL IDDQ" "0,1"
|
|
line.long 0x04 "PLL_P0_CTL2_0,XUSB PADCTL IOPHY PLL P0 CTL2"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PLL_MISC_OUT ,PLL_MISC_OUT"
|
|
bitfld.long 0x04 20.--23. " PLL1_CP_CNTL ,PLL1 CP CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " PLL0_CP_CNTL ,PLL0 CP CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 15. " PLL_BYPASS_EN ,PLL BYPASS EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 13. " PLL_EMULATION_ON ,PLL EMULATION ON" "0,1"
|
|
bitfld.long 0x04 12. " TCLKOUT_EN ,TCLKOUT EN" "0,1"
|
|
bitfld.long 0x04 8.--11. " TCLKOUT_SEL ,TCLKOUT SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 7. " XDIGCLK4P5_EN ,XDIGCLK4P5 EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 6. " REFCLKBUF_EN ,REFCLKBUF EN" "0,1"
|
|
bitfld.long 0x04 5. " TXCLKREF_EN ,TXCLKREF EN" "0,1"
|
|
bitfld.long 0x04 4. " TXCLKREF_SEL ,TXCLKREF SEL" "0,1"
|
|
bitfld.long 0x04 3. " XDIGCLK_EN ,XDIGCLK EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " XDIGCLK_SEL ,XDIGCLK SEL" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "PLL_P0_CTL3_0,XUSB PADCTL IOPHY PLL P0 CTL3 0"
|
|
bitfld.long 0x08 28.--31. " PLL_TEMP_CNTL ,PLL TEMP CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 20.--25. " PLL_BW_CNTL ,PLL BW CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 16.--17. " PLL_BGAP_CNTL ,PLL BGAP CNTL" "0,1,2,3"
|
|
rbitfld.long 0x08 15. " RCAL_DONE ,RCAL DONE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 14. " RCAL_RESET ,RCAL RESET" "0,1"
|
|
rbitfld.long 0x08 8.--12. " RCAL_VAL ,RCAL VAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 7. " RCAL_BYPASS ,RCAL BYPASS" "0,1"
|
|
bitfld.long 0x08 0.--4. " RCAL_CODE ,RCAL CODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "PLL_P0_CTL4_0,XUSB PADCTL IOPHY PLL P0 CTL4 0"
|
|
hexmask.long.word 0x0C 0.--11. 1. " PLL_MISC_CNTL ,PLL MISC CNTL"
|
|
line.long 0x10 "USB3_PAD0_CTL_1_0,XUSB PADCTL IOPHY USB3 PAD0 CTL 1"
|
|
bitfld.long 0x10 21.--22. " RX_DIV ,RX_DIV" "0,1,2,3"
|
|
bitfld.long 0x10 19.--20. " TX_DIV ,TX_DIV" "0,1,2,3"
|
|
bitfld.long 0x10 15.--18. " TX_DRV_CNTL ,TX_DRV_CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x10 11.--14. " TX_CMADJ ,TX_CMADJ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 5.--10. " TX_AMP ,TX_AMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x10 3.--4. " RX_RATE ,RX_RATE" "0,1,2,3"
|
|
bitfld.long 0x10 1.--2. " TX_RATE ,TX_RATE" "0,1,2,3"
|
|
bitfld.long 0x10 0. " RATE_MODE ,RATE_MODE" "0,1"
|
|
line.long 0x14 "USB3_PAD1_CTL_1_0,XUSB PADCTL IOPHY USB3 PAD0 CTL 2"
|
|
bitfld.long 0x14 21.--22. " RX_DIV ,RX_DIV" "0,1,2,3"
|
|
bitfld.long 0x14 19.--20. " TX_DIV ,TX_DIV" "0,1,2,3"
|
|
bitfld.long 0x14 15.--18. " TX_DRV_CNTL ,TX_DRV_CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x14 11.--14. " TX_CMADJ ,TX_CMADJ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 5.--10. " TX_AMP ,TX_AMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x14 3.--4. " RX_RATE ,RX_RATE" "0,1,2,3"
|
|
bitfld.long 0x14 1.--2. " TX_RATE ,TX_RATE" "0,1,2,3"
|
|
bitfld.long 0x14 0. " RATE_MODE ,RATE_MODE" "0,1"
|
|
line.long 0x18 "USB3_PAD0_CTL_2_0,XUSB PADCTL IOPHY USB3 PAD0 CTL 2"
|
|
hexmask.long.byte 0x18 24.--31. 1. " CDR_CNTL ,CDR CNTL"
|
|
hexmask.long.word 0x18 8.--23. 1. " RX_EQ ,RX EQ"
|
|
bitfld.long 0x18 4.--7. " RX_WANDER ,RX WANDER" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 2.--3. " RX_TERM_CNTL ,RX TERM CNTL" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x18 0.--1. " TX_TERM_CNTL ,TX TERM CNTL" "0,1,2,3"
|
|
line.long 0x1C "USB3_PAD1_CTL_2_0,XUSB PADCTL IOPHY USB3 PAD0 CTL 2"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " CDR_CNTL ,CDR CNTL"
|
|
hexmask.long.word 0x1C 8.--23. 1. " RX_EQ ,RX EQ"
|
|
bitfld.long 0x1C 4.--7. " RX_WANDER ,RX WANDER" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 2.--3. " RX_TERM_CNTL ,RX TERM CNTL" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--1. " TX_TERM_CNTL ,TX TERM CNTL" "0,1,2,3"
|
|
line.long 0x20 "USB3_PAD0_CTL_3_0,XUSB PADCTL IOPHY USB3 PAD0 CTL 3"
|
|
hexmask.long.word 0x20 0.--15. 1. " EOM_CNTL ,EOM CNTL"
|
|
line.long 0x24 "USB3_PAD1_CTL_3_0,XUSB PADCTL IOPHY USB3 PAD1 CTL 3"
|
|
hexmask.long.word 0x24 0.--15. 1. " EOM_CNTL ,EOM CNTL"
|
|
line.long 0x28 "USB3_PAD0_CTL_4_0,XUSB PADCTL IOPHY USB3 PAD0 CTL 4"
|
|
line.long 0x2C "USB3_PAD1_CTL_4_0,XUSB PADCTL IOPHY USB3 PAD1 CTL 4"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MISC_PAD_P0_CTL_1_0,XUSB PADCTL IOPHY MISC PAD P0 CTL 1"
|
|
bitfld.long 0x00 27. " RX_PWR_OVRD ,RX PWR OVRD" "0,1"
|
|
bitfld.long 0x00 26. " TX_PWR_OVRD ,TX PWR OVRD" "0,1"
|
|
bitfld.long 0x00 25. " RATE_MODE_OVRD ,RATE MODE OVRD" "0,1"
|
|
bitfld.long 0x00 24. " RATE_MODE ,RATE MODE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RX_DIV ,RX DIV" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " TX_DIV ,TX DIV" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " RX_RATE ,RX RATE" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " TX_RATE ,TX RATE" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TX_RDET ,TX RDET" "0,1"
|
|
rbitfld.long 0x00 13. " TX_STAT_PRESENT ,TX STAT PRESENT" "0,1"
|
|
rbitfld.long 0x00 12. " RX_STAT_IDLE ,RX STAT IDLE" "0,1"
|
|
bitfld.long 0x00 11. " RX_DATA_EN ,RX DATA EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RX_DATA_READY ,RX DATA READY" "0,1"
|
|
bitfld.long 0x00 8.--9. " RX_SLEEP ,RX SLEEP" "0,1,2,3"
|
|
bitfld.long 0x00 7. " TX_DATA_EN ,TX DATA EN" "0,1"
|
|
bitfld.long 0x00 6. " TX_DATA_READY ,TX DATA READY" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TX_SLEEP ,TX SLEEP" "0,1,2,3"
|
|
bitfld.long 0x00 3. " CKBUFPD_OVRD ,CKBUFPD OVRD" "0,1"
|
|
bitfld.long 0x00 2. " CKBUFPD ,CKBUFPD" "0,1"
|
|
bitfld.long 0x00 1. " IDDQ_OVRD ,IDDQ OVRD" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDDQ ,IDDQ" "0,1"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MISC_PAD_P1_CTL_1_0,XUSB PADCTL IOPHY MISC PAD P0 CTL 1"
|
|
bitfld.long 0x00 27. " RX_PWR_OVRD ,RX PWR OVRD" "0,1"
|
|
bitfld.long 0x00 26. " TX_PWR_OVRD ,TX PWR OVRD" "0,1"
|
|
bitfld.long 0x00 25. " RATE_MODE_OVRD ,RATE MODE OVRD" "0,1"
|
|
bitfld.long 0x00 24. " RATE_MODE ,RATE MODE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RX_DIV ,RX DIV" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " TX_DIV ,TX DIV" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " RX_RATE ,RX RATE" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " TX_RATE ,TX RATE" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TX_RDET ,TX RDET" "0,1"
|
|
rbitfld.long 0x00 13. " TX_STAT_PRESENT ,TX STAT PRESENT" "0,1"
|
|
rbitfld.long 0x00 12. " RX_STAT_IDLE ,RX STAT IDLE" "0,1"
|
|
bitfld.long 0x00 11. " RX_DATA_EN ,RX DATA EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RX_DATA_READY ,RX DATA READY" "0,1"
|
|
bitfld.long 0x00 8.--9. " RX_SLEEP ,RX SLEEP" "0,1,2,3"
|
|
bitfld.long 0x00 7. " TX_DATA_EN ,TX DATA EN" "0,1"
|
|
bitfld.long 0x00 6. " TX_DATA_READY ,TX DATA READY" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TX_SLEEP ,TX SLEEP" "0,1,2,3"
|
|
bitfld.long 0x00 3. " CKBUFPD_OVRD ,CKBUFPD OVRD" "0,1"
|
|
bitfld.long 0x00 2. " CKBUFPD ,CKBUFPD" "0,1"
|
|
bitfld.long 0x00 1. " IDDQ_OVRD ,IDDQ OVRD" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDDQ ,IDDQ" "0,1"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "MISC_PAD_P0_CTL_2_0,XUSB PADCTL IOPHY MISC PAD P0 CTL 2"
|
|
rbitfld.long 0x00 30.--31. " SPARE_OUT ,SPARE OUT" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " SPARE_IN ,SPARE IN" "0,1,2,3"
|
|
bitfld.long 0x00 27. " TEST_EN ,TEST EN" "0,1"
|
|
bitfld.long 0x00 25. " PRBS_CHK_EN ,PRBS_CHK_EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SPARE_OUT ,SPARE OUT" "0,1"
|
|
bitfld.long 0x00 13. " RX_CDR_RESET ,RX CDR RESET" "0,1"
|
|
bitfld.long 0x00 12. " TX_SYNC ,TX SYNC" "0,1"
|
|
bitfld.long 0x00 11. " FED_LOOP ,FED LOOP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " TX_DATA_MODE ,TX DATA MODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " FEA_LOOP ,FEA LOOP" "0,1"
|
|
bitfld.long 0x00 4.--6. " FEA_MODE ,FEA MODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " NEA_LOOP ,NEA_LOOP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NED_LOOP ,NED_LOOP" "0,1"
|
|
bitfld.long 0x00 0.--1. " NED_MODE ,NED_MODE" "0,1,2,3"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "MISC_PAD_P1_CTL_2_0,XUSB PADCTL IOPHY MISC PAD P1 CTL 2"
|
|
rbitfld.long 0x00 30.--31. " SPARE_OUT ,SPARE OUT" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " SPARE_IN ,SPARE IN" "0,1,2,3"
|
|
bitfld.long 0x00 27. " TEST_EN ,TEST EN" "0,1"
|
|
bitfld.long 0x00 25. " PRBS_CHK_EN ,PRBS_CHK_EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SPARE_OUT ,SPARE OUT" "0,1"
|
|
bitfld.long 0x00 13. " RX_CDR_RESET ,RX CDR RESET" "0,1"
|
|
bitfld.long 0x00 12. " TX_SYNC ,TX SYNC" "0,1"
|
|
bitfld.long 0x00 11. " FED_LOOP ,FED LOOP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " TX_DATA_MODE ,TX DATA MODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " FEA_LOOP ,FEA LOOP" "0,1"
|
|
bitfld.long 0x00 4.--6. " FEA_MODE ,FEA MODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " NEA_LOOP ,NEA_LOOP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NED_LOOP ,NED_LOOP" "0,1"
|
|
bitfld.long 0x00 0.--1. " NED_MODE ,NED_MODE" "0,1,2,3"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "MISC_PAD_P0_CTL_3_0,XUSB PADCTL IOPHY MISC PAD P0 CTL 3"
|
|
hexmask.long.word 0x00 20.--31. 1. " CDR_TEST ,CDR TEST"
|
|
bitfld.long 0x00 19. " RX_IDLE_MODE_OVRD ,RX IDLE MODE OVRD" "0,1"
|
|
bitfld.long 0x00 18. " RX_IDLE_MODE ,RX IDLE MODE" "0,1"
|
|
bitfld.long 0x00 17. " RX_IDLE_BYP ,RX IDLE BYP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TX_RDET_BYP ,TX RDET BYP" "0,1"
|
|
bitfld.long 0x00 14.--15. " RX_IDLE_T ,RX IDLE T" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " TX_RDET_T ,TX RDET T" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. " TX_SEL_LOAD ,TX SEL LOAD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MISC_CNTL ,MISC CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "MISC_PAD_P1_CTL_3_0,XUSB PADCTL IOPHY MISC PAD P1 CTL 3"
|
|
hexmask.long.word 0x00 20.--31. 1. " CDR_TEST ,CDR TEST"
|
|
bitfld.long 0x00 19. " RX_IDLE_MODE_OVRD ,RX IDLE MODE OVRD" "0,1"
|
|
bitfld.long 0x00 18. " RX_IDLE_MODE ,RX IDLE MODE" "0,1"
|
|
bitfld.long 0x00 17. " RX_IDLE_BYP ,RX IDLE BYP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TX_RDET_BYP ,TX RDET BYP" "0,1"
|
|
bitfld.long 0x00 14.--15. " RX_IDLE_T ,RX IDLE T" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " TX_RDET_T ,TX RDET T" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. " TX_SEL_LOAD ,TX SEL LOAD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MISC_CNTL ,MISC CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "MISC_PAD_P0_CTL_4_0,XUSB PADCTL IOPHY MISC PAD P0 CTL 4"
|
|
rbitfld.long 0x00 31. " AUX_RX_STAT_IDLE ,AUX RX STAT IDLE" "0,1"
|
|
bitfld.long 0x00 30. " AUX_RX_IDLE_MODE ,AUX RX IDLE MODE" "0,1"
|
|
bitfld.long 0x00 29. " AUX_RX_IDLE_EN ,AUX RX IDLE EN" "0,1"
|
|
bitfld.long 0x00 28. " AUX_RX_TERM_EN ,AUX RX TERM EN" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " AUX_TX_STAT_PRESENT ,AUX TX STAT PRESENT" "0,1"
|
|
bitfld.long 0x00 26. " AUX_TX_RDET_CLK_EN ,AUX TX RDET CLK EN" "0,1"
|
|
bitfld.long 0x00 25. " AUX_TX_RDET_EN ,AUX TX RDET EN" "0,1"
|
|
bitfld.long 0x00 24. " AUX_TX_TERM_EN ,AUX TX TERM EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AUX_MODE_OVRD ,AUX MODE OVRD" "0,1"
|
|
bitfld.long 0x00 22. " AUX_HOLD_EN ,AUX HOLD EN" "0,1"
|
|
bitfld.long 0x00 21. " AUX_IDDQ_OVRD ,AUX IDDQ OVRD" "0,1"
|
|
bitfld.long 0x00 20. " AUX_IDDQ ,AUX IDDQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TX_BYP_OVRD ,TX BYP OVRD" "0,1"
|
|
bitfld.long 0x00 12. " RX_BYP_MODE ,RX BYP MODE" "0,1"
|
|
bitfld.long 0x00 11. " RX_BYP_EN ,RX BYP EN" "0,1"
|
|
bitfld.long 0x00 10. " RX_BYP_DIR ,RX BYP DIR" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " RX_BYP_IN ,RX BYP IN" "0,1"
|
|
bitfld.long 0x00 8. " RX_BYP_OUT ,RX BYP OUT" "0,1"
|
|
bitfld.long 0x00 7. " TX_BYP_EN ,TX BYP EN" "0,1"
|
|
bitfld.long 0x00 6. " TX_BYP_DIR ,TX BYP DIR" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " TX_BYP_IN ,TX BYP IN" "0,1"
|
|
bitfld.long 0x00 4. " TX_BYP_OUT ,TX BYP OUT" "0,1"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "MISC_PAD_P1_CTL_4_0,XUSB PADCTL IOPHY MISC PAD P1 CTL 4"
|
|
rbitfld.long 0x00 31. " AUX_RX_STAT_IDLE ,AUX RX STAT IDLE" "0,1"
|
|
bitfld.long 0x00 30. " AUX_RX_IDLE_MODE ,AUX RX IDLE MODE" "0,1"
|
|
bitfld.long 0x00 29. " AUX_RX_IDLE_EN ,AUX RX IDLE EN" "0,1"
|
|
bitfld.long 0x00 28. " AUX_RX_TERM_EN ,AUX RX TERM EN" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " AUX_TX_STAT_PRESENT ,AUX TX STAT PRESENT" "0,1"
|
|
bitfld.long 0x00 26. " AUX_TX_RDET_CLK_EN ,AUX TX RDET CLK EN" "0,1"
|
|
bitfld.long 0x00 25. " AUX_TX_RDET_EN ,AUX TX RDET EN" "0,1"
|
|
bitfld.long 0x00 24. " AUX_TX_TERM_EN ,AUX TX TERM EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AUX_MODE_OVRD ,AUX MODE OVRD" "0,1"
|
|
bitfld.long 0x00 22. " AUX_HOLD_EN ,AUX HOLD EN" "0,1"
|
|
bitfld.long 0x00 21. " AUX_IDDQ_OVRD ,AUX IDDQ OVRD" "0,1"
|
|
bitfld.long 0x00 20. " AUX_IDDQ ,AUX IDDQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TX_BYP_OVRD ,TX BYP OVRD" "0,1"
|
|
bitfld.long 0x00 12. " RX_BYP_MODE ,RX BYP MODE" "0,1"
|
|
bitfld.long 0x00 11. " RX_BYP_EN ,RX BYP EN" "0,1"
|
|
bitfld.long 0x00 10. " RX_BYP_DIR ,RX BYP DIR" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " RX_BYP_IN ,RX BYP IN" "0,1"
|
|
bitfld.long 0x00 8. " RX_BYP_OUT ,RX BYP OUT" "0,1"
|
|
bitfld.long 0x00 7. " TX_BYP_EN ,TX BYP EN" "0,1"
|
|
bitfld.long 0x00 6. " TX_BYP_DIR ,TX BYP DIR" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " TX_BYP_IN ,TX BYP IN" "0,1"
|
|
bitfld.long 0x00 4. " TX_BYP_OUT ,TX BYP OUT" "0,1"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "MISC_PAD_P0_CTL_5_0,XUSB PADCTL IOPHY MISC PAD P0 CTL 5"
|
|
rbitfld.long 0x00 12.--17. " RX_QEYE_OUT ,RX QEYE OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8. " RX_QEYE_EN ,RX QEYE EN" "0,1"
|
|
bitfld.long 0x00 7. " EOM_EN ,EOM EN" "0,1"
|
|
rbitfld.long 0x00 5. " EOM_TRAIN_DONE ,EOM TRAIN DONE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EOM_TRAIN_EN ,EOM TRAIN EN" "0,1"
|
|
bitfld.long 0x00 3. " DFE_RESET ,DFE RESET" "0,1"
|
|
rbitfld.long 0x00 1. " DFE_TRAIN_DONE ,DFE TRAIN DONE" "0,1"
|
|
bitfld.long 0x00 0. " DFE_TRAIN_EN ,DFE TRAIN EN" "0,1"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "MISC_PAD_P1_CTL_5_0,XUSB PADCTL IOPHY MISC PAD P1 CTL 5"
|
|
rbitfld.long 0x00 12.--17. " RX_QEYE_OUT ,RX QEYE OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8. " RX_QEYE_EN ,RX QEYE EN" "0,1"
|
|
bitfld.long 0x00 7. " EOM_EN ,EOM EN" "0,1"
|
|
rbitfld.long 0x00 5. " EOM_TRAIN_DONE ,EOM TRAIN DONE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EOM_TRAIN_EN ,EOM TRAIN EN" "0,1"
|
|
bitfld.long 0x00 3. " DFE_RESET ,DFE RESET" "0,1"
|
|
rbitfld.long 0x00 1. " DFE_TRAIN_DONE ,DFE TRAIN DONE" "0,1"
|
|
bitfld.long 0x00 0. " DFE_TRAIN_EN ,DFE TRAIN EN" "0,1"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "MISC_PAD_P0_CTL_6_0,XUSB PADCTL IOPHY MISC PAD P0 CTL 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MISC_OUT ,MISC_OUT"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MISC_OUT_SEL ,MISC_OUT_SEL"
|
|
hexmask.long.word 0x00 0.--15. 1. " MISC_TEST ,MISC_TEST"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "MISC_PAD_P1_CTL_6_0,XUSB PADCTL IOPHY MISC PAD P1 CTL 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MISC_OUT ,MISC_OUT"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MISC_OUT_SEL ,MISC_OUT_SEL"
|
|
hexmask.long.word 0x00 0.--15. 1. " MISC_TEST ,MISC_TEST"
|
|
tree.end
|
|
width 24.
|
|
tree "USB2_OTG/BIAS_PAD(0..2)"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "USB2_OTG_PAD0_CTL_0_0,OTGPAD0 CTL0 static settings"
|
|
bitfld.long 0x00 23. " LSBIAS_SEL ,LSBIAS_SEL" "0,1"
|
|
bitfld.long 0x00 22. " DISCON_DETECT_METHOD ,DISCON DETECT METHOD" "0,1"
|
|
bitfld.long 0x00 21. " PD_ZI ,PD ZI" "0,1"
|
|
bitfld.long 0x00 20. " PD2 ,PD2" "0,1"
|
|
bitfld.long 0x00 19. " PD ,PD" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TERM_EN ,TERM_EN" "0,1"
|
|
bitfld.long 0x00 16.--17. " LS_FSLEW ,LS_FSLEW" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " LS_RSLEW ,LS_RSLEW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " FS_SLEW ,FS_SLEW" "0,1,2,3"
|
|
bitfld.long 0x00 6.--11. " HS_SLEW ,HS_SLEW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " HS_CURR_LEVEL ,HS_CURR_LEVEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "USB2_OTG_PAD1_CTL_0_0,OTGPAD1 CTL0 static settings"
|
|
bitfld.long 0x00 23. " LSBIAS_SEL ,LSBIAS_SEL" "0,1"
|
|
bitfld.long 0x00 22. " DISCON_DETECT_METHOD ,DISCON DETECT METHOD" "0,1"
|
|
bitfld.long 0x00 21. " PD_ZI ,PD ZI" "0,1"
|
|
bitfld.long 0x00 20. " PD2 ,PD2" "0,1"
|
|
bitfld.long 0x00 19. " PD ,PD" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TERM_EN ,TERM_EN" "0,1"
|
|
bitfld.long 0x00 16.--17. " LS_FSLEW ,LS_FSLEW" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " LS_RSLEW ,LS_RSLEW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " FS_SLEW ,FS_SLEW" "0,1,2,3"
|
|
bitfld.long 0x00 6.--11. " HS_SLEW ,HS_SLEW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " HS_CURR_LEVEL ,HS_CURR_LEVEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "USB2_OTG_PAD2_CTL_0_0,OTGPAD2 CTL0 static settings"
|
|
bitfld.long 0x00 23. " LSBIAS_SEL ,LSBIAS_SEL" "0,1"
|
|
bitfld.long 0x00 22. " DISCON_DETECT_METHOD ,DISCON DETECT METHOD" "0,1"
|
|
bitfld.long 0x00 21. " PD_ZI ,PD ZI" "0,1"
|
|
bitfld.long 0x00 20. " PD2 ,PD2" "0,1"
|
|
bitfld.long 0x00 19. " PD ,PD" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TERM_EN ,TERM_EN" "0,1"
|
|
bitfld.long 0x00 16.--17. " LS_FSLEW ,LS_FSLEW" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " LS_RSLEW ,LS_RSLEW" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " FS_SLEW ,FS_SLEW" "0,1,2,3"
|
|
bitfld.long 0x00 6.--11. " HS_SLEW ,HS_SLEW" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " HS_CURR_LEVEL ,HS_CURR_LEVEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "USB2_OTG_PAD0_CTL_1_0,OTGPAD0 CTL1 static settings"
|
|
bitfld.long 0x00 11.--12. " RPU_RANGE_ADJ ,RPU RANGE ADJ" "0,1,2,3"
|
|
bitfld.long 0x00 9.--10. " HS_IREF_CAP ,HS IREF CAP" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. " SPARE ,SPARE" "0,1,2,3"
|
|
bitfld.long 0x00 3.--6. " TERM_RANGE_ADJ ,TERM RANGE ADJ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PD_DR ,PD DR" "0,1"
|
|
bitfld.long 0x00 1. " PD_DISC_FORCE_POWERUP ,PD DISC FORCE POWERUP" "0,1"
|
|
bitfld.long 0x00 0. " PD_CHRP_FORCE_POWERUP ,PD CHRP FORCE POWERUP" "0,1"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "USB2_OTG_PAD1_CTL_1_0,OTGPAD1 CTL1 static settings"
|
|
bitfld.long 0x00 11.--12. " RPU_RANGE_ADJ ,RPU RANGE ADJ" "0,1,2,3"
|
|
bitfld.long 0x00 9.--10. " HS_IREF_CAP ,HS IREF CAP" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. " SPARE ,SPARE" "0,1,2,3"
|
|
bitfld.long 0x00 3.--6. " TERM_RANGE_ADJ ,TERM RANGE ADJ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PD_DR ,PD DR" "0,1"
|
|
bitfld.long 0x00 1. " PD_DISC_FORCE_POWERUP ,PD DISC FORCE POWERUP" "0,1"
|
|
bitfld.long 0x00 0. " PD_CHRP_FORCE_POWERUP ,PD CHRP FORCE POWERUP" "0,1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "USB2_OTG_PAD2_CTL_1_0,OTGPAD2 CTL1 static settings"
|
|
bitfld.long 0x00 11.--12. " RPU_RANGE_ADJ ,RPU RANGE ADJ" "0,1,2,3"
|
|
bitfld.long 0x00 9.--10. " HS_IREF_CAP ,HS IREF CAP" "0,1,2,3"
|
|
bitfld.long 0x00 7.--8. " SPARE ,SPARE" "0,1,2,3"
|
|
bitfld.long 0x00 3.--6. " TERM_RANGE_ADJ ,TERM RANGE ADJ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PD_DR ,PD DR" "0,1"
|
|
bitfld.long 0x00 1. " PD_DISC_FORCE_POWERUP ,PD DISC FORCE POWERUP" "0,1"
|
|
bitfld.long 0x00 0. " PD_CHRP_FORCE_POWERUP ,PD CHRP FORCE POWERUP" "0,1"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "USB2_BIAS_PAD_CTL_0_0,XUSB PADCTL USB2 BIAS PAD CTL 0 0"
|
|
bitfld.long 0x00 14.--16. " ADJRPU ,ADJRPU" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13. " PD_TRK ,PD_TRK" "0,1"
|
|
bitfld.long 0x00 12. " PD ,PD" "0,1"
|
|
bitfld.long 0x00 9.--11. " TERM_OFFSET ,TERM_OFFSET" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " VBUS_LEVEL ,VBUS_LEVEL" "0,1,2,3"
|
|
bitfld.long 0x00 5.--6. " HS_CHIRP_LEVEL ,HS_CHIRP_LEVEL" "0,1,2,3"
|
|
bitfld.long 0x00 2.--4. " HS_DISCON_LEVEL ,HS_DISCON_LEVEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. " HS_SQUELCH_LEVEL ,HS_SQUELCH_LEVEL" "0,1,2,3"
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "USB2_BIAS_PAD_CTL_1_0,XUSB PADCTL USB2 BIAS PAD CTL 1 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " TCTRL ,TCTRL"
|
|
hexmask.long.word 0x00 0.--15. 1. " RCTRL ,RCTRL"
|
|
tree.end
|
|
width 20.
|
|
tree "HSIC_PAD(0..1)_CTL"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "HSIC_PAD0_CTL_0_0,HSIC PAD0 CTL0"
|
|
bitfld.long 0x00 16.--19. " HSIC_OPT ,HSIC OPT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " TX_SLEWN ,TX SLEWN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " TX_SLEWP ,TX SLEWP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " TX_RTUNEN ,TX RTUNEN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_RTUNEP ,TX RTUNEP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "HSIC_PAD1_CTL_0_0,HSIC PAD1 CTL0"
|
|
bitfld.long 0x00 16.--19. " HSIC_OPT ,HSIC OPT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " TX_SLEWN ,TX SLEWN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " TX_SLEWP ,TX SLEWP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " TX_RTUNEN ,TX RTUNEN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TX_RTUNEP ,TX RTUNEP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "HSIC_PAD0_CTL_1_0,HSIC PAD0 CTL1"
|
|
bitfld.long 0x00 10. " RPU_STROBE ,RPU STROBE" "0,1"
|
|
bitfld.long 0x00 9. " RPU_DATA ,RPU DATA" "0,1"
|
|
bitfld.long 0x00 8. " RPD_STROBE ,RPD STROBE" "0,1"
|
|
bitfld.long 0x00 7. " RPD_DATA ,RPD DATA" "0,1"
|
|
bitfld.long 0x00 6. " LPBK ,LPBK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PD_ZI ,PD ZI" "0,1"
|
|
bitfld.long 0x00 4. " PD_RX ,PD RX" "0,1"
|
|
bitfld.long 0x00 3. " PD_TRX ,PD TRX" "0,1"
|
|
bitfld.long 0x00 2. " PD_TX ,PD TX" "0,1"
|
|
bitfld.long 0x00 1. " IDDQ ,IDDQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_TERM_EN ,AUTO TERM EN" "0,1"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "HSIC_PAD1_CTL_1_0,HSIC PAD1 CTL1"
|
|
bitfld.long 0x00 10. " RPU_STROBE ,RPU STROBE" "0,1"
|
|
bitfld.long 0x00 9. " RPU_DATA ,RPU DATA" "0,1"
|
|
bitfld.long 0x00 8. " RPD_STROBE ,RPD STROBE" "0,1"
|
|
bitfld.long 0x00 7. " RPD_DATA ,RPD DATA" "0,1"
|
|
bitfld.long 0x00 6. " LPBK ,LPBK" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PD_ZI ,PD ZI" "0,1"
|
|
bitfld.long 0x00 4. " PD_RX ,PD RX" "0,1"
|
|
bitfld.long 0x00 3. " PD_TRX ,PD TRX" "0,1"
|
|
bitfld.long 0x00 2. " PD_TX ,PD TX" "0,1"
|
|
bitfld.long 0x00 1. " IDDQ ,IDDQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_TERM_EN ,AUTO TERM EN" "0,1"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "HSIC_PAD0_CTL_2_0,HSIC PAD0 CTL2"
|
|
hexmask.long.word 0x00 16.--31. 1. " CALIOUT ,CALIOUT"
|
|
bitfld.long 0x00 4.--7. " RX_STROBE_TRIM ,RX STROBE TRIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RX_DATA_TRIM ,RX DATA TRIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "HSIC_PAD1_CTL_2_0,HSIC PAD1 CTL2"
|
|
hexmask.long.word 0x00 16.--31. 1. " CALIOUT ,CALIOUT"
|
|
bitfld.long 0x00 4.--7. " RX_STROBE_TRIM ,RX STROBE TRIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " RX_DATA_TRIM ,RX DATA TRIM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 30.
|
|
textline " "
|
|
group.long 0xD8++0x0B
|
|
line.long 0x00 "ULPI_LINK_TRIM_CONTROL_0,ULPI LINK and NULL Mode Trimmer Controls"
|
|
bitfld.long 0x00 25. " CTL_SEL_DEL1 ,CTL SEL DEL1" "0,1"
|
|
bitfld.long 0x00 24. " CTL_SEL_DEL0 ,CTL_SEL_DEL0" "0,1"
|
|
bitfld.long 0x00 23. " CTL_TRIM_VAL ,CTL TRIM VAL" "0,1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CTL_TRIM_VAL ,CTL TRIM VAL"
|
|
bitfld.long 0x00 10. " DAT_SEL_DEL1 ,DAT SEL DEL1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DAT_SEL_DEL0 ,DAT SEL DEL0" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DAT_TRIM_VAL ,DAT TRIM VAL"
|
|
line.long 0x04 "ULPI_NULL_CLK_TRIM_CONTROL_0,XUSB PADCTL ULPI NULL CLK TRIM CONTROL 0"
|
|
bitfld.long 0x04 8.--12. " NULL_LBKCLK_TRIM_VAL ,NULL LBKCLK TRIM VAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " NULL_CLKOUT_TRIM_VAL ,NULL CLKOUT TRIM VAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "HSIC_STRB_TRIM_CONTROL_0,XUSB PADCTL HSIC STRB TRIM CONTROL 0"
|
|
bitfld.long 0x08 0.--5. " STRB_TRIM_VAL ,STRB TRIM VAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
group.long 0xE4++0x07
|
|
line.long 0x00 "WAKE_CTRL_0,Wake Logic AUX RDET CLK FORCE ON"
|
|
bitfld.long 0x00 5. " LANE_S0_FORCE_TX_RDET_CLK_ENABLE ,LANE S0 FORCE TX RDET CLK ENABLE" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LANE_P4_FORCE_TX_RDET_CLK_ENABLE ,LANE P4 FORCE TX RDET CLK ENABLE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LANE_P3_FORCE_TX_RDET_CLK_ENABLE ,LANE P3 FORCE TX RDET CLK ENABLE" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LANE_P2_FORCE_TX_RDET_CLK_ENABLE ,LANE P2 FORCE TX RDET CLK ENABLE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LANE_P1_FORCE_TX_RDET_CLK_ENABLE ,LANE P1 FORCE TX RDET CLK ENABLE" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LANE_P0_FORCE_TX_RDET_CLK_ENABLE ,LANE P0 FORCE TX RDET CLK ENABLE" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "PM_SPARE_0,XUSB PADCTL PM SPARE 0"
|
|
bitfld.long 0x04 11. " HSIC_PM_SPARE_BIT3 ,HSIC PM SPARE BIT3" "0,1"
|
|
bitfld.long 0x04 10. " HSIC_PM_SPARE_BIT2 ,HSIC PM SPARE BIT2" "0,1"
|
|
bitfld.long 0x04 9. " HSIC_PM_SPARE_BIT1 ,HSIC PM SPARE BIT1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 8. " HSIC_PM_SPARE_BIT0 ,HSIC PM SPARE BIT0" "0,1"
|
|
bitfld.long 0x04 7. " ULPI_PM_SPARE_BIT3 ,ULPI PM SPARE BIT3" "0,1"
|
|
bitfld.long 0x04 6. " ULPI_PM_SPARE_BIT2 ,ULPI PM SPARE BIT2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ULPI_PM_SPARE_BIT1 ,ULPI PM SPARE BIT1" "0,1"
|
|
bitfld.long 0x04 4. " ULPI_PM_SPARE_BIT0 ,ULPI PM SPARE BIT0" "0,1"
|
|
bitfld.long 0x04 3. " OTG_PM_SPARE_BIT3 ,OTG PM SPARE BIT3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 2. " OTG_PM_SPARE_BIT2 ,OTG_PM_SPARE_BIT2" "0,1"
|
|
bitfld.long 0x04 1. " OTG_PM_SPARE_BIT1 ,OTG PM SPARE BIT1" "0,1"
|
|
bitfld.long 0x04 0. " OTG_PM_SPARE_BIT0 ,OTG PM SPARE BIT0" "0,1"
|
|
width 23.
|
|
tree "IOPHY_MISC_PAD_P(2..4)_CTL"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "MISC_PAD_P2_CTL_1_0,Miscellaneous Direction Control Register 1 for PAD 2"
|
|
bitfld.long 0x00 27. " RX_PWR_OVRD ,RX PWR OVRD" "0,1"
|
|
bitfld.long 0x00 26. " TX_PWR_OVRD ,TX PWR OVRD" "0,1"
|
|
bitfld.long 0x00 25. " RATE_MODE_OVRD ,RATE MODE OVRD" "0,1"
|
|
bitfld.long 0x00 24. " RATE_OVRD ,RATE OVRD" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RX_DIV ,RX DIV" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " TX_DIV ,TX DIV" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " RX_RATE ,RX RATE" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " TX_RATE ,TX RATE" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TX_RDET ,TX_RDET" "0,1"
|
|
rbitfld.long 0x00 13. " TX_STAT_PRESENT ,TX STAT PRESENT" "0,1"
|
|
rbitfld.long 0x00 12. " RX_STAT_IDLE ,RX STAT IDLE" "0,1"
|
|
bitfld.long 0x00 11. " RX_DATA_EN ,RX DATA EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RX_DATA_READY ,RX DATA READY" "0,1"
|
|
bitfld.long 0x00 8.--9. " RX_SLEEP ,RX SLEEP" "0,1,2,3"
|
|
bitfld.long 0x00 7. " TX_DATA_EN ,TX DATA EN" "0,1"
|
|
bitfld.long 0x00 6. " TX_DATA_READY ,TX DATA READY" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TX_SLEEP ,TX SLEEP" "0,1,2,3"
|
|
bitfld.long 0x00 3. " CKBUFPD_OVRD ,CKBUFPD OVRD" "0,1"
|
|
bitfld.long 0x00 2. " CKBUFPD ,CKBUFPD" "0,1"
|
|
bitfld.long 0x00 1. " IDDQ_OVRD ,IDDQ OVRD" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDDQ ,IDDQ" "0,1"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "MISC_PAD_P3_CTL_1_0,Miscellaneous Direction Control Register 1 for PAD 3"
|
|
bitfld.long 0x00 27. " RX_PWR_OVRD ,RX PWR OVRD" "0,1"
|
|
bitfld.long 0x00 26. " TX_PWR_OVRD ,TX PWR OVRD" "0,1"
|
|
bitfld.long 0x00 25. " RATE_MODE_OVRD ,RATE MODE OVRD" "0,1"
|
|
bitfld.long 0x00 24. " RATE_OVRD ,RATE OVRD" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RX_DIV ,RX DIV" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " TX_DIV ,TX DIV" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " RX_RATE ,RX RATE" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " TX_RATE ,TX RATE" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TX_RDET ,TX_RDET" "0,1"
|
|
rbitfld.long 0x00 13. " TX_STAT_PRESENT ,TX STAT PRESENT" "0,1"
|
|
rbitfld.long 0x00 12. " RX_STAT_IDLE ,RX STAT IDLE" "0,1"
|
|
bitfld.long 0x00 11. " RX_DATA_EN ,RX DATA EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RX_DATA_READY ,RX DATA READY" "0,1"
|
|
bitfld.long 0x00 8.--9. " RX_SLEEP ,RX SLEEP" "0,1,2,3"
|
|
bitfld.long 0x00 7. " TX_DATA_EN ,TX DATA EN" "0,1"
|
|
bitfld.long 0x00 6. " TX_DATA_READY ,TX DATA READY" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TX_SLEEP ,TX SLEEP" "0,1,2,3"
|
|
bitfld.long 0x00 3. " CKBUFPD_OVRD ,CKBUFPD OVRD" "0,1"
|
|
bitfld.long 0x00 2. " CKBUFPD ,CKBUFPD" "0,1"
|
|
bitfld.long 0x00 1. " IDDQ_OVRD ,IDDQ OVRD" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDDQ ,IDDQ" "0,1"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "MISC_PAD_P4_CTL_1_0,Miscellaneous Direction Control Register 1 for PAD 4"
|
|
bitfld.long 0x00 27. " RX_PWR_OVRD ,RX PWR OVRD" "0,1"
|
|
bitfld.long 0x00 26. " TX_PWR_OVRD ,TX PWR OVRD" "0,1"
|
|
bitfld.long 0x00 25. " RATE_MODE_OVRD ,RATE MODE OVRD" "0,1"
|
|
bitfld.long 0x00 24. " RATE_OVRD ,RATE OVRD" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RX_DIV ,RX DIV" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " TX_DIV ,TX DIV" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " RX_RATE ,RX RATE" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " TX_RATE ,TX RATE" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TX_RDET ,TX_RDET" "0,1"
|
|
rbitfld.long 0x00 13. " TX_STAT_PRESENT ,TX STAT PRESENT" "0,1"
|
|
rbitfld.long 0x00 12. " RX_STAT_IDLE ,RX STAT IDLE" "0,1"
|
|
bitfld.long 0x00 11. " RX_DATA_EN ,RX DATA EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RX_DATA_READY ,RX DATA READY" "0,1"
|
|
bitfld.long 0x00 8.--9. " RX_SLEEP ,RX SLEEP" "0,1,2,3"
|
|
bitfld.long 0x00 7. " TX_DATA_EN ,TX DATA EN" "0,1"
|
|
bitfld.long 0x00 6. " TX_DATA_READY ,TX DATA READY" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TX_SLEEP ,TX SLEEP" "0,1,2,3"
|
|
bitfld.long 0x00 3. " CKBUFPD_OVRD ,CKBUFPD OVRD" "0,1"
|
|
bitfld.long 0x00 2. " CKBUFPD ,CKBUFPD" "0,1"
|
|
bitfld.long 0x00 1. " IDDQ_OVRD ,IDDQ OVRD" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDDQ ,IDDQ" "0,1"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "MISC_PAD_P2_CTL_2_0,Miscellaneous Direction Control Register 2 for PAD 2"
|
|
rbitfld.long 0x00 30.--31. " SPARE_OUT ,SPARE OUT" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " SPARE_IN ,SPARE IN" "0,1,2,3"
|
|
bitfld.long 0x00 27. " TEST_EN ,TEST EN" "0,1"
|
|
bitfld.long 0x00 25. " PRBS_CHK_EN ,PRBS CHK EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PRBS_ERROR ,PRBS ERROR" "0,1"
|
|
bitfld.long 0x00 13. " RX_CDR_RESET ,TX SYNC" "0,1"
|
|
bitfld.long 0x00 12. " FED_LOOP ,FED LOOP" "0,1"
|
|
bitfld.long 0x00 8.--10. " TX_DATA_MODE ,TX DATA MODE" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FEA_LOOP ,FEA LOOP" "0,1"
|
|
bitfld.long 0x00 4.--6. " FEA_MODE ,FEA MODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " NEA_LOOP ,NEA LOOP" "0,1"
|
|
bitfld.long 0x00 2. " NED_LOOP ,NED LOOP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NED_MODE ,NED MODE" "0,1,2,3"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "MISC_PAD_P2_CTL_2_0,Miscellaneous Direction Control Register 2 for PAD 3"
|
|
rbitfld.long 0x00 30.--31. " SPARE_OUT ,SPARE OUT" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " SPARE_IN ,SPARE IN" "0,1,2,3"
|
|
bitfld.long 0x00 27. " TEST_EN ,TEST EN" "0,1"
|
|
bitfld.long 0x00 25. " PRBS_CHK_EN ,PRBS CHK EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PRBS_ERROR ,PRBS ERROR" "0,1"
|
|
bitfld.long 0x00 13. " RX_CDR_RESET ,TX SYNC" "0,1"
|
|
bitfld.long 0x00 12. " FED_LOOP ,FED LOOP" "0,1"
|
|
bitfld.long 0x00 8.--10. " TX_DATA_MODE ,TX DATA MODE" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FEA_LOOP ,FEA LOOP" "0,1"
|
|
bitfld.long 0x00 4.--6. " FEA_MODE ,FEA MODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " NEA_LOOP ,NEA LOOP" "0,1"
|
|
bitfld.long 0x00 2. " NED_LOOP ,NED LOOP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NED_MODE ,NED MODE" "0,1,2,3"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MISC_PAD_P2_CTL_2_0,Miscellaneous Direction Control Register 2 for PAD 4"
|
|
rbitfld.long 0x00 30.--31. " SPARE_OUT ,SPARE OUT" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " SPARE_IN ,SPARE IN" "0,1,2,3"
|
|
bitfld.long 0x00 27. " TEST_EN ,TEST EN" "0,1"
|
|
bitfld.long 0x00 25. " PRBS_CHK_EN ,PRBS CHK EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PRBS_ERROR ,PRBS ERROR" "0,1"
|
|
bitfld.long 0x00 13. " RX_CDR_RESET ,TX SYNC" "0,1"
|
|
bitfld.long 0x00 12. " FED_LOOP ,FED LOOP" "0,1"
|
|
bitfld.long 0x00 8.--10. " TX_DATA_MODE ,TX DATA MODE" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FEA_LOOP ,FEA LOOP" "0,1"
|
|
bitfld.long 0x00 4.--6. " FEA_MODE ,FEA MODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " NEA_LOOP ,NEA LOOP" "0,1"
|
|
bitfld.long 0x00 2. " NED_LOOP ,NED LOOP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " NED_MODE ,NED MODE" "0,1,2,3"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "MISC_PAD_P2_CTL_3_0,Miscellaneous Direction Control Register 3 for PAD 2"
|
|
hexmask.long.word 0x00 20.--31. 1. " CDR_TEST ,CDR TEST"
|
|
bitfld.long 0x00 19. " RX_IDLE_MODE_OVRD ,RX IDLE MODE OVRD" "0,1"
|
|
bitfld.long 0x00 18. " RX_IDLE_MODE ,RX IDLE MODE" "0,1"
|
|
bitfld.long 0x00 17. " RX_IDLE_BYP ,RX IDLE BYP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TX_RDET_BYP ,TX RDET BYP" "0,1"
|
|
bitfld.long 0x00 14.--15. " RX_IDLE_T ,RX IDLE T" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " TX_RDET_T ,TX RDET T" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. " TX_SEL_LOAD ,TX SEL LOAD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MISC_CNTL ,MISC CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "MISC_PAD_P3_CTL_3_0,Miscellaneous Direction Control Register 3 for PAD 3"
|
|
hexmask.long.word 0x00 20.--31. 1. " CDR_TEST ,CDR TEST"
|
|
bitfld.long 0x00 19. " RX_IDLE_MODE_OVRD ,RX IDLE MODE OVRD" "0,1"
|
|
bitfld.long 0x00 18. " RX_IDLE_MODE ,RX IDLE MODE" "0,1"
|
|
bitfld.long 0x00 17. " RX_IDLE_BYP ,RX IDLE BYP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TX_RDET_BYP ,TX RDET BYP" "0,1"
|
|
bitfld.long 0x00 14.--15. " RX_IDLE_T ,RX IDLE T" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " TX_RDET_T ,TX RDET T" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. " TX_SEL_LOAD ,TX SEL LOAD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MISC_CNTL ,MISC CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "MISC_PAD_P4_CTL_3_0,Miscellaneous Direction Control Register 3 for PAD 4"
|
|
hexmask.long.word 0x00 20.--31. 1. " CDR_TEST ,CDR TEST"
|
|
bitfld.long 0x00 19. " RX_IDLE_MODE_OVRD ,RX IDLE MODE OVRD" "0,1"
|
|
bitfld.long 0x00 18. " RX_IDLE_MODE ,RX IDLE MODE" "0,1"
|
|
bitfld.long 0x00 17. " RX_IDLE_BYP ,RX IDLE BYP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TX_RDET_BYP ,TX RDET BYP" "0,1"
|
|
bitfld.long 0x00 14.--15. " RX_IDLE_T ,RX IDLE T" "0,1,2,3"
|
|
bitfld.long 0x00 12.--13. " TX_RDET_T ,TX RDET T" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. " TX_SEL_LOAD ,TX SEL LOAD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MISC_CNTL ,MISC CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MISC_PAD_P2_CTL_4_0,Miscellaneous Direction Control Register 4 for PAD $2"
|
|
rbitfld.long 0x00 31. " AUX_RX_STAT_IDLE ,AUX RX STAT IDLE" "0,1"
|
|
bitfld.long 0x00 30. " AUX_RX_IDLE_MODE ,AUX RX IDLE MODE" "0,1"
|
|
bitfld.long 0x00 29. " AUX_RX_IDLE_EN ,AUX RX IDLE EN" "0,1"
|
|
bitfld.long 0x00 28. " AUX_RX_TERM_EN ,AUX RX TERM EN" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " AUX_TX_STAT_PRESENT ,AUX TX STAT PRESENT" "0,1"
|
|
bitfld.long 0x00 26. " AUX_TX_RDET_CLK_EN ,AUX TX RDET CLK EN" "0,1"
|
|
bitfld.long 0x00 25. " AUX_TX_RDET_EN ,AUX TX RDET EN" "0,1"
|
|
bitfld.long 0x00 24. " AUX_TX_TERM_EN ,AUX TX TERM EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AUX_MODE_OVRD ,AUX MODE OVRD" "0,1"
|
|
bitfld.long 0x00 22. " AUX_HOLD_EN ,AUX HOLD EN" "0,1"
|
|
bitfld.long 0x00 21. " AUX_IDDQ_OVRD ,AUX IDDQ OVRD" "0,1"
|
|
bitfld.long 0x00 20. " AUX_IDDQ ,AUX IDDQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TX_BYP_OVRD ,TX BYP OVRD" "0,1"
|
|
bitfld.long 0x00 12. " RX_BYP_MODE ,RX BYP MODE" "0,1"
|
|
bitfld.long 0x00 11. " RX_BYP_EN ,RX BYP EN" "0,1"
|
|
bitfld.long 0x00 10. " RX_BYP_DIR ,RX BYP DIR" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " RX_BYP_IN ,RX BYP OUT" "0,1"
|
|
bitfld.long 0x00 8. " RX_BYP_OUT ,RX BYP IN" "0,1"
|
|
bitfld.long 0x00 7. " TX_BYP_EN ,TX BYP EN" "0,1"
|
|
bitfld.long 0x00 6. " TX_BYP_DIR ,TX BYP DIR" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " TX_BYP_IN ,TX BYP IN" "0,1"
|
|
bitfld.long 0x00 4. " TX_BYP_OUT ,TX BYP OUT" "0,1"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "MISC_PAD_P3_CTL_4_0,Miscellaneous Direction Control Register 4 for PAD 3"
|
|
rbitfld.long 0x00 31. " AUX_RX_STAT_IDLE ,AUX RX STAT IDLE" "0,1"
|
|
bitfld.long 0x00 30. " AUX_RX_IDLE_MODE ,AUX RX IDLE MODE" "0,1"
|
|
bitfld.long 0x00 29. " AUX_RX_IDLE_EN ,AUX RX IDLE EN" "0,1"
|
|
bitfld.long 0x00 28. " AUX_RX_TERM_EN ,AUX RX TERM EN" "0,1"
|
|
rbitfld.long 0x00 27. " AUX_TX_STAT_PRESENT ,AUX TX STAT PRESENT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 26. " AUX_TX_RDET_CLK_EN ,AUX TX RDET CLK EN" "0,1"
|
|
bitfld.long 0x00 25. " AUX_TX_RDET_EN ,AUX TX RDET EN" "0,1"
|
|
bitfld.long 0x00 24. " AUX_TX_TERM_EN ,AUX TX TERM EN" "0,1"
|
|
bitfld.long 0x00 23. " AUX_MODE_OVRD ,AUX MODE OVRD" "0,1"
|
|
bitfld.long 0x00 22. " AUX_HOLD_EN ,AUX HOLD EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " AUX_IDDQ_OVRD ,AUX IDDQ OVRD" "0,1"
|
|
bitfld.long 0x00 20. " AUX_IDDQ ,AUX IDDQ" "0,1"
|
|
bitfld.long 0x00 13. " TX_BYP_OVRD ,TX BYP OVRD" "0,1"
|
|
bitfld.long 0x00 12. " RX_BYP_MODE ,RX BYP MODE" "0,1"
|
|
bitfld.long 0x00 11. " RX_BYP_EN ,RX BYP EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RX_BYP_DIR ,RX BYP DIR" "0,1"
|
|
bitfld.long 0x00 9. " RX_BYP_OUT ,RX BYP OUT" "0,1"
|
|
rbitfld.long 0x00 8. " RX_BYP_IN ,RX BYP IN" "0,1"
|
|
bitfld.long 0x00 7. " TX_BYP_EN ,TX BYP EN" "0,1"
|
|
bitfld.long 0x00 6. " TX_BYP_DIR ,TX BYP DIR" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " TX_BYP_IN ,TX BYP IN" "0,1"
|
|
bitfld.long 0x00 4. " TX_BYP_OUT ,TX BYP OUT" "0,1"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "MISC_PAD_P4_CTL_4_0,Miscellaneous Direction Control Register 4 for PAD 4"
|
|
rbitfld.long 0x00 31. " AUX_RX_STAT_IDLE ,AUX RX STAT IDLE" "0,1"
|
|
bitfld.long 0x00 30. " AUX_RX_IDLE_MODE ,AUX RX IDLE MODE" "0,1"
|
|
bitfld.long 0x00 29. " AUX_RX_IDLE_EN ,AUX RX IDLE EN" "0,1"
|
|
bitfld.long 0x00 28. " AUX_RX_TERM_EN ,AUX RX TERM EN" "0,1"
|
|
rbitfld.long 0x00 27. " AUX_TX_STAT_PRESENT ,AUX TX STAT PRESENT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 26. " AUX_TX_RDET_CLK_EN ,AUX TX RDET CLK EN" "0,1"
|
|
bitfld.long 0x00 25. " AUX_TX_RDET_EN ,AUX TX RDET EN" "0,1"
|
|
bitfld.long 0x00 24. " AUX_TX_TERM_EN ,AUX TX TERM EN" "0,1"
|
|
bitfld.long 0x00 23. " AUX_MODE_OVRD ,AUX MODE OVRD" "0,1"
|
|
bitfld.long 0x00 22. " AUX_HOLD_EN ,AUX HOLD EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " AUX_IDDQ_OVRD ,AUX IDDQ OVRD" "0,1"
|
|
bitfld.long 0x00 20. " AUX_IDDQ ,AUX IDDQ" "0,1"
|
|
bitfld.long 0x00 13. " TX_BYP_OVRD ,TX BYP OVRD" "0,1"
|
|
bitfld.long 0x00 12. " RX_BYP_MODE ,RX BYP MODE" "0,1"
|
|
bitfld.long 0x00 11. " RX_BYP_EN ,RX BYP EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RX_BYP_DIR ,RX BYP DIR" "0,1"
|
|
bitfld.long 0x00 9. " RX_BYP_OUT ,RX BYP OUT" "0,1"
|
|
rbitfld.long 0x00 8. " RX_BYP_IN ,RX BYP IN" "0,1"
|
|
bitfld.long 0x00 7. " TX_BYP_EN ,TX BYP EN" "0,1"
|
|
bitfld.long 0x00 6. " TX_BYP_DIR ,TX BYP DIR" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " TX_BYP_IN ,TX BYP IN" "0,1"
|
|
bitfld.long 0x00 4. " TX_BYP_OUT ,TX BYP OUT" "0,1"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "MISC_PAD_P2_CTL_5_0,Miscellaneous Direction Control Register 5 for PAD 2"
|
|
rbitfld.long 0x00 12.--17. " RX_QEYE_OUT ,RX QEYE OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8. " RX_QEYE_EN ,RX QEYE EN" "0,1"
|
|
bitfld.long 0x00 7. " EOM_EN ,EOM EN" "0,1"
|
|
rbitfld.long 0x00 5. " EOM_TRAIN_DONE ,EOM TRAIN DONE" "0,1"
|
|
bitfld.long 0x00 4. " EOM_TRAIN_EN ,EOM TRAIN EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DFE_RESET ,DFE RESET" "0,1"
|
|
rbitfld.long 0x00 1. " DFE_TRAIN_DONE ,DFE TRAIN DONE" "0,1"
|
|
bitfld.long 0x00 0. " DFE_TRAIN_EN ,DFE TRAIN EN" "0,1"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "MISC_PAD_P3_CTL_5_0,Miscellaneous Direction Control Register 5 for PAD 3"
|
|
rbitfld.long 0x00 12.--17. " RX_QEYE_OUT ,RX QEYE OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8. " RX_QEYE_EN ,RX QEYE EN" "0,1"
|
|
bitfld.long 0x00 7. " EOM_EN ,EOM EN" "0,1"
|
|
rbitfld.long 0x00 5. " EOM_TRAIN_DONE ,EOM TRAIN DONE" "0,1"
|
|
bitfld.long 0x00 4. " EOM_TRAIN_EN ,EOM TRAIN EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DFE_RESET ,DFE RESET" "0,1"
|
|
rbitfld.long 0x00 1. " DFE_TRAIN_DONE ,DFE TRAIN DONE" "0,1"
|
|
bitfld.long 0x00 0. " DFE_TRAIN_EN ,DFE TRAIN EN" "0,1"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "MISC_PAD_P4_CTL_5_0,Miscellaneous Direction Control Register 5 for PAD 4"
|
|
rbitfld.long 0x00 12.--17. " RX_QEYE_OUT ,RX QEYE OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8. " RX_QEYE_EN ,RX QEYE EN" "0,1"
|
|
bitfld.long 0x00 7. " EOM_EN ,EOM EN" "0,1"
|
|
rbitfld.long 0x00 5. " EOM_TRAIN_DONE ,EOM TRAIN DONE" "0,1"
|
|
bitfld.long 0x00 4. " EOM_TRAIN_EN ,EOM TRAIN EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DFE_RESET ,DFE RESET" "0,1"
|
|
rbitfld.long 0x00 1. " DFE_TRAIN_DONE ,DFE TRAIN DONE" "0,1"
|
|
bitfld.long 0x00 0. " DFE_TRAIN_EN ,DFE TRAIN EN" "0,1"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "MISC_PAD_P2_CTL_6_0,Miscellaneous Direction Control Register 6 for PAD 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MISC_OUT ,MISC OUT"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MISC_OUT_SEL ,MISC OUT SEL"
|
|
hexmask.long.word 0x00 0.--15. 1. " MISC_TEST ,MISC TEST"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "MISC_PAD_P3_CTL_6_0,Miscellaneous Direction Control Register 6 for PAD 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MISC_OUT ,MISC OUT"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MISC_OUT_SEL ,MISC OUT SEL"
|
|
hexmask.long.word 0x00 0.--15. 1. " MISC_TEST ,MISC TEST"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "MISC_PAD_P4_CTL_6_0,Miscellaneous Direction Control Register 6 for PAD 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MISC_OUT ,MISC OUT"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MISC_OUT_SEL ,MISC OUT SEL"
|
|
hexmask.long.word 0x00 0.--15. 1. " MISC_TEST ,MISC TEST"
|
|
tree.end
|
|
width 16.
|
|
tree "USB3_PAD_MUX"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "USB3_PAD_MUX_0,XUSB PADCTL USB3 PAD MUX 0"
|
|
bitfld.long 0x00 26.--27. " SATA_PAD_LANE0 ,SATA PAD LANE0" "PCIE,USB3_SS,SATA,"
|
|
bitfld.long 0x00 24.--25. " PCIE_PAD_LANE4 ,PCIE PAD LANE4" "PCIE,USB3_SS,SATA,"
|
|
bitfld.long 0x00 22.--23. " PCIE_PAD_LANE3 ,PCIE PAD LANE3" "PCIE,USB3_SS,SATA,"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " PCIE_PAD_LANE2 ,PCIE PAD LANE2" "PCIE,USB3_SS,SATA,"
|
|
bitfld.long 0x00 18.--19. " PCIE_PAD_LANE1 ,PCIE PAD LANE1" "PCIE,USB3_SS,SATA,"
|
|
bitfld.long 0x00 16.--17. " PCIE_PAD_LANE0 ,PCIE PAD LANE0" "PCIE,USB3_SS,SATA,"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 ,FORCE SATA PAD IDDQ DISABLE MASK0" "Not disabled,Disabled"
|
|
bitfld.long 0x00 5. " FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4 ,FORCE PCIE PAD IDDQ DISABLE MASK4" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 ,FORCE PCIE PAD IDDQ DISABLE MASK3" "Not disabled,Disabled"
|
|
bitfld.long 0x00 3. " FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 ,FORCE PCIE PAD IDDQ DISABLE MASK2" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 ,FORCE PCIE PAD IDDQ DISABLE MASK1" "Not disabled,Disabled"
|
|
bitfld.long 0x00 1. " FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0 ,FORCE PCIE PAD IDDQ DISABLE MASK0" "Not disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FORCE_PCIE_PAD_IDDQ_DISABLE ,FORCE PCIE PAD IDDQ DISABLE" "Not disabled,Disabled"
|
|
tree.end
|
|
width 15.
|
|
tree "IOPHY_PLL_S0_CTL(1..4)"
|
|
group.long 0x138++0x0F
|
|
line.long 0x00 "PLL_S0_CTL1_0,XUSB PADCTL IOPHY PLL S0 CTL1"
|
|
bitfld.long 0x00 28.--29. " PLL1_REFCLK_NDIV ,PLL1 REFCLK NDIV" "0,1,2,3"
|
|
rbitfld.long 0x00 27. " PLL1_LOCKDET ,PLL1 LOCKDET" "0,1"
|
|
bitfld.long 0x00 24. " PLL1_MODE ,PLL1 MODE" "0,1"
|
|
bitfld.long 0x00 20.--21. " PLL0_REFCLK_NDIV ,PLL0 REFCLK NDIV" "0,1,2,3"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " PLL0_LOCKDET ,PLL0 LOCKDET" "0,1"
|
|
bitfld.long 0x00 16. " PLL0_MODE ,PLL0 MODE" "0,1"
|
|
bitfld.long 0x00 12.--15. " REFCLK_SEL ,REFCLK SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. " REFCLK_TERM100 ,REFCLK TERM100" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PLL_CKBUFPD_OVR ,PLL CKBUFPD OVR" "0,1"
|
|
bitfld.long 0x00 8. " PLL_CKBUFPD_M ,PLL CKBUFPD M" "0,1"
|
|
bitfld.long 0x00 7. " PLL_CKBUFPD_BL ,PLL CKBUFPD BL" "0,1"
|
|
bitfld.long 0x00 6. " PLL_CKBUFPD_BR ,PLL CKBUFPD BR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PLL_CKBUFPD_TL ,PLL CKBUFPD TL" "0,1"
|
|
bitfld.long 0x00 4. " PLL_CKBUFPD_TR ,PLL CKBUFPD TR" "0,1"
|
|
bitfld.long 0x00 3. " PLL_PWR_OVRD ,PLL PWR OVRD" "0,1"
|
|
bitfld.long 0x00 2. " PLL_EMULATION_RST ,PLL EMULATION RST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLL_RST ,PLL RST" "0,1"
|
|
bitfld.long 0x00 0. " PLL_IDDQ ,PLL IDDQ" "0,1"
|
|
line.long 0x04 "PLL_S0_CTL2_0,XUSB PADCTL IOPHY PLL S0 CTL2"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PLL_MISC_OUT ,PLL MISC OUT"
|
|
bitfld.long 0x04 20.--23. " PLL1_CP_CNTL ,PLL1 CP CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " PLL0_CP_CNTL ,PLL0 CP CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 15. " PLL_BYPASS_EN ,PLL BYPASS EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 13. " PLL_EMULATION_ON ,PLL EMULATION ON" "0,1"
|
|
bitfld.long 0x04 12. " TCLKOUT_EN ,TCLKOUT EN" "0,1"
|
|
bitfld.long 0x04 8.--11. " TCLKOUT_SEL ,TCLKOUT SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 7. " XDIGCLK4P5_EN ,XDIGCLK4P5 EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 6. " PLL_EMULATION_ON ,PLL EMULATION ON" "0,1"
|
|
bitfld.long 0x04 5. " TCLKOUT_EN ,TCLKOUT EN" "0,1"
|
|
bitfld.long 0x04 4. " TCLKOUT_SEL ,TCLKOUT SEL" "0,1"
|
|
bitfld.long 0x04 3. " XDIGCLK4P5_EN ,XDIGCLK4P5 EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " XDIGCLK_SEL ,XDIGCLK_SEL" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "PLL_S0_CTL3_0,XUSB PADCTL IOPHY PLL S0 CTL3"
|
|
bitfld.long 0x08 28.--31. " PLL_TEMP_CNTL ,PLL TEMP CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 20.--25. " PLL_BW_CNTL ,PLL BW CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 16.--17. " PLL_BGAP_CNTL ,PLL BGAP CNTL" "0,1,2,3"
|
|
rbitfld.long 0x08 15. " RCAL_DONE ,RCAL DONE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 14. " RCAL_RESET ,RCAL RESET" "0,1"
|
|
rbitfld.long 0x08 8.--12. " RCAL_VAL ,RCAL VAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 7. " RCAL_BYPASS ,RCAL BYPASS" "0,1"
|
|
bitfld.long 0x08 0.--4. " RCAL_CODE ,RCAL CODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "PLL_S0_CTL4_0,XUSB PADCTL IOPHY PLL S0 CTL4"
|
|
hexmask.long.word 0x0C 0.--11. 1. " PLL_MISC_CNTL ,PLL MISC CNTL"
|
|
tree.end
|
|
width 21.
|
|
tree "IOPHY_MISC_PAD_S0_CTL(1...6)"
|
|
group.long 0x148++0x13
|
|
line.long 0x00 "MISC_PAD_S0_CTL_1_0,XUSB PADCTL IOPHY MISC PAD S0 CTL 1"
|
|
bitfld.long 0x00 27. " RX_PWR_OVRD ,RX PWR OVRD" "0,1"
|
|
bitfld.long 0x00 26. " TX_PWR_OVRD ,TX PWR OVRD" "0,1"
|
|
bitfld.long 0x00 25. " RATE_MODE_OVRD ,RATE MODE OVRD" "0,1"
|
|
bitfld.long 0x00 24. " RATE_MODE ,RATE MODE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RX_DIV ,RX DIV" "0,1,2,3"
|
|
bitfld.long 0x00 20.--21. " TX_DIV ,TX DIV" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " RX_RATE ,RX RATE" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " TX_RATE ,TX RATE" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TX_RDET ,TX RDET" "0,1"
|
|
rbitfld.long 0x00 13. " TX_STAT_PRESENT ,TX STAT PRESENT" "0,1"
|
|
rbitfld.long 0x00 12. " RX_STAT_IDLE ,RX STAT IDLE" "0,1"
|
|
bitfld.long 0x00 11. " RX_DATA_EN ,RX DATA EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RX_DATA_READY ,RX DATA READY" "0,1"
|
|
bitfld.long 0x00 8.--9. " RX_SLEEP ,RX_SLEEP" "0,1,2,3"
|
|
bitfld.long 0x00 7. " TX_DATA_EN ,TX DATA EN" "0,1"
|
|
bitfld.long 0x00 6. " TX_DATA_READY ,TX DATA READY" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TX_SLEEP ,TX SLEEP" "0,1,2,3"
|
|
bitfld.long 0x00 3. " CKBUFPD_OVRD ,CKBUFPD OVRD" "0,1"
|
|
bitfld.long 0x00 2. " CKBUFPD ,CKBUFPD" "0,1"
|
|
bitfld.long 0x00 1. " IDDQ_OVRD ,IDDQ OVRD" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDDQ ,IDDQ" "0,1"
|
|
line.long 0x04 "MISC_PAD_S0_CTL_2_0,XUSB PADCTL IOPHY MISC PAD S0 CTL 2"
|
|
rbitfld.long 0x04 30.--31. " SPARE_OUT ,SPARE OUT" "0,1,2,3"
|
|
bitfld.long 0x04 28.--29. " SPARE_IN ,SPARE IN" "0,1,2,3"
|
|
bitfld.long 0x04 27. " TEST_EN ,TEST EN" "0,1"
|
|
bitfld.long 0x04 25. " PRBS_CHK_EN ,PRBS CHK EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 24. " PRBS_ERROR ,PRBS ERROR" "0,1"
|
|
bitfld.long 0x04 13. " RX_CDR_RESET ,RX CDR RESET" "0,1"
|
|
bitfld.long 0x04 12. " TX_SYNC ,TX SYNC" "0,1"
|
|
bitfld.long 0x04 11. " FED_LOOP ,FED LOOP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " TX_DATA_MODE ,TX DATA MODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 7. " FEA_LOOP ,FEA LOOP" "0,1"
|
|
bitfld.long 0x04 4.--6. " FEA_MODE ,FEA MODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 3. " NEA_LOOP ,NEA LOOP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 2. " NED_LOOP ,NED LOOP" "0,1"
|
|
bitfld.long 0x04 0.--1. " NED_MODE ,NED MODE" "0,1,2,3"
|
|
line.long 0x08 "MISC_PAD_S0_CTL_3_0,XUSB PADCTL IOPHY MISC PAD S0 CTL 3"
|
|
hexmask.long.word 0x08 20.--31. 1. " CDR_TEST ,CDR TEST"
|
|
bitfld.long 0x08 19. " RX_IDLE_MODE_OVRD ,RX IDLE MODE OVRD" "0,1"
|
|
bitfld.long 0x08 18. " RX_IDLE_MODE ,RX IDLE MODE" "0,1"
|
|
bitfld.long 0x08 17. " RX_IDLE_BYP ,RX IDLE BYP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 16. " TX_RDET_BYP ,TX RDET BYP" "0,1"
|
|
bitfld.long 0x08 14.--15. " RX_IDLE_T ,RX IDLE T" "0,1,2,3"
|
|
bitfld.long 0x08 12.--13. " TX_RDET_T ,TX RDET T" "0,1,2,3"
|
|
bitfld.long 0x08 8.--11. " TX_SEL_LOAD ,TX SEL LOAD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " MISC_CNTL ,MISC CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "MISC_PAD_S0_CTL_4_0,XUSB PADCTL IOPHY MISC PAD S0 CTL 4"
|
|
rbitfld.long 0x0C 31. " AUX_RX_STAT_IDLE ,AUX RX STAT IDLE" "0,1"
|
|
bitfld.long 0x0C 30. " AUX_RX_IDLE_MODE ,AUX RX IDLE MODE" "0,1"
|
|
bitfld.long 0x0C 29. " AUX_RX_IDLE_EN ,AUX RX IDLE EN" "0,1"
|
|
bitfld.long 0x0C 28. " AUX_RX_TERM_EN ,AUX RX TERM EN" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x0C 27. " AUX_TX_STAT_PRESENT ,AUX TX STAT PRESENT" "0,1"
|
|
bitfld.long 0x0C 26. " AUX_TX_RDET_CLK_EN ,AUX TX RDET CLK EN" "0,1"
|
|
bitfld.long 0x0C 25. " AUX_TX_RDET_EN ,AUX TX RDET EN" "0,1"
|
|
bitfld.long 0x0C 24. " AUX_TX_TERM_EN ,AUX TX TERM EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " AUX_MODE_OVR ,AUX_MODE_OVR" "0,1"
|
|
bitfld.long 0x0C 22. " AUX_HOLD_EN ,AUX_HOLD_EN" "0,1"
|
|
bitfld.long 0x0C 21. " AUX_IDDQ_ORVD ,AUX_IDDQ_ORVD" "0,1"
|
|
bitfld.long 0x0C 20. " AUX_IDDQ ,AUX_IDDQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " TX_BYP_OVRD ,TX_BYP_OVRD" "0,1"
|
|
bitfld.long 0x0C 12. " RX_BYP_MODE ,RX_BYP_MODE" "0,1"
|
|
bitfld.long 0x0C 11. " RX_BYP_EN ,RX_BYP_EN" "0,1"
|
|
bitfld.long 0x0C 10. " RX_BYP_EN ,RX_BYP_EN" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x0C 9. " RX_BYP_IN ,RX_BYP_IN" "0,1"
|
|
bitfld.long 0x0C 8. " RX_BYP_OUT ,RX_BYP_OUT" "0,1"
|
|
bitfld.long 0x0C 7. " TX_BYP_EN ,TX_BYP_EN" "0,1"
|
|
bitfld.long 0x0C 6. " TX_BYP_DIR ,TX_BYP_DIR" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x0C 5. " TX_BYP_IN ,TX_BYP_IN" "0,1"
|
|
bitfld.long 0x0C 4. " TX_BYP_OUT ,TX_BYP_OUT" "0,1"
|
|
line.long 0x10 "MISC_PAD_S0_CTL_5_0,XUSB PADCTL IOPHY MISC PAD S0 CTL 5"
|
|
rbitfld.long 0x10 12.--17. " RX_QEYE_OUT ,RX QEYE OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x10 8. " RX_QEYE_EN ,RX QEYE EN" "0,1"
|
|
bitfld.long 0x10 7. " EOM_EN ,EOM EN" "0,1"
|
|
rbitfld.long 0x10 5. " EOM_TRAIN_DONE ,EOM TRAIN DONE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EOM_TRAIN_EN ,EOM TRAIN EN" "0,1"
|
|
bitfld.long 0x10 3. " DFE_RESET ,DFE RESET" "0,1"
|
|
rbitfld.long 0x10 1. " DFE_TRAIN_DONE ,DFE TRAIN DONE" "0,1"
|
|
bitfld.long 0x10 0. " DFE_TRAIN_EN ,DFE TRAIN EN" "0,1"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "MISC_PAD_S0_CTL_6_0,XUSB PADCTL IOPHY MISC PAD S0 CTL 6 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MISC_OUT ,MISC OUT"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MISC_OUT_SEL ,MISC OUT SEL"
|
|
hexmask.long.word 0x00 0.--15. 1. " MISC_TEST ,MISC TEST"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "XUSB DEV Registers"
|
|
base ad:0x700D0000
|
|
width 8.
|
|
tree "XUSB PCI Config Registers"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CFG_0,XUSB Configuration Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " DEVICE_ID_UNIT ,DEVICE ID UNIT"
|
|
hexmask.long.word 0x00 0.--15. 1. " VENDOR_ID ,VENDOR ID"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CFG_1,XUSB Configuration Register 1"
|
|
rbitfld.long 0x00 31. " DETECTED_PERR ,T_XUSB_CFG_1 DETECTED PERR" "Not active,Active"
|
|
rbitfld.long 0x00 30. " SIGNALED_SERR ,T_XUSB_CFG_1 SIGNALED SERR" "Not active,Active"
|
|
rbitfld.long 0x00 29. " RECEIVED_MASTER ,T_XUSB_CFG_1 RECEIVED MASTER" "Not aborted,Aborted"
|
|
rbitfld.long 0x00 28. " RECEIVED_TARGET ,T_XUSB_CFG_1 RECEIVED TARGET" "Not aborted,Aborted"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " SIGNALED_TARGET ,T_XUSB_CFG_1 SIGNALED TARGET" "Not aborted,Aborted"
|
|
rbitfld.long 0x00 25.--26. " DEVSEL_TIMING ,T_XUSB_CFG_1 DEVSEL TIMING" "Fast,Medium,Slow,?..."
|
|
rbitfld.long 0x00 24. " MASTER_DATA_PERR ,T_XUSB_CFG_1 MASTER DATA PERR" "Inactive,Active"
|
|
rbitfld.long 0x00 23. " FAST_BACK2BACK ,T_XUSB_CFG_1 FAST BACK2BACK" "Incapable,Capable"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " 66MHZ ,T_XUSB_CFG_1 66MHZ" "Incapable,Capable"
|
|
rbitfld.long 0x00 20. " CAPLIST ,T_XUSB_CFG_1 CAPLIST" "Not present,Present"
|
|
rbitfld.long 0x00 19. " INTR_STATUS ,T_XUSB_CFG_1 INTR STATUS" "0,1"
|
|
bitfld.long 0x00 10. " INTR_DISABLE ,T_XUSB_CFG_1 INTR DISABLE" "On,Off"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " BACK2BACK ,T_XUSB_CFG_1 BACK2BACK" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " SERR ,T_XUSB_CFG_1 SERR" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " STEP ,T_XUSB_CFG_1 STEP" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " PERR ,T_XUSB_CFG_1 PERR" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " PALETTE_SNOOP ,T_XUSB_CFG_1 PALETTE SNOOP" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " WRITE_AND_INVAL ,T_XUSB_CFG_1 WRITE AND INVAL" "Disabled,Enabled"
|
|
sif (cpu()=="TEGRAX1"||cpu()=="TEGRAX2")
|
|
textline " "
|
|
rbitfld.long 0x00 3. " SPECIAL_CYCLE ,T_XUSB_CFG_1 SPECIAL CYCLE" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 3. " SPECIAL_CYCLE ,T_XUSB_CFG_1 SPECIAL CYCLE" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " BUS_MASTER ,T_XUSB_CFG_1 BUS MASTER" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MEMORY_SPACE ,T_XUSB_CFG_1 MEMORY SPACE" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IO_SPACE ,T_XUSB_CFG_1 IO SPACE" "Disabled,Enabled"
|
|
rgroup.long 0x08++0x07
|
|
line.long 0x00 "CFG_2,PCI Revision ID And Class Code Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BASE_CLASS ,T_XUSB_CFG_2 BASE CLASS"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SUB_CLASS ,T_XUSB_CFG 2 SUB CLASS"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PROG_IF ,T_XUSB_CFG 2 PROG IF"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REVISION_ID ,T_XUSB_CFG_2 REVISION ID"
|
|
line.long 0x04 "CFG_3,PCI Configuration Register 3"
|
|
bitfld.long 0x04 23. " HEADER_TYPE_FUNC ,Identify whenever device contains single or multiple functions" "Single,Multi"
|
|
hexmask.long.byte 0x04 16.--22. 1. " HEADER_TYPE_DEVICE ,Header type - identify the layout of the bytes (0x10--0x3f) in configuration space"
|
|
bitfld.long 0x04 11.--15. " LATENCY_TIMER ,The value of the latency timer for this PCI bus master (In units of PCI bus clocks)" "0 clocks,8 clocks,16 clocks,24 clocks,32 clocks,40 clocks,48 clocks,56 clocks,64 clocks,72 clocks,80 clocks,88 clocks,96 clocks,104 clocks,112 clocks,120 clocks,128 clocks,136 clocks,144 clocks,152 clocks,160 clocks,168 clocks,176 clocks,184 clocks,192 clocks,200 clocks,208 clocks,216 clocks,224 clocks,232 clocks,240 clocks,248 clocks"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CACHE_LINE_SIZE ,T_XUSB_CFG_3 CACHE LINE SIZE"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "CFG_4,PCI Configuration Register 4"
|
|
hexmask.long.tbyte 0x00 15.--31. 0x80 " BASE_ADDRESS ,Base address of the device"
|
|
hexmask.long.word 0x00 4.--14. 1. " BAR_SIZE_32KB ,T_XUSB_CFG_4 BAR SIZE 32KB"
|
|
rbitfld.long 0x00 3. " PREFETCHABLE ,T_XUSB_CFG_4 PREFETCHABLE" "Not prefetchable,Prefetchable"
|
|
rbitfld.long 0x00 1.--2. " ADDRESS_TYPE ,The ADDRESS_TYPE bits contain the type of the base address" "32,,64,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 0. " SPACE_TYPE ,The SPACE_TYPE bit indicates whether the register maps into memory or I/O space" "Memory,IO"
|
|
line.long 0x04 "CFG_5,XUSB Configuration Register 5"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "CFG_11,PCI Configuration Register 11"
|
|
hexmask.long.word 0x00 16.--31. 1. " SUBSYSTEM_ID ,T_XUSB_CFG_11 SUBSYSTEM ID"
|
|
hexmask.long.word 0x00 0.--15. 1. " SUBSYSTEM_VENDOR_ID ,T_XUSB_CFG_11 SUBSYSTEM VENDOR ID"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "CFG_13,PCI Configuration Register 13"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAP_PTR ,CAP pointer"
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "CFG_15,PCI Configuration Register 15"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAX_LAT ,Maximum time the device requires to gain access to the CPI bus"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MIN_GNT ,Length of the burst period a device needs assuming a clock rate of 33 mhz"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTR_PIN ,Interrupt pin the device uses"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTR_LINE ,Interrupt routing information"
|
|
line.long 0x04 "CFG_16,PCI Configuration Register 16"
|
|
hexmask.long.word 0x04 16.--31. 1. " SUBSYSTEM_ID ,SUBSYSTEM ID"
|
|
hexmask.long.word 0x04 0.--15. 1. " SUBSYSTEM_VENDOR_ID ,SUBSYSTEM VENDOR ID"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CFG_17,PCI Configuration Register 17"
|
|
bitfld.long 0x00 31. " D3CPME_SUPPORT ,T_XUSB_CFG_17 D3CPME SUPPORT" "Not supported,Supported"
|
|
bitfld.long 0x00 30. " D3HPME_SUPPORT ,T_XUSB_CFG_17 D3HPME SUPPORT" "Not supported,Supported"
|
|
bitfld.long 0x00 29. " D2PME_SUPPORT ,T_XUSB_CFG_17 D2PME SUPPORT" "Not supported,Supported"
|
|
bitfld.long 0x00 28. " D1PME_SUPPORT ,T_XUSB_CFG_17 D1PME SUPPORT" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 27. " D0PME_SUPPORT ,T_XUSB_CFG_17 D0PME SUPPORT" "Not supported,Supported"
|
|
bitfld.long 0x00 26. " D2_SUPPORT ,T_XUSB_CFG_17 D2 SUPPORT" "Not supported,Supported"
|
|
bitfld.long 0x00 25. " D1_SUPPORT ,T_XUSB_CFG_17 D1 SUPPORT" "Not supported,Supported"
|
|
bitfld.long 0x00 22.--24. " AUXCUR ,T_XUSB_CFG_17 AUXCUR" "Self,55 mA,100 mA,160 mA,220 mA,270 mA,320 mA,375 mA"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSI ,T_XUSB_CFG_17 DSI" "Not needed,Needed"
|
|
bitfld.long 0x00 19. " PMECLK ,T_XUSB_CFG_17 PMECLK" "Not required,Required"
|
|
bitfld.long 0x00 16.--18. " VER ,T_XUSB_CFG_17 VER" ",,,VER_1P2,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " NEXT_PTR ,T_XUSB_CFG_17 NEXT PTR"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAP ,T_XUSB_CFG_17 CAP"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CFG_18,T_XUSB_CFG_18 PMCSR"
|
|
eventfld.long 0x00 15. " PMCSR_PMESTATUS ,T_XUSB_CFG_18 PMCSR PMESTATUS" "Not pending,Pending"
|
|
rbitfld.long 0x00 13.--14. " PMCSR_DSCALE ,T_XUSB_CFG_18 PMCSR DSCALE" "DSCALE_INIT,?..."
|
|
rbitfld.long 0x00 9.--12. " PMCSR_DSEL ,T_XUSB_CFG_18 PMCSR DSEL" "DSEL_INIT,?..."
|
|
bitfld.long 0x00 8. " PMCSR_PME ,T_XUSB_CFG_18 PMCSR PME" "Enabled,Disabled"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " PMCSR_NSR ,T_XUSB_CFG_18 PMCSR NSR" "No reset,Reset"
|
|
bitfld.long 0x00 0.--1. " PMCSR_PWRSTATE ,PMCSR_PWRSTATE" "D0,D1,D2,D3H"
|
|
sif (cpu()=="TEGRAX1"||cpu()=="TEGRAX2")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CFG_24,XUSB XHCI Configuration Control"
|
|
bitfld.long 0x00 8.--13. " FLADJ ,Frame length adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SBRN ,Serial bus release number register"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CFG_24,XUSB XHCI Configuration Control"
|
|
bitfld.long 0x00 8.--13. " FLADJ ,Frame length adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SBRN ,Serial bus release number register"
|
|
endif
|
|
textline " "
|
|
width 11.
|
|
group.long 0xC0++0x0F
|
|
line.long 0x00 "MSI_CTRL,MSI Message Control And Capability Register"
|
|
rbitfld.long 0x00 24. " VECTOR_MASK_CAP ,MSI-per-vector masking support" "Not supported,Supported"
|
|
rbitfld.long 0x00 23. " 64_ADDR_CAP ,Generating a 64-bit message address capability" "Not capable,Capable"
|
|
bitfld.long 0x00 20.--22. " MULT_MSG_ENABLE ,System software writes to this field to indicate the number of allocated vectors" "1,2,4,8,16,32,?..."
|
|
rbitfld.long 0x00 17.--19. " MULT_MSG_CAP ,Number of requested vectors" "1,2,4,8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSI_ENABLE ,Enables the MSI capability" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NEXT_PTR ,Next item in the capabilities list"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAP_ID ,Capability block as the MSI capability block"
|
|
line.long 0x04 "MSI_ADDR1,MSI Message Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " MSG_ADDR ,System-specified message address"
|
|
line.long 0x08 "MSI_ADDR2,MSI Message Upper Address Register"
|
|
line.long 0x0C "MSI_DATA,MSI Message Data Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " MSG_DATA ,System-specified message data"
|
|
sif (cpu()=="TEGRAX1"||cpu()=="TEGRAX2")
|
|
group.long 0xD0++0x07
|
|
line.long 0x00 "MSI_MASK,MSI Message Data Register"
|
|
bitfld.long 0x00 0. " BIT ,T_XUSB_MSI_MASK_BIT" "0,1"
|
|
line.long 0x04 "MSI_PEND,MSI Pending Bits Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " BIT ,T_XUSB_MSI_PEND_BIT"
|
|
endif
|
|
tree.end
|
|
width 18.
|
|
tree "XUSB Mailbox"
|
|
group.long 0xE0++0x13
|
|
line.long 0x00 "MAILBOX_CAP,CFG ARU MAILBOX CAP"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LENGTH ,CFG ARU MAILBOX CAP LENGTH"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NEXTPTR ,CFG ARU MAILBOX CAP NEXTPTR"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ID ,CFG ARU MAILBOX CAP ID"
|
|
line.long 0x04 "MAILBOX_CMD,CFG ARU MAILBOX CMD"
|
|
bitfld.long 0x04 31. " INT_EN ,CFG ARU MAILBOX CMD INT EN" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " DEST_XHCI ,CFG ARU MAILBOX CMD DEST XHCI" "Initialized,Completed"
|
|
bitfld.long 0x04 29. " DEST_SMI ,CFG ARU MAILBOX CMD DEST SMI" "Initialized,Completed"
|
|
bitfld.long 0x04 28. " DEST_PME ,CFG ARU MAILBOX CMD DEST PME" "Initialized,Completed"
|
|
bitfld.long 0x04 27. " DEST_FALCON ,CFG ARU MAILBOX CMD DEST FALCON" "Initialized,Completed"
|
|
line.long 0x08 "MAILBOX_DATA_IN,CFG ARU MAILBOX DATA IN"
|
|
line.long 0x0C "MAILBOX_DATA_OUT,CFG ARU MAILBOX DATA OUT"
|
|
line.long 0x10 "MAILBOX_OWNER,CFG ARU MAILBOX OWNER"
|
|
hexmask.long.byte 0x10 0.--7. 1. " ID ,CFG ARU MAILBOX OWNER ID"
|
|
tree.end
|
|
sif (cpu()=="TEGRAX1")
|
|
base ad:0x70090000
|
|
width 21.
|
|
tree "XUSB XHCI Registers"
|
|
rgroup.long 0x00++0x1B
|
|
line.long 0x00 "CAP_REG0,CAP REG0"
|
|
sif (cpu()=="TEGRAX1"||cpu()=="TEGRAX2")
|
|
hexmask.long.word 0x00 16.--31. 1. " HCIVERSION ,CAP REG0 HCIVERSION"
|
|
textline " "
|
|
else
|
|
hexmask.long.tbyte 0x00 15.--31. 1. " HCIVERSION ,CAP REG0 HCIVERSION"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,CAP REG0 CAPLENGTH"
|
|
line.long 0x04 "CAP_HCSPARAMS1,CAP HCSPARAMS1"
|
|
hexmask.long.byte 0x04 24.--31. 1. " MAXPORTS ,CAP HCSPARAMS1 MAXPORTS"
|
|
hexmask.long.word 0x04 8.--18. 1. " MAXINTRS ,CAP HCSPARAMS1 MAXINTRS"
|
|
hexmask.long.byte 0x04 0.--7. 1. " MAXSLOTS ,CAP HCSPARAMS1 MAXSLOTS"
|
|
line.long 0x08 "CAP_HCSPARAMS2,CAP HCSPARAMS2"
|
|
bitfld.long 0x08 27.--31. " MAXSPBLO ,CAP HCSPARAMS2 MAXSPBLO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 26. " SPR ,CAP HCSPARAMS2 SPR" "False,True"
|
|
bitfld.long 0x08 21.--25. " MAXSPBHI ,CAP HCSPARAMS2 MAXSPBHI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 4.--7. " ERST_MAX ,CAP HCSPARAMS2 ERST MAX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " IST ,CAP HCSPARAMS2 IST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "CAP_HCSPARAMS3,CAP HCSPARAMS3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " U2LAT ,CAP HCSPARAMS3 U2LAT"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " U1LAT ,CAP HCSPARAMS3 U1LAT"
|
|
line.long 0x10 "CAP_HCCPARAMS,CAP HCCPARAMS"
|
|
hexmask.long.word 0x10 16.--31. 1. " XECP ,CAP HCCPARAMS XECP"
|
|
bitfld.long 0x10 12.--15. " MAXPSASIZE ,CAP HCCPARAMS MAXPSASIZE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8. " PAE ,CAP HCCPARAMS PAE" "False,True"
|
|
bitfld.long 0x10 7. " NSS ,CAP HCCPARAMS NSS" "False,True"
|
|
textline " "
|
|
bitfld.long 0x10 6. " LTC ,CAP HCCPARAMS LTC" "False,True"
|
|
bitfld.long 0x10 5. " LHRC ,CAP HCCPARAMS LHRC" "False,True"
|
|
bitfld.long 0x10 4. " PIND ,CAP HCCPARAMS PIND" "False,True"
|
|
bitfld.long 0x10 3. " PPC ,CAP HCCPARAMS PPC" "False,True"
|
|
textline " "
|
|
bitfld.long 0x10 2. " CSZ ,CAP HCCPARAMS CSZ" "32B,64B"
|
|
bitfld.long 0x10 1. " BNC ,CAP HCCPARAMS BNC" "False,True"
|
|
bitfld.long 0x10 0. " AC64 ,CAP HCCPARAMS AC64" "False,True"
|
|
line.long 0x14 "CAP_DBOFF,CAP DBOFF"
|
|
hexmask.long 0x14 2.--31. 0x04 " OFFSET ,CAP DBOFF OFFSET"
|
|
line.long 0x18 "CAP_RTSOFF,CAP RTSOFF"
|
|
hexmask.long 0x18 5.--31. 0x20 " OFFSET ,CAP RTSOFF OFFSET"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "OP_USBCMD,OP USBCMD"
|
|
bitfld.long 0x00 11. " EU3S ,OP USBCMD EU3S" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " EWE ,OP USBCMD EWE" "Disabled,Enabled"
|
|
eventfld.long 0x00 9. " CRS ,OP USBCMD CRS" "Initialized,Start"
|
|
eventfld.long 0x00 8. " CSS ,OP USBCMD CSS" "Initialized,Start"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LHCRST ,OP USBCMD LHCRST" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " HSEE ,OP USBCMD HSEE" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTE ,OP USBCMD INTE" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HCRST ,OP USBCMD HCRST" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RS ,OP USBCMD RS" "Stopped,Running"
|
|
line.long 0x04 "OP_USBSTS,OP USBSTS"
|
|
rbitfld.long 0x04 12. " HCE ,OP USBSTS HCE" "No error,Error"
|
|
rbitfld.long 0x04 11. " CNR ,OP USBSTS CNR" "Not ready,Ready"
|
|
eventfld.long 0x04 10. " SRE ,OP USBSTS SRE" "Not pending,Pending"
|
|
rbitfld.long 0x04 9. " RSS ,OP USBSTS RSS" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x04 8. " SSS ,OP USBSTS SSS" "Not pending,Pending"
|
|
eventfld.long 0x04 4. " PCD ,OP USBSTS PCD" "Not pending,Pending"
|
|
eventfld.long 0x04 3. " EINT ,OP USBSTS EINT" "Not pending,Pending"
|
|
eventfld.long 0x04 2. " HSE ,OP USBSTS HSE" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " HCH ,HCH" "Halted,Running"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "OP_PGSZ,OP PGSZ"
|
|
hexmask.long.word 0x00 0.--15. 1. " PAGESIZE ,OP PGSZ PAGESIZE"
|
|
group.long 0x34++0x0B
|
|
line.long 0x00 "OP_DNCTRL,OP DNCTRL"
|
|
bitfld.long 0x00 15. " N15 ,OP DNCTRL N15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " N14 ,OP DNCTRL N14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " N13 ,OP DNCTRL N13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " N12 ,OP DNCTRL N12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " N11 ,OP DNCTRL N11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " N10 ,OP DNCTRL N10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " N9 ,OP DNCTRL N9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " N8 ,OP DNCTRL N8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " N7 ,OP DNCTRL N7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " N6 ,OP DNCTRL N6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " N5 ,OP DNCTRL N5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " N4 ,OP DNCTRL N4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " N3 ,OP DNCTRL N3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " N2 ,OP DNCTRL N2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " N1 ,OP DNCTRL N1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " N0 ,OP DNCTRL N0" "Disabled,Enabled"
|
|
line.long 0x04 "OP_CRCR0,OP CRCR0"
|
|
hexmask.long 0x04 6.--31. 1. " CRPLO ,OP CRCR0 CRPLO"
|
|
textline " "
|
|
rbitfld.long 0x04 3. " CRR ,OP CRCR0 CRR" "Stopped,Running"
|
|
eventfld.long 0x04 2. " CA ,OP CRCR0 CA" "Initialized,Aborted"
|
|
textline " "
|
|
eventfld.long 0x04 1. " CS ,OP CRCR0 CS" "Initialized,Stop"
|
|
eventfld.long 0x04 0. " RCS ,OP CRCR0 RCS" "0,1"
|
|
line.long 0x08 "OP_CRCR1,OP CRCR1"
|
|
group.long 0x50++0x0B
|
|
line.long 0x00 "OP_DCBAAP0,OP DCBAAP0"
|
|
hexmask.long 0x00 6.--31. 1. " DCBAAPLO ,OP DCBAAP0 DCBAAPLO"
|
|
line.long 0x04 "OP_DCBAAP1,OP DCBAAP1"
|
|
line.long 0x08 "OP_CONFIG,OP CONFIG"
|
|
hexmask.long.byte 0x08 0.--7. 1. " MAXSLOTSEN ,OP CONFIG MAXSLOTSEN"
|
|
textline " "
|
|
sif (cpu()=="TEGRAX1"||cpu()=="TEGRAX2")
|
|
width 23.
|
|
group.long 0x420++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x420+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x420+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x420+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x420+0x08)++0x03
|
|
line.long 0x00 "OP_PORTLISC,OP PORTLISC"
|
|
hexmask.long.word 0x00 0.--15. 1. " LEC ,T XUSB OP PORTLISC LEC"
|
|
rgroup.long (0x420+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x430++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x430+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x430+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x430+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x430+0x08)++0x03
|
|
line.long 0x00 "OP_PORTLISC,OP PORTLISC"
|
|
hexmask.long.word 0x00 0.--15. 1. " LEC ,T XUSB OP PORTLISC LEC"
|
|
rgroup.long (0x430+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x440++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x440+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x440+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x440+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x440+0x08)++0x03
|
|
line.long 0x00 "OP_PORTLISC,OP PORTLISC"
|
|
hexmask.long.word 0x00 0.--15. 1. " LEC ,T XUSB OP PORTLISC LEC"
|
|
rgroup.long (0x440+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x450++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x450+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x450+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x450+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x450+0x08)++0x03
|
|
line.long 0x00 "OP_PORTLISC,OP PORTLISC"
|
|
hexmask.long.word 0x00 0.--15. 1. " LEC ,T XUSB OP PORTLISC LEC"
|
|
rgroup.long (0x450+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x460++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x460+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x460+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x460+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x460+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x470++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x470+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x470+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x470+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x470+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x480++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x480+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x480+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x480+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x480+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x490++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x490+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x490+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x490+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x490+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x4A0++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x4A0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x4A0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x4A0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x4A0+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x4B0++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x4B0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x4B0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x4B0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x4B0+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x4C0++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x4C0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x4C0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x4C0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x4C0+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x4D0++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x4D0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x4D0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x4D0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x4D0+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x4E0++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x4E0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x4E0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x4E0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x4E0+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x4F0++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x4F0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x4F0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x4F0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x4F0+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x500++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x500+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x500+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x500+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x500+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x510++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x510+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x510+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x510+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x510+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
endif
|
|
textline " "
|
|
width 24.
|
|
group.long 0x600++0x07
|
|
line.long 0x00 "EC_USBLEGSUP,EC USBLEGSUP"
|
|
bitfld.long 0x00 24. " OSSEM ,EC USBLEGSUP OSSEM" "0,1"
|
|
bitfld.long 0x00 16. " BIOSSEM ,T XUSB EC USBLEGSUP BIOSSEM" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NEXT ,EC USBLEGSUP NEXT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAPID ,EC USBLEGSUP CAPID"
|
|
line.long 0x04 "HCI_EC_USBLEGCTLSTS,HCI_EC_USBLEGCTLSTS"
|
|
eventfld.long 0x04 31. " BAR ,EC USBLEGCTLSTS BAR" "Not pending,Pending"
|
|
eventfld.long 0x04 30. " PCIC ,EC USBLEGCTLSTS PCIC" "Not pending,Pending"
|
|
eventfld.long 0x04 29. " OSOC ,EC USBLEGCTLSTS OSOC" "Not pending,Pending"
|
|
rbitfld.long 0x04 20. " HSE ,EC USBLEGCTLSTS HSE" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x04 16. " EVI ,EC USBLEGCTLSTS EVI" "Not pending,Pending"
|
|
bitfld.long 0x04 15. " BAREN ,EC USBLEGCTLSTS BAR enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " PCIEN ,EC USBLEGCTLSTS PCI enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " OSOEN ,EC USBLEGCTLSTS OSO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " HSEEN ,EC USBLEGCTLSTS HSE enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SMIEN ,EC USBLEGCTLSTS SMI enable" "Disabled,Enabled"
|
|
rgroup.long 0x610++0x23
|
|
line.long 0x00 "EC_SUPPROT_USB3_0,EC SUPPROT USB3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJORREV ,EC SUPPROT USB3 0 MAJORREV"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINORREV ,EC SUPPROT USB3 0 MINORREV"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NEXT ,EC SUPPROT USB3 0 NEXT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAPID ,EC SUPPROT USB3 0 CAPID"
|
|
line.long 0x04 "EC_SUPPROT_USB3_1,EC SUPPROT USB3 1"
|
|
line.long 0x08 "EC_SUPPROT_USB3_2,EC SUPPROT USB3 2"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PORTCNT ,EC SUPPROT USB3 2 PORTCNT"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PORTOFS ,EC SUPPROT USB3 2 PORTOFS"
|
|
line.long 0x0C "EC_SUPPROT_USB3_3,EC SUPPROT USB3 3"
|
|
line.long 0x10 "EC_SUPPROT_USB2_0,EC SUPPROT USB2 0"
|
|
hexmask.long.byte 0x10 24.--31. 1. " MAJORREV ,EC SUPPROT USB2 0 MAJORREV"
|
|
hexmask.long.byte 0x10 16.--23. 1. " MINORREV ,EC SUPPROT USB2 0 MINORREV"
|
|
hexmask.long.byte 0x10 8.--15. 1. " XNEXT ,EC SUPPROT USB2 0 NEXT"
|
|
hexmask.long.byte 0x10 0.--7. 1. " CAPID ,EC SUPPROT USB2 0 CAPID"
|
|
line.long 0x14 "EC_SUPPROT_USB2_1,EC SUPPROT USB2 1"
|
|
line.long 0x18 "EC_SUPPROT_USB2_2,EC SUPPROT USB2 2"
|
|
bitfld.long 0x18 25.--27. " MHD ,EC SUPPROT USB2 2 MHD" "MHD,?..."
|
|
bitfld.long 0x18 20. " BLC ,EC_SUPPROT_USB2_2_BLC" "False,True"
|
|
bitfld.long 0x18 19. " HLC ,EC_SUPPROT_USB2_2_HLC" "False,True"
|
|
bitfld.long 0x18 18. " IHI ,EC_SUPPROT_USB2_2_IHI" "True,False"
|
|
textline " "
|
|
bitfld.long 0x18 17. " HSO ,EC_SUPPROT_USB2_2_HSO" "True,False"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PORTCNT ,EC SUPPROT USB2 2 PORTCNT"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PORTOFS ,EC SUPPROT USB2 2 PORTOFS"
|
|
line.long 0x1C "EC_SUPPROT_USB2_3,EC SUPPROT USB2 3"
|
|
line.long 0x20 "EC_DBCAP_DCID,EC_DBCAP_DCID"
|
|
bitfld.long 0x20 16.--20. " DCERSTM ,EC_DBCAP_DCID_DCERSTM" ",DCERSTM_VALUE,?..."
|
|
hexmask.long.byte 0x20 8.--15. 1. " NEXT ,EC DBCAP DCID NEXT"
|
|
hexmask.long.byte 0x20 0.--7. 1. " CAPID ,EC DBCAP DCID CAPID"
|
|
wgroup.long 0x634++0x03
|
|
line.long 0x00 "EC_DBCAP_DCDB,EC DBCAP DCDB"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DBTARGET ,EC DBCAP DCDB DBTARGET"
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "EC_DBCAP_DCERSTSZ,EC DBCAP DCERSTSZ"
|
|
hexmask.long.word 0x00 0.--15. 1. " ERSTSZ ,EC DBCAP DCERSTSZ ERSTSZ"
|
|
textline " "
|
|
width 26.
|
|
group.long 0x640++0x13
|
|
line.long 0x00 "EC_DBCAP_DCERSTBALO,EC DBCAP DCERSTBALO"
|
|
hexmask.long 0x00 4.--31. 1. " ADDRLO ,EC DBCAP DCERSTBALO"
|
|
line.long 0x04 "EC_DBCAP_DCERSTBAHI,EC DBCAP DCERSTBAHI"
|
|
line.long 0x08 "EC_DBCAP_DCERDPLO,EC DBCAP DCERDPLO"
|
|
hexmask.long 0x08 4.--31. 1. " ADDRLO ,EC DBCAP DCERDPLO ADDRLO"
|
|
bitfld.long 0x08 0.--2. " DESI ,EC DBCAP DCERDPLO DESI" "Initialized,?..."
|
|
line.long 0x0C "EC_DBCAP_DCERDPHI,EC DBCAP DCERDPHI ADDRHI"
|
|
line.long 0x10 "EC_DBCAP_DCCTRL,EC DBCAP DCCTRL"
|
|
bitfld.long 0x10 31. " DCE ,EC DBCAP DCCTRL DCE" "Disabled,Enabled"
|
|
hexmask.long.byte 0x10 24.--30. 1. " DEVADR ,EC DBCAP DCCTRL DEVADR"
|
|
hexmask.long.byte 0x10 16.--23. 1. " MAXBURST ,EC DBCAP DCCTRL MAXBURST"
|
|
eventfld.long 0x10 4. " DRC ,EC DBCAP DCCTRL DRC" "Initialized,Clear"
|
|
textline " "
|
|
bitfld.long 0x10 3. " HIT ,EC DBCAP DCCTRL HIT" "False,True"
|
|
bitfld.long 0x10 2. " HOT ,EC DBCAP DCCTRL HOT" "False,True"
|
|
bitfld.long 0x10 1. " LSE ,EC DBCAP DCCTRL LSE" "Disabled,Enabled"
|
|
rbitfld.long 0x10 0. " DCR ,EC DBCAP DCCTRL DCR" "Stop,Run"
|
|
rgroup.long 0x654++0x03
|
|
line.long 0x00 "EC_DBCAP_DCST,EC DBCAP DCST"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DPN ,EC DBCAP DCST DPN"
|
|
bitfld.long 0x00 0. " ER ,EC DBCAP DCST ER" "Empty,Not empty"
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "EC_DBCAP_DCPORTSC,EC DBCAP DCPORTSC"
|
|
eventfld.long 0x00 23. " CEC ,EC DBCAP DCPORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,EC DBCAP DCPORTSC PLC" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " PRC ,EC DBCAP DCPORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " CSC ,EC DBCAP DCPORTSC CSC" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 10.--13. " PS ,EC DBCAP DCPORTSC PS" "Undefined,,,,SS,?..."
|
|
rbitfld.long 0x00 5.--8. " PLS ,EC DBCAP DCPORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detect,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
rbitfld.long 0x00 4. " PR ,EC DBCAP DCPORTSC PR" "No reset,Reset"
|
|
bitfld.long 0x00 1. " PED ,HCI EC DBCAP DCPORTSC PED" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " CCS ,EC DBCAP DCPORTSC CCS" "No CON,CON"
|
|
group.long 0x660++0x0F
|
|
line.long 0x00 "EC_DBCAP_DCECPLO,EC DBCAP DCECPLO"
|
|
hexmask.long 0x00 4.--31. 1. " ADDRLO ,EC DBCAP DCECPLO ADDRLO"
|
|
line.long 0x04 "EC_DBCAP_DCECPHI,EC DBCAP DCECPHI ADDRHI"
|
|
line.long 0x08 "EC_DBCAP_INFO0,EC DBCAP INFO0"
|
|
hexmask.long.word 0x08 16.--31. 1. " VENDORID ,EC DBCAP INFO0 VENDORID"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PROTOCOL ,EC DBCAP INFO0 PROTOCOL"
|
|
line.long 0x0C "EC_DBCAP_INFO1,EC_DBCAP_INFO1"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DEV_REV ,EC DBCAP INFO1 DEV REV"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PRODUCTID ,EC DBCAP INFO1 PRODUCTID"
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "RT_MFINDEX,RT MFINDEX"
|
|
hexmask.long.word 0x00 0.--13. 1. " MFINDEX ,RT MFINDEX MFINDEX"
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "RT_IMAN,RT IMAN"
|
|
bitfld.long 0x00 1. " IE ,RT IMAN IE" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " IP ,RT IMAN IP" "Not pending,Pending"
|
|
group.long 0x824++0x07
|
|
line.long 0x00 "RT_IMOD,RT IMOD"
|
|
hexmask.long.word 0x00 16.--31. 1. " IMODC ,RT IMOD IMODC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IMODI ,RT IMOD IMODI"
|
|
line.long 0x04 "RT_ERSTSZ,RT ERSTSZ"
|
|
hexmask.long.word 0x04 0.--15. 1. " SZ ,RT ERSTSZ SZ"
|
|
group.long 0x830++0x0F
|
|
line.long 0x00 "RT_ERSTBA0,RT ERSTBA0"
|
|
hexmask.long 0x00 4.--31. 1. " ERSTBLO ,RT ERSTBA0 ERSTBLO"
|
|
line.long 0x04 "RT_ERSTBA1,RT ERSTBA1"
|
|
line.long 0x08 "RT_ERDP0,RT ERDP0"
|
|
hexmask.long 0x08 4.--31. 1. " DQPTRLO ,RT ERDP0 DQPTRLO"
|
|
bitfld.long 0x08 0.--2. " DESI ,RT ERDP0 DESI" "Initialized,?..."
|
|
line.long 0x0C "RT_ERDP1,RT ERDP1"
|
|
wgroup.long 0xC00++0x03
|
|
line.long 0x00 "DB,DB"
|
|
button "BGR" "d (0xC00)--(0xFFC) /long"
|
|
tree.end
|
|
width 0x0B
|
|
elif (cpu()=="TEGRAX2")
|
|
base ad:0x03530000
|
|
width 21.
|
|
tree "XUSB XHCI Registers"
|
|
rgroup.long 0x00++0x1B
|
|
line.long 0x00 "CAP_REG0,CAP REG0"
|
|
sif (cpu()=="TEGRAX1"||cpu()=="TEGRAX2")
|
|
hexmask.long.word 0x00 16.--31. 1. " HCIVERSION ,CAP REG0 HCIVERSION"
|
|
textline " "
|
|
else
|
|
hexmask.long.tbyte 0x00 15.--31. 1. " HCIVERSION ,CAP REG0 HCIVERSION"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,CAP REG0 CAPLENGTH"
|
|
line.long 0x04 "CAP_HCSPARAMS1,CAP HCSPARAMS1"
|
|
hexmask.long.byte 0x04 24.--31. 1. " MAXPORTS ,CAP HCSPARAMS1 MAXPORTS"
|
|
hexmask.long.word 0x04 8.--18. 1. " MAXINTRS ,CAP HCSPARAMS1 MAXINTRS"
|
|
hexmask.long.byte 0x04 0.--7. 1. " MAXSLOTS ,CAP HCSPARAMS1 MAXSLOTS"
|
|
line.long 0x08 "CAP_HCSPARAMS2,CAP HCSPARAMS2"
|
|
bitfld.long 0x08 27.--31. " MAXSPBLO ,CAP HCSPARAMS2 MAXSPBLO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 26. " SPR ,CAP HCSPARAMS2 SPR" "False,True"
|
|
bitfld.long 0x08 21.--25. " MAXSPBHI ,CAP HCSPARAMS2 MAXSPBHI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 4.--7. " ERST_MAX ,CAP HCSPARAMS2 ERST MAX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " IST ,CAP HCSPARAMS2 IST" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "CAP_HCSPARAMS3,CAP HCSPARAMS3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " U2LAT ,CAP HCSPARAMS3 U2LAT"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " U1LAT ,CAP HCSPARAMS3 U1LAT"
|
|
line.long 0x10 "CAP_HCCPARAMS,CAP HCCPARAMS"
|
|
hexmask.long.word 0x10 16.--31. 1. " XECP ,CAP HCCPARAMS XECP"
|
|
bitfld.long 0x10 12.--15. " MAXPSASIZE ,CAP HCCPARAMS MAXPSASIZE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8. " PAE ,CAP HCCPARAMS PAE" "False,True"
|
|
bitfld.long 0x10 7. " NSS ,CAP HCCPARAMS NSS" "False,True"
|
|
textline " "
|
|
bitfld.long 0x10 6. " LTC ,CAP HCCPARAMS LTC" "False,True"
|
|
bitfld.long 0x10 5. " LHRC ,CAP HCCPARAMS LHRC" "False,True"
|
|
bitfld.long 0x10 4. " PIND ,CAP HCCPARAMS PIND" "False,True"
|
|
bitfld.long 0x10 3. " PPC ,CAP HCCPARAMS PPC" "False,True"
|
|
textline " "
|
|
bitfld.long 0x10 2. " CSZ ,CAP HCCPARAMS CSZ" "32B,64B"
|
|
bitfld.long 0x10 1. " BNC ,CAP HCCPARAMS BNC" "False,True"
|
|
bitfld.long 0x10 0. " AC64 ,CAP HCCPARAMS AC64" "False,True"
|
|
line.long 0x14 "CAP_DBOFF,CAP DBOFF"
|
|
hexmask.long 0x14 2.--31. 0x04 " OFFSET ,CAP DBOFF OFFSET"
|
|
line.long 0x18 "CAP_RTSOFF,CAP RTSOFF"
|
|
hexmask.long 0x18 5.--31. 0x20 " OFFSET ,CAP RTSOFF OFFSET"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "OP_USBCMD,OP USBCMD"
|
|
bitfld.long 0x00 11. " EU3S ,OP USBCMD EU3S" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " EWE ,OP USBCMD EWE" "Disabled,Enabled"
|
|
eventfld.long 0x00 9. " CRS ,OP USBCMD CRS" "Initialized,Start"
|
|
eventfld.long 0x00 8. " CSS ,OP USBCMD CSS" "Initialized,Start"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LHCRST ,OP USBCMD LHCRST" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " HSEE ,OP USBCMD HSEE" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTE ,OP USBCMD INTE" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HCRST ,OP USBCMD HCRST" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RS ,OP USBCMD RS" "Stopped,Running"
|
|
line.long 0x04 "OP_USBSTS,OP USBSTS"
|
|
rbitfld.long 0x04 12. " HCE ,OP USBSTS HCE" "No error,Error"
|
|
rbitfld.long 0x04 11. " CNR ,OP USBSTS CNR" "Not ready,Ready"
|
|
eventfld.long 0x04 10. " SRE ,OP USBSTS SRE" "Not pending,Pending"
|
|
rbitfld.long 0x04 9. " RSS ,OP USBSTS RSS" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x04 8. " SSS ,OP USBSTS SSS" "Not pending,Pending"
|
|
eventfld.long 0x04 4. " PCD ,OP USBSTS PCD" "Not pending,Pending"
|
|
eventfld.long 0x04 3. " EINT ,OP USBSTS EINT" "Not pending,Pending"
|
|
eventfld.long 0x04 2. " HSE ,OP USBSTS HSE" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " HCH ,HCH" "Halted,Running"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "OP_PGSZ,OP PGSZ"
|
|
hexmask.long.word 0x00 0.--15. 1. " PAGESIZE ,OP PGSZ PAGESIZE"
|
|
group.long 0x34++0x0B
|
|
line.long 0x00 "OP_DNCTRL,OP DNCTRL"
|
|
bitfld.long 0x00 15. " N15 ,OP DNCTRL N15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " N14 ,OP DNCTRL N14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " N13 ,OP DNCTRL N13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " N12 ,OP DNCTRL N12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " N11 ,OP DNCTRL N11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " N10 ,OP DNCTRL N10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " N9 ,OP DNCTRL N9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " N8 ,OP DNCTRL N8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " N7 ,OP DNCTRL N7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " N6 ,OP DNCTRL N6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " N5 ,OP DNCTRL N5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " N4 ,OP DNCTRL N4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " N3 ,OP DNCTRL N3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " N2 ,OP DNCTRL N2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " N1 ,OP DNCTRL N1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " N0 ,OP DNCTRL N0" "Disabled,Enabled"
|
|
line.long 0x04 "OP_CRCR0,OP CRCR0"
|
|
hexmask.long 0x04 6.--31. 1. " CRPLO ,OP CRCR0 CRPLO"
|
|
textline " "
|
|
rbitfld.long 0x04 3. " CRR ,OP CRCR0 CRR" "Stopped,Running"
|
|
eventfld.long 0x04 2. " CA ,OP CRCR0 CA" "Initialized,Aborted"
|
|
textline " "
|
|
eventfld.long 0x04 1. " CS ,OP CRCR0 CS" "Initialized,Stop"
|
|
eventfld.long 0x04 0. " RCS ,OP CRCR0 RCS" "0,1"
|
|
line.long 0x08 "OP_CRCR1,OP CRCR1"
|
|
group.long 0x50++0x0B
|
|
line.long 0x00 "OP_DCBAAP0,OP DCBAAP0"
|
|
hexmask.long 0x00 6.--31. 1. " DCBAAPLO ,OP DCBAAP0 DCBAAPLO"
|
|
line.long 0x04 "OP_DCBAAP1,OP DCBAAP1"
|
|
line.long 0x08 "OP_CONFIG,OP CONFIG"
|
|
hexmask.long.byte 0x08 0.--7. 1. " MAXSLOTSEN ,OP CONFIG MAXSLOTSEN"
|
|
textline " "
|
|
sif (cpu()=="TEGRAX1"||cpu()=="TEGRAX2")
|
|
width 23.
|
|
group.long 0x420++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x420+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x420+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x420+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x420+0x08)++0x03
|
|
line.long 0x00 "OP_PORTLISC,OP PORTLISC"
|
|
hexmask.long.word 0x00 0.--15. 1. " LEC ,T XUSB OP PORTLISC LEC"
|
|
rgroup.long (0x420+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x430++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x430+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x430+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x430+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x430+0x08)++0x03
|
|
line.long 0x00 "OP_PORTLISC,OP PORTLISC"
|
|
hexmask.long.word 0x00 0.--15. 1. " LEC ,T XUSB OP PORTLISC LEC"
|
|
rgroup.long (0x430+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x440++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x440+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x440+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x440+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x440+0x08)++0x03
|
|
line.long 0x00 "OP_PORTLISC,OP PORTLISC"
|
|
hexmask.long.word 0x00 0.--15. 1. " LEC ,T XUSB OP PORTLISC LEC"
|
|
rgroup.long (0x440+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x450++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x450+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x450+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x450+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x450+0x08)++0x03
|
|
line.long 0x00 "OP_PORTLISC,OP PORTLISC"
|
|
hexmask.long.word 0x00 0.--15. 1. " LEC ,T XUSB OP PORTLISC LEC"
|
|
rgroup.long (0x450+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x460++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x460+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x460+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x460+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x460+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x470++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x470+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x470+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x470+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x470+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x480++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x480+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x480+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x480+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x480+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x490++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x490+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x490+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x490+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x490+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x4A0++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x4A0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x4A0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x4A0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x4A0+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x4B0++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x4B0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x4B0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x4B0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x4B0+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x4C0++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x4C0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x4C0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x4C0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x4C0+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x4D0++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x4D0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x4D0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x4D0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x4D0+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x4E0++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x4E0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x4E0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x4E0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x4E0+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x4F0++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x4F0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x4F0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x4F0+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x4F0+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x500++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x500+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x500+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x500+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x500+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
group.long 0x510++0x07
|
|
line.long 0x00 "OP PORTSC,OP PORTSC"
|
|
rbitfld.long 0x00 31. " WPR ,OP PORTSC WPR" "Not pending,Pending"
|
|
rbitfld.long 0x00 30. " DR ,T XUSB OP PORTSC DR" "False,True"
|
|
bitfld.long 0x00 27. " WOE ,T XUSB OP PORTSC WOE" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDE ,T XUSB OP PORTSC WDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCE ,T XUSB OP PORTSC WCE" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " CAS ,T XUSB OP PORTSC CAS" "Initialized,?..."
|
|
eventfld.long 0x00 23. " CEC ,T XUSB OP PORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,T XUSB OP PORTSC PLC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 21. " PRC ,T XUSB OP PORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " OCC ,T XUSB OP PORTSC OCC" "Not pending,Pending"
|
|
eventfld.long 0x00 19. " WRC ,T XUSB OP PORTSC WRC" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " PEC ,T XUSB OP PORTSC PEC" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 17. " CSC ,T XUSB OP PORTSC CSC" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " LWS ,T XUSB OP PORTSC LWS" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PIC ,T XUSB OP PORTSC PIC" "Off,Amber,Green,Undefined"
|
|
rbitfld.long 0x00 10.--13. " PSPD ,T XUSB OP PORTSC PSPD" "UNDEFINED,FS,LS,HS,SS,,,,,,,,,,,Unknown"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PP ,T XUSB OP PORTSC PP" "Off,On"
|
|
bitfld.long 0x00 5.--8. " PLS ,T XUSB OP PORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detected,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
bitfld.long 0x00 4. " PR ,T XUSB OP PORTSC PR" "Not pending,Pending"
|
|
rbitfld.long 0x00 3. " OCA ,T XUSB OP PORTSC OCA" "False,True"
|
|
textline " "
|
|
eventfld.long 0x00 1. " PED ,T XUSB OP PORTSC PED" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " CCS ,T XUSB OP PORTSC CCS" "No dev,Dev"
|
|
sif (cpu()=="TEGRAX2")
|
|
group.long (0x510+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/SS,OP PORTPMSCSS/SS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
elif (cpu()=="TEGRAX1")
|
|
group.long (0x510+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS,OP PORTPMSCSS"
|
|
bitfld.long 0x00 16. " FLA ,OP PORTPMSCSS FLA" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " U2TIMEOUT ,OP PORTPMSCSS U2TIMEOUT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " U1TIMEOUT ,OP PORTPMSCSS U1TIMEOUT"
|
|
else
|
|
group.long (0x510+0x04)++0x07
|
|
line.long 0x00 "OP_PORTPMSCSS/HS,OP PORTPMSCSS/HS"
|
|
endif
|
|
rgroup.long (0x510+0x0C)++0x03
|
|
line.long 0x00 "OP PORTHLPMC,OP PORTHLPMC"
|
|
bitfld.long 0x00 10.--13. " BESLD ,T XUSB OP PORTHLPMC BESLD" "Initialized,?..."
|
|
hexmask.long.byte 0x00 2.--9. 1. " L1_TIMEOUT ,T XUSB OP PORTHLPMC L1 TIMEOUT"
|
|
bitfld.long 0x00 0.--1. " HIRDM ,T XUSB OP PORTHLPMC HIRDM" "Initialized,?..."
|
|
endif
|
|
textline " "
|
|
width 24.
|
|
group.long 0x600++0x07
|
|
line.long 0x00 "EC_USBLEGSUP,EC USBLEGSUP"
|
|
bitfld.long 0x00 24. " OSSEM ,EC USBLEGSUP OSSEM" "0,1"
|
|
bitfld.long 0x00 16. " BIOSSEM ,T XUSB EC USBLEGSUP BIOSSEM" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NEXT ,EC USBLEGSUP NEXT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAPID ,EC USBLEGSUP CAPID"
|
|
line.long 0x04 "HCI_EC_USBLEGCTLSTS,HCI_EC_USBLEGCTLSTS"
|
|
eventfld.long 0x04 31. " BAR ,EC USBLEGCTLSTS BAR" "Not pending,Pending"
|
|
eventfld.long 0x04 30. " PCIC ,EC USBLEGCTLSTS PCIC" "Not pending,Pending"
|
|
eventfld.long 0x04 29. " OSOC ,EC USBLEGCTLSTS OSOC" "Not pending,Pending"
|
|
rbitfld.long 0x04 20. " HSE ,EC USBLEGCTLSTS HSE" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x04 16. " EVI ,EC USBLEGCTLSTS EVI" "Not pending,Pending"
|
|
bitfld.long 0x04 15. " BAREN ,EC USBLEGCTLSTS BAR enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " PCIEN ,EC USBLEGCTLSTS PCI enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " OSOEN ,EC USBLEGCTLSTS OSO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " HSEEN ,EC USBLEGCTLSTS HSE enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SMIEN ,EC USBLEGCTLSTS SMI enable" "Disabled,Enabled"
|
|
rgroup.long 0x610++0x23
|
|
line.long 0x00 "EC_SUPPROT_USB3_0,EC SUPPROT USB3 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAJORREV ,EC SUPPROT USB3 0 MAJORREV"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MINORREV ,EC SUPPROT USB3 0 MINORREV"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NEXT ,EC SUPPROT USB3 0 NEXT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAPID ,EC SUPPROT USB3 0 CAPID"
|
|
line.long 0x04 "EC_SUPPROT_USB3_1,EC SUPPROT USB3 1"
|
|
line.long 0x08 "EC_SUPPROT_USB3_2,EC SUPPROT USB3 2"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PORTCNT ,EC SUPPROT USB3 2 PORTCNT"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PORTOFS ,EC SUPPROT USB3 2 PORTOFS"
|
|
line.long 0x0C "EC_SUPPROT_USB3_3,EC SUPPROT USB3 3"
|
|
line.long 0x10 "EC_SUPPROT_USB2_0,EC SUPPROT USB2 0"
|
|
hexmask.long.byte 0x10 24.--31. 1. " MAJORREV ,EC SUPPROT USB2 0 MAJORREV"
|
|
hexmask.long.byte 0x10 16.--23. 1. " MINORREV ,EC SUPPROT USB2 0 MINORREV"
|
|
hexmask.long.byte 0x10 8.--15. 1. " XNEXT ,EC SUPPROT USB2 0 NEXT"
|
|
hexmask.long.byte 0x10 0.--7. 1. " CAPID ,EC SUPPROT USB2 0 CAPID"
|
|
line.long 0x14 "EC_SUPPROT_USB2_1,EC SUPPROT USB2 1"
|
|
line.long 0x18 "EC_SUPPROT_USB2_2,EC SUPPROT USB2 2"
|
|
bitfld.long 0x18 25.--27. " MHD ,EC SUPPROT USB2 2 MHD" "MHD,?..."
|
|
bitfld.long 0x18 20. " BLC ,EC_SUPPROT_USB2_2_BLC" "False,True"
|
|
bitfld.long 0x18 19. " HLC ,EC_SUPPROT_USB2_2_HLC" "False,True"
|
|
bitfld.long 0x18 18. " IHI ,EC_SUPPROT_USB2_2_IHI" "True,False"
|
|
textline " "
|
|
bitfld.long 0x18 17. " HSO ,EC_SUPPROT_USB2_2_HSO" "True,False"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PORTCNT ,EC SUPPROT USB2 2 PORTCNT"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PORTOFS ,EC SUPPROT USB2 2 PORTOFS"
|
|
line.long 0x1C "EC_SUPPROT_USB2_3,EC SUPPROT USB2 3"
|
|
line.long 0x20 "EC_DBCAP_DCID,EC_DBCAP_DCID"
|
|
bitfld.long 0x20 16.--20. " DCERSTM ,EC_DBCAP_DCID_DCERSTM" ",DCERSTM_VALUE,?..."
|
|
hexmask.long.byte 0x20 8.--15. 1. " NEXT ,EC DBCAP DCID NEXT"
|
|
hexmask.long.byte 0x20 0.--7. 1. " CAPID ,EC DBCAP DCID CAPID"
|
|
wgroup.long 0x634++0x03
|
|
line.long 0x00 "EC_DBCAP_DCDB,EC DBCAP DCDB"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DBTARGET ,EC DBCAP DCDB DBTARGET"
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "EC_DBCAP_DCERSTSZ,EC DBCAP DCERSTSZ"
|
|
hexmask.long.word 0x00 0.--15. 1. " ERSTSZ ,EC DBCAP DCERSTSZ ERSTSZ"
|
|
textline " "
|
|
width 26.
|
|
group.long 0x640++0x13
|
|
line.long 0x00 "EC_DBCAP_DCERSTBALO,EC DBCAP DCERSTBALO"
|
|
hexmask.long 0x00 4.--31. 1. " ADDRLO ,EC DBCAP DCERSTBALO"
|
|
line.long 0x04 "EC_DBCAP_DCERSTBAHI,EC DBCAP DCERSTBAHI"
|
|
line.long 0x08 "EC_DBCAP_DCERDPLO,EC DBCAP DCERDPLO"
|
|
hexmask.long 0x08 4.--31. 1. " ADDRLO ,EC DBCAP DCERDPLO ADDRLO"
|
|
bitfld.long 0x08 0.--2. " DESI ,EC DBCAP DCERDPLO DESI" "Initialized,?..."
|
|
line.long 0x0C "EC_DBCAP_DCERDPHI,EC DBCAP DCERDPHI ADDRHI"
|
|
line.long 0x10 "EC_DBCAP_DCCTRL,EC DBCAP DCCTRL"
|
|
bitfld.long 0x10 31. " DCE ,EC DBCAP DCCTRL DCE" "Disabled,Enabled"
|
|
hexmask.long.byte 0x10 24.--30. 1. " DEVADR ,EC DBCAP DCCTRL DEVADR"
|
|
hexmask.long.byte 0x10 16.--23. 1. " MAXBURST ,EC DBCAP DCCTRL MAXBURST"
|
|
eventfld.long 0x10 4. " DRC ,EC DBCAP DCCTRL DRC" "Initialized,Clear"
|
|
textline " "
|
|
bitfld.long 0x10 3. " HIT ,EC DBCAP DCCTRL HIT" "False,True"
|
|
bitfld.long 0x10 2. " HOT ,EC DBCAP DCCTRL HOT" "False,True"
|
|
bitfld.long 0x10 1. " LSE ,EC DBCAP DCCTRL LSE" "Disabled,Enabled"
|
|
rbitfld.long 0x10 0. " DCR ,EC DBCAP DCCTRL DCR" "Stop,Run"
|
|
rgroup.long 0x654++0x03
|
|
line.long 0x00 "EC_DBCAP_DCST,EC DBCAP DCST"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DPN ,EC DBCAP DCST DPN"
|
|
bitfld.long 0x00 0. " ER ,EC DBCAP DCST ER" "Empty,Not empty"
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "EC_DBCAP_DCPORTSC,EC DBCAP DCPORTSC"
|
|
eventfld.long 0x00 23. " CEC ,EC DBCAP DCPORTSC CEC" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " PLC ,EC DBCAP DCPORTSC PLC" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " PRC ,EC DBCAP DCPORTSC PRC" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " CSC ,EC DBCAP DCPORTSC CSC" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 10.--13. " PS ,EC DBCAP DCPORTSC PS" "Undefined,,,,SS,?..."
|
|
rbitfld.long 0x00 5.--8. " PLS ,EC DBCAP DCPORTSC PLS" "U0,U1,U2,U3,Disabled,Rx detect,Inactive,Polling,Recovery,Hot reset,Compliance,Loopback,,,,Resumed"
|
|
rbitfld.long 0x00 4. " PR ,EC DBCAP DCPORTSC PR" "No reset,Reset"
|
|
bitfld.long 0x00 1. " PED ,HCI EC DBCAP DCPORTSC PED" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " CCS ,EC DBCAP DCPORTSC CCS" "No CON,CON"
|
|
group.long 0x660++0x0F
|
|
line.long 0x00 "EC_DBCAP_DCECPLO,EC DBCAP DCECPLO"
|
|
hexmask.long 0x00 4.--31. 1. " ADDRLO ,EC DBCAP DCECPLO ADDRLO"
|
|
line.long 0x04 "EC_DBCAP_DCECPHI,EC DBCAP DCECPHI ADDRHI"
|
|
line.long 0x08 "EC_DBCAP_INFO0,EC DBCAP INFO0"
|
|
hexmask.long.word 0x08 16.--31. 1. " VENDORID ,EC DBCAP INFO0 VENDORID"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PROTOCOL ,EC DBCAP INFO0 PROTOCOL"
|
|
line.long 0x0C "EC_DBCAP_INFO1,EC_DBCAP_INFO1"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DEV_REV ,EC DBCAP INFO1 DEV REV"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PRODUCTID ,EC DBCAP INFO1 PRODUCTID"
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "RT_MFINDEX,RT MFINDEX"
|
|
hexmask.long.word 0x00 0.--13. 1. " MFINDEX ,RT MFINDEX MFINDEX"
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "RT_IMAN,RT IMAN"
|
|
bitfld.long 0x00 1. " IE ,RT IMAN IE" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " IP ,RT IMAN IP" "Not pending,Pending"
|
|
group.long 0x824++0x07
|
|
line.long 0x00 "RT_IMOD,RT IMOD"
|
|
hexmask.long.word 0x00 16.--31. 1. " IMODC ,RT IMOD IMODC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IMODI ,RT IMOD IMODI"
|
|
line.long 0x04 "RT_ERSTSZ,RT ERSTSZ"
|
|
hexmask.long.word 0x04 0.--15. 1. " SZ ,RT ERSTSZ SZ"
|
|
group.long 0x830++0x0F
|
|
line.long 0x00 "RT_ERSTBA0,RT ERSTBA0"
|
|
hexmask.long 0x00 4.--31. 1. " ERSTBLO ,RT ERSTBA0 ERSTBLO"
|
|
line.long 0x04 "RT_ERSTBA1,RT ERSTBA1"
|
|
line.long 0x08 "RT_ERDP0,RT ERDP0"
|
|
hexmask.long 0x08 4.--31. 1. " DQPTRLO ,RT ERDP0 DQPTRLO"
|
|
bitfld.long 0x08 0.--2. " DESI ,RT ERDP0 DESI" "Initialized,?..."
|
|
line.long 0x0C "RT_ERDP1,RT ERDP1"
|
|
wgroup.long 0xC00++0x03
|
|
line.long 0x00 "DB,DB"
|
|
button "BGR" "d (0xC00)--(0xFFC) /long"
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
width 25.
|
|
tree "XUSB CSB Registers"
|
|
group.long 0x101A00++0x03
|
|
line.long 0x00 "MEMPOOL_ILOAD_ATTR_0,L2IMEMOP Static Configuration Register"
|
|
bitfld.long 0x00 31. " TC ,TC" "0,1"
|
|
bitfld.long 0x00 30. " NS ,NS" "0,1"
|
|
bitfld.long 0x00 29. " RO ,RO" "0,1"
|
|
textline " "
|
|
sif (cpu()=="TEGRAX1"||cpu()=="TEGRAX2")
|
|
bitfld.long 0x00 28. " RDPASSPW ,RDPASSPW" "0,1"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x00 8.--19. 1. " SIZE ,SIZE"
|
|
rgroup.long 0x101A04++0x03
|
|
line.long 0x00 "MEMPOOL_ILOAD_BASE_LO_0,L2IMEMOP Static Configuration Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SRC_ADDR ,SRC_ADDR"
|
|
group.long 0x101A08++0x03
|
|
line.long 0x00 "MEMPOOL_ILOAD_BASE_HI_0,L2IMEMOP Static Configuration Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SRC_ADDR ,SRC_ADDR"
|
|
group.long 0x101A10++0x07
|
|
line.long 0x00 "MEMPOOL_L2IMEMOP_SIZE_0,MEMPOOL L2IMEMOP SIZE 0 - Operational Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SRC_COUNT ,SRC_COUNT"
|
|
hexmask.long.word 0x00 8.--19. 1. " SRC_OFFSET ,SRC_OFFSET"
|
|
line.long 0x04 "MEMPOOL_L2IMEMOP_TRIG_0,L2IMEMOP Operational Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " ACTION ,ACTION"
|
|
hexmask.long.word 0x04 8.--17. 1. " DEST_INDEX ,DEST_INDEX"
|
|
group.long 0x10181C++0x03
|
|
line.long 0x00 "MEMPOOL_APMAP_0,Aperture Programming Register"
|
|
bitfld.long 0x00 31. " BOOTPATH ,BOOTPATH" "0,1"
|
|
bitfld.long 0x00 24. " XREQ_READ ,XREQ_READ" "0,1"
|
|
bitfld.long 0x00 8.--9. " XMAP ,XMAP" "A,B,C,?..."
|
|
bitfld.long 0x00 0.--2. " FDDMA ,FDDMA" "A,B,C,D,E,?..."
|
|
tree.end
|
|
width 14.
|
|
tree "XUSB Falcon Register"
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "CPUCTL_0,FALCON CPUCTL 0"
|
|
rbitfld.long 0x00 5. " STOPPED ,Indicates whether the CPU is currently in the stopped state" "Not stopped,Stopped"
|
|
rbitfld.long 0x00 4. " HALTED ,Indicates whether the CPU is currently in the halted state" "Not halted,Halted"
|
|
bitfld.long 0x00 3. " HRESET ,Apply a hard reset" "No reset,Reset"
|
|
bitfld.long 0x00 2. " SRESET ,Apply a soft reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STARTCPU ,Request to start CPU execution while in a HALTED state" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " IINVAL ,Mark all blocks in IMEM except block 0 as INVALID" "No effect,Invalidate"
|
|
line.long 0x04 "BOOTVEC_0,FALCON BOOTVEC 0"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DMACTL_0,FALCON DMACTL 0"
|
|
sif (cpu()!="TEGRAX1"&&cpu()!="TEGRAX2")
|
|
rbitfld.long 0x00 7. " SECURE_STAT ,SECURE STAT" "0,1"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 3.--6. " DMAQ_NUM ,Valid request number at the DMA request queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 2. " IMEM_SCRUBBING ,IMEM scrubbing state" "Done,Pending"
|
|
rbitfld.long 0x00 1. " DMEM_SCRUBBING ,DMEM scrubbing state" "Done,Pending"
|
|
sif (cpu()=="TEGRAX1"||cpu()=="TEGRAX2")
|
|
textline " "
|
|
bitfld.long 0x00 0. " REQUIRE_CTX ,Valid context must be loaded before any DMA request can be serviced" "False,True"
|
|
else
|
|
textline " "
|
|
rbitfld.long 0x00 0. " REQUIRE_CTX ,Valid context must be loaded before any DMA request can be serviced" "False,True"
|
|
endif
|
|
group.long 0x154++0x07
|
|
line.long 0x00 "IMFILLRNG1_0,IMFILLRNG1 Indicates Tag Values For The Low And High End Of The PC Range To Be auto-filled"
|
|
hexmask.long.word 0x00 16.--31. 1. " TAG_HI ,TAG HI"
|
|
hexmask.long.word 0x00 0.--15. 1. " TAG_LO ,TAG LO"
|
|
line.long 0x04 "IMFILLCTL_0,FALCON IMFILLCTL 0"
|
|
hexmask.long.byte 0x04 0.--7. 1. " NBLOCKS ,NBLOCKS"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree "Audio HUB"
|
|
tree "APBIF2"
|
|
base ad:0x70300200
|
|
width 22.
|
|
tree.open "CHANNEL4"
|
|
group.long 0x0++0x07
|
|
line.long 0x00 "CTRL_0,Apbif2 Channel Control Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Enable TX channel to AUDIO" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_ENABLE ,Enable RX channel to AUDIO" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " LOOPBACK ,RX CIF is directly hooked up to the TX CIF (Debug mode)" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TX_THRESHOLD ,Trigger threshold level"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " RX_THRESHOLD ,Trigger threshold level"
|
|
bitfld.long 0x00 6. " TX_PACK_EN ,Enable packed data" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " TX_PACK ,Tx pack" "No pack,,Pack8_4,Pack16"
|
|
bitfld.long 0x00 2. " RX_PACK_EN ,Enable packed data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " RX_PACK ,Rx pack" "No pack,,Pack8_4,Pack16"
|
|
line.long 0x04 "CLEAR_0,Apbif2 Channel Clear Register"
|
|
bitfld.long 0x04 31. " TX_SOFT_RESET ,Tx soft reset" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " RX_SOFT_RESET ,Rx soft reset" "Disabled,Enabled"
|
|
rgroup.long (0x0+0x08)++0x03
|
|
line.long 0x00 "STATUS_0,Apbif2 Channel Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TX_FREE_COUNT ,Number of free slots in the TX FIFO"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_FREE_COUNT ,Number of free slots in the RX FIFO"
|
|
bitfld.long 0x00 1. " TX_TRIG ,TX FIFO threshold" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RX_TRIG ,RX FIFO threshold" "Disabled,Enabled"
|
|
group.long (0x0+0x0C)++0x0F
|
|
line.long 0x00 "TXFIFO_0,Apbif2 Channel Tx FIFO Register"
|
|
line.long 0x04 "RXFIFO_0,APBIF2 Channel RX FIFO Register"
|
|
line.long 0x08 "AUDIOCIF_TX4_CTRL_0,APBIF2 Audio CIF TX Control Register"
|
|
bitfld.long 0x08 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x08 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x08 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x08 6.--7. " EXPAND ,Expand" "Zero,One,Lfsr,?..."
|
|
bitfld.long 0x08 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,Avg,?..."
|
|
bitfld.long 0x08 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " DIRECTION ,Direction" "Txcif,Rxcif"
|
|
bitfld.long 0x08 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x08 0. " MONO_CONY ,Mono cony" "Zero,copy"
|
|
line.long 0x0C "AUDIOCIF_RX4_CTRL_0,APBIF2 Audio CIF RX Control Register"
|
|
bitfld.long 0x0c 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0c 20.--23. " AUDIO_CHANNELS ,AUdio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x0c 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x0c 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x0c 6.--7. " EXPAND ,Expand" "Zero,One,Lfsr,?..."
|
|
bitfld.long 0x0c 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,Avg,?..."
|
|
bitfld.long 0x0c 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0c 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x0c 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x0c 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
tree.end
|
|
tree.open "CHANNEL5"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "CTRL_0,Apbif2 Channel Control Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Enable TX channel to AUDIO" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_ENABLE ,Enable RX channel to AUDIO" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " LOOPBACK ,RX CIF is directly hooked up to the TX CIF (Debug mode)" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TX_THRESHOLD ,Trigger threshold level"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " RX_THRESHOLD ,Trigger threshold level"
|
|
bitfld.long 0x00 6. " TX_PACK_EN ,Enable packed data" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " TX_PACK ,Tx pack" "No pack,,Pack8_4,Pack16"
|
|
bitfld.long 0x00 2. " RX_PACK_EN ,Enable packed data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " RX_PACK ,Rx pack" "No pack,,Pack8_4,Pack16"
|
|
line.long 0x04 "CLEAR_0,Apbif2 Channel Clear Register"
|
|
bitfld.long 0x04 31. " TX_SOFT_RESET ,Tx soft reset" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " RX_SOFT_RESET ,Rx soft reset" "Disabled,Enabled"
|
|
rgroup.long (0x20+0x08)++0x03
|
|
line.long 0x00 "STATUS_0,Apbif2 Channel Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TX_FREE_COUNT ,Number of free slots in the TX FIFO"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_FREE_COUNT ,Number of free slots in the RX FIFO"
|
|
bitfld.long 0x00 1. " TX_TRIG ,TX FIFO threshold" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RX_TRIG ,RX FIFO threshold" "Disabled,Enabled"
|
|
group.long (0x20+0x0C)++0x0F
|
|
line.long 0x00 "TXFIFO_0,Apbif2 Channel Tx FIFO Register"
|
|
line.long 0x04 "RXFIFO_0,APBIF2 Channel RX FIFO Register"
|
|
line.long 0x08 "AUDIOCIF_TX5_CTRL_0,APBIF2 Audio CIF TX Control Register"
|
|
bitfld.long 0x08 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x08 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x08 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x08 6.--7. " EXPAND ,Expand" "Zero,One,Lfsr,?..."
|
|
bitfld.long 0x08 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,Avg,?..."
|
|
bitfld.long 0x08 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " DIRECTION ,Direction" "Txcif,Rxcif"
|
|
bitfld.long 0x08 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x08 0. " MONO_CONY ,Mono cony" "Zero,copy"
|
|
line.long 0x0C "AUDIOCIF_RX5_CTRL_0,APBIF2 Audio CIF RX Control Register"
|
|
bitfld.long 0x0c 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0c 20.--23. " AUDIO_CHANNELS ,AUdio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x0c 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x0c 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x0c 6.--7. " EXPAND ,Expand" "Zero,One,Lfsr,?..."
|
|
bitfld.long 0x0c 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,Avg,?..."
|
|
bitfld.long 0x0c 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0c 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x0c 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x0c 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
tree.end
|
|
tree.open "CHANNEL6"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "CTRL_0,Apbif2 Channel Control Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Enable TX channel to AUDIO" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_ENABLE ,Enable RX channel to AUDIO" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " LOOPBACK ,RX CIF is directly hooked up to the TX CIF (Debug mode)" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TX_THRESHOLD ,Trigger threshold level"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " RX_THRESHOLD ,Trigger threshold level"
|
|
bitfld.long 0x00 6. " TX_PACK_EN ,Enable packed data" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " TX_PACK ,Tx pack" "No pack,,Pack8_4,Pack16"
|
|
bitfld.long 0x00 2. " RX_PACK_EN ,Enable packed data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " RX_PACK ,Rx pack" "No pack,,Pack8_4,Pack16"
|
|
line.long 0x04 "CLEAR_0,Apbif2 Channel Clear Register"
|
|
bitfld.long 0x04 31. " TX_SOFT_RESET ,Tx soft reset" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " RX_SOFT_RESET ,Rx soft reset" "Disabled,Enabled"
|
|
rgroup.long (0x40+0x08)++0x03
|
|
line.long 0x00 "STATUS_0,Apbif2 Channel Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TX_FREE_COUNT ,Number of free slots in the TX FIFO"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_FREE_COUNT ,Number of free slots in the RX FIFO"
|
|
bitfld.long 0x00 1. " TX_TRIG ,TX FIFO threshold" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RX_TRIG ,RX FIFO threshold" "Disabled,Enabled"
|
|
group.long (0x40+0x0C)++0x0F
|
|
line.long 0x00 "TXFIFO_0,Apbif2 Channel Tx FIFO Register"
|
|
line.long 0x04 "RXFIFO_0,APBIF2 Channel RX FIFO Register"
|
|
line.long 0x08 "AUDIOCIF_TX6_CTRL_0,APBIF2 Audio CIF TX Control Register"
|
|
bitfld.long 0x08 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x08 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x08 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x08 6.--7. " EXPAND ,Expand" "Zero,One,Lfsr,?..."
|
|
bitfld.long 0x08 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,Avg,?..."
|
|
bitfld.long 0x08 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " DIRECTION ,Direction" "Txcif,Rxcif"
|
|
bitfld.long 0x08 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x08 0. " MONO_CONY ,Mono cony" "Zero,copy"
|
|
line.long 0x0C "AUDIOCIF_RX6_CTRL_0,APBIF2 Audio CIF RX Control Register"
|
|
bitfld.long 0x0c 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0c 20.--23. " AUDIO_CHANNELS ,AUdio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x0c 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x0c 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x0c 6.--7. " EXPAND ,Expand" "Zero,One,Lfsr,?..."
|
|
bitfld.long 0x0c 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,Avg,?..."
|
|
bitfld.long 0x0c 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0c 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x0c 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x0c 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
tree.end
|
|
tree.open "CHANNEL7"
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "CTRL_0,Apbif2 Channel Control Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Enable TX channel to AUDIO" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_ENABLE ,Enable RX channel to AUDIO" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " LOOPBACK ,RX CIF is directly hooked up to the TX CIF (Debug mode)" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TX_THRESHOLD ,Trigger threshold level"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " RX_THRESHOLD ,Trigger threshold level"
|
|
bitfld.long 0x00 6. " TX_PACK_EN ,Enable packed data" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " TX_PACK ,Tx pack" "No pack,,Pack8_4,Pack16"
|
|
bitfld.long 0x00 2. " RX_PACK_EN ,Enable packed data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " RX_PACK ,Rx pack" "No pack,,Pack8_4,Pack16"
|
|
line.long 0x04 "CLEAR_0,Apbif2 Channel Clear Register"
|
|
bitfld.long 0x04 31. " TX_SOFT_RESET ,Tx soft reset" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " RX_SOFT_RESET ,Rx soft reset" "Disabled,Enabled"
|
|
rgroup.long (0x60+0x08)++0x03
|
|
line.long 0x00 "STATUS_0,Apbif2 Channel Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TX_FREE_COUNT ,Number of free slots in the TX FIFO"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_FREE_COUNT ,Number of free slots in the RX FIFO"
|
|
bitfld.long 0x00 1. " TX_TRIG ,TX FIFO threshold" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RX_TRIG ,RX FIFO threshold" "Disabled,Enabled"
|
|
group.long (0x60+0x0C)++0x0F
|
|
line.long 0x00 "TXFIFO_0,Apbif2 Channel Tx FIFO Register"
|
|
line.long 0x04 "RXFIFO_0,APBIF2 Channel RX FIFO Register"
|
|
line.long 0x08 "AUDIOCIF_TX7_CTRL_0,APBIF2 Audio CIF TX Control Register"
|
|
bitfld.long 0x08 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x08 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x08 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x08 6.--7. " EXPAND ,Expand" "Zero,One,Lfsr,?..."
|
|
bitfld.long 0x08 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,Avg,?..."
|
|
bitfld.long 0x08 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " DIRECTION ,Direction" "Txcif,Rxcif"
|
|
bitfld.long 0x08 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x08 0. " MONO_CONY ,Mono cony" "Zero,copy"
|
|
line.long 0x0C "AUDIOCIF_RX7_CTRL_0,APBIF2 Audio CIF RX Control Register"
|
|
bitfld.long 0x0c 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0c 20.--23. " AUDIO_CHANNELS ,AUdio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x0c 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x0c 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x0c 6.--7. " EXPAND ,Expand" "Zero,One,Lfsr,?..."
|
|
bitfld.long 0x0c 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,Avg,?..."
|
|
bitfld.long 0x0c 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0c 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x0c 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x0c 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
tree.end
|
|
tree.open "CHANNEL8"
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CTRL_0,Apbif2 Channel Control Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Enable TX channel to AUDIO" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_ENABLE ,Enable RX channel to AUDIO" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " LOOPBACK ,RX CIF is directly hooked up to the TX CIF (Debug mode)" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TX_THRESHOLD ,Trigger threshold level"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " RX_THRESHOLD ,Trigger threshold level"
|
|
bitfld.long 0x00 6. " TX_PACK_EN ,Enable packed data" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " TX_PACK ,Tx pack" "No pack,,Pack8_4,Pack16"
|
|
bitfld.long 0x00 2. " RX_PACK_EN ,Enable packed data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " RX_PACK ,Rx pack" "No pack,,Pack8_4,Pack16"
|
|
line.long 0x04 "CLEAR_0,Apbif2 Channel Clear Register"
|
|
bitfld.long 0x04 31. " TX_SOFT_RESET ,Tx soft reset" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " RX_SOFT_RESET ,Rx soft reset" "Disabled,Enabled"
|
|
rgroup.long (0x80+0x08)++0x03
|
|
line.long 0x00 "STATUS_0,Apbif2 Channel Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TX_FREE_COUNT ,Number of free slots in the TX FIFO"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_FREE_COUNT ,Number of free slots in the RX FIFO"
|
|
bitfld.long 0x00 1. " TX_TRIG ,TX FIFO threshold" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RX_TRIG ,RX FIFO threshold" "Disabled,Enabled"
|
|
group.long (0x80+0x0C)++0x0F
|
|
line.long 0x00 "TXFIFO_0,Apbif2 Channel Tx FIFO Register"
|
|
line.long 0x04 "RXFIFO_0,APBIF2 Channel RX FIFO Register"
|
|
line.long 0x08 "AUDIOCIF_TX8_CTRL_0,APBIF2 Audio CIF TX Control Register"
|
|
bitfld.long 0x08 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x08 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x08 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x08 6.--7. " EXPAND ,Expand" "Zero,One,Lfsr,?..."
|
|
bitfld.long 0x08 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,Avg,?..."
|
|
bitfld.long 0x08 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " DIRECTION ,Direction" "Txcif,Rxcif"
|
|
bitfld.long 0x08 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x08 0. " MONO_CONY ,Mono cony" "Zero,copy"
|
|
line.long 0x0C "AUDIOCIF_RX8_CTRL_0,APBIF2 Audio CIF RX Control Register"
|
|
bitfld.long 0x0c 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0c 20.--23. " AUDIO_CHANNELS ,AUdio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x0c 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x0c 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x0c 6.--7. " EXPAND ,Expand" "Zero,One,Lfsr,?..."
|
|
bitfld.long 0x0c 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,Avg,?..."
|
|
bitfld.long 0x0c 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0c 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x0c 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x0c 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
tree.end
|
|
tree.open "CHANNEL9"
|
|
group.long 0xA0++0x07
|
|
line.long 0x00 "CTRL_0,Apbif2 Channel Control Register"
|
|
bitfld.long 0x00 31. " TX_ENABLE ,Enable TX channel to AUDIO" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RX_ENABLE ,Enable RX channel to AUDIO" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " LOOPBACK ,RX CIF is directly hooked up to the TX CIF (Debug mode)" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TX_THRESHOLD ,Trigger threshold level"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " RX_THRESHOLD ,Trigger threshold level"
|
|
bitfld.long 0x00 6. " TX_PACK_EN ,Enable packed data" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " TX_PACK ,Tx pack" "No pack,,Pack8_4,Pack16"
|
|
bitfld.long 0x00 2. " RX_PACK_EN ,Enable packed data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " RX_PACK ,Rx pack" "No pack,,Pack8_4,Pack16"
|
|
line.long 0x04 "CLEAR_0,Apbif2 Channel Clear Register"
|
|
bitfld.long 0x04 31. " TX_SOFT_RESET ,Tx soft reset" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " RX_SOFT_RESET ,Rx soft reset" "Disabled,Enabled"
|
|
rgroup.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "STATUS_0,Apbif2 Channel Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TX_FREE_COUNT ,Number of free slots in the TX FIFO"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_FREE_COUNT ,Number of free slots in the RX FIFO"
|
|
bitfld.long 0x00 1. " TX_TRIG ,TX FIFO threshold" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RX_TRIG ,RX FIFO threshold" "Disabled,Enabled"
|
|
group.long (0xA0+0x0C)++0x0F
|
|
line.long 0x00 "TXFIFO_0,Apbif2 Channel Tx FIFO Register"
|
|
line.long 0x04 "RXFIFO_0,APBIF2 Channel RX FIFO Register"
|
|
line.long 0x08 "AUDIOCIF_TX9_CTRL_0,APBIF2 Audio CIF TX Control Register"
|
|
bitfld.long 0x08 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x08 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x08 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x08 6.--7. " EXPAND ,Expand" "Zero,One,Lfsr,?..."
|
|
bitfld.long 0x08 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,Avg,?..."
|
|
bitfld.long 0x08 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " DIRECTION ,Direction" "Txcif,Rxcif"
|
|
bitfld.long 0x08 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x08 0. " MONO_CONY ,Mono cony" "Zero,copy"
|
|
line.long 0x0C "AUDIOCIF_RX9_CTRL_0,APBIF2 Audio CIF RX Control Register"
|
|
bitfld.long 0x0c 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0c 20.--23. " AUDIO_CHANNELS ,AUdio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x0c 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x0c 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x0c 6.--7. " EXPAND ,Expand" "Zero,One,Lfsr,?..."
|
|
bitfld.long 0x0c 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,Avg,?..."
|
|
bitfld.long 0x0c 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x0c 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x0c 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x0c 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
tree.end
|
|
width 33.
|
|
textline " "
|
|
rgroup.long 0xC0++0x13
|
|
line.long 0x00 "AFC_LIVE_TX_FIFO_EMPTY_STATUS_0,Apbif2_Afc_Live_Tx_FIFO_Empty_Status_0"
|
|
bitfld.long 0x00 5. " AFC5_TX_FIFO_EMPTY ,AFC5 Tx FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 4. " AFC4_TX_FIFO_EMPTY ,AFC4 Tx FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 3. " AFC3_TX_FIFO_EMPTY ,AFC3 Tx FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AFC2_TX_FIFO_EMPTY ,AFC2 Tx FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 1. " AFC1_TX_FIFO_EMPTY ,AFC1 Tx FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 0. " AFC0_TX_FIFO_EMPTY ,AFC0 Tx FIFO empty" "Not empty,Empty"
|
|
line.long 0x04 "AFC_LIVE_TX_FIFO_FULL_STATUS_0,APBIF2_Afc_Live_Tx_FIFO_Full_Status_0"
|
|
bitfld.long 0x04 5. " AFC5_TX_FIFO_FULL ,AFC5 Tx FIFO full" "Not full,Full"
|
|
bitfld.long 0x04 4. " AFC4_TX_FIFO_FULL ,AFC4 Tx FIFO full" "Not full,Full"
|
|
bitfld.long 0x04 3. " AFC3_TX_FIFO_FULL ,AFC3 Tx FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x04 2. " AFC2_TX_FIFO_FULL ,AFC2 Tx FIFO full" "Not full,Full"
|
|
bitfld.long 0x04 1. " AFC1_TX_FIFO_FULL ,AFC1 tx FIFO full" "Not full,Full"
|
|
bitfld.long 0x04 0. " AFC0_TX_FIFO_FULL ,AFC0 Tx FIFO full" "Not full,Full"
|
|
line.long 0x08 "AFC_LIVE_RX_FIFO_EMPTY_STATUS_0,APBIF2_Afc_Live_Rx_FIFO_Empty_Status_0"
|
|
bitfld.long 0x08 5. " AFC5_RX_FIFO_EMPTY ,AFC5 Rx FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x08 4. " AFC4_RX_FIFO_EMPTY ,AFC4 Rx FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x08 3. " AFC3_RX_FIFO_EMPTY ,AFC3 Rx FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x08 2. " AFC2_RX_FIFO_EMPTY ,AFC2 Rx FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x08 1. " AFC1_RX_FIFO_EMPTY ,AFC1 Rx FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x08 0. " AFC0_RX_FIFO_EMPTY ,AFC0 Rx FIFO empty" "Not empty,Empty"
|
|
line.long 0x0C "AFC_LIVE_RX_FIFO_FULL_STATUS_0,APBIF2_Afc_Live_Rx_FIFO_Full_Status_0"
|
|
bitfld.long 0x0C 5. " AFC5_RX_FIFO_FULL ,AFC5 Rx Fifo full" "Not full,Full"
|
|
bitfld.long 0x0C 4. " AFC4_RX_FIFO_FULL ,AFC4 Rx Fifo full" "Not full,Full"
|
|
bitfld.long 0x0C 3. " AFC3_RX_FIFO_FULL ,AFC3 rx Fifo full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " AFC2_RX_FIFO_FULL ,AFC2 rx Fifo full" "Not full,Full"
|
|
bitfld.long 0x0C 1. " AFC1_RX_FIFO_FULL ,AFC1 rx Fifo full" "Not full,Full"
|
|
bitfld.long 0x0C 0. " AFC0_RX_FIFO_FULL ,AFC0 rx Fifo full" "Not full,Full"
|
|
line.long 0x10 "AFC_LIVE_TX_ENABLED_STATUS_0,Apbif2_Afc_Live_Tx_Enabled_Status_0"
|
|
bitfld.long 0x10 5. " AFC5_TX_ENABLED ,AFC5 Tx enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " AFC4_TX_ENABLED ,AFC4 Tx enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 3. " AFC3_TX_ENABLED ,AFC3 Tx enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " AFC2_TX_ENABLED ,AFC2 Tx enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " AFC1_TX_ENABLED ,AFC1 Tx enabled" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " AFC0_TX_ENABLED ,AFC0 Tx enabled" "Disabled,Enabled"
|
|
group.long 0xD4++0x0F
|
|
line.long 0x00 "AFC_TX_DONE_INT_MASK_0,APBIF2_AFC_TX_DONE_INT_MASK_0"
|
|
bitfld.long 0x00 5. " AFC5_TX_DONE ,AFC5 Tx done interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 4. " AFC4_TX_DONE ,AFC4 Tx done interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 3. " AFC3_TX_DONE ,AFC3 Tx done interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AFC2_TX_DONE ,AFC2 Tx done interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 1. " AFC1_TX_DONE ,AFC1 Tx done interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x00 0. " AFC0_TX_DONE ,AFC0 Tx done interrupt mask" "Masked,Unmasked"
|
|
line.long 0x04 "AFC_FLOW_CTL_INT_MASK_0,Apbif2_Afc_Flow_Ctl_Int_Mask_0"
|
|
bitfld.long 0x04 5. " AFC5_FLOW_CTL ,AFC5 flow ctl interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " AFC4_FLOW_CTL ,AFC4 flow ctl interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 3. " AFC3_FLOW_CTL ,AFC3 flow ctl interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " AFC2_FLOW_CTL ,AFC2 flow ctl interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " AFC1_FLOW_CTL ,AFC1 flow ctl interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 0. " AFC0_FLOW_CTL ,AFC0 flow ctl interrupt mask" "Masked,Unmasked"
|
|
line.long 0x08 "AFC_TX_DONE_INT_STATUS_0,Apbif2_Afc_Tx_Done_Int_Status_0"
|
|
bitfld.long 0x08 5. " AFC5_TX_DONE ,AFC5 Tx done" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " AFC5_TX_DONE ,AFC5 Tx done" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " AFC5_TX_DONE ,AFC5 Tx done" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " AFC5_TX_DONE ,AFC5 Tx done" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " AFC5_TX_DONE ,AFC5 Tx done" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " AFC5_TX_DONE ,AFC5 Tx done" "Disabled,Enabled"
|
|
line.long 0x0C "AFC_FLOW_CTL_INT_STATUS_0,Apbif2_Afc_Flow_Ctl_Int_Status_0"
|
|
bitfld.long 0x0C 5. " AFC5_FLOW_CTL ,AFC5 flow control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " AFC4_FLOW_CTL ,AFC4 flow control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " AFC3_FLOW_CTL ,AFC3 flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " AFC2_FLOW_CTL ,AFC2 flow control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " AFC1_FLOW_CTL ,AFC1 flow control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " AFC0_FLOW_CTL ,AFC0 flow control" "Disabled,Enabled"
|
|
rgroup.long 0xE4++0x07
|
|
line.long 0x00 "AFC_TX_DONE_INT_SOURCE_0,Apbif2_Afc_Tx_Done_Int_Source_0"
|
|
bitfld.long 0x00 5. " AFC5_TX_DONE ,AFC5 Tx done" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " AFC4_TX_DONE ,AFC4 Tx done" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " AFC3_TX_DONE ,AFC3 Tx done" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AFC2_TX_DONE ,AFC2 Tx done" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AFC1_TX_DONE ,AFC1 Tx done" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AFC0_TX_DONE ,AFC0 Tx done" "Disabled,Enabled"
|
|
line.long 0x04 "AFC_FLOW_CTL_INT_SOURCE_0,Apbif2_Afc_Flow_Ctl_Int_Source_0"
|
|
bitfld.long 0x04 5. " AFC5_FLOW_CTL ,AFC5 flow control" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " AFC4_FLOW_CTL ,AFC5 flow control" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " AFC3_FLOW_CTL ,AFC5 flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " AFC2_FLOW_CTL ,AFC5 flow control" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " AFC1_FLOW_CTL ,AFC5 flow control" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " AFC0_FLOW_CTL ,AFC5 flow control" "Disabled,Enabled"
|
|
group.long 0xEC++0x07
|
|
line.long 0x00 "AFC_TX_DONE_INT_SET_0,Apbif2_Afc_Tx_Done_Int_Set_0"
|
|
bitfld.long 0x00 5. " AFC5_TX_DONE ,AFC5 Tx done" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " AFC4_TX_DONE ,AFC4 Tx done" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " AFC3_TX_DONE ,AFC3 Tx done" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AFC2_TX_DONE ,AFC2 Tx done" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AFC1_TX_DONE ,AFC1 Tx done" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AFC0_TX_DONE ,AFC0 Tx done" "Disabled,Enabled"
|
|
line.long 0x04 "AFC_FLOW_CTL_INT_SET_0,Apbif2_Afc_Flow_Ctl_Int_Set_0"
|
|
bitfld.long 0x04 5. " AFC5_FLOW_CTL ,AFC5 flow ctl" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " AFC4_FLOW_CTL ,AFC4 flow ctl" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " AFC3_FLOW_CTL ,AFC3 flow ctl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " AFC2_FLOW_CTL ,AFC2 flow ctl" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " AFC1_FLOW_CTL ,AFC1 flow ctl" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " AFC0_FLOW_CTL ,AFC0 flow ctl" "Disabled,Enabled"
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "MISC_LIVE_STATUS0_0,Apbif2_Misc_Live_Status0_0"
|
|
bitfld.long 0x00 5. " AFC5_AUDIO_CLKEN ,AFC5 audio clken" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " AFC4_AUDIO_CLKEN ,AFC4 audio clken" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " AFC3_AUDIO_CLKEN ,AFC3 audio clken" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AFC2_AUDIO_CLKEN ,AFC2 audio clken" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AFC1_AUDIO_CLKEN ,AFC1 audio clken" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AFC0_AUDIO_CLKEN ,AFC0 audio clken" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DAM"
|
|
tree "DAM0"
|
|
base ad:0x70302000
|
|
width 28.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL_0,Control Register 0"
|
|
bitfld.long 0x00 31. " SOFT_RESET ,Soft reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " FSOUT ,Output data sample rate" "FS8,FS16,FS44,FS48,FS11,FS22,FS24,FS32,FS88,FS96,FS176,FS192,..."
|
|
bitfld.long 0x00 3. " STEREO_MIXING_EN ,Enables stereo mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " STEREO_SRC_EN ,Enables stereo SRC" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CG_EN ,Enables DAM second level clock gating" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the DAM" "Disabled,Enabled"
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "AUDIOCIF_OUT_CTRL_0,DAM Output"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,Avg,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CH0x10_CTRL_0,DAM Channel 0x10 Control 0 Register"
|
|
bitfld.long 0x00 16.--19. " FILT_STAGES ,Number of filter stages" "1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x00 8.--11. " FSIN ,Input sample rate" "Fs8,Fs16,Fs44,Fs48,Fs11,Fs22,Fs24,Fs32,Fs88,Fs96,Fs176,Fs192,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DATA_SYNC ,Bit says the mixer should wait for data in other channels" ",Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15"
|
|
bitfld.long 0x00 0. " Enable ,Enable" "Disabled,Enabled"
|
|
group.long (0x10+0x0C)++0x03
|
|
line.long 0x00 "AUDIOCIF_CH0x10_CTRL_0,DAM AUDIOCIF Channel 0x10 Control 0 Register"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " Client_Channels ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Clients bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " DIRECTION ,Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CH0x20_CTRL_0,DAM Channel 0x20 Control 0 Register"
|
|
bitfld.long 0x00 16.--19. " FILT_STAGES ,Number of filter stages" "1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x00 8.--11. " FSIN ,Input sample rate" "Fs8,Fs16,Fs44,Fs48,Fs11,Fs22,Fs24,Fs32,Fs88,Fs96,Fs176,Fs192,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DATA_SYNC ,Bit says the mixer should wait for data in other channels" ",Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15"
|
|
bitfld.long 0x00 0. " Enable ,Enable" "Disabled,Enabled"
|
|
group.long (0x20+0x0C)++0x03
|
|
line.long 0x00 "AUDIOCIF_CH0x20_CTRL_0,DAM AUDIOCIF Channel 0x20 Control 0 Register"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " Client_Channels ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Clients bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " DIRECTION ,Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DAM1"
|
|
base ad:0x70302200
|
|
width 28.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL_0,Control Register 0"
|
|
bitfld.long 0x00 31. " SOFT_RESET ,Soft reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " FSOUT ,Output data sample rate" "FS8,FS16,FS44,FS48,FS11,FS22,FS24,FS32,FS88,FS96,FS176,FS192,..."
|
|
bitfld.long 0x00 3. " STEREO_MIXING_EN ,Enables stereo mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " STEREO_SRC_EN ,Enables stereo SRC" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CG_EN ,Enables DAM second level clock gating" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the DAM" "Disabled,Enabled"
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "AUDIOCIF_OUT_CTRL_0,DAM Output"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,Avg,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CH0x10_CTRL_0,DAM Channel 0x10 Control 0 Register"
|
|
bitfld.long 0x00 16.--19. " FILT_STAGES ,Number of filter stages" "1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x00 8.--11. " FSIN ,Input sample rate" "Fs8,Fs16,Fs44,Fs48,Fs11,Fs22,Fs24,Fs32,Fs88,Fs96,Fs176,Fs192,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DATA_SYNC ,Bit says the mixer should wait for data in other channels" ",Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15"
|
|
bitfld.long 0x00 0. " Enable ,Enable" "Disabled,Enabled"
|
|
group.long (0x10+0x0C)++0x03
|
|
line.long 0x00 "AUDIOCIF_CH0x10_CTRL_0,DAM AUDIOCIF Channel 0x10 Control 0 Register"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " Client_Channels ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Clients bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " DIRECTION ,Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CH0x20_CTRL_0,DAM Channel 0x20 Control 0 Register"
|
|
bitfld.long 0x00 16.--19. " FILT_STAGES ,Number of filter stages" "1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x00 8.--11. " FSIN ,Input sample rate" "Fs8,Fs16,Fs44,Fs48,Fs11,Fs22,Fs24,Fs32,Fs88,Fs96,Fs176,Fs192,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DATA_SYNC ,Bit says the mixer should wait for data in other channels" ",Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15"
|
|
bitfld.long 0x00 0. " Enable ,Enable" "Disabled,Enabled"
|
|
group.long (0x20+0x0C)++0x03
|
|
line.long 0x00 "AUDIOCIF_CH0x20_CTRL_0,DAM AUDIOCIF Channel 0x20 Control 0 Register"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " Client_Channels ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Clients bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " DIRECTION ,Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DAM2"
|
|
base ad:0x70302400
|
|
width 28.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL_0,Control Register 0"
|
|
bitfld.long 0x00 31. " SOFT_RESET ,Soft reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--7. " FSOUT ,Output data sample rate" "FS8,FS16,FS44,FS48,FS11,FS22,FS24,FS32,FS88,FS96,FS176,FS192,..."
|
|
bitfld.long 0x00 3. " STEREO_MIXING_EN ,Enables stereo mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " STEREO_SRC_EN ,Enables stereo SRC" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CG_EN ,Enables DAM second level clock gating" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the DAM" "Disabled,Enabled"
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "AUDIOCIF_OUT_CTRL_0,DAM Output"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,Avg,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CH0x10_CTRL_0,DAM Channel 0x10 Control 0 Register"
|
|
bitfld.long 0x00 16.--19. " FILT_STAGES ,Number of filter stages" "1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x00 8.--11. " FSIN ,Input sample rate" "Fs8,Fs16,Fs44,Fs48,Fs11,Fs22,Fs24,Fs32,Fs88,Fs96,Fs176,Fs192,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DATA_SYNC ,Bit says the mixer should wait for data in other channels" ",Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15"
|
|
bitfld.long 0x00 0. " Enable ,Enable" "Disabled,Enabled"
|
|
group.long (0x10+0x0C)++0x03
|
|
line.long 0x00 "AUDIOCIF_CH0x10_CTRL_0,DAM AUDIOCIF Channel 0x10 Control 0 Register"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " Client_Channels ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Clients bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " DIRECTION ,Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CH0x20_CTRL_0,DAM Channel 0x20 Control 0 Register"
|
|
bitfld.long 0x00 16.--19. " FILT_STAGES ,Number of filter stages" "1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x00 8.--11. " FSIN ,Input sample rate" "Fs8,Fs16,Fs44,Fs48,Fs11,Fs22,Fs24,Fs32,Fs88,Fs96,Fs176,Fs192,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DATA_SYNC ,Bit says the mixer should wait for data in other channels" ",Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15"
|
|
bitfld.long 0x00 0. " Enable ,Enable" "Disabled,Enabled"
|
|
group.long (0x20+0x0C)++0x03
|
|
line.long 0x00 "AUDIOCIF_CH0x20_CTRL_0,DAM AUDIOCIF Channel 0x20 Control 0 Register"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " Client_Channels ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Clients bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " DIRECTION ,Direction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "I2S"
|
|
tree "I2S0"
|
|
base ad:0x70301000
|
|
width 28.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "I2S_CTRL_0,I2S Control Register"
|
|
bitfld.long 0x00 31. " XFER_EN_TX ,Enable I2S Transmit channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " XFER_EN_RX ,Enable I2S Receive channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CG_EN ,Enable I2S second level clock gating" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOFT_RESET ,Configuration registers are not reset by soft reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TX_FLOWCTL_EN ,Enable flow control in Transmit channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PIPE_MACRO_EN ,Enable pipe macro stage" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " FRAME_FORMAT ,Frame format" "LRCK,FSYNC,..."
|
|
bitfld.long 0x00 10. " MASTER ,Controller Master/Slave mode selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LRCK_POLARITY ,Left/right control polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LPBK ,Tx->Rx loop back enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " BIT_CODE ,Sample compression/decompression" "Linear,uLAW,ALAW,"
|
|
bitfld.long 0x00 0.--2. " BIT_SIZE ,Bit size" ",8,12,16,20,24,28,32"
|
|
line.long 0x04 "I2S_TIMING_0,I2S Timing Register"
|
|
bitfld.long 0x04 12. " NON_SYM_EN ,Enable non-symmetry mode" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 0.--10. 1. " CHANNEL_BIT_CNT ,Channel bit cnt"
|
|
line.long 0x08 "I2S_OFFSET_0,I2S_Offset_0"
|
|
hexmask.long.word 0x08 16.--26. 1. " RX_DATA_OFFSET ,RX Data offset to fsync"
|
|
hexmask.long.word 0x08 0.--10. 1. " TX_DATA_OFFSET ,TX Data offset to fsync"
|
|
line.long 0x0C "I2S_CH_CTRL_0,I2s Ch Ctrl 0"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " FSYNC_WIDTH ,Fsync width in terms of bit clocks"
|
|
bitfld.long 0x0C 12.--13. " HIGHZ_CTRL ,HighZ control" "Nohighz,Highz,Highz on half,"
|
|
bitfld.long 0x0C 10. " RX_BIT_ORDER ,Configure to appear Most/Least Significant Bit first on sdata out" "MSB,LSB"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " TX_BIT_ORDER ,Configure to appear Most/Least Significant Bit first on sdata out" "MSB,LSB"
|
|
bitfld.long 0x0C 8. " EDGE_CTRL ,Edge (Positive/Negative) on which Data is driven" "POS,NEG"
|
|
bitfld.long 0x0C 4.--6. " RX_MASK_BITS ,RX mask bits - Used for PCM mode" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--2. " TX_MASK_BITS ,TX mask bits - Used for PCM mode" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "I2S_SLOT_CTRL_0,I2S_Slot_Ctrl_0"
|
|
bitfld.long 0x10 0.--3. " TOTAL_SLOTS ,Number of slots per fsync" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x14 "I2S_AUDIOCIF_I2STX_CTRL_0,CIF RX Port for I2S TX Path"
|
|
bitfld.long 0x14 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x14 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x14 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
textline " "
|
|
bitfld.long 0x14 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x14 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x14 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
textline " "
|
|
bitfld.long 0x14 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x14 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
rbitfld.long 0x14 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
textline " "
|
|
bitfld.long 0x14 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x14 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
line.long 0x18 "I2S_AUDIOCIF_I2SRX_CTRL_0,CIF TX Port for I2S RX Path"
|
|
bitfld.long 0x18 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x18 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x18 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
textline " "
|
|
bitfld.long 0x18 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x18 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x18 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
textline " "
|
|
bitfld.long 0x18 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x18 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
rbitfld.long 0x18 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
textline " "
|
|
bitfld.long 0x18 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x18 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
line.long 0x1C "I2S_FLOWCTL_0,Flowctrl"
|
|
bitfld.long 0x1C 31. " FILTER ,Use linear or quadratic filter" "Linear,Quad"
|
|
bitfld.long 0x1C 30. " DUMMY_WR_EN ,Insert a dummy frame when enabled" "Disabled,Enabled"
|
|
bitfld.long 0x1C 16.--17. " START_THRESHOLD_MSB ,Threshold value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x1C 14.--15. " HIGH_THRESHOLD_MSB ,Threshold value" "0,1,2,3"
|
|
bitfld.long 0x1C 12.--13. " LOW_THRESHOLD_MSB ,Threshold value" "0,1,2,3"
|
|
bitfld.long 0x1C 8.--11. " START_THRESHOLD ,Threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 4.--7. " HIGH_THRESHOLD ,High-threshold" "1,2,3,4,5,6,7,8,9,10,11,12,13,1,15,16"
|
|
bitfld.long 0x1C 0.--3. " LOW_THRESHOLD , Low threshold" "1,2,3,4,5,6,7,8,9,10,11,12,13,1,15,16"
|
|
line.long 0x20 "I2S_TX_STEP_0,I2s Tx step"
|
|
hexmask.long.word 0x20 0.--15. 1. " STEP_SIZE ,Compensation value for the clock difference between input and output"
|
|
line.long 0x24 "I2S_FLOW_STATUS_0,Flow Controller Monitor/Counter"
|
|
bitfld.long 0x24 31. " FLOW_UNDERFLOW ,FIFO depth is less than threshold" "Normal,Underflow"
|
|
bitfld.long 0x24 30. " FLOW_OVERFLOW ,FIFO depth is greater than threshold" "Normal,Overflow"
|
|
bitfld.long 0x24 4. " MONITOR_INT_EN ,Enable monitor interrupt to APBIF" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 3. " COUNTER_CLR ,Clear counter" "No effect,Clear"
|
|
bitfld.long 0x24 2. " MONITOR_CLR ,Clear monitor" "No effect,Clear"
|
|
bitfld.long 0x24 1. " COUNTER_EN ,Enable counter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 0. " MONITOR_EN ,Enable monitor" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x0B
|
|
line.long 0x00 "I2S_FLOW_TOTAL_0,I2S_Flow_Total_0"
|
|
line.long 0x04 "I2S_FLOW_OVER_0,I2S_Flow_Over_0"
|
|
line.long 0x08 "I2S_FLOW_UNDER_0,I2S_Flow_Under_0"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "I2S_SLOT_CTRL2_0,I2S_Slot_Ctrl2_0"
|
|
hexmask.long.word 0x00 16.--31. 1. " RX_SLOT_ENABLES ,Rx slot enables - used fot TDM mode"
|
|
hexmask.long.word 0x00 0.--15. 1. " TX_SLOT_ENABLES ,Tx Slot enables - used fot TDM mode"
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2S1"
|
|
base ad:0x70301100
|
|
width 28.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "I2S_CTRL_0,I2S Control Register"
|
|
bitfld.long 0x00 31. " XFER_EN_TX ,Enable I2S Transmit channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " XFER_EN_RX ,Enable I2S Receive channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CG_EN ,Enable I2S second level clock gating" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOFT_RESET ,Configuration registers are not reset by soft reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TX_FLOWCTL_EN ,Enable flow control in Transmit channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PIPE_MACRO_EN ,Enable pipe macro stage" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " FRAME_FORMAT ,Frame format" "LRCK,FSYNC,..."
|
|
bitfld.long 0x00 10. " MASTER ,Controller Master/Slave mode selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LRCK_POLARITY ,Left/right control polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LPBK ,Tx->Rx loop back enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " BIT_CODE ,Sample compression/decompression" "Linear,uLAW,ALAW,"
|
|
bitfld.long 0x00 0.--2. " BIT_SIZE ,Bit size" ",8,12,16,20,24,28,32"
|
|
line.long 0x04 "I2S_TIMING_0,I2S Timing Register"
|
|
bitfld.long 0x04 12. " NON_SYM_EN ,Enable non-symmetry mode" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 0.--10. 1. " CHANNEL_BIT_CNT ,Channel bit cnt"
|
|
line.long 0x08 "I2S_OFFSET_0,I2S_Offset_0"
|
|
hexmask.long.word 0x08 16.--26. 1. " RX_DATA_OFFSET ,RX Data offset to fsync"
|
|
hexmask.long.word 0x08 0.--10. 1. " TX_DATA_OFFSET ,TX Data offset to fsync"
|
|
line.long 0x0C "I2S_CH_CTRL_0,I2s Ch Ctrl 0"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " FSYNC_WIDTH ,Fsync width in terms of bit clocks"
|
|
bitfld.long 0x0C 12.--13. " HIGHZ_CTRL ,HighZ control" "Nohighz,Highz,Highz on half,"
|
|
bitfld.long 0x0C 10. " RX_BIT_ORDER ,Configure to appear Most/Least Significant Bit first on sdata out" "MSB,LSB"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " TX_BIT_ORDER ,Configure to appear Most/Least Significant Bit first on sdata out" "MSB,LSB"
|
|
bitfld.long 0x0C 8. " EDGE_CTRL ,Edge (Positive/Negative) on which Data is driven" "POS,NEG"
|
|
bitfld.long 0x0C 4.--6. " RX_MASK_BITS ,RX mask bits - Used for PCM mode" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--2. " TX_MASK_BITS ,TX mask bits - Used for PCM mode" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "I2S_SLOT_CTRL_0,I2S_Slot_Ctrl_0"
|
|
bitfld.long 0x10 0.--3. " TOTAL_SLOTS ,Number of slots per fsync" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x14 "I2S_AUDIOCIF_I2STX_CTRL_0,CIF RX Port for I2S TX Path"
|
|
bitfld.long 0x14 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x14 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x14 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
textline " "
|
|
bitfld.long 0x14 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x14 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x14 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
textline " "
|
|
bitfld.long 0x14 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x14 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
rbitfld.long 0x14 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
textline " "
|
|
bitfld.long 0x14 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x14 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
line.long 0x18 "I2S_AUDIOCIF_I2SRX_CTRL_0,CIF TX Port for I2S RX Path"
|
|
bitfld.long 0x18 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x18 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x18 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
textline " "
|
|
bitfld.long 0x18 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x18 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x18 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
textline " "
|
|
bitfld.long 0x18 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x18 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
rbitfld.long 0x18 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
textline " "
|
|
bitfld.long 0x18 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x18 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
line.long 0x1C "I2S_FLOWCTL_0,Flowctrl"
|
|
bitfld.long 0x1C 31. " FILTER ,Use linear or quadratic filter" "Linear,Quad"
|
|
bitfld.long 0x1C 30. " DUMMY_WR_EN ,Insert a dummy frame when enabled" "Disabled,Enabled"
|
|
bitfld.long 0x1C 16.--17. " START_THRESHOLD_MSB ,Threshold value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x1C 14.--15. " HIGH_THRESHOLD_MSB ,Threshold value" "0,1,2,3"
|
|
bitfld.long 0x1C 12.--13. " LOW_THRESHOLD_MSB ,Threshold value" "0,1,2,3"
|
|
bitfld.long 0x1C 8.--11. " START_THRESHOLD ,Threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 4.--7. " HIGH_THRESHOLD ,High-threshold" "1,2,3,4,5,6,7,8,9,10,11,12,13,1,15,16"
|
|
bitfld.long 0x1C 0.--3. " LOW_THRESHOLD , Low threshold" "1,2,3,4,5,6,7,8,9,10,11,12,13,1,15,16"
|
|
line.long 0x20 "I2S_TX_STEP_0,I2s Tx step"
|
|
hexmask.long.word 0x20 0.--15. 1. " STEP_SIZE ,Compensation value for the clock difference between input and output"
|
|
line.long 0x24 "I2S_FLOW_STATUS_0,Flow Controller Monitor/Counter"
|
|
bitfld.long 0x24 31. " FLOW_UNDERFLOW ,FIFO depth is less than threshold" "Normal,Underflow"
|
|
bitfld.long 0x24 30. " FLOW_OVERFLOW ,FIFO depth is greater than threshold" "Normal,Overflow"
|
|
bitfld.long 0x24 4. " MONITOR_INT_EN ,Enable monitor interrupt to APBIF" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 3. " COUNTER_CLR ,Clear counter" "No effect,Clear"
|
|
bitfld.long 0x24 2. " MONITOR_CLR ,Clear monitor" "No effect,Clear"
|
|
bitfld.long 0x24 1. " COUNTER_EN ,Enable counter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 0. " MONITOR_EN ,Enable monitor" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x0B
|
|
line.long 0x00 "I2S_FLOW_TOTAL_0,I2S_Flow_Total_0"
|
|
line.long 0x04 "I2S_FLOW_OVER_0,I2S_Flow_Over_0"
|
|
line.long 0x08 "I2S_FLOW_UNDER_0,I2S_Flow_Under_0"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "I2S_SLOT_CTRL2_0,I2S_Slot_Ctrl2_0"
|
|
hexmask.long.word 0x00 16.--31. 1. " RX_SLOT_ENABLES ,Rx slot enables - used fot TDM mode"
|
|
hexmask.long.word 0x00 0.--15. 1. " TX_SLOT_ENABLES ,Tx Slot enables - used fot TDM mode"
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2S2"
|
|
base ad:0x70301200
|
|
width 28.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "I2S_CTRL_0,I2S Control Register"
|
|
bitfld.long 0x00 31. " XFER_EN_TX ,Enable I2S Transmit channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " XFER_EN_RX ,Enable I2S Receive channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CG_EN ,Enable I2S second level clock gating" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOFT_RESET ,Configuration registers are not reset by soft reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TX_FLOWCTL_EN ,Enable flow control in Transmit channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PIPE_MACRO_EN ,Enable pipe macro stage" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " FRAME_FORMAT ,Frame format" "LRCK,FSYNC,..."
|
|
bitfld.long 0x00 10. " MASTER ,Controller Master/Slave mode selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LRCK_POLARITY ,Left/right control polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LPBK ,Tx->Rx loop back enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " BIT_CODE ,Sample compression/decompression" "Linear,uLAW,ALAW,"
|
|
bitfld.long 0x00 0.--2. " BIT_SIZE ,Bit size" ",8,12,16,20,24,28,32"
|
|
line.long 0x04 "I2S_TIMING_0,I2S Timing Register"
|
|
bitfld.long 0x04 12. " NON_SYM_EN ,Enable non-symmetry mode" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 0.--10. 1. " CHANNEL_BIT_CNT ,Channel bit cnt"
|
|
line.long 0x08 "I2S_OFFSET_0,I2S_Offset_0"
|
|
hexmask.long.word 0x08 16.--26. 1. " RX_DATA_OFFSET ,RX Data offset to fsync"
|
|
hexmask.long.word 0x08 0.--10. 1. " TX_DATA_OFFSET ,TX Data offset to fsync"
|
|
line.long 0x0C "I2S_CH_CTRL_0,I2s Ch Ctrl 0"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " FSYNC_WIDTH ,Fsync width in terms of bit clocks"
|
|
bitfld.long 0x0C 12.--13. " HIGHZ_CTRL ,HighZ control" "Nohighz,Highz,Highz on half,"
|
|
bitfld.long 0x0C 10. " RX_BIT_ORDER ,Configure to appear Most/Least Significant Bit first on sdata out" "MSB,LSB"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " TX_BIT_ORDER ,Configure to appear Most/Least Significant Bit first on sdata out" "MSB,LSB"
|
|
bitfld.long 0x0C 8. " EDGE_CTRL ,Edge (Positive/Negative) on which Data is driven" "POS,NEG"
|
|
bitfld.long 0x0C 4.--6. " RX_MASK_BITS ,RX mask bits - Used for PCM mode" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--2. " TX_MASK_BITS ,TX mask bits - Used for PCM mode" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "I2S_SLOT_CTRL_0,I2S_Slot_Ctrl_0"
|
|
bitfld.long 0x10 0.--3. " TOTAL_SLOTS ,Number of slots per fsync" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x14 "I2S_AUDIOCIF_I2STX_CTRL_0,CIF RX Port for I2S TX Path"
|
|
bitfld.long 0x14 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x14 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x14 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
textline " "
|
|
bitfld.long 0x14 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x14 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x14 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
textline " "
|
|
bitfld.long 0x14 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x14 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
rbitfld.long 0x14 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
textline " "
|
|
bitfld.long 0x14 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x14 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
line.long 0x18 "I2S_AUDIOCIF_I2SRX_CTRL_0,CIF TX Port for I2S RX Path"
|
|
bitfld.long 0x18 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x18 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x18 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
textline " "
|
|
bitfld.long 0x18 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x18 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x18 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
textline " "
|
|
bitfld.long 0x18 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x18 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
rbitfld.long 0x18 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
textline " "
|
|
bitfld.long 0x18 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x18 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
line.long 0x1C "I2S_FLOWCTL_0,Flowctrl"
|
|
bitfld.long 0x1C 31. " FILTER ,Use linear or quadratic filter" "Linear,Quad"
|
|
bitfld.long 0x1C 30. " DUMMY_WR_EN ,Insert a dummy frame when enabled" "Disabled,Enabled"
|
|
bitfld.long 0x1C 16.--17. " START_THRESHOLD_MSB ,Threshold value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x1C 14.--15. " HIGH_THRESHOLD_MSB ,Threshold value" "0,1,2,3"
|
|
bitfld.long 0x1C 12.--13. " LOW_THRESHOLD_MSB ,Threshold value" "0,1,2,3"
|
|
bitfld.long 0x1C 8.--11. " START_THRESHOLD ,Threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 4.--7. " HIGH_THRESHOLD ,High-threshold" "1,2,3,4,5,6,7,8,9,10,11,12,13,1,15,16"
|
|
bitfld.long 0x1C 0.--3. " LOW_THRESHOLD , Low threshold" "1,2,3,4,5,6,7,8,9,10,11,12,13,1,15,16"
|
|
line.long 0x20 "I2S_TX_STEP_0,I2s Tx step"
|
|
hexmask.long.word 0x20 0.--15. 1. " STEP_SIZE ,Compensation value for the clock difference between input and output"
|
|
line.long 0x24 "I2S_FLOW_STATUS_0,Flow Controller Monitor/Counter"
|
|
bitfld.long 0x24 31. " FLOW_UNDERFLOW ,FIFO depth is less than threshold" "Normal,Underflow"
|
|
bitfld.long 0x24 30. " FLOW_OVERFLOW ,FIFO depth is greater than threshold" "Normal,Overflow"
|
|
bitfld.long 0x24 4. " MONITOR_INT_EN ,Enable monitor interrupt to APBIF" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 3. " COUNTER_CLR ,Clear counter" "No effect,Clear"
|
|
bitfld.long 0x24 2. " MONITOR_CLR ,Clear monitor" "No effect,Clear"
|
|
bitfld.long 0x24 1. " COUNTER_EN ,Enable counter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 0. " MONITOR_EN ,Enable monitor" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x0B
|
|
line.long 0x00 "I2S_FLOW_TOTAL_0,I2S_Flow_Total_0"
|
|
line.long 0x04 "I2S_FLOW_OVER_0,I2S_Flow_Over_0"
|
|
line.long 0x08 "I2S_FLOW_UNDER_0,I2S_Flow_Under_0"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "I2S_SLOT_CTRL2_0,I2S_Slot_Ctrl2_0"
|
|
hexmask.long.word 0x00 16.--31. 1. " RX_SLOT_ENABLES ,Rx slot enables - used fot TDM mode"
|
|
hexmask.long.word 0x00 0.--15. 1. " TX_SLOT_ENABLES ,Tx Slot enables - used fot TDM mode"
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2S3"
|
|
base ad:0x70301300
|
|
width 28.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "I2S_CTRL_0,I2S Control Register"
|
|
bitfld.long 0x00 31. " XFER_EN_TX ,Enable I2S Transmit channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " XFER_EN_RX ,Enable I2S Receive channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CG_EN ,Enable I2S second level clock gating" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOFT_RESET ,Configuration registers are not reset by soft reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TX_FLOWCTL_EN ,Enable flow control in Transmit channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PIPE_MACRO_EN ,Enable pipe macro stage" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " FRAME_FORMAT ,Frame format" "LRCK,FSYNC,..."
|
|
bitfld.long 0x00 10. " MASTER ,Controller Master/Slave mode selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LRCK_POLARITY ,Left/right control polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LPBK ,Tx->Rx loop back enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " BIT_CODE ,Sample compression/decompression" "Linear,uLAW,ALAW,"
|
|
bitfld.long 0x00 0.--2. " BIT_SIZE ,Bit size" ",8,12,16,20,24,28,32"
|
|
line.long 0x04 "I2S_TIMING_0,I2S Timing Register"
|
|
bitfld.long 0x04 12. " NON_SYM_EN ,Enable non-symmetry mode" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 0.--10. 1. " CHANNEL_BIT_CNT ,Channel bit cnt"
|
|
line.long 0x08 "I2S_OFFSET_0,I2S_Offset_0"
|
|
hexmask.long.word 0x08 16.--26. 1. " RX_DATA_OFFSET ,RX Data offset to fsync"
|
|
hexmask.long.word 0x08 0.--10. 1. " TX_DATA_OFFSET ,TX Data offset to fsync"
|
|
line.long 0x0C "I2S_CH_CTRL_0,I2s Ch Ctrl 0"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " FSYNC_WIDTH ,Fsync width in terms of bit clocks"
|
|
bitfld.long 0x0C 12.--13. " HIGHZ_CTRL ,HighZ control" "Nohighz,Highz,Highz on half,"
|
|
bitfld.long 0x0C 10. " RX_BIT_ORDER ,Configure to appear Most/Least Significant Bit first on sdata out" "MSB,LSB"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " TX_BIT_ORDER ,Configure to appear Most/Least Significant Bit first on sdata out" "MSB,LSB"
|
|
bitfld.long 0x0C 8. " EDGE_CTRL ,Edge (Positive/Negative) on which Data is driven" "POS,NEG"
|
|
bitfld.long 0x0C 4.--6. " RX_MASK_BITS ,RX mask bits - Used for PCM mode" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--2. " TX_MASK_BITS ,TX mask bits - Used for PCM mode" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "I2S_SLOT_CTRL_0,I2S_Slot_Ctrl_0"
|
|
bitfld.long 0x10 0.--3. " TOTAL_SLOTS ,Number of slots per fsync" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x14 "I2S_AUDIOCIF_I2STX_CTRL_0,CIF RX Port for I2S TX Path"
|
|
bitfld.long 0x14 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x14 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x14 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
textline " "
|
|
bitfld.long 0x14 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x14 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x14 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
textline " "
|
|
bitfld.long 0x14 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x14 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
rbitfld.long 0x14 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
textline " "
|
|
bitfld.long 0x14 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x14 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
line.long 0x18 "I2S_AUDIOCIF_I2SRX_CTRL_0,CIF TX Port for I2S RX Path"
|
|
bitfld.long 0x18 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x18 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x18 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
textline " "
|
|
bitfld.long 0x18 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x18 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x18 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
textline " "
|
|
bitfld.long 0x18 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x18 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
rbitfld.long 0x18 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
textline " "
|
|
bitfld.long 0x18 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x18 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
line.long 0x1C "I2S_FLOWCTL_0,Flowctrl"
|
|
bitfld.long 0x1C 31. " FILTER ,Use linear or quadratic filter" "Linear,Quad"
|
|
bitfld.long 0x1C 30. " DUMMY_WR_EN ,Insert a dummy frame when enabled" "Disabled,Enabled"
|
|
bitfld.long 0x1C 16.--17. " START_THRESHOLD_MSB ,Threshold value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x1C 14.--15. " HIGH_THRESHOLD_MSB ,Threshold value" "0,1,2,3"
|
|
bitfld.long 0x1C 12.--13. " LOW_THRESHOLD_MSB ,Threshold value" "0,1,2,3"
|
|
bitfld.long 0x1C 8.--11. " START_THRESHOLD ,Threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 4.--7. " HIGH_THRESHOLD ,High-threshold" "1,2,3,4,5,6,7,8,9,10,11,12,13,1,15,16"
|
|
bitfld.long 0x1C 0.--3. " LOW_THRESHOLD , Low threshold" "1,2,3,4,5,6,7,8,9,10,11,12,13,1,15,16"
|
|
line.long 0x20 "I2S_TX_STEP_0,I2s Tx step"
|
|
hexmask.long.word 0x20 0.--15. 1. " STEP_SIZE ,Compensation value for the clock difference between input and output"
|
|
line.long 0x24 "I2S_FLOW_STATUS_0,Flow Controller Monitor/Counter"
|
|
bitfld.long 0x24 31. " FLOW_UNDERFLOW ,FIFO depth is less than threshold" "Normal,Underflow"
|
|
bitfld.long 0x24 30. " FLOW_OVERFLOW ,FIFO depth is greater than threshold" "Normal,Overflow"
|
|
bitfld.long 0x24 4. " MONITOR_INT_EN ,Enable monitor interrupt to APBIF" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 3. " COUNTER_CLR ,Clear counter" "No effect,Clear"
|
|
bitfld.long 0x24 2. " MONITOR_CLR ,Clear monitor" "No effect,Clear"
|
|
bitfld.long 0x24 1. " COUNTER_EN ,Enable counter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 0. " MONITOR_EN ,Enable monitor" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x0B
|
|
line.long 0x00 "I2S_FLOW_TOTAL_0,I2S_Flow_Total_0"
|
|
line.long 0x04 "I2S_FLOW_OVER_0,I2S_Flow_Over_0"
|
|
line.long 0x08 "I2S_FLOW_UNDER_0,I2S_Flow_Under_0"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "I2S_SLOT_CTRL2_0,I2S_Slot_Ctrl2_0"
|
|
hexmask.long.word 0x00 16.--31. 1. " RX_SLOT_ENABLES ,Rx slot enables - used fot TDM mode"
|
|
hexmask.long.word 0x00 0.--15. 1. " TX_SLOT_ENABLES ,Tx Slot enables - used fot TDM mode"
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2S4"
|
|
base ad:0x70301400
|
|
width 28.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "I2S_CTRL_0,I2S Control Register"
|
|
bitfld.long 0x00 31. " XFER_EN_TX ,Enable I2S Transmit channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " XFER_EN_RX ,Enable I2S Receive channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CG_EN ,Enable I2S second level clock gating" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SOFT_RESET ,Configuration registers are not reset by soft reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TX_FLOWCTL_EN ,Enable flow control in Transmit channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PIPE_MACRO_EN ,Enable pipe macro stage" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " FRAME_FORMAT ,Frame format" "LRCK,FSYNC,..."
|
|
bitfld.long 0x00 10. " MASTER ,Controller Master/Slave mode selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LRCK_POLARITY ,Left/right control polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LPBK ,Tx->Rx loop back enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " BIT_CODE ,Sample compression/decompression" "Linear,uLAW,ALAW,"
|
|
bitfld.long 0x00 0.--2. " BIT_SIZE ,Bit size" ",8,12,16,20,24,28,32"
|
|
line.long 0x04 "I2S_TIMING_0,I2S Timing Register"
|
|
bitfld.long 0x04 12. " NON_SYM_EN ,Enable non-symmetry mode" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 0.--10. 1. " CHANNEL_BIT_CNT ,Channel bit cnt"
|
|
line.long 0x08 "I2S_OFFSET_0,I2S_Offset_0"
|
|
hexmask.long.word 0x08 16.--26. 1. " RX_DATA_OFFSET ,RX Data offset to fsync"
|
|
hexmask.long.word 0x08 0.--10. 1. " TX_DATA_OFFSET ,TX Data offset to fsync"
|
|
line.long 0x0C "I2S_CH_CTRL_0,I2s Ch Ctrl 0"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " FSYNC_WIDTH ,Fsync width in terms of bit clocks"
|
|
bitfld.long 0x0C 12.--13. " HIGHZ_CTRL ,HighZ control" "Nohighz,Highz,Highz on half,"
|
|
bitfld.long 0x0C 10. " RX_BIT_ORDER ,Configure to appear Most/Least Significant Bit first on sdata out" "MSB,LSB"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " TX_BIT_ORDER ,Configure to appear Most/Least Significant Bit first on sdata out" "MSB,LSB"
|
|
bitfld.long 0x0C 8. " EDGE_CTRL ,Edge (Positive/Negative) on which Data is driven" "POS,NEG"
|
|
bitfld.long 0x0C 4.--6. " RX_MASK_BITS ,RX mask bits - Used for PCM mode" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--2. " TX_MASK_BITS ,TX mask bits - Used for PCM mode" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "I2S_SLOT_CTRL_0,I2S_Slot_Ctrl_0"
|
|
bitfld.long 0x10 0.--3. " TOTAL_SLOTS ,Number of slots per fsync" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x14 "I2S_AUDIOCIF_I2STX_CTRL_0,CIF RX Port for I2S TX Path"
|
|
bitfld.long 0x14 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x14 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x14 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
textline " "
|
|
bitfld.long 0x14 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x14 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x14 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
textline " "
|
|
bitfld.long 0x14 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x14 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
rbitfld.long 0x14 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
textline " "
|
|
bitfld.long 0x14 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x14 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
line.long 0x18 "I2S_AUDIOCIF_I2SRX_CTRL_0,CIF TX Port for I2S RX Path"
|
|
bitfld.long 0x18 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x18 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x18 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
textline " "
|
|
bitfld.long 0x18 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x18 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x18 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
textline " "
|
|
bitfld.long 0x18 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x18 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
rbitfld.long 0x18 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
textline " "
|
|
bitfld.long 0x18 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x18 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
line.long 0x1C "I2S_FLOWCTL_0,Flowctrl"
|
|
bitfld.long 0x1C 31. " FILTER ,Use linear or quadratic filter" "Linear,Quad"
|
|
bitfld.long 0x1C 30. " DUMMY_WR_EN ,Insert a dummy frame when enabled" "Disabled,Enabled"
|
|
bitfld.long 0x1C 16.--17. " START_THRESHOLD_MSB ,Threshold value" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x1C 14.--15. " HIGH_THRESHOLD_MSB ,Threshold value" "0,1,2,3"
|
|
bitfld.long 0x1C 12.--13. " LOW_THRESHOLD_MSB ,Threshold value" "0,1,2,3"
|
|
bitfld.long 0x1C 8.--11. " START_THRESHOLD ,Threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x1C 4.--7. " HIGH_THRESHOLD ,High-threshold" "1,2,3,4,5,6,7,8,9,10,11,12,13,1,15,16"
|
|
bitfld.long 0x1C 0.--3. " LOW_THRESHOLD , Low threshold" "1,2,3,4,5,6,7,8,9,10,11,12,13,1,15,16"
|
|
line.long 0x20 "I2S_TX_STEP_0,I2s Tx step"
|
|
hexmask.long.word 0x20 0.--15. 1. " STEP_SIZE ,Compensation value for the clock difference between input and output"
|
|
line.long 0x24 "I2S_FLOW_STATUS_0,Flow Controller Monitor/Counter"
|
|
bitfld.long 0x24 31. " FLOW_UNDERFLOW ,FIFO depth is less than threshold" "Normal,Underflow"
|
|
bitfld.long 0x24 30. " FLOW_OVERFLOW ,FIFO depth is greater than threshold" "Normal,Overflow"
|
|
bitfld.long 0x24 4. " MONITOR_INT_EN ,Enable monitor interrupt to APBIF" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 3. " COUNTER_CLR ,Clear counter" "No effect,Clear"
|
|
bitfld.long 0x24 2. " MONITOR_CLR ,Clear monitor" "No effect,Clear"
|
|
bitfld.long 0x24 1. " COUNTER_EN ,Enable counter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 0. " MONITOR_EN ,Enable monitor" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x0B
|
|
line.long 0x00 "I2S_FLOW_TOTAL_0,I2S_Flow_Total_0"
|
|
line.long 0x04 "I2S_FLOW_OVER_0,I2S_Flow_Over_0"
|
|
line.long 0x08 "I2S_FLOW_UNDER_0,I2S_Flow_Under_0"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "I2S_SLOT_CTRL2_0,I2S_Slot_Ctrl2_0"
|
|
hexmask.long.word 0x00 16.--31. 1. " RX_SLOT_ENABLES ,Rx slot enables - used fot TDM mode"
|
|
hexmask.long.word 0x00 0.--15. 1. " TX_SLOT_ENABLES ,Tx Slot enables - used fot TDM mode"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SPDIF"
|
|
base ad:0x70306000
|
|
width 30.
|
|
if (((d.l(ad:0x70306000+0x00))&0x20000000)==0x20000000)||(((d.l(ad:0x70306000+0x00))&0x10000000)==0x10000000)
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "SPDIF_CTRL_0,SPDIF Control Register"
|
|
bitfld.long 0x00 31. " FLOWCTL_EN ,Enable flow control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CAP_LC ,Start capturing from left/right channel" "Right_Ch,Left_Ch"
|
|
bitfld.long 0x00 29. " RX_EN ,SPDIF receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " TX_EN ,SPDIF transmitter enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " TC_EN ,Transmit channel status" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " TU_EN ,Transmit user data" "Disabled,Enabled"
|
|
rbitfld.long 0x00 15. " LBK_EN ,Loopback test mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " PACK ,Pack data mode (Single data/Packeted left or right ch# data into a single word)" "Single,Packeted"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " BIT_MODE ,Bit mode" "16bit,20bit,24bit,Raw"
|
|
bitfld.long 0x00 11. " CG_EN ,Second level clock gating enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SOFT_RESET ,Resets I2s logic including CIFs and flow control" "No reset,Reset"
|
|
else
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "SPDIF_CTRL_0,SPDIF Control Register"
|
|
bitfld.long 0x00 31. " FLOWCTL_EN ,Enable flow control" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CAP_LC ,Start capturing from left/right channel" "Right_Ch,Left_Ch"
|
|
bitfld.long 0x00 29. " RX_EN ,SPDIF receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " TX_EN ,SPDIF transmitter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " TC_EN ,Transmit Channel status" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TU_EN ,Transmit user Data" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " LBK_EN ,Loopback test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PACK ,Pack data mode (Single data/Packeted left or right ch# data into a single word)" "Single,Packeted"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BIT_MODE ,Bit mode" "16bit,20bit,24bit,Raw"
|
|
bitfld.long 0x00 11. " CG_EN ,Second level clock gating" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SOFT_RESET ,Resets I2s logic including CIFs and flow control" "No reset,Reset"
|
|
endif
|
|
textline " "
|
|
group.long 0x04++0x13
|
|
line.long 0x00 "SPDIF_STROBE_CTRL_0,SPDIF Data Strobe Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PERIOD ,Indicates the approximate number of detected SPDIFIN clocks within a biphase period"
|
|
bitfld.long 0x00 15. " STROBE ,SPDIFIN Data Strobe Mode" "Auto,Manual"
|
|
bitfld.long 0x00 8.--12. " DATA_STROBES ,Manual data strobe time within the biphase clock period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--5. " CLOCK_PERIOD ,Manual SPDIFIN biphase clock period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "SPDIF_AUDIOCIF_TXDATA_CTRL_0,SPDIF AUDIOCIF TXDATA Control Register"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,?..."
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,?..."
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " DIRCETION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "SPDIF_AUDIOCIF_RXDATA_CTRL_0,SPDIF AUDIOCIF RXDATA Control Register"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,?..."
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,?..."
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " DIRCETION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SPDIF_AUDIOCIF_TXUSER_CTRL_0,SPDIF AUDIOCIF TXUSER Control Register"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,?..."
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,?..."
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " DIRCETION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SPDIF_AUDIOCIF_RXUSER_CTRL_0,SPDIF AUDIOCIF RXUSER Control Register"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,?..."
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,?..."
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " DIRCETION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
rgroup.long 0x18++0x17
|
|
line.long 0x00 "SPDIF_CH_STA_RX_A_0,SPDIF Channel Status Rx Page Buffer Register A"
|
|
line.long 0x04 "SPDIF_CH_STA_RX_B_0,SPDIF Channel Status Rx Page Buffer Register B"
|
|
line.long 0x08 "SPDIF_CH_STA_RX_C_0,SPDIF Channel Status Rx Page Buffer Register C"
|
|
line.long 0x0C "SPDIF_CH_STA_RX_D_0,SPDIF Channel Status Rx Page Buffer Register D"
|
|
line.long 0x10 "SPDIF_CH_STA_RX_E_0,SPDIF Channel Status Rx Page Buffer Register E"
|
|
line.long 0x14 "SPDIF_CH_STA_RX_F_0,SPDIF Channel Status Rx Page Buffer Register F"
|
|
group.long 0x30++0x17
|
|
line.long 0x00 "SPDIF_CH_STA_TX_A_0,SPDIF Channel Status Tx Page Buffer Register A"
|
|
line.long 0x04 "SPDIF_CH_STA_TX_B_0,SPDIF Channel Status Tx Page Buffer Register B"
|
|
line.long 0x08 "SPDIF_CH_STA_TX_C_0,SPDIF Channel Status Tx Page Buffer Register C"
|
|
line.long 0x0C "SPDIF_CH_STA_TX_D_0,SPDIF Channel Status Tx Page Buffer Register D"
|
|
line.long 0x10 "SPDIF_CH_STA_TX_E_0,SPDIF Channel Status Tx Page Buffer Register E"
|
|
line.long 0x14 "SPDIF_CH_STA_TX_F_0,SPDIF Channel Status Tx Page Buffer Register F"
|
|
group.long 0x70++0x0B
|
|
line.long 0x00 "SPDIF_FLOWCTL_CTRL_0,SPDIF Flowctl Ctrl 0"
|
|
sif cpuis("TEGRAX2")
|
|
rbitfld.long 0x00 31. " FILTER ,Quadric filter" "Linear,Quad"
|
|
elif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 31. " FILTER ,Quadric filter" "Linear,Quad"
|
|
else
|
|
bitfld.long 0x00 31. " FILTER ,Quadric filter" ",Quad"
|
|
endif
|
|
bitfld.long 0x00 30. " DUMMY_WR_EN ,Insert a dummy frame when enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " START_THRESHOLD ,Flow control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 4.--7. " HIGH_THRESHOLD ,High-threshold for HIGH state" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " LOW_THRESHOLD ,Low-threshold for LOW state" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "SPDIF_TX_STEP_0,SPDIF TX Step"
|
|
hexmask.long.word 0x04 0.--15. 1. " STEP_SIZE ,Step size"
|
|
line.long 0x08 "SPDIF_FLOW_STATUS_0,Flow Controller Monitor/Counter"
|
|
bitfld.long 0x08 31. " FLOW_UNDERFLOW ,FIFO depth is less than threshold" "Normal,Under"
|
|
bitfld.long 0x08 30. " FLOW_OVERFLOW ,FIFO depth is greater than threshold" "Normal,Over"
|
|
bitfld.long 0x08 4. " MONITOR_INT_EN ,Enable monitor interrupt to APBIF" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " COUNTER_CLR ,Clear counter" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 2. " MONITOR_CLR ,Clear monitor" "0,1"
|
|
bitfld.long 0x08 1. " COUNTER_EN ,Enable counter" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " MONITOR_EN ,Enable monitor" "Disabled,Enabled"
|
|
rgroup.long 0x7C++0x0B
|
|
line.long 0x00 "SPDIF_FLOW_TOTAL_0,Spdif Flow Total"
|
|
line.long 0x04 "SPDIF_FLOW_OVER_0,Spdif Flow Over"
|
|
line.long 0x08 "SPDIF_FLOW_UNDER_0,Spdif Flow Under"
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
group.long 0xAC++0x07
|
|
line.long 0x00 "SPDIF_INT_STATUS_0_SET/CLR,SPDIF Interrupt Status Register"
|
|
setclrfld.long 0x00 15. 0x08 15. 0x0C 15. " USER_TX_DONE ,User TX done" "False,True"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x0C 14. " USER_RX_DONE ,User RX done" "False,True"
|
|
setclrfld.long 0x00 13. 0x08 13. 0x0C 13. " DATA_TX_DONE ,Data TX done" "False,True"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x08 12. 0x0C 12. " DATA_RX_DONE ,Data RX done" "False,True"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x0C 11. " USER_TXCIF_OVERRUN ,User TXCIF overrun" "False,True"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x0C 10. " DATA_TXCIF_OVERRUN ,Data TXCIF overrun" "False,True"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x08 9. 0x0C 9. " USER_RXCIF_UNDERRUN ,User RXCIF underrun" "False,True"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x0C 8. " DATA_RXCIF_UNDERRUN ,Data RXCIF underrun" "False,True"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x0C 4. " RX_IU ,RX IU" "False,True"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x0C 3. " RX_CHANNEL ,RX channel" "False,True"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x0C 2. " FLOW_CTL_INT ,Flow CTL INT" "False,True"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x0C 1. " BAD_PREAMBLE ,Bad preamble" "False,True"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x08 0. 0x0C 0. " BSYNC ,BSYNC" "False,True"
|
|
line.long 0x04 "SPDIF_INT_MASK_0,SPDIF Interrupt Mask Register"
|
|
bitfld.long 0x04 15. " USER_TX_DONE ,User TX done" "Unmasked,Masked"
|
|
bitfld.long 0x04 14. " USER_RX_DONE ,User RX done" "Unmasked,Masked"
|
|
bitfld.long 0x04 13. " DATA_TX_DONE ,Data TX done" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DATA_RX_DONE ,Data RX done" "Unmasked,Masked"
|
|
bitfld.long 0x04 11. " USER_TXCIF_OVERRUN ,User TXCIF overrun" "Unmasked,Masked"
|
|
bitfld.long 0x04 10. " DATA_TXCIF_OVERRUN ,Data TXCIF overrun" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " USER_RXCIF_UNDERRUN ,User RXCIF underrun" "Unmasked,Masked"
|
|
bitfld.long 0x04 8. " DATA_RXCIF_UNDERRUN ,Data RXCIF underrun" "Unmasked,Masked"
|
|
bitfld.long 0x04 4. " RX_IU ,RX IU" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RX_CHANNEL ,RX channel" "Unmasked,Masked"
|
|
bitfld.long 0x04 2. " FLOW_CTL_INT ,Flow CTL INT" "Unmasked,Masked"
|
|
bitfld.long 0x04 1. " BAD_PREAMBLE ,Bad preamble" "Unmasked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " BSYNC ,BSYNC" "Unmasked,Masked"
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "SPDIF_LIVE_STATUS_0,SPDIF Live Status Register"
|
|
bitfld.long 0x00 24. " TXC_BSY ,TXC BSY" "0,1"
|
|
bitfld.long 0x00 19. " USER_TX_FIFO_FULL ,User TX FIFO full" "False,True"
|
|
bitfld.long 0x00 18. " USER_TX_FIFO_EMPTY ,User TX FIFO empty" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DATA_TX_FIFO_FULL ,Data TX FIFO full" "False,True"
|
|
bitfld.long 0x00 16. " DATA_TX_FIFO_EMPTY ,Data TX FIFO empty" "False,True"
|
|
bitfld.long 0x00 11. " USER_RX_FIFO_FULL ,User RX FIFO full" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 10. " USER_RX_FIFO_EMPTY ,User RX FIFO empty" "False,True"
|
|
bitfld.long 0x00 9. " DATA_RX_FIFO_FULL ,Data RX FIFO full" "False,True"
|
|
bitfld.long 0x00 8. " DATA_RX_FIFO_EMPTY ,Data RX FIFO empty" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USER_TX_ENABLED ,User TX enabled" "False,True"
|
|
bitfld.long 0x00 2. " USER_RX_ENABLED ,User RX enabled" "False,True"
|
|
bitfld.long 0x00 1. " DATA_TX_ENABLED ,Data TX enabled" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA_RX_ENABLED ,Data RX enabled" "False,True"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "AMX"
|
|
tree "AMX0"
|
|
base ad:0x70303000
|
|
width 28.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "AMX_CTRL_0,AMX Control Register"
|
|
bitfld.long 0x00 31. " SOFT_RESET ,Resets AMX logic" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CG_EN ,Second level clock gating enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSTR_CH_NUM ,Designated master channel" "Ch0,Ch1,Ch2,Ch3"
|
|
bitfld.long 0x00 8.--9. " CH_DEP ,Send output" "On_all,On_any,On_master,"
|
|
line.long 0x04 "AMX_OUT_CH_CTRL_0,AMX output channels control"
|
|
bitfld.long 0x04 11. " CH3_FORCE_DISABLE ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " CH2_FORCE_DISABLE ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CH1_FORCE_DISABLE ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CH0_FORCE_DISABLE ,Channel 0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3_EN ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2_EN ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1_EN ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0_EN ,Channel 0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x08 "AMX_IN_BYTE_EN0_0,Byte enables for bytes 0 to 31"
|
|
bitfld.long 0x08 31. " BYTE_EN[31] ,Byte 31 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [30] ,Byte 30 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [29] ,Byte 29 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [28] ,Byte 28 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [27] ,Byte 27 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [26] ,Byte 26 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [25] ,Byte 25 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [24] ,Byte 24 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [23] ,Byte 23 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [22] ,Byte 22 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [21] ,Byte 21 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [20] ,Byte 20 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [19] ,Byte 19 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [18] ,Byte 18 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [17] ,Byte 17 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [16] ,Byte 16 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [15] ,Byte 15 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [14] ,Byte 14 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [13] ,Byte 13 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [12] ,Byte 12 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [11] ,Byte 11 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [10] ,Byte 10 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [9] ,Byte 9 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [8] ,Byte 8 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [7] ,Byte 7 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [6] ,Byte 6 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [5] ,Byte 5 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [4] ,Byte 4 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,Byte 3 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Byte 2 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [1] ,Byte 1 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [0] ,Byte 0 byte enable" "Disabled,Enabled"
|
|
line.long 0x0C "AMX_IN_BYTE_EN1_0,Byte enables for bytes 32 to 63"
|
|
bitfld.long 0x0C 31. " BYTE_EN[63] ,Byte 63 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [62] ,Byte 62 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [61] ,Byte 61 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [60] ,Byte 60 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [59] ,Byte 59 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [58] ,Byte 58 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [57] ,Byte 57 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [56] ,Byte 56 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [55] ,Byte 55 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [54] ,Byte 54 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [53] ,Byte 53 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [52] ,Byte 52 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [51] ,Byte 51 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [50] ,Byte 50 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [49] ,Byte 49 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [48] ,Byte 48 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [47] ,Byte 47 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [46] ,Byte 46 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [45] ,Byte 45 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [44] ,Byte 44 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [43] ,Byte 43 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [42] ,Byte 42 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [41] ,Byte 41 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [40] ,Byte 40 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [39] ,Byte 39 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [38] ,Byte 38 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [37] ,Byte 37 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [36] ,Byte 36 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [35] ,Byte 35 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [34] ,Byte 34 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [33] ,Byte 33 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [32] ,Byte 32 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x10 "AMX_AUDIORAMCTL_AMX_CTRL_0,AMX_AUDIORAMCTL_AMX_CTRL_0"
|
|
rbitfld.long 0x10 31. " READ_BUSY ,Read busy" "Done,Busy"
|
|
bitfld.long 0x10 14. " RW ,Read write access" "Read,Write"
|
|
bitfld.long 0x10 13. " RESET_HW_ADR ,Reset hardware address" "Done,Busy"
|
|
bitfld.long 0x10 12. " HW_ADR_EN ,Hardware address enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " RAM_ADR ,Ram address"
|
|
line.long 0x14 "AMX_AUDIORAMCTL_AMX_DATA_0,AMX_AUDIORAMCTL ADX Data_0"
|
|
line.long 0x18 "AMX_AUDIOCIF_IN_CTRL_0,AMX_AUDIOCIF_IN_CTRL_0"
|
|
bitfld.long 0x18 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x18 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x18 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x18 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x18 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x18 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x18 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x18 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x18 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "AMX_AUDIOCIF_CH0_CTRL_0,AMX_Audiocif_Ch0_Ctrl_0"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,mono conv" "Zero,Copy"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AMX_AUDIOCIF_CH1_CTRL_0,AMX_Audiocif_Ch1_Ctrl_0"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,mono conv" "Zero,Copy"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AMX_AUDIOCIF_CH2_CTRL_0,AMX_Audiocif_Ch2_Ctrl_0"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,mono conv" "Zero,Copy"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "AMX_AUDIOCIF_CH3_CTRL_0,AMX_Audiocif_Ch3_Ctrl_0"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,mono conv" "Zero,Copy"
|
|
width 0x0B
|
|
tree.end
|
|
tree "AMX1"
|
|
base ad:0x70303100
|
|
width 28.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "AMX_CTRL_0,AMX Control Register"
|
|
bitfld.long 0x00 31. " SOFT_RESET ,Resets AMX logic" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CG_EN ,Second level clock gating enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MSTR_CH_NUM ,Designated master channel" "Ch0,Ch1,Ch2,Ch3"
|
|
bitfld.long 0x00 8.--9. " CH_DEP ,Send output" "On_all,On_any,On_master,"
|
|
line.long 0x04 "AMX_OUT_CH_CTRL_0,AMX output channels control"
|
|
bitfld.long 0x04 11. " CH3_FORCE_DISABLE ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " CH2_FORCE_DISABLE ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CH1_FORCE_DISABLE ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CH0_FORCE_DISABLE ,Channel 0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3_EN ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2_EN ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1_EN ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0_EN ,Channel 0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x08 "AMX_IN_BYTE_EN0_0,Byte enables for bytes 0 to 31"
|
|
bitfld.long 0x08 31. " BYTE_EN[31] ,Byte 31 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [30] ,Byte 30 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [29] ,Byte 29 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [28] ,Byte 28 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [27] ,Byte 27 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [26] ,Byte 26 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [25] ,Byte 25 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [24] ,Byte 24 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [23] ,Byte 23 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [22] ,Byte 22 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [21] ,Byte 21 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [20] ,Byte 20 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [19] ,Byte 19 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [18] ,Byte 18 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [17] ,Byte 17 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [16] ,Byte 16 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [15] ,Byte 15 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [14] ,Byte 14 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [13] ,Byte 13 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [12] ,Byte 12 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [11] ,Byte 11 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [10] ,Byte 10 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [9] ,Byte 9 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [8] ,Byte 8 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [7] ,Byte 7 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [6] ,Byte 6 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [5] ,Byte 5 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [4] ,Byte 4 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,Byte 3 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Byte 2 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [1] ,Byte 1 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [0] ,Byte 0 byte enable" "Disabled,Enabled"
|
|
line.long 0x0C "AMX_IN_BYTE_EN1_0,Byte enables for bytes 32 to 63"
|
|
bitfld.long 0x0C 31. " BYTE_EN[63] ,Byte 63 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [62] ,Byte 62 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [61] ,Byte 61 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [60] ,Byte 60 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [59] ,Byte 59 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [58] ,Byte 58 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [57] ,Byte 57 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [56] ,Byte 56 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [55] ,Byte 55 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [54] ,Byte 54 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [53] ,Byte 53 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [52] ,Byte 52 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [51] ,Byte 51 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [50] ,Byte 50 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [49] ,Byte 49 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [48] ,Byte 48 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [47] ,Byte 47 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [46] ,Byte 46 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [45] ,Byte 45 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [44] ,Byte 44 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [43] ,Byte 43 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [42] ,Byte 42 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [41] ,Byte 41 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [40] ,Byte 40 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [39] ,Byte 39 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [38] ,Byte 38 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [37] ,Byte 37 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [36] ,Byte 36 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [35] ,Byte 35 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [34] ,Byte 34 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [33] ,Byte 33 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [32] ,Byte 32 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x10 "AMX_AUDIORAMCTL_AMX_CTRL_0,AMX_AUDIORAMCTL_AMX_CTRL_0"
|
|
rbitfld.long 0x10 31. " READ_BUSY ,Read busy" "Done,Busy"
|
|
bitfld.long 0x10 14. " RW ,Read write access" "Read,Write"
|
|
bitfld.long 0x10 13. " RESET_HW_ADR ,Reset hardware address" "Done,Busy"
|
|
bitfld.long 0x10 12. " HW_ADR_EN ,Hardware address enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " RAM_ADR ,Ram address"
|
|
line.long 0x14 "AMX_AUDIORAMCTL_AMX_DATA_0,AMX_AUDIORAMCTL ADX Data_0"
|
|
line.long 0x18 "AMX_AUDIOCIF_IN_CTRL_0,AMX_AUDIOCIF_IN_CTRL_0"
|
|
bitfld.long 0x18 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x18 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x18 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x18 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x18 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x18 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x18 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x18 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x18 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "AMX_AUDIOCIF_CH0_CTRL_0,AMX_Audiocif_Ch0_Ctrl_0"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,mono conv" "Zero,Copy"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AMX_AUDIOCIF_CH1_CTRL_0,AMX_Audiocif_Ch1_Ctrl_0"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,mono conv" "Zero,Copy"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AMX_AUDIOCIF_CH2_CTRL_0,AMX_Audiocif_Ch2_Ctrl_0"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,mono conv" "Zero,Copy"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "AMX_AUDIOCIF_CH3_CTRL_0,AMX_Audiocif_Ch3_Ctrl_0"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,mono conv" "Zero,Copy"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "ADX"
|
|
tree "ADX0"
|
|
base ad:0x70303800
|
|
width 28.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "ADX_CTRL_0,ADX Control Register"
|
|
bitfld.long 0x00 31. " SOFT_RESET ,Resets ADX logic" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CG_EN ,Second-level clock gating enable" "Disabled,Enabled"
|
|
line.long 0x04 "ADX_OUT_CH_CTRL_0,ADX output channels control"
|
|
bitfld.long 0x04 11. " CH3_FORCE_DISABLE ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " CH2_FORCE_DISABLE ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CH1_FORCE_DISABLE ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CH0_FORCE_DISABLE ,Channel 0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3_EN ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2_EN ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1_EN ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0_EN ,Channel 0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x08 "ADX_IN_BYTE_EN0_0,Byte enables for bytes 0 to 31"
|
|
bitfld.long 0x08 31. " BYTE_EN[31] ,Byte 31 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [30] ,Byte 30 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [29] ,Byte 29 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [28] ,Byte 28 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " [27] ,Byte 27 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [26] ,Byte 26 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [25] ,Byte 25 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [24] ,Byte 24 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [23] ,Byte 23 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [22] ,Byte 22 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [21] ,Byte 21 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [20] ,Byte 20 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [19] ,Byte 19 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [18] ,Byte 18 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [17] ,Byte 17 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [16] ,Byte 16 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [15] ,Byte 15 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [14] ,Byte 14 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [13] ,Byte 13 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [12] ,Byte 12 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [11] ,Byte 11 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [10] ,Byte 10 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [9] ,Byte 9 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [8] ,Byte 8 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [7] ,Byte 7 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [6] ,Byte 6 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [5] ,Byte 5 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [4] ,Byte 4 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,Byte 3 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Byte 2 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [1] ,Byte 1 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [0] ,Byte 0 byte enable" "Disabled,Enabled"
|
|
line.long 0x0C "ADX_IN_BYTE_EN1_0,Byte enables for bytes 32 to 63"
|
|
bitfld.long 0x0C 31. " BYTE_EN[63] ,Byte 63 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [62] ,Byte 62 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [61] ,Byte 61 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [60] ,Byte 60 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [59] ,Byte 59 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [58] ,Byte 58 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [57] ,Byte 57 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [56] ,Byte 56 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [55] ,Byte 55 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [54] ,Byte 54 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [53] ,Byte 53 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [52] ,Byte 52 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [51] ,Byte 51 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [50] ,Byte 50 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [49] ,Byte 49 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [48] ,Byte 48 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [47] ,Byte 47 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [46] ,Byte 46 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [45] ,Byte 45 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [44] ,Byte 44 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [43] ,Byte 43 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [42] ,Byte 42 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [41] ,Byte 41 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [40] ,Byte 40 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [39] ,Byte 39 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [38] ,Byte 38 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [37] ,Byte 37 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [36] ,Byte 36 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [35] ,Byte 35 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [34] ,Byte 34 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [33] ,Byte 33 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [32] ,Byte 32 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x10 "ADX_AUDIORAMCTL_ADX_CTRL_0,ADX_AUDIORAMCTL_ADX_CTRL_0"
|
|
rbitfld.long 0x10 31. " READ_BUSY ,Read busy" "Done,Busy"
|
|
bitfld.long 0x10 14. " RW ,Read write access" "Read,Write"
|
|
bitfld.long 0x10 13. " RESET_HW_ADR ,Reset hardware address" "Done,Busy"
|
|
bitfld.long 0x10 12. " HW_ADR_EN ,Hardware address enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " RAM_ADR ,Ram address"
|
|
line.long 0x14 "ADX_AUDIORAMCTL_ADX_DATA_0,ADX_AUDIORAMCTL ADX Data_0"
|
|
line.long 0x18 "ADX_AUDIOCIF_IN_CTRL_0,ADX_AUDIOCIF_IN_CTRL_0"
|
|
bitfld.long 0x18 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x18 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
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|
bitfld.long 0x18 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x18 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x18 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x18 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x18 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x18 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x18 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ADX_AUDIOCIF_CH0_CTRL_0,Adx_Audiocif_Ch0_Ctrl_0"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
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|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
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|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,mono conv" "Zero,Copy"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ADX_AUDIOCIF_CH1_CTRL_0,Adx_Audiocif_Ch1_Ctrl_0"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
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|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,mono conv" "Zero,Copy"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ADX_AUDIOCIF_CH2_CTRL_0,Adx_Audiocif_Ch2_Ctrl_0"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,mono conv" "Zero,Copy"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ADX_AUDIOCIF_CH3_CTRL_0,Adx_Audiocif_Ch3_Ctrl_0"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,mono conv" "Zero,Copy"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADX1"
|
|
base ad:0x70303900
|
|
width 28.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "ADX_CTRL_0,ADX Control Register"
|
|
bitfld.long 0x00 31. " SOFT_RESET ,Resets ADX logic" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CG_EN ,Second-level clock gating enable" "Disabled,Enabled"
|
|
line.long 0x04 "ADX_OUT_CH_CTRL_0,ADX output channels control"
|
|
bitfld.long 0x04 11. " CH3_FORCE_DISABLE ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " CH2_FORCE_DISABLE ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " CH1_FORCE_DISABLE ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CH0_FORCE_DISABLE ,Channel 0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CH3_EN ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CH2_EN ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CH1_EN ,Channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH0_EN ,Channel 0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x08 "ADX_IN_BYTE_EN0_0,Byte enables for bytes 0 to 31"
|
|
bitfld.long 0x08 31. " BYTE_EN[31] ,Byte 31 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [30] ,Byte 30 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [29] ,Byte 29 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [28] ,Byte 28 byte enable" "Disabled,Enabled"
|
|
textline " "
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|
bitfld.long 0x08 27. " [27] ,Byte 27 byte enable" "Disabled,Enabled"
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|
bitfld.long 0x08 26. " [26] ,Byte 26 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [25] ,Byte 25 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [24] ,Byte 24 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " [23] ,Byte 23 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [22] ,Byte 22 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [21] ,Byte 21 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [20] ,Byte 20 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [19] ,Byte 19 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [18] ,Byte 18 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [17] ,Byte 17 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [16] ,Byte 16 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " [15] ,Byte 15 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [14] ,Byte 14 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [13] ,Byte 13 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [12] ,Byte 12 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " [11] ,Byte 11 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [10] ,Byte 10 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [9] ,Byte 9 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [8] ,Byte 8 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [7] ,Byte 7 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [6] ,Byte 6 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [5] ,Byte 5 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [4] ,Byte 4 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,Byte 3 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Byte 2 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [1] ,Byte 1 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [0] ,Byte 0 byte enable" "Disabled,Enabled"
|
|
line.long 0x0C "ADX_IN_BYTE_EN1_0,Byte enables for bytes 32 to 63"
|
|
bitfld.long 0x0C 31. " BYTE_EN[63] ,Byte 63 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [62] ,Byte 62 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [61] ,Byte 61 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [60] ,Byte 60 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " [59] ,Byte 59 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [58] ,Byte 58 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [57] ,Byte 57 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [56] ,Byte 56 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " [55] ,Byte 55 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [54] ,Byte 54 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [53] ,Byte 53 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [52] ,Byte 52 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [51] ,Byte 51 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [50] ,Byte 50 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [49] ,Byte 49 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [48] ,Byte 48 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " [47] ,Byte 47 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [46] ,Byte 46 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [45] ,Byte 45 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [44] ,Byte 44 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " [43] ,Byte 43 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [42] ,Byte 42 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [41] ,Byte 41 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [40] ,Byte 40 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [39] ,Byte 39 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [38] ,Byte 38 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [37] ,Byte 37 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [36] ,Byte 36 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [35] ,Byte 35 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [34] ,Byte 34 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [33] ,Byte 33 byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [32] ,Byte 32 byte enable" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x10 "ADX_AUDIORAMCTL_ADX_CTRL_0,ADX_AUDIORAMCTL_ADX_CTRL_0"
|
|
rbitfld.long 0x10 31. " READ_BUSY ,Read busy" "Done,Busy"
|
|
bitfld.long 0x10 14. " RW ,Read write access" "Read,Write"
|
|
bitfld.long 0x10 13. " RESET_HW_ADR ,Reset hardware address" "Done,Busy"
|
|
bitfld.long 0x10 12. " HW_ADR_EN ,Hardware address enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " RAM_ADR ,Ram address"
|
|
line.long 0x14 "ADX_AUDIORAMCTL_ADX_DATA_0,ADX_AUDIORAMCTL ADX Data_0"
|
|
line.long 0x18 "ADX_AUDIOCIF_IN_CTRL_0,ADX_AUDIOCIF_IN_CTRL_0"
|
|
bitfld.long 0x18 24.--29. " FIFO_THRESHOLD ,Fifo threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x18 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x18 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x18 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x18 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x18 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x18 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x18 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x18 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x18 0. " MONO_CONV ,Mono conv" "Zero,Copy"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ADX_AUDIOCIF_CH0_CTRL_0,Adx_Audiocif_Ch0_Ctrl_0"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,mono conv" "Zero,Copy"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ADX_AUDIOCIF_CH1_CTRL_0,Adx_Audiocif_Ch1_Ctrl_0"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,mono conv" "Zero,Copy"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ADX_AUDIOCIF_CH2_CTRL_0,Adx_Audiocif_Ch2_Ctrl_0"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,mono conv" "Zero,Copy"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ADX_AUDIOCIF_CH3_CTRL_0,Adx_Audiocif_Ch3_Ctrl_0"
|
|
bitfld.long 0x00 24.--29. " FIFO_THRESHOLD ,FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--23. " AUDIO_CHANNELS ,Audio channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 16.--19. " CLIENT_CHANNELS ,Client channels" "Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,CH10,CH11,Ch12,Ch13,Ch14,Ch15,Ch16"
|
|
bitfld.long 0x00 12.--14. " AUDIO_BITS ,Audio bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLIENT_BITS ,Client bits" "Bit4,Bit8,Bit12,Bit16,Bit20,Bit24,Bit28,Bit32"
|
|
bitfld.long 0x00 6.--7. " EXPAND ,Expand" "Zero,One,LFSR,"
|
|
bitfld.long 0x00 4.--5. " STEREO_CONV ,Stereo conv" "Ch0,Ch1,AVG,"
|
|
bitfld.long 0x00 3. " REPLICATE ,Replicate" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DIRECTION ,Direction" "TXCIF,RXCIF"
|
|
bitfld.long 0x00 1. " TRUNCATE ,Truncate" "Round,Chop"
|
|
bitfld.long 0x00 0. " MONO_CONV ,mono conv" "Zero,Copy"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree "Display Controller"
|
|
tree "Display A"
|
|
base ad:0x54200000
|
|
width 29.
|
|
tree "Display CMD Registers"
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "GENERAL_INCR_SYNCPT_0,GENERAL_INCR_SYNCPT_0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERAL_COND ,Condition mapped from raise/wait"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GENERAL_INDX ,Syncpt index value"
|
|
line.long 0x04 "GENERAL_INCR_SYNCPT_CNTRL_0,GENERAL_INCR_SYNCPT_CNTRL_0"
|
|
bitfld.long 0x04 8. " GENERAL_INCR_SYNCPT_NO_STALL ,GENERAL_INCR_SYNCPT_NO_STALL" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " GENERAL_INCR_SYNCPT_SOFT_RESET ,GENERAL_INCR_SYNCPT_SOFT_RESET" "No reset,Reset"
|
|
line.long 0x08 "GENERAL_INCR_SYNCPT_ERROR_0,GENERAL_INCR_SYNCPT_ERROR_0"
|
|
eventfld.long 0x08 31. " COND_STATUS[31] ,FIFO overflow for COND[31]" "No overflow,Overflow"
|
|
eventfld.long 0x08 30. " [30] ,FIFO overflow for COND[30]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 29. " [29] ,FIFO overflow for COND[29]" "No overflow,Overflow"
|
|
eventfld.long 0x08 28. " [28] ,FIFO overflow for COND[28]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 27. " [27] ,FIFO overflow for COND[27]" "No overflow,Overflow"
|
|
eventfld.long 0x08 26. " [26] ,FIFO overflow for COND[26]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 25. " [25] ,FIFO overflow for COND[25]" "No overflow,Overflow"
|
|
eventfld.long 0x08 24. " [24] ,FIFO overflow for COND[24]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 23. " [23] ,FIFO overflow for COND[23]" "No overflow,Overflow"
|
|
eventfld.long 0x08 22. " [22] ,FIFO overflow for COND[22]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 21. " [21] ,FIFO overflow for COND[21]" "No overflow,Overflow"
|
|
eventfld.long 0x08 20. " [20] ,FIFO overflow for COND[20]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 19. " [19] ,FIFO overflow for COND[19]" "No overflow,Overflow"
|
|
eventfld.long 0x08 18. " [18] ,FIFO overflow for COND[18]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 17. " [17] ,FIFO overflow for COND[17]" "No overflow,Overflow"
|
|
eventfld.long 0x08 16. " [16] ,FIFO overflow for COND[16]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 15. " [15] ,FIFO overflow for COND[15]" "No overflow,Overflow"
|
|
eventfld.long 0x08 14. " [14] ,FIFO overflow for COND[14]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 13. " [13] ,FIFO overflow for COND[13]" "No overflow,Overflow"
|
|
eventfld.long 0x08 12. " [12] ,FIFO overflow for COND[12]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 11. " [11] ,FIFO overflow for COND[11]" "No overflow,Overflow"
|
|
eventfld.long 0x08 10. " [10] ,FIFO overflow for COND[10]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 9. " [9] ,FIFO overflow for COND[9]" "No overflow,Overflow"
|
|
eventfld.long 0x08 8. " [8] ,FIFO overflow for COND[8]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 7. " [7] ,FIFO overflow for COND[7]" "No overflow,Overflow"
|
|
eventfld.long 0x08 6. " [6] ,FIFO overflow for COND[6]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 5. " [5] ,FIFO overflow for COND[5]" "No overflow,Overflow"
|
|
eventfld.long 0x08 4. " [4] ,FIFO overflow for COND[4]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 3. " [3] ,FIFO overflow for COND[3]" "No overflow,Overflow"
|
|
eventfld.long 0x08 2. " [2] ,FIFO overflow for COND[2]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 1. " [1] ,FIFO overflow for COND[1]" "No overflow,Overflow"
|
|
eventfld.long 0x08 0. " [0] ,FIFO overflow for COND[0]" "No overflow,Overflow"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "WIN_A_INCR_SYNCPT_0,WIN_A_INCR_SYNCPT_0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WIN_A_COND ,Condition mapped from raise/wait"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WIN_A_INDX ,Syncpt index value"
|
|
line.long 0x04 "WIN_A_INCR_SYNCPT_CNTRL_0,WIN_A_INCR_SYNCPT_CNTRL_0"
|
|
bitfld.long 0x04 8. " WIN_A_INCR_SYNCPT_NO_STALL ,WIN_A_INCR_SYNCPT_NO_STALL" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " WIN_A_INCR_SYNCPT_SOFT_RESET ,WIN_A_INCR_SYNCPT_SOFT_RESET" "No reset,Reset"
|
|
line.long 0x08 "WIN_A_INCR_SYNCPT_ERROR_0,WIN_A_INCR_SYNCPT_ERROR_0"
|
|
eventfld.long 0x08 31. " COND_STATUS[31] ,FIFO overflow for COND[31]" "No overflow,Overflow"
|
|
eventfld.long 0x08 30. " [30] ,FIFO overflow for COND[30]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 29. " [29] ,FIFO overflow for COND[29]" "No overflow,Overflow"
|
|
eventfld.long 0x08 28. " [28] ,FIFO overflow for COND[28]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 27. " [27] ,FIFO overflow for COND[27]" "No overflow,Overflow"
|
|
eventfld.long 0x08 26. " [26] ,FIFO overflow for COND[26]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 25. " [25] ,FIFO overflow for COND[25]" "No overflow,Overflow"
|
|
eventfld.long 0x08 24. " [24] ,FIFO overflow for COND[24]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 23. " [23] ,FIFO overflow for COND[23]" "No overflow,Overflow"
|
|
eventfld.long 0x08 22. " [22] ,FIFO overflow for COND[22]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 21. " [21] ,FIFO overflow for COND[21]" "No overflow,Overflow"
|
|
eventfld.long 0x08 20. " [20] ,FIFO overflow for COND[20]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 19. " [19] ,FIFO overflow for COND[19]" "No overflow,Overflow"
|
|
eventfld.long 0x08 18. " [18] ,FIFO overflow for COND[18]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 17. " [17] ,FIFO overflow for COND[17]" "No overflow,Overflow"
|
|
eventfld.long 0x08 16. " [16] ,FIFO overflow for COND[16]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 15. " [15] ,FIFO overflow for COND[15]" "No overflow,Overflow"
|
|
eventfld.long 0x08 14. " [14] ,FIFO overflow for COND[14]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 13. " [13] ,FIFO overflow for COND[13]" "No overflow,Overflow"
|
|
eventfld.long 0x08 12. " [12] ,FIFO overflow for COND[12]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 11. " [11] ,FIFO overflow for COND[11]" "No overflow,Overflow"
|
|
eventfld.long 0x08 10. " [10] ,FIFO overflow for COND[10]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 9. " [9] ,FIFO overflow for COND[9]" "No overflow,Overflow"
|
|
eventfld.long 0x08 8. " [8] ,FIFO overflow for COND[8]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 7. " [7] ,FIFO overflow for COND[7]" "No overflow,Overflow"
|
|
eventfld.long 0x08 6. " [6] ,FIFO overflow for COND[6]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 5. " [5] ,FIFO overflow for COND[5]" "No overflow,Overflow"
|
|
eventfld.long 0x08 4. " [4] ,FIFO overflow for COND[4]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 3. " [3] ,FIFO overflow for COND[3]" "No overflow,Overflow"
|
|
eventfld.long 0x08 2. " [2] ,FIFO overflow for COND[2]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 1. " [1] ,FIFO overflow for COND[1]" "No overflow,Overflow"
|
|
eventfld.long 0x08 0. " [0] ,FIFO overflow for COND[0]" "No overflow,Overflow"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "WIN_B_INCR_SYNCPT_0,WIN_B_INCR_SYNCPT_0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WIN_B_COND ,Condition mapped from raise/wait"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WIN_B_INDX ,Syncpt index value"
|
|
line.long 0x04 "WIN_B_INCR_SYNCPT_CNTRL_0,WIN_B_INCR_SYNCPT_CNTRL_0"
|
|
bitfld.long 0x04 8. " WIN_B_INCR_SYNCPT_NO_STALL ,WIN_B_INCR_SYNCPT_NO_STALL" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " WIN_B_INCR_SYNCPT_SOFT_RESET ,WIN_B_INCR_SYNCPT_SOFT_RESET" "No reset,Reset"
|
|
line.long 0x08 "WIN_B_INCR_SYNCPT_ERROR_0,WIN_B_INCR_SYNCPT_ERROR_0"
|
|
eventfld.long 0x08 31. " COND_STATUS[31] ,FIFO overflow for COND[31]" "No overflow,Overflow"
|
|
eventfld.long 0x08 30. " [30] ,FIFO overflow for COND[30]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 29. " [29] ,FIFO overflow for COND[29]" "No overflow,Overflow"
|
|
eventfld.long 0x08 28. " [28] ,FIFO overflow for COND[28]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 27. " [27] ,FIFO overflow for COND[27]" "No overflow,Overflow"
|
|
eventfld.long 0x08 26. " [26] ,FIFO overflow for COND[26]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 25. " [25] ,FIFO overflow for COND[25]" "No overflow,Overflow"
|
|
eventfld.long 0x08 24. " [24] ,FIFO overflow for COND[24]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 23. " [23] ,FIFO overflow for COND[23]" "No overflow,Overflow"
|
|
eventfld.long 0x08 22. " [22] ,FIFO overflow for COND[22]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 21. " [21] ,FIFO overflow for COND[21]" "No overflow,Overflow"
|
|
eventfld.long 0x08 20. " [20] ,FIFO overflow for COND[20]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 19. " [19] ,FIFO overflow for COND[19]" "No overflow,Overflow"
|
|
eventfld.long 0x08 18. " [18] ,FIFO overflow for COND[18]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 17. " [17] ,FIFO overflow for COND[17]" "No overflow,Overflow"
|
|
eventfld.long 0x08 16. " [16] ,FIFO overflow for COND[16]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 15. " [15] ,FIFO overflow for COND[15]" "No overflow,Overflow"
|
|
eventfld.long 0x08 14. " [14] ,FIFO overflow for COND[14]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 13. " [13] ,FIFO overflow for COND[13]" "No overflow,Overflow"
|
|
eventfld.long 0x08 12. " [12] ,FIFO overflow for COND[12]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 11. " [11] ,FIFO overflow for COND[11]" "No overflow,Overflow"
|
|
eventfld.long 0x08 10. " [10] ,FIFO overflow for COND[10]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 9. " [9] ,FIFO overflow for COND[9]" "No overflow,Overflow"
|
|
eventfld.long 0x08 8. " [8] ,FIFO overflow for COND[8]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 7. " [7] ,FIFO overflow for COND[7]" "No overflow,Overflow"
|
|
eventfld.long 0x08 6. " [6] ,FIFO overflow for COND[6]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 5. " [5] ,FIFO overflow for COND[5]" "No overflow,Overflow"
|
|
eventfld.long 0x08 4. " [4] ,FIFO overflow for COND[4]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 3. " [3] ,FIFO overflow for COND[3]" "No overflow,Overflow"
|
|
eventfld.long 0x08 2. " [2] ,FIFO overflow for COND[2]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 1. " [1] ,FIFO overflow for COND[1]" "No overflow,Overflow"
|
|
eventfld.long 0x08 0. " [0] ,FIFO overflow for COND[0]" "No overflow,Overflow"
|
|
group.long 0x60++0x0B
|
|
line.long 0x00 "WIN_C_INCR_SYNCPT_0,WIN_C_INCR_SYNCPT_0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WIN_C_COND ,Condition mapped from raise/wait"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WIN_C_INDX ,Syncpt index value"
|
|
line.long 0x04 "WIN_C_INCR_SYNCPT_CNTRL_0,WIN_C_INCR_SYNCPT_CNTRL_0"
|
|
bitfld.long 0x04 8. " WIN_C_INCR_SYNCPT_NO_STALL ,WIN_C_INCR_SYNCPT_NO_STALL" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " WIN_C_INCR_SYNCPT_SOFT_RESET ,WIN_C_INCR_SYNCPT_SOFT_RESET" "No reset,Reset"
|
|
line.long 0x08 "WIN_C_INCR_SYNCPT_ERROR_0,WIN_C_INCR_SYNCPT_ERROR_0"
|
|
eventfld.long 0x08 31. " COND_STATUS[31] ,FIFO overflow for COND[31]" "No overflow,Overflow"
|
|
eventfld.long 0x08 30. " [30] ,FIFO overflow for COND[30]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 29. " [29] ,FIFO overflow for COND[29]" "No overflow,Overflow"
|
|
eventfld.long 0x08 28. " [28] ,FIFO overflow for COND[28]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 27. " [27] ,FIFO overflow for COND[27]" "No overflow,Overflow"
|
|
eventfld.long 0x08 26. " [26] ,FIFO overflow for COND[26]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 25. " [25] ,FIFO overflow for COND[25]" "No overflow,Overflow"
|
|
eventfld.long 0x08 24. " [24] ,FIFO overflow for COND[24]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 23. " [23] ,FIFO overflow for COND[23]" "No overflow,Overflow"
|
|
eventfld.long 0x08 22. " [22] ,FIFO overflow for COND[22]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 21. " [21] ,FIFO overflow for COND[21]" "No overflow,Overflow"
|
|
eventfld.long 0x08 20. " [20] ,FIFO overflow for COND[20]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 19. " [19] ,FIFO overflow for COND[19]" "No overflow,Overflow"
|
|
eventfld.long 0x08 18. " [18] ,FIFO overflow for COND[18]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 17. " [17] ,FIFO overflow for COND[17]" "No overflow,Overflow"
|
|
eventfld.long 0x08 16. " [16] ,FIFO overflow for COND[16]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 15. " [15] ,FIFO overflow for COND[15]" "No overflow,Overflow"
|
|
eventfld.long 0x08 14. " [14] ,FIFO overflow for COND[14]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 13. " [13] ,FIFO overflow for COND[13]" "No overflow,Overflow"
|
|
eventfld.long 0x08 12. " [12] ,FIFO overflow for COND[12]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 11. " [11] ,FIFO overflow for COND[11]" "No overflow,Overflow"
|
|
eventfld.long 0x08 10. " [10] ,FIFO overflow for COND[10]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 9. " [9] ,FIFO overflow for COND[9]" "No overflow,Overflow"
|
|
eventfld.long 0x08 8. " [8] ,FIFO overflow for COND[8]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 7. " [7] ,FIFO overflow for COND[7]" "No overflow,Overflow"
|
|
eventfld.long 0x08 6. " [6] ,FIFO overflow for COND[6]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 5. " [5] ,FIFO overflow for COND[5]" "No overflow,Overflow"
|
|
eventfld.long 0x08 4. " [4] ,FIFO overflow for COND[4]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 3. " [3] ,FIFO overflow for COND[3]" "No overflow,Overflow"
|
|
eventfld.long 0x08 2. " [2] ,FIFO overflow for COND[2]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 1. " [1] ,FIFO overflow for COND[1]" "No overflow,Overflow"
|
|
eventfld.long 0x08 0. " [0] ,FIFO overflow for COND[0]" "No overflow,Overflow"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CONT_SYNCPT_VSYNC_0,CONT_SYNCPT_VSYNC_0"
|
|
bitfld.long 0x00 8. " VSYNC_EN ,Vsync enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VSYNC_INDX ,Return INDX"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CTXSW_0,Context Switch Register"
|
|
rbitfld.long 0x00 28.--31. " NEXT_CHANNEL ,Next requested channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 16.--25. 1. " NEXT_CLASS ,Next requested class"
|
|
bitfld.long 0x00 12.--15. " CURR_CHANNEL ,Current working channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AUTO_ACK ,Automatically acknowledge any incoming context switch requests" "Manual,AutoACK"
|
|
hexmask.long.word 0x00 0.--9. 1. " CURR_CLASS ,Current working class"
|
|
if (((per.l(ad:0x54200000+0xC8))&0x60)==0x40)
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DISPLAY_COMMAND_OPTION0_0,Display Controller Option 0"
|
|
bitfld.long 0x00 18. " WINDOW_C_NC_DISPLAY ,Window C Non-Continuous display" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " WINDOW_B_NC_DISPLAY ,Window B Non-Continuous display" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " WINDOW_A_NC_DISPLAY ,Window A Non-Continuous display" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SSF_SOURCE ,Source pin for the SSF input" "SSF_LDC,SSF_LSPI,SSF_LSDI,?..."
|
|
bitfld.long 0x00 5. " SSF_ENABLE ,Sub-Display Stop Frame (SSF) input" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SSF_POLARITY ,Sub-Display Stop Frame (SSF) Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MSF_SOURCE ,Source pin for the MSF input" "MSF_LSPI,MSF_LDC,MSF_LSDI,?..."
|
|
bitfld.long 0x00 1. " MSF_ENABLE ,Main-Display Stop Frame (MSF) input" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MSF_POLARITY ,Main-Display Stop Frame (MSF) Polarity" "Active high,Active low"
|
|
else
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DISPLAY_COMMAND_OPTION0_0,Display Controller Option 0"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SSF_SOURCE ,Source pin for the SSF input" "SSF_LDC,SSF_LSPI,SSF_LSDI,?..."
|
|
bitfld.long 0x00 4. " SSF_POLARITY ,Sub-Display Stop Frame (SSF) Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MSF_SOURCE ,Source pin for the MSF input" "MSF_LSPI,MSF_LDC,MSF_LSDI,?..."
|
|
bitfld.long 0x00 0. " MSF_POLARITY ,Main-Display Stop Frame (MSF) Polarity" "Active high,Active low"
|
|
endif
|
|
group.long 0xC8++0x07
|
|
line.long 0x00 "DISPLAY_COMMAND_0,Display Command"
|
|
bitfld.long 0x00 27.--30. " DISP_COMMAND_RAISE_CHANNEL_ID ,Display Command Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--26. " DISP_COMMAND_RAISE_VECTOR ,Display Command Raise Vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--6. " DISPLAY_CTRL_MODE ,Display Controller Mode" "STOP,Continuous,Non-Continuous,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DISP_COMMAND_RAISE ,Display Command Raise" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "SIGNAL_RAISE_0,SIGNAL_RAISE_0"
|
|
bitfld.long 0x04 16.--19. " SIGNAL_RAISE_CHANNEL_ID ,Signal Raise Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 12. " SIGNAL_RAISE_TYPE ,Signal raise type" "One-shot,Continuous"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " SIGNAL_RAISE_SELECT ,Signal to raise" "None,Frame End,V Blank,V Pulse 3,Rising edge of V Blank,Falling edge of V Blank,Rising edge of V Pulse 3,Falling edge of V Pulse 3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " SIGNAL_RAISE_VECTOR ,Bit number to raise" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "DISPLAY_POWER_CONTROL_0,Display Power Control"
|
|
width 17.
|
|
textline " "
|
|
group.long 0xDC++0x1F
|
|
line.long 0x00 "INT_STATUS_0,Display Interrupt and Status"
|
|
sif CPUIS("TEGRAX1")
|
|
eventfld.long 0x00 29. " DSC_TO_UF_INT ,DSC TO Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " DSC_BBUF_UF_INT ,DSC BBUF Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 27. " DSC_RBUF_UF_INT ,DSC RBUF Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 26. " DSC_OBUF_UF_INT ,DSC OBUF Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 25. " WIN_T_UF_INT ,Window T Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " WIN_D_UF_INT ,Window D Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " HC_UF_INT ,Cursor Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CMU_LUT_CONFLICT_INT ,CMU LUT read/write conflict" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " WIN_C_OF_INT ,Window C Overflow Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " WIN_B_OF_INT ,Window B Overflow Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " WIN_A_OF_INT ,Window A Overflow Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " SSF_INT ,Sub-Display Stop Frame Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " MSF_INT ,Main-Display Stop Frame Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 10. " WIN_C_UF_INT ,Window C Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " WIN_B_UF_INT ,Window B Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " WIN_A_UF_INT ,Window A Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " SPI_BUSY_INT ,SPI Busy Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " V_PULSE2_INT ,Vertical Pulse 2 Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " V_PULSE3_INT ,Vertical Pulse 3 Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " H_BLANK_INT ,Horizontal Blank Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " V_BLANK_INT ,Vertical Blank Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " FRAME_END_INT ,Frame End Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " CTXSW_INT ,Context Switch Interrupt Status" "No interrupt,Interrupt"
|
|
line.long 0x04 "INT_MASK_0,Interrupt Mask"
|
|
sif CPUIS("TEGRAX1")
|
|
bitfld.long 0x04 29. " DSC_TO_UF_INT ,DSC TO Underflow Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 28. " DSC_BBUF_UF_INT ,DSC BBUF Underflow Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 27. " DSC_RBUF_UF_INT ,DSC RBUF Underflow Interrupt Mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 26. " DSC_OBUF_UF_INT ,DSC OBUF Underflow Interrupt Mask" "Masked,Unmasked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 25. " WIN_T_UF_INT_MASK ,Window T Underflow Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 24. " WIN_D_UF_INT_MASK ,Window D Underflow Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 23. " HC_UF_INT_MASK ,Cursor Underflow Interrupt Mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 22. " CMU_LUT_CONFLICT_INT_MASK ,CMU LUT read/write conflict Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 16. " WIN_C_OF_INT_MASK ,Window C Overflow Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 15. " WIN_B_OF_INT_MASK ,Window B Overflow Interrupt Mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " WIN_A_OF_INT_MASK ,Window A Overflow Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 13. " SSF_INT_MASK ,Sub-Display Stop Frame Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 12. " MSF_INT_MASK ,Main-Display Stop Frame Interrupt Mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " WIN_C_UF_INT_MASK ,Window C Underflow Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " WIN_B_UF_INT_MASK ,Window B Underflow Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " WIN_A_UF_INT_MASK ,Window A Underflow Interrupt Mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SPI_BUSY_INT_MASK ,SPI Busy Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 5. " V_PULSE2_INT_MASK ,Vertical Pulse 2 Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " V_PULSE3_INT_MASK ,Vertical Pulse 3 Interrupt Mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " H_BLANK_INT_MASK ,Horizontal Blank Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 2. " V_BLANK_INT_MASK ,Vertical Blank Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " FRAME_END_INT_MASK ,Frame End Interrupt Mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CTXSW_INT_MASK ,Context Switch Interrupt Mask" "Masked,Unmasked"
|
|
line.long 0x08 "INT_ENABLE_0,Interrupt Enable"
|
|
sif CPUIS("TEGRAX1")
|
|
bitfld.long 0x08 29. " DSC_TO_UF_INT_ENABLE ,DSC TO Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " DSC_BBUF_UF_INT_ENABLE ,DSC BBUF Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " DSC_RBUF_UF_INT_ENABLE ,DSC RBUF Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 26. " DSC_OBUF_UF_INT_ENABLE ,DSC OBUF Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 25. " WIN_T_UF_INT_ENABLE ,Window T Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " WIN_D_UF_INT_ENABLE ,Window D Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " HC_UF_INT_ENABLE ,Cursor Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 22. " CMU_LUT_CONFLICT_INT_ENABLE ,CMU LUT read/write conflict" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " WIN_C_OF_INT_ENABLE ,Window C Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " WIN_B_OF_INT_ENABLE ,Window B Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 14. " WIN_A_OF_INT_ENABLE ,Window A Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " SSF_INT_ENABLE ,Sub-Display Stop Frame Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " MSF_INT_ENABLE ,Main-Display Stop Frame Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " WIN_C_UF_INT_ENABLE ,Window C Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " WIN_B_UF_INT_ENABLE ,Window B Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " WIN_A_UF_INT_ENABLE ,Window A Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SPI_BUSY_INT_ENABLE ,SPI Busy Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " V_PULSE2_INT_ENABLE ,Vertical Pulse 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " V_PULSE3_INT_ENABLE ,Vertical Pulse 3 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " H_BLANK_INT_ENABLE ,Horizontal Blank Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " V_BLANK_INT_ENABLE ,Vertical Blank Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " FRAME_END_INT_ENABLE ,Frame End Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CTXSW_INT_ENABLE ,Context Switch Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x0C "INT_TYPE_0,Interrupt Type"
|
|
sif CPUIS("TEGRAX1")
|
|
bitfld.long 0x0C 29. " DSC_TO_UF_INT_TYPE ,DSC TO Underflow Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 28. " DSC_BBUF_UF_INT_TYPE ,DSC BBUF Underflow Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 27. " DSC_RBUF_UF_INT_TYPE ,DSC RBUF Underflow Interrupt Type" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x0C 26. " DSC_OBUF_UF_INT_TYPE ,DSC OBUF Underflow Interrupt Type" "Edge,Level"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 25. " WIN_T_UF_INT_TYPE ,Window T Underflow Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 24. " WIN_D_UF_INT_TYPE ,Window D Underflow Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 23. " HC_UF_INT_TYPE ,Cursor Underflow Interrupt Type" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " CMU_LUT_CONFLICT_INT_TYPE ,CMU LUT read/write conflict" "Edge,Level"
|
|
bitfld.long 0x0C 16. " WIN_C_OF_INT_TYPE ,Window C Overflow Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 15. " WIN_B_OF_INT_TYPE ,Window B Overflow Interrupt Type" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " WIN_A_OF_INT_TYPE ,Window A Overflow Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 13. " SSF_INT_TYPE ,Sub-Display Stop Frame Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 11. " EPP_OF_INT_TYPE ,Display2epp Overflow Interrupt Type" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " WIN_C_UF_INT_TYPE ,Window C Underflow Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 9. " WIN_B_UF_INT_TYPE ,Window B Underflow Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 8. " WIN_A_UF_INT_TYPE ,Window A Underflow Interrupt Type" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " SPI_BUSY_INT_TYPE ,SPI Busy Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 5. " V_PULSE2_INT_TYPE ,Vertical Pulse 2 Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 4. " V_PULSE3_INT_TYPE ,Vertical Pulse 3 Interrupt Type" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " H_BLANK_INT_TYPE ,Horizontal Blank Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 2. " V_BLANK_INT_TYPE ,Vertical Blank Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 1. " FRAME_END_INT_TYPE ,Frame End Interrupt Type" "Edge,Level"
|
|
line.long 0x10 "INT_POLARITY_0,Interrupt Polarity"
|
|
sif CPUIS("TEGRAX1")
|
|
bitfld.long 0x10 29. " DSC_TO_UF_INT_POLARITY ,DSC TO Underflow Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 28. " DSC_BBUF_UF_INT_POLARITY ,DSC BBUF Underflow Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 27. " DSC_RBUF_UF_INT_POLARITY ,DSC RBUF Underflow Interrupt Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 26. " DSC_OBUF_UF_INT_POLARITY ,DSC OBUF Underflow Interrupt Polarity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 25. " WIN_T_UF_INT_POLARITY ,Window T Underflow Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 24. " WIN_D_UF_INT_POLARITY ,Window D Underflow Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 23. " HC_UF_INT_POLARITY ,Cursor Underflow Interrupt Polarity" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x10 22. " CMU_LUT_CONFLICT_INT_POLARITY ,CMU LUT read/write conflict" "Low,High"
|
|
bitfld.long 0x10 16. " WIN_C_OF_INT_POLARITY ,Window C Overflow Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 15. " WIN_B_OF_INT_POLARITY ,Window B Overflow Interrupt Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 14. " WIN_A_OF_INT_POLARITY ,Window A Overflow Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 13. " SSF_INT_POLARITY ,Sub-Display Stop Frame Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 12. " MSF_INT_POLARITY ,Main-Display Stop Frame Interrupt Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 10. " WIN_C_UF_INT_POLARITY ,Window C Underflow Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 9. " WIN_B_UF_INT_POLARITY ,Window B Underflow Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 8. " WIN_A_UF_INT_POLARITY ,Window A Underflow Interrupt Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 7. " SPI_BUSY_INT_POLARITY ,SPI Busy Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 5. " V_PULSE2_INT_POLARITY ,V Pulse 2 Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 4. " V_PULSE3_INT_POLARITY ,Vertical Pulse 3 Interrupt Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 3. " H_BLANK_INT_POLARITY ,Horizontal Blank Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 2. " V_BLANK_INT_POLARITY ,Vertical Blank Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 1. " FRAME_END_INT_POLARITY ,Frame End Interrupt Polarity" "Low,High"
|
|
line.long 0x14 "SIGNAL_RAISE1_0,SIGNAL_RAISE1_0"
|
|
bitfld.long 0x14 16.--19. " SIGNAL_RAISE1_CHANNEL_ID ,Signal Raise Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 12. " SIGNAL_RAISE1_TYPE ,Signal Raise Type" "Oneshot,Continuous"
|
|
bitfld.long 0x14 8.--10. " SIGNAL_RAISE1_SELECT ,Signal Raise Select" "None,Frame End,V Blank,V Pulse 3,Rising edge of V Blank,Falling edge of V Blank,Rising edge of V Pulse 3,Falling edge of V Pulse 3"
|
|
textline " "
|
|
bitfld.long 0x14 0.--4. " SIGNAL_RAISE1_VECTOR ,Bit number to raise" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "SIGNAL_RAISE2_0,SIGNAL_RAISE2_0"
|
|
bitfld.long 0x18 16.--19. " SIGNAL_RAISE2_CHANNEL_ID ,Signal Raise Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 12. " SIGNAL_RAISE2_TYPE ,Signal Raise Type" "Oneshot,Continuous"
|
|
bitfld.long 0x18 8.--10. " SIGNAL_RAISE2_SELECT ,Signal Raise Select" "None,Frame End,V Blank,V Pulse 3,Rising edge of V Blank,Falling edge of V Blank,Rising edge of V Pulse 3,Falling edge of V Pulse 3"
|
|
textline " "
|
|
bitfld.long 0x18 0.--4. " SIGNAL_RAISE2_VECTOR ,Bit number to raise" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1C "SIGNAL_RAISE3_0,SIGNAL_RAISE3_0"
|
|
bitfld.long 0x1C 16.--19. " SIGNAL_RAISE3_CHANNEL_ID ,Signal Raise Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 12. " SIGNAL_RAISE3_TYPE ,Signal Raise Type" "Oneshot,Continuous"
|
|
bitfld.long 0x1C 8.--10. " SIGNAL_RAISE3_SELECT ,Signal Raise Select" "None,Frame End,V Blank,V Pulse 3,Rising edge of V Blank,Falling edge of V Blank,Rising edge of V Pulse 3,Falling edge of V Pulse 3"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--4. " SIGNAL_RAISE3_VECTOR ,Bit number to raise" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "STATE_ACCESS_0,Double/triple buffers read and write access control"
|
|
bitfld.long 0x00 2. " WRITE_MUX ,Write access control" "Assembly,Active"
|
|
bitfld.long 0x00 0. " READ_MUX ,Read access control" "Assembly,Active"
|
|
if (((per.l(ad:0x54200000+0xC8))&0x60)==0x40)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "STATE_CONTROL_0,State Control for Activating/Arming New Register State"
|
|
bitfld.long 0x00 24. " NC_HOST_TRIG_ENABLE ,Host trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CURSOR_UPDATE ,Trigger for the arming state for a subset of the triple buffered registers" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WIN_D_UPDATE ,Trigger for the arming state for the win D subset of the triple buffered registers" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WIN_C_UPDATE ,Trigger for arming state for the win C subset of the triple buffered registers" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WIN_B_UPDATE ,Trigger for arming state for the win B subset of the triple buffered registers" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " WIN_A_UPDATE ,rigger for arming state for the win A subset of the triple buffered registers" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GENERAL_UPDATE ,Trigger for arming state for a subset of the triple buffered registers" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CURSOR_ACT_REQ ,Non-window specific" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " WIN_D_ACT_REQ ,Window D activation request" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " WIN_C_ACT_REQ ,Window C activation request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WIN_B_ACT_REQ ,Window B activation request" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WIN_A_ACT_REQ ,Window A activation request" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GENERAL_ACT_REQ ,Non-window-specific" "Disabled,Enabled"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "STATE_CONTROL_0,State Control for Activating/Arming New Register State"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CURSOR_UPDATE ,Trigger for the arming state for a subset of the triple buffered registers" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WIN_D_UPDATE ,Trigger for the arming state for the win D subset of the triple buffered registers" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WIN_C_UPDATE ,Trigger for arming state for the win C subset of the triple buffered registers" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WIN_B_UPDATE ,Trigger for arming state for the win B subset of the triple buffered registers" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " WIN_A_UPDATE ,rigger for arming state for the win A subset of the triple buffered registers" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GENERAL_UPDATE ,Trigger for arming state for a subset of the triple buffered registers" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CURSOR_ACT_REQ ,Non-window specific" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " WIN_D_ACT_REQ ,Window D activation request" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " WIN_C_ACT_REQ ,Window C activation request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WIN_B_ACT_REQ ,Window B activation request" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WIN_A_ACT_REQ ,Window A activation request" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GENERAL_ACT_REQ ,Non-window-specific" "Disabled,Enabled"
|
|
endif
|
|
width 27.
|
|
textline " "
|
|
group.long 0x108++0x0F
|
|
line.long 0x00 "DISPLAY_WINDOW_HEADER_0,Display Window Programming Header"
|
|
bitfld.long 0x00 7. " WINDOW_D_SELECT ,Enable window D programming" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " WINDOW_C_SELECT ,Enable window C programming" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WINDOW_B_SELECT ,Enable window B programming" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WINDOW_A_SELECT ,Enable window A programming" "Disabled,Enabled"
|
|
line.long 0x04 "REG_ACT_CONTROL_0,Register activation options"
|
|
bitfld.long 0x04 10. " WIN_D_ACT_CNTR_SEL ,Select which counter to use for window D activation" "V counter,H counter"
|
|
bitfld.long 0x04 7. " CURSOR_ACT_CNTR_SEL ,Select which counter to use for Cursor activation" "V counter,H counter"
|
|
bitfld.long 0x04 6. " WIN_C_ACT_CNTR_SEL ,Select which counter to use for window C activation" "V counter,H counter"
|
|
textline " "
|
|
bitfld.long 0x04 4. " WIN_B_ACT_CNTR_SEL ,Select which counter to use for window B activation" "V counter,H counter"
|
|
bitfld.long 0x04 2. " WIN_A_ACT_CNTR_SEL ,Select which counter to use for window A activation" "V counter,H counter"
|
|
bitfld.long 0x04 0. " GENERAL_ACT_CNTR_SEL ,Select which counter to use for general activation" "V counter,H counter"
|
|
line.long 0x08 "WIN_T_STATE_CONTROL_0,WIN_T State control register for activating/arming new register state"
|
|
bitfld.long 0x08 8. " WIN_T_UPDATE ,Trigger for the arming state for the win B subset of the triple buffered registers" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " WIN_T_ACT_REQ ,Request pending" "Not requested,Requested"
|
|
line.long 0x0C "SECURE_CONTROL_0,Secure control register for enabling secure mode"
|
|
sif CPUIS("TEGRAX1")
|
|
bitfld.long 0x0C 14. " SECURE_SOR1_PROTECT ,Blanks the display output to SOR1" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 13. " SECURE_SOR_PROTECT ,Blanks the display output to SOR" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " SECURE_DSIB_PROTECT ,Blanks the display output to DSIB" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " SECURE_DSIA_PROTECT ,Blanks the display output to DSIA" "Disabled,Enabled"
|
|
textline " "
|
|
sif CPUIS("TEGRAK1")
|
|
bitfld.long 0x0C 10. " SECURE_HDMI_PROTECT ,Blanks the display output to HDMI" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 9. " SECURE_READ_MUX ,Controls which of the double-buffered window registers are read in TZ Secure mode" "Assembly,Active"
|
|
bitfld.long 0x0C 8. " SECURE_WRITE_MUX ,Controls which of the double-buffered window registers are written in TZ Secure mode" "Assembly,Active"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SECURE_CRC_PROTECT ,Disable CRC computation when enabled" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " SECURE_CMU_PROTECT ,CMU registers are only accessible in TZ Secure mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " SECURE_ENABLE ,Secure mode enable" "Disabled,Enabled"
|
|
group.long 0x130++0x0B
|
|
line.long 0x00 "WIN_D_INCR_SYNCPT_0,WIN_D_INCR_SYNCPT_0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WIN_D_COND ,Condition mapped from raise/wait"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WIN_D_INDX ,Syncpt index value"
|
|
line.long 0x04 "WIN_D_INCR_SYNCPT_CNTRL_0,WIN_D_INCR_SYNCPT_CNTRL_0"
|
|
bitfld.long 0x04 8. " WIN_D_INCR_SYNCPT_NO_STALL ,Host interface stall" "Stalled,Not stalled"
|
|
bitfld.long 0x04 0. " WIN_D_INCR_SYNCPT_SOFT_RESET ,Internal states of the client syncpt block reset" "No reset,Reset"
|
|
line.long 0x08 "WIN_D_INCR_SYNCPT_ERROR_0,WIN_D_INCR_SYNCPT_ERROR_0"
|
|
eventfld.long 0x08 31. " COND_STATUS[31] ,FIFO overflow for COND[31]" "No overflow,Overflow"
|
|
eventfld.long 0x08 30. " [30] ,FIFO overflow for COND[30]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 29. " [29] ,FIFO overflow for COND[29]" "No overflow,Overflow"
|
|
eventfld.long 0x08 28. " [28] ,FIFO overflow for COND[28]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 27. " [27] ,FIFO overflow for COND[27]" "No overflow,Overflow"
|
|
eventfld.long 0x08 26. " [26] ,FIFO overflow for COND[26]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 25. " [25] ,FIFO overflow for COND[25]" "No overflow,Overflow"
|
|
eventfld.long 0x08 24. " [24] ,FIFO overflow for COND[24]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 23. " [23] ,FIFO overflow for COND[23]" "No overflow,Overflow"
|
|
eventfld.long 0x08 22. " [22] ,FIFO overflow for COND[22]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 21. " [21] ,FIFO overflow for COND[21]" "No overflow,Overflow"
|
|
eventfld.long 0x08 20. " [20] ,FIFO overflow for COND[20]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 19. " [19] ,FIFO overflow for COND[19]" "No overflow,Overflow"
|
|
eventfld.long 0x08 18. " [18] ,FIFO overflow for COND[18]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 17. " [17] ,FIFO overflow for COND[17]" "No overflow,Overflow"
|
|
eventfld.long 0x08 16. " [16] ,FIFO overflow for COND[16]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 15. " [15] ,FIFO overflow for COND[15]" "No overflow,Overflow"
|
|
eventfld.long 0x08 14. " [14] ,FIFO overflow for COND[14]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 13. " [13] ,FIFO overflow for COND[13]" "No overflow,Overflow"
|
|
eventfld.long 0x08 12. " [12] ,FIFO overflow for COND[12]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 11. " [11] ,FIFO overflow for COND[11]" "No overflow,Overflow"
|
|
eventfld.long 0x08 10. " [10] ,FIFO overflow for COND[10]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 9. " [9] ,FIFO overflow for COND[9]" "No overflow,Overflow"
|
|
eventfld.long 0x08 8. " [8] ,FIFO overflow for COND[8]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 7. " [7] ,FIFO overflow for COND[7]" "No overflow,Overflow"
|
|
eventfld.long 0x08 6. " [6] ,FIFO overflow for COND[6]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 5. " [5] ,FIFO overflow for COND[5]" "No overflow,Overflow"
|
|
eventfld.long 0x08 4. " [4] ,FIFO overflow for COND[4]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 3. " [3] ,FIFO overflow for COND[3]" "No overflow,Overflow"
|
|
eventfld.long 0x08 2. " [2] ,FIFO overflow for COND[2]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 1. " [1] ,FIFO overflow for COND[1]" "No overflow,Overflow"
|
|
eventfld.long 0x08 0. " [0] ,FIFO overflow for COND[0]" "No overflow,Overflow"
|
|
tree.end
|
|
width 24.
|
|
tree "Display COM Registers"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "CRC_CONTROL_0,CRC Control"
|
|
bitfld.long 0x00 3. " CRC_ALWAYS ,CRC always" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CRC_INPUT_DATA ,CRC input data" "Full frame,Active display"
|
|
bitfld.long 0x00 1. " CRC_WAIT ,CRC Wait" "1 Vsync,2 Vsyncs"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CRC_ENABLE ,CRC Enable" "Disabled,Enabled"
|
|
rgroup.long 0xC04++0x03
|
|
line.long 0x00 "CRC_CHECKSUM_0,CRC Checksum"
|
|
group.long 0xC6C++0x0B
|
|
line.long 0x00 "PIN_MISC_CONTROL_0,Pin Miscellaneous Control"
|
|
bitfld.long 0x00 2. " DISP_CLOCK_OUTPUT ,Display Clock (DCLK)" "Disabled,Enabled"
|
|
line.long 0x04 "PM0_CONTROL_0,PM0 Signal Control"
|
|
bitfld.long 0x04 18.--23. " PM0_PERIOD ,PM0 Period" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256"
|
|
hexmask.long.word 0x04 4.--17. 1. " PM0_CLOCK_DIVIDER ,PM0 Clock Divider"
|
|
bitfld.long 0x04 0.--1. " PM0_CLOCK_SELECT ,PM0 Clock Select" "SCdiv output,Pixel,Line,Frame"
|
|
line.long 0x08 "PM0_DUTY_CYCLE_0,PM0 Duty Cycle"
|
|
hexmask.long.word 0x08 0.--8. 1. " PM0_DUTY_CYCLE ,PM0 Duty Cycle"
|
|
group.long 0xC94++0x07
|
|
line.long 0x00 "SCRATCH_REGISTER_A_0,Scratch Register A"
|
|
line.long 0x04 "SCRATCH_REGISTER_B_0,Scratch Register B"
|
|
rgroup.long 0xCA4++0x03
|
|
line.long 0x00 "CRC_CHECKSUM_LATCHED_0,CRC Checksum latched"
|
|
group.long 0xCA8++0x23
|
|
line.long 0x00 "CMU_CSC_KRR_0,CMU Color Space Conversion Matrix (KRR)"
|
|
hexmask.long.word 0x00 0.--9. 1. " KRR ,KRR"
|
|
line.long 0x04 "CMU_CSC_KGR_0,CMU Color Space Conversion Matrix (KGR)"
|
|
hexmask.long.word 0x04 0.--9. 1. " KGR ,KGR"
|
|
line.long 0x08 "CMU_CSC_KBR_0,CMU Color Space Conversion Matrix (KBR)"
|
|
hexmask.long.word 0x08 0.--9. 1. " KBR ,KBR"
|
|
line.long 0x0C "CMU_CSC_KRG_0,CMU Color Space Conversion Matrix (KRG)"
|
|
hexmask.long.word 0x0c 0.--9. 1. " KRG ,KRG"
|
|
line.long 0x10 "CMU_CSC_KGG_0,CMU Color Space Conversion Matrix (KGG)"
|
|
hexmask.long.word 0x10 0.--9. 1. " KGG ,KGG"
|
|
line.long 0x14 "CMU_CSC_KBG_0,CMU Color Space Conversion Matrix (KBG)"
|
|
hexmask.long.word 0x14 0.--9. 1. " KBG ,KBG"
|
|
line.long 0x18 "CMU_CSC_KRB_0,CMU Color Space Conversion Matrix (KRB)"
|
|
hexmask.long.word 0x18 0.--9. 1. " KRB ,KRB"
|
|
line.long 0x1C "CMU_CSC_KGB_0,CMU Color Space Conversion Matrix (KGB)"
|
|
hexmask.long.word 0x1c 0.--9. 1. " KGB ,KGB"
|
|
line.long 0x20 "CMU_CSC_KBB_0,CMU Color Space Conversion Matrix (KBB)"
|
|
hexmask.long.word 0x20 0.--9. 1. " KBB ,KBB"
|
|
group.long 0xCCC++0x03
|
|
line.long 0x00 "CMU_LUT_MASK_0,CMU LUT Mask"
|
|
bitfld.long 0x00 8.--9. " LUT2_WR_MASK ,Color channel write mask" "All,Red,Green,Blue"
|
|
bitfld.long 0x00 0.--1. " LUT1_WR_MASK ,Color channel write mask" "All,Red,Green,Blue"
|
|
group.long 0xCD8++0x07
|
|
line.long 0x00 "CMU_LUT1_0,CMU LUT1"
|
|
hexmask.long.word 0x00 16.--27. 1. " LUT1_DATA ,LUT1 DATA"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LUT1_ADDR ,LUT1 ADDR"
|
|
line.long 0x04 "CMU_LUT2_0,CMU LUT2"
|
|
hexmask.long.byte 0x04 16.--23. 1. " LUT2_DATA ,LUT2 DATA"
|
|
hexmask.long.word 0x04 0.--9. 1. " LUT2_ADDR ,LUT2 ADDR"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long 0xCF8++0x63
|
|
line.long 0x00 "DSC_TOP_CTL_0,DSC_TOP_CTL_0"
|
|
hexmask.long.word 0x00 4.--19. 1. " DSC_TIMEOUT_COUNTER ,Timeout counter"
|
|
bitfld.long 0x00 3. " DSC_AUTO_RESET ,Auto reset" "No reset,Reset"
|
|
bitfld.long 0x00 2. " DSC_SLCG_OVERRIDE ,SLCG override" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DSC_ENABLE ,Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DSC_SOFT_RESET ,Soft reset" "No reset,Reset"
|
|
line.long 0x04 "DSC_DELAY_0,DSC_DELAY_0"
|
|
hexmask.long.word 0x04 0.--15. 1. " DSC_OUTPUT_DELAY ,Delay"
|
|
line.long 0x08 "DSC_COMMON_CTL_0,DSC_COMMON_CTL_0"
|
|
hexmask.long.word 0x08 16.--31. 1. " DSC_CHUNK_SIZE ,Chunk size"
|
|
bitfld.long 0x08 10. " DSC_BLOCK_PRED_ENABLE ,DSC_BLOCK_PRED_ENABLE" "Disabled,Enabled"
|
|
hexmask.long.word 0x08 0.--9. 1. " DSC_BITS_PER_PIXEL ,Bits per pixel"
|
|
line.long 0x0C "DSC_SLICE_INFO_0,DSC_SLICE_INFO_0"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSC_SLICE_HEIGHT ,Slice height in pixels"
|
|
hexmask.long.word 0x0C 0.--15. 1. " DSC_SLICE_WIDTH ,Slice width in pixels"
|
|
line.long 0x10 "DSC_RC_DELAY_INFO_0,DSC_RC_DELAY_INFO_0"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSC_INITIAL_DEC_DELAY ,Number of pixels to delay the VLD"
|
|
hexmask.long.word 0x10 0.--9. 1. " DSC_INITIAL_XMIT_DELAY ,Number of pixels to delay the initial transmission"
|
|
line.long 0x14 "DSC_RC_SCALE_INFO_0,DSC_RC_SCALE_INFO_0"
|
|
hexmask.long.word 0x14 6.--21. 1. " DSC_SCALE_DECR_INTERVAL ,Decrement scale factor every scale_decr_interval group"
|
|
bitfld.long 0x14 0.--5. " DSC_INITIAL_SCALE_VALUE ,Initial value for scale factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x18 "DSC_RC_SCALE_INFO_2_0,DSC_RC_SCALE_INFO_2_0"
|
|
hexmask.long.word 0x18 0.--15. 1. " DSC_SCALE_INCR_INTERVAL ,Increment scale factor every scale_incr_interval group"
|
|
line.long 0x1C "DSC_RC_BPGOFF_INFO_0,DSC_RC_BPGOFF_INFO_0"
|
|
hexmask.long.word 0x1C 16.--31. 1. " DSC_RC_BPGOFF_INFO_0 ,BPG offset used to enforce slice bit constraint"
|
|
hexmask.long.word 0x1C 0.--15. 1. " DSC_NFL_BPG_OFFSET ,Non-first line BPG offset to use"
|
|
line.long 0x20 "DSC_RC_OFFSET_INFO_0,DSC_RC_OFFSET_INFO_0"
|
|
hexmask.long.word 0x20 16.--31. 1. " DSC_FINAL_OFFSET ,Final RC linear transformation offset value"
|
|
hexmask.long.word 0x20 1.--15. 1. " DSC_INITIAL_OFFSET ,Value to use for RC model offset at slice start"
|
|
line.long 0x24 "DSC_RC_FLATNESS_INFO_0,DSC_RC_FLATNESS_INFO_0"
|
|
hexmask.long.byte 0x24 10.--14. 0x4 " DSC_FIRST_LINE_BPG_OFFS ,BPG offset to use for first line of the slice"
|
|
bitfld.long 0x24 5.--9. " DSC_FLATNESS_MAX_QP ,Maximum QP where flatness information is sent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x24 0.--4. " DSC_FLATNESS_MIN_QP ,Minimum QP where flatness information is sent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x28 "DSC_RC_PARAM_SET_0,DSC_RC_PARAM_SET_0"
|
|
hexmask.long.byte 0x28 18.--21. 0x4 " DSC_RC_TGT_OFFSET_LO ,Offset to BPG used by RC to determine QP adjustment"
|
|
hexmask.long.byte 0x28 14.--17. 0x40 " DSC_RC_TGT_OFFSET_HI ,Offset to BPG used by RC to determine QP adjustment"
|
|
bitfld.long 0x28 9.--13. " DSC_RC_QUANT_INCR_LIMIT1 ,Slow down incrementing once the range reaches this value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x28 4.--8. " DSC_RC_QUANT_INCR_LIMIT0 ,Slow down incrementing once the range reaches this value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x28 0.--3. " DSC_RC_EDGE_FACTOR ,Factor to determine if an edge is present based on the bits produced" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x2C "DSC_RC_BUF_THRESH0_0,DC_COM_DSC_RC_BUF_THRESH0_0"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " DSC_RC_BUF_THRESH1 ,Threshold1 defining the buffer ranges"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " DSC_RC_BUF_THRESH0 ,Threshold0 defining the buffer ranges"
|
|
hexmask.long.word 0x2C 0.--15. 1. " DSC_RC_MODEL_SIZE ,Total size of RC model"
|
|
line.long 0x30 "DSC_RC_BUF_THRESH1_0,DC_COM_DSC_RC_BUF_THRESH1_0"
|
|
hexmask.long.byte 0x30 24.--31. 1. " DSC_RC_BUF_THRESH5 ,Threshold5 defining the buffer ranges"
|
|
hexmask.long.byte 0x30 16.--23. 1. " DSC_RC_BUF_THRESH4 ,Threshold4 defining the buffer ranges"
|
|
hexmask.long.byte 0x30 8.--15. 1. " DSC_RC_BUF_THRESH3 ,Threshold3 defining the buffer ranges"
|
|
textline " "
|
|
hexmask.long.byte 0x30 0.--7. 1. " DSC_RC_BUF_THRESH2 ,Threshold2 defining the buffer ranges"
|
|
line.long 0x34 "DSC_RC_BUF_THRESH2_0,DSC_RC_BUF_THRESH2_0"
|
|
hexmask.long.byte 0x34 24.--31. 1. " DSC_RC_BUF_THRESH9 ,Threshold9 defining the buffer ranges"
|
|
hexmask.long.byte 0x34 16.--23. 1. " DSC_RC_BUF_THRESH8 ,Threshold8 defining the buffer ranges"
|
|
hexmask.long.byte 0x34 8.--15. 1. " DSC_RC_BUF_THRESH7 ,Threshold7 defining the buffer ranges"
|
|
textline " "
|
|
hexmask.long.byte 0x34 0.--7. 1. " DSC_RC_BUF_THRESH6 ,Threshold6 defining the buffer ranges"
|
|
line.long 0x38 "DSC_RC_BUF_THRESH3_0,DSC_RC_BUF_THRESH3_0"
|
|
hexmask.long.byte 0x38 24.--31. 1. " DSC_RC_BUF_THRESH13 ,Threshold13 defining the buffer ranges"
|
|
hexmask.long.byte 0x38 16.--23. 1. " DSC_RC_BUF_THRESH12 ,Threshold12 defining the buffer ranges"
|
|
hexmask.long.byte 0x38 8.--15. 1. " DSC_RC_BUF_THRESH11 ,Threshold11 defining the buffer ranges"
|
|
textline " "
|
|
hexmask.long.byte 0x38 0.--7. 1. " DSC_RC_BUF_THRESH10 ,Threshold10 defining the buffer ranges"
|
|
line.long 0x3C "DSC_RC_RANGE_CFG0_0,DSC_RC_RANGE_CFG0_0"
|
|
hexmask.long.word 0x3C 16.--31. 1. " DSC_RC_RANGE_PARAM1 ,Parameters for RC range1"
|
|
hexmask.long.word 0x3C 0.--15. 1. " DSC_RC_RANGE_PARAM0 ,Parameters for RC range0"
|
|
line.long 0x40 "DSC_RC_RANGE_CFG1_0,DSC_RC_RANGE_CFG1_0"
|
|
hexmask.long.word 0x40 16.--31. 1. " DSC_RC_RANGE_PARAM3 ,Parameters for RC range3"
|
|
hexmask.long.word 0x40 0.--15. 1. " DSC_RC_RANGE_PARAM2 ,Parameters for RC range2"
|
|
line.long 0x44 "DSC_RC_RANGE_CFG2_0,DSC_RC_RANGE_CFG2_0"
|
|
hexmask.long.word 0x44 16.--31. 1. " DSC_RC_RANGE_PARAM5 ,Parameters for RC range5"
|
|
hexmask.long.word 0x44 0.--15. 1. " DSC_RC_RANGE_PARAM4 ,Parameters for RC range4"
|
|
line.long 0x48 "DSC_RC_RANGE_CFG3_0,DSC_RC_RANGE_CFG3_0"
|
|
hexmask.long.word 0x48 16.--31. 1. " DSC_RC_RANGE_PARAM7 ,Parameters for RC range7"
|
|
hexmask.long.word 0x48 0.--15. 1. " DSC_RC_RANGE_PARAM6 ,Parameters for RC range6"
|
|
line.long 0x4C "DSC_RC_RANGE_CFG4_0,DSC_RC_RANGE_CFG4_0"
|
|
hexmask.long.word 0x4C 16.--31. 1. " DSC_RC_RANGE_PARAM9 ,Parameters for RC range9"
|
|
hexmask.long.word 0x4C 0.--15. 1. " DSC_RC_RANGE_PARAM8 ,Parameters for RC range8"
|
|
line.long 0x50 "DSC_RC_RANGE_CFG5_0,DSC_RC_RANGE_CFG5_0"
|
|
hexmask.long.word 0x50 16.--31. 1. " DSC_RC_RANGE_PARAM11 ,Parameters for RC range11"
|
|
hexmask.long.word 0x50 0.--15. 1. " DSC_RC_RANGE_PARAM10 ,Parameters for RC range10"
|
|
line.long 0x54 "DSC_RC_RANGE_CFG6_0,DSC_RC_RANGE_CFG6_0"
|
|
hexmask.long.word 0x54 16.--31. 1. " DSC_RC_RANGE_PARAM13 ,Parameters for RC range13"
|
|
hexmask.long.word 0x54 0.--15. 1. " DSC_RC_RANGE_PARAM12 ,Parameters for RC range12"
|
|
line.long 0x58 "DSC_RC_RANGE_CFG7_0,DSC_RC_RANGE_CFG7_0"
|
|
hexmask.long.word 0x58 16.--31. 1. " DSC_RC_RANGE_PARAM15 ,Parameters for RC range15"
|
|
hexmask.long.word 0x58 0.--15. 1. " DSC_RC_RANGE_PARAM14 ,Parameters for RC range14"
|
|
line.long 0x5C "DSC_UNIT_SET_0,DSC_UNIT_SET_0"
|
|
bitfld.long 0x5C 2. " DSC_LINEBUF_DEPTH ,Line buffer depth" "9 bits,8 bits"
|
|
bitfld.long 0x5C 0.--1. " DSC_SLICE_NUM_MINUS1_IN_LINE ,The slice number in the line" "1,2,3,4"
|
|
line.long 0x60 "DSC_CRC_CONTROL_0,DSC_CRC_CONTROL_0"
|
|
bitfld.long 0x60 1. " DSC_CRC_ALWAYS ,CRC ALWAYS" "Disabled,Enabled"
|
|
bitfld.long 0x60 0. " DSC_CRC_ENABLE ,CRC Enable" "Disabled,Enabled"
|
|
rgroup.long 0xD5C++0x0B
|
|
line.long 0x00 "DSC_CRC_CHECKSUM_0,CRC Checksum latched"
|
|
line.long 0x04 "DSC_STATUS_0,DC_COM_DSC_STATUS_0"
|
|
bitfld.long 0x04 16.--17. " DSC_STATUS_SLICEID ,Slice ID" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--15. 1. " DSC_STATUS_HINDEX ,Horizontal index"
|
|
line.long 0x08 "DSC_STATUS_2_0,DSC_STATUS_2_0"
|
|
bitfld.long 0x08 16. " DSC_STATUS_BUSY ,Busy" "Not busy,Busy"
|
|
hexmask.long.word 0x08 0.--15. 1. " DSC_STATUS_VINDEX ,Vertical index"
|
|
endif
|
|
tree.end
|
|
width 35.
|
|
tree "Display DISP Registers"
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "DISP_SIGNAL_OPTIONS0_0,Display Signal Options 0"
|
|
bitfld.long 0x00 26. " M1_ENABLE ,M1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " M0_ENABLE ,M0 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " V_PULSE3_ENABLE ,V Pulse 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " V_PULSE2_ENABLE ,V Pulse 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " V_PULSE1_ENABLE ,V Pulse 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " V_PULSE0_ENABLE ,V Pulse 0 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " H_PULSE2_ENABLE ,H Pulse 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " H_PULSE1_ENABLE ,H Pulse 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " H_PULSE0_ENABLE ,H Pulse 0 Enable" "Disabled,Enabled"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "DISP_WIN_OPTIONS_0,Display Window Options"
|
|
sif CPUIS("TEGRAK1")
|
|
bitfld.long 0x00 30. " HDMI_ENABLE ,HDMI interface" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " DSI_ENABLE ,MIPI Display Serial Interface Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif CPUIS("TEGRAX1")
|
|
bitfld.long 0x00 27. " SOR1_TIMING_CYA ,HDMI expects a delayed vsync and preamble compared to DP" "DP,HDMI"
|
|
bitfld.long 0x00 26. " SOR1_ENABLE ,SOR1 interface - DP/HDMI" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " SOR_ENABLE ,SOR Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CURSOR_ENABLE ,Cursor Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x1014++0x1B
|
|
line.long 0x00 "DISP_TIMING_OPTIONS_0,Display Timing Options"
|
|
hexmask.long.word 0x00 0.--12. 1. " VSYNC_H_POSITION ,VSYNC Horizontal Position"
|
|
line.long 0x04 "REF_TO_SYNC_0,H/V Reference to Sync"
|
|
hexmask.long.word 0x04 16.--28. 1. " V_REF_TO_SYNC ,V reference to VSYNC"
|
|
hexmask.long.word 0x04 0.--12. 1. " H_REF_TO_SYNC ,H reference to HSYNC"
|
|
line.long 0x08 "SYNC_WIDTH_0,H/V SYNC Pulse Width"
|
|
hexmask.long.word 0x08 16.--28. 1. " V_SYNC_WIDTH ,VSYNC pulse width"
|
|
hexmask.long.word 0x08 0.--12. 1. " H_SYNC_WIDTH ,HSYNC pulse width"
|
|
line.long 0x0C "BACK_PORCH_0,H/V Back Porch"
|
|
hexmask.long.word 0x0C 16.--28. 1. " V_BACK_PORCH ,V back porch"
|
|
hexmask.long.word 0x0C 0.--12. 1. " H_BACK_PORCH ,H back porch"
|
|
line.long 0x10 "DISP_ACTIVE_0,H/V Display Active width"
|
|
hexmask.long.word 0x10 16.--28. 1. " V_DISP_ACTIVE ,V display active width"
|
|
hexmask.long.word 0x10 0.--12. 1. " H_DISP_ACTIVE ,H display active width"
|
|
line.long 0x14 "FRONT_PORCH_0,H/V Front Porch"
|
|
hexmask.long.word 0x14 16.--28. 1. " V_FRONT_PORCH ,VSYNC front porch"
|
|
hexmask.long.word 0x14 0.--12. 1. " H_FRONT_PORCH ,VSYNC front porch"
|
|
line.long 0x18 "H_PULSE0_CONTROL_0,H Pulse 0 Control"
|
|
bitfld.long 0x18 8.--11. " H_PULSE0_LAST ,H Pulse 0 Last point" "Start A,End A,Start B,End B,Start C,End C,Start D,End D,?..."
|
|
bitfld.long 0x18 6.--7. " H_PULSE0_V_QUAL ,H Pulse 0 Vertical Qualifier" "Always,,V active,V active+1"
|
|
textline " "
|
|
bitfld.long 0x18 4. " H_PULSE0_POLARITY ,H Pulse 0 Polarity" "High,Low"
|
|
bitfld.long 0x18 3. " H_PULSE0_MODE ,H Pulse 0 Mode" "Normal,Single-clock"
|
|
group.long 0x1030++0x03
|
|
line.long 0x00 "H_PULSE0_POSITION_A_0,H Pulse 0 Position A"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE0_END_A ,H Pulse 0 End A"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE0_START_A ,H Pulse 0 Start A"
|
|
group.long 0x1034++0x03
|
|
line.long 0x00 "H_PULSE0_POSITION_B_0,H Pulse 0 Position B"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE0_END_B ,H Pulse 0 End B"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE0_START_B ,H Pulse 0 Start B"
|
|
group.long 0x1038++0x03
|
|
line.long 0x00 "H_PULSE0_POSITION_C_0,H Pulse 0 Position C"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE0_END_C ,H Pulse 0 End C"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE0_START_C ,H Pulse 0 Start C"
|
|
group.long 0x103C++0x03
|
|
line.long 0x00 "H_PULSE0_POSITION_D_0,H Pulse 0 Position D"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE0_END_D ,H Pulse 0 End D"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE0_START_D ,H Pulse 0 Start D"
|
|
group.long 0x1040++0x03
|
|
line.long 0x00 "H_PULSE1_CONTROL_0,H Pulse 1 Control"
|
|
bitfld.long 0x00 8.--11. " H_PULSE1_LAST ,H Pulse 1 Last point" "Start A,End A,Start B,End B,Start C,End C,Start D,End D,?..."
|
|
bitfld.long 0x00 6.--7. " H_PULSE1_V_QUAL ,H Pulse 1 Vertical Qualifier" "Always,,V active,V active+1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " H_PULSE1_POLARITY ,H Pulse 1 Polarity" "High,Low"
|
|
bitfld.long 0x00 3. " H_PULSE1_MODE ,H Pulse 1 Mode" "Normal,Single-clock"
|
|
group.long 0x1044++0x03
|
|
line.long 0x00 "H_PULSE1_POSITION_A_0,H Pulse 1 Position A"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE1_END_A ,H Pulse 1 End A"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE1_START_A ,H Pulse 1 Start A"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "H_PULSE1_POSITION_B_0,H Pulse 1 Position B"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE1_END_B ,H Pulse 1 End B"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE1_START_B ,H Pulse 1 Start B"
|
|
group.long 0x104C++0x03
|
|
line.long 0x00 "H_PULSE1_POSITION_C_0,H Pulse 1 Position C"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE1_END_C ,H Pulse 1 End C"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE1_START_C ,H Pulse 1 Start C"
|
|
group.long 0x1050++0x03
|
|
line.long 0x00 "H_PULSE1_POSITION_D_0,H Pulse 1 Position D"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE1_END_D ,H Pulse 1 End D"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE1_START_D ,H Pulse 1 Start D"
|
|
group.long 0x1054++0x03
|
|
line.long 0x00 "H_PULSE2_CONTROL_0,H Pulse 2 Control"
|
|
bitfld.long 0x00 8.--11. " H_PULSE2_LAST ,H Pulse 2 Last point" "Start A,End A,Start B,End B,Start C,End C,Start D,End D,?..."
|
|
bitfld.long 0x00 6.--7. " H_PULSE2_V_QUAL ,H Pulse 2 Vertical Qualifier" "Always,,V active,V active+1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " H_PULSE2_POLARITY ,H Pulse 2 Polarity" "High,Low"
|
|
bitfld.long 0x00 3. " H_PULSE2_MODE ,H Pulse 2 Mode" "Normal,Single-clock"
|
|
group.long 0x1058++0x03
|
|
line.long 0x00 "H_PULSE2_POSITION_A_0,H Pulse 2 Position A"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE2_END_A ,H Pulse 2 End A"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE2_START_A ,H Pulse 2 Start A"
|
|
group.long 0x105C++0x03
|
|
line.long 0x00 "H_PULSE2_POSITION_B_0,H Pulse 2 Position B"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE2_END_B ,H Pulse 2 End B"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE2_START_B ,H Pulse 2 Start B"
|
|
group.long 0x1060++0x03
|
|
line.long 0x00 "H_PULSE2_POSITION_C_0,H Pulse 2 Position C"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE2_END_C ,H Pulse 2 End C"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE2_START_C ,H Pulse 2 Start C"
|
|
group.long 0x1064++0x03
|
|
line.long 0x00 "H_PULSE2_POSITION_D_0,H Pulse 2 Position D"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE2_END_D ,H Pulse 2 End D"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE2_START_D ,H Pulse 2 Start D"
|
|
group.long 0x1068++0x03
|
|
line.long 0x00 "V_PULSE0_CONTROL_0,V Pulse 0 Control"
|
|
hexmask.long.word 0x00 16.--28. 1. " V_PULSE0_H_POSITION ,V Pulse 0 Horizontal Position"
|
|
bitfld.long 0x00 8.--11. " V_PULSE0_LAST ,V Pulse 0 Last point" "Start A,End A,Start B,End B,Start C,End C,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " V_PULSE0_DELAY ,V Pulse 0 Delay" "No delay,1-line delay,2-line delay,?..."
|
|
bitfld.long 0x00 4. " V_PULSE0_POLARITY ,V Pulse 0 Polarity" "High,Low"
|
|
group.long 0x106C++0x03
|
|
line.long 0x00 "V_PULSE0_POSITION_A_0,H Pulse 0 Position A"
|
|
hexmask.long.word 0x00 16.--28. 1. " V_PULSE0_END_A ,V Pulse 0 End A"
|
|
hexmask.long.word 0x00 0.--12. 1. " V_PULSE0_START_A ,V Pulse 0 Start A"
|
|
group.long 0x1070++0x03
|
|
line.long 0x00 "V_PULSE0_POSITION_B_0,H Pulse 0 Position B"
|
|
hexmask.long.word 0x00 16.--28. 1. " V_PULSE0_END_B ,V Pulse 0 End B"
|
|
hexmask.long.word 0x00 0.--12. 1. " V_PULSE0_START_B ,V Pulse 0 Start B"
|
|
group.long 0x1074++0x03
|
|
line.long 0x00 "V_PULSE0_POSITION_C_0,H Pulse 0 Position C"
|
|
hexmask.long.word 0x00 16.--28. 1. " V_PULSE0_END_C ,V Pulse 0 End C"
|
|
hexmask.long.word 0x00 0.--12. 1. " V_PULSE0_START_C ,V Pulse 0 Start C"
|
|
group.long 0x1078++0x03
|
|
line.long 0x00 "V_PULSE1_CONTROL_0,V Pulse 1 Control"
|
|
hexmask.long.word 0x00 16.--28. 1. " V_PULSE1_H_POSITION ,V Pulse 1 Horizontal Position"
|
|
bitfld.long 0x00 8.--11. " V_PULSE1_LAST ,V Pulse 1 Last point" "Start A,End A,Start B,End B,Start C,End C,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " V_PULSE1_DELAY ,V Pulse 1 Delay" "No delay,1-line delay,2-line delay,?..."
|
|
bitfld.long 0x00 4. " V_PULSE1_POLARITY ,V Pulse 1 Polarity" "High,Low"
|
|
group.long 0x107C++0x03
|
|
line.long 0x00 "V_PULSE1_POSITION_A_0,H Pulse 1 Position A"
|
|
hexmask.long.word 0x00 16.--28. 1. " V_PULSE1_END_A ,V Pulse 1 End A"
|
|
hexmask.long.word 0x00 0.--12. 1. " V_PULSE1_START_A ,V Pulse 1 Start A"
|
|
group.long 0x1080++0x03
|
|
line.long 0x00 "V_PULSE1_POSITION_B_0,H Pulse 1 Position B"
|
|
hexmask.long.word 0x00 16.--28. 1. " V_PULSE1_END_B ,V Pulse 1 End B"
|
|
hexmask.long.word 0x00 0.--12. 1. " V_PULSE1_START_B ,V Pulse 1 Start B"
|
|
group.long 0x1084++0x03
|
|
line.long 0x00 "V_PULSE1_POSITION_C_0,H Pulse 1 Position C"
|
|
hexmask.long.word 0x00 16.--28. 1. " V_PULSE1_END_C ,V Pulse 1 End C"
|
|
hexmask.long.word 0x00 0.--12. 1. " V_PULSE1_START_C ,V Pulse 1 Start C"
|
|
group.long 0x1088++0x0F
|
|
line.long 0x00 "V_PULSE2_CONTROL_0,V Pulse 2 Control"
|
|
hexmask.long.word 0x00 16.--28. 1. " V_PULSE2_H_POSITION ,V Pulse 2 Horizontal Position"
|
|
bitfld.long 0x00 8. " V_PULSE2_LAST ,V Pulse 2 Last point" "Start A,End A"
|
|
textline " "
|
|
bitfld.long 0x00 4. " V_PULSE2_POLARITY ,V Pulse 2 Polarity" "High,Low"
|
|
line.long 0x04 "V_PULSE2_POSITION_A_0,H Pulse 2 Position A"
|
|
hexmask.long.word 0x04 16.--28. 1. " V_PULSE2_END_A ,V Pulse 2 End A"
|
|
hexmask.long.word 0x04 0.--12. 1. " V_PULSE2_START_A ,V Pulse 2 Start A"
|
|
line.long 0x08 "V_PULSE3_CONTROL_0,V Pulse 3 Control"
|
|
hexmask.long.word 0x08 16.--28. 1. " V_PULSE3_H_POSITION ,V Pulse 3 Horizontal Position"
|
|
bitfld.long 0x08 8. " V_PULSE3_LAST ,V Pulse 3 Last point" "Start A,End A"
|
|
textline " "
|
|
bitfld.long 0x08 4. " V_PULSE3_POLARITY ,V Pulse 3 Polarity" "High,Low"
|
|
line.long 0x0C "V_PULSE3_POSITION_A_0,H Pulse 3 Position A"
|
|
hexmask.long.word 0x0C 16.--28. 1. " V_PULSE3_END_A ,V Pulse 3 End A"
|
|
hexmask.long.word 0x0C 0.--12. 1. " V_PULSE3_START_A ,V Pulse 3 Start A"
|
|
textline " "
|
|
group.long 0x10B8++0x07
|
|
line.long 0x00 "DISP_CLOCK_CONTROL_0,Display Clock Control"
|
|
bitfld.long 0x00 8.--11. " PIXEL_CLK_DIVIDER ,Pixel Clock Divider" "/1,/1.5,/2,/3,/4,/6,/8,/9,/12,/16,/18,/24,/13,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SHIFT_CLK_DIVIDER ,Shift Clock Divider"
|
|
line.long 0x04 "DISP_INTERFACE_CONTROL_0,Display Interface Control"
|
|
bitfld.long 0x04 9. " DISP_DATA_ORDER ,Display Data Order" "RED_BLUE,BLUE_RED"
|
|
bitfld.long 0x04 8. " DISP_DATA_ALIGNMENT ,Display Data Alignment" "MSB,LSB"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " DISP_DATA_FORMAT ,Display Data Format Pixel Clock Divider" "DF1P1C,DF1P2C24B,DF1P2C18B,DF1P2C16B,DF1S,DF2S,DF3S,DFSPI,DF1P3C24B,DF2P1C18B,DFDUAL1P1C18B,?..."
|
|
group.long 0x10C0++0x03
|
|
line.long 0x00 "DISP_COLOR_CONTROL_0,Display Color Control"
|
|
sif CPUIS("TEGRAK1")
|
|
bitfld.long 0x00 27. " LCD_MD3 ,LCD Mode 3 signal" "Low,High"
|
|
bitfld.long 0x00 26. " LCD_MD2 ,LCD Mode 2 signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LCD_MD1 ,LCD Mode 1 signal" "Low,High"
|
|
bitfld.long 0x00 24. " LCD_MD0 ,LCD Mode 0 signal" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CMU_ENABLE ,CMU_ENABLE" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " NON_BASE_COLOR ,Non Base Color" "Zeros,Ones"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BLANK_COLOR ,Blank Color" "Zeros,Ones"
|
|
bitfld.long 0x00 16. " DISP_COLOR_SWAP ,Display Color Swap" "RGB,BGR"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " ORD_DITHER_ROTATION ,Ordered Dither Frame Rotation" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DITHER_CONTROL ,Dither Control" "Disabled,,Ordered,Temporal"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TEMPORAL_DITHER_PHASE ,Temporal dither LFSR phase control" "Previous val,34'H3FFFFFFFF,34'H155555555,34'H2AAAAAAAA"
|
|
bitfld.long 0x00 0.--3. " BASE_COLOR_SIZE ,Display Base Color Size" "BASE666,BASE111,BASE222,BASE333,BASE444,BASE555,BASE565,BASE332,BASE888,?..."
|
|
textline " "
|
|
group.long 0x10D8++0x0F
|
|
line.long 0x00 "COLOR_KEY0_LOWER_0,Color Key 0 Lower value"
|
|
hexmask.long.byte 0x00 24.--31. 1. " COLOR_KEY0_L_A ,Color Key 0 Alpha (0xFF) Lower value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " COLOR_KEY0_L_B ,Color Key 0 Blue (U) Lower value"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " COLOR_KEY0_L_G ,Color Key 0 Green (Y) Lower value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " COLOR_KEY0_L_R ,Color Key 0 Red (V) Lower value"
|
|
line.long 0x04 "COLOR_KEY0_UPPER_0,Color Key 0 Upper value"
|
|
hexmask.long.byte 0x04 24.--31. 1. " COLOR_KEY0_U_A ,Color Key 0 Alpha (0xFF) Upper value"
|
|
hexmask.long.byte 0x04 16.--23. 1. " COLOR_KEY0_U_B ,Color Key 0 Blue (U) Upper value"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " COLOR_KEY0_U_G ,Color Key 0 Green (Y) Upper value"
|
|
hexmask.long.byte 0x04 0.--7. 1. " COLOR_KEY0_U_R ,Color Key 0 Red (V) Upper value"
|
|
line.long 0x08 "COLOR_KEY1_LOWER_0,Color Key 1 Lower value"
|
|
hexmask.long.byte 0x08 24.--31. 1. " COLOR_KEY1_L_A ,Color Key 1 Alpha (0xFF) Lower value"
|
|
hexmask.long.byte 0x08 16.--23. 1. " COLOR_KEY1_L_B ,Color Key 1 Blue (U) Lower value"
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " COLOR_KEY1_L_G ,Color Key 1 Green (Y) Lower value"
|
|
hexmask.long.byte 0x08 0.--7. 1. " COLOR_KEY1_L_R ,Color Key 1 Red (V) Lower value"
|
|
line.long 0x0C "COLOR_KEY1_UPPER_0,Color Key 1 Upper value"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " COLOR_KEY1_U_A ,Color Key 1 Alpha (0xFF) Upper value"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " COLOR_KEY1_U_B ,Color Key 1 Blue (U) Upper value"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 8.--15. 1. " COLOR_KEY1_U_G ,Color Key 1 Green (Y) Upper value"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " COLOR_KEY1_U_R ,Color Key 1 Red (V) Upper value"
|
|
group.long 0x10F0++0x0B
|
|
line.long 0x00 "CURSOR_FOREGROUND_0,Cursor Foreground color"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CURSOR_FOREGROUND_B ,Cursor Blue Foreground Color"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CURSOR_FOREGROUND_G ,Cursor Green Foreground Color"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CURSOR_FOREGROUND_R ,Cursor Red Foreground Color"
|
|
line.long 0x04 "CURSOR_BACKGROUND_0,Cursor Background color"
|
|
hexmask.long.byte 0x04 16.--23. 1. " CURSOR_BACKGROUND_B ,Cursor Blue Background Color"
|
|
hexmask.long.byte 0x04 8.--15. 1. " CURSOR_BACKGROUND_G ,Cursor Green Background Color"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " CURSOR_BACKGROUND_R ,Cursor Red Background Color"
|
|
textline " "
|
|
line.long 0x08 "CURSOR_START_ADDR_0,Cursor Start Address"
|
|
bitfld.long 0x08 28.--29. " CURSOR_CLIPPING ,Cursor Clipping Select" "Display,Window A,Window B,Window C"
|
|
bitfld.long 0x08 24.--25. " CURSOR_SIZE ,Cursor Size" "C32x32,C64x64,C128X128,C256X256"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--21. 1. " CURSOR_START_ADDR ,Cursor Start Address bits"
|
|
sif CPUIS("TEGRAK1")
|
|
group.long 0x10FC++0x03
|
|
line.long 0x00 "CURSOR_START_ADDR_NS_0,Shadow of Cursor Start Address"
|
|
bitfld.long 0x00 28.--29. " CURSOR_CLIPPING_NS ,Cursor Clipping Select" "Display,Window A,Window B,Window C"
|
|
bitfld.long 0x00 24.--25. " CURSOR_SIZE_NS ,Cursor Size" "32x32,64x64,C128X128,C256X256"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--21. 1. " CURSOR_START_ADDR_NS ,Cursor Start Address bits"
|
|
endif
|
|
group.long 0x1100++0x03
|
|
line.long 0x00 "CURSOR_POSITION_0,Cursor Position"
|
|
hexmask.long.word 0x00 16.--29. 1. " V_CURSOR_POSITION ,V cursor position"
|
|
hexmask.long.word 0x00 0.--13. 1. " H_CURSOR_POSITION ,H cursor position"
|
|
sif CPUIS("TEGRAK1")
|
|
group.long 0x1104++0x03
|
|
line.long 0x00 "CURSOR_POSITION_NS_0,Shadow of Cursor Position"
|
|
hexmask.long.word 0x00 16.--29. 1. " V_CURSOR_POSITION_NS ,V cursor position"
|
|
hexmask.long.word 0x00 0.--13. 1. " H_CURSOR_POSITION_NS ,H cursor position"
|
|
endif
|
|
group.long 0x1200++0x03
|
|
line.long 0x00 "DC_MCCIF_FIFOCTRL_0,Memory Client Interface FIFO Control Register"
|
|
bitfld.long 0x00 20. " DC_RCLK_OVR_MODE ,DC_RCLK_OVERRIDE" "LEGACY,ON"
|
|
bitfld.long 0x00 19. " DC_WCLK_OVR_MODE ,DC_WCLK_OVERRIDE" "LEGACY,ON"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DC_CCLK_OVERRIDE ,DC_CCLK_OVERRIDE" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DC_RCLK_OVERRIDE ,DC_RCLK_OVERRIDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DC_WCLK_OVERRIDE ,DC_WCLK_OVERRIDE" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DC_MCCIF_RDCL_RDFAST ,DC_MCCIF_RDCL_RDFAST" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DC_MCCIF_WRMC_CLLE2X ,DC_MCCIF_WRMC_CLLE2X" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DC_MCCIF_RDMC_RDFAST ,DC_MCCIF_RDMC_RDFAST" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DC_MCCIF_WRCL_MCLE2X ,DC_MCCIF_WRCL_MCLE2X" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x1204++0x03
|
|
line.long 0x00 "MCCIF_DISPLAY0A_HYST_0,Memory Client Hysteresis Control Register"
|
|
eventfld.long 0x00 31. " CBR_DISPLAY0A2MC_HYST_EN ,CBR_DISPLAY0A2MC_HYST_EN" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--30. " CBR_DISPLAY0A2MC_HYST_REQ_TH ,CBR_DISPLAY0A2MC_HYST_REQ_TH" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CBR_DISPLAY0A2MC_HYST_TM ,CBR_DISPLAY0A2MC_HYST_TM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CBR_DISPLAY0A2MC_DHYST_TH ,CBR_DISPLAY0A2MC_DHYST_TH"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CBR_DISPLAY0A2MC_DHYST_TM ,CBR_DISPLAY0A2MC_DHYST_TM"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CBR_DISPLAY0A2MC_HYST_REQ_TM ,CBR_DISPLAY0A2MC_HYST_REQ_TM"
|
|
group.long 0x1208++0x03
|
|
line.long 0x00 "MCCIF_DISPLAY0B_HYST_0,Memory Client Hysteresis Control Register"
|
|
eventfld.long 0x00 31. " CBR_DISPLAY0B2MC_HYST_EN ,CBR_DISPLAY0B2MC_HYST_EN" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--30. " CBR_DISPLAY0B2MC_HYST_REQ_TH ,CBR_DISPLAY0B2MC_HYST_REQ_TH" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CBR_DISPLAY0B2MC_HYST_TM ,CBR_DISPLAY0B2MC_HYST_TM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CBR_DISPLAY0B2MC_DHYST_TH ,CBR_DISPLAY0B2MC_DHYST_TH"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CBR_DISPLAY0B2MC_DHYST_TM ,CBR_DISPLAY0B2MC_DHYST_TM"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CBR_DISPLAY0B2MC_HYST_REQ_TM ,CBR_DISPLAY0B2MC_HYST_REQ_TM"
|
|
group.long 0x120C++0x03
|
|
line.long 0x00 "MCCIF_DISPLAY0C_HYST_0,Memory Client Hysteresis Control Register"
|
|
eventfld.long 0x00 31. " CBR_DISPLAY0C2MC_HYST_EN ,CBR_DISPLAY0C2MC_HYST_EN" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--30. " CBR_DISPLAY0C2MC_HYST_REQ_TH ,CBR_DISPLAY0C2MC_HYST_REQ_TH" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CBR_DISPLAY0C2MC_HYST_TM ,CBR_DISPLAY0C2MC_HYST_TM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CBR_DISPLAY0C2MC_DHYST_TH ,CBR_DISPLAY0C2MC_DHYST_TH"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CBR_DISPLAY0C2MC_DHYST_TM ,CBR_DISPLAY0C2MC_DHYST_TM"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CBR_DISPLAY0C2MC_HYST_REQ_TM ,CBR_DISPLAY0C2MC_HYST_REQ_TM"
|
|
textline " "
|
|
group.long 0x1304++0x03
|
|
line.long 0x00 "DISP_MISC_CONTROL_0,Miscellaneous controls"
|
|
eventfld.long 0x00 1. " UF_LINE_FLUSH ,Enable underflow line flush" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PHASE_SHIFT_2P1C18B ,Enable phase shift for 2P1C format" "Disabled,Enabled"
|
|
group.long 0x1308++0x03
|
|
line.long 0x00 "SD_CONTROL_0,PRISM 3 Control"
|
|
bitfld.long 0x00 29.--30. " K_INIT_BIAS ,BIAS of the initial K bias MSB of count" "BIAS0,BIAS1,BIAS_HALF,BIAS_MSB"
|
|
bitfld.long 0x00 28. " SD_FRAME_PROC_CONTROL ,Run per-frame processing" "VSYNC,VPULSE2"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SMOOTH_K_ENABLE ,Enable maximum raw K change per frame is limited to SMOOTH_K_INCR" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " SOFT_CLIPPING_ENABLE ,Enable enhancement gain is reduced for pixels above SOFT_CLIPPING_THRESHOLD level" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SD_WINDOW_ENABLE ,Enable constrain histogram to a rectangular subset of display" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " K_LIMIT_ENABLE ,Enable Max K is taken from K_LIMIT register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SD_CORRECTION_MODE ,Determines which K values are used to modify the pixel values" "AUTO_CORRECT,MANUAL"
|
|
bitfld.long 0x00 10. " SD_ONE_SHOT ,Enables the PRISM 3 function for one frame only" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " HW_UPDATE_DLY ,Determines the delay" "No delay,1 frame,2 frame,3 frame"
|
|
bitfld.long 0x00 5.--7. " AGGRESSIVENESS ,The aggressiveness level of the PRISM 3 algorithm" "0,1,2,3,4,5,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " BIN_WIDTH ,Width of the Histogram bins in quantization levels" "1,2,4,8"
|
|
bitfld.long 0x00 2. " USE_VID_LUMA ,Use Video Luminance control of luminance" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SD_ENABLE ,Enables the PRISM 3 Function" "Disabled,Enabled,ONE_SHOT,?..."
|
|
sif CPUIS("TEGRAX1")
|
|
group.long 0x130C++0x03
|
|
line.long 0x00 "SD_CSC_COEFF_0,SD_CSC_COEFF_0"
|
|
bitfld.long 0x00 20.--23. " B_COEFF ,Blue coefficient for luminance calculation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " G_COEFF ,Green coefficient for luminance calculation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " R_COEFF ,Red coefficient for luminance calculation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
group.long 0x1310++0x03
|
|
line.long 0x00 "SD_LUT_0,SD_LUT_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_LUT ,Blue Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G_LUT ,Green Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R_LUT ,Red Enhancement value (k) Look Up Table"
|
|
group.long 0x1314++0x03
|
|
line.long 0x00 "SD_LUT_1,SD_LUT_1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_LUT ,Blue Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G_LUT ,Green Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R_LUT ,Red Enhancement value (k) Look Up Table"
|
|
group.long 0x1318++0x03
|
|
line.long 0x00 "SD_LUT_2,SD_LUT_2"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_LUT ,Blue Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G_LUT ,Green Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R_LUT ,Red Enhancement value (k) Look Up Table"
|
|
group.long 0x131C++0x03
|
|
line.long 0x00 "SD_LUT_3,SD_LUT_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_LUT ,Blue Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G_LUT ,Green Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R_LUT ,Red Enhancement value (k) Look Up Table"
|
|
group.long 0x1320++0x03
|
|
line.long 0x00 "SD_LUT_4,SD_LUT_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_LUT ,Blue Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G_LUT ,Green Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R_LUT ,Red Enhancement value (k) Look Up Table"
|
|
group.long 0x1324++0x03
|
|
line.long 0x00 "SD_LUT_5,SD_LUT_5"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_LUT ,Blue Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G_LUT ,Green Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R_LUT ,Red Enhancement value (k) Look Up Table"
|
|
group.long 0x1328++0x03
|
|
line.long 0x00 "SD_LUT_6,SD_LUT_6"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_LUT ,Blue Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G_LUT ,Green Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R_LUT ,Red Enhancement value (k) Look Up Table"
|
|
group.long 0x132C++0x03
|
|
line.long 0x00 "SD_LUT_7,SD_LUT_7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_LUT ,Blue Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G_LUT ,Green Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R_LUT ,Red Enhancement value (k) Look Up Table"
|
|
group.long 0x1330++0x03
|
|
line.long 0x00 "SD_LUT_8,SD_LUT_8"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_LUT ,Blue Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G_LUT ,Green Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R_LUT ,Red Enhancement value (k) Look Up Table"
|
|
textline " "
|
|
group.long 0x1334++0x07
|
|
line.long 0x00 "SD_FLICKER_CONTROL_0,Flicker Reduction Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " THRESHOLD ,The amount by which the currently calculated enhancement value must deviate"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TIME_LIMIT ,Length of time - in frames - that the enhancement value must deviate"
|
|
line.long 0x04 "SD_PIXEL_COUNT_0,Status / debug register showing the total number of active pixels"
|
|
hexmask.long.word 0x04 0.--15. 1. " NUM_PIXELS ,Number of pixels in the preceding output frame"
|
|
textline " "
|
|
group.long 0x133C++0x03
|
|
line.long 0x00 "SD_HISTOGRAM_0,SD_HISTOGRAM_0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BIN_3 ,BIN_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BIN_2 ,BIN_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BIN_1 ,BIN_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BIN_0 ,BIN_0"
|
|
group.long 0x1340++0x03
|
|
line.long 0x00 "SD_HISTOGRAM_1,SD_HISTOGRAM_1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BIN_3 ,BIN_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BIN_2 ,BIN_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BIN_1 ,BIN_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BIN_0 ,BIN_0"
|
|
group.long 0x1344++0x03
|
|
line.long 0x00 "SD_HISTOGRAM_2,SD_HISTOGRAM_2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BIN_3 ,BIN_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BIN_2 ,BIN_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BIN_1 ,BIN_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BIN_0 ,BIN_0"
|
|
group.long 0x1348++0x03
|
|
line.long 0x00 "SD_HISTOGRAM_3,SD_HISTOGRAM_3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BIN_3 ,BIN_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BIN_2 ,BIN_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BIN_1 ,BIN_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BIN_0 ,BIN_0"
|
|
group.long 0x134C++0x03
|
|
line.long 0x00 "SD_HISTOGRAM_4,SD_HISTOGRAM_4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BIN_3 ,BIN_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BIN_2 ,BIN_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BIN_1 ,BIN_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BIN_0 ,BIN_0"
|
|
group.long 0x1350++0x03
|
|
line.long 0x00 "SD_HISTOGRAM_5,SD_HISTOGRAM_5"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BIN_3 ,BIN_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BIN_2 ,BIN_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BIN_1 ,BIN_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BIN_0 ,BIN_0"
|
|
group.long 0x1354++0x03
|
|
line.long 0x00 "SD_HISTOGRAM_6,SD_HISTOGRAM_6"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BIN_3 ,BIN_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BIN_2 ,BIN_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BIN_1 ,BIN_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BIN_0 ,BIN_0"
|
|
group.long 0x1358++0x03
|
|
line.long 0x00 "SD_HISTOGRAM_7,SD_HISTOGRAM_7"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BIN_3 ,BIN_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BIN_2 ,BIN_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BIN_1 ,BIN_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BIN_0 ,BIN_0"
|
|
textline " "
|
|
group.long 0x135C++0x03
|
|
line.long 0x00 "SD_BL_PARAMETERS_0,Backlight response parameters"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STEP ,Determines the instantaneous portion of the target value of enhancement that is applied"
|
|
hexmask.long.word 0x00 0.--10. 1. " TIME_CONSTANT ,The time constant for the response curve"
|
|
textline " "
|
|
group.long 0x1360++0x03
|
|
line.long 0x00 "SD_BL_TF_0,Backlight Transfer Function"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POINT_3 ,POINT_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " POINT_2 ,POINT_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " POINT_1 ,POINT_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " POINT_0 ,POINT_0"
|
|
group.long 0x1364++0x03
|
|
line.long 0x00 "SD_BL_TF_1,Backlight Transfer Function"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POINT_3 ,POINT_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " POINT_2 ,POINT_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " POINT_1 ,POINT_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " POINT_0 ,POINT_0"
|
|
group.long 0x1368++0x03
|
|
line.long 0x00 "SD_BL_TF_2,Backlight Transfer Function"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POINT_3 ,POINT_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " POINT_2 ,POINT_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " POINT_1 ,POINT_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " POINT_0 ,POINT_0"
|
|
group.long 0x136C++0x03
|
|
line.long 0x00 "SD_BL_TF_3,Backlight Transfer Function"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POINT_3 ,POINT_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " POINT_2 ,POINT_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " POINT_1 ,POINT_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " POINT_0 ,POINT_0"
|
|
textline " "
|
|
group.long 0x1370++0x03
|
|
line.long 0x00 "SD_BL_CONTROL_0,SD_BL_CONTROL_0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BRIGHTNESS ,Backlight brightness modification value"
|
|
bitfld.long 0x00 0.--1. " BL_MODE ,Control Mode: and adjust the backlight brightness itself" "MANUAL,PWM_AUTO,?..."
|
|
rgroup.long 0x1374++0x03
|
|
line.long 0x00 "SD_HW_K_VALUES_0,Hardware-computed values of K for each color component"
|
|
hexmask.long.word 0x00 20.--29. 1. " HW_K_BLUE ,Value of K for blue pixels"
|
|
hexmask.long.word 0x00 10.--19. 1. " HW_K_GREEN ,Value of K for green pixels"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " HW_K_RED ,Value of K for red pixels"
|
|
group.long 0x1378++0x3B
|
|
line.long 0x00 "SD_MAN_K_VALUES_0,Manual values of K for each color component"
|
|
hexmask.long.word 0x00 20.--29. 1. " MAN_K_BLUE ,Value of K for blue pixels"
|
|
hexmask.long.word 0x00 10.--19. 1. " MAN_K_GREEN ,Value of K for green pixels"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " MAN_K_RED ,Value of K for red pixels"
|
|
line.long 0x04 "SD_K_LIMIT_0,SD_K_LIMIT_0"
|
|
hexmask.long.word 0x04 0.--9. 1. " K_LIMIT ,When K_LIMIT_ENABLE=ENABLE limits raw K independently of AGGRESSIVENESS"
|
|
line.long 0x08 "SD_WINDOW_POSITION_0,SD Window Position"
|
|
hexmask.long.word 0x08 16.--28. 1. " SD_WIN_V_POSITION ,SD window vertical position (pixels)"
|
|
hexmask.long.word 0x08 0.--12. 1. " SD_WIN_H_POSITION ,SD window horizontal position (pixels)"
|
|
line.long 0x0C "SD_WINDOW_SIZE_0,SD Window Size"
|
|
hexmask.long.word 0x0C 16.--28. 1. " SD_WIN_V_SIZE ,SD window vertical height (pixels)"
|
|
hexmask.long.word 0x0C 0.--12. 1. " SD_WIN_H_SIZE ,SD window horizontal width (pixels)"
|
|
line.long 0x10 "SD_SOFT_CLIPPING_0,SD soft clipping parameters"
|
|
hexmask.long.word 0x10 16.--31. 1. " SOFT_CLIPPING_RECIP ,Reciprocal of inverse threshold"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SOFT_CLIPPING_THRESHOLD ,Threshold at which pixel enhancement gain is reduced"
|
|
line.long 0x14 "SD_SMOOTH_K_0,SD_SMOOTH_K_0"
|
|
hexmask.long.word 0x14 0.--13. 1. " SMOOTH_K_INCR ,When SMOOTH_K_ENABLE=1 the raw K is changed at most by SMOOTH_K_INCR per frame"
|
|
line.long 0x18 "BLEND_BACKGROUND_COLOR_0,BLEND_BACKGROUND_COLOR_0"
|
|
hexmask.long.byte 0x18 24.--31. 1. " BKGND_ALPHA ,Background color of alpha canal"
|
|
hexmask.long.byte 0x18 16.--23. 1. " BKGND_BLUE ,Background color of blue canal"
|
|
textline " "
|
|
hexmask.long.byte 0x18 8.--15. 1. " BKGND_GREEN ,Background color of green canal"
|
|
hexmask.long.byte 0x18 0.--7. 1. " BKGND_RED ,Background color of red canal"
|
|
line.long 0x1C "INTERLACE_CONTROL_0,Control interlacing"
|
|
rbitfld.long 0x1C 2. " INTERLACE_STATUS ,Status" "FIELD1,FIELD2"
|
|
bitfld.long 0x1C 1. " INTERLACE_START ,Start" "FIELD1,FIELD2"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " INTERLACE_ENABLE ,Enable" "Disabled,Enabled"
|
|
line.long 0x20 "INTERLACE_FIELD2_REF_TO_SYNC_0,Control the ref to sync offset for H sync and V sync for FIELD2"
|
|
hexmask.long.word 0x20 16.--28. 1. " FIELD2_V_REF_TO_SYNC ,V reference to VSYNC for FIELD2"
|
|
hexmask.long.word 0x20 0.--12. 1. " FIELD2_H_REF_TO_SYNC ,H reference to HSYNC for FIELD2"
|
|
line.long 0x24 "INTERLACE_FIELD2_SYNC_WIDTH_0,Control the H and V sync widths for FIELD2"
|
|
hexmask.long.word 0x24 16.--28. 1. " FIELD2_V_SYNC_WIDTH ,This field controls the V sync widths for FIELD2"
|
|
hexmask.long.word 0x24 0.--12. 1. " FIELD2_H_SYNC_WIDTH ,This field controls the H sync widths for FIELD2"
|
|
line.long 0x28 "INTERLACE_FIELD2_BACK_PORCH_0,Control the H and V back porch widths for FIELD2"
|
|
hexmask.long.word 0x28 16.--28. 1. " FIELD2_V_BACK_PORCH ,V back porch"
|
|
hexmask.long.word 0x28 0.--12. 1. " FIELD2_H_BACK_PORCH ,H back porch"
|
|
line.long 0x2C "INTERLACE_FIELD2_FRONT_PORCH_0,Control the H and V front porch widths for FIELD2"
|
|
hexmask.long.word 0x2C 16.--28. 1. " FIELD2_V_FRONT_PORCH ,V front porch"
|
|
hexmask.long.word 0x2C 0.--12. 1. " FIELD2_H_FRONT_PORCH ,H front porch"
|
|
line.long 0x30 "INTERLACE_FIELD2_DISP_ACTIVE_0,Control the H and V active widths for FIELD2"
|
|
hexmask.long.word 0x30 16.--28. 1. " FIELD2_V_DISP_ACTIVE ,V active width"
|
|
hexmask.long.word 0x30 0.--12. 1. " FIELD2_H_DISP_ACTIVE ,H active width"
|
|
line.long 0x34 "CURSOR_UNDERFLOW_CTRL_0,CURSOR_UNDERFLOW_CTRL_0"
|
|
bitfld.long 0x34 7. " CURSOR_UFLOW_CYA ,CURSOR_UFLOW_CYA" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " CURSOR_UFLOW_CTRL_DBG_MODE ,CURSOR_UFLOW_CTRL_DBG_MODE" "Disabled,Enabled"
|
|
line.long 0x38 "CURSOR_START_ADDR_HI_0,Cursor Start Address"
|
|
bitfld.long 0x38 0.--1. " CURSOR_START_ADDR_HI ,Cursor Start Address bits 33:32" "0,1,2,3"
|
|
group.long 0x13B8++0x07
|
|
line.long 0x00 "CURSOR_INTERLACE_CONTROL_0,Control interlacing"
|
|
bitfld.long 0x00 4. " CURSOR_INTERLACE_FIELD2_VOFF_INCR ,FIELD2 v position incr Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CURSOR_INTERLACE_FIELD1_VOFF_INCR ,FIELD1 v position incr Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " CURSOR_INTERLACE_STATUS ,Current line start" "LINE0,LINE1"
|
|
bitfld.long 0x00 1. " CURSOR_INTERLACE_START ,Starting line" "LINE0,LINE1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CURSOR_INTERLACE_ENABLE ,Interlace enable" "Disabled,Enabled"
|
|
line.long 0x04 "CSC2_CONTROL_0,The CSC2 can be used for RGB to YCbCr conversion used in 1080i HDMI output"
|
|
bitfld.long 0x04 2. " LIMIT_RGB_COLOR ,Scale RGB [0,255] to [16,235]" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--1. " OUTPUT_COLOR_SELECT ,Output color select" "RGB,YCBCR709,YCBCR601,?..."
|
|
group.long 0x13C4++0x13
|
|
line.long 0x00 "BLEND_CURSOR_CONTROL_0,BLEND_CURSOR_CONTROL_0"
|
|
bitfld.long 0x00 24. " CURSOR_MODE_SELECT ,CURSOR_MODE_SELECT" "LEGACY,NORMAL"
|
|
bitfld.long 0x00 16.--17. " CURSOR_DST_BLEND_FACTOR_SELECT ,Controls the DST_FACTOR" "ZERO,K1,NEG_K1_TIMES_SRC,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CURSOR_SRC_BLEND_FACTOR_SELECT ,Controls the SRC_FACTOR" "K1,K1_TIMES_SRC,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " CURSOR_ALPHA ,CURSOR_ALPHA"
|
|
line.long 0x04 "DVFS_CURSOR_CONTROL_0,DVFS_CURSOR_CONTROL_0"
|
|
bitfld.long 0x04 8. " CURSOR_DVFS_ENABLE ,Enable ready_for_latency_event to toggle based on CURSOR_DVFS_THRESHOLD (When disabled ready_for_latency_event is true)" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CURSOR_DVFS_THRESHOLD ,CURSOR_DVFS_THRESHOLD"
|
|
line.long 0x08 "CURSOR_UFLOW_DBG_PIXEL_0,CURSOR_UFLOW_DBG_PIXEL_0"
|
|
line.long 0x0C "CURSOR_SPOOLUP_CONTROL_0,Programmable spool up for cursor If spoolup count > hc_vactive_start it will be clamped to zero"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CURSOR_SPOOLUP_START ,CURSOR_SPOOLUP_START"
|
|
line.long 0x10 "DISPLAY_CLK_GATE_OVERRIDE_0,DISPLAY_CLK_GATE_OVERRIDE_0"
|
|
bitfld.long 0x10 1. " CMU_CLK_GATE_OVERRIDE ,Disable clock-gating of the CMU module" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " CURSOR_CLK_GATE_OVERRIDE ,Disable clock-gating of cursor memfetch/control modules" "Disabled,Enabled"
|
|
rgroup.long 0x13D8++0x03
|
|
line.long 0x00 "DISPLAY_DBG_TIMING_0,DISPLAY_DBG_TIMING_0"
|
|
bitfld.long 0x00 31. " H_BLANK ,H_BLANK" "0,1"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_COUNT ,H_COUNT"
|
|
textline " "
|
|
bitfld.long 0x00 15. " V_BLANK ,V_BLANK" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " V_COUNT ,V_COUNT"
|
|
group.long 0x13DC++0x07
|
|
line.long 0x00 "DISPLAY_SPARE0_0,DISPLAY_SPARE0_0"
|
|
hexmask.long.word 0x00 4.--13. 1. " DSC_RC_OVERFLOW_THRESH ,Program the threshold of bufferFullness + throttle_offset (currently it is -172)"
|
|
bitfld.long 0x00 2.--3. " DSC_RC_SOLUTION_MODE ,DSC_RC_SOLUTION_MODE" "Disabled,Solution#1,Solution#2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " DSC_CHECK_FLATNESS2 ,DSC_CHECK_FLATNESS2" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DSC_FLATNESS_FIX_EN ,Diagnostic bit for flatness updates only" "Disabled,Enabled"
|
|
line.long 0x04 "DISPLAY_SPARE1_0,DISPLAY_SPARE1_0"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
width 21.
|
|
tree "Window A Registers"
|
|
wgroup.long 0x1400++0x03
|
|
line.long 0x00 "COLOR_PALETTE_0,Window A Color Palette"
|
|
button "BGR" "d (ad:0x54200000+0x1400)--(ad:0x54200000+0x17fc) /long"
|
|
group.long 0x1800++0x03
|
|
line.long 0x00 "PALETTE_COLOR_EXT_0,Window A Palette Color Extension"
|
|
hexmask.long.byte 0x00 1.--7. 1. " A_PALETTE_COLOR_EXT ,Window A Palette Color Extension"
|
|
group.long 0x1804++0x03
|
|
line.long 0x00 "H_FILTER_P00_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P00C5 ,Phase 00 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " A_H_FILTER_P00C4 ,Phase 00 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P00C3 ,Phase 00 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 00 coefficient 2"
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|
bitfld.long 0x00 3.--7. " A_H_FILTER_P00C1 ,Phase 00 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 0.--2. " A_H_FILTER_P00C0 ,Phase 00 coefficient 0" "0,1,2,3,4,5,6,7"
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|
group.long 0x1808++0x03
|
|
line.long 0x00 "H_FILTER_P01_0,Horizontal Scaling Filter Coefficients"
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|
bitfld.long 0x00 29.--31. " A_H_FILTER_P01C5 ,Phase 01 coefficient 5" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 24.--28. " A_H_FILTER_P01C4 ,Phase 01 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P01C3 ,Phase 01 coefficient 3"
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|
textline " "
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hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 01 coefficient 2"
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bitfld.long 0x00 3.--7. " A_H_FILTER_P01C1 ,Phase 01 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 0.--2. " A_H_FILTER_P01C0 ,Phase 01 coefficient 0" "0,1,2,3,4,5,6,7"
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|
group.long 0x180C++0x03
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|
line.long 0x00 "H_FILTER_P02_0,Horizontal Scaling Filter Coefficients"
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|
bitfld.long 0x00 29.--31. " A_H_FILTER_P02C5 ,Phase 02 coefficient 5" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 24.--28. " A_H_FILTER_P02C4 ,Phase 02 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P02C3 ,Phase 02 coefficient 3"
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textline " "
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hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 02 coefficient 2"
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bitfld.long 0x00 3.--7. " A_H_FILTER_P02C1 ,Phase 02 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 0.--2. " A_H_FILTER_P02C0 ,Phase 02 coefficient 0" "0,1,2,3,4,5,6,7"
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group.long 0x1810++0x03
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line.long 0x00 "H_FILTER_P03_0,Horizontal Scaling Filter Coefficients"
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bitfld.long 0x00 29.--31. " A_H_FILTER_P03C5 ,Phase 03 coefficient 5" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--28. " A_H_FILTER_P03C4 ,Phase 03 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P03C3 ,Phase 03 coefficient 3"
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textline " "
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hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 03 coefficient 2"
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bitfld.long 0x00 3.--7. " A_H_FILTER_P03C1 ,Phase 03 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--2. " A_H_FILTER_P03C0 ,Phase 03 coefficient 0" "0,1,2,3,4,5,6,7"
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group.long 0x1814++0x03
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line.long 0x00 "H_FILTER_P04_0,Horizontal Scaling Filter Coefficients"
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bitfld.long 0x00 29.--31. " A_H_FILTER_P04C5 ,Phase 04 coefficient 5" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--28. " A_H_FILTER_P04C4 ,Phase 04 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P04C3 ,Phase 04 coefficient 3"
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textline " "
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hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 04 coefficient 2"
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bitfld.long 0x00 3.--7. " A_H_FILTER_P04C1 ,Phase 04 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--2. " A_H_FILTER_P04C0 ,Phase 04 coefficient 0" "0,1,2,3,4,5,6,7"
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group.long 0x1818++0x03
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line.long 0x00 "H_FILTER_P05_0,Horizontal Scaling Filter Coefficients"
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bitfld.long 0x00 29.--31. " A_H_FILTER_P05C5 ,Phase 05 coefficient 5" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--28. " A_H_FILTER_P05C4 ,Phase 05 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P05C3 ,Phase 05 coefficient 3"
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textline " "
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hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 05 coefficient 2"
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bitfld.long 0x00 3.--7. " A_H_FILTER_P05C1 ,Phase 05 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--2. " A_H_FILTER_P05C0 ,Phase 05 coefficient 0" "0,1,2,3,4,5,6,7"
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group.long 0x181C++0x03
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line.long 0x00 "H_FILTER_P06_0,Horizontal Scaling Filter Coefficients"
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bitfld.long 0x00 29.--31. " A_H_FILTER_P06C5 ,Phase 06 coefficient 5" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--28. " A_H_FILTER_P06C4 ,Phase 06 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P06C3 ,Phase 06 coefficient 3"
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textline " "
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hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 06 coefficient 2"
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bitfld.long 0x00 3.--7. " A_H_FILTER_P06C1 ,Phase 06 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 0.--2. " A_H_FILTER_P06C0 ,Phase 06 coefficient 0" "0,1,2,3,4,5,6,7"
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|
group.long 0x1820++0x03
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|
line.long 0x00 "H_FILTER_P07_0,Horizontal Scaling Filter Coefficients"
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|
bitfld.long 0x00 29.--31. " A_H_FILTER_P07C5 ,Phase 07 coefficient 5" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--28. " A_H_FILTER_P07C4 ,Phase 07 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P07C3 ,Phase 07 coefficient 3"
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|
textline " "
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hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 07 coefficient 2"
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bitfld.long 0x00 3.--7. " A_H_FILTER_P07C1 ,Phase 07 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 0.--2. " A_H_FILTER_P07C0 ,Phase 07 coefficient 0" "0,1,2,3,4,5,6,7"
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|
group.long 0x1824++0x03
|
|
line.long 0x00 "H_FILTER_P08_0,Horizontal Scaling Filter Coefficients"
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bitfld.long 0x00 29.--31. " A_H_FILTER_P08C5 ,Phase 08 coefficient 5" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--28. " A_H_FILTER_P08C4 ,Phase 08 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P08C3 ,Phase 08 coefficient 3"
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textline " "
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hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 08 coefficient 2"
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bitfld.long 0x00 3.--7. " A_H_FILTER_P08C1 ,Phase 08 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--2. " A_H_FILTER_P08C0 ,Phase 08 coefficient 0" "0,1,2,3,4,5,6,7"
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group.long 0x1828++0x03
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line.long 0x00 "H_FILTER_P09_0,Horizontal Scaling Filter Coefficients"
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bitfld.long 0x00 29.--31. " A_H_FILTER_P09C5 ,Phase 09 coefficient 5" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--28. " A_H_FILTER_P09C4 ,Phase 09 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P09C3 ,Phase 09 coefficient 3"
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textline " "
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hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 09 coefficient 2"
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bitfld.long 0x00 3.--7. " A_H_FILTER_P09C1 ,Phase 09 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--2. " A_H_FILTER_P09C0 ,Phase 09 coefficient 0" "0,1,2,3,4,5,6,7"
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group.long 0x182C++0x03
|
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line.long 0x00 "H_FILTER_P0A_0,Horizontal Scaling Filter Coefficients"
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bitfld.long 0x00 29.--31. " A_H_FILTER_P0AC5 ,Phase 0A coefficient 5" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--28. " A_H_FILTER_P0AC4 ,Phase 0A coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P0AC3 ,Phase 0A coefficient 3"
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textline " "
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hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 0A coefficient 2"
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bitfld.long 0x00 3.--7. " A_H_FILTER_P0AC1 ,Phase 0A coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--2. " A_H_FILTER_P0AC0 ,Phase 0A coefficient 0" "0,1,2,3,4,5,6,7"
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group.long 0x1830++0x03
|
|
line.long 0x00 "H_FILTER_P0B_0,Horizontal Scaling Filter Coefficients"
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|
bitfld.long 0x00 29.--31. " A_H_FILTER_P0BC5 ,Phase 0B coefficient 5" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--28. " A_H_FILTER_P0BC4 ,Phase 0B coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P0BC3 ,Phase 0B coefficient 3"
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textline " "
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hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 0B coefficient 2"
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bitfld.long 0x00 3.--7. " A_H_FILTER_P0BC1 ,Phase 0B coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 0.--2. " A_H_FILTER_P0BC0 ,Phase 0B coefficient 0" "0,1,2,3,4,5,6,7"
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|
group.long 0x1834++0x03
|
|
line.long 0x00 "H_FILTER_P0C_0,Horizontal Scaling Filter Coefficients"
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|
bitfld.long 0x00 29.--31. " A_H_FILTER_P0CC5 ,Phase 0C coefficient 5" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--28. " A_H_FILTER_P0CC4 ,Phase 0C coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P0CC3 ,Phase 0C coefficient 3"
|
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textline " "
|
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hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 0C coefficient 2"
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bitfld.long 0x00 3.--7. " A_H_FILTER_P0CC1 ,Phase 0C coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--2. " A_H_FILTER_P0CC0 ,Phase 0C coefficient 0" "0,1,2,3,4,5,6,7"
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|
group.long 0x1838++0x03
|
|
line.long 0x00 "H_FILTER_P0D_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P0DC5 ,Phase 0D coefficient 5" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--28. " A_H_FILTER_P0DC4 ,Phase 0D coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P0DC3 ,Phase 0D coefficient 3"
|
|
textline " "
|
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hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 0D coefficient 2"
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bitfld.long 0x00 3.--7. " A_H_FILTER_P0DC1 ,Phase 0D coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 0.--2. " A_H_FILTER_P0DC0 ,Phase 0D coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x183C++0x03
|
|
line.long 0x00 "H_FILTER_P0E_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P0EC5 ,Phase 0E coefficient 5" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 24.--28. " A_H_FILTER_P0EC4 ,Phase 0E coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P0EC3 ,Phase 0E coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 0E coefficient 2"
|
|
bitfld.long 0x00 3.--7. " A_H_FILTER_P0EC1 ,Phase 0E coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 0.--2. " A_H_FILTER_P0EC0 ,Phase 0E coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1840++0x03
|
|
line.long 0x00 "H_FILTER_P0F_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P0FC5 ,Phase 0F coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " A_H_FILTER_P0FC4 ,Phase 0F coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P0FC3 ,Phase 0F coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 0F coefficient 2"
|
|
bitfld.long 0x00 3.--7. " A_H_FILTER_P0FC1 ,Phase 0F coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " A_H_FILTER_P0FC0 ,Phase 0F coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1844++0x1F
|
|
line.long 0x00 "CSC_YOF_0,Colour Space Conversion Coefficients"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_CSC_YOF ,Y Offset in s.7.0 format"
|
|
line.long 0x04 "CSC_KYRGB_0,Window A CSC Y Coefficient for RGB"
|
|
hexmask.long.word 0x04 0.--9. 1. " A_CSC_KYRGB ,Y Gain for R, G, B colours in 2.8 format"
|
|
line.long 0x08 "CSC_KUR_0,Window A CSC U coefficient for R"
|
|
hexmask.long.word 0x08 0.--10. 1. " A_CSC_KUR ,U coefficients for R in s.2.8 format"
|
|
line.long 0x0C "CSC_KVR_0,Window A CSC V coefficient for R"
|
|
hexmask.long.word 0x0C 0.--10. 1. " A_CSC_KVR ,V coefficients for R in s.2.8 format"
|
|
line.long 0x10 "CSC_KUG_0,Window A CSC U coefficient for G"
|
|
hexmask.long.word 0x10 0.--9. 1. " A_CSC_KUG ,U coefficients for G in s.1.8 format"
|
|
line.long 0x14 "CSC_KVG_0,Window A CSC V coefficient for G"
|
|
hexmask.long.word 0x14 0.--9. 1. " A_CSC_KVG ,V coefficients for G in s.1.8 format"
|
|
line.long 0x18 "CSC_KUB_0,Window A CSC U coefficient for B"
|
|
hexmask.long.word 0x18 0.--10. 1. " A_CSC_KUB ,U coefficients for B in s.2.8 format"
|
|
line.long 0x1C "CSC_KVB_0,Window A CSC V coefficient for B"
|
|
hexmask.long.word 0x1C 0.--10. 1. " A_CSC_KVB ,V coefficients for B in s.2.8 format"
|
|
textline " "
|
|
group.long 0x1864++0x03
|
|
line.long 0x00 "V_FILTER_P00_0,Window A Vertical Filter phase 00"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P00C0 ,Phase 00 coefficient 0"
|
|
group.long 0x1868++0x03
|
|
line.long 0x00 "V_FILTER_P01_0,Window A Vertical Filter phase 01"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P01C0 ,Phase 01 coefficient 1"
|
|
group.long 0x186C++0x03
|
|
line.long 0x00 "V_FILTER_P02_0,Window A Vertical Filter phase 02"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P02C0 ,Phase 02 coefficient 2"
|
|
group.long 0x1870++0x03
|
|
line.long 0x00 "V_FILTER_P03_0,Window A Vertical Filter phase 03"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P03C0 ,Phase 03 coefficient 3"
|
|
group.long 0x1874++0x03
|
|
line.long 0x00 "V_FILTER_P04_0,Window A Vertical Filter phase 04"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P04C0 ,Phase 04 coefficient 4"
|
|
group.long 0x1878++0x03
|
|
line.long 0x00 "V_FILTER_P05_0,Window A Vertical Filter phase 05"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P05C0 ,Phase 05 coefficient 5"
|
|
group.long 0x187C++0x03
|
|
line.long 0x00 "V_FILTER_P06_0,Window A Vertical Filter phase 06"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P06C0 ,Phase 06 coefficient 6"
|
|
group.long 0x1880++0x03
|
|
line.long 0x00 "V_FILTER_P07_0,Window A Vertical Filter phase 07"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P07C0 ,Phase 07 coefficient 7"
|
|
group.long 0x1884++0x03
|
|
line.long 0x00 "V_FILTER_P08_0,Window A Vertical Filter phase 08"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P08C0 ,Phase 08 coefficient 8"
|
|
group.long 0x1888++0x03
|
|
line.long 0x00 "V_FILTER_P09_0,Window A Vertical Filter phase 09"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P09C0 ,Phase 09 coefficient 9"
|
|
group.long 0x188C++0x03
|
|
line.long 0x00 "V_FILTER_P0A_0,Window A Vertical Filter phase 0A"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P0AC0 ,Phase 0A coefficient A"
|
|
group.long 0x1890++0x03
|
|
line.long 0x00 "V_FILTER_P0B_0,Window A Vertical Filter phase 0B"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P0BC0 ,Phase 0B coefficient B"
|
|
group.long 0x1894++0x03
|
|
line.long 0x00 "V_FILTER_P0C_0,Window A Vertical Filter phase 0C"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P0CC0 ,Phase 0C coefficient C"
|
|
group.long 0x1898++0x03
|
|
line.long 0x00 "V_FILTER_P0D_0,Window A Vertical Filter phase 0D"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P0DC0 ,Phase 0D coefficient D"
|
|
group.long 0x189C++0x03
|
|
line.long 0x00 "V_FILTER_P0E_0,Window A Vertical Filter phase 0E"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P0EC0 ,Phase 0E coefficient E"
|
|
group.long 0x18A0++0x03
|
|
line.long 0x00 "V_FILTER_P0F_0,Window A Vertical Filter phase 0F"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P0FC0 ,Phase 0F coefficient F"
|
|
textline " "
|
|
group.long 0x18A4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P00_0,Window A Horizontal Filter phase 00"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P00C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P00C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P00C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P00C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P00C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P00C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18A8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P01_0,Window A Horizontal Filter phase 01"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P01C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P01C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P01C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P01C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P01C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P01C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18AC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P02_0,Window A Horizontal Filter phase 02"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P02C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P02C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P02C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P02C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P02C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P02C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18B0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P03_0,Window A Horizontal Filter phase 03"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P03C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P03C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P03C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P03C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P03C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P03C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18B4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P04_0,Window A Horizontal Filter phase 04"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P04C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P04C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P04C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P04C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P04C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P04C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18B8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P05_0,Window A Horizontal Filter phase 05"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P05C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P05C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P05C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P05C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P05C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P05C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18BC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P06_0,Window A Horizontal Filter phase 06"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P06C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P06C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P06C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P06C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P06C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P06C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18C0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P07_0,Window A Horizontal Filter phase 07"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P07C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P07C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P07C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P07C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P07C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P07C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18C4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P08_0,Window A Horizontal Filter phase 08"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P08C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P08C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P08C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P08C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P08C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P08C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18C8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P09_0,Window A Horizontal Filter phase 09"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P09C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P09C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P09C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P09C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P09C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P09C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18CC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0A_0,Window A Horizontal Filter phase 0A"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P0AC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P0AC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P0AC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P0AC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P0AC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P0AC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18D0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0B_0,Window A Horizontal Filter phase 0B"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P0BC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P0BC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P0BC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P0BC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P0BC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P0BC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18D4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0C_0,Window A Horizontal Filter phase 0C"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P0CC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P0CC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P0CC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P0CC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P0CC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P0CC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18D8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0D_0,Window A Horizontal Filter phase 0D"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P0DC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P0DC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P0DC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P0DC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P0DC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P0DC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18DC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0E_0,Window A Horizontal Filter phase 0E"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P0EC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P0EC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P0EC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P0EC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P0EC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P0EC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18E0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0F_0,Window A Horizontal Filter phase 0F"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P0FC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P0FC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P0FC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P0FC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P0FC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P0FC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
textline " "
|
|
width 17.
|
|
if (((d.l(ad:0x54200000+0x1C00))&0x400)==0x400)
|
|
group.long 0x1C00++0x03
|
|
line.long 0x00 "WIN_OPTIONS_0,Window A Options"
|
|
bitfld.long 0x00 31. " A_H_FILTER_MODE ,Horizontal filter mode" "Old,New"
|
|
bitfld.long 0x00 30. " A_WIN_ENABLE ,Window A Window enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " A_INTERLACE_ENABLE ,Window A Interlace enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " A_YUV_RANGE_EXPAND ,Window A Enable range expansion" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " A_DV_ENABLE ,Window A Digital Vibrance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " A_CSC_ENABLE ,Window A Color Space Conversion Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " A_CP_ENABLE ,Window A Color Palette Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " A_V_FILTER_UV_ALIGN ,Window A V Filter UV Alignment" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " A_V_FILTER_OPTIMIZE ,Window A V Filter Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " A_V_FILTER_ENABLE ,Window A V Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " A_H_FILTER_ENABLE ,Window A H Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " A_COLOR_EXPAND ,Color expansion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_SCAN_COLUMN ,Window A Scanning direction" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " A_V_DIRECTION ,Window A Vertical (Y) drawing Direction" "Increment,Decrement"
|
|
bitfld.long 0x00 0. " A_H_DIRECTION ,Window A Horizontal (X) drawing Direction" "Increment,Decrement"
|
|
else
|
|
group.long 0x1C00++0x03
|
|
line.long 0x00 "WIN_OPTIONS_0,Window A Options"
|
|
bitfld.long 0x00 31. " A_H_FILTER_MODE ,Horizontal filter mode" "Old,New"
|
|
bitfld.long 0x00 30. " A_WIN_ENABLE ,Window A Window enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " A_INTERLACE_ENABLE ,Window A Interlace enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " A_YUV_RANGE_EXPAND ,Window A Enable range expansion" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " A_DV_ENABLE ,Window A Digital Vibrance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " A_CSC_ENABLE ,Window A Color Space Conversion Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " A_CP_ENABLE ,Window A Color Palette Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " A_V_FILTER_ENABLE ,Window A V Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " A_H_FILTER_ENABLE ,Window A H Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " A_COLOR_EXPAND ,Color expansion" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " A_SCAN_COLUMN ,Window A Scanning direction" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " A_V_DIRECTION ,Window A Vertical (Y) drawing Direction" "Increment,Decrement"
|
|
textline " "
|
|
bitfld.long 0x00 0. " A_H_DIRECTION ,Window A Horizontal (X) drawing Direction" "Increment,Decrement"
|
|
endif
|
|
group.long 0x1C04++0x03
|
|
line.long 0x00 "BYTE_SWAP_0,Window A Byte Swap"
|
|
bitfld.long 0x00 0.--2. " A_BYTE_SWAP ,Window A Byte Swap" "NOSWAP,SWAP2,SWAP4,SWAP4HW,SWAP02,SWAPLEFT,,"
|
|
group.long 0x1C0C++0x03
|
|
line.long 0x00 "COLOR_DEPTH_0,Window A Color depth"
|
|
hexmask.long.byte 0x00 0.--6. 1. " A_COLOR_DEPTH ,Window A Color Depth"
|
|
width 18.
|
|
textline " "
|
|
group.long 0x1C10++0x03
|
|
line.long 0x00 "POSITION_0,Window A Position"
|
|
hexmask.long.word 0x00 16.--28. 1. " A_V_POSITION ,Window A V Position"
|
|
hexmask.long.word 0x00 0.--12. 1. " A_H_POSITION ,Window A H Position"
|
|
group.long 0x1C14++0x03
|
|
line.long 0x00 "SIZE_0,Window A Size"
|
|
hexmask.long.word 0x00 16.--28. 1. " A_V_SIZE ,Vertical size after scaling"
|
|
hexmask.long.word 0x00 0.--12. 1. " A_H_SIZE ,Horizontal size after scaling"
|
|
group.long 0x1C18++0x03
|
|
line.long 0x00 "PRESCALED_SIZE_0,Window A Pre-scaled Size"
|
|
hexmask.long.word 0x00 16.--28. 1. " A_V_PRESCALED_SIZE ,Window A V Pre-scaled Size"
|
|
hexmask.long.word 0x00 0.--14. 1. " A_H_PRESCALED_SIZE ,Window A H Pre-scaled Size"
|
|
group.long 0x1C1C++0x03
|
|
line.long 0x00 "H_INITIAL_DDA_0,Window A H Initial DDA"
|
|
hexmask.long.word 0x00 0.--15. 1. " A_H_INITIAL_DDA ,Window A H Initial DDA"
|
|
group.long 0x1C20++0x03
|
|
line.long 0x00 "V_INITIAL_DDA_0,Window A V Initial DDA"
|
|
hexmask.long.word 0x00 0.--15. 1. " A_V_INITIAL_DDA ,Window A V Initial DDA"
|
|
group.long 0x1C24++0x03
|
|
line.long 0x00 "DDA_INCREMENT_0,Window A DDA Increment"
|
|
hexmask.long.word 0x00 16.--31. 1. " A_V_DDA_INCREMENT ,Window A Vertical DDA Increment"
|
|
hexmask.long.word 0x00 0.--15. 1. " A_H_DDA_INCREMENT ,Window A Horizontal DDA Increment"
|
|
group.long 0x1C28++0x03
|
|
line.long 0x00 "LINE_STRIDE_0,Window A Line Stride"
|
|
hexmask.long.word 0x00 16.--31. 1. " A_UV_LINE_STRIDE ,Window A Line Stride for Chroma"
|
|
hexmask.long.word 0x00 0.--15. 1. " A_LINE_STRIDE ,Window A Line Stride"
|
|
group.long 0x1C38++0x03
|
|
line.long 0x00 "DV_CONTROL_0,Window A Digital Vibrance Control"
|
|
bitfld.long 0x00 16.--18. " A_DV_CONTROL_B ,Digital Vibrance control for B" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " A_DV_CONTROL_G ,Digital Vibrance control for G" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " A_DV_CONTROL_R ,Digital Vibrance control for R" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
width 24.
|
|
group.long 0x1C58++0x0F
|
|
line.long 0x00 "BLEND_LAYER_CONTROL_0,Window A"
|
|
bitfld.long 0x00 25.--27. " A_COLOR_KEY_SELECT ,A COLOR KEY SELECT" "0,1,2,3,4,5,6,7"
|
|
eventfld.long 0x00 24. " A_BLEND_BYPASS ,A BLEND BYPASS" "BLEND_ENABLE,BLEND_BYPASS"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_K2 ,A K2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_K1 ,A K1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_WINDOW_LAYER_DEPTH ,A WINDOW LAYER DEPTH"
|
|
line.long 0x04 "BLEND_MATCH_SELECT_0,DC WIN A BLEND MATCH SELECT 0"
|
|
bitfld.long 0x04 12.--13. " A_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT ,A BLEND FACTOR DST ALPHA MATCH SELECT" "0,1,EG_K1_TIMES_SRC,K2"
|
|
bitfld.long 0x04 8.--9. " A_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT ,A BLEND FACTOR SRC ALPHA MATCH SELECT" "0,K1,K2,"
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " A_BLEND_FACTOR_DST_COLOR_MATCH_SELECT ,A BLEND FACTOR DST COLOR MATCH SELECT" "0,1,K1,K2,K1_TIMES_DST,NEG_K1_TIMES_DST,NEG_K1_TIMES_SRC,NEG_K1"
|
|
bitfld.long 0x04 0.--2. " A_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT ,A BLEND FACTOR SRC COLOR MATCH SELECT" "0,1,K1,K1_TIMES_DST,NEG_K1_TIMES_DST,K1_TIMES_SRC,,"
|
|
line.long 0x08 "BLEND_NOMATCH_SELECT_0,DC WIN A BLEND NOMATCH SELECT 0"
|
|
bitfld.long 0x08 12.--13. " A_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT ,A BLEND FACTOR DST ALPHA NOMATCH SELECT" "0,1,EG_K1_TIMES_SRC,K2"
|
|
bitfld.long 0x08 8.--9. " A_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT ,A BLEND FACTOR SRC ALPHA NOMATCH SELECT" "0,K1,K2,"
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " A_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT ,A BLEND FACTOR DST COLOR NOMATCH SELECT" "0,1,K1,K2,K1_TIMES_DST,NEG_K1_TIMES_DST,NEG_K1_TIMES_SRC,NEG_K1"
|
|
bitfld.long 0x08 0.--2. " A_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT ,A BLEND FACTOR SRC COLOR NOMATCH SELECT" "0,1,K1,K1_TIMES_DST,NEG_K1_TIMES_DST,K1_TIMES_SRC,,"
|
|
line.long 0x0C "BLEND_ALPHA_1BIT_0,DC WIN A BLEND ALPHA 1BIT 0"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " A_BLEND_WEIGHT1 ,Alpha value of 1"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " A_BLEND_WEIGHT0 ,Alpha value of 0"
|
|
tree.end
|
|
width 18.
|
|
tree "WINBUF_A Registers"
|
|
group.long 0x2000++0x27
|
|
line.long 0x00 "START_ADDR_0,Window A Start Address"
|
|
line.long 0x04 "START_ADDR_NS_0,Window A Shadowed Start Address"
|
|
line.long 0x08 "START_ADDR_U_0,Window A Start Address for U plane"
|
|
line.long 0x0C "START_ADDR_U_NS_0,Window A Shadowed Start Address for U plane"
|
|
line.long 0x10 "START_ADDR_V_0,Window A Start Address for V plane"
|
|
line.long 0x14 "START_ADDR_V_NS_0,WWindow A Shadowed Start Address for V plane"
|
|
line.long 0x18 "ADDR_H_OFFSET_0,Window A Horizontal Address Offset"
|
|
line.long 0x1C "ADDR_H_OFFSET_NS_0,Window A Shadowed Horizontal Address Offset"
|
|
line.long 0x20 "ADDR_V_OFFSET_0,Window A Vertical Address Offset"
|
|
line.long 0x24 "ADDR_V_OFFSET_NS_0,Window A Shadowed Vertical Address Offset"
|
|
group.long 0x2028++0x0B
|
|
line.long 0x00 "UFLOW_STATUS,Window A FIFO Underflow Status Register"
|
|
bitfld.long 0x00 30. " COUNT_OFLOW ,Counter has overflowed" "Not occurred,Occurred"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " UFLOW_COUNT ,Underflow count"
|
|
line.long 0x04 "SURFACE_KIND_0,Window A Surface Kind"
|
|
bitfld.long 0x04 4.--6. " A_BLOCK_HEIGHT ,Block Height" "HEIGHT_1,HEIGHT_2,HEIGHT_4,HEIGHT_8,HEIGHT_16,HEIGHT_32,,"
|
|
bitfld.long 0x04 0.--1. " A_SURFACE_KIND ,Surface kind" "PITCH,TILED,BL_16B2,"
|
|
line.long 0x08 "SURFACE_WEIGHT_0,Window A Surface Weights"
|
|
bitfld.long 0x08 5.--6. " A_SURFACE_WEIGHT_V ,Window A V Surface Weights" "2,4,8,16"
|
|
bitfld.long 0x08 3.--4. " A_SURFACE_WEIGHT_U ,Window A U or UV Surface Weights" "2,4,8,16"
|
|
bitfld.long 0x08 1.--2. " A_SURFACE_WEIGHT_Y ,Window A Y or packed Surface Weights" "2,4,8,16"
|
|
bitfld.long 0x08 0. " A_SURFACE_WEIGHT_OVERRIDE ,Weight Override" "Disabled,Enabled"
|
|
textline " "
|
|
width 22.
|
|
group.long 0x2034++0x17
|
|
line.long 0x00 "START_ADDR_HI_0,Window A Higher 2 bits of Start Address"
|
|
bitfld.long 0x00 0.--1. " A_START_ADDR_HI ,Window A Start Address" "0,1,2,3"
|
|
line.long 0x04 "START_ADDR_HI_NS_0,Window A Higher 2 bits of Start Address"
|
|
bitfld.long 0x04 0.--1. " A_START_ADDR_HI_NS ,Window A Shadowed Start Address" "0,1,2,3"
|
|
line.long 0x08 "START_ADDR_HI_U_0,Window A Higher 2 bits of Start Address"
|
|
bitfld.long 0x08 0.--1. " A_START_ADDR_HI ,Window A Start Address" "0,1,2,3"
|
|
line.long 0x0C "START_ADDR_HI_U_NS_0,Window A Shadowed Higher 2 bits of Start Address for U Plane"
|
|
bitfld.long 0x0C 0.--1. " A_START_ADDR_HI_U_NS ,Window A Shadowed Higher 2 bits of Start Address for U plane" "0,1,2,3"
|
|
line.long 0x10 "START_ADDR_HI_V_0,Window A Higher 2 bits of Start Address for V Plane"
|
|
bitfld.long 0x10 0.--1. " A_START_ADDR_HI_V ,Window A Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
line.long 0x14 "START_ADDR_HI_V_NS_0,Window A Shadowed Higher 2 bits of Start Address for V Plane"
|
|
bitfld.long 0x14 0.--1. " A_START_ADDR_HI_V_NS ,Window A Shadowed Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
textline " "
|
|
width 29.
|
|
group.long 0x204C++0x17
|
|
line.long 0x00 "START_ADDR_FIELD2_0,Window A Start Address"
|
|
line.long 0x04 "START_ADDR_FIELD2_NS_0,Window A Shadowed Start Address"
|
|
line.long 0x08 "START_ADDR_FIELD2_U_0,Window A Start Address for U plane"
|
|
line.long 0x0C "START_ADDR_FIELD2_U_NS_0,Window A Shadowed Start Address for U plane"
|
|
line.long 0x10 "START_ADDR_FIELD2_V_0,Window A Start Address for V plane"
|
|
line.long 0x14 "START_ADDR_FIELD2_V_NS_0,Window A Shadowed Start Address for V plane"
|
|
group.long 0x2064++0x17
|
|
line.long 0x00 "START_ADDR_FIELD2_HI_0,Window A Higher 2 bits of Start Address"
|
|
bitfld.long 0x00 0.--1. " A_START_ADDR_FIELD2_HI ,Window A Start Address" "0,1,2,3"
|
|
line.long 0x04 "START_ADDR_FIELD2_HI_NS_0,Window A Shadowed Higher 2 bits of Start Address"
|
|
bitfld.long 0x04 0.--1. " A_START_ADDR_FIELD2_HI_NS ,Window A Shadowed Start Address" "0,1,2,3"
|
|
line.long 0x08 "START_ADDR_FIELD2_HI_U_0,Window A Higher 2 bits of Start Address for U plane"
|
|
bitfld.long 0x08 0.--1. " A_START_ADDR_FIELD2_HI_U ,Window A Start Address for U plane" "0,1,2,3"
|
|
line.long 0x0C "START_ADDR_FIELD2_HI_U_NS_0,Window A Shadowed Higher 32 bits of Start Address for U plane"
|
|
bitfld.long 0x0C 0.--1. " A_START_ADDR_FIELD2_HI_U_NS ,Window A Shadowed Higher 2 bits of Start Address for U plane" "0,1,2,3"
|
|
line.long 0x10 "START_ADDR_FIELD2_HI_V_0,Window A Higher 2 bits of Start Address for V plane"
|
|
bitfld.long 0x10 0.--1. " A_START_ADDR_FIELD2_HI_V ,Window A Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
line.long 0x14 "START_ADDR_FIELD2_HI_V_NS_0,Window A Shadowed Higher 2 bits of Start Address for V plane"
|
|
bitfld.long 0x14 0.--1. " A_START_ADDR_FIELD2_HI_V_NS ,Window A Shadowed Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
group.long 0x207C++0x0F
|
|
line.long 0x00 "ADDR_H_OFFSET_FIELD2_0,Window A Horizontal address offset"
|
|
line.long 0x04 "ADDR_H_OFFSET_FIELD2_NS_0,Window A Shadowed Horizontal address offset"
|
|
line.long 0x08 "ADDR_V_OFFSET_FIELD2_0,Window A Vertical address offset"
|
|
line.long 0x0C "ADDR_V_OFFSET_FIELD2_NS_0,Window A Shadowed Vertical address offset"
|
|
group.long 0x2090++0x03
|
|
line.long 0x00 "UFLOW_CTRL_0,DC WINBUF A UFLOW CTRL 0"
|
|
bitfld.long 0x00 0. " A_UFLOW_CTRL_DBG_MODE ,A UFLOW CTRL DBG MODE" "Disabled,Enabled"
|
|
textline " "
|
|
width 25.
|
|
group.long 0x2094++0x27
|
|
line.long 0x00 "UFLOW_DBG_PIXEL_0,DC WINBUF A UFLOW DBG PIXEL 0"
|
|
line.long 0x04 "UFLOW_THRESHOLD_0,DC WINBUF A UFLOW THRESHOLD 0"
|
|
hexmask.long.word 0x04 0.--12. 1. " A_UFLOW_THRESHOLD ,A UFLOW THRESHOLD"
|
|
line.long 0x08 "SPOOL_UP_0,Spool up time configuration for different windows related logic"
|
|
hexmask.long.word 0x08 16.--28. 1. " A_SPOOL_UP_DURATION ,A SPOOL UP DURATION"
|
|
bitfld.long 0x08 1. " A_SPOOL_UP_EDGE ,A SPOOL UP EDGE" "NEGEDGE,POSEDGE"
|
|
bitfld.long 0x08 0. " A_SPOOL_UP_CTRL ,A SPOOL UP CTRL" "MAX,PROGRAMMABLE"
|
|
line.long 0x0C "SCALEFACTOR_THRESHOLD_0,DC WINBUF A SCALEFACTOR THRESHOLD 0"
|
|
hexmask.long.word 0x0C 16.--31. 1. " A_SF_LWM_THRESHOLD ,A SF LWM THRESHOLD"
|
|
hexmask.long.word 0x0C 0.--15. 1. " A_SF_HWM_THRESHOLD ,A SF HWM THRESHOLD"
|
|
line.long 0x10 "LATENCY_THRESHOLD_0,Register controls the behavior of the rdy4_latency_event from the display to the MC"
|
|
bitfld.long 0x10 31. " A_RDY4LATENCY_THRESHOLD_ENABLE ,A RDY4LATENCY THRESHOLD ENABLE" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " A_RDY4LATENCY_SPOOLUP_CTRL ,A RDY4LATENCY SPOOLUP CTRL" "DISALLOW,ALLOW"
|
|
textline " "
|
|
hexmask.long.word 0x10 16.--28. 1. " A_RDY4LATENCY_SPOOLUP_DURATION ,A RDY4LATENCY THRESHOLD"
|
|
hexmask.long.word 0x10 0.--15. 1. " A_RDY4LATENCY_THRESHOLD ,A RDY4LATENCY THRESHOLD"
|
|
line.long 0x14 "MEMFETCH_DEBUG_STATUS_0,Memfetch Debug Status"
|
|
bitfld.long 0x14 16. " A_DEBUG_ENABLE ,Reg to enable FGCG for flops added to debug signals in memfetch" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " B_ALIGN_FIFO_NON_IDLE ,Align FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 13. " B_PIPE0_FIFO_NON_IDLE ,Pipe0 FIFO idle at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 12. " B_FRAME_FIFO_NON_IDLE ,Frame FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 11. " B_SURFACE_FIFO_NON_IDLE ,Surface FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 10. " B_TAG_FIFO_NON_IDLE ,Tag FIFO idle at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 9. " B_RSP_FIFO_NON_IDLE ,Response FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 8. " B_REQ_FIFO_NON_IDLE ,Request FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 7. " B_DP_VALID_NON_IDLE ,DP lines valid at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 6. " B_V_SSM_NON_IDLE ,V SSM is non-idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 5. " B_U_SSM_NON_IDLE ,U SSM is non-idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 4. " B_Y_SSM_NON_IDLE ,Y SSM is non-idle at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 3. " B_DP_POOL_AVAIL ,DP thinks there is data in the pool at end of frame" "No data,Data"
|
|
bitfld.long 0x14 2. " B_POOL_NOT_EMPTY ,Status of pool at end of frame" "Empty,Not empty"
|
|
bitfld.long 0x14 1. " B_UNDERFLOW_LINE1 ,Underflow of line0" "No underflow,Line0 underflowed"
|
|
textline " "
|
|
bitfld.long 0x14 0. " B_UNDERFLOW_LINE0 ,Underflow of line0" "No underflow,Line0 underflowed"
|
|
line.long 0x18 "MEMFETCH_CONTROL_0,Memfetch Control Register"
|
|
bitfld.long 0x18 1. " A_MEMFETCH_CLK_GATE_OVERRIDE ,Disable clock-gating of memfetch for a controller" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " A_MEMFETCH_RESET ,Reset memfetch for a controller" "Disabled,Enabled"
|
|
line.long 0x1C "OCCUPANCY_THROTTLE_0,DC WINBUF A OCCUPANCY THROTTLE 0"
|
|
hexmask.long.word 0x1C 16.--31. 1. " A_OCCUPANCY_MAX_THRESHOLD ,A OCCUPANCY MAX THRESHOLD"
|
|
bitfld.long 0x1C 0. " A_OCCUPANCY_THROTTLE_MODE ,A OCCUPANCY THROTTLE MODE" "Disabled,Enabled"
|
|
line.long 0x20 "SCRATCH_REGISTER_0_0,DC WINBUF A SCRATCH REGISTER 0 0"
|
|
line.long 0x24 "SCRATCH_REGISTER_1_0,DC WINBUF A SCRATCH REGISTER 1 0"
|
|
tree.end
|
|
width 19.
|
|
tree "Window B Registers"
|
|
wgroup.long 0x1400++0x03
|
|
line.long 0x00 "COLOR_PALETTE_0,Window B Color Palette"
|
|
button "BGR" "d (ad:0x54200000+0x1400)--(ad:0x54200000+0x17fc) /long"
|
|
group.long 0x1800++0x03
|
|
line.long 0x00 "PALETTE_COLOR_EXT_0,Window B Palette Color Extension"
|
|
hexmask.long.byte 0x00 1.--7. 1. " B_PALETTE_COLOR_EXT ,Window B Palette Color Extension"
|
|
group.long 0x1804++0x03
|
|
line.long 0x00 "H_FILTER_P00_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P00C5 ,Phase 00 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P00C4 ,Phase 00 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P00C3 ,Phase 00 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 00 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P00C1 ,Phase 00 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P00C0 ,Phase 00 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1808++0x03
|
|
line.long 0x00 "H_FILTER_P01_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P01C5 ,Phase 01 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P01C4 ,Phase 01 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P01C3 ,Phase 01 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 01 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P01C1 ,Phase 01 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P01C0 ,Phase 01 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x180C++0x03
|
|
line.long 0x00 "H_FILTER_P02_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P02C5 ,Phase 02 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P02C4 ,Phase 02 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P02C3 ,Phase 02 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 02 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P02C1 ,Phase 02 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P02C0 ,Phase 02 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1810++0x03
|
|
line.long 0x00 "H_FILTER_P03_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P03C5 ,Phase 03 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P03C4 ,Phase 03 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P03C3 ,Phase 03 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 03 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P03C1 ,Phase 03 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P03C0 ,Phase 03 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1814++0x03
|
|
line.long 0x00 "H_FILTER_P04_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P04C5 ,Phase 04 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P04C4 ,Phase 04 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P04C3 ,Phase 04 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 04 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P04C1 ,Phase 04 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P04C0 ,Phase 04 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1818++0x03
|
|
line.long 0x00 "H_FILTER_P05_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P05C5 ,Phase 05 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P05C4 ,Phase 05 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P05C3 ,Phase 05 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 05 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P05C1 ,Phase 05 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 0.--2. " B_H_FILTER_P05C0 ,Phase 05 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x181C++0x03
|
|
line.long 0x00 "H_FILTER_P06_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P06C5 ,Phase 06 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P06C4 ,Phase 06 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P06C3 ,Phase 06 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 06 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P06C1 ,Phase 06 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P06C0 ,Phase 06 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1820++0x03
|
|
line.long 0x00 "H_FILTER_P07_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P07C5 ,Phase 07 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P07C4 ,Phase 07 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P07C3 ,Phase 07 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 07 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P07C1 ,Phase 07 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P07C0 ,Phase 07 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1824++0x03
|
|
line.long 0x00 "H_FILTER_P08_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P08C5 ,Phase 08 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P08C4 ,Phase 08 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P08C3 ,Phase 08 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 08 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P08C1 ,Phase 08 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P08C0 ,Phase 08 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1828++0x03
|
|
line.long 0x00 "H_FILTER_P09_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P09C5 ,Phase 09 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P09C4 ,Phase 09 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P09C3 ,Phase 09 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 09 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P09C1 ,Phase 09 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P09C0 ,Phase 09 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x182C++0x03
|
|
line.long 0x00 "H_FILTER_P0A_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P0AC5 ,Phase 0A coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P0AC4 ,Phase 0A coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P0AC3 ,Phase 0A coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 0A coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P0AC1 ,Phase 0A coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P0AC0 ,Phase 0A coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1830++0x03
|
|
line.long 0x00 "H_FILTER_P0B_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P0BC5 ,Phase 0B coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P0BC4 ,Phase 0B coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P0BC3 ,Phase 0B coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 0B coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P0BC1 ,Phase 0B coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P0BC0 ,Phase 0B coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1834++0x03
|
|
line.long 0x00 "H_FILTER_P0C_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P0CC5 ,Phase 0C coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P0CC4 ,Phase 0C coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P0CC3 ,Phase 0C coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 0C coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P0CC1 ,Phase 0C coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P0CC0 ,Phase 0C coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1838++0x03
|
|
line.long 0x00 "H_FILTER_P0D_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P0DC5 ,Phase 0D coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P0DC4 ,Phase 0D coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P0DC3 ,Phase 0D coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 0D coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P0DC1 ,Phase 0D coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P0DC0 ,Phase 0D coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x183C++0x03
|
|
line.long 0x00 "H_FILTER_P0E_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P0EC5 ,Phase 0E coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P0EC4 ,Phase 0E coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P0EC3 ,Phase 0E coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 0E coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P0EC1 ,Phase 0E coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P0EC0 ,Phase 0E coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1840++0x03
|
|
line.long 0x00 "H_FILTER_P0F_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P0FC5 ,Phase 0F coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P0FC4 ,Phase 0F coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P0FC3 ,Phase 0F coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 0F coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P0FC1 ,Phase 0F coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P0FC0 ,Phase 0F coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1844++0x1F
|
|
line.long 0x00 "CSC_YOF_0,Colour Space Conversion Coefficients"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_CSC_YOF ,Y Offset in s.7.0 format"
|
|
line.long 0x04 "CSC_KYRGB_0,Window B CSC Y Coefficient for RGB"
|
|
hexmask.long.word 0x04 0.--9. 1. " B_CSC_KYRGB ,Y Gain for R, G, B colours in 2.8 format"
|
|
line.long 0x08 "CSC_KUR_0,Window B CSC U coefficient for R"
|
|
hexmask.long.word 0x08 0.--10. 1. " B_CSC_KUR ,U coefficients for R in s.2.8 format"
|
|
line.long 0x0C "CSC_KVR_0,Window B CSC V coefficient for R"
|
|
hexmask.long.word 0x0C 0.--10. 1. " B_CSC_KVR ,V coefficients for R in s.2.8 format"
|
|
line.long 0x10 "CSC_KUG_0,Window B CSC U coefficient for G"
|
|
hexmask.long.word 0x10 0.--9. 1. " B_CSC_KUG ,U coefficients for G in s.1.8 format"
|
|
line.long 0x14 "CSC_KVG_0,Window B CSC V coefficient for G"
|
|
hexmask.long.word 0x14 0.--9. 1. " B_CSC_KVG ,V coefficients for G in s.1.8 format"
|
|
line.long 0x18 "CSC_KUB_0,Window B CSC U coefficient for B"
|
|
hexmask.long.word 0x18 0.--10. 1. " B_CSC_KUB ,U coefficients for B in s.2.8 format"
|
|
line.long 0x1C "CSC_KVB_0,Window B CSC V coefficient for B"
|
|
hexmask.long.word 0x1C 0.--10. 1. " B_CSC_KVB ,V coefficients for B in s.2.8 format"
|
|
textline " "
|
|
group.long 0x1864++0x03
|
|
line.long 0x00 "V_FILTER_P00_0,Window B Vertical Filter phase 00"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P00C0 ,Phase 00 coefficient 0"
|
|
group.long 0x1868++0x03
|
|
line.long 0x00 "V_FILTER_P01_0,Window B Vertical Filter phase 01"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P01C0 ,Phase 01 coefficient 1"
|
|
group.long 0x186C++0x03
|
|
line.long 0x00 "V_FILTER_P02_0,Window B Vertical Filter phase 02"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P02C0 ,Phase 02 coefficient 2"
|
|
group.long 0x1870++0x03
|
|
line.long 0x00 "V_FILTER_P03_0,Window B Vertical Filter phase 03"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P03C0 ,Phase 03 coefficient 3"
|
|
group.long 0x1874++0x03
|
|
line.long 0x00 "V_FILTER_P04_0,Window B Vertical Filter phase 04"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P04C0 ,Phase 04 coefficient 4"
|
|
group.long 0x1878++0x03
|
|
line.long 0x00 "V_FILTER_P05_0,Window B Vertical Filter phase 05"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P05C0 ,Phase 05 coefficient 5"
|
|
group.long 0x187C++0x03
|
|
line.long 0x00 "V_FILTER_P06_0,Window B Vertical Filter phase 06"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P06C0 ,Phase 06 coefficient 6"
|
|
group.long 0x1880++0x03
|
|
line.long 0x00 "V_FILTER_P07_0,Window B Vertical Filter phase 07"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P07C0 ,Phase 07 coefficient 7"
|
|
group.long 0x1884++0x03
|
|
line.long 0x00 "V_FILTER_P08_0,Window B Vertical Filter phase 08"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P08C0 ,Phase 08 coefficient 8"
|
|
group.long 0x1888++0x03
|
|
line.long 0x00 "V_FILTER_P09_0,Window B Vertical Filter phase 09"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P09C0 ,Phase 09 coefficient 9"
|
|
group.long 0x188C++0x03
|
|
line.long 0x00 "V_FILTER_P0A_0,Window B Vertical Filter phase 0A"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P0AC0 ,Phase 0A coefficient A"
|
|
group.long 0x1890++0x03
|
|
line.long 0x00 "V_FILTER_P0B_0,Window B Vertical Filter phase 0B"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P0BC0 ,Phase 0B coefficient B"
|
|
group.long 0x1894++0x03
|
|
line.long 0x00 "V_FILTER_P0C_0,Window B Vertical Filter phase 0C"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P0CC0 ,Phase 0C coefficient C"
|
|
group.long 0x1898++0x03
|
|
line.long 0x00 "V_FILTER_P0D_0,Window B Vertical Filter phase 0D"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P0DC0 ,Phase 0D coefficient D"
|
|
group.long 0x189C++0x03
|
|
line.long 0x00 "V_FILTER_P0E_0,Window B Vertical Filter phase 0E"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P0EC0 ,Phase 0E coefficient E"
|
|
group.long 0x18A0++0x03
|
|
line.long 0x00 "V_FILTER_P0F_0,Window B Vertical Filter phase 0F"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P0FC0 ,Phase 0F coefficient F"
|
|
textline " "
|
|
group.long 0x18A4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P00_0,Window B Horizontal Filter phase 00"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P00C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P00C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P00C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P00C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P00C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P00C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18A8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P01_0,Window B Horizontal Filter phase 01"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P01C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P01C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P01C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P01C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P01C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P01C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18AC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P02_0,Window B Horizontal Filter phase 02"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P02C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P02C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P02C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P02C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P02C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P02C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18B0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P03_0,Window B Horizontal Filter phase 03"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P03C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P03C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P03C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P03C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P03C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P03C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18B4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P04_0,Window B Horizontal Filter phase 04"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P04C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P04C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P04C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P04C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P04C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P04C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18B8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P05_0,Window B Horizontal Filter phase 05"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P05C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P05C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P05C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P05C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P05C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P05C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18BC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P06_0,Window B Horizontal Filter phase 06"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P06C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P06C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P06C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P06C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P06C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P06C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18C0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P07_0,Window B Horizontal Filter phase 07"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P07C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P07C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P07C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P07C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P07C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P07C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18C4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P08_0,Window B Horizontal Filter phase 08"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P08C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P08C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P08C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P08C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P08C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P08C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18C8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P09_0,Window B Horizontal Filter phase 09"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P09C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P09C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P09C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P09C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P09C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P09C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18CC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0A_0,Window B Horizontal Filter phase 0A"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P0AC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P0AC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P0AC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P0AC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P0AC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P0AC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18D0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0B_0,Window B Horizontal Filter phase 0B"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P0BC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P0BC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P0BC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P0BC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P0BC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P0BC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18D4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0C_0,Window B Horizontal Filter phase 0C"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P0CC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P0CC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P0CC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P0CC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P0CC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P0CC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18D8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0D_0,Window B Horizontal Filter phase 0D"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P0DC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P0DC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P0DC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P0DC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P0DC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P0DC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18DC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0E_0,Window B Horizontal Filter phase 0E"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P0EC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P0EC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P0EC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P0EC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P0EC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P0EC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18E0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0F_0,Window B Horizontal Filter phase 0F"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P0FC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P0FC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P0FC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P0FC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P0FC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P0FC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
textline " "
|
|
width 15.
|
|
if (((d.l(ad:0x54200000+0x1C00))&0x400)==0x400)
|
|
group.long 0x1C00++0x03
|
|
line.long 0x00 "WIN_OPTIONS_0,Window B Options"
|
|
bitfld.long 0x00 31. " B_H_FILTER_MODE ,Horizontal filter mode" "Old,New"
|
|
bitfld.long 0x00 30. " B_WIN_ENABLE ,Window B Window enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " B_INTERLACE_ENABLE ,Window B Interlace enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " B_YUV_RANGE_EXPAND ,Window B Enable range expansion" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " B_DV_ENABLE ,Window B Digital Vibrance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " B_CSC_ENABLE ,Window B Color Space Conversion Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " B_CP_ENABLE ,Window B Color Palette Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " B_V_FILTER_UV_ALIGN ,Window B V Filter UV Alignment" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " B_V_FILTER_OPTIMIZE ,Window B V Filter Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " B_V_FILTER_ENABLE ,Window B V Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " B_H_FILTER_ENABLE ,Window B H Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " B_COLOR_EXPAND ,Color expansion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_SCAN_COLUMN ,Window B Scanning direction" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " B_V_DIRECTION ,Window B Vertical (Y) drawing Direction" "Increment,Decrement"
|
|
bitfld.long 0x00 0. " B_H_DIRECTION ,Window B Horizontal (X) drawing Direction" "Increment,Decrement"
|
|
else
|
|
group.long 0x1C00++0x03
|
|
line.long 0x00 "WIN_OPTIONS_0,Window B Options"
|
|
bitfld.long 0x00 31. " B_H_FILTER_MODE ,Horizontal filter mode" "Old,New"
|
|
bitfld.long 0x00 30. " B_WIN_ENABLE ,Window B Window enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " B_INTERLACE_ENABLE ,Window B Interlace enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " B_YUV_RANGE_EXPAND ,Window B Enable range expansion" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " B_DV_ENABLE ,Window B Digital Vibrance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " B_CSC_ENABLE ,Window B Color Space Conversion Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " B_CP_ENABLE ,Window B Color Palette Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " B_V_FILTER_ENABLE ,Window B V Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " B_H_FILTER_ENABLE ,Window B H Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " B_COLOR_EXPAND ,Color expansion" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " B_SCAN_COLUMN ,Window B Scanning direction" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " B_V_DIRECTION ,Window B Vertical (Y) drawing Direction" "Increment,Decrement"
|
|
textline " "
|
|
bitfld.long 0x00 0. " B_H_DIRECTION ,Window B Horizontal (X) drawing Direction" "Increment,Decrement"
|
|
endif
|
|
group.long 0x1C04++0x03
|
|
line.long 0x00 "BYTE_SWAP_0,Window B Byte Swap"
|
|
bitfld.long 0x00 0.--2. " B_BYTE_SWAP ,Window B Byte Swap" "NOSWAP,SWAP2,SWAP4,SWAP4HW,SWAP02,SWAPLEFT,,"
|
|
group.long 0x1C0C++0x03
|
|
line.long 0x00 "COLOR_DEPTH_0,Window B Color depth"
|
|
hexmask.long.byte 0x00 0.--6. 1. " B_COLOR_DEPTH ,Window B Color Depth"
|
|
width 18.
|
|
textline " "
|
|
group.long 0x1C10++0x03
|
|
line.long 0x00 "POSITION_0,Window B Position"
|
|
hexmask.long.word 0x00 16.--28. 1. " B_V_POSITION ,Window B V Position"
|
|
hexmask.long.word 0x00 0.--12. 1. " B_H_POSITION ,Window B H Position"
|
|
group.long 0x1C14++0x03
|
|
line.long 0x00 "SIZE_0,Window B Size"
|
|
hexmask.long.word 0x00 16.--28. 1. " B_V_SIZE ,Vertical size after scaling"
|
|
hexmask.long.word 0x00 0.--12. 1. " B_H_SIZE ,Horizontal size after scaling"
|
|
group.long 0x1C18++0x03
|
|
line.long 0x00 "PRESCALED_SIZE_0,Window B Pre-scaled Size"
|
|
hexmask.long.word 0x00 16.--28. 1. " B_V_PRESCALED_SIZE ,Window B V Pre-scaled Size"
|
|
hexmask.long.word 0x00 0.--14. 1. " B_H_PRESCALED_SIZE ,Window B H Pre-scaled Size"
|
|
group.long 0x1C1C++0x03
|
|
line.long 0x00 "H_INITIAL_DDA_0,Window B H Initial DDA"
|
|
hexmask.long.word 0x00 0.--15. 1. " B_H_INITIAL_DDA ,Window B H Initial DDA"
|
|
group.long 0x1C20++0x03
|
|
line.long 0x00 "V_INITIAL_DDA_0,Window B V Initial DDA"
|
|
hexmask.long.word 0x00 0.--15. 1. " B_V_INITIAL_DDA ,Window B V Initial DDA"
|
|
group.long 0x1C24++0x03
|
|
line.long 0x00 "DDA_INCREMENT_0,Window B DDA Increment"
|
|
hexmask.long.word 0x00 16.--31. 1. " B_V_DDA_INCREMENT ,Window B Vertical DDA Increment"
|
|
hexmask.long.word 0x00 0.--15. 1. " B_H_DDA_INCREMENT ,Window B Horizontal DDA Increment"
|
|
group.long 0x1C28++0x03
|
|
line.long 0x00 "LINE_STRIDE_0,Window B Line Stride"
|
|
hexmask.long.word 0x00 16.--31. 1. " B_UV_LINE_STRIDE ,Window B Line Stride for Chroma"
|
|
hexmask.long.word 0x00 0.--15. 1. " B_LINE_STRIDE ,Window B Line Stride"
|
|
group.long 0x1C38++0x03
|
|
line.long 0x00 "DV_CONTROL_0,Window B Digital Vibrance Control"
|
|
bitfld.long 0x00 16.--18. " B_DV_CONTROL_B ,Digital Vibrance control for B" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " B_DV_CONTROL_G ,Digital Vibrance control for G" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " B_DV_CONTROL_R ,Digital Vibrance control for R" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
width 24.
|
|
group.long 0x1C58++0x0F
|
|
line.long 0x00 "BLEND_LAYER_CONTROL_0,Window B"
|
|
bitfld.long 0x00 25.--27. " B_COLOR_KEY_SELECT ,B COLOR KEY SELECT" "0,1,2,3,4,5,6,7"
|
|
eventfld.long 0x00 24. " B_BLEND_BYPASS ,B BLEND BYPASS" "BLEND_ENABLE,BLEND_BYPASS"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_K2 ,B K2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_K1 ,B K1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_WINDOW_LAYER_DEPTH ,B window layer depth"
|
|
line.long 0x04 "BLEND_MATCH_SELECT_0,DC WIN B BLEND MATCH SELECT 0"
|
|
bitfld.long 0x04 12.--13. " B_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT ,B blend factor dst alpha match select" "0,1,EG_K1_TIMES_SRC,K2"
|
|
bitfld.long 0x04 8.--9. " B_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT ,B blend factor src alpha match select" "0,K1,K2,"
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " B_BLEND_FACTOR_DST_COLOR_MATCH_SELECT ,B blend factor dst color match select" "0,1,K1,K2,K1_TIMES_DST,NEG_K1_TIMES_DST,NEG_K1_TIMES_SRC,NEG_K1"
|
|
bitfld.long 0x04 0.--2. " B_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT ,B blend factor src color match select" "0,1,K1,K1_TIMES_DST,NEG_K1_TIMES_DST,K1_TIMES_SRC,,"
|
|
line.long 0x08 "BLEND_NOMATCH_SELECT_0,DC WIN B BLEND NOMATCH SELECT 0"
|
|
bitfld.long 0x08 12.--13. " B_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT ,B blend factor dst alpha nomatch select" "0,1,EG_K1_TIMES_SRC,K2"
|
|
bitfld.long 0x08 8.--9. " B_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT ,B blend factor src alpha nomatch select" "0,K1,K2,"
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " B_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT ,B blend factor dst color nomatch select" "0,1,K1,K2,K1_TIMES_DST,NEG_K1_TIMES_DST,NEG_K1_TIMES_SRC,NEG_K1"
|
|
bitfld.long 0x08 0.--2. " B_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT ,B blend factor src color nomatch select" "0,1,K1,K1_TIMES_DST,NEG_K1_TIMES_DST,K1_TIMES_SRC,,"
|
|
line.long 0x0C "BLEND_ALPHA_1BIT_0,Win B blend alpha 1bit 0"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " B_BLEND_WEIGHT1 ,Alpha value of 1"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " B_BLEND_WEIGHT0 ,Alpha value of 0"
|
|
tree.end
|
|
width 19.
|
|
tree "WINBUF_B Registers"
|
|
group.long 0x2000++0x27
|
|
line.long 0x00 "START_ADDR_0,Window B Start Address"
|
|
line.long 0x04 "START_ADDR_NS_0,Window B Shadowed Start Address"
|
|
line.long 0x08 "START_ADDR_U_0,Window B Start Address for U plane"
|
|
line.long 0x0C "START_ADDR_U_NS_0,Window B Shadowed Start Address for U plane"
|
|
line.long 0x10 "START_ADDR_V_0,Window B Start Address for V plane"
|
|
line.long 0x14 "START_ADDR_V_NS_0,WWindow B Shadowed Start Address for V plane"
|
|
line.long 0x18 "ADDR_H_OFFSET_0,Window B Horizontal Address Offset"
|
|
line.long 0x1C "ADDR_H_OFFSET_NS_0,Window B Shadowed Horizontal Address Offset"
|
|
line.long 0x20 "ADDR_V_OFFSET_0,Window B Vertical Address Offset"
|
|
line.long 0x24 "ADDR_V_OFFSET_NS_0,Window B Shadowed Vertical Address Offset"
|
|
group.long 0x2028++0x0B
|
|
line.long 0x00 "UFLOW_STATUS,Window B FIFO Underflow Status Register"
|
|
bitfld.long 0x00 30. " COUNT_OFLOW ,Counter has overflowed" "Not occurred,Occurred"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " UFLOW_COUNT ,Underflow count"
|
|
line.long 0x04 "SURFACE_KIND_0,Window B Surface Kind"
|
|
bitfld.long 0x04 4.--6. " B_BLOCK_HEIGHT ,Block Height" "HEIGHT_1,HEIGHT_2,HEIGHT_4,HEIGHT_8,HEIGHT_16,HEIGHT_32,,"
|
|
bitfld.long 0x04 0.--1. " B_SURFACE_KIND ,Surface kind" "PITCH,TILED,BL_16B2,"
|
|
line.long 0x08 "SURFACE_WEIGHT_0,Window B Surface Weights"
|
|
bitfld.long 0x08 5.--6. " B_SURFACE_WEIGHT_V ,Window B V Surface Weights" "2,4,8,16"
|
|
bitfld.long 0x08 3.--4. " B_SURFACE_WEIGHT_U ,Window B U or UV Surface Weights" "2,4,8,16"
|
|
bitfld.long 0x08 1.--2. " B_SURFACE_WEIGHT_Y ,Window B Y or packed Surface Weights" "2,4,8,16"
|
|
textline " "
|
|
bitfld.long 0x08 0. " B_SURFACE_WEIGHT_OVERRIDE ,Weight Override" "Disabled,Enabled"
|
|
textline " "
|
|
width 22.
|
|
group.long 0x2034++0x17
|
|
line.long 0x00 "START_ADDR_HI_0,Window B Higher 2 bits of Start Address"
|
|
bitfld.long 0x00 0.--1. " B_START_ADDR_HI ,Window B Start Address" "0,1,2,3"
|
|
line.long 0x04 "START_ADDR_HI_NS_0,Window B Higher 2 bits of Start Address"
|
|
bitfld.long 0x04 0.--1. " B_START_ADDR_HI_NS ,Window B Shadowed Start Address" "0,1,2,3"
|
|
line.long 0x08 "START_ADDR_HI_U_0,Window B Higher 2 bits of Start Address"
|
|
bitfld.long 0x08 0.--1. " B_START_ADDR_HI ,Window B Start Address" "0,1,2,3"
|
|
line.long 0x0C "START_ADDR_HI_U_NS_0,Window B Shadowed Higher 2 bits of Start Address for U Plane"
|
|
bitfld.long 0x0C 0.--1. " B_START_ADDR_HI_U_NS ,Window B Shadowed Higher 2 bits of Start Address for U plane" "0,1,2,3"
|
|
line.long 0x10 "START_ADDR_HI_V_0,Window B Higher 2 bits of Start Address for V Plane"
|
|
bitfld.long 0x10 0.--1. " B_START_ADDR_HI_V ,Window B Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
line.long 0x14 "START_ADDR_HI_V_NS_0,Window B Shadowed Higher 2 bits of Start Address for V Plane"
|
|
bitfld.long 0x14 0.--1. " B_START_ADDR_HI_V_NS ,Window B Shadowed Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
textline " "
|
|
width 29.
|
|
group.long 0x204C++0x17
|
|
line.long 0x00 "START_ADDR_FIELD2_0,Window B Start Address"
|
|
line.long 0x04 "START_ADDR_FIELD2_NS_0,Window B Shadowed Start Address"
|
|
line.long 0x08 "START_ADDR_FIELD2_U_0,Window B Start Address for U plane"
|
|
line.long 0x0C "START_ADDR_FIELD2_U_NS_0,Window B Shadowed Start Address for U plane"
|
|
line.long 0x10 "START_ADDR_FIELD2_V_0,Window B Start Address for V plane"
|
|
line.long 0x14 "START_ADDR_FIELD2_V_NS_0,Window B Shadowed Start Address for V plane"
|
|
group.long 0x2064++0x17
|
|
line.long 0x00 "START_ADDR_FIELD2_HI_0,Window B Higher 2 bits of Start Address"
|
|
bitfld.long 0x00 0.--1. " B_START_ADDR_FIELD2_HI ,Window B Start Address" "0,1,2,3"
|
|
line.long 0x04 "START_ADDR_FIELD2_HI_NS_0,Window B Shadowed Higher 2 bits of Start Address"
|
|
bitfld.long 0x04 0.--1. " B_START_ADDR_FIELD2_HI_NS ,Window B Shadowed Start Address" "0,1,2,3"
|
|
line.long 0x08 "START_ADDR_FIELD2_HI_U_0,Window B Higher 2 bits of Start Address for U plane"
|
|
bitfld.long 0x08 0.--1. " B_START_ADDR_FIELD2_HI_U ,Window B Start Address for U plane" "0,1,2,3"
|
|
line.long 0x0C "START_ADDR_FIELD2_HI_U_NS_0,Window B Shadowed Higher 32 bits of Start Address for U plane"
|
|
bitfld.long 0x0C 0.--1. " B_START_ADDR_FIELD2_HI_U_NS ,Window B Shadowed Higher 2 bits of Start Address for U plane" "0,1,2,3"
|
|
line.long 0x10 "START_ADDR_FIELD2_HI_V_0,Window B Higher 2 bits of Start Address for V plane"
|
|
bitfld.long 0x10 0.--1. " B_START_ADDR_FIELD2_HI_V ,Window B Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
line.long 0x14 "START_ADDR_FIELD2_HI_V_NS_0,Window B Shadowed Higher 2 bits of Start Address for V plane"
|
|
bitfld.long 0x14 0.--1. " B_START_ADDR_FIELD2_HI_V_NS ,Window B Shadowed Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
group.long 0x207C++0x0F
|
|
line.long 0x00 "ADDR_H_OFFSET_FIELD2_0,Window B Horizontal address offset"
|
|
line.long 0x04 "ADDR_H_OFFSET_FIELD2_NS_0,Window B Shadowed Horizontal address offset"
|
|
line.long 0x08 "ADDR_V_OFFSET_FIELD2_0,Window B Vertical address offset"
|
|
line.long 0x0C "ADDR_V_OFFSET_FIELD2_NS_0,Window B Shadowed Vertical address offset"
|
|
group.long 0x2090++0x03
|
|
line.long 0x00 "UFLOW_CTRL_0,DC WINBUF B UFLOW CTRL 0"
|
|
bitfld.long 0x00 0. " B_UFLOW_CTRL_DBG_MODE ,B UFLOW CTRL DBG MODE" "Disabled,Enabled"
|
|
textline " "
|
|
width 25.
|
|
group.long 0x2094++0x27
|
|
line.long 0x00 "UFLOW_DBG_PIXEL_0,DC WINBUF B UFLOW DBG PIXEL 0"
|
|
line.long 0x04 "UFLOW_THRESHOLD_0,DC WINBUF B UFLOW THRESHOLD 0"
|
|
hexmask.long.word 0x04 0.--12. 1. " B_UFLOW_THRESHOLD ,B UFLOW THRESHOLD"
|
|
line.long 0x08 "SPOOL_UP_0,Spool up time configuration for different windows related logic"
|
|
hexmask.long.word 0x08 16.--28. 1. " B_SPOOL_UP_DURATION ,B SPOOL UP DURATION"
|
|
bitfld.long 0x08 1. " B_SPOOL_UP_EDGE ,B SPOOL UP EDGE" "NEGEDGE,POSEDGE"
|
|
bitfld.long 0x08 0. " B_SPOOL_UP_CTRL ,B SPOOL UP CTRL" "MAX,PROGRAMMABLE"
|
|
line.long 0x0C "SCALEFACTOR_THRESHOLD_0,DC WINBUF B SCALEFACTOR THRESHOLD 0"
|
|
hexmask.long.word 0x0C 16.--31. 1. " B_SF_LWM_THRESHOLD ,B SF LWM THRESHOLD"
|
|
hexmask.long.word 0x0C 0.--15. 1. " B_SF_HWM_THRESHOLD ,B SF HWM THRESHOLD"
|
|
line.long 0x10 "LATENCY_THRESHOLD_0,Register controls the behavior of the rdy4_latency_event from the display to the MC"
|
|
bitfld.long 0x10 31. " B_RDY4LATENCY_THRESHOLD_ENABLE ,B RDY4LATENCY THRESHOLD ENABLE" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " B_RDY4LATENCY_SPOOLUP_CTRL ,B RDY4LATENCY SPOOLUP CTRL" "DISALLOW,ALLOW"
|
|
textline " "
|
|
hexmask.long.word 0x10 16.--28. 1. " B_RDY4LATENCY_SPOOLUP_DURATION ,B RDY4LATENCY THRESHOLD"
|
|
hexmask.long.word 0x10 0.--15. 1. " B_RDY4LATENCY_THRESHOLD ,B RDY4LATENCY THRESHOLD"
|
|
line.long 0x14 "MEMFETCH_DEBUG_STATUS_0,Memfetch Debug Status"
|
|
bitfld.long 0x14 16. " B_DEBUG_ENABLE ,Reg to enable FGCG for flops added to debug signals in memfetch" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " B_ALIGN_FIFO_NON_IDLE ,Align FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 13. " B_PIPE0_FIFO_NON_IDLE ,Pipe0 FIFO idle at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 12. " B_FRAME_FIFO_NON_IDLE ,Frame FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 11. " B_SURFACE_FIFO_NON_IDLE ,Surface FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 10. " B_TAG_FIFO_NON_IDLE ,Tag FIFO idle at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 9. " B_RSP_FIFO_NON_IDLE ,Response FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 8. " B_REQ_FIFO_NON_IDLE ,Request FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 7. " B_DP_VALID_NON_IDLE ,DP lines valid at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 6. " B_V_SSM_NON_IDLE ,V SSM is non-idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 5. " B_U_SSM_NON_IDLE ,U SSM is non-idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 4. " B_Y_SSM_NON_IDLE ,Y SSM is non-idle at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 3. " B_DP_POOL_AVAIL ,DP thinks there is data in the pool at end of frame" "No data,Data"
|
|
bitfld.long 0x14 2. " B_POOL_NOT_EMPTY ,Status of pool at end of frame" "Empty,Not empty"
|
|
bitfld.long 0x14 1. " B_UNDERFLOW_LINE1 ,Underflow of line0" "No underflow,Line0 underflowed"
|
|
textline " "
|
|
bitfld.long 0x14 0. " B_UNDERFLOW_LINE0 ,Underflow of line0" "No underflow,Line0 underflowed"
|
|
line.long 0x18 "MEMFETCH_CONTROL_0,Memfetch Control Register"
|
|
bitfld.long 0x18 1. " B_MEMFETCH_CLK_GATE_OVERRIDE ,Disable clock-gating of memfetch for a controller" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " B_MEMFETCH_RESET ,Reset memfetch for a controller" "Disabled,Enabled"
|
|
line.long 0x1C "OCCUPANCY_THROTTLE_0,DC WINBUF B OCCUPANCY THROTTLE 0"
|
|
hexmask.long.word 0x1C 16.--31. 1. " B_OCCUPANCY_MAX_THRESHOLD ,B OCCUPANCY MAX THRESHOLD"
|
|
bitfld.long 0x1C 0. " B_OCCUPANCY_THROTTLE_MODE ,B OCCUPANCY THROTTLE MODE" "Disabled,Enabled"
|
|
line.long 0x20 "SCRATCH_REGISTER_0_0,DC WINBUF B SCRATCH REGISTER 0 0"
|
|
line.long 0x24 "SCRATCH_REGISTER_1_0,DC WINBUF B SCRATCH REGISTER 1 0"
|
|
tree.end
|
|
width 19.
|
|
tree "Window C Registers"
|
|
wgroup.long 0x1400++0x03
|
|
line.long 0x00 "COLOR_PALETTE_0,Window C Color Palette"
|
|
button "BGR" "d (ad:0x54200000+0x1400)--(ad:0x54200000+0x17fc) /long"
|
|
group.long 0x1800++0x03
|
|
line.long 0x00 "PALETTE_COLOR_EXT_0,Window C Palette Color Extension"
|
|
hexmask.long.byte 0x00 1.--7. 1. " C_PALETTE_COLOR_EXT ,Window C Palette Color Extension"
|
|
group.long 0x1804++0x03
|
|
line.long 0x00 "H_FILTER_P00_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P00C5 ,Phase 00 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P00C4 ,Phase 00 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P00C3 ,Phase 00 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 00 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P00C1 ,Phase 00 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P00C0 ,Phase 00 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1808++0x03
|
|
line.long 0x00 "H_FILTER_P01_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P01C5 ,Phase 01 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P01C4 ,Phase 01 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P01C3 ,Phase 01 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 01 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P01C1 ,Phase 01 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P01C0 ,Phase 01 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x180C++0x03
|
|
line.long 0x00 "H_FILTER_P02_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P02C5 ,Phase 02 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P02C4 ,Phase 02 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P02C3 ,Phase 02 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 02 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P02C1 ,Phase 02 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P02C0 ,Phase 02 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1810++0x03
|
|
line.long 0x00 "H_FILTER_P03_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P03C5 ,Phase 03 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P03C4 ,Phase 03 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P03C3 ,Phase 03 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 03 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P03C1 ,Phase 03 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P03C0 ,Phase 03 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1814++0x03
|
|
line.long 0x00 "H_FILTER_P04_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P04C5 ,Phase 04 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P04C4 ,Phase 04 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P04C3 ,Phase 04 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 04 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P04C1 ,Phase 04 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P04C0 ,Phase 04 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1818++0x03
|
|
line.long 0x00 "H_FILTER_P05_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P05C5 ,Phase 05 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P05C4 ,Phase 05 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P05C3 ,Phase 05 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 05 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P05C1 ,Phase 05 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P05C0 ,Phase 05 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x181C++0x03
|
|
line.long 0x00 "H_FILTER_P06_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P06C5 ,Phase 06 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P06C4 ,Phase 06 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P06C3 ,Phase 06 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 06 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P06C1 ,Phase 06 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P06C0 ,Phase 06 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1820++0x03
|
|
line.long 0x00 "H_FILTER_P07_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P07C5 ,Phase 07 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P07C4 ,Phase 07 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P07C3 ,Phase 07 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 07 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P07C1 ,Phase 07 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P07C0 ,Phase 07 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1824++0x03
|
|
line.long 0x00 "H_FILTER_P08_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P08C5 ,Phase 08 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P08C4 ,Phase 08 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P08C3 ,Phase 08 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 08 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P08C1 ,Phase 08 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P08C0 ,Phase 08 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1828++0x03
|
|
line.long 0x00 "H_FILTER_P09_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P09C5 ,Phase 09 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P09C4 ,Phase 09 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P09C3 ,Phase 09 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 09 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P09C1 ,Phase 09 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P09C0 ,Phase 09 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x182C++0x03
|
|
line.long 0x00 "H_FILTER_P0A_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P0AC5 ,Phase 0A coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P0AC4 ,Phase 0A coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P0AC3 ,Phase 0A coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 0A coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P0AC1 ,Phase 0A coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P0AC0 ,Phase 0A coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1830++0x03
|
|
line.long 0x00 "H_FILTER_P0B_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P0BC5 ,Phase 0B coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P0BC4 ,Phase 0B coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P0BC3 ,Phase 0B coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 0B coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P0BC1 ,Phase 0B coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P0BC0 ,Phase 0B coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1834++0x03
|
|
line.long 0x00 "H_FILTER_P0C_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P0CC5 ,Phase 0C coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P0CC4 ,Phase 0C coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P0CC3 ,Phase 0C coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 0C coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P0CC1 ,Phase 0C coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P0CC0 ,Phase 0C coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1838++0x03
|
|
line.long 0x00 "H_FILTER_P0D_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P0DC5 ,Phase 0D coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P0DC4 ,Phase 0D coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P0DC3 ,Phase 0D coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 0D coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P0DC1 ,Phase 0D coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P0DC0 ,Phase 0D coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x183C++0x03
|
|
line.long 0x00 "H_FILTER_P0E_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P0EC5 ,Phase 0E coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P0EC4 ,Phase 0E coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P0EC3 ,Phase 0E coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 0E coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P0EC1 ,Phase 0E coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P0EC0 ,Phase 0E coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1840++0x03
|
|
line.long 0x00 "H_FILTER_P0F_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P0FC5 ,Phase 0F coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P0FC4 ,Phase 0F coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P0FC3 ,Phase 0F coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 0F coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P0FC1 ,Phase 0F coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P0FC0 ,Phase 0F coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1844++0x1F
|
|
line.long 0x00 "CSC_YOF_0,Colour Space Conversion Coefficients"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_CSC_YOF ,Y Offset in s.7.0 format"
|
|
line.long 0x04 "CSC_KYRGB_0,Window C CSC Y Coefficient for RGB"
|
|
hexmask.long.word 0x04 0.--9. 1. " C_CSC_KYRGB ,Y Gain for R, G, B colours in 2.8 format"
|
|
line.long 0x08 "CSC_KUR_0,Window C CSC U coefficient for R"
|
|
hexmask.long.word 0x08 0.--10. 1. " C_CSC_KUR ,U coefficients for R in s.2.8 format"
|
|
line.long 0x0C "CSC_KVR_0,Window C CSC V coefficient for R"
|
|
hexmask.long.word 0x0C 0.--10. 1. " C_CSC_KVR ,V coefficients for R in s.2.8 format"
|
|
line.long 0x10 "CSC_KUG_0,Window C CSC U coefficient for G"
|
|
hexmask.long.word 0x10 0.--9. 1. " C_CSC_KUG ,U coefficients for G in s.1.8 format"
|
|
line.long 0x14 "CSC_KVG_0,Window C CSC V coefficient for G"
|
|
hexmask.long.word 0x14 0.--9. 1. " C_CSC_KVG ,V coefficients for G in s.1.8 format"
|
|
line.long 0x18 "CSC_KUB_0,Window C CSC U coefficient for B"
|
|
hexmask.long.word 0x18 0.--10. 1. " C_CSC_KUB ,U coefficients for B in s.2.8 format"
|
|
line.long 0x1C "CSC_KVB_0,Window C CSC V coefficient for B"
|
|
hexmask.long.word 0x1C 0.--10. 1. " C_CSC_KVB ,V coefficients for B in s.2.8 format"
|
|
textline " "
|
|
group.long 0x1864++0x03
|
|
line.long 0x00 "V_FILTER_P00_0,Window C Vertical Filter phase 00"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P00C0 ,Phase 00 coefficient 0"
|
|
group.long 0x1868++0x03
|
|
line.long 0x00 "V_FILTER_P01_0,Window C Vertical Filter phase 01"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P01C0 ,Phase 01 coefficient 1"
|
|
group.long 0x186C++0x03
|
|
line.long 0x00 "V_FILTER_P02_0,Window C Vertical Filter phase 02"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P02C0 ,Phase 02 coefficient 2"
|
|
group.long 0x1870++0x03
|
|
line.long 0x00 "V_FILTER_P03_0,Window C Vertical Filter phase 03"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P03C0 ,Phase 03 coefficient 3"
|
|
group.long 0x1874++0x03
|
|
line.long 0x00 "V_FILTER_P04_0,Window C Vertical Filter phase 04"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P04C0 ,Phase 04 coefficient 4"
|
|
group.long 0x1878++0x03
|
|
line.long 0x00 "V_FILTER_P05_0,Window C Vertical Filter phase 05"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P05C0 ,Phase 05 coefficient 5"
|
|
group.long 0x187C++0x03
|
|
line.long 0x00 "V_FILTER_P06_0,Window C Vertical Filter phase 06"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P06C0 ,Phase 06 coefficient 6"
|
|
group.long 0x1880++0x03
|
|
line.long 0x00 "V_FILTER_P07_0,Window C Vertical Filter phase 07"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P07C0 ,Phase 07 coefficient 7"
|
|
group.long 0x1884++0x03
|
|
line.long 0x00 "V_FILTER_P08_0,Window C Vertical Filter phase 08"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P08C0 ,Phase 08 coefficient 8"
|
|
group.long 0x1888++0x03
|
|
line.long 0x00 "V_FILTER_P09_0,Window C Vertical Filter phase 09"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P09C0 ,Phase 09 coefficient 9"
|
|
group.long 0x188C++0x03
|
|
line.long 0x00 "V_FILTER_P0A_0,Window C Vertical Filter phase 0A"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P0AC0 ,Phase 0A coefficient A"
|
|
group.long 0x1890++0x03
|
|
line.long 0x00 "V_FILTER_P0B_0,Window C Vertical Filter phase 0B"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P0BC0 ,Phase 0B coefficient B"
|
|
group.long 0x1894++0x03
|
|
line.long 0x00 "V_FILTER_P0C_0,Window C Vertical Filter phase 0C"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P0CC0 ,Phase 0C coefficient C"
|
|
group.long 0x1898++0x03
|
|
line.long 0x00 "V_FILTER_P0D_0,Window C Vertical Filter phase 0D"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P0DC0 ,Phase 0D coefficient D"
|
|
group.long 0x189C++0x03
|
|
line.long 0x00 "V_FILTER_P0E_0,Window C Vertical Filter phase 0E"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P0EC0 ,Phase 0E coefficient E"
|
|
group.long 0x18A0++0x03
|
|
line.long 0x00 "V_FILTER_P0F_0,Window C Vertical Filter phase 0F"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P0FC0 ,Phase 0F coefficient F"
|
|
textline " "
|
|
group.long 0x18A4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P00_0,Window C Horizontal Filter phase 00"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P00C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P00C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P00C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P00C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P00C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P00C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18A8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P01_0,Window C Horizontal Filter phase 01"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P01C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P01C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P01C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P01C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P01C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P01C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18AC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P02_0,Window C Horizontal Filter phase 02"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P02C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P02C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P02C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P02C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P02C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P02C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18B0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P03_0,Window C Horizontal Filter phase 03"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P03C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P03C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P03C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P03C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P03C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P03C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18B4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P04_0,Window C Horizontal Filter phase 04"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P04C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P04C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P04C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P04C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P04C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P04C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18B8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P05_0,Window C Horizontal Filter phase 05"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P05C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P05C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P05C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P05C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P05C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P05C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18BC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P06_0,Window C Horizontal Filter phase 06"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P06C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P06C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P06C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P06C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P06C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P06C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18C0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P07_0,Window C Horizontal Filter phase 07"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P07C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P07C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P07C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P07C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P07C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P07C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18C4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P08_0,Window C Horizontal Filter phase 08"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P08C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P08C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P08C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P08C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P08C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P08C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18C8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P09_0,Window C Horizontal Filter phase 09"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P09C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P09C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P09C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P09C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P09C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P09C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18CC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0A_0,Window C Horizontal Filter phase 0A"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P0AC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P0AC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P0AC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P0AC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P0AC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P0AC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18D0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0B_0,Window C Horizontal Filter phase 0B"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P0BC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P0BC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P0BC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P0BC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P0BC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P0BC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18D4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0C_0,Window C Horizontal Filter phase 0C"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P0CC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P0CC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P0CC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P0CC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P0CC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P0CC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18D8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0D_0,Window C Horizontal Filter phase 0D"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P0DC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P0DC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P0DC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P0DC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P0DC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P0DC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18DC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0E_0,Window C Horizontal Filter phase 0E"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P0EC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P0EC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P0EC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P0EC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P0EC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P0EC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18E0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0F_0,Window C Horizontal Filter phase 0F"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P0FC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P0FC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P0FC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P0FC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P0FC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P0FC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
textline " "
|
|
width 15.
|
|
if (((d.l(ad:0x54200000+0x1C00))&0x400)==0x400)
|
|
group.long 0x1C00++0x03
|
|
line.long 0x00 "WIN_OPTIONS_0,Window C Options"
|
|
bitfld.long 0x00 31. " C_H_FILTER_MODE ,Horizontal filter mode" "Old,New"
|
|
bitfld.long 0x00 30. " C_WIN_ENABLE ,Window C Window enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " C_INTERLACE_ENABLE ,Window C Interlace enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " C_YUV_RANGE_EXPAND ,Window C Enable range expansion" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " C_DV_ENABLE ,Window C Digital Vibrance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " C_CSC_ENABLE ,Window C Color Space Conversion Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " C_CP_ENABLE ,Window C Color Palette Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " C_V_FILTER_UV_ALIGN ,Window C V Filter UV Alignment" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " C_V_FILTER_OPTIMIZE ,Window C V Filter Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " C_V_FILTER_ENABLE ,Window C V Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " C_H_FILTER_ENABLE ,Window C H Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " C_COLOR_EXPAND ,Color expansion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_SCAN_COLUMN ,Window C Scanning direction" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " C_V_DIRECTION ,Window C Vertical (Y) drawing Direction" "Increment,Decrement"
|
|
bitfld.long 0x00 0. " C_H_DIRECTION ,Window C Horizontal (X) drawing Direction" "Increment,Decrement"
|
|
else
|
|
group.long 0x1C00++0x03
|
|
line.long 0x00 "WIN_OPTIONS_0,Window C Options"
|
|
bitfld.long 0x00 31. " C_H_FILTER_MODE ,Horizontal filter mode" "Old,New"
|
|
bitfld.long 0x00 30. " C_WIN_ENABLE ,Window C Window enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " C_INTERLACE_ENABLE ,Window C Interlace enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " C_YUV_RANGE_EXPAND ,Window C Enable range expansion" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " C_DV_ENABLE ,Window C Digital Vibrance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " C_CSC_ENABLE ,Window C Color Space Conversion Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " C_CP_ENABLE ,Window C Color Palette Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " C_V_FILTER_ENABLE ,Window C V Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " C_H_FILTER_ENABLE ,Window C H Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " C_COLOR_EXPAND ,Color expansion" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " C_SCAN_COLUMN ,Window C Scanning direction" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " C_V_DIRECTION ,Window C Vertical (Y) drawing Direction" "Increment,Decrement"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_H_DIRECTION ,Window C Horizontal (X) drawing Direction" "Increment,Decrement"
|
|
endif
|
|
group.long 0x1C04++0x03
|
|
line.long 0x00 "BYTE_SWAP_0,Window C Byte Swap"
|
|
bitfld.long 0x00 0.--2. " C_BYTE_SWAP ,Window C Byte Swap" "NOSWAP,SWAP2,SWAP4,SWAP4HW,SWAP02,SWAPLEFT,,"
|
|
group.long 0x1C0C++0x03
|
|
line.long 0x00 "COLOR_DEPTH_0,Window C Color depth"
|
|
hexmask.long.byte 0x00 0.--6. 1. " C_COLOR_DEPTH ,Window C Color Depth"
|
|
width 18.
|
|
group.long 0x1C10++0x03
|
|
line.long 0x00 "POSITION_0,Window C Position"
|
|
hexmask.long.word 0x00 16.--28. 1. " C_V_POSITION ,Window C V Position"
|
|
hexmask.long.word 0x00 0.--12. 1. " C_H_POSITION ,Window C H Position"
|
|
group.long 0x1C14++0x03
|
|
line.long 0x00 "SIZE_0,Window C Size"
|
|
hexmask.long.word 0x00 16.--28. 1. " C_V_SIZE ,Vertical size after scaling"
|
|
hexmask.long.word 0x00 0.--12. 1. " C_H_SIZE ,Horizontal size after scaling"
|
|
group.long 0x1C18++0x03
|
|
line.long 0x00 "PRESCALED_SIZE_0,Window C Pre-scaled Size"
|
|
hexmask.long.word 0x00 16.--28. 1. " C_V_PRESCALED_SIZE ,Window C V Pre-scaled Size"
|
|
hexmask.long.word 0x00 0.--14. 1. " C_H_PRESCALED_SIZE ,Window C H Pre-scaled Size"
|
|
group.long 0x1C1C++0x03
|
|
line.long 0x00 "H_INITIAL_DDA_0,Window C H Initial DDA"
|
|
hexmask.long.word 0x00 0.--15. 1. " C_H_INITIAL_DDA ,Window C H Initial DDA"
|
|
group.long 0x1C20++0x03
|
|
line.long 0x00 "V_INITIAL_DDA_0,Window C V Initial DDA"
|
|
hexmask.long.word 0x00 0.--15. 1. " C_V_INITIAL_DDA ,Window C V Initial DDA"
|
|
group.long 0x1C24++0x03
|
|
line.long 0x00 "DDA_INCREMENT_0,Window C DDA Increment"
|
|
hexmask.long.word 0x00 16.--31. 1. " C_V_DDA_INCREMENT ,Window C Vertical DDA Increment"
|
|
hexmask.long.word 0x00 0.--15. 1. " C_H_DDA_INCREMENT ,Window C Horizontal DDA Increment"
|
|
group.long 0x1C28++0x03
|
|
line.long 0x00 "LINE_STRIDE_0,Window C Line Stride"
|
|
hexmask.long.word 0x00 16.--31. 1. " C_UV_LINE_STRIDE ,Window C Line Stride for Chroma"
|
|
hexmask.long.word 0x00 0.--15. 1. " C_LINE_STRIDE ,Window C Line Stride"
|
|
group.long 0x1C38++0x03
|
|
line.long 0x00 "DV_CONTROL_0,Window C Digital Vibrance Control"
|
|
bitfld.long 0x00 16.--18. " C_DV_CONTROL_B ,Digital Vibrance control for B" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " C_DV_CONTROL_G ,Digital Vibrance control for G" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " C_DV_CONTROL_R ,Digital Vibrance control for R" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
width 24.
|
|
group.long 0x1C58++0x0F
|
|
line.long 0x00 "BLEND_LAYER_CONTROL_0,Window C"
|
|
bitfld.long 0x00 25.--27. " C_COLOR_KEY_SELECT ,C color key select" "0,1,2,3,4,5,6,7"
|
|
eventfld.long 0x00 24. " C_BLEND_BYPASS ,C blend bypass" "BLEND_ENABLE,BLEND_BYPASS"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_K2 ,C K2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_K1 ,C K1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_WINDOW_LAYER_DEPTH ,Window C layer depth"
|
|
line.long 0x04 "BLEND_MATCH_SELECT_0,DC WIN C BLEND MATCH SELECT 0"
|
|
bitfld.long 0x04 12.--13. " C_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT ,C blend factor dst alpha match select" "0,1,EG_K1_TIMES_SRC,K2"
|
|
bitfld.long 0x04 8.--9. " C_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT ,C blend factor src alpha match select" "0,K1,K2,"
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " C_BLEND_FACTOR_DST_COLOR_MATCH_SELECT ,C blend factor dst color match select" "0,1,K1,K2,K1_TIMES_DST,NEG_K1_TIMES_DST,NEG_K1_TIMES_SRC,NEG_K1"
|
|
bitfld.long 0x04 0.--2. " C_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT ,C blend factor src color match select" "0,1,K1,K1_TIMES_DST,NEG_K1_TIMES_DST,K1_TIMES_SRC,,"
|
|
line.long 0x08 "BLEND_NOMATCH_SELECT_0,WIN C blend nomatch select 0"
|
|
bitfld.long 0x08 12.--13. " C_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT ,C blend factor dst alpha nomatch select" "0,1,EG_K1_TIMES_SRC,K2"
|
|
bitfld.long 0x08 8.--9. " C_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT ,C blend factor src alpha nomatch select" "0,K1,K2,"
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " C_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT ,C blend factor dst color nomatch select" "0,1,K1,K2,K1_TIMES_DST,NEG_K1_TIMES_DST,NEG_K1_TIMES_SRC,NEG_K1"
|
|
bitfld.long 0x08 0.--2. " C_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT ,C blend factor src color nomatch select" "0,1,K1,K1_TIMES_DST,NEG_K1_TIMES_DST,K1_TIMES_SRC,,"
|
|
line.long 0x0C "BLEND_ALPHA_1BIT_0,DC WIN C BLEND ALPHA 1BIT 0"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " C_BLEND_WEIGHT1 ,Alpha value of 1"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " C_BLEND_WEIGHT0 ,Alpha value of 0"
|
|
tree.end
|
|
width 19.
|
|
tree "WINBUF_C Registers"
|
|
group.long 0x2000++0x27
|
|
line.long 0x00 "START_ADDR_0,Window C Start Address"
|
|
line.long 0x04 "START_ADDR_NS_0,Window C Shadowed Start Address"
|
|
line.long 0x08 "START_ADDR_U_0,Window C Start Address for U plane"
|
|
line.long 0x0C "START_ADDR_U_NS_0,Window C Shadowed Start Address for U plane"
|
|
line.long 0x10 "START_ADDR_V_0,Window C Start Address for V plane"
|
|
line.long 0x14 "START_ADDR_V_NS_0,WWindow C Shadowed Start Address for V plane"
|
|
line.long 0x18 "ADDR_H_OFFSET_0,Window C Horizontal Address Offset"
|
|
line.long 0x1C "ADDR_H_OFFSET_NS_0,Window C Shadowed Horizontal Address Offset"
|
|
line.long 0x20 "ADDR_V_OFFSET_0,Window C Vertical Address Offset"
|
|
line.long 0x24 "ADDR_V_OFFSET_NS_0,Window C Shadowed Vertical Address Offset"
|
|
group.long 0x2028++0x0B
|
|
line.long 0x00 "UFLOW_STATUS,Window C FIFO Underflow Status Register"
|
|
bitfld.long 0x00 30. " COUNT_OFLOW ,Counter has overflowed" "Not occurred,Occurred"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " UFLOW_COUNT ,Underflow count"
|
|
line.long 0x04 "SURFACE_KIND_0,Window C Surface Kind"
|
|
bitfld.long 0x04 4.--6. " C_BLOCK_HEIGHT ,Block Height" "HEIGHT_1,HEIGHT_2,HEIGHT_4,HEIGHT_8,HEIGHT_16,HEIGHT_32,,"
|
|
bitfld.long 0x04 0.--1. " C_SURFACE_KIND ,Surface kind" "PITCH,TILED,BL_16B2,"
|
|
line.long 0x08 "SURFACE_WEIGHT_0,Window C Surface Weights"
|
|
bitfld.long 0x08 5.--6. " C_SURFACE_WEIGHT_V ,Window C V Surface Weights" "2,4,8,16"
|
|
bitfld.long 0x08 3.--4. " C_SURFACE_WEIGHT_U ,Window C U or UV Surface Weights" "2,4,8,16"
|
|
bitfld.long 0x08 1.--2. " C_SURFACE_WEIGHT_Y ,Window C Y or packed Surface Weights" "2,4,8,16"
|
|
textline " "
|
|
bitfld.long 0x08 0. " C_SURFACE_WEIGHT_OVERRIDE ,Weight Override" "Disabled,Enabled"
|
|
textline " "
|
|
width 22.
|
|
group.long 0x2034++0x17
|
|
line.long 0x00 "START_ADDR_HI_0,Window C Higher 2 bits of Start Address"
|
|
bitfld.long 0x00 0.--1. " C_START_ADDR_HI ,Window C Start Address" "0,1,2,3"
|
|
line.long 0x04 "START_ADDR_HI_NS_0,Window C Higher 2 bits of Start Address"
|
|
bitfld.long 0x04 0.--1. " C_START_ADDR_HI_NS ,Window C Shadowed Start Address" "0,1,2,3"
|
|
line.long 0x08 "START_ADDR_HI_U_0,Window C Higher 2 bits of Start Address"
|
|
bitfld.long 0x08 0.--1. " C_START_ADDR_HI ,Window C Start Address" "0,1,2,3"
|
|
line.long 0x0C "START_ADDR_HI_U_NS_0,Window C Shadowed Higher 2 bits of Start Address for U Plane"
|
|
bitfld.long 0x0C 0.--1. " C_START_ADDR_HI_U_NS ,Window C Shadowed Higher 2 bits of Start Address for U plane" "0,1,2,3"
|
|
line.long 0x10 "START_ADDR_HI_V_0,Window C Higher 2 bits of Start Address for V Plane"
|
|
bitfld.long 0x10 0.--1. " C_START_ADDR_HI_V ,Window C Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
line.long 0x14 "START_ADDR_HI_V_NS_0,Window C Shadowed Higher 2 bits of Start Address for V Plane"
|
|
bitfld.long 0x14 0.--1. " C_START_ADDR_HI_V_NS ,Window C Shadowed Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
textline " "
|
|
width 29.
|
|
group.long 0x204C++0x17
|
|
line.long 0x00 "START_ADDR_FIELD2_0,Window C Start Address"
|
|
line.long 0x04 "START_ADDR_FIELD2_NS_0,Window C Shadowed Start Address"
|
|
line.long 0x08 "START_ADDR_FIELD2_U_0,Window C Start Address for U plane"
|
|
line.long 0x0C "START_ADDR_FIELD2_U_NS_0,Window C Shadowed Start Address for U plane"
|
|
line.long 0x10 "START_ADDR_FIELD2_V_0,Window C Start Address for V plane"
|
|
line.long 0x14 "START_ADDR_FIELD2_V_NS_0,Window C Shadowed Start Address for V plane"
|
|
group.long 0x2064++0x17
|
|
line.long 0x00 "START_ADDR_FIELD2_HI_0,Window C Higher 2 bits of Start Address"
|
|
bitfld.long 0x00 0.--1. " C_START_ADDR_FIELD2_HI ,Window C Start Address" "0,1,2,3"
|
|
line.long 0x04 "START_ADDR_FIELD2_HI_NS_0,Window C Shadowed Higher 2 bits of Start Address"
|
|
bitfld.long 0x04 0.--1. " C_START_ADDR_FIELD2_HI_NS ,Window C Shadowed Start Address" "0,1,2,3"
|
|
line.long 0x08 "START_ADDR_FIELD2_HI_U_0,Window C Higher 2 bits of Start Address for U plane"
|
|
bitfld.long 0x08 0.--1. " C_START_ADDR_FIELD2_HI_U ,Window C Start Address for U plane" "0,1,2,3"
|
|
line.long 0x0C "START_ADDR_FIELD2_HI_U_NS_0,Window C Shadowed Higher 32 bits of Start Address for U plane"
|
|
bitfld.long 0x0C 0.--1. " C_START_ADDR_FIELD2_HI_U_NS ,Window C Shadowed Higher 2 bits of Start Address for U plane" "0,1,2,3"
|
|
line.long 0x10 "START_ADDR_FIELD2_HI_V_0,Window C Higher 2 bits of Start Address for V plane"
|
|
bitfld.long 0x10 0.--1. " C_START_ADDR_FIELD2_HI_V ,Window C Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
line.long 0x14 "START_ADDR_FIELD2_HI_V_NS_0,Window C Shadowed Higher 2 bits of Start Address for V plane"
|
|
bitfld.long 0x14 0.--1. " C_START_ADDR_FIELD2_HI_V_NS ,Window C Shadowed Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
group.long 0x207C++0x0F
|
|
line.long 0x00 "ADDR_H_OFFSET_FIELD2_0,Window C Horizontal address offset"
|
|
line.long 0x04 "ADDR_H_OFFSET_FIELD2_NS_0,Window C Shadowed Horizontal address offset"
|
|
line.long 0x08 "ADDR_V_OFFSET_FIELD2_0,Window C Vertical address offset"
|
|
line.long 0x0C "ADDR_V_OFFSET_FIELD2_NS_0,Window C Shadowed Vertical address offset"
|
|
group.long 0x2090++0x03
|
|
line.long 0x00 "UFLOW_CTRL_0,DC WINBUF C uflow ctrl 0"
|
|
bitfld.long 0x00 0. " C_UFLOW_CTRL_DBG_MODE ,C uflow ctrl dbg mode" "Disabled,Enabled"
|
|
textline " "
|
|
width 25.
|
|
group.long 0x2094++0x27
|
|
line.long 0x00 "UFLOW_DBG_PIXEL_0,DC WINBUF C uflow dbg pixel 0"
|
|
line.long 0x04 "UFLOW_THRESHOLD_0,DC WINBUF C uflow threshold 0"
|
|
hexmask.long.word 0x04 0.--12. 1. " C_UFLOW_THRESHOLD ,C uflow threshold"
|
|
line.long 0x08 "SPOOL_UP_0,Spool up time configuration for different windows related logic"
|
|
hexmask.long.word 0x08 16.--28. 1. " C_SPOOL_UP_DURATION ,C spool up duration"
|
|
bitfld.long 0x08 1. " C_SPOOL_UP_EDGE ,C spool up edge" "Negedge,Posedge"
|
|
bitfld.long 0x08 0. " C_SPOOL_UP_CTRL ,C spool up ctrl" "Max,Programmable"
|
|
line.long 0x0C "SCALEFACTOR_THRESHOLD_0,DC WINBUF C SCALEFACTOR THRESHOLD 0"
|
|
hexmask.long.word 0x0C 16.--31. 1. " C_SF_LWM_THRESHOLD ,C sf lwm threshold"
|
|
hexmask.long.word 0x0C 0.--15. 1. " C_SF_HWM_THRESHOLD ,C sf hwm threshold"
|
|
line.long 0x10 "LATENCY_THRESHOLD_0,Register controls the behavior of the rdy4_latency_event from the display to the MC"
|
|
bitfld.long 0x10 31. " C_RDY4LATENCY_THRESHOLD_ENABLE ,C RDY4LATENCY THRESHOLD ENABLE" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " C_RDY4LATENCY_SPOOLUP_CTRL ,C RDY4LATENCY spoolup ctrl" "Disallow,Allow"
|
|
textline " "
|
|
hexmask.long.word 0x10 16.--28. 1. " C_RDY4LATENCY_SPOOLUP_DURATION ,C RDY4LATENCY threshold"
|
|
hexmask.long.word 0x10 0.--15. 1. " C_RDY4LATENCY_THRESHOLD ,C RDY4LATENCY threshold"
|
|
line.long 0x14 "MEMFETCH_DEBUG_STATUS_0,Memfetch Debug Status"
|
|
bitfld.long 0x14 16. " C_DEBUG_ENABLE ,Reg to enable FGCG for flops added to debug signals in memfetch" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " C_ALIGN_FIFO_NON_IDLE ,Align FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 13. " C_PIPE0_FIFO_NON_IDLE ,Pipe0 FIFO idle at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 12. " C_FRAME_FIFO_NON_IDLE ,Frame FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 11. " C_SURFACE_FIFO_NON_IDLE ,Surface FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 10. " C_TAG_FIFO_NON_IDLE ,Tag FIFO idle at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 9. " C_RSP_FIFO_NON_IDLE ,Response FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 8. " C_REQ_FIFO_NON_IDLE ,Request FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 7. " C_DP_VALID_NON_IDLE ,DP lines valid at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 6. " C_V_SSM_NON_IDLE ,V SSM is non-idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 5. " C_U_SSM_NON_IDLE ,U SSM is non-idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 4. " C_Y_SSM_NON_IDLE ,Y SSM is non-idle at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 3. " C_DP_POOL_AVAIL ,DP thinks there is data in the pool at end of frame" "No data,Data"
|
|
bitfld.long 0x14 2. " C_POOL_NOT_EMPTY ,Status of pool at end of frame" "Empty,Not empty"
|
|
bitfld.long 0x14 1. " C_UNDERFLOW_LINE1 ,Underflow of line0" "No underflow,Line0 underflowed"
|
|
textline " "
|
|
bitfld.long 0x14 0. " C_UNDERFLOW_LINE0 ,Underflow of line0" "No underflow,Line0 underflowed"
|
|
line.long 0x18 "MEMFETCH_CONTROL_0,Memfetch Control Register"
|
|
bitfld.long 0x18 1. " C_MEMFETCH_CLK_GATE_OVERRIDE ,Disable clock-gating of memfetch for a controller" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " C_MEMFETCH_RESET ,Reset memfetch for a controller" "Disabled,Enabled"
|
|
line.long 0x1C "OCCUPANCY_THROTTLE_0,DC WINBUF C OCCUPANCY THROTTLE 0"
|
|
hexmask.long.word 0x1C 16.--31. 1. " C_OCCUPANCY_MAX_THRESHOLD ,C occupancy max threshold"
|
|
bitfld.long 0x1C 0. " C_OCCUPANCY_THROTTLE_MODE ,C occupancy throttle mode" "Disabled,Enabled"
|
|
line.long 0x20 "SCRATCH_REGISTER_0_0,DC WINBUF C scratch register 0 0"
|
|
line.long 0x24 "SCRATCH_REGISTER_1_0,DC WINBUF C scratch register 1 0"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "Display B"
|
|
base ad:0x542400000
|
|
width 29.
|
|
tree "Display CMD Registers"
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "GENERAL_INCR_SYNCPT_0,GENERAL_INCR_SYNCPT_0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERAL_COND ,Condition mapped from raise/wait"
|
|
hexmask.long.byte 0x00 0.--7. 1. " GENERAL_INDX ,Syncpt index value"
|
|
line.long 0x04 "GENERAL_INCR_SYNCPT_CNTRL_0,GENERAL_INCR_SYNCPT_CNTRL_0"
|
|
bitfld.long 0x04 8. " GENERAL_INCR_SYNCPT_NO_STALL ,GENERAL_INCR_SYNCPT_NO_STALL" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " GENERAL_INCR_SYNCPT_SOFT_RESET ,GENERAL_INCR_SYNCPT_SOFT_RESET" "No reset,Reset"
|
|
line.long 0x08 "GENERAL_INCR_SYNCPT_ERROR_0,GENERAL_INCR_SYNCPT_ERROR_0"
|
|
eventfld.long 0x08 31. " COND_STATUS[31] ,FIFO overflow for COND[31]" "No overflow,Overflow"
|
|
eventfld.long 0x08 30. " [30] ,FIFO overflow for COND[30]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 29. " [29] ,FIFO overflow for COND[29]" "No overflow,Overflow"
|
|
eventfld.long 0x08 28. " [28] ,FIFO overflow for COND[28]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 27. " [27] ,FIFO overflow for COND[27]" "No overflow,Overflow"
|
|
eventfld.long 0x08 26. " [26] ,FIFO overflow for COND[26]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 25. " [25] ,FIFO overflow for COND[25]" "No overflow,Overflow"
|
|
eventfld.long 0x08 24. " [24] ,FIFO overflow for COND[24]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 23. " [23] ,FIFO overflow for COND[23]" "No overflow,Overflow"
|
|
eventfld.long 0x08 22. " [22] ,FIFO overflow for COND[22]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 21. " [21] ,FIFO overflow for COND[21]" "No overflow,Overflow"
|
|
eventfld.long 0x08 20. " [20] ,FIFO overflow for COND[20]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 19. " [19] ,FIFO overflow for COND[19]" "No overflow,Overflow"
|
|
eventfld.long 0x08 18. " [18] ,FIFO overflow for COND[18]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 17. " [17] ,FIFO overflow for COND[17]" "No overflow,Overflow"
|
|
eventfld.long 0x08 16. " [16] ,FIFO overflow for COND[16]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 15. " [15] ,FIFO overflow for COND[15]" "No overflow,Overflow"
|
|
eventfld.long 0x08 14. " [14] ,FIFO overflow for COND[14]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 13. " [13] ,FIFO overflow for COND[13]" "No overflow,Overflow"
|
|
eventfld.long 0x08 12. " [12] ,FIFO overflow for COND[12]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 11. " [11] ,FIFO overflow for COND[11]" "No overflow,Overflow"
|
|
eventfld.long 0x08 10. " [10] ,FIFO overflow for COND[10]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 9. " [9] ,FIFO overflow for COND[9]" "No overflow,Overflow"
|
|
eventfld.long 0x08 8. " [8] ,FIFO overflow for COND[8]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 7. " [7] ,FIFO overflow for COND[7]" "No overflow,Overflow"
|
|
eventfld.long 0x08 6. " [6] ,FIFO overflow for COND[6]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 5. " [5] ,FIFO overflow for COND[5]" "No overflow,Overflow"
|
|
eventfld.long 0x08 4. " [4] ,FIFO overflow for COND[4]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 3. " [3] ,FIFO overflow for COND[3]" "No overflow,Overflow"
|
|
eventfld.long 0x08 2. " [2] ,FIFO overflow for COND[2]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 1. " [1] ,FIFO overflow for COND[1]" "No overflow,Overflow"
|
|
eventfld.long 0x08 0. " [0] ,FIFO overflow for COND[0]" "No overflow,Overflow"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "WIN_A_INCR_SYNCPT_0,WIN_A_INCR_SYNCPT_0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WIN_A_COND ,Condition mapped from raise/wait"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WIN_A_INDX ,Syncpt index value"
|
|
line.long 0x04 "WIN_A_INCR_SYNCPT_CNTRL_0,WIN_A_INCR_SYNCPT_CNTRL_0"
|
|
bitfld.long 0x04 8. " WIN_A_INCR_SYNCPT_NO_STALL ,WIN_A_INCR_SYNCPT_NO_STALL" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " WIN_A_INCR_SYNCPT_SOFT_RESET ,WIN_A_INCR_SYNCPT_SOFT_RESET" "No reset,Reset"
|
|
line.long 0x08 "WIN_A_INCR_SYNCPT_ERROR_0,WIN_A_INCR_SYNCPT_ERROR_0"
|
|
eventfld.long 0x08 31. " COND_STATUS[31] ,FIFO overflow for COND[31]" "No overflow,Overflow"
|
|
eventfld.long 0x08 30. " [30] ,FIFO overflow for COND[30]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 29. " [29] ,FIFO overflow for COND[29]" "No overflow,Overflow"
|
|
eventfld.long 0x08 28. " [28] ,FIFO overflow for COND[28]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 27. " [27] ,FIFO overflow for COND[27]" "No overflow,Overflow"
|
|
eventfld.long 0x08 26. " [26] ,FIFO overflow for COND[26]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 25. " [25] ,FIFO overflow for COND[25]" "No overflow,Overflow"
|
|
eventfld.long 0x08 24. " [24] ,FIFO overflow for COND[24]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 23. " [23] ,FIFO overflow for COND[23]" "No overflow,Overflow"
|
|
eventfld.long 0x08 22. " [22] ,FIFO overflow for COND[22]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 21. " [21] ,FIFO overflow for COND[21]" "No overflow,Overflow"
|
|
eventfld.long 0x08 20. " [20] ,FIFO overflow for COND[20]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 19. " [19] ,FIFO overflow for COND[19]" "No overflow,Overflow"
|
|
eventfld.long 0x08 18. " [18] ,FIFO overflow for COND[18]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 17. " [17] ,FIFO overflow for COND[17]" "No overflow,Overflow"
|
|
eventfld.long 0x08 16. " [16] ,FIFO overflow for COND[16]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 15. " [15] ,FIFO overflow for COND[15]" "No overflow,Overflow"
|
|
eventfld.long 0x08 14. " [14] ,FIFO overflow for COND[14]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 13. " [13] ,FIFO overflow for COND[13]" "No overflow,Overflow"
|
|
eventfld.long 0x08 12. " [12] ,FIFO overflow for COND[12]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 11. " [11] ,FIFO overflow for COND[11]" "No overflow,Overflow"
|
|
eventfld.long 0x08 10. " [10] ,FIFO overflow for COND[10]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 9. " [9] ,FIFO overflow for COND[9]" "No overflow,Overflow"
|
|
eventfld.long 0x08 8. " [8] ,FIFO overflow for COND[8]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 7. " [7] ,FIFO overflow for COND[7]" "No overflow,Overflow"
|
|
eventfld.long 0x08 6. " [6] ,FIFO overflow for COND[6]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 5. " [5] ,FIFO overflow for COND[5]" "No overflow,Overflow"
|
|
eventfld.long 0x08 4. " [4] ,FIFO overflow for COND[4]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 3. " [3] ,FIFO overflow for COND[3]" "No overflow,Overflow"
|
|
eventfld.long 0x08 2. " [2] ,FIFO overflow for COND[2]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 1. " [1] ,FIFO overflow for COND[1]" "No overflow,Overflow"
|
|
eventfld.long 0x08 0. " [0] ,FIFO overflow for COND[0]" "No overflow,Overflow"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "WIN_B_INCR_SYNCPT_0,WIN_B_INCR_SYNCPT_0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WIN_B_COND ,Condition mapped from raise/wait"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WIN_B_INDX ,Syncpt index value"
|
|
line.long 0x04 "WIN_B_INCR_SYNCPT_CNTRL_0,WIN_B_INCR_SYNCPT_CNTRL_0"
|
|
bitfld.long 0x04 8. " WIN_B_INCR_SYNCPT_NO_STALL ,WIN_B_INCR_SYNCPT_NO_STALL" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " WIN_B_INCR_SYNCPT_SOFT_RESET ,WIN_B_INCR_SYNCPT_SOFT_RESET" "No reset,Reset"
|
|
line.long 0x08 "WIN_B_INCR_SYNCPT_ERROR_0,WIN_B_INCR_SYNCPT_ERROR_0"
|
|
eventfld.long 0x08 31. " COND_STATUS[31] ,FIFO overflow for COND[31]" "No overflow,Overflow"
|
|
eventfld.long 0x08 30. " [30] ,FIFO overflow for COND[30]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 29. " [29] ,FIFO overflow for COND[29]" "No overflow,Overflow"
|
|
eventfld.long 0x08 28. " [28] ,FIFO overflow for COND[28]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 27. " [27] ,FIFO overflow for COND[27]" "No overflow,Overflow"
|
|
eventfld.long 0x08 26. " [26] ,FIFO overflow for COND[26]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 25. " [25] ,FIFO overflow for COND[25]" "No overflow,Overflow"
|
|
eventfld.long 0x08 24. " [24] ,FIFO overflow for COND[24]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 23. " [23] ,FIFO overflow for COND[23]" "No overflow,Overflow"
|
|
eventfld.long 0x08 22. " [22] ,FIFO overflow for COND[22]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 21. " [21] ,FIFO overflow for COND[21]" "No overflow,Overflow"
|
|
eventfld.long 0x08 20. " [20] ,FIFO overflow for COND[20]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 19. " [19] ,FIFO overflow for COND[19]" "No overflow,Overflow"
|
|
eventfld.long 0x08 18. " [18] ,FIFO overflow for COND[18]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 17. " [17] ,FIFO overflow for COND[17]" "No overflow,Overflow"
|
|
eventfld.long 0x08 16. " [16] ,FIFO overflow for COND[16]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 15. " [15] ,FIFO overflow for COND[15]" "No overflow,Overflow"
|
|
eventfld.long 0x08 14. " [14] ,FIFO overflow for COND[14]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 13. " [13] ,FIFO overflow for COND[13]" "No overflow,Overflow"
|
|
eventfld.long 0x08 12. " [12] ,FIFO overflow for COND[12]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 11. " [11] ,FIFO overflow for COND[11]" "No overflow,Overflow"
|
|
eventfld.long 0x08 10. " [10] ,FIFO overflow for COND[10]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 9. " [9] ,FIFO overflow for COND[9]" "No overflow,Overflow"
|
|
eventfld.long 0x08 8. " [8] ,FIFO overflow for COND[8]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 7. " [7] ,FIFO overflow for COND[7]" "No overflow,Overflow"
|
|
eventfld.long 0x08 6. " [6] ,FIFO overflow for COND[6]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 5. " [5] ,FIFO overflow for COND[5]" "No overflow,Overflow"
|
|
eventfld.long 0x08 4. " [4] ,FIFO overflow for COND[4]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 3. " [3] ,FIFO overflow for COND[3]" "No overflow,Overflow"
|
|
eventfld.long 0x08 2. " [2] ,FIFO overflow for COND[2]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 1. " [1] ,FIFO overflow for COND[1]" "No overflow,Overflow"
|
|
eventfld.long 0x08 0. " [0] ,FIFO overflow for COND[0]" "No overflow,Overflow"
|
|
group.long 0x60++0x0B
|
|
line.long 0x00 "WIN_C_INCR_SYNCPT_0,WIN_C_INCR_SYNCPT_0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WIN_C_COND ,Condition mapped from raise/wait"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WIN_C_INDX ,Syncpt index value"
|
|
line.long 0x04 "WIN_C_INCR_SYNCPT_CNTRL_0,WIN_C_INCR_SYNCPT_CNTRL_0"
|
|
bitfld.long 0x04 8. " WIN_C_INCR_SYNCPT_NO_STALL ,WIN_C_INCR_SYNCPT_NO_STALL" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " WIN_C_INCR_SYNCPT_SOFT_RESET ,WIN_C_INCR_SYNCPT_SOFT_RESET" "No reset,Reset"
|
|
line.long 0x08 "WIN_C_INCR_SYNCPT_ERROR_0,WIN_C_INCR_SYNCPT_ERROR_0"
|
|
eventfld.long 0x08 31. " COND_STATUS[31] ,FIFO overflow for COND[31]" "No overflow,Overflow"
|
|
eventfld.long 0x08 30. " [30] ,FIFO overflow for COND[30]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 29. " [29] ,FIFO overflow for COND[29]" "No overflow,Overflow"
|
|
eventfld.long 0x08 28. " [28] ,FIFO overflow for COND[28]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 27. " [27] ,FIFO overflow for COND[27]" "No overflow,Overflow"
|
|
eventfld.long 0x08 26. " [26] ,FIFO overflow for COND[26]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 25. " [25] ,FIFO overflow for COND[25]" "No overflow,Overflow"
|
|
eventfld.long 0x08 24. " [24] ,FIFO overflow for COND[24]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 23. " [23] ,FIFO overflow for COND[23]" "No overflow,Overflow"
|
|
eventfld.long 0x08 22. " [22] ,FIFO overflow for COND[22]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 21. " [21] ,FIFO overflow for COND[21]" "No overflow,Overflow"
|
|
eventfld.long 0x08 20. " [20] ,FIFO overflow for COND[20]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 19. " [19] ,FIFO overflow for COND[19]" "No overflow,Overflow"
|
|
eventfld.long 0x08 18. " [18] ,FIFO overflow for COND[18]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 17. " [17] ,FIFO overflow for COND[17]" "No overflow,Overflow"
|
|
eventfld.long 0x08 16. " [16] ,FIFO overflow for COND[16]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 15. " [15] ,FIFO overflow for COND[15]" "No overflow,Overflow"
|
|
eventfld.long 0x08 14. " [14] ,FIFO overflow for COND[14]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 13. " [13] ,FIFO overflow for COND[13]" "No overflow,Overflow"
|
|
eventfld.long 0x08 12. " [12] ,FIFO overflow for COND[12]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 11. " [11] ,FIFO overflow for COND[11]" "No overflow,Overflow"
|
|
eventfld.long 0x08 10. " [10] ,FIFO overflow for COND[10]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 9. " [9] ,FIFO overflow for COND[9]" "No overflow,Overflow"
|
|
eventfld.long 0x08 8. " [8] ,FIFO overflow for COND[8]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 7. " [7] ,FIFO overflow for COND[7]" "No overflow,Overflow"
|
|
eventfld.long 0x08 6. " [6] ,FIFO overflow for COND[6]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 5. " [5] ,FIFO overflow for COND[5]" "No overflow,Overflow"
|
|
eventfld.long 0x08 4. " [4] ,FIFO overflow for COND[4]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 3. " [3] ,FIFO overflow for COND[3]" "No overflow,Overflow"
|
|
eventfld.long 0x08 2. " [2] ,FIFO overflow for COND[2]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 1. " [1] ,FIFO overflow for COND[1]" "No overflow,Overflow"
|
|
eventfld.long 0x08 0. " [0] ,FIFO overflow for COND[0]" "No overflow,Overflow"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CONT_SYNCPT_VSYNC_0,CONT_SYNCPT_VSYNC_0"
|
|
bitfld.long 0x00 8. " VSYNC_EN ,Vsync enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VSYNC_INDX ,Return INDX"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CTXSW_0,Context Switch Register"
|
|
rbitfld.long 0x00 28.--31. " NEXT_CHANNEL ,Next requested channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 16.--25. 1. " NEXT_CLASS ,Next requested class"
|
|
bitfld.long 0x00 12.--15. " CURR_CHANNEL ,Current working channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AUTO_ACK ,Automatically acknowledge any incoming context switch requests" "Manual,AutoACK"
|
|
hexmask.long.word 0x00 0.--9. 1. " CURR_CLASS ,Current working class"
|
|
if (((per.l(ad:0x542400000+0xC8))&0x60)==0x40)
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DISPLAY_COMMAND_OPTION0_0,Display Controller Option 0"
|
|
bitfld.long 0x00 18. " WINDOW_C_NC_DISPLAY ,Window C Non-Continuous display" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " WINDOW_B_NC_DISPLAY ,Window B Non-Continuous display" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " WINDOW_A_NC_DISPLAY ,Window A Non-Continuous display" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SSF_SOURCE ,Source pin for the SSF input" "SSF_LDC,SSF_LSPI,SSF_LSDI,?..."
|
|
bitfld.long 0x00 5. " SSF_ENABLE ,Sub-Display Stop Frame (SSF) input" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SSF_POLARITY ,Sub-Display Stop Frame (SSF) Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MSF_SOURCE ,Source pin for the MSF input" "MSF_LSPI,MSF_LDC,MSF_LSDI,?..."
|
|
bitfld.long 0x00 1. " MSF_ENABLE ,Main-Display Stop Frame (MSF) input" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MSF_POLARITY ,Main-Display Stop Frame (MSF) Polarity" "Active high,Active low"
|
|
else
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DISPLAY_COMMAND_OPTION0_0,Display Controller Option 0"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SSF_SOURCE ,Source pin for the SSF input" "SSF_LDC,SSF_LSPI,SSF_LSDI,?..."
|
|
bitfld.long 0x00 4. " SSF_POLARITY ,Sub-Display Stop Frame (SSF) Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MSF_SOURCE ,Source pin for the MSF input" "MSF_LSPI,MSF_LDC,MSF_LSDI,?..."
|
|
bitfld.long 0x00 0. " MSF_POLARITY ,Main-Display Stop Frame (MSF) Polarity" "Active high,Active low"
|
|
endif
|
|
group.long 0xC8++0x07
|
|
line.long 0x00 "DISPLAY_COMMAND_0,Display Command"
|
|
bitfld.long 0x00 27.--30. " DISP_COMMAND_RAISE_CHANNEL_ID ,Display Command Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--26. " DISP_COMMAND_RAISE_VECTOR ,Display Command Raise Vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--6. " DISPLAY_CTRL_MODE ,Display Controller Mode" "STOP,Continuous,Non-Continuous,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " DISP_COMMAND_RAISE ,Display Command Raise" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x04 "SIGNAL_RAISE_0,SIGNAL_RAISE_0"
|
|
bitfld.long 0x04 16.--19. " SIGNAL_RAISE_CHANNEL_ID ,Signal Raise Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 12. " SIGNAL_RAISE_TYPE ,Signal raise type" "One-shot,Continuous"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " SIGNAL_RAISE_SELECT ,Signal to raise" "None,Frame End,V Blank,V Pulse 3,Rising edge of V Blank,Falling edge of V Blank,Rising edge of V Pulse 3,Falling edge of V Pulse 3"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " SIGNAL_RAISE_VECTOR ,Bit number to raise" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "DISPLAY_POWER_CONTROL_0,Display Power Control"
|
|
width 17.
|
|
textline " "
|
|
group.long 0xDC++0x1F
|
|
line.long 0x00 "INT_STATUS_0,Display Interrupt and Status"
|
|
sif CPUIS("TEGRAX1")
|
|
eventfld.long 0x00 29. " DSC_TO_UF_INT ,DSC TO Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " DSC_BBUF_UF_INT ,DSC BBUF Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 27. " DSC_RBUF_UF_INT ,DSC RBUF Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 26. " DSC_OBUF_UF_INT ,DSC OBUF Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 25. " WIN_T_UF_INT ,Window T Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " WIN_D_UF_INT ,Window D Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " HC_UF_INT ,Cursor Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CMU_LUT_CONFLICT_INT ,CMU LUT read/write conflict" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " WIN_C_OF_INT ,Window C Overflow Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " WIN_B_OF_INT ,Window B Overflow Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " WIN_A_OF_INT ,Window A Overflow Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " SSF_INT ,Sub-Display Stop Frame Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " MSF_INT ,Main-Display Stop Frame Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 10. " WIN_C_UF_INT ,Window C Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " WIN_B_UF_INT ,Window B Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " WIN_A_UF_INT ,Window A Underflow Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " SPI_BUSY_INT ,SPI Busy Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " V_PULSE2_INT ,Vertical Pulse 2 Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " V_PULSE3_INT ,Vertical Pulse 3 Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " H_BLANK_INT ,Horizontal Blank Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " V_BLANK_INT ,Vertical Blank Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " FRAME_END_INT ,Frame End Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " CTXSW_INT ,Context Switch Interrupt Status" "No interrupt,Interrupt"
|
|
line.long 0x04 "INT_MASK_0,Interrupt Mask"
|
|
sif CPUIS("TEGRAX1")
|
|
bitfld.long 0x04 29. " DSC_TO_UF_INT ,DSC TO Underflow Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 28. " DSC_BBUF_UF_INT ,DSC BBUF Underflow Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 27. " DSC_RBUF_UF_INT ,DSC RBUF Underflow Interrupt Mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 26. " DSC_OBUF_UF_INT ,DSC OBUF Underflow Interrupt Mask" "Masked,Unmasked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 25. " WIN_T_UF_INT_MASK ,Window T Underflow Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 24. " WIN_D_UF_INT_MASK ,Window D Underflow Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 23. " HC_UF_INT_MASK ,Cursor Underflow Interrupt Mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 22. " CMU_LUT_CONFLICT_INT_MASK ,CMU LUT read/write conflict Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 16. " WIN_C_OF_INT_MASK ,Window C Overflow Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 15. " WIN_B_OF_INT_MASK ,Window B Overflow Interrupt Mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " WIN_A_OF_INT_MASK ,Window A Overflow Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 13. " SSF_INT_MASK ,Sub-Display Stop Frame Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 12. " MSF_INT_MASK ,Main-Display Stop Frame Interrupt Mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " WIN_C_UF_INT_MASK ,Window C Underflow Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 9. " WIN_B_UF_INT_MASK ,Window B Underflow Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 8. " WIN_A_UF_INT_MASK ,Window A Underflow Interrupt Mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SPI_BUSY_INT_MASK ,SPI Busy Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 5. " V_PULSE2_INT_MASK ,Vertical Pulse 2 Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 4. " V_PULSE3_INT_MASK ,Vertical Pulse 3 Interrupt Mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " H_BLANK_INT_MASK ,Horizontal Blank Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 2. " V_BLANK_INT_MASK ,Vertical Blank Interrupt Mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " FRAME_END_INT_MASK ,Frame End Interrupt Mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CTXSW_INT_MASK ,Context Switch Interrupt Mask" "Masked,Unmasked"
|
|
line.long 0x08 "INT_ENABLE_0,Interrupt Enable"
|
|
sif CPUIS("TEGRAX1")
|
|
bitfld.long 0x08 29. " DSC_TO_UF_INT_ENABLE ,DSC TO Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " DSC_BBUF_UF_INT_ENABLE ,DSC BBUF Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " DSC_RBUF_UF_INT_ENABLE ,DSC RBUF Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 26. " DSC_OBUF_UF_INT_ENABLE ,DSC OBUF Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 25. " WIN_T_UF_INT_ENABLE ,Window T Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " WIN_D_UF_INT_ENABLE ,Window D Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " HC_UF_INT_ENABLE ,Cursor Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 22. " CMU_LUT_CONFLICT_INT_ENABLE ,CMU LUT read/write conflict" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " WIN_C_OF_INT_ENABLE ,Window C Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " WIN_B_OF_INT_ENABLE ,Window B Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 14. " WIN_A_OF_INT_ENABLE ,Window A Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " SSF_INT_ENABLE ,Sub-Display Stop Frame Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " MSF_INT_ENABLE ,Main-Display Stop Frame Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " WIN_C_UF_INT_ENABLE ,Window C Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " WIN_B_UF_INT_ENABLE ,Window B Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " WIN_A_UF_INT_ENABLE ,Window A Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SPI_BUSY_INT_ENABLE ,SPI Busy Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " V_PULSE2_INT_ENABLE ,Vertical Pulse 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " V_PULSE3_INT_ENABLE ,Vertical Pulse 3 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " H_BLANK_INT_ENABLE ,Horizontal Blank Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " V_BLANK_INT_ENABLE ,Vertical Blank Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " FRAME_END_INT_ENABLE ,Frame End Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CTXSW_INT_ENABLE ,Context Switch Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x0C "INT_TYPE_0,Interrupt Type"
|
|
sif CPUIS("TEGRAX1")
|
|
bitfld.long 0x0C 29. " DSC_TO_UF_INT_TYPE ,DSC TO Underflow Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 28. " DSC_BBUF_UF_INT_TYPE ,DSC BBUF Underflow Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 27. " DSC_RBUF_UF_INT_TYPE ,DSC RBUF Underflow Interrupt Type" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x0C 26. " DSC_OBUF_UF_INT_TYPE ,DSC OBUF Underflow Interrupt Type" "Edge,Level"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 25. " WIN_T_UF_INT_TYPE ,Window T Underflow Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 24. " WIN_D_UF_INT_TYPE ,Window D Underflow Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 23. " HC_UF_INT_TYPE ,Cursor Underflow Interrupt Type" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " CMU_LUT_CONFLICT_INT_TYPE ,CMU LUT read/write conflict" "Edge,Level"
|
|
bitfld.long 0x0C 16. " WIN_C_OF_INT_TYPE ,Window C Overflow Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 15. " WIN_B_OF_INT_TYPE ,Window B Overflow Interrupt Type" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " WIN_A_OF_INT_TYPE ,Window A Overflow Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 13. " SSF_INT_TYPE ,Sub-Display Stop Frame Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 11. " EPP_OF_INT_TYPE ,Display2epp Overflow Interrupt Type" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " WIN_C_UF_INT_TYPE ,Window C Underflow Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 9. " WIN_B_UF_INT_TYPE ,Window B Underflow Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 8. " WIN_A_UF_INT_TYPE ,Window A Underflow Interrupt Type" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " SPI_BUSY_INT_TYPE ,SPI Busy Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 5. " V_PULSE2_INT_TYPE ,Vertical Pulse 2 Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 4. " V_PULSE3_INT_TYPE ,Vertical Pulse 3 Interrupt Type" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " H_BLANK_INT_TYPE ,Horizontal Blank Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 2. " V_BLANK_INT_TYPE ,Vertical Blank Interrupt Type" "Edge,Level"
|
|
bitfld.long 0x0C 1. " FRAME_END_INT_TYPE ,Frame End Interrupt Type" "Edge,Level"
|
|
line.long 0x10 "INT_POLARITY_0,Interrupt Polarity"
|
|
sif CPUIS("TEGRAX1")
|
|
bitfld.long 0x10 29. " DSC_TO_UF_INT_POLARITY ,DSC TO Underflow Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 28. " DSC_BBUF_UF_INT_POLARITY ,DSC BBUF Underflow Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 27. " DSC_RBUF_UF_INT_POLARITY ,DSC RBUF Underflow Interrupt Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 26. " DSC_OBUF_UF_INT_POLARITY ,DSC OBUF Underflow Interrupt Polarity" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 25. " WIN_T_UF_INT_POLARITY ,Window T Underflow Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 24. " WIN_D_UF_INT_POLARITY ,Window D Underflow Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 23. " HC_UF_INT_POLARITY ,Cursor Underflow Interrupt Polarity" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x10 22. " CMU_LUT_CONFLICT_INT_POLARITY ,CMU LUT read/write conflict" "Low,High"
|
|
bitfld.long 0x10 16. " WIN_C_OF_INT_POLARITY ,Window C Overflow Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 15. " WIN_B_OF_INT_POLARITY ,Window B Overflow Interrupt Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 14. " WIN_A_OF_INT_POLARITY ,Window A Overflow Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 13. " SSF_INT_POLARITY ,Sub-Display Stop Frame Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 12. " MSF_INT_POLARITY ,Main-Display Stop Frame Interrupt Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 10. " WIN_C_UF_INT_POLARITY ,Window C Underflow Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 9. " WIN_B_UF_INT_POLARITY ,Window B Underflow Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 8. " WIN_A_UF_INT_POLARITY ,Window A Underflow Interrupt Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 7. " SPI_BUSY_INT_POLARITY ,SPI Busy Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 5. " V_PULSE2_INT_POLARITY ,V Pulse 2 Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 4. " V_PULSE3_INT_POLARITY ,Vertical Pulse 3 Interrupt Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 3. " H_BLANK_INT_POLARITY ,Horizontal Blank Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 2. " V_BLANK_INT_POLARITY ,Vertical Blank Interrupt Polarity" "Low,High"
|
|
bitfld.long 0x10 1. " FRAME_END_INT_POLARITY ,Frame End Interrupt Polarity" "Low,High"
|
|
line.long 0x14 "SIGNAL_RAISE1_0,SIGNAL_RAISE1_0"
|
|
bitfld.long 0x14 16.--19. " SIGNAL_RAISE1_CHANNEL_ID ,Signal Raise Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 12. " SIGNAL_RAISE1_TYPE ,Signal Raise Type" "Oneshot,Continuous"
|
|
bitfld.long 0x14 8.--10. " SIGNAL_RAISE1_SELECT ,Signal Raise Select" "None,Frame End,V Blank,V Pulse 3,Rising edge of V Blank,Falling edge of V Blank,Rising edge of V Pulse 3,Falling edge of V Pulse 3"
|
|
textline " "
|
|
bitfld.long 0x14 0.--4. " SIGNAL_RAISE1_VECTOR ,Bit number to raise" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "SIGNAL_RAISE2_0,SIGNAL_RAISE2_0"
|
|
bitfld.long 0x18 16.--19. " SIGNAL_RAISE2_CHANNEL_ID ,Signal Raise Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 12. " SIGNAL_RAISE2_TYPE ,Signal Raise Type" "Oneshot,Continuous"
|
|
bitfld.long 0x18 8.--10. " SIGNAL_RAISE2_SELECT ,Signal Raise Select" "None,Frame End,V Blank,V Pulse 3,Rising edge of V Blank,Falling edge of V Blank,Rising edge of V Pulse 3,Falling edge of V Pulse 3"
|
|
textline " "
|
|
bitfld.long 0x18 0.--4. " SIGNAL_RAISE2_VECTOR ,Bit number to raise" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1C "SIGNAL_RAISE3_0,SIGNAL_RAISE3_0"
|
|
bitfld.long 0x1C 16.--19. " SIGNAL_RAISE3_CHANNEL_ID ,Signal Raise Channel ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x1C 12. " SIGNAL_RAISE3_TYPE ,Signal Raise Type" "Oneshot,Continuous"
|
|
bitfld.long 0x1C 8.--10. " SIGNAL_RAISE3_SELECT ,Signal Raise Select" "None,Frame End,V Blank,V Pulse 3,Rising edge of V Blank,Falling edge of V Blank,Rising edge of V Pulse 3,Falling edge of V Pulse 3"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--4. " SIGNAL_RAISE3_VECTOR ,Bit number to raise" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "STATE_ACCESS_0,Double/triple buffers read and write access control"
|
|
bitfld.long 0x00 2. " WRITE_MUX ,Write access control" "Assembly,Active"
|
|
bitfld.long 0x00 0. " READ_MUX ,Read access control" "Assembly,Active"
|
|
if (((per.l(ad:0x542400000+0xC8))&0x60)==0x40)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "STATE_CONTROL_0,State Control for Activating/Arming New Register State"
|
|
bitfld.long 0x00 24. " NC_HOST_TRIG_ENABLE ,Host trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CURSOR_UPDATE ,Trigger for the arming state for a subset of the triple buffered registers" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WIN_D_UPDATE ,Trigger for the arming state for the win D subset of the triple buffered registers" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WIN_C_UPDATE ,Trigger for arming state for the win C subset of the triple buffered registers" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WIN_B_UPDATE ,Trigger for arming state for the win B subset of the triple buffered registers" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " WIN_A_UPDATE ,rigger for arming state for the win A subset of the triple buffered registers" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GENERAL_UPDATE ,Trigger for arming state for a subset of the triple buffered registers" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CURSOR_ACT_REQ ,Non-window specific" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " WIN_D_ACT_REQ ,Window D activation request" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " WIN_C_ACT_REQ ,Window C activation request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WIN_B_ACT_REQ ,Window B activation request" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WIN_A_ACT_REQ ,Window A activation request" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GENERAL_ACT_REQ ,Non-window-specific" "Disabled,Enabled"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "STATE_CONTROL_0,State Control for Activating/Arming New Register State"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CURSOR_UPDATE ,Trigger for the arming state for a subset of the triple buffered registers" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WIN_D_UPDATE ,Trigger for the arming state for the win D subset of the triple buffered registers" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WIN_C_UPDATE ,Trigger for arming state for the win C subset of the triple buffered registers" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WIN_B_UPDATE ,Trigger for arming state for the win B subset of the triple buffered registers" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " WIN_A_UPDATE ,rigger for arming state for the win A subset of the triple buffered registers" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GENERAL_UPDATE ,Trigger for arming state for a subset of the triple buffered registers" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CURSOR_ACT_REQ ,Non-window specific" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " WIN_D_ACT_REQ ,Window D activation request" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " WIN_C_ACT_REQ ,Window C activation request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WIN_B_ACT_REQ ,Window B activation request" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WIN_A_ACT_REQ ,Window A activation request" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GENERAL_ACT_REQ ,Non-window-specific" "Disabled,Enabled"
|
|
endif
|
|
width 27.
|
|
textline " "
|
|
group.long 0x108++0x0F
|
|
line.long 0x00 "DISPLAY_WINDOW_HEADER_0,Display Window Programming Header"
|
|
bitfld.long 0x00 7. " WINDOW_D_SELECT ,Enable window D programming" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " WINDOW_C_SELECT ,Enable window C programming" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " WINDOW_B_SELECT ,Enable window B programming" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WINDOW_A_SELECT ,Enable window A programming" "Disabled,Enabled"
|
|
line.long 0x04 "REG_ACT_CONTROL_0,Register activation options"
|
|
bitfld.long 0x04 10. " WIN_D_ACT_CNTR_SEL ,Select which counter to use for window D activation" "V counter,H counter"
|
|
bitfld.long 0x04 7. " CURSOR_ACT_CNTR_SEL ,Select which counter to use for Cursor activation" "V counter,H counter"
|
|
bitfld.long 0x04 6. " WIN_C_ACT_CNTR_SEL ,Select which counter to use for window C activation" "V counter,H counter"
|
|
textline " "
|
|
bitfld.long 0x04 4. " WIN_B_ACT_CNTR_SEL ,Select which counter to use for window B activation" "V counter,H counter"
|
|
bitfld.long 0x04 2. " WIN_A_ACT_CNTR_SEL ,Select which counter to use for window A activation" "V counter,H counter"
|
|
bitfld.long 0x04 0. " GENERAL_ACT_CNTR_SEL ,Select which counter to use for general activation" "V counter,H counter"
|
|
line.long 0x08 "WIN_T_STATE_CONTROL_0,WIN_T State control register for activating/arming new register state"
|
|
bitfld.long 0x08 8. " WIN_T_UPDATE ,Trigger for the arming state for the win B subset of the triple buffered registers" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " WIN_T_ACT_REQ ,Request pending" "Not requested,Requested"
|
|
line.long 0x0C "SECURE_CONTROL_0,Secure control register for enabling secure mode"
|
|
sif CPUIS("TEGRAX1")
|
|
bitfld.long 0x0C 14. " SECURE_SOR1_PROTECT ,Blanks the display output to SOR1" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 13. " SECURE_SOR_PROTECT ,Blanks the display output to SOR" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " SECURE_DSIB_PROTECT ,Blanks the display output to DSIB" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " SECURE_DSIA_PROTECT ,Blanks the display output to DSIA" "Disabled,Enabled"
|
|
textline " "
|
|
sif CPUIS("TEGRAK1")
|
|
bitfld.long 0x0C 10. " SECURE_HDMI_PROTECT ,Blanks the display output to HDMI" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 9. " SECURE_READ_MUX ,Controls which of the double-buffered window registers are read in TZ Secure mode" "Assembly,Active"
|
|
bitfld.long 0x0C 8. " SECURE_WRITE_MUX ,Controls which of the double-buffered window registers are written in TZ Secure mode" "Assembly,Active"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SECURE_CRC_PROTECT ,Disable CRC computation when enabled" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " SECURE_CMU_PROTECT ,CMU registers are only accessible in TZ Secure mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " SECURE_ENABLE ,Secure mode enable" "Disabled,Enabled"
|
|
group.long 0x130++0x0B
|
|
line.long 0x00 "WIN_D_INCR_SYNCPT_0,WIN_D_INCR_SYNCPT_0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WIN_D_COND ,Condition mapped from raise/wait"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WIN_D_INDX ,Syncpt index value"
|
|
line.long 0x04 "WIN_D_INCR_SYNCPT_CNTRL_0,WIN_D_INCR_SYNCPT_CNTRL_0"
|
|
bitfld.long 0x04 8. " WIN_D_INCR_SYNCPT_NO_STALL ,Host interface stall" "Stalled,Not stalled"
|
|
bitfld.long 0x04 0. " WIN_D_INCR_SYNCPT_SOFT_RESET ,Internal states of the client syncpt block reset" "No reset,Reset"
|
|
line.long 0x08 "WIN_D_INCR_SYNCPT_ERROR_0,WIN_D_INCR_SYNCPT_ERROR_0"
|
|
eventfld.long 0x08 31. " COND_STATUS[31] ,FIFO overflow for COND[31]" "No overflow,Overflow"
|
|
eventfld.long 0x08 30. " [30] ,FIFO overflow for COND[30]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 29. " [29] ,FIFO overflow for COND[29]" "No overflow,Overflow"
|
|
eventfld.long 0x08 28. " [28] ,FIFO overflow for COND[28]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 27. " [27] ,FIFO overflow for COND[27]" "No overflow,Overflow"
|
|
eventfld.long 0x08 26. " [26] ,FIFO overflow for COND[26]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 25. " [25] ,FIFO overflow for COND[25]" "No overflow,Overflow"
|
|
eventfld.long 0x08 24. " [24] ,FIFO overflow for COND[24]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 23. " [23] ,FIFO overflow for COND[23]" "No overflow,Overflow"
|
|
eventfld.long 0x08 22. " [22] ,FIFO overflow for COND[22]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 21. " [21] ,FIFO overflow for COND[21]" "No overflow,Overflow"
|
|
eventfld.long 0x08 20. " [20] ,FIFO overflow for COND[20]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 19. " [19] ,FIFO overflow for COND[19]" "No overflow,Overflow"
|
|
eventfld.long 0x08 18. " [18] ,FIFO overflow for COND[18]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 17. " [17] ,FIFO overflow for COND[17]" "No overflow,Overflow"
|
|
eventfld.long 0x08 16. " [16] ,FIFO overflow for COND[16]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 15. " [15] ,FIFO overflow for COND[15]" "No overflow,Overflow"
|
|
eventfld.long 0x08 14. " [14] ,FIFO overflow for COND[14]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 13. " [13] ,FIFO overflow for COND[13]" "No overflow,Overflow"
|
|
eventfld.long 0x08 12. " [12] ,FIFO overflow for COND[12]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 11. " [11] ,FIFO overflow for COND[11]" "No overflow,Overflow"
|
|
eventfld.long 0x08 10. " [10] ,FIFO overflow for COND[10]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 9. " [9] ,FIFO overflow for COND[9]" "No overflow,Overflow"
|
|
eventfld.long 0x08 8. " [8] ,FIFO overflow for COND[8]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 7. " [7] ,FIFO overflow for COND[7]" "No overflow,Overflow"
|
|
eventfld.long 0x08 6. " [6] ,FIFO overflow for COND[6]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 5. " [5] ,FIFO overflow for COND[5]" "No overflow,Overflow"
|
|
eventfld.long 0x08 4. " [4] ,FIFO overflow for COND[4]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 3. " [3] ,FIFO overflow for COND[3]" "No overflow,Overflow"
|
|
eventfld.long 0x08 2. " [2] ,FIFO overflow for COND[2]" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x08 1. " [1] ,FIFO overflow for COND[1]" "No overflow,Overflow"
|
|
eventfld.long 0x08 0. " [0] ,FIFO overflow for COND[0]" "No overflow,Overflow"
|
|
tree.end
|
|
width 24.
|
|
tree "Display COM Registers"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "CRC_CONTROL_0,CRC Control"
|
|
bitfld.long 0x00 3. " CRC_ALWAYS ,CRC always" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CRC_INPUT_DATA ,CRC input data" "Full frame,Active display"
|
|
bitfld.long 0x00 1. " CRC_WAIT ,CRC Wait" "1 Vsync,2 Vsyncs"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CRC_ENABLE ,CRC Enable" "Disabled,Enabled"
|
|
rgroup.long 0xC04++0x03
|
|
line.long 0x00 "CRC_CHECKSUM_0,CRC Checksum"
|
|
group.long 0xC6C++0x0B
|
|
line.long 0x00 "PIN_MISC_CONTROL_0,Pin Miscellaneous Control"
|
|
bitfld.long 0x00 2. " DISP_CLOCK_OUTPUT ,Display Clock (DCLK)" "Disabled,Enabled"
|
|
line.long 0x04 "PM0_CONTROL_0,PM0 Signal Control"
|
|
bitfld.long 0x04 18.--23. " PM0_PERIOD ,PM0 Period" "4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256"
|
|
hexmask.long.word 0x04 4.--17. 1. " PM0_CLOCK_DIVIDER ,PM0 Clock Divider"
|
|
bitfld.long 0x04 0.--1. " PM0_CLOCK_SELECT ,PM0 Clock Select" "SCdiv output,Pixel,Line,Frame"
|
|
line.long 0x08 "PM0_DUTY_CYCLE_0,PM0 Duty Cycle"
|
|
hexmask.long.word 0x08 0.--8. 1. " PM0_DUTY_CYCLE ,PM0 Duty Cycle"
|
|
group.long 0xC94++0x07
|
|
line.long 0x00 "SCRATCH_REGISTER_A_0,Scratch Register A"
|
|
line.long 0x04 "SCRATCH_REGISTER_B_0,Scratch Register B"
|
|
rgroup.long 0xCA4++0x03
|
|
line.long 0x00 "CRC_CHECKSUM_LATCHED_0,CRC Checksum latched"
|
|
group.long 0xCA8++0x23
|
|
line.long 0x00 "CMU_CSC_KRR_0,CMU Color Space Conversion Matrix (KRR)"
|
|
hexmask.long.word 0x00 0.--9. 1. " KRR ,KRR"
|
|
line.long 0x04 "CMU_CSC_KGR_0,CMU Color Space Conversion Matrix (KGR)"
|
|
hexmask.long.word 0x04 0.--9. 1. " KGR ,KGR"
|
|
line.long 0x08 "CMU_CSC_KBR_0,CMU Color Space Conversion Matrix (KBR)"
|
|
hexmask.long.word 0x08 0.--9. 1. " KBR ,KBR"
|
|
line.long 0x0C "CMU_CSC_KRG_0,CMU Color Space Conversion Matrix (KRG)"
|
|
hexmask.long.word 0x0c 0.--9. 1. " KRG ,KRG"
|
|
line.long 0x10 "CMU_CSC_KGG_0,CMU Color Space Conversion Matrix (KGG)"
|
|
hexmask.long.word 0x10 0.--9. 1. " KGG ,KGG"
|
|
line.long 0x14 "CMU_CSC_KBG_0,CMU Color Space Conversion Matrix (KBG)"
|
|
hexmask.long.word 0x14 0.--9. 1. " KBG ,KBG"
|
|
line.long 0x18 "CMU_CSC_KRB_0,CMU Color Space Conversion Matrix (KRB)"
|
|
hexmask.long.word 0x18 0.--9. 1. " KRB ,KRB"
|
|
line.long 0x1C "CMU_CSC_KGB_0,CMU Color Space Conversion Matrix (KGB)"
|
|
hexmask.long.word 0x1c 0.--9. 1. " KGB ,KGB"
|
|
line.long 0x20 "CMU_CSC_KBB_0,CMU Color Space Conversion Matrix (KBB)"
|
|
hexmask.long.word 0x20 0.--9. 1. " KBB ,KBB"
|
|
group.long 0xCCC++0x03
|
|
line.long 0x00 "CMU_LUT_MASK_0,CMU LUT Mask"
|
|
bitfld.long 0x00 8.--9. " LUT2_WR_MASK ,Color channel write mask" "All,Red,Green,Blue"
|
|
bitfld.long 0x00 0.--1. " LUT1_WR_MASK ,Color channel write mask" "All,Red,Green,Blue"
|
|
group.long 0xCD8++0x07
|
|
line.long 0x00 "CMU_LUT1_0,CMU LUT1"
|
|
hexmask.long.word 0x00 16.--27. 1. " LUT1_DATA ,LUT1 DATA"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LUT1_ADDR ,LUT1 ADDR"
|
|
line.long 0x04 "CMU_LUT2_0,CMU LUT2"
|
|
hexmask.long.byte 0x04 16.--23. 1. " LUT2_DATA ,LUT2 DATA"
|
|
hexmask.long.word 0x04 0.--9. 1. " LUT2_ADDR ,LUT2 ADDR"
|
|
sif CPUIS("TEGRAX1")
|
|
group.long 0xCF8++0x63
|
|
line.long 0x00 "DSC_TOP_CTL_0,DSC_TOP_CTL_0"
|
|
hexmask.long.word 0x00 4.--19. 1. " DSC_TIMEOUT_COUNTER ,Timeout counter"
|
|
bitfld.long 0x00 3. " DSC_AUTO_RESET ,Auto reset" "No reset,Reset"
|
|
bitfld.long 0x00 2. " DSC_SLCG_OVERRIDE ,SLCG override" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DSC_ENABLE ,Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DSC_SOFT_RESET ,Soft reset" "No reset,Reset"
|
|
line.long 0x04 "DSC_DELAY_0,DSC_DELAY_0"
|
|
hexmask.long.word 0x04 0.--15. 1. " DSC_OUTPUT_DELAY ,Delay"
|
|
line.long 0x08 "DSC_COMMON_CTL_0,DSC_COMMON_CTL_0"
|
|
hexmask.long.word 0x08 16.--31. 1. " DSC_CHUNK_SIZE ,Chunk size"
|
|
bitfld.long 0x08 10. " DSC_BLOCK_PRED_ENABLE ,DSC_BLOCK_PRED_ENABLE" "Disabled,Enabled"
|
|
hexmask.long.word 0x08 0.--9. 1. " DSC_BITS_PER_PIXEL ,Bits per pixel"
|
|
line.long 0x0C "DSC_SLICE_INFO_0,DSC_SLICE_INFO_0"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSC_SLICE_HEIGHT ,Slice height in pixels"
|
|
hexmask.long.word 0x0C 0.--15. 1. " DSC_SLICE_WIDTH ,Slice width in pixels"
|
|
line.long 0x10 "DSC_RC_DELAY_INFO_0,DSC_RC_DELAY_INFO_0"
|
|
hexmask.long.word 0x10 16.--31. 1. " DSC_INITIAL_DEC_DELAY ,Number of pixels to delay the VLD"
|
|
hexmask.long.word 0x10 0.--9. 1. " DSC_INITIAL_XMIT_DELAY ,Number of pixels to delay the initial transmission"
|
|
line.long 0x14 "DSC_RC_SCALE_INFO_0,DSC_RC_SCALE_INFO_0"
|
|
hexmask.long.word 0x14 6.--21. 1. " DSC_SCALE_DECR_INTERVAL ,Decrement scale factor every scale_decr_interval group"
|
|
bitfld.long 0x14 0.--5. " DSC_INITIAL_SCALE_VALUE ,Initial value for scale factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x18 "DSC_RC_SCALE_INFO_2_0,DSC_RC_SCALE_INFO_2_0"
|
|
hexmask.long.word 0x18 0.--15. 1. " DSC_SCALE_INCR_INTERVAL ,Increment scale factor every scale_incr_interval group"
|
|
line.long 0x1C "DSC_RC_BPGOFF_INFO_0,DSC_RC_BPGOFF_INFO_0"
|
|
hexmask.long.word 0x1C 16.--31. 1. " DSC_RC_BPGOFF_INFO_0 ,BPG offset used to enforce slice bit constraint"
|
|
hexmask.long.word 0x1C 0.--15. 1. " DSC_NFL_BPG_OFFSET ,Non-first line BPG offset to use"
|
|
line.long 0x20 "DSC_RC_OFFSET_INFO_0,DSC_RC_OFFSET_INFO_0"
|
|
hexmask.long.word 0x20 16.--31. 1. " DSC_FINAL_OFFSET ,Final RC linear transformation offset value"
|
|
hexmask.long.word 0x20 1.--15. 1. " DSC_INITIAL_OFFSET ,Value to use for RC model offset at slice start"
|
|
line.long 0x24 "DSC_RC_FLATNESS_INFO_0,DSC_RC_FLATNESS_INFO_0"
|
|
hexmask.long.byte 0x24 10.--14. 0x4 " DSC_FIRST_LINE_BPG_OFFS ,BPG offset to use for first line of the slice"
|
|
bitfld.long 0x24 5.--9. " DSC_FLATNESS_MAX_QP ,Maximum QP where flatness information is sent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x24 0.--4. " DSC_FLATNESS_MIN_QP ,Minimum QP where flatness information is sent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x28 "DSC_RC_PARAM_SET_0,DSC_RC_PARAM_SET_0"
|
|
hexmask.long.byte 0x28 18.--21. 0x4 " DSC_RC_TGT_OFFSET_LO ,Offset to BPG used by RC to determine QP adjustment"
|
|
hexmask.long.byte 0x28 14.--17. 0x40 " DSC_RC_TGT_OFFSET_HI ,Offset to BPG used by RC to determine QP adjustment"
|
|
bitfld.long 0x28 9.--13. " DSC_RC_QUANT_INCR_LIMIT1 ,Slow down incrementing once the range reaches this value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x28 4.--8. " DSC_RC_QUANT_INCR_LIMIT0 ,Slow down incrementing once the range reaches this value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x28 0.--3. " DSC_RC_EDGE_FACTOR ,Factor to determine if an edge is present based on the bits produced" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x2C "DSC_RC_BUF_THRESH0_0,DC_COM_DSC_RC_BUF_THRESH0_0"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " DSC_RC_BUF_THRESH1 ,Threshold1 defining the buffer ranges"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " DSC_RC_BUF_THRESH0 ,Threshold0 defining the buffer ranges"
|
|
hexmask.long.word 0x2C 0.--15. 1. " DSC_RC_MODEL_SIZE ,Total size of RC model"
|
|
line.long 0x30 "DSC_RC_BUF_THRESH1_0,DC_COM_DSC_RC_BUF_THRESH1_0"
|
|
hexmask.long.byte 0x30 24.--31. 1. " DSC_RC_BUF_THRESH5 ,Threshold5 defining the buffer ranges"
|
|
hexmask.long.byte 0x30 16.--23. 1. " DSC_RC_BUF_THRESH4 ,Threshold4 defining the buffer ranges"
|
|
hexmask.long.byte 0x30 8.--15. 1. " DSC_RC_BUF_THRESH3 ,Threshold3 defining the buffer ranges"
|
|
textline " "
|
|
hexmask.long.byte 0x30 0.--7. 1. " DSC_RC_BUF_THRESH2 ,Threshold2 defining the buffer ranges"
|
|
line.long 0x34 "DSC_RC_BUF_THRESH2_0,DSC_RC_BUF_THRESH2_0"
|
|
hexmask.long.byte 0x34 24.--31. 1. " DSC_RC_BUF_THRESH9 ,Threshold9 defining the buffer ranges"
|
|
hexmask.long.byte 0x34 16.--23. 1. " DSC_RC_BUF_THRESH8 ,Threshold8 defining the buffer ranges"
|
|
hexmask.long.byte 0x34 8.--15. 1. " DSC_RC_BUF_THRESH7 ,Threshold7 defining the buffer ranges"
|
|
textline " "
|
|
hexmask.long.byte 0x34 0.--7. 1. " DSC_RC_BUF_THRESH6 ,Threshold6 defining the buffer ranges"
|
|
line.long 0x38 "DSC_RC_BUF_THRESH3_0,DSC_RC_BUF_THRESH3_0"
|
|
hexmask.long.byte 0x38 24.--31. 1. " DSC_RC_BUF_THRESH13 ,Threshold13 defining the buffer ranges"
|
|
hexmask.long.byte 0x38 16.--23. 1. " DSC_RC_BUF_THRESH12 ,Threshold12 defining the buffer ranges"
|
|
hexmask.long.byte 0x38 8.--15. 1. " DSC_RC_BUF_THRESH11 ,Threshold11 defining the buffer ranges"
|
|
textline " "
|
|
hexmask.long.byte 0x38 0.--7. 1. " DSC_RC_BUF_THRESH10 ,Threshold10 defining the buffer ranges"
|
|
line.long 0x3C "DSC_RC_RANGE_CFG0_0,DSC_RC_RANGE_CFG0_0"
|
|
hexmask.long.word 0x3C 16.--31. 1. " DSC_RC_RANGE_PARAM1 ,Parameters for RC range1"
|
|
hexmask.long.word 0x3C 0.--15. 1. " DSC_RC_RANGE_PARAM0 ,Parameters for RC range0"
|
|
line.long 0x40 "DSC_RC_RANGE_CFG1_0,DSC_RC_RANGE_CFG1_0"
|
|
hexmask.long.word 0x40 16.--31. 1. " DSC_RC_RANGE_PARAM3 ,Parameters for RC range3"
|
|
hexmask.long.word 0x40 0.--15. 1. " DSC_RC_RANGE_PARAM2 ,Parameters for RC range2"
|
|
line.long 0x44 "DSC_RC_RANGE_CFG2_0,DSC_RC_RANGE_CFG2_0"
|
|
hexmask.long.word 0x44 16.--31. 1. " DSC_RC_RANGE_PARAM5 ,Parameters for RC range5"
|
|
hexmask.long.word 0x44 0.--15. 1. " DSC_RC_RANGE_PARAM4 ,Parameters for RC range4"
|
|
line.long 0x48 "DSC_RC_RANGE_CFG3_0,DSC_RC_RANGE_CFG3_0"
|
|
hexmask.long.word 0x48 16.--31. 1. " DSC_RC_RANGE_PARAM7 ,Parameters for RC range7"
|
|
hexmask.long.word 0x48 0.--15. 1. " DSC_RC_RANGE_PARAM6 ,Parameters for RC range6"
|
|
line.long 0x4C "DSC_RC_RANGE_CFG4_0,DSC_RC_RANGE_CFG4_0"
|
|
hexmask.long.word 0x4C 16.--31. 1. " DSC_RC_RANGE_PARAM9 ,Parameters for RC range9"
|
|
hexmask.long.word 0x4C 0.--15. 1. " DSC_RC_RANGE_PARAM8 ,Parameters for RC range8"
|
|
line.long 0x50 "DSC_RC_RANGE_CFG5_0,DSC_RC_RANGE_CFG5_0"
|
|
hexmask.long.word 0x50 16.--31. 1. " DSC_RC_RANGE_PARAM11 ,Parameters for RC range11"
|
|
hexmask.long.word 0x50 0.--15. 1. " DSC_RC_RANGE_PARAM10 ,Parameters for RC range10"
|
|
line.long 0x54 "DSC_RC_RANGE_CFG6_0,DSC_RC_RANGE_CFG6_0"
|
|
hexmask.long.word 0x54 16.--31. 1. " DSC_RC_RANGE_PARAM13 ,Parameters for RC range13"
|
|
hexmask.long.word 0x54 0.--15. 1. " DSC_RC_RANGE_PARAM12 ,Parameters for RC range12"
|
|
line.long 0x58 "DSC_RC_RANGE_CFG7_0,DSC_RC_RANGE_CFG7_0"
|
|
hexmask.long.word 0x58 16.--31. 1. " DSC_RC_RANGE_PARAM15 ,Parameters for RC range15"
|
|
hexmask.long.word 0x58 0.--15. 1. " DSC_RC_RANGE_PARAM14 ,Parameters for RC range14"
|
|
line.long 0x5C "DSC_UNIT_SET_0,DSC_UNIT_SET_0"
|
|
bitfld.long 0x5C 2. " DSC_LINEBUF_DEPTH ,Line buffer depth" "9 bits,8 bits"
|
|
bitfld.long 0x5C 0.--1. " DSC_SLICE_NUM_MINUS1_IN_LINE ,The slice number in the line" "1,2,3,4"
|
|
line.long 0x60 "DSC_CRC_CONTROL_0,DSC_CRC_CONTROL_0"
|
|
bitfld.long 0x60 1. " DSC_CRC_ALWAYS ,CRC ALWAYS" "Disabled,Enabled"
|
|
bitfld.long 0x60 0. " DSC_CRC_ENABLE ,CRC Enable" "Disabled,Enabled"
|
|
rgroup.long 0xD5C++0x0B
|
|
line.long 0x00 "DSC_CRC_CHECKSUM_0,CRC Checksum latched"
|
|
line.long 0x04 "DSC_STATUS_0,DC_COM_DSC_STATUS_0"
|
|
bitfld.long 0x04 16.--17. " DSC_STATUS_SLICEID ,Slice ID" "0,1,2,3"
|
|
hexmask.long.word 0x04 0.--15. 1. " DSC_STATUS_HINDEX ,Horizontal index"
|
|
line.long 0x08 "DSC_STATUS_2_0,DSC_STATUS_2_0"
|
|
bitfld.long 0x08 16. " DSC_STATUS_BUSY ,Busy" "Not busy,Busy"
|
|
hexmask.long.word 0x08 0.--15. 1. " DSC_STATUS_VINDEX ,Vertical index"
|
|
endif
|
|
tree.end
|
|
width 35.
|
|
tree "Display DISP Registers"
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "DISP_SIGNAL_OPTIONS0_0,Display Signal Options 0"
|
|
bitfld.long 0x00 26. " M1_ENABLE ,M1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " M0_ENABLE ,M0 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " V_PULSE3_ENABLE ,V Pulse 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " V_PULSE2_ENABLE ,V Pulse 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " V_PULSE1_ENABLE ,V Pulse 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " V_PULSE0_ENABLE ,V Pulse 0 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " H_PULSE2_ENABLE ,H Pulse 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " H_PULSE1_ENABLE ,H Pulse 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " H_PULSE0_ENABLE ,H Pulse 0 Enable" "Disabled,Enabled"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "DISP_WIN_OPTIONS_0,Display Window Options"
|
|
sif CPUIS("TEGRAK1")
|
|
bitfld.long 0x00 30. " HDMI_ENABLE ,HDMI interface" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " DSI_ENABLE ,MIPI Display Serial Interface Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif CPUIS("TEGRAX1")
|
|
bitfld.long 0x00 27. " SOR1_TIMING_CYA ,HDMI expects a delayed vsync and preamble compared to DP" "DP,HDMI"
|
|
bitfld.long 0x00 26. " SOR1_ENABLE ,SOR1 interface - DP/HDMI" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " SOR_ENABLE ,SOR Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CURSOR_ENABLE ,Cursor Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x1014++0x1B
|
|
line.long 0x00 "DISP_TIMING_OPTIONS_0,Display Timing Options"
|
|
hexmask.long.word 0x00 0.--12. 1. " VSYNC_H_POSITION ,VSYNC Horizontal Position"
|
|
line.long 0x04 "REF_TO_SYNC_0,H/V Reference to Sync"
|
|
hexmask.long.word 0x04 16.--28. 1. " V_REF_TO_SYNC ,V reference to VSYNC"
|
|
hexmask.long.word 0x04 0.--12. 1. " H_REF_TO_SYNC ,H reference to HSYNC"
|
|
line.long 0x08 "SYNC_WIDTH_0,H/V SYNC Pulse Width"
|
|
hexmask.long.word 0x08 16.--28. 1. " V_SYNC_WIDTH ,VSYNC pulse width"
|
|
hexmask.long.word 0x08 0.--12. 1. " H_SYNC_WIDTH ,HSYNC pulse width"
|
|
line.long 0x0C "BACK_PORCH_0,H/V Back Porch"
|
|
hexmask.long.word 0x0C 16.--28. 1. " V_BACK_PORCH ,V back porch"
|
|
hexmask.long.word 0x0C 0.--12. 1. " H_BACK_PORCH ,H back porch"
|
|
line.long 0x10 "DISP_ACTIVE_0,H/V Display Active width"
|
|
hexmask.long.word 0x10 16.--28. 1. " V_DISP_ACTIVE ,V display active width"
|
|
hexmask.long.word 0x10 0.--12. 1. " H_DISP_ACTIVE ,H display active width"
|
|
line.long 0x14 "FRONT_PORCH_0,H/V Front Porch"
|
|
hexmask.long.word 0x14 16.--28. 1. " V_FRONT_PORCH ,VSYNC front porch"
|
|
hexmask.long.word 0x14 0.--12. 1. " H_FRONT_PORCH ,VSYNC front porch"
|
|
line.long 0x18 "H_PULSE0_CONTROL_0,H Pulse 0 Control"
|
|
bitfld.long 0x18 8.--11. " H_PULSE0_LAST ,H Pulse 0 Last point" "Start A,End A,Start B,End B,Start C,End C,Start D,End D,?..."
|
|
bitfld.long 0x18 6.--7. " H_PULSE0_V_QUAL ,H Pulse 0 Vertical Qualifier" "Always,,V active,V active+1"
|
|
textline " "
|
|
bitfld.long 0x18 4. " H_PULSE0_POLARITY ,H Pulse 0 Polarity" "High,Low"
|
|
bitfld.long 0x18 3. " H_PULSE0_MODE ,H Pulse 0 Mode" "Normal,Single-clock"
|
|
group.long 0x1030++0x03
|
|
line.long 0x00 "H_PULSE0_POSITION_A_0,H Pulse 0 Position A"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE0_END_A ,H Pulse 0 End A"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE0_START_A ,H Pulse 0 Start A"
|
|
group.long 0x1034++0x03
|
|
line.long 0x00 "H_PULSE0_POSITION_B_0,H Pulse 0 Position B"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE0_END_B ,H Pulse 0 End B"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE0_START_B ,H Pulse 0 Start B"
|
|
group.long 0x1038++0x03
|
|
line.long 0x00 "H_PULSE0_POSITION_C_0,H Pulse 0 Position C"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE0_END_C ,H Pulse 0 End C"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE0_START_C ,H Pulse 0 Start C"
|
|
group.long 0x103C++0x03
|
|
line.long 0x00 "H_PULSE0_POSITION_D_0,H Pulse 0 Position D"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE0_END_D ,H Pulse 0 End D"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE0_START_D ,H Pulse 0 Start D"
|
|
group.long 0x1040++0x03
|
|
line.long 0x00 "H_PULSE1_CONTROL_0,H Pulse 1 Control"
|
|
bitfld.long 0x00 8.--11. " H_PULSE1_LAST ,H Pulse 1 Last point" "Start A,End A,Start B,End B,Start C,End C,Start D,End D,?..."
|
|
bitfld.long 0x00 6.--7. " H_PULSE1_V_QUAL ,H Pulse 1 Vertical Qualifier" "Always,,V active,V active+1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " H_PULSE1_POLARITY ,H Pulse 1 Polarity" "High,Low"
|
|
bitfld.long 0x00 3. " H_PULSE1_MODE ,H Pulse 1 Mode" "Normal,Single-clock"
|
|
group.long 0x1044++0x03
|
|
line.long 0x00 "H_PULSE1_POSITION_A_0,H Pulse 1 Position A"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE1_END_A ,H Pulse 1 End A"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE1_START_A ,H Pulse 1 Start A"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "H_PULSE1_POSITION_B_0,H Pulse 1 Position B"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE1_END_B ,H Pulse 1 End B"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE1_START_B ,H Pulse 1 Start B"
|
|
group.long 0x104C++0x03
|
|
line.long 0x00 "H_PULSE1_POSITION_C_0,H Pulse 1 Position C"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE1_END_C ,H Pulse 1 End C"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE1_START_C ,H Pulse 1 Start C"
|
|
group.long 0x1050++0x03
|
|
line.long 0x00 "H_PULSE1_POSITION_D_0,H Pulse 1 Position D"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE1_END_D ,H Pulse 1 End D"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE1_START_D ,H Pulse 1 Start D"
|
|
group.long 0x1054++0x03
|
|
line.long 0x00 "H_PULSE2_CONTROL_0,H Pulse 2 Control"
|
|
bitfld.long 0x00 8.--11. " H_PULSE2_LAST ,H Pulse 2 Last point" "Start A,End A,Start B,End B,Start C,End C,Start D,End D,?..."
|
|
bitfld.long 0x00 6.--7. " H_PULSE2_V_QUAL ,H Pulse 2 Vertical Qualifier" "Always,,V active,V active+1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " H_PULSE2_POLARITY ,H Pulse 2 Polarity" "High,Low"
|
|
bitfld.long 0x00 3. " H_PULSE2_MODE ,H Pulse 2 Mode" "Normal,Single-clock"
|
|
group.long 0x1058++0x03
|
|
line.long 0x00 "H_PULSE2_POSITION_A_0,H Pulse 2 Position A"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE2_END_A ,H Pulse 2 End A"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE2_START_A ,H Pulse 2 Start A"
|
|
group.long 0x105C++0x03
|
|
line.long 0x00 "H_PULSE2_POSITION_B_0,H Pulse 2 Position B"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE2_END_B ,H Pulse 2 End B"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE2_START_B ,H Pulse 2 Start B"
|
|
group.long 0x1060++0x03
|
|
line.long 0x00 "H_PULSE2_POSITION_C_0,H Pulse 2 Position C"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE2_END_C ,H Pulse 2 End C"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE2_START_C ,H Pulse 2 Start C"
|
|
group.long 0x1064++0x03
|
|
line.long 0x00 "H_PULSE2_POSITION_D_0,H Pulse 2 Position D"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_PULSE2_END_D ,H Pulse 2 End D"
|
|
hexmask.long.word 0x00 0.--12. 1. " H_PULSE2_START_D ,H Pulse 2 Start D"
|
|
group.long 0x1068++0x03
|
|
line.long 0x00 "V_PULSE0_CONTROL_0,V Pulse 0 Control"
|
|
hexmask.long.word 0x00 16.--28. 1. " V_PULSE0_H_POSITION ,V Pulse 0 Horizontal Position"
|
|
bitfld.long 0x00 8.--11. " V_PULSE0_LAST ,V Pulse 0 Last point" "Start A,End A,Start B,End B,Start C,End C,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " V_PULSE0_DELAY ,V Pulse 0 Delay" "No delay,1-line delay,2-line delay,?..."
|
|
bitfld.long 0x00 4. " V_PULSE0_POLARITY ,V Pulse 0 Polarity" "High,Low"
|
|
group.long 0x106C++0x03
|
|
line.long 0x00 "V_PULSE0_POSITION_A_0,H Pulse 0 Position A"
|
|
hexmask.long.word 0x00 16.--28. 1. " V_PULSE0_END_A ,V Pulse 0 End A"
|
|
hexmask.long.word 0x00 0.--12. 1. " V_PULSE0_START_A ,V Pulse 0 Start A"
|
|
group.long 0x1070++0x03
|
|
line.long 0x00 "V_PULSE0_POSITION_B_0,H Pulse 0 Position B"
|
|
hexmask.long.word 0x00 16.--28. 1. " V_PULSE0_END_B ,V Pulse 0 End B"
|
|
hexmask.long.word 0x00 0.--12. 1. " V_PULSE0_START_B ,V Pulse 0 Start B"
|
|
group.long 0x1074++0x03
|
|
line.long 0x00 "V_PULSE0_POSITION_C_0,H Pulse 0 Position C"
|
|
hexmask.long.word 0x00 16.--28. 1. " V_PULSE0_END_C ,V Pulse 0 End C"
|
|
hexmask.long.word 0x00 0.--12. 1. " V_PULSE0_START_C ,V Pulse 0 Start C"
|
|
group.long 0x1078++0x03
|
|
line.long 0x00 "V_PULSE1_CONTROL_0,V Pulse 1 Control"
|
|
hexmask.long.word 0x00 16.--28. 1. " V_PULSE1_H_POSITION ,V Pulse 1 Horizontal Position"
|
|
bitfld.long 0x00 8.--11. " V_PULSE1_LAST ,V Pulse 1 Last point" "Start A,End A,Start B,End B,Start C,End C,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " V_PULSE1_DELAY ,V Pulse 1 Delay" "No delay,1-line delay,2-line delay,?..."
|
|
bitfld.long 0x00 4. " V_PULSE1_POLARITY ,V Pulse 1 Polarity" "High,Low"
|
|
group.long 0x107C++0x03
|
|
line.long 0x00 "V_PULSE1_POSITION_A_0,H Pulse 1 Position A"
|
|
hexmask.long.word 0x00 16.--28. 1. " V_PULSE1_END_A ,V Pulse 1 End A"
|
|
hexmask.long.word 0x00 0.--12. 1. " V_PULSE1_START_A ,V Pulse 1 Start A"
|
|
group.long 0x1080++0x03
|
|
line.long 0x00 "V_PULSE1_POSITION_B_0,H Pulse 1 Position B"
|
|
hexmask.long.word 0x00 16.--28. 1. " V_PULSE1_END_B ,V Pulse 1 End B"
|
|
hexmask.long.word 0x00 0.--12. 1. " V_PULSE1_START_B ,V Pulse 1 Start B"
|
|
group.long 0x1084++0x03
|
|
line.long 0x00 "V_PULSE1_POSITION_C_0,H Pulse 1 Position C"
|
|
hexmask.long.word 0x00 16.--28. 1. " V_PULSE1_END_C ,V Pulse 1 End C"
|
|
hexmask.long.word 0x00 0.--12. 1. " V_PULSE1_START_C ,V Pulse 1 Start C"
|
|
group.long 0x1088++0x0F
|
|
line.long 0x00 "V_PULSE2_CONTROL_0,V Pulse 2 Control"
|
|
hexmask.long.word 0x00 16.--28. 1. " V_PULSE2_H_POSITION ,V Pulse 2 Horizontal Position"
|
|
bitfld.long 0x00 8. " V_PULSE2_LAST ,V Pulse 2 Last point" "Start A,End A"
|
|
textline " "
|
|
bitfld.long 0x00 4. " V_PULSE2_POLARITY ,V Pulse 2 Polarity" "High,Low"
|
|
line.long 0x04 "V_PULSE2_POSITION_A_0,H Pulse 2 Position A"
|
|
hexmask.long.word 0x04 16.--28. 1. " V_PULSE2_END_A ,V Pulse 2 End A"
|
|
hexmask.long.word 0x04 0.--12. 1. " V_PULSE2_START_A ,V Pulse 2 Start A"
|
|
line.long 0x08 "V_PULSE3_CONTROL_0,V Pulse 3 Control"
|
|
hexmask.long.word 0x08 16.--28. 1. " V_PULSE3_H_POSITION ,V Pulse 3 Horizontal Position"
|
|
bitfld.long 0x08 8. " V_PULSE3_LAST ,V Pulse 3 Last point" "Start A,End A"
|
|
textline " "
|
|
bitfld.long 0x08 4. " V_PULSE3_POLARITY ,V Pulse 3 Polarity" "High,Low"
|
|
line.long 0x0C "V_PULSE3_POSITION_A_0,H Pulse 3 Position A"
|
|
hexmask.long.word 0x0C 16.--28. 1. " V_PULSE3_END_A ,V Pulse 3 End A"
|
|
hexmask.long.word 0x0C 0.--12. 1. " V_PULSE3_START_A ,V Pulse 3 Start A"
|
|
textline " "
|
|
group.long 0x10B8++0x07
|
|
line.long 0x00 "DISP_CLOCK_CONTROL_0,Display Clock Control"
|
|
bitfld.long 0x00 8.--11. " PIXEL_CLK_DIVIDER ,Pixel Clock Divider" "/1,/1.5,/2,/3,/4,/6,/8,/9,/12,/16,/18,/24,/13,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " SHIFT_CLK_DIVIDER ,Shift Clock Divider"
|
|
line.long 0x04 "DISP_INTERFACE_CONTROL_0,Display Interface Control"
|
|
bitfld.long 0x04 9. " DISP_DATA_ORDER ,Display Data Order" "RED_BLUE,BLUE_RED"
|
|
bitfld.long 0x04 8. " DISP_DATA_ALIGNMENT ,Display Data Alignment" "MSB,LSB"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " DISP_DATA_FORMAT ,Display Data Format Pixel Clock Divider" "DF1P1C,DF1P2C24B,DF1P2C18B,DF1P2C16B,DF1S,DF2S,DF3S,DFSPI,DF1P3C24B,DF2P1C18B,DFDUAL1P1C18B,?..."
|
|
group.long 0x10C0++0x03
|
|
line.long 0x00 "DISP_COLOR_CONTROL_0,Display Color Control"
|
|
sif CPUIS("TEGRAK1")
|
|
bitfld.long 0x00 27. " LCD_MD3 ,LCD Mode 3 signal" "Low,High"
|
|
bitfld.long 0x00 26. " LCD_MD2 ,LCD Mode 2 signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " LCD_MD1 ,LCD Mode 1 signal" "Low,High"
|
|
bitfld.long 0x00 24. " LCD_MD0 ,LCD Mode 0 signal" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " CMU_ENABLE ,CMU_ENABLE" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " NON_BASE_COLOR ,Non Base Color" "Zeros,Ones"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BLANK_COLOR ,Blank Color" "Zeros,Ones"
|
|
bitfld.long 0x00 16. " DISP_COLOR_SWAP ,Display Color Swap" "RGB,BGR"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " ORD_DITHER_ROTATION ,Ordered Dither Frame Rotation" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " DITHER_CONTROL ,Dither Control" "Disabled,,Ordered,Temporal"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TEMPORAL_DITHER_PHASE ,Temporal dither LFSR phase control" "Previous val,34'H3FFFFFFFF,34'H155555555,34'H2AAAAAAAA"
|
|
bitfld.long 0x00 0.--3. " BASE_COLOR_SIZE ,Display Base Color Size" "BASE666,BASE111,BASE222,BASE333,BASE444,BASE555,BASE565,BASE332,BASE888,?..."
|
|
textline " "
|
|
group.long 0x10D8++0x0F
|
|
line.long 0x00 "COLOR_KEY0_LOWER_0,Color Key 0 Lower value"
|
|
hexmask.long.byte 0x00 24.--31. 1. " COLOR_KEY0_L_A ,Color Key 0 Alpha (0xFF) Lower value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " COLOR_KEY0_L_B ,Color Key 0 Blue (U) Lower value"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " COLOR_KEY0_L_G ,Color Key 0 Green (Y) Lower value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " COLOR_KEY0_L_R ,Color Key 0 Red (V) Lower value"
|
|
line.long 0x04 "COLOR_KEY0_UPPER_0,Color Key 0 Upper value"
|
|
hexmask.long.byte 0x04 24.--31. 1. " COLOR_KEY0_U_A ,Color Key 0 Alpha (0xFF) Upper value"
|
|
hexmask.long.byte 0x04 16.--23. 1. " COLOR_KEY0_U_B ,Color Key 0 Blue (U) Upper value"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " COLOR_KEY0_U_G ,Color Key 0 Green (Y) Upper value"
|
|
hexmask.long.byte 0x04 0.--7. 1. " COLOR_KEY0_U_R ,Color Key 0 Red (V) Upper value"
|
|
line.long 0x08 "COLOR_KEY1_LOWER_0,Color Key 1 Lower value"
|
|
hexmask.long.byte 0x08 24.--31. 1. " COLOR_KEY1_L_A ,Color Key 1 Alpha (0xFF) Lower value"
|
|
hexmask.long.byte 0x08 16.--23. 1. " COLOR_KEY1_L_B ,Color Key 1 Blue (U) Lower value"
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " COLOR_KEY1_L_G ,Color Key 1 Green (Y) Lower value"
|
|
hexmask.long.byte 0x08 0.--7. 1. " COLOR_KEY1_L_R ,Color Key 1 Red (V) Lower value"
|
|
line.long 0x0C "COLOR_KEY1_UPPER_0,Color Key 1 Upper value"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " COLOR_KEY1_U_A ,Color Key 1 Alpha (0xFF) Upper value"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " COLOR_KEY1_U_B ,Color Key 1 Blue (U) Upper value"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 8.--15. 1. " COLOR_KEY1_U_G ,Color Key 1 Green (Y) Upper value"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " COLOR_KEY1_U_R ,Color Key 1 Red (V) Upper value"
|
|
group.long 0x10F0++0x0B
|
|
line.long 0x00 "CURSOR_FOREGROUND_0,Cursor Foreground color"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CURSOR_FOREGROUND_B ,Cursor Blue Foreground Color"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CURSOR_FOREGROUND_G ,Cursor Green Foreground Color"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CURSOR_FOREGROUND_R ,Cursor Red Foreground Color"
|
|
line.long 0x04 "CURSOR_BACKGROUND_0,Cursor Background color"
|
|
hexmask.long.byte 0x04 16.--23. 1. " CURSOR_BACKGROUND_B ,Cursor Blue Background Color"
|
|
hexmask.long.byte 0x04 8.--15. 1. " CURSOR_BACKGROUND_G ,Cursor Green Background Color"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " CURSOR_BACKGROUND_R ,Cursor Red Background Color"
|
|
textline " "
|
|
line.long 0x08 "CURSOR_START_ADDR_0,Cursor Start Address"
|
|
bitfld.long 0x08 28.--29. " CURSOR_CLIPPING ,Cursor Clipping Select" "Display,Window A,Window B,Window C"
|
|
bitfld.long 0x08 24.--25. " CURSOR_SIZE ,Cursor Size" "C32x32,C64x64,C128X128,C256X256"
|
|
textline " "
|
|
hexmask.long.tbyte 0x08 0.--21. 1. " CURSOR_START_ADDR ,Cursor Start Address bits"
|
|
sif CPUIS("TEGRAK1")
|
|
group.long 0x10FC++0x03
|
|
line.long 0x00 "CURSOR_START_ADDR_NS_0,Shadow of Cursor Start Address"
|
|
bitfld.long 0x00 28.--29. " CURSOR_CLIPPING_NS ,Cursor Clipping Select" "Display,Window A,Window B,Window C"
|
|
bitfld.long 0x00 24.--25. " CURSOR_SIZE_NS ,Cursor Size" "32x32,64x64,C128X128,C256X256"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--21. 1. " CURSOR_START_ADDR_NS ,Cursor Start Address bits"
|
|
endif
|
|
group.long 0x1100++0x03
|
|
line.long 0x00 "CURSOR_POSITION_0,Cursor Position"
|
|
hexmask.long.word 0x00 16.--29. 1. " V_CURSOR_POSITION ,V cursor position"
|
|
hexmask.long.word 0x00 0.--13. 1. " H_CURSOR_POSITION ,H cursor position"
|
|
sif CPUIS("TEGRAK1")
|
|
group.long 0x1104++0x03
|
|
line.long 0x00 "CURSOR_POSITION_NS_0,Shadow of Cursor Position"
|
|
hexmask.long.word 0x00 16.--29. 1. " V_CURSOR_POSITION_NS ,V cursor position"
|
|
hexmask.long.word 0x00 0.--13. 1. " H_CURSOR_POSITION_NS ,H cursor position"
|
|
endif
|
|
group.long 0x1200++0x03
|
|
line.long 0x00 "DC_MCCIF_FIFOCTRL_0,Memory Client Interface FIFO Control Register"
|
|
bitfld.long 0x00 20. " DC_RCLK_OVR_MODE ,DC_RCLK_OVERRIDE" "LEGACY,ON"
|
|
bitfld.long 0x00 19. " DC_WCLK_OVR_MODE ,DC_WCLK_OVERRIDE" "LEGACY,ON"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DC_CCLK_OVERRIDE ,DC_CCLK_OVERRIDE" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DC_RCLK_OVERRIDE ,DC_RCLK_OVERRIDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DC_WCLK_OVERRIDE ,DC_WCLK_OVERRIDE" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DC_MCCIF_RDCL_RDFAST ,DC_MCCIF_RDCL_RDFAST" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DC_MCCIF_WRMC_CLLE2X ,DC_MCCIF_WRMC_CLLE2X" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DC_MCCIF_RDMC_RDFAST ,DC_MCCIF_RDMC_RDFAST" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DC_MCCIF_WRCL_MCLE2X ,DC_MCCIF_WRCL_MCLE2X" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x1204++0x03
|
|
line.long 0x00 "MCCIF_DISPLAY0A_HYST_0,Memory Client Hysteresis Control Register"
|
|
eventfld.long 0x00 31. " CBR_DISPLAY0A2MC_HYST_EN ,CBR_DISPLAY0A2MC_HYST_EN" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--30. " CBR_DISPLAY0A2MC_HYST_REQ_TH ,CBR_DISPLAY0A2MC_HYST_REQ_TH" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CBR_DISPLAY0A2MC_HYST_TM ,CBR_DISPLAY0A2MC_HYST_TM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CBR_DISPLAY0A2MC_DHYST_TH ,CBR_DISPLAY0A2MC_DHYST_TH"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CBR_DISPLAY0A2MC_DHYST_TM ,CBR_DISPLAY0A2MC_DHYST_TM"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CBR_DISPLAY0A2MC_HYST_REQ_TM ,CBR_DISPLAY0A2MC_HYST_REQ_TM"
|
|
group.long 0x1208++0x03
|
|
line.long 0x00 "MCCIF_DISPLAY0B_HYST_0,Memory Client Hysteresis Control Register"
|
|
eventfld.long 0x00 31. " CBR_DISPLAY0B2MC_HYST_EN ,CBR_DISPLAY0B2MC_HYST_EN" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--30. " CBR_DISPLAY0B2MC_HYST_REQ_TH ,CBR_DISPLAY0B2MC_HYST_REQ_TH" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CBR_DISPLAY0B2MC_HYST_TM ,CBR_DISPLAY0B2MC_HYST_TM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CBR_DISPLAY0B2MC_DHYST_TH ,CBR_DISPLAY0B2MC_DHYST_TH"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CBR_DISPLAY0B2MC_DHYST_TM ,CBR_DISPLAY0B2MC_DHYST_TM"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CBR_DISPLAY0B2MC_HYST_REQ_TM ,CBR_DISPLAY0B2MC_HYST_REQ_TM"
|
|
group.long 0x120C++0x03
|
|
line.long 0x00 "MCCIF_DISPLAY0C_HYST_0,Memory Client Hysteresis Control Register"
|
|
eventfld.long 0x00 31. " CBR_DISPLAY0C2MC_HYST_EN ,CBR_DISPLAY0C2MC_HYST_EN" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--30. " CBR_DISPLAY0C2MC_HYST_REQ_TH ,CBR_DISPLAY0C2MC_HYST_REQ_TH" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " CBR_DISPLAY0C2MC_HYST_TM ,CBR_DISPLAY0C2MC_HYST_TM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CBR_DISPLAY0C2MC_DHYST_TH ,CBR_DISPLAY0C2MC_DHYST_TH"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CBR_DISPLAY0C2MC_DHYST_TM ,CBR_DISPLAY0C2MC_DHYST_TM"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CBR_DISPLAY0C2MC_HYST_REQ_TM ,CBR_DISPLAY0C2MC_HYST_REQ_TM"
|
|
textline " "
|
|
group.long 0x1304++0x03
|
|
line.long 0x00 "DISP_MISC_CONTROL_0,Miscellaneous controls"
|
|
eventfld.long 0x00 1. " UF_LINE_FLUSH ,Enable underflow line flush" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PHASE_SHIFT_2P1C18B ,Enable phase shift for 2P1C format" "Disabled,Enabled"
|
|
group.long 0x1308++0x03
|
|
line.long 0x00 "SD_CONTROL_0,PRISM 3 Control"
|
|
bitfld.long 0x00 29.--30. " K_INIT_BIAS ,BIAS of the initial K bias MSB of count" "BIAS0,BIAS1,BIAS_HALF,BIAS_MSB"
|
|
bitfld.long 0x00 28. " SD_FRAME_PROC_CONTROL ,Run per-frame processing" "VSYNC,VPULSE2"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SMOOTH_K_ENABLE ,Enable maximum raw K change per frame is limited to SMOOTH_K_INCR" "Disabled,Enabled"
|
|
eventfld.long 0x00 14. " SOFT_CLIPPING_ENABLE ,Enable enhancement gain is reduced for pixels above SOFT_CLIPPING_THRESHOLD level" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SD_WINDOW_ENABLE ,Enable constrain histogram to a rectangular subset of display" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " K_LIMIT_ENABLE ,Enable Max K is taken from K_LIMIT register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SD_CORRECTION_MODE ,Determines which K values are used to modify the pixel values" "AUTO_CORRECT,MANUAL"
|
|
bitfld.long 0x00 10. " SD_ONE_SHOT ,Enables the PRISM 3 function for one frame only" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " HW_UPDATE_DLY ,Determines the delay" "No delay,1 frame,2 frame,3 frame"
|
|
bitfld.long 0x00 5.--7. " AGGRESSIVENESS ,The aggressiveness level of the PRISM 3 algorithm" "0,1,2,3,4,5,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " BIN_WIDTH ,Width of the Histogram bins in quantization levels" "1,2,4,8"
|
|
bitfld.long 0x00 2. " USE_VID_LUMA ,Use Video Luminance control of luminance" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SD_ENABLE ,Enables the PRISM 3 Function" "Disabled,Enabled,ONE_SHOT,?..."
|
|
sif CPUIS("TEGRAX1")
|
|
group.long 0x130C++0x03
|
|
line.long 0x00 "SD_CSC_COEFF_0,SD_CSC_COEFF_0"
|
|
bitfld.long 0x00 20.--23. " B_COEFF ,Blue coefficient for luminance calculation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " G_COEFF ,Green coefficient for luminance calculation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " R_COEFF ,Red coefficient for luminance calculation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
group.long 0x1310++0x03
|
|
line.long 0x00 "SD_LUT_0,SD_LUT_0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_LUT ,Blue Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G_LUT ,Green Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R_LUT ,Red Enhancement value (k) Look Up Table"
|
|
group.long 0x1314++0x03
|
|
line.long 0x00 "SD_LUT_1,SD_LUT_1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_LUT ,Blue Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G_LUT ,Green Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R_LUT ,Red Enhancement value (k) Look Up Table"
|
|
group.long 0x1318++0x03
|
|
line.long 0x00 "SD_LUT_2,SD_LUT_2"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_LUT ,Blue Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G_LUT ,Green Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R_LUT ,Red Enhancement value (k) Look Up Table"
|
|
group.long 0x131C++0x03
|
|
line.long 0x00 "SD_LUT_3,SD_LUT_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_LUT ,Blue Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G_LUT ,Green Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R_LUT ,Red Enhancement value (k) Look Up Table"
|
|
group.long 0x1320++0x03
|
|
line.long 0x00 "SD_LUT_4,SD_LUT_4"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_LUT ,Blue Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G_LUT ,Green Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R_LUT ,Red Enhancement value (k) Look Up Table"
|
|
group.long 0x1324++0x03
|
|
line.long 0x00 "SD_LUT_5,SD_LUT_5"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_LUT ,Blue Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G_LUT ,Green Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R_LUT ,Red Enhancement value (k) Look Up Table"
|
|
group.long 0x1328++0x03
|
|
line.long 0x00 "SD_LUT_6,SD_LUT_6"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_LUT ,Blue Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G_LUT ,Green Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R_LUT ,Red Enhancement value (k) Look Up Table"
|
|
group.long 0x132C++0x03
|
|
line.long 0x00 "SD_LUT_7,SD_LUT_7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_LUT ,Blue Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G_LUT ,Green Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R_LUT ,Red Enhancement value (k) Look Up Table"
|
|
group.long 0x1330++0x03
|
|
line.long 0x00 "SD_LUT_8,SD_LUT_8"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_LUT ,Blue Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 8.--15. 1. " G_LUT ,Green Enhancement value (k) Look Up Table"
|
|
hexmask.long.byte 0x00 0.--7. 1. " R_LUT ,Red Enhancement value (k) Look Up Table"
|
|
textline " "
|
|
group.long 0x1334++0x07
|
|
line.long 0x00 "SD_FLICKER_CONTROL_0,Flicker Reduction Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " THRESHOLD ,The amount by which the currently calculated enhancement value must deviate"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TIME_LIMIT ,Length of time - in frames - that the enhancement value must deviate"
|
|
line.long 0x04 "SD_PIXEL_COUNT_0,Status / debug register showing the total number of active pixels"
|
|
hexmask.long.word 0x04 0.--15. 1. " NUM_PIXELS ,Number of pixels in the preceding output frame"
|
|
textline " "
|
|
group.long 0x133C++0x03
|
|
line.long 0x00 "SD_HISTOGRAM_0,SD_HISTOGRAM_0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BIN_3 ,BIN_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BIN_2 ,BIN_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BIN_1 ,BIN_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BIN_0 ,BIN_0"
|
|
group.long 0x1340++0x03
|
|
line.long 0x00 "SD_HISTOGRAM_1,SD_HISTOGRAM_1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BIN_3 ,BIN_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BIN_2 ,BIN_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BIN_1 ,BIN_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BIN_0 ,BIN_0"
|
|
group.long 0x1344++0x03
|
|
line.long 0x00 "SD_HISTOGRAM_2,SD_HISTOGRAM_2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BIN_3 ,BIN_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BIN_2 ,BIN_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BIN_1 ,BIN_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BIN_0 ,BIN_0"
|
|
group.long 0x1348++0x03
|
|
line.long 0x00 "SD_HISTOGRAM_3,SD_HISTOGRAM_3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BIN_3 ,BIN_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BIN_2 ,BIN_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BIN_1 ,BIN_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BIN_0 ,BIN_0"
|
|
group.long 0x134C++0x03
|
|
line.long 0x00 "SD_HISTOGRAM_4,SD_HISTOGRAM_4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BIN_3 ,BIN_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BIN_2 ,BIN_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BIN_1 ,BIN_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BIN_0 ,BIN_0"
|
|
group.long 0x1350++0x03
|
|
line.long 0x00 "SD_HISTOGRAM_5,SD_HISTOGRAM_5"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BIN_3 ,BIN_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BIN_2 ,BIN_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BIN_1 ,BIN_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BIN_0 ,BIN_0"
|
|
group.long 0x1354++0x03
|
|
line.long 0x00 "SD_HISTOGRAM_6,SD_HISTOGRAM_6"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BIN_3 ,BIN_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BIN_2 ,BIN_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BIN_1 ,BIN_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BIN_0 ,BIN_0"
|
|
group.long 0x1358++0x03
|
|
line.long 0x00 "SD_HISTOGRAM_7,SD_HISTOGRAM_7"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BIN_3 ,BIN_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BIN_2 ,BIN_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BIN_1 ,BIN_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BIN_0 ,BIN_0"
|
|
textline " "
|
|
group.long 0x135C++0x03
|
|
line.long 0x00 "SD_BL_PARAMETERS_0,Backlight response parameters"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STEP ,Determines the instantaneous portion of the target value of enhancement that is applied"
|
|
hexmask.long.word 0x00 0.--10. 1. " TIME_CONSTANT ,The time constant for the response curve"
|
|
textline " "
|
|
group.long 0x1360++0x03
|
|
line.long 0x00 "SD_BL_TF_0,Backlight Transfer Function"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POINT_3 ,POINT_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " POINT_2 ,POINT_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " POINT_1 ,POINT_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " POINT_0 ,POINT_0"
|
|
group.long 0x1364++0x03
|
|
line.long 0x00 "SD_BL_TF_1,Backlight Transfer Function"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POINT_3 ,POINT_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " POINT_2 ,POINT_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " POINT_1 ,POINT_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " POINT_0 ,POINT_0"
|
|
group.long 0x1368++0x03
|
|
line.long 0x00 "SD_BL_TF_2,Backlight Transfer Function"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POINT_3 ,POINT_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " POINT_2 ,POINT_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " POINT_1 ,POINT_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " POINT_0 ,POINT_0"
|
|
group.long 0x136C++0x03
|
|
line.long 0x00 "SD_BL_TF_3,Backlight Transfer Function"
|
|
hexmask.long.byte 0x00 24.--31. 1. " POINT_3 ,POINT_3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " POINT_2 ,POINT_2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " POINT_1 ,POINT_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " POINT_0 ,POINT_0"
|
|
textline " "
|
|
group.long 0x1370++0x03
|
|
line.long 0x00 "SD_BL_CONTROL_0,SD_BL_CONTROL_0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BRIGHTNESS ,Backlight brightness modification value"
|
|
bitfld.long 0x00 0.--1. " BL_MODE ,Control Mode: and adjust the backlight brightness itself" "MANUAL,PWM_AUTO,?..."
|
|
rgroup.long 0x1374++0x03
|
|
line.long 0x00 "SD_HW_K_VALUES_0,Hardware-computed values of K for each color component"
|
|
hexmask.long.word 0x00 20.--29. 1. " HW_K_BLUE ,Value of K for blue pixels"
|
|
hexmask.long.word 0x00 10.--19. 1. " HW_K_GREEN ,Value of K for green pixels"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " HW_K_RED ,Value of K for red pixels"
|
|
group.long 0x1378++0x3B
|
|
line.long 0x00 "SD_MAN_K_VALUES_0,Manual values of K for each color component"
|
|
hexmask.long.word 0x00 20.--29. 1. " MAN_K_BLUE ,Value of K for blue pixels"
|
|
hexmask.long.word 0x00 10.--19. 1. " MAN_K_GREEN ,Value of K for green pixels"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " MAN_K_RED ,Value of K for red pixels"
|
|
line.long 0x04 "SD_K_LIMIT_0,SD_K_LIMIT_0"
|
|
hexmask.long.word 0x04 0.--9. 1. " K_LIMIT ,When K_LIMIT_ENABLE=ENABLE limits raw K independently of AGGRESSIVENESS"
|
|
line.long 0x08 "SD_WINDOW_POSITION_0,SD Window Position"
|
|
hexmask.long.word 0x08 16.--28. 1. " SD_WIN_V_POSITION ,SD window vertical position (pixels)"
|
|
hexmask.long.word 0x08 0.--12. 1. " SD_WIN_H_POSITION ,SD window horizontal position (pixels)"
|
|
line.long 0x0C "SD_WINDOW_SIZE_0,SD Window Size"
|
|
hexmask.long.word 0x0C 16.--28. 1. " SD_WIN_V_SIZE ,SD window vertical height (pixels)"
|
|
hexmask.long.word 0x0C 0.--12. 1. " SD_WIN_H_SIZE ,SD window horizontal width (pixels)"
|
|
line.long 0x10 "SD_SOFT_CLIPPING_0,SD soft clipping parameters"
|
|
hexmask.long.word 0x10 16.--31. 1. " SOFT_CLIPPING_RECIP ,Reciprocal of inverse threshold"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SOFT_CLIPPING_THRESHOLD ,Threshold at which pixel enhancement gain is reduced"
|
|
line.long 0x14 "SD_SMOOTH_K_0,SD_SMOOTH_K_0"
|
|
hexmask.long.word 0x14 0.--13. 1. " SMOOTH_K_INCR ,When SMOOTH_K_ENABLE=1 the raw K is changed at most by SMOOTH_K_INCR per frame"
|
|
line.long 0x18 "BLEND_BACKGROUND_COLOR_0,BLEND_BACKGROUND_COLOR_0"
|
|
hexmask.long.byte 0x18 24.--31. 1. " BKGND_ALPHA ,Background color of alpha canal"
|
|
hexmask.long.byte 0x18 16.--23. 1. " BKGND_BLUE ,Background color of blue canal"
|
|
textline " "
|
|
hexmask.long.byte 0x18 8.--15. 1. " BKGND_GREEN ,Background color of green canal"
|
|
hexmask.long.byte 0x18 0.--7. 1. " BKGND_RED ,Background color of red canal"
|
|
line.long 0x1C "INTERLACE_CONTROL_0,Control interlacing"
|
|
rbitfld.long 0x1C 2. " INTERLACE_STATUS ,Status" "FIELD1,FIELD2"
|
|
bitfld.long 0x1C 1. " INTERLACE_START ,Start" "FIELD1,FIELD2"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " INTERLACE_ENABLE ,Enable" "Disabled,Enabled"
|
|
line.long 0x20 "INTERLACE_FIELD2_REF_TO_SYNC_0,Control the ref to sync offset for H sync and V sync for FIELD2"
|
|
hexmask.long.word 0x20 16.--28. 1. " FIELD2_V_REF_TO_SYNC ,V reference to VSYNC for FIELD2"
|
|
hexmask.long.word 0x20 0.--12. 1. " FIELD2_H_REF_TO_SYNC ,H reference to HSYNC for FIELD2"
|
|
line.long 0x24 "INTERLACE_FIELD2_SYNC_WIDTH_0,Control the H and V sync widths for FIELD2"
|
|
hexmask.long.word 0x24 16.--28. 1. " FIELD2_V_SYNC_WIDTH ,This field controls the V sync widths for FIELD2"
|
|
hexmask.long.word 0x24 0.--12. 1. " FIELD2_H_SYNC_WIDTH ,This field controls the H sync widths for FIELD2"
|
|
line.long 0x28 "INTERLACE_FIELD2_BACK_PORCH_0,Control the H and V back porch widths for FIELD2"
|
|
hexmask.long.word 0x28 16.--28. 1. " FIELD2_V_BACK_PORCH ,V back porch"
|
|
hexmask.long.word 0x28 0.--12. 1. " FIELD2_H_BACK_PORCH ,H back porch"
|
|
line.long 0x2C "INTERLACE_FIELD2_FRONT_PORCH_0,Control the H and V front porch widths for FIELD2"
|
|
hexmask.long.word 0x2C 16.--28. 1. " FIELD2_V_FRONT_PORCH ,V front porch"
|
|
hexmask.long.word 0x2C 0.--12. 1. " FIELD2_H_FRONT_PORCH ,H front porch"
|
|
line.long 0x30 "INTERLACE_FIELD2_DISP_ACTIVE_0,Control the H and V active widths for FIELD2"
|
|
hexmask.long.word 0x30 16.--28. 1. " FIELD2_V_DISP_ACTIVE ,V active width"
|
|
hexmask.long.word 0x30 0.--12. 1. " FIELD2_H_DISP_ACTIVE ,H active width"
|
|
line.long 0x34 "CURSOR_UNDERFLOW_CTRL_0,CURSOR_UNDERFLOW_CTRL_0"
|
|
bitfld.long 0x34 7. " CURSOR_UFLOW_CYA ,CURSOR_UFLOW_CYA" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " CURSOR_UFLOW_CTRL_DBG_MODE ,CURSOR_UFLOW_CTRL_DBG_MODE" "Disabled,Enabled"
|
|
line.long 0x38 "CURSOR_START_ADDR_HI_0,Cursor Start Address"
|
|
bitfld.long 0x38 0.--1. " CURSOR_START_ADDR_HI ,Cursor Start Address bits 33:32" "0,1,2,3"
|
|
group.long 0x13B8++0x07
|
|
line.long 0x00 "CURSOR_INTERLACE_CONTROL_0,Control interlacing"
|
|
bitfld.long 0x00 4. " CURSOR_INTERLACE_FIELD2_VOFF_INCR ,FIELD2 v position incr Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CURSOR_INTERLACE_FIELD1_VOFF_INCR ,FIELD1 v position incr Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " CURSOR_INTERLACE_STATUS ,Current line start" "LINE0,LINE1"
|
|
bitfld.long 0x00 1. " CURSOR_INTERLACE_START ,Starting line" "LINE0,LINE1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CURSOR_INTERLACE_ENABLE ,Interlace enable" "Disabled,Enabled"
|
|
line.long 0x04 "CSC2_CONTROL_0,The CSC2 can be used for RGB to YCbCr conversion used in 1080i HDMI output"
|
|
bitfld.long 0x04 2. " LIMIT_RGB_COLOR ,Scale RGB [0,255] to [16,235]" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--1. " OUTPUT_COLOR_SELECT ,Output color select" "RGB,YCBCR709,YCBCR601,?..."
|
|
group.long 0x13C4++0x13
|
|
line.long 0x00 "BLEND_CURSOR_CONTROL_0,BLEND_CURSOR_CONTROL_0"
|
|
bitfld.long 0x00 24. " CURSOR_MODE_SELECT ,CURSOR_MODE_SELECT" "LEGACY,NORMAL"
|
|
bitfld.long 0x00 16.--17. " CURSOR_DST_BLEND_FACTOR_SELECT ,Controls the DST_FACTOR" "ZERO,K1,NEG_K1_TIMES_SRC,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CURSOR_SRC_BLEND_FACTOR_SELECT ,Controls the SRC_FACTOR" "K1,K1_TIMES_SRC,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " CURSOR_ALPHA ,CURSOR_ALPHA"
|
|
line.long 0x04 "DVFS_CURSOR_CONTROL_0,DVFS_CURSOR_CONTROL_0"
|
|
bitfld.long 0x04 8. " CURSOR_DVFS_ENABLE ,Enable ready_for_latency_event to toggle based on CURSOR_DVFS_THRESHOLD (When disabled ready_for_latency_event is true)" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CURSOR_DVFS_THRESHOLD ,CURSOR_DVFS_THRESHOLD"
|
|
line.long 0x08 "CURSOR_UFLOW_DBG_PIXEL_0,CURSOR_UFLOW_DBG_PIXEL_0"
|
|
line.long 0x0C "CURSOR_SPOOLUP_CONTROL_0,Programmable spool up for cursor If spoolup count > hc_vactive_start it will be clamped to zero"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CURSOR_SPOOLUP_START ,CURSOR_SPOOLUP_START"
|
|
line.long 0x10 "DISPLAY_CLK_GATE_OVERRIDE_0,DISPLAY_CLK_GATE_OVERRIDE_0"
|
|
bitfld.long 0x10 1. " CMU_CLK_GATE_OVERRIDE ,Disable clock-gating of the CMU module" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " CURSOR_CLK_GATE_OVERRIDE ,Disable clock-gating of cursor memfetch/control modules" "Disabled,Enabled"
|
|
rgroup.long 0x13D8++0x03
|
|
line.long 0x00 "DISPLAY_DBG_TIMING_0,DISPLAY_DBG_TIMING_0"
|
|
bitfld.long 0x00 31. " H_BLANK ,H_BLANK" "0,1"
|
|
hexmask.long.word 0x00 16.--28. 1. " H_COUNT ,H_COUNT"
|
|
textline " "
|
|
bitfld.long 0x00 15. " V_BLANK ,V_BLANK" "0,1"
|
|
hexmask.long.word 0x00 0.--12. 1. " V_COUNT ,V_COUNT"
|
|
group.long 0x13DC++0x07
|
|
line.long 0x00 "DISPLAY_SPARE0_0,DISPLAY_SPARE0_0"
|
|
hexmask.long.word 0x00 4.--13. 1. " DSC_RC_OVERFLOW_THRESH ,Program the threshold of bufferFullness + throttle_offset (currently it is -172)"
|
|
bitfld.long 0x00 2.--3. " DSC_RC_SOLUTION_MODE ,DSC_RC_SOLUTION_MODE" "Disabled,Solution#1,Solution#2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " DSC_CHECK_FLATNESS2 ,DSC_CHECK_FLATNESS2" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DSC_FLATNESS_FIX_EN ,Diagnostic bit for flatness updates only" "Disabled,Enabled"
|
|
line.long 0x04 "DISPLAY_SPARE1_0,DISPLAY_SPARE1_0"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
width 21.
|
|
tree "Window A Registers"
|
|
wgroup.long 0x1400++0x03
|
|
line.long 0x00 "COLOR_PALETTE_0,Window A Color Palette"
|
|
button "BGR" "d (ad:0x542400000+0x1400)--(ad:0x542400000+0x17fc) /long"
|
|
group.long 0x1800++0x03
|
|
line.long 0x00 "PALETTE_COLOR_EXT_0,Window A Palette Color Extension"
|
|
hexmask.long.byte 0x00 1.--7. 1. " A_PALETTE_COLOR_EXT ,Window A Palette Color Extension"
|
|
group.long 0x1804++0x03
|
|
line.long 0x00 "H_FILTER_P00_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P00C5 ,Phase 00 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " A_H_FILTER_P00C4 ,Phase 00 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P00C3 ,Phase 00 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 00 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " A_H_FILTER_P00C1 ,Phase 00 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " A_H_FILTER_P00C0 ,Phase 00 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1808++0x03
|
|
line.long 0x00 "H_FILTER_P01_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P01C5 ,Phase 01 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " A_H_FILTER_P01C4 ,Phase 01 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P01C3 ,Phase 01 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 01 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " A_H_FILTER_P01C1 ,Phase 01 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " A_H_FILTER_P01C0 ,Phase 01 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x180C++0x03
|
|
line.long 0x00 "H_FILTER_P02_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P02C5 ,Phase 02 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " A_H_FILTER_P02C4 ,Phase 02 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P02C3 ,Phase 02 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 02 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " A_H_FILTER_P02C1 ,Phase 02 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " A_H_FILTER_P02C0 ,Phase 02 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1810++0x03
|
|
line.long 0x00 "H_FILTER_P03_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P03C5 ,Phase 03 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " A_H_FILTER_P03C4 ,Phase 03 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P03C3 ,Phase 03 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 03 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " A_H_FILTER_P03C1 ,Phase 03 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " A_H_FILTER_P03C0 ,Phase 03 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1814++0x03
|
|
line.long 0x00 "H_FILTER_P04_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P04C5 ,Phase 04 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " A_H_FILTER_P04C4 ,Phase 04 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P04C3 ,Phase 04 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 04 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " A_H_FILTER_P04C1 ,Phase 04 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " A_H_FILTER_P04C0 ,Phase 04 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1818++0x03
|
|
line.long 0x00 "H_FILTER_P05_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P05C5 ,Phase 05 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " A_H_FILTER_P05C4 ,Phase 05 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P05C3 ,Phase 05 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 05 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " A_H_FILTER_P05C1 ,Phase 05 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " A_H_FILTER_P05C0 ,Phase 05 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x181C++0x03
|
|
line.long 0x00 "H_FILTER_P06_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P06C5 ,Phase 06 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " A_H_FILTER_P06C4 ,Phase 06 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P06C3 ,Phase 06 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 06 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " A_H_FILTER_P06C1 ,Phase 06 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " A_H_FILTER_P06C0 ,Phase 06 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1820++0x03
|
|
line.long 0x00 "H_FILTER_P07_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P07C5 ,Phase 07 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " A_H_FILTER_P07C4 ,Phase 07 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P07C3 ,Phase 07 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 07 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " A_H_FILTER_P07C1 ,Phase 07 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " A_H_FILTER_P07C0 ,Phase 07 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1824++0x03
|
|
line.long 0x00 "H_FILTER_P08_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P08C5 ,Phase 08 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " A_H_FILTER_P08C4 ,Phase 08 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P08C3 ,Phase 08 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 08 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " A_H_FILTER_P08C1 ,Phase 08 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " A_H_FILTER_P08C0 ,Phase 08 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1828++0x03
|
|
line.long 0x00 "H_FILTER_P09_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P09C5 ,Phase 09 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " A_H_FILTER_P09C4 ,Phase 09 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P09C3 ,Phase 09 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 09 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " A_H_FILTER_P09C1 ,Phase 09 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " A_H_FILTER_P09C0 ,Phase 09 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x182C++0x03
|
|
line.long 0x00 "H_FILTER_P0A_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P0AC5 ,Phase 0A coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " A_H_FILTER_P0AC4 ,Phase 0A coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P0AC3 ,Phase 0A coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 0A coefficient 2"
|
|
bitfld.long 0x00 3.--7. " A_H_FILTER_P0AC1 ,Phase 0A coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " A_H_FILTER_P0AC0 ,Phase 0A coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1830++0x03
|
|
line.long 0x00 "H_FILTER_P0B_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P0BC5 ,Phase 0B coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " A_H_FILTER_P0BC4 ,Phase 0B coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P0BC3 ,Phase 0B coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 0B coefficient 2"
|
|
bitfld.long 0x00 3.--7. " A_H_FILTER_P0BC1 ,Phase 0B coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " A_H_FILTER_P0BC0 ,Phase 0B coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1834++0x03
|
|
line.long 0x00 "H_FILTER_P0C_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P0CC5 ,Phase 0C coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " A_H_FILTER_P0CC4 ,Phase 0C coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P0CC3 ,Phase 0C coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 0C coefficient 2"
|
|
bitfld.long 0x00 3.--7. " A_H_FILTER_P0CC1 ,Phase 0C coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " A_H_FILTER_P0CC0 ,Phase 0C coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1838++0x03
|
|
line.long 0x00 "H_FILTER_P0D_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P0DC5 ,Phase 0D coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " A_H_FILTER_P0DC4 ,Phase 0D coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P0DC3 ,Phase 0D coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 0D coefficient 2"
|
|
bitfld.long 0x00 3.--7. " A_H_FILTER_P0DC1 ,Phase 0D coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " A_H_FILTER_P0DC0 ,Phase 0D coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x183C++0x03
|
|
line.long 0x00 "H_FILTER_P0E_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P0EC5 ,Phase 0E coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " A_H_FILTER_P0EC4 ,Phase 0E coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P0EC3 ,Phase 0E coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 0E coefficient 2"
|
|
bitfld.long 0x00 3.--7. " A_H_FILTER_P0EC1 ,Phase 0E coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " A_H_FILTER_P0EC0 ,Phase 0E coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1840++0x03
|
|
line.long 0x00 "H_FILTER_P0F_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " A_H_FILTER_P0FC5 ,Phase 0F coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " A_H_FILTER_P0FC4 ,Phase 0F coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_H_FILTER_P0FC3 ,Phase 0F coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_H_FILTER_P00C2 ,Phase 0F coefficient 2"
|
|
bitfld.long 0x00 3.--7. " A_H_FILTER_P0FC1 ,Phase 0F coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " A_H_FILTER_P0FC0 ,Phase 0F coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1844++0x1F
|
|
line.long 0x00 "CSC_YOF_0,Colour Space Conversion Coefficients"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_CSC_YOF ,Y Offset in s.7.0 format"
|
|
line.long 0x04 "CSC_KYRGB_0,Window A CSC Y Coefficient for RGB"
|
|
hexmask.long.word 0x04 0.--9. 1. " A_CSC_KYRGB ,Y Gain for R, G, B colours in 2.8 format"
|
|
line.long 0x08 "CSC_KUR_0,Window A CSC U coefficient for R"
|
|
hexmask.long.word 0x08 0.--10. 1. " A_CSC_KUR ,U coefficients for R in s.2.8 format"
|
|
line.long 0x0C "CSC_KVR_0,Window A CSC V coefficient for R"
|
|
hexmask.long.word 0x0C 0.--10. 1. " A_CSC_KVR ,V coefficients for R in s.2.8 format"
|
|
line.long 0x10 "CSC_KUG_0,Window A CSC U coefficient for G"
|
|
hexmask.long.word 0x10 0.--9. 1. " A_CSC_KUG ,U coefficients for G in s.1.8 format"
|
|
line.long 0x14 "CSC_KVG_0,Window A CSC V coefficient for G"
|
|
hexmask.long.word 0x14 0.--9. 1. " A_CSC_KVG ,V coefficients for G in s.1.8 format"
|
|
line.long 0x18 "CSC_KUB_0,Window A CSC U coefficient for B"
|
|
hexmask.long.word 0x18 0.--10. 1. " A_CSC_KUB ,U coefficients for B in s.2.8 format"
|
|
line.long 0x1C "CSC_KVB_0,Window A CSC V coefficient for B"
|
|
hexmask.long.word 0x1C 0.--10. 1. " A_CSC_KVB ,V coefficients for B in s.2.8 format"
|
|
textline " "
|
|
group.long 0x1864++0x03
|
|
line.long 0x00 "V_FILTER_P00_0,Window A Vertical Filter phase 00"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P00C0 ,Phase 00 coefficient 0"
|
|
group.long 0x1868++0x03
|
|
line.long 0x00 "V_FILTER_P01_0,Window A Vertical Filter phase 01"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P01C0 ,Phase 01 coefficient 1"
|
|
group.long 0x186C++0x03
|
|
line.long 0x00 "V_FILTER_P02_0,Window A Vertical Filter phase 02"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P02C0 ,Phase 02 coefficient 2"
|
|
group.long 0x1870++0x03
|
|
line.long 0x00 "V_FILTER_P03_0,Window A Vertical Filter phase 03"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P03C0 ,Phase 03 coefficient 3"
|
|
group.long 0x1874++0x03
|
|
line.long 0x00 "V_FILTER_P04_0,Window A Vertical Filter phase 04"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P04C0 ,Phase 04 coefficient 4"
|
|
group.long 0x1878++0x03
|
|
line.long 0x00 "V_FILTER_P05_0,Window A Vertical Filter phase 05"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P05C0 ,Phase 05 coefficient 5"
|
|
group.long 0x187C++0x03
|
|
line.long 0x00 "V_FILTER_P06_0,Window A Vertical Filter phase 06"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P06C0 ,Phase 06 coefficient 6"
|
|
group.long 0x1880++0x03
|
|
line.long 0x00 "V_FILTER_P07_0,Window A Vertical Filter phase 07"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P07C0 ,Phase 07 coefficient 7"
|
|
group.long 0x1884++0x03
|
|
line.long 0x00 "V_FILTER_P08_0,Window A Vertical Filter phase 08"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P08C0 ,Phase 08 coefficient 8"
|
|
group.long 0x1888++0x03
|
|
line.long 0x00 "V_FILTER_P09_0,Window A Vertical Filter phase 09"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P09C0 ,Phase 09 coefficient 9"
|
|
group.long 0x188C++0x03
|
|
line.long 0x00 "V_FILTER_P0A_0,Window A Vertical Filter phase 0A"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P0AC0 ,Phase 0A coefficient A"
|
|
group.long 0x1890++0x03
|
|
line.long 0x00 "V_FILTER_P0B_0,Window A Vertical Filter phase 0B"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P0BC0 ,Phase 0B coefficient B"
|
|
group.long 0x1894++0x03
|
|
line.long 0x00 "V_FILTER_P0C_0,Window A Vertical Filter phase 0C"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P0CC0 ,Phase 0C coefficient C"
|
|
group.long 0x1898++0x03
|
|
line.long 0x00 "V_FILTER_P0D_0,Window A Vertical Filter phase 0D"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P0DC0 ,Phase 0D coefficient D"
|
|
group.long 0x189C++0x03
|
|
line.long 0x00 "V_FILTER_P0E_0,Window A Vertical Filter phase 0E"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P0EC0 ,Phase 0E coefficient E"
|
|
group.long 0x18A0++0x03
|
|
line.long 0x00 "V_FILTER_P0F_0,Window A Vertical Filter phase 0F"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_V_FILTER_P0FC0 ,Phase 0F coefficient F"
|
|
textline " "
|
|
group.long 0x18A4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P00_0,Window A Horizontal Filter phase 00"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P00C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P00C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P00C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P00C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P00C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P00C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18A8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P01_0,Window A Horizontal Filter phase 01"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P01C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P01C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P01C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P01C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P01C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P01C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18AC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P02_0,Window A Horizontal Filter phase 02"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P02C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P02C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P02C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P02C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P02C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P02C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18B0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P03_0,Window A Horizontal Filter phase 03"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P03C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P03C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P03C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P03C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P03C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P03C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18B4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P04_0,Window A Horizontal Filter phase 04"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P04C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P04C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P04C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P04C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P04C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P04C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18B8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P05_0,Window A Horizontal Filter phase 05"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P05C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P05C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P05C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P05C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P05C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P05C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18BC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P06_0,Window A Horizontal Filter phase 06"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P06C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P06C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P06C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P06C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P06C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P06C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18C0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P07_0,Window A Horizontal Filter phase 07"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P07C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P07C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P07C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P07C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P07C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P07C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18C4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P08_0,Window A Horizontal Filter phase 08"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P08C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P08C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P08C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P08C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P08C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P08C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18C8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P09_0,Window A Horizontal Filter phase 09"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P09C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P09C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P09C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P09C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P09C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P09C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18CC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0A_0,Window A Horizontal Filter phase 0A"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P0AC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P0AC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P0AC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P0AC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P0AC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P0AC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18D0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0B_0,Window A Horizontal Filter phase 0B"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P0BC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P0BC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P0BC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P0BC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P0BC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P0BC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18D4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0C_0,Window A Horizontal Filter phase 0C"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P0CC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P0CC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P0CC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P0CC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P0CC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P0CC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18D8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0D_0,Window A Horizontal Filter phase 0D"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P0DC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P0DC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P0DC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P0DC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P0DC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P0DC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18DC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0E_0,Window A Horizontal Filter phase 0E"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P0EC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P0EC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P0EC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P0EC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P0EC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P0EC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18E0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0F_0,Window A Horizontal Filter phase 0F"
|
|
bitfld.long 0x00 8.--9. " A_H_FILTER_HI_P0FC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " A_H_FILTER_HI_P0FC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " A_H_FILTER_HI_P0FC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_H_FILTER_HI_P0FC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " A_H_FILTER_HI_P0FC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " A_H_FILTER_HI_P0FC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
textline " "
|
|
width 17.
|
|
if (((d.l(ad:0x542400000+0x1C00))&0x400)==0x400)
|
|
group.long 0x1C00++0x03
|
|
line.long 0x00 "WIN_OPTIONS_0,Window A Options"
|
|
bitfld.long 0x00 31. " A_H_FILTER_MODE ,Horizontal filter mode" "Old,New"
|
|
bitfld.long 0x00 30. " A_WIN_ENABLE ,Window A Window enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " A_INTERLACE_ENABLE ,Window A Interlace enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " A_YUV_RANGE_EXPAND ,Window A Enable range expansion" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " A_DV_ENABLE ,Window A Digital Vibrance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " A_CSC_ENABLE ,Window A Color Space Conversion Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " A_CP_ENABLE ,Window A Color Palette Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " A_V_FILTER_UV_ALIGN ,Window A V Filter UV Alignment" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " A_V_FILTER_OPTIMIZE ,Window A V Filter Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " A_V_FILTER_ENABLE ,Window A V Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " A_H_FILTER_ENABLE ,Window A H Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " A_COLOR_EXPAND ,Color expansion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " A_SCAN_COLUMN ,Window A Scanning direction" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " A_V_DIRECTION ,Window A Vertical (Y) drawing Direction" "Increment,Decrement"
|
|
bitfld.long 0x00 0. " A_H_DIRECTION ,Window A Horizontal (X) drawing Direction" "Increment,Decrement"
|
|
else
|
|
group.long 0x1C00++0x03
|
|
line.long 0x00 "WIN_OPTIONS_0,Window A Options"
|
|
bitfld.long 0x00 31. " A_H_FILTER_MODE ,Horizontal filter mode" "Old,New"
|
|
bitfld.long 0x00 30. " A_WIN_ENABLE ,Window A Window enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " A_INTERLACE_ENABLE ,Window A Interlace enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " A_YUV_RANGE_EXPAND ,Window A Enable range expansion" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " A_DV_ENABLE ,Window A Digital Vibrance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " A_CSC_ENABLE ,Window A Color Space Conversion Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " A_CP_ENABLE ,Window A Color Palette Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " A_V_FILTER_ENABLE ,Window A V Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " A_H_FILTER_ENABLE ,Window A H Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " A_COLOR_EXPAND ,Color expansion" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " A_SCAN_COLUMN ,Window A Scanning direction" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " A_V_DIRECTION ,Window A Vertical (Y) drawing Direction" "Increment,Decrement"
|
|
textline " "
|
|
bitfld.long 0x00 0. " A_H_DIRECTION ,Window A Horizontal (X) drawing Direction" "Increment,Decrement"
|
|
endif
|
|
group.long 0x1C04++0x03
|
|
line.long 0x00 "BYTE_SWAP_0,Window A Byte Swap"
|
|
bitfld.long 0x00 0.--2. " A_BYTE_SWAP ,Window A Byte Swap" "NOSWAP,SWAP2,SWAP4,SWAP4HW,SWAP02,SWAPLEFT,,"
|
|
group.long 0x1C0C++0x03
|
|
line.long 0x00 "COLOR_DEPTH_0,Window A Color depth"
|
|
hexmask.long.byte 0x00 0.--6. 1. " A_COLOR_DEPTH ,Window A Color Depth"
|
|
width 18.
|
|
textline " "
|
|
group.long 0x1C10++0x03
|
|
line.long 0x00 "POSITION_0,Window A Position"
|
|
hexmask.long.word 0x00 16.--28. 1. " A_V_POSITION ,Window A V Position"
|
|
hexmask.long.word 0x00 0.--12. 1. " A_H_POSITION ,Window A H Position"
|
|
group.long 0x1C14++0x03
|
|
line.long 0x00 "SIZE_0,Window A Size"
|
|
hexmask.long.word 0x00 16.--28. 1. " A_V_SIZE ,Vertical size after scaling"
|
|
hexmask.long.word 0x00 0.--12. 1. " A_H_SIZE ,Horizontal size after scaling"
|
|
group.long 0x1C18++0x03
|
|
line.long 0x00 "PRESCALED_SIZE_0,Window A Pre-scaled Size"
|
|
hexmask.long.word 0x00 16.--28. 1. " A_V_PRESCALED_SIZE ,Window A V Pre-scaled Size"
|
|
hexmask.long.word 0x00 0.--14. 1. " A_H_PRESCALED_SIZE ,Window A H Pre-scaled Size"
|
|
group.long 0x1C1C++0x03
|
|
line.long 0x00 "H_INITIAL_DDA_0,Window A H Initial DDA"
|
|
hexmask.long.word 0x00 0.--15. 1. " A_H_INITIAL_DDA ,Window A H Initial DDA"
|
|
group.long 0x1C20++0x03
|
|
line.long 0x00 "V_INITIAL_DDA_0,Window A V Initial DDA"
|
|
hexmask.long.word 0x00 0.--15. 1. " A_V_INITIAL_DDA ,Window A V Initial DDA"
|
|
group.long 0x1C24++0x03
|
|
line.long 0x00 "DDA_INCREMENT_0,Window A DDA Increment"
|
|
hexmask.long.word 0x00 16.--31. 1. " A_V_DDA_INCREMENT ,Window A Vertical DDA Increment"
|
|
hexmask.long.word 0x00 0.--15. 1. " A_H_DDA_INCREMENT ,Window A Horizontal DDA Increment"
|
|
group.long 0x1C28++0x03
|
|
line.long 0x00 "LINE_STRIDE_0,Window A Line Stride"
|
|
hexmask.long.word 0x00 16.--31. 1. " A_UV_LINE_STRIDE ,Window A Line Stride for Chroma"
|
|
hexmask.long.word 0x00 0.--15. 1. " A_LINE_STRIDE ,Window A Line Stride"
|
|
group.long 0x1C38++0x03
|
|
line.long 0x00 "DV_CONTROL_0,Window A Digital Vibrance Control"
|
|
bitfld.long 0x00 16.--18. " A_DV_CONTROL_B ,Digital Vibrance control for B" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " A_DV_CONTROL_G ,Digital Vibrance control for G" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " A_DV_CONTROL_R ,Digital Vibrance control for R" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
width 24.
|
|
group.long 0x1C58++0x0F
|
|
line.long 0x00 "BLEND_LAYER_CONTROL_0,Window A"
|
|
bitfld.long 0x00 25.--27. " A_COLOR_KEY_SELECT ,A COLOR KEY SELECT" "0,1,2,3,4,5,6,7"
|
|
eventfld.long 0x00 24. " A_BLEND_BYPASS ,A BLEND BYPASS" "BLEND_ENABLE,BLEND_BYPASS"
|
|
hexmask.long.byte 0x00 16.--23. 1. " A_K2 ,A K2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " A_K1 ,A K1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A_WINDOW_LAYER_DEPTH ,A WINDOW LAYER DEPTH"
|
|
line.long 0x04 "BLEND_MATCH_SELECT_0,DC WIN A BLEND MATCH SELECT 0"
|
|
bitfld.long 0x04 12.--13. " A_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT ,A BLEND FACTOR DST ALPHA MATCH SELECT" "0,1,EG_K1_TIMES_SRC,K2"
|
|
bitfld.long 0x04 8.--9. " A_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT ,A BLEND FACTOR SRC ALPHA MATCH SELECT" "0,K1,K2,"
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " A_BLEND_FACTOR_DST_COLOR_MATCH_SELECT ,A BLEND FACTOR DST COLOR MATCH SELECT" "0,1,K1,K2,K1_TIMES_DST,NEG_K1_TIMES_DST,NEG_K1_TIMES_SRC,NEG_K1"
|
|
bitfld.long 0x04 0.--2. " A_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT ,A BLEND FACTOR SRC COLOR MATCH SELECT" "0,1,K1,K1_TIMES_DST,NEG_K1_TIMES_DST,K1_TIMES_SRC,,"
|
|
line.long 0x08 "BLEND_NOMATCH_SELECT_0,DC WIN A BLEND NOMATCH SELECT 0"
|
|
bitfld.long 0x08 12.--13. " A_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT ,A BLEND FACTOR DST ALPHA NOMATCH SELECT" "0,1,EG_K1_TIMES_SRC,K2"
|
|
bitfld.long 0x08 8.--9. " A_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT ,A BLEND FACTOR SRC ALPHA NOMATCH SELECT" "0,K1,K2,"
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " A_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT ,A BLEND FACTOR DST COLOR NOMATCH SELECT" "0,1,K1,K2,K1_TIMES_DST,NEG_K1_TIMES_DST,NEG_K1_TIMES_SRC,NEG_K1"
|
|
bitfld.long 0x08 0.--2. " A_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT ,A BLEND FACTOR SRC COLOR NOMATCH SELECT" "0,1,K1,K1_TIMES_DST,NEG_K1_TIMES_DST,K1_TIMES_SRC,,"
|
|
line.long 0x0C "BLEND_ALPHA_1BIT_0,DC WIN A BLEND ALPHA 1BIT 0"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " A_BLEND_WEIGHT1 ,Alpha value of 1"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " A_BLEND_WEIGHT0 ,Alpha value of 0"
|
|
tree.end
|
|
width 18.
|
|
tree "WINBUF_A Registers"
|
|
group.long 0x2000++0x27
|
|
line.long 0x00 "START_ADDR_0,Window A Start Address"
|
|
line.long 0x04 "START_ADDR_NS_0,Window A Shadowed Start Address"
|
|
line.long 0x08 "START_ADDR_U_0,Window A Start Address for U plane"
|
|
line.long 0x0C "START_ADDR_U_NS_0,Window A Shadowed Start Address for U plane"
|
|
line.long 0x10 "START_ADDR_V_0,Window A Start Address for V plane"
|
|
line.long 0x14 "START_ADDR_V_NS_0,WWindow A Shadowed Start Address for V plane"
|
|
line.long 0x18 "ADDR_H_OFFSET_0,Window A Horizontal Address Offset"
|
|
line.long 0x1C "ADDR_H_OFFSET_NS_0,Window A Shadowed Horizontal Address Offset"
|
|
line.long 0x20 "ADDR_V_OFFSET_0,Window A Vertical Address Offset"
|
|
line.long 0x24 "ADDR_V_OFFSET_NS_0,Window A Shadowed Vertical Address Offset"
|
|
group.long 0x2028++0x0B
|
|
line.long 0x00 "UFLOW_STATUS,Window A FIFO Underflow Status Register"
|
|
bitfld.long 0x00 30. " COUNT_OFLOW ,Counter has overflowed" "Not occurred,Occurred"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " UFLOW_COUNT ,Underflow count"
|
|
line.long 0x04 "SURFACE_KIND_0,Window A Surface Kind"
|
|
bitfld.long 0x04 4.--6. " A_BLOCK_HEIGHT ,Block Height" "HEIGHT_1,HEIGHT_2,HEIGHT_4,HEIGHT_8,HEIGHT_16,HEIGHT_32,,"
|
|
bitfld.long 0x04 0.--1. " A_SURFACE_KIND ,Surface kind" "PITCH,TILED,BL_16B2,"
|
|
line.long 0x08 "SURFACE_WEIGHT_0,Window A Surface Weights"
|
|
bitfld.long 0x08 5.--6. " A_SURFACE_WEIGHT_V ,Window A V Surface Weights" "2,4,8,16"
|
|
bitfld.long 0x08 3.--4. " A_SURFACE_WEIGHT_U ,Window A U or UV Surface Weights" "2,4,8,16"
|
|
bitfld.long 0x08 1.--2. " A_SURFACE_WEIGHT_Y ,Window A Y or packed Surface Weights" "2,4,8,16"
|
|
bitfld.long 0x08 0. " A_SURFACE_WEIGHT_OVERRIDE ,Weight Override" "Disabled,Enabled"
|
|
textline " "
|
|
width 22.
|
|
group.long 0x2034++0x17
|
|
line.long 0x00 "START_ADDR_HI_0,Window A Higher 2 bits of Start Address"
|
|
bitfld.long 0x00 0.--1. " A_START_ADDR_HI ,Window A Start Address" "0,1,2,3"
|
|
line.long 0x04 "START_ADDR_HI_NS_0,Window A Higher 2 bits of Start Address"
|
|
bitfld.long 0x04 0.--1. " A_START_ADDR_HI_NS ,Window A Shadowed Start Address" "0,1,2,3"
|
|
line.long 0x08 "START_ADDR_HI_U_0,Window A Higher 2 bits of Start Address"
|
|
bitfld.long 0x08 0.--1. " A_START_ADDR_HI ,Window A Start Address" "0,1,2,3"
|
|
line.long 0x0C "START_ADDR_HI_U_NS_0,Window A Shadowed Higher 2 bits of Start Address for U Plane"
|
|
bitfld.long 0x0C 0.--1. " A_START_ADDR_HI_U_NS ,Window A Shadowed Higher 2 bits of Start Address for U plane" "0,1,2,3"
|
|
line.long 0x10 "START_ADDR_HI_V_0,Window A Higher 2 bits of Start Address for V Plane"
|
|
bitfld.long 0x10 0.--1. " A_START_ADDR_HI_V ,Window A Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
line.long 0x14 "START_ADDR_HI_V_NS_0,Window A Shadowed Higher 2 bits of Start Address for V Plane"
|
|
bitfld.long 0x14 0.--1. " A_START_ADDR_HI_V_NS ,Window A Shadowed Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
textline " "
|
|
width 29.
|
|
group.long 0x204C++0x17
|
|
line.long 0x00 "START_ADDR_FIELD2_0,Window A Start Address"
|
|
line.long 0x04 "START_ADDR_FIELD2_NS_0,Window A Shadowed Start Address"
|
|
line.long 0x08 "START_ADDR_FIELD2_U_0,Window A Start Address for U plane"
|
|
line.long 0x0C "START_ADDR_FIELD2_U_NS_0,Window A Shadowed Start Address for U plane"
|
|
line.long 0x10 "START_ADDR_FIELD2_V_0,Window A Start Address for V plane"
|
|
line.long 0x14 "START_ADDR_FIELD2_V_NS_0,Window A Shadowed Start Address for V plane"
|
|
group.long 0x2064++0x17
|
|
line.long 0x00 "START_ADDR_FIELD2_HI_0,Window A Higher 2 bits of Start Address"
|
|
bitfld.long 0x00 0.--1. " A_START_ADDR_FIELD2_HI ,Window A Start Address" "0,1,2,3"
|
|
line.long 0x04 "START_ADDR_FIELD2_HI_NS_0,Window A Shadowed Higher 2 bits of Start Address"
|
|
bitfld.long 0x04 0.--1. " A_START_ADDR_FIELD2_HI_NS ,Window A Shadowed Start Address" "0,1,2,3"
|
|
line.long 0x08 "START_ADDR_FIELD2_HI_U_0,Window A Higher 2 bits of Start Address for U plane"
|
|
bitfld.long 0x08 0.--1. " A_START_ADDR_FIELD2_HI_U ,Window A Start Address for U plane" "0,1,2,3"
|
|
line.long 0x0C "START_ADDR_FIELD2_HI_U_NS_0,Window A Shadowed Higher 32 bits of Start Address for U plane"
|
|
bitfld.long 0x0C 0.--1. " A_START_ADDR_FIELD2_HI_U_NS ,Window A Shadowed Higher 2 bits of Start Address for U plane" "0,1,2,3"
|
|
line.long 0x10 "START_ADDR_FIELD2_HI_V_0,Window A Higher 2 bits of Start Address for V plane"
|
|
bitfld.long 0x10 0.--1. " A_START_ADDR_FIELD2_HI_V ,Window A Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
line.long 0x14 "START_ADDR_FIELD2_HI_V_NS_0,Window A Shadowed Higher 2 bits of Start Address for V plane"
|
|
bitfld.long 0x14 0.--1. " A_START_ADDR_FIELD2_HI_V_NS ,Window A Shadowed Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
group.long 0x207C++0x0F
|
|
line.long 0x00 "ADDR_H_OFFSET_FIELD2_0,Window A Horizontal address offset"
|
|
line.long 0x04 "ADDR_H_OFFSET_FIELD2_NS_0,Window A Shadowed Horizontal address offset"
|
|
line.long 0x08 "ADDR_V_OFFSET_FIELD2_0,Window A Vertical address offset"
|
|
line.long 0x0C "ADDR_V_OFFSET_FIELD2_NS_0,Window A Shadowed Vertical address offset"
|
|
group.long 0x2090++0x03
|
|
line.long 0x00 "UFLOW_CTRL_0,DC WINBUF A UFLOW CTRL 0"
|
|
bitfld.long 0x00 0. " A_UFLOW_CTRL_DBG_MODE ,A UFLOW CTRL DBG MODE" "Disabled,Enabled"
|
|
textline " "
|
|
width 25.
|
|
group.long 0x2094++0x27
|
|
line.long 0x00 "UFLOW_DBG_PIXEL_0,DC WINBUF A UFLOW DBG PIXEL 0"
|
|
line.long 0x04 "UFLOW_THRESHOLD_0,DC WINBUF A UFLOW THRESHOLD 0"
|
|
hexmask.long.word 0x04 0.--12. 1. " A_UFLOW_THRESHOLD ,A UFLOW THRESHOLD"
|
|
line.long 0x08 "SPOOL_UP_0,Spool up time configuration for different windows related logic"
|
|
hexmask.long.word 0x08 16.--28. 1. " A_SPOOL_UP_DURATION ,A SPOOL UP DURATION"
|
|
bitfld.long 0x08 1. " A_SPOOL_UP_EDGE ,A SPOOL UP EDGE" "NEGEDGE,POSEDGE"
|
|
bitfld.long 0x08 0. " A_SPOOL_UP_CTRL ,A SPOOL UP CTRL" "MAX,PROGRAMMABLE"
|
|
line.long 0x0C "SCALEFACTOR_THRESHOLD_0,DC WINBUF A SCALEFACTOR THRESHOLD 0"
|
|
hexmask.long.word 0x0C 16.--31. 1. " A_SF_LWM_THRESHOLD ,A SF LWM THRESHOLD"
|
|
hexmask.long.word 0x0C 0.--15. 1. " A_SF_HWM_THRESHOLD ,A SF HWM THRESHOLD"
|
|
line.long 0x10 "LATENCY_THRESHOLD_0,Register controls the behavior of the rdy4_latency_event from the display to the MC"
|
|
bitfld.long 0x10 31. " A_RDY4LATENCY_THRESHOLD_ENABLE ,A RDY4LATENCY THRESHOLD ENABLE" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " A_RDY4LATENCY_SPOOLUP_CTRL ,A RDY4LATENCY SPOOLUP CTRL" "DISALLOW,ALLOW"
|
|
textline " "
|
|
hexmask.long.word 0x10 16.--28. 1. " A_RDY4LATENCY_SPOOLUP_DURATION ,A RDY4LATENCY THRESHOLD"
|
|
hexmask.long.word 0x10 0.--15. 1. " A_RDY4LATENCY_THRESHOLD ,A RDY4LATENCY THRESHOLD"
|
|
line.long 0x14 "MEMFETCH_DEBUG_STATUS_0,Memfetch Debug Status"
|
|
bitfld.long 0x14 16. " A_DEBUG_ENABLE ,Reg to enable FGCG for flops added to debug signals in memfetch" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " B_ALIGN_FIFO_NON_IDLE ,Align FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 13. " B_PIPE0_FIFO_NON_IDLE ,Pipe0 FIFO idle at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 12. " B_FRAME_FIFO_NON_IDLE ,Frame FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 11. " B_SURFACE_FIFO_NON_IDLE ,Surface FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 10. " B_TAG_FIFO_NON_IDLE ,Tag FIFO idle at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 9. " B_RSP_FIFO_NON_IDLE ,Response FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 8. " B_REQ_FIFO_NON_IDLE ,Request FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 7. " B_DP_VALID_NON_IDLE ,DP lines valid at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 6. " B_V_SSM_NON_IDLE ,V SSM is non-idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 5. " B_U_SSM_NON_IDLE ,U SSM is non-idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 4. " B_Y_SSM_NON_IDLE ,Y SSM is non-idle at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 3. " B_DP_POOL_AVAIL ,DP thinks there is data in the pool at end of frame" "No data,Data"
|
|
bitfld.long 0x14 2. " B_POOL_NOT_EMPTY ,Status of pool at end of frame" "Empty,Not empty"
|
|
bitfld.long 0x14 1. " B_UNDERFLOW_LINE1 ,Underflow of line0" "No underflow,Line0 underflowed"
|
|
textline " "
|
|
bitfld.long 0x14 0. " B_UNDERFLOW_LINE0 ,Underflow of line0" "No underflow,Line0 underflowed"
|
|
line.long 0x18 "MEMFETCH_CONTROL_0,Memfetch Control Register"
|
|
bitfld.long 0x18 1. " A_MEMFETCH_CLK_GATE_OVERRIDE ,Disable clock-gating of memfetch for a controller" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " A_MEMFETCH_RESET ,Reset memfetch for a controller" "Disabled,Enabled"
|
|
line.long 0x1C "OCCUPANCY_THROTTLE_0,DC WINBUF A OCCUPANCY THROTTLE 0"
|
|
hexmask.long.word 0x1C 16.--31. 1. " A_OCCUPANCY_MAX_THRESHOLD ,A OCCUPANCY MAX THRESHOLD"
|
|
bitfld.long 0x1C 0. " A_OCCUPANCY_THROTTLE_MODE ,A OCCUPANCY THROTTLE MODE" "Disabled,Enabled"
|
|
line.long 0x20 "SCRATCH_REGISTER_0_0,DC WINBUF A SCRATCH REGISTER 0 0"
|
|
line.long 0x24 "SCRATCH_REGISTER_1_0,DC WINBUF A SCRATCH REGISTER 1 0"
|
|
tree.end
|
|
width 19.
|
|
tree "Window B Registers"
|
|
wgroup.long 0x1400++0x03
|
|
line.long 0x00 "COLOR_PALETTE_0,Window B Color Palette"
|
|
button "BGR" "d (ad:0x542400000+0x1400)--(ad:0x542400000+0x17fc) /long"
|
|
group.long 0x1800++0x03
|
|
line.long 0x00 "PALETTE_COLOR_EXT_0,Window B Palette Color Extension"
|
|
hexmask.long.byte 0x00 1.--7. 1. " B_PALETTE_COLOR_EXT ,Window B Palette Color Extension"
|
|
group.long 0x1804++0x03
|
|
line.long 0x00 "H_FILTER_P00_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P00C5 ,Phase 00 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P00C4 ,Phase 00 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P00C3 ,Phase 00 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 00 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P00C1 ,Phase 00 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P00C0 ,Phase 00 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1808++0x03
|
|
line.long 0x00 "H_FILTER_P01_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P01C5 ,Phase 01 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P01C4 ,Phase 01 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P01C3 ,Phase 01 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 01 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P01C1 ,Phase 01 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P01C0 ,Phase 01 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x180C++0x03
|
|
line.long 0x00 "H_FILTER_P02_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P02C5 ,Phase 02 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P02C4 ,Phase 02 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P02C3 ,Phase 02 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 02 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P02C1 ,Phase 02 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P02C0 ,Phase 02 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1810++0x03
|
|
line.long 0x00 "H_FILTER_P03_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P03C5 ,Phase 03 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P03C4 ,Phase 03 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P03C3 ,Phase 03 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 03 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P03C1 ,Phase 03 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P03C0 ,Phase 03 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1814++0x03
|
|
line.long 0x00 "H_FILTER_P04_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P04C5 ,Phase 04 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P04C4 ,Phase 04 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P04C3 ,Phase 04 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 04 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P04C1 ,Phase 04 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P04C0 ,Phase 04 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1818++0x03
|
|
line.long 0x00 "H_FILTER_P05_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P05C5 ,Phase 05 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P05C4 ,Phase 05 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P05C3 ,Phase 05 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 05 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P05C1 ,Phase 05 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P05C0 ,Phase 05 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x181C++0x03
|
|
line.long 0x00 "H_FILTER_P06_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P06C5 ,Phase 06 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P06C4 ,Phase 06 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P06C3 ,Phase 06 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 06 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P06C1 ,Phase 06 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P06C0 ,Phase 06 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1820++0x03
|
|
line.long 0x00 "H_FILTER_P07_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P07C5 ,Phase 07 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P07C4 ,Phase 07 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P07C3 ,Phase 07 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 07 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P07C1 ,Phase 07 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P07C0 ,Phase 07 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1824++0x03
|
|
line.long 0x00 "H_FILTER_P08_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P08C5 ,Phase 08 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P08C4 ,Phase 08 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P08C3 ,Phase 08 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 08 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P08C1 ,Phase 08 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P08C0 ,Phase 08 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1828++0x03
|
|
line.long 0x00 "H_FILTER_P09_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P09C5 ,Phase 09 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P09C4 ,Phase 09 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P09C3 ,Phase 09 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 09 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P09C1 ,Phase 09 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P09C0 ,Phase 09 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x182C++0x03
|
|
line.long 0x00 "H_FILTER_P0A_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P0AC5 ,Phase 0A coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P0AC4 ,Phase 0A coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P0AC3 ,Phase 0A coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 0A coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P0AC1 ,Phase 0A coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P0AC0 ,Phase 0A coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1830++0x03
|
|
line.long 0x00 "H_FILTER_P0B_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P0BC5 ,Phase 0B coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P0BC4 ,Phase 0B coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P0BC3 ,Phase 0B coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 0B coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P0BC1 ,Phase 0B coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P0BC0 ,Phase 0B coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1834++0x03
|
|
line.long 0x00 "H_FILTER_P0C_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P0CC5 ,Phase 0C coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P0CC4 ,Phase 0C coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P0CC3 ,Phase 0C coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 0C coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P0CC1 ,Phase 0C coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P0CC0 ,Phase 0C coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1838++0x03
|
|
line.long 0x00 "H_FILTER_P0D_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P0DC5 ,Phase 0D coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P0DC4 ,Phase 0D coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P0DC3 ,Phase 0D coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 0D coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P0DC1 ,Phase 0D coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P0DC0 ,Phase 0D coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x183C++0x03
|
|
line.long 0x00 "H_FILTER_P0E_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P0EC5 ,Phase 0E coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P0EC4 ,Phase 0E coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P0EC3 ,Phase 0E coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 0E coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P0EC1 ,Phase 0E coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P0EC0 ,Phase 0E coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1840++0x03
|
|
line.long 0x00 "H_FILTER_P0F_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " B_H_FILTER_P0FC5 ,Phase 0F coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " B_H_FILTER_P0FC4 ,Phase 0F coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_H_FILTER_P0FC3 ,Phase 0F coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_H_FILTER_P00C2 ,Phase 0F coefficient 2"
|
|
bitfld.long 0x00 3.--7. " B_H_FILTER_P0FC1 ,Phase 0F coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " B_H_FILTER_P0FC0 ,Phase 0F coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1844++0x1F
|
|
line.long 0x00 "CSC_YOF_0,Colour Space Conversion Coefficients"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_CSC_YOF ,Y Offset in s.7.0 format"
|
|
line.long 0x04 "CSC_KYRGB_0,Window B CSC Y Coefficient for RGB"
|
|
hexmask.long.word 0x04 0.--9. 1. " B_CSC_KYRGB ,Y Gain for R, G, B colours in 2.8 format"
|
|
line.long 0x08 "CSC_KUR_0,Window B CSC U coefficient for R"
|
|
hexmask.long.word 0x08 0.--10. 1. " B_CSC_KUR ,U coefficients for R in s.2.8 format"
|
|
line.long 0x0C "CSC_KVR_0,Window B CSC V coefficient for R"
|
|
hexmask.long.word 0x0C 0.--10. 1. " B_CSC_KVR ,V coefficients for R in s.2.8 format"
|
|
line.long 0x10 "CSC_KUG_0,Window B CSC U coefficient for G"
|
|
hexmask.long.word 0x10 0.--9. 1. " B_CSC_KUG ,U coefficients for G in s.1.8 format"
|
|
line.long 0x14 "CSC_KVG_0,Window B CSC V coefficient for G"
|
|
hexmask.long.word 0x14 0.--9. 1. " B_CSC_KVG ,V coefficients for G in s.1.8 format"
|
|
line.long 0x18 "CSC_KUB_0,Window B CSC U coefficient for B"
|
|
hexmask.long.word 0x18 0.--10. 1. " B_CSC_KUB ,U coefficients for B in s.2.8 format"
|
|
line.long 0x1C "CSC_KVB_0,Window B CSC V coefficient for B"
|
|
hexmask.long.word 0x1C 0.--10. 1. " B_CSC_KVB ,V coefficients for B in s.2.8 format"
|
|
textline " "
|
|
group.long 0x1864++0x03
|
|
line.long 0x00 "V_FILTER_P00_0,Window B Vertical Filter phase 00"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P00C0 ,Phase 00 coefficient 0"
|
|
group.long 0x1868++0x03
|
|
line.long 0x00 "V_FILTER_P01_0,Window B Vertical Filter phase 01"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P01C0 ,Phase 01 coefficient 1"
|
|
group.long 0x186C++0x03
|
|
line.long 0x00 "V_FILTER_P02_0,Window B Vertical Filter phase 02"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P02C0 ,Phase 02 coefficient 2"
|
|
group.long 0x1870++0x03
|
|
line.long 0x00 "V_FILTER_P03_0,Window B Vertical Filter phase 03"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P03C0 ,Phase 03 coefficient 3"
|
|
group.long 0x1874++0x03
|
|
line.long 0x00 "V_FILTER_P04_0,Window B Vertical Filter phase 04"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P04C0 ,Phase 04 coefficient 4"
|
|
group.long 0x1878++0x03
|
|
line.long 0x00 "V_FILTER_P05_0,Window B Vertical Filter phase 05"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P05C0 ,Phase 05 coefficient 5"
|
|
group.long 0x187C++0x03
|
|
line.long 0x00 "V_FILTER_P06_0,Window B Vertical Filter phase 06"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P06C0 ,Phase 06 coefficient 6"
|
|
group.long 0x1880++0x03
|
|
line.long 0x00 "V_FILTER_P07_0,Window B Vertical Filter phase 07"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P07C0 ,Phase 07 coefficient 7"
|
|
group.long 0x1884++0x03
|
|
line.long 0x00 "V_FILTER_P08_0,Window B Vertical Filter phase 08"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P08C0 ,Phase 08 coefficient 8"
|
|
group.long 0x1888++0x03
|
|
line.long 0x00 "V_FILTER_P09_0,Window B Vertical Filter phase 09"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P09C0 ,Phase 09 coefficient 9"
|
|
group.long 0x188C++0x03
|
|
line.long 0x00 "V_FILTER_P0A_0,Window B Vertical Filter phase 0A"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P0AC0 ,Phase 0A coefficient A"
|
|
group.long 0x1890++0x03
|
|
line.long 0x00 "V_FILTER_P0B_0,Window B Vertical Filter phase 0B"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P0BC0 ,Phase 0B coefficient B"
|
|
group.long 0x1894++0x03
|
|
line.long 0x00 "V_FILTER_P0C_0,Window B Vertical Filter phase 0C"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P0CC0 ,Phase 0C coefficient C"
|
|
group.long 0x1898++0x03
|
|
line.long 0x00 "V_FILTER_P0D_0,Window B Vertical Filter phase 0D"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P0DC0 ,Phase 0D coefficient D"
|
|
group.long 0x189C++0x03
|
|
line.long 0x00 "V_FILTER_P0E_0,Window B Vertical Filter phase 0E"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P0EC0 ,Phase 0E coefficient E"
|
|
group.long 0x18A0++0x03
|
|
line.long 0x00 "V_FILTER_P0F_0,Window B Vertical Filter phase 0F"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_V_FILTER_P0FC0 ,Phase 0F coefficient F"
|
|
textline " "
|
|
group.long 0x18A4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P00_0,Window B Horizontal Filter phase 00"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P00C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P00C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P00C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P00C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P00C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P00C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18A8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P01_0,Window B Horizontal Filter phase 01"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P01C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P01C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P01C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P01C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P01C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P01C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18AC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P02_0,Window B Horizontal Filter phase 02"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P02C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P02C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P02C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P02C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P02C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P02C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18B0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P03_0,Window B Horizontal Filter phase 03"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P03C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P03C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P03C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P03C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P03C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P03C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18B4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P04_0,Window B Horizontal Filter phase 04"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P04C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P04C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P04C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P04C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P04C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P04C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18B8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P05_0,Window B Horizontal Filter phase 05"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P05C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P05C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P05C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P05C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P05C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P05C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18BC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P06_0,Window B Horizontal Filter phase 06"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P06C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P06C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P06C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P06C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P06C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P06C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18C0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P07_0,Window B Horizontal Filter phase 07"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P07C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P07C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P07C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P07C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P07C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P07C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18C4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P08_0,Window B Horizontal Filter phase 08"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P08C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P08C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P08C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P08C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P08C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P08C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18C8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P09_0,Window B Horizontal Filter phase 09"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P09C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P09C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P09C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P09C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P09C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P09C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18CC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0A_0,Window B Horizontal Filter phase 0A"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P0AC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P0AC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P0AC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P0AC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P0AC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P0AC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18D0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0B_0,Window B Horizontal Filter phase 0B"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P0BC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P0BC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P0BC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P0BC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P0BC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P0BC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18D4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0C_0,Window B Horizontal Filter phase 0C"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P0CC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P0CC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P0CC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P0CC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P0CC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P0CC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18D8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0D_0,Window B Horizontal Filter phase 0D"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P0DC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P0DC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P0DC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P0DC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P0DC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P0DC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18DC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0E_0,Window B Horizontal Filter phase 0E"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P0EC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P0EC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P0EC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P0EC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P0EC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P0EC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18E0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0F_0,Window B Horizontal Filter phase 0F"
|
|
bitfld.long 0x00 8.--9. " B_H_FILTER_HI_P0FC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " B_H_FILTER_HI_P0FC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " B_H_FILTER_HI_P0FC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_H_FILTER_HI_P0FC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " B_H_FILTER_HI_P0FC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " B_H_FILTER_HI_P0FC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
textline " "
|
|
width 15.
|
|
if (((d.l(ad:0x542400000+0x1C00))&0x400)==0x400)
|
|
group.long 0x1C00++0x03
|
|
line.long 0x00 "WIN_OPTIONS_0,Window B Options"
|
|
bitfld.long 0x00 31. " B_H_FILTER_MODE ,Horizontal filter mode" "Old,New"
|
|
bitfld.long 0x00 30. " B_WIN_ENABLE ,Window B Window enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " B_INTERLACE_ENABLE ,Window B Interlace enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " B_YUV_RANGE_EXPAND ,Window B Enable range expansion" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " B_DV_ENABLE ,Window B Digital Vibrance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " B_CSC_ENABLE ,Window B Color Space Conversion Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " B_CP_ENABLE ,Window B Color Palette Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " B_V_FILTER_UV_ALIGN ,Window B V Filter UV Alignment" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " B_V_FILTER_OPTIMIZE ,Window B V Filter Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " B_V_FILTER_ENABLE ,Window B V Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " B_H_FILTER_ENABLE ,Window B H Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " B_COLOR_EXPAND ,Color expansion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " B_SCAN_COLUMN ,Window B Scanning direction" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " B_V_DIRECTION ,Window B Vertical (Y) drawing Direction" "Increment,Decrement"
|
|
bitfld.long 0x00 0. " B_H_DIRECTION ,Window B Horizontal (X) drawing Direction" "Increment,Decrement"
|
|
else
|
|
group.long 0x1C00++0x03
|
|
line.long 0x00 "WIN_OPTIONS_0,Window B Options"
|
|
bitfld.long 0x00 31. " B_H_FILTER_MODE ,Horizontal filter mode" "Old,New"
|
|
bitfld.long 0x00 30. " B_WIN_ENABLE ,Window B Window enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " B_INTERLACE_ENABLE ,Window B Interlace enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " B_YUV_RANGE_EXPAND ,Window B Enable range expansion" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " B_DV_ENABLE ,Window B Digital Vibrance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " B_CSC_ENABLE ,Window B Color Space Conversion Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " B_CP_ENABLE ,Window B Color Palette Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " B_V_FILTER_ENABLE ,Window B V Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " B_H_FILTER_ENABLE ,Window B H Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " B_COLOR_EXPAND ,Color expansion" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " B_SCAN_COLUMN ,Window B Scanning direction" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " B_V_DIRECTION ,Window B Vertical (Y) drawing Direction" "Increment,Decrement"
|
|
textline " "
|
|
bitfld.long 0x00 0. " B_H_DIRECTION ,Window B Horizontal (X) drawing Direction" "Increment,Decrement"
|
|
endif
|
|
group.long 0x1C04++0x03
|
|
line.long 0x00 "BYTE_SWAP_0,Window B Byte Swap"
|
|
bitfld.long 0x00 0.--2. " B_BYTE_SWAP ,Window B Byte Swap" "NOSWAP,SWAP2,SWAP4,SWAP4HW,SWAP02,SWAPLEFT,,"
|
|
group.long 0x1C0C++0x03
|
|
line.long 0x00 "COLOR_DEPTH_0,Window B Color depth"
|
|
hexmask.long.byte 0x00 0.--6. 1. " B_COLOR_DEPTH ,Window B Color Depth"
|
|
width 18.
|
|
textline " "
|
|
group.long 0x1C10++0x03
|
|
line.long 0x00 "POSITION_0,Window B Position"
|
|
hexmask.long.word 0x00 16.--28. 1. " B_V_POSITION ,Window B V Position"
|
|
hexmask.long.word 0x00 0.--12. 1. " B_H_POSITION ,Window B H Position"
|
|
group.long 0x1C14++0x03
|
|
line.long 0x00 "SIZE_0,Window B Size"
|
|
hexmask.long.word 0x00 16.--28. 1. " B_V_SIZE ,Vertical size after scaling"
|
|
hexmask.long.word 0x00 0.--12. 1. " B_H_SIZE ,Horizontal size after scaling"
|
|
group.long 0x1C18++0x03
|
|
line.long 0x00 "PRESCALED_SIZE_0,Window B Pre-scaled Size"
|
|
hexmask.long.word 0x00 16.--28. 1. " B_V_PRESCALED_SIZE ,Window B V Pre-scaled Size"
|
|
hexmask.long.word 0x00 0.--14. 1. " B_H_PRESCALED_SIZE ,Window B H Pre-scaled Size"
|
|
group.long 0x1C1C++0x03
|
|
line.long 0x00 "H_INITIAL_DDA_0,Window B H Initial DDA"
|
|
hexmask.long.word 0x00 0.--15. 1. " B_H_INITIAL_DDA ,Window B H Initial DDA"
|
|
group.long 0x1C20++0x03
|
|
line.long 0x00 "V_INITIAL_DDA_0,Window B V Initial DDA"
|
|
hexmask.long.word 0x00 0.--15. 1. " B_V_INITIAL_DDA ,Window B V Initial DDA"
|
|
group.long 0x1C24++0x03
|
|
line.long 0x00 "DDA_INCREMENT_0,Window B DDA Increment"
|
|
hexmask.long.word 0x00 16.--31. 1. " B_V_DDA_INCREMENT ,Window B Vertical DDA Increment"
|
|
hexmask.long.word 0x00 0.--15. 1. " B_H_DDA_INCREMENT ,Window B Horizontal DDA Increment"
|
|
group.long 0x1C28++0x03
|
|
line.long 0x00 "LINE_STRIDE_0,Window B Line Stride"
|
|
hexmask.long.word 0x00 16.--31. 1. " B_UV_LINE_STRIDE ,Window B Line Stride for Chroma"
|
|
hexmask.long.word 0x00 0.--15. 1. " B_LINE_STRIDE ,Window B Line Stride"
|
|
group.long 0x1C38++0x03
|
|
line.long 0x00 "DV_CONTROL_0,Window B Digital Vibrance Control"
|
|
bitfld.long 0x00 16.--18. " B_DV_CONTROL_B ,Digital Vibrance control for B" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " B_DV_CONTROL_G ,Digital Vibrance control for G" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " B_DV_CONTROL_R ,Digital Vibrance control for R" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
width 24.
|
|
group.long 0x1C58++0x0F
|
|
line.long 0x00 "BLEND_LAYER_CONTROL_0,Window B"
|
|
bitfld.long 0x00 25.--27. " B_COLOR_KEY_SELECT ,B COLOR KEY SELECT" "0,1,2,3,4,5,6,7"
|
|
eventfld.long 0x00 24. " B_BLEND_BYPASS ,B BLEND BYPASS" "BLEND_ENABLE,BLEND_BYPASS"
|
|
hexmask.long.byte 0x00 16.--23. 1. " B_K2 ,B K2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " B_K1 ,B K1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " B_WINDOW_LAYER_DEPTH ,B window layer depth"
|
|
line.long 0x04 "BLEND_MATCH_SELECT_0,DC WIN B BLEND MATCH SELECT 0"
|
|
bitfld.long 0x04 12.--13. " B_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT ,B blend factor dst alpha match select" "0,1,EG_K1_TIMES_SRC,K2"
|
|
bitfld.long 0x04 8.--9. " B_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT ,B blend factor src alpha match select" "0,K1,K2,"
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " B_BLEND_FACTOR_DST_COLOR_MATCH_SELECT ,B blend factor dst color match select" "0,1,K1,K2,K1_TIMES_DST,NEG_K1_TIMES_DST,NEG_K1_TIMES_SRC,NEG_K1"
|
|
bitfld.long 0x04 0.--2. " B_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT ,B blend factor src color match select" "0,1,K1,K1_TIMES_DST,NEG_K1_TIMES_DST,K1_TIMES_SRC,,"
|
|
line.long 0x08 "BLEND_NOMATCH_SELECT_0,DC WIN B BLEND NOMATCH SELECT 0"
|
|
bitfld.long 0x08 12.--13. " B_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT ,B blend factor dst alpha nomatch select" "0,1,EG_K1_TIMES_SRC,K2"
|
|
bitfld.long 0x08 8.--9. " B_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT ,B blend factor src alpha nomatch select" "0,K1,K2,"
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " B_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT ,B blend factor dst color nomatch select" "0,1,K1,K2,K1_TIMES_DST,NEG_K1_TIMES_DST,NEG_K1_TIMES_SRC,NEG_K1"
|
|
bitfld.long 0x08 0.--2. " B_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT ,B blend factor src color nomatch select" "0,1,K1,K1_TIMES_DST,NEG_K1_TIMES_DST,K1_TIMES_SRC,,"
|
|
line.long 0x0C "BLEND_ALPHA_1BIT_0,Win B blend alpha 1bit 0"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " B_BLEND_WEIGHT1 ,Alpha value of 1"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " B_BLEND_WEIGHT0 ,Alpha value of 0"
|
|
tree.end
|
|
width 19.
|
|
tree "WINBUF_B Registers"
|
|
group.long 0x2000++0x27
|
|
line.long 0x00 "START_ADDR_0,Window B Start Address"
|
|
line.long 0x04 "START_ADDR_NS_0,Window B Shadowed Start Address"
|
|
line.long 0x08 "START_ADDR_U_0,Window B Start Address for U plane"
|
|
line.long 0x0C "START_ADDR_U_NS_0,Window B Shadowed Start Address for U plane"
|
|
line.long 0x10 "START_ADDR_V_0,Window B Start Address for V plane"
|
|
line.long 0x14 "START_ADDR_V_NS_0,WWindow B Shadowed Start Address for V plane"
|
|
line.long 0x18 "ADDR_H_OFFSET_0,Window B Horizontal Address Offset"
|
|
line.long 0x1C "ADDR_H_OFFSET_NS_0,Window B Shadowed Horizontal Address Offset"
|
|
line.long 0x20 "ADDR_V_OFFSET_0,Window B Vertical Address Offset"
|
|
line.long 0x24 "ADDR_V_OFFSET_NS_0,Window B Shadowed Vertical Address Offset"
|
|
group.long 0x2028++0x0B
|
|
line.long 0x00 "UFLOW_STATUS,Window B FIFO Underflow Status Register"
|
|
bitfld.long 0x00 30. " COUNT_OFLOW ,Counter has overflowed" "Not occurred,Occurred"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " UFLOW_COUNT ,Underflow count"
|
|
line.long 0x04 "SURFACE_KIND_0,Window B Surface Kind"
|
|
bitfld.long 0x04 4.--6. " B_BLOCK_HEIGHT ,Block Height" "HEIGHT_1,HEIGHT_2,HEIGHT_4,HEIGHT_8,HEIGHT_16,HEIGHT_32,,"
|
|
bitfld.long 0x04 0.--1. " B_SURFACE_KIND ,Surface kind" "PITCH,TILED,BL_16B2,"
|
|
line.long 0x08 "SURFACE_WEIGHT_0,Window B Surface Weights"
|
|
bitfld.long 0x08 5.--6. " B_SURFACE_WEIGHT_V ,Window B V Surface Weights" "2,4,8,16"
|
|
bitfld.long 0x08 3.--4. " B_SURFACE_WEIGHT_U ,Window B U or UV Surface Weights" "2,4,8,16"
|
|
bitfld.long 0x08 1.--2. " B_SURFACE_WEIGHT_Y ,Window B Y or packed Surface Weights" "2,4,8,16"
|
|
textline " "
|
|
bitfld.long 0x08 0. " B_SURFACE_WEIGHT_OVERRIDE ,Weight Override" "Disabled,Enabled"
|
|
textline " "
|
|
width 22.
|
|
group.long 0x2034++0x17
|
|
line.long 0x00 "START_ADDR_HI_0,Window B Higher 2 bits of Start Address"
|
|
bitfld.long 0x00 0.--1. " B_START_ADDR_HI ,Window B Start Address" "0,1,2,3"
|
|
line.long 0x04 "START_ADDR_HI_NS_0,Window B Higher 2 bits of Start Address"
|
|
bitfld.long 0x04 0.--1. " B_START_ADDR_HI_NS ,Window B Shadowed Start Address" "0,1,2,3"
|
|
line.long 0x08 "START_ADDR_HI_U_0,Window B Higher 2 bits of Start Address"
|
|
bitfld.long 0x08 0.--1. " B_START_ADDR_HI ,Window B Start Address" "0,1,2,3"
|
|
line.long 0x0C "START_ADDR_HI_U_NS_0,Window B Shadowed Higher 2 bits of Start Address for U Plane"
|
|
bitfld.long 0x0C 0.--1. " B_START_ADDR_HI_U_NS ,Window B Shadowed Higher 2 bits of Start Address for U plane" "0,1,2,3"
|
|
line.long 0x10 "START_ADDR_HI_V_0,Window B Higher 2 bits of Start Address for V Plane"
|
|
bitfld.long 0x10 0.--1. " B_START_ADDR_HI_V ,Window B Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
line.long 0x14 "START_ADDR_HI_V_NS_0,Window B Shadowed Higher 2 bits of Start Address for V Plane"
|
|
bitfld.long 0x14 0.--1. " B_START_ADDR_HI_V_NS ,Window B Shadowed Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
textline " "
|
|
width 29.
|
|
group.long 0x204C++0x17
|
|
line.long 0x00 "START_ADDR_FIELD2_0,Window B Start Address"
|
|
line.long 0x04 "START_ADDR_FIELD2_NS_0,Window B Shadowed Start Address"
|
|
line.long 0x08 "START_ADDR_FIELD2_U_0,Window B Start Address for U plane"
|
|
line.long 0x0C "START_ADDR_FIELD2_U_NS_0,Window B Shadowed Start Address for U plane"
|
|
line.long 0x10 "START_ADDR_FIELD2_V_0,Window B Start Address for V plane"
|
|
line.long 0x14 "START_ADDR_FIELD2_V_NS_0,Window B Shadowed Start Address for V plane"
|
|
group.long 0x2064++0x17
|
|
line.long 0x00 "START_ADDR_FIELD2_HI_0,Window B Higher 2 bits of Start Address"
|
|
bitfld.long 0x00 0.--1. " B_START_ADDR_FIELD2_HI ,Window B Start Address" "0,1,2,3"
|
|
line.long 0x04 "START_ADDR_FIELD2_HI_NS_0,Window B Shadowed Higher 2 bits of Start Address"
|
|
bitfld.long 0x04 0.--1. " B_START_ADDR_FIELD2_HI_NS ,Window B Shadowed Start Address" "0,1,2,3"
|
|
line.long 0x08 "START_ADDR_FIELD2_HI_U_0,Window B Higher 2 bits of Start Address for U plane"
|
|
bitfld.long 0x08 0.--1. " B_START_ADDR_FIELD2_HI_U ,Window B Start Address for U plane" "0,1,2,3"
|
|
line.long 0x0C "START_ADDR_FIELD2_HI_U_NS_0,Window B Shadowed Higher 32 bits of Start Address for U plane"
|
|
bitfld.long 0x0C 0.--1. " B_START_ADDR_FIELD2_HI_U_NS ,Window B Shadowed Higher 2 bits of Start Address for U plane" "0,1,2,3"
|
|
line.long 0x10 "START_ADDR_FIELD2_HI_V_0,Window B Higher 2 bits of Start Address for V plane"
|
|
bitfld.long 0x10 0.--1. " B_START_ADDR_FIELD2_HI_V ,Window B Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
line.long 0x14 "START_ADDR_FIELD2_HI_V_NS_0,Window B Shadowed Higher 2 bits of Start Address for V plane"
|
|
bitfld.long 0x14 0.--1. " B_START_ADDR_FIELD2_HI_V_NS ,Window B Shadowed Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
group.long 0x207C++0x0F
|
|
line.long 0x00 "ADDR_H_OFFSET_FIELD2_0,Window B Horizontal address offset"
|
|
line.long 0x04 "ADDR_H_OFFSET_FIELD2_NS_0,Window B Shadowed Horizontal address offset"
|
|
line.long 0x08 "ADDR_V_OFFSET_FIELD2_0,Window B Vertical address offset"
|
|
line.long 0x0C "ADDR_V_OFFSET_FIELD2_NS_0,Window B Shadowed Vertical address offset"
|
|
group.long 0x2090++0x03
|
|
line.long 0x00 "UFLOW_CTRL_0,DC WINBUF B UFLOW CTRL 0"
|
|
bitfld.long 0x00 0. " B_UFLOW_CTRL_DBG_MODE ,B UFLOW CTRL DBG MODE" "Disabled,Enabled"
|
|
textline " "
|
|
width 25.
|
|
group.long 0x2094++0x27
|
|
line.long 0x00 "UFLOW_DBG_PIXEL_0,DC WINBUF B UFLOW DBG PIXEL 0"
|
|
line.long 0x04 "UFLOW_THRESHOLD_0,DC WINBUF B UFLOW THRESHOLD 0"
|
|
hexmask.long.word 0x04 0.--12. 1. " B_UFLOW_THRESHOLD ,B UFLOW THRESHOLD"
|
|
line.long 0x08 "SPOOL_UP_0,Spool up time configuration for different windows related logic"
|
|
hexmask.long.word 0x08 16.--28. 1. " B_SPOOL_UP_DURATION ,B SPOOL UP DURATION"
|
|
bitfld.long 0x08 1. " B_SPOOL_UP_EDGE ,B SPOOL UP EDGE" "NEGEDGE,POSEDGE"
|
|
bitfld.long 0x08 0. " B_SPOOL_UP_CTRL ,B SPOOL UP CTRL" "MAX,PROGRAMMABLE"
|
|
line.long 0x0C "SCALEFACTOR_THRESHOLD_0,DC WINBUF B SCALEFACTOR THRESHOLD 0"
|
|
hexmask.long.word 0x0C 16.--31. 1. " B_SF_LWM_THRESHOLD ,B SF LWM THRESHOLD"
|
|
hexmask.long.word 0x0C 0.--15. 1. " B_SF_HWM_THRESHOLD ,B SF HWM THRESHOLD"
|
|
line.long 0x10 "LATENCY_THRESHOLD_0,Register controls the behavior of the rdy4_latency_event from the display to the MC"
|
|
bitfld.long 0x10 31. " B_RDY4LATENCY_THRESHOLD_ENABLE ,B RDY4LATENCY THRESHOLD ENABLE" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " B_RDY4LATENCY_SPOOLUP_CTRL ,B RDY4LATENCY SPOOLUP CTRL" "DISALLOW,ALLOW"
|
|
textline " "
|
|
hexmask.long.word 0x10 16.--28. 1. " B_RDY4LATENCY_SPOOLUP_DURATION ,B RDY4LATENCY THRESHOLD"
|
|
hexmask.long.word 0x10 0.--15. 1. " B_RDY4LATENCY_THRESHOLD ,B RDY4LATENCY THRESHOLD"
|
|
line.long 0x14 "MEMFETCH_DEBUG_STATUS_0,Memfetch Debug Status"
|
|
bitfld.long 0x14 16. " B_DEBUG_ENABLE ,Reg to enable FGCG for flops added to debug signals in memfetch" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " B_ALIGN_FIFO_NON_IDLE ,Align FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 13. " B_PIPE0_FIFO_NON_IDLE ,Pipe0 FIFO idle at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 12. " B_FRAME_FIFO_NON_IDLE ,Frame FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 11. " B_SURFACE_FIFO_NON_IDLE ,Surface FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 10. " B_TAG_FIFO_NON_IDLE ,Tag FIFO idle at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 9. " B_RSP_FIFO_NON_IDLE ,Response FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 8. " B_REQ_FIFO_NON_IDLE ,Request FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 7. " B_DP_VALID_NON_IDLE ,DP lines valid at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 6. " B_V_SSM_NON_IDLE ,V SSM is non-idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 5. " B_U_SSM_NON_IDLE ,U SSM is non-idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 4. " B_Y_SSM_NON_IDLE ,Y SSM is non-idle at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 3. " B_DP_POOL_AVAIL ,DP thinks there is data in the pool at end of frame" "No data,Data"
|
|
bitfld.long 0x14 2. " B_POOL_NOT_EMPTY ,Status of pool at end of frame" "Empty,Not empty"
|
|
bitfld.long 0x14 1. " B_UNDERFLOW_LINE1 ,Underflow of line0" "No underflow,Line0 underflowed"
|
|
textline " "
|
|
bitfld.long 0x14 0. " B_UNDERFLOW_LINE0 ,Underflow of line0" "No underflow,Line0 underflowed"
|
|
line.long 0x18 "MEMFETCH_CONTROL_0,Memfetch Control Register"
|
|
bitfld.long 0x18 1. " B_MEMFETCH_CLK_GATE_OVERRIDE ,Disable clock-gating of memfetch for a controller" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " B_MEMFETCH_RESET ,Reset memfetch for a controller" "Disabled,Enabled"
|
|
line.long 0x1C "OCCUPANCY_THROTTLE_0,DC WINBUF B OCCUPANCY THROTTLE 0"
|
|
hexmask.long.word 0x1C 16.--31. 1. " B_OCCUPANCY_MAX_THRESHOLD ,B OCCUPANCY MAX THRESHOLD"
|
|
bitfld.long 0x1C 0. " B_OCCUPANCY_THROTTLE_MODE ,B OCCUPANCY THROTTLE MODE" "Disabled,Enabled"
|
|
line.long 0x20 "SCRATCH_REGISTER_0_0,DC WINBUF B SCRATCH REGISTER 0 0"
|
|
line.long 0x24 "SCRATCH_REGISTER_1_0,DC WINBUF B SCRATCH REGISTER 1 0"
|
|
tree.end
|
|
width 19.
|
|
tree "Window C Registers"
|
|
wgroup.long 0x1400++0x03
|
|
line.long 0x00 "COLOR_PALETTE_0,Window C Color Palette"
|
|
button "BGR" "d (ad:0x542400000+0x1400)--(ad:0x542400000+0x17fc) /long"
|
|
group.long 0x1800++0x03
|
|
line.long 0x00 "PALETTE_COLOR_EXT_0,Window C Palette Color Extension"
|
|
hexmask.long.byte 0x00 1.--7. 1. " C_PALETTE_COLOR_EXT ,Window C Palette Color Extension"
|
|
group.long 0x1804++0x03
|
|
line.long 0x00 "H_FILTER_P00_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P00C5 ,Phase 00 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P00C4 ,Phase 00 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P00C3 ,Phase 00 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 00 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P00C1 ,Phase 00 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P00C0 ,Phase 00 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1808++0x03
|
|
line.long 0x00 "H_FILTER_P01_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P01C5 ,Phase 01 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P01C4 ,Phase 01 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P01C3 ,Phase 01 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 01 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P01C1 ,Phase 01 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P01C0 ,Phase 01 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x180C++0x03
|
|
line.long 0x00 "H_FILTER_P02_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P02C5 ,Phase 02 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P02C4 ,Phase 02 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P02C3 ,Phase 02 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 02 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P02C1 ,Phase 02 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P02C0 ,Phase 02 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1810++0x03
|
|
line.long 0x00 "H_FILTER_P03_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P03C5 ,Phase 03 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P03C4 ,Phase 03 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P03C3 ,Phase 03 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 03 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P03C1 ,Phase 03 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P03C0 ,Phase 03 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1814++0x03
|
|
line.long 0x00 "H_FILTER_P04_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P04C5 ,Phase 04 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P04C4 ,Phase 04 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P04C3 ,Phase 04 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 04 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P04C1 ,Phase 04 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P04C0 ,Phase 04 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1818++0x03
|
|
line.long 0x00 "H_FILTER_P05_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P05C5 ,Phase 05 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P05C4 ,Phase 05 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P05C3 ,Phase 05 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 05 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P05C1 ,Phase 05 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P05C0 ,Phase 05 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x181C++0x03
|
|
line.long 0x00 "H_FILTER_P06_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P06C5 ,Phase 06 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P06C4 ,Phase 06 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P06C3 ,Phase 06 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 06 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P06C1 ,Phase 06 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P06C0 ,Phase 06 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1820++0x03
|
|
line.long 0x00 "H_FILTER_P07_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P07C5 ,Phase 07 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P07C4 ,Phase 07 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P07C3 ,Phase 07 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 07 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P07C1 ,Phase 07 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P07C0 ,Phase 07 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1824++0x03
|
|
line.long 0x00 "H_FILTER_P08_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P08C5 ,Phase 08 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P08C4 ,Phase 08 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P08C3 ,Phase 08 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 08 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P08C1 ,Phase 08 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P08C0 ,Phase 08 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1828++0x03
|
|
line.long 0x00 "H_FILTER_P09_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P09C5 ,Phase 09 coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P09C4 ,Phase 09 coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P09C3 ,Phase 09 coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 09 coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P09C1 ,Phase 09 coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P09C0 ,Phase 09 coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x182C++0x03
|
|
line.long 0x00 "H_FILTER_P0A_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P0AC5 ,Phase 0A coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P0AC4 ,Phase 0A coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P0AC3 ,Phase 0A coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 0A coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P0AC1 ,Phase 0A coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P0AC0 ,Phase 0A coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1830++0x03
|
|
line.long 0x00 "H_FILTER_P0B_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P0BC5 ,Phase 0B coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P0BC4 ,Phase 0B coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P0BC3 ,Phase 0B coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 0B coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P0BC1 ,Phase 0B coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P0BC0 ,Phase 0B coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1834++0x03
|
|
line.long 0x00 "H_FILTER_P0C_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P0CC5 ,Phase 0C coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P0CC4 ,Phase 0C coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P0CC3 ,Phase 0C coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 0C coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P0CC1 ,Phase 0C coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P0CC0 ,Phase 0C coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1838++0x03
|
|
line.long 0x00 "H_FILTER_P0D_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P0DC5 ,Phase 0D coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P0DC4 ,Phase 0D coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P0DC3 ,Phase 0D coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 0D coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P0DC1 ,Phase 0D coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P0DC0 ,Phase 0D coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x183C++0x03
|
|
line.long 0x00 "H_FILTER_P0E_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P0EC5 ,Phase 0E coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P0EC4 ,Phase 0E coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P0EC3 ,Phase 0E coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 0E coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P0EC1 ,Phase 0E coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P0EC0 ,Phase 0E coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1840++0x03
|
|
line.long 0x00 "H_FILTER_P0F_0,Horizontal Scaling Filter Coefficients"
|
|
bitfld.long 0x00 29.--31. " C_H_FILTER_P0FC5 ,Phase 0F coefficient 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--28. " C_H_FILTER_P0FC4 ,Phase 0F coefficient 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_H_FILTER_P0FC3 ,Phase 0F coefficient 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_H_FILTER_P00C2 ,Phase 0F coefficient 2"
|
|
bitfld.long 0x00 3.--7. " C_H_FILTER_P0FC1 ,Phase 0F coefficient 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " C_H_FILTER_P0FC0 ,Phase 0F coefficient 0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1844++0x1F
|
|
line.long 0x00 "CSC_YOF_0,Colour Space Conversion Coefficients"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_CSC_YOF ,Y Offset in s.7.0 format"
|
|
line.long 0x04 "CSC_KYRGB_0,Window C CSC Y Coefficient for RGB"
|
|
hexmask.long.word 0x04 0.--9. 1. " C_CSC_KYRGB ,Y Gain for R, G, B colours in 2.8 format"
|
|
line.long 0x08 "CSC_KUR_0,Window C CSC U coefficient for R"
|
|
hexmask.long.word 0x08 0.--10. 1. " C_CSC_KUR ,U coefficients for R in s.2.8 format"
|
|
line.long 0x0C "CSC_KVR_0,Window C CSC V coefficient for R"
|
|
hexmask.long.word 0x0C 0.--10. 1. " C_CSC_KVR ,V coefficients for R in s.2.8 format"
|
|
line.long 0x10 "CSC_KUG_0,Window C CSC U coefficient for G"
|
|
hexmask.long.word 0x10 0.--9. 1. " C_CSC_KUG ,U coefficients for G in s.1.8 format"
|
|
line.long 0x14 "CSC_KVG_0,Window C CSC V coefficient for G"
|
|
hexmask.long.word 0x14 0.--9. 1. " C_CSC_KVG ,V coefficients for G in s.1.8 format"
|
|
line.long 0x18 "CSC_KUB_0,Window C CSC U coefficient for B"
|
|
hexmask.long.word 0x18 0.--10. 1. " C_CSC_KUB ,U coefficients for B in s.2.8 format"
|
|
line.long 0x1C "CSC_KVB_0,Window C CSC V coefficient for B"
|
|
hexmask.long.word 0x1C 0.--10. 1. " C_CSC_KVB ,V coefficients for B in s.2.8 format"
|
|
textline " "
|
|
group.long 0x1864++0x03
|
|
line.long 0x00 "V_FILTER_P00_0,Window C Vertical Filter phase 00"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P00C0 ,Phase 00 coefficient 0"
|
|
group.long 0x1868++0x03
|
|
line.long 0x00 "V_FILTER_P01_0,Window C Vertical Filter phase 01"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P01C0 ,Phase 01 coefficient 1"
|
|
group.long 0x186C++0x03
|
|
line.long 0x00 "V_FILTER_P02_0,Window C Vertical Filter phase 02"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P02C0 ,Phase 02 coefficient 2"
|
|
group.long 0x1870++0x03
|
|
line.long 0x00 "V_FILTER_P03_0,Window C Vertical Filter phase 03"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P03C0 ,Phase 03 coefficient 3"
|
|
group.long 0x1874++0x03
|
|
line.long 0x00 "V_FILTER_P04_0,Window C Vertical Filter phase 04"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P04C0 ,Phase 04 coefficient 4"
|
|
group.long 0x1878++0x03
|
|
line.long 0x00 "V_FILTER_P05_0,Window C Vertical Filter phase 05"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P05C0 ,Phase 05 coefficient 5"
|
|
group.long 0x187C++0x03
|
|
line.long 0x00 "V_FILTER_P06_0,Window C Vertical Filter phase 06"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P06C0 ,Phase 06 coefficient 6"
|
|
group.long 0x1880++0x03
|
|
line.long 0x00 "V_FILTER_P07_0,Window C Vertical Filter phase 07"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P07C0 ,Phase 07 coefficient 7"
|
|
group.long 0x1884++0x03
|
|
line.long 0x00 "V_FILTER_P08_0,Window C Vertical Filter phase 08"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P08C0 ,Phase 08 coefficient 8"
|
|
group.long 0x1888++0x03
|
|
line.long 0x00 "V_FILTER_P09_0,Window C Vertical Filter phase 09"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P09C0 ,Phase 09 coefficient 9"
|
|
group.long 0x188C++0x03
|
|
line.long 0x00 "V_FILTER_P0A_0,Window C Vertical Filter phase 0A"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P0AC0 ,Phase 0A coefficient A"
|
|
group.long 0x1890++0x03
|
|
line.long 0x00 "V_FILTER_P0B_0,Window C Vertical Filter phase 0B"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P0BC0 ,Phase 0B coefficient B"
|
|
group.long 0x1894++0x03
|
|
line.long 0x00 "V_FILTER_P0C_0,Window C Vertical Filter phase 0C"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P0CC0 ,Phase 0C coefficient C"
|
|
group.long 0x1898++0x03
|
|
line.long 0x00 "V_FILTER_P0D_0,Window C Vertical Filter phase 0D"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P0DC0 ,Phase 0D coefficient D"
|
|
group.long 0x189C++0x03
|
|
line.long 0x00 "V_FILTER_P0E_0,Window C Vertical Filter phase 0E"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P0EC0 ,Phase 0E coefficient E"
|
|
group.long 0x18A0++0x03
|
|
line.long 0x00 "V_FILTER_P0F_0,Window C Vertical Filter phase 0F"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_V_FILTER_P0FC0 ,Phase 0F coefficient F"
|
|
textline " "
|
|
group.long 0x18A4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P00_0,Window C Horizontal Filter phase 00"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P00C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P00C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P00C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P00C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P00C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P00C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18A8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P01_0,Window C Horizontal Filter phase 01"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P01C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P01C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P01C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P01C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P01C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P01C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18AC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P02_0,Window C Horizontal Filter phase 02"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P02C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P02C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P02C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P02C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P02C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P02C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18B0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P03_0,Window C Horizontal Filter phase 03"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P03C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P03C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P03C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P03C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P03C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P03C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18B4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P04_0,Window C Horizontal Filter phase 04"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P04C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P04C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P04C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P04C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P04C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P04C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18B8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P05_0,Window C Horizontal Filter phase 05"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P05C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P05C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P05C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P05C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P05C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P05C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18BC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P06_0,Window C Horizontal Filter phase 06"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P06C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P06C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P06C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P06C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P06C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P06C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18C0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P07_0,Window C Horizontal Filter phase 07"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P07C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P07C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P07C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P07C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P07C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P07C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18C4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P08_0,Window C Horizontal Filter phase 08"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P08C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P08C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P08C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P08C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P08C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P08C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18C8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P09_0,Window C Horizontal Filter phase 09"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P09C5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P09C4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P09C3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P09C2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P09C1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P09C0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18CC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0A_0,Window C Horizontal Filter phase 0A"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P0AC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P0AC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P0AC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P0AC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P0AC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P0AC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18D0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0B_0,Window C Horizontal Filter phase 0B"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P0BC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P0BC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P0BC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P0BC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P0BC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P0BC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18D4++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0C_0,Window C Horizontal Filter phase 0C"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P0CC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P0CC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P0CC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P0CC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P0CC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P0CC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18D8++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0D_0,Window C Horizontal Filter phase 0D"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P0DC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P0DC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P0DC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P0DC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P0DC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P0DC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18DC++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0E_0,Window C Horizontal Filter phase 0E"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P0EC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P0EC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P0EC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P0EC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P0EC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P0EC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
group.long 0x18E0++0x03
|
|
line.long 0x00 "H_FILTER_HI_P0F_0,Window C Horizontal Filter phase 0F"
|
|
bitfld.long 0x00 8.--9. " C_H_FILTER_HI_P0FC5 ,MSB of the lobe 5" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " C_H_FILTER_HI_P0FC4 ,MSB of the lobe 4" "0,1,2,3"
|
|
bitfld.long 0x00 5. " C_H_FILTER_HI_P0FC3 ,MSB of the lobe 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_H_FILTER_HI_P0FC2 ,MSB of the lobe 2" "0,1"
|
|
bitfld.long 0x00 2.--3. " C_H_FILTER_HI_P0FC1 ,MSB of the lobe 1" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " C_H_FILTER_HI_P0FC0 ,MSB of the lobe 0" "0,1,2,3"
|
|
textline " "
|
|
width 15.
|
|
if (((d.l(ad:0x542400000+0x1C00))&0x400)==0x400)
|
|
group.long 0x1C00++0x03
|
|
line.long 0x00 "WIN_OPTIONS_0,Window C Options"
|
|
bitfld.long 0x00 31. " C_H_FILTER_MODE ,Horizontal filter mode" "Old,New"
|
|
bitfld.long 0x00 30. " C_WIN_ENABLE ,Window C Window enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " C_INTERLACE_ENABLE ,Window C Interlace enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " C_YUV_RANGE_EXPAND ,Window C Enable range expansion" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " C_DV_ENABLE ,Window C Digital Vibrance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " C_CSC_ENABLE ,Window C Color Space Conversion Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " C_CP_ENABLE ,Window C Color Palette Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " C_V_FILTER_UV_ALIGN ,Window C V Filter UV Alignment" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " C_V_FILTER_OPTIMIZE ,Window C V Filter Optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " C_V_FILTER_ENABLE ,Window C V Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " C_H_FILTER_ENABLE ,Window C H Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " C_COLOR_EXPAND ,Color expansion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " C_SCAN_COLUMN ,Window C Scanning direction" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " C_V_DIRECTION ,Window C Vertical (Y) drawing Direction" "Increment,Decrement"
|
|
bitfld.long 0x00 0. " C_H_DIRECTION ,Window C Horizontal (X) drawing Direction" "Increment,Decrement"
|
|
else
|
|
group.long 0x1C00++0x03
|
|
line.long 0x00 "WIN_OPTIONS_0,Window C Options"
|
|
bitfld.long 0x00 31. " C_H_FILTER_MODE ,Horizontal filter mode" "Old,New"
|
|
bitfld.long 0x00 30. " C_WIN_ENABLE ,Window C Window enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " C_INTERLACE_ENABLE ,Window C Interlace enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " C_YUV_RANGE_EXPAND ,Window C Enable range expansion" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " C_DV_ENABLE ,Window C Digital Vibrance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " C_CSC_ENABLE ,Window C Color Space Conversion Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " C_CP_ENABLE ,Window C Color Palette Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " C_V_FILTER_ENABLE ,Window C V Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " C_H_FILTER_ENABLE ,Window C H Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " C_COLOR_EXPAND ,Color expansion" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " C_SCAN_COLUMN ,Window C Scanning direction" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " C_V_DIRECTION ,Window C Vertical (Y) drawing Direction" "Increment,Decrement"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C_H_DIRECTION ,Window C Horizontal (X) drawing Direction" "Increment,Decrement"
|
|
endif
|
|
group.long 0x1C04++0x03
|
|
line.long 0x00 "BYTE_SWAP_0,Window C Byte Swap"
|
|
bitfld.long 0x00 0.--2. " C_BYTE_SWAP ,Window C Byte Swap" "NOSWAP,SWAP2,SWAP4,SWAP4HW,SWAP02,SWAPLEFT,,"
|
|
group.long 0x1C0C++0x03
|
|
line.long 0x00 "COLOR_DEPTH_0,Window C Color depth"
|
|
hexmask.long.byte 0x00 0.--6. 1. " C_COLOR_DEPTH ,Window C Color Depth"
|
|
width 18.
|
|
group.long 0x1C10++0x03
|
|
line.long 0x00 "POSITION_0,Window C Position"
|
|
hexmask.long.word 0x00 16.--28. 1. " C_V_POSITION ,Window C V Position"
|
|
hexmask.long.word 0x00 0.--12. 1. " C_H_POSITION ,Window C H Position"
|
|
group.long 0x1C14++0x03
|
|
line.long 0x00 "SIZE_0,Window C Size"
|
|
hexmask.long.word 0x00 16.--28. 1. " C_V_SIZE ,Vertical size after scaling"
|
|
hexmask.long.word 0x00 0.--12. 1. " C_H_SIZE ,Horizontal size after scaling"
|
|
group.long 0x1C18++0x03
|
|
line.long 0x00 "PRESCALED_SIZE_0,Window C Pre-scaled Size"
|
|
hexmask.long.word 0x00 16.--28. 1. " C_V_PRESCALED_SIZE ,Window C V Pre-scaled Size"
|
|
hexmask.long.word 0x00 0.--14. 1. " C_H_PRESCALED_SIZE ,Window C H Pre-scaled Size"
|
|
group.long 0x1C1C++0x03
|
|
line.long 0x00 "H_INITIAL_DDA_0,Window C H Initial DDA"
|
|
hexmask.long.word 0x00 0.--15. 1. " C_H_INITIAL_DDA ,Window C H Initial DDA"
|
|
group.long 0x1C20++0x03
|
|
line.long 0x00 "V_INITIAL_DDA_0,Window C V Initial DDA"
|
|
hexmask.long.word 0x00 0.--15. 1. " C_V_INITIAL_DDA ,Window C V Initial DDA"
|
|
group.long 0x1C24++0x03
|
|
line.long 0x00 "DDA_INCREMENT_0,Window C DDA Increment"
|
|
hexmask.long.word 0x00 16.--31. 1. " C_V_DDA_INCREMENT ,Window C Vertical DDA Increment"
|
|
hexmask.long.word 0x00 0.--15. 1. " C_H_DDA_INCREMENT ,Window C Horizontal DDA Increment"
|
|
group.long 0x1C28++0x03
|
|
line.long 0x00 "LINE_STRIDE_0,Window C Line Stride"
|
|
hexmask.long.word 0x00 16.--31. 1. " C_UV_LINE_STRIDE ,Window C Line Stride for Chroma"
|
|
hexmask.long.word 0x00 0.--15. 1. " C_LINE_STRIDE ,Window C Line Stride"
|
|
group.long 0x1C38++0x03
|
|
line.long 0x00 "DV_CONTROL_0,Window C Digital Vibrance Control"
|
|
bitfld.long 0x00 16.--18. " C_DV_CONTROL_B ,Digital Vibrance control for B" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " C_DV_CONTROL_G ,Digital Vibrance control for G" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " C_DV_CONTROL_R ,Digital Vibrance control for R" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
width 24.
|
|
group.long 0x1C58++0x0F
|
|
line.long 0x00 "BLEND_LAYER_CONTROL_0,Window C"
|
|
bitfld.long 0x00 25.--27. " C_COLOR_KEY_SELECT ,C color key select" "0,1,2,3,4,5,6,7"
|
|
eventfld.long 0x00 24. " C_BLEND_BYPASS ,C blend bypass" "BLEND_ENABLE,BLEND_BYPASS"
|
|
hexmask.long.byte 0x00 16.--23. 1. " C_K2 ,C K2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " C_K1 ,C K1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C_WINDOW_LAYER_DEPTH ,Window C layer depth"
|
|
line.long 0x04 "BLEND_MATCH_SELECT_0,DC WIN C BLEND MATCH SELECT 0"
|
|
bitfld.long 0x04 12.--13. " C_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT ,C blend factor dst alpha match select" "0,1,EG_K1_TIMES_SRC,K2"
|
|
bitfld.long 0x04 8.--9. " C_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT ,C blend factor src alpha match select" "0,K1,K2,"
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " C_BLEND_FACTOR_DST_COLOR_MATCH_SELECT ,C blend factor dst color match select" "0,1,K1,K2,K1_TIMES_DST,NEG_K1_TIMES_DST,NEG_K1_TIMES_SRC,NEG_K1"
|
|
bitfld.long 0x04 0.--2. " C_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT ,C blend factor src color match select" "0,1,K1,K1_TIMES_DST,NEG_K1_TIMES_DST,K1_TIMES_SRC,,"
|
|
line.long 0x08 "BLEND_NOMATCH_SELECT_0,WIN C blend nomatch select 0"
|
|
bitfld.long 0x08 12.--13. " C_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT ,C blend factor dst alpha nomatch select" "0,1,EG_K1_TIMES_SRC,K2"
|
|
bitfld.long 0x08 8.--9. " C_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT ,C blend factor src alpha nomatch select" "0,K1,K2,"
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " C_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT ,C blend factor dst color nomatch select" "0,1,K1,K2,K1_TIMES_DST,NEG_K1_TIMES_DST,NEG_K1_TIMES_SRC,NEG_K1"
|
|
bitfld.long 0x08 0.--2. " C_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT ,C blend factor src color nomatch select" "0,1,K1,K1_TIMES_DST,NEG_K1_TIMES_DST,K1_TIMES_SRC,,"
|
|
line.long 0x0C "BLEND_ALPHA_1BIT_0,DC WIN C BLEND ALPHA 1BIT 0"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " C_BLEND_WEIGHT1 ,Alpha value of 1"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " C_BLEND_WEIGHT0 ,Alpha value of 0"
|
|
tree.end
|
|
width 19.
|
|
tree "WINBUF_C Registers"
|
|
group.long 0x2000++0x27
|
|
line.long 0x00 "START_ADDR_0,Window C Start Address"
|
|
line.long 0x04 "START_ADDR_NS_0,Window C Shadowed Start Address"
|
|
line.long 0x08 "START_ADDR_U_0,Window C Start Address for U plane"
|
|
line.long 0x0C "START_ADDR_U_NS_0,Window C Shadowed Start Address for U plane"
|
|
line.long 0x10 "START_ADDR_V_0,Window C Start Address for V plane"
|
|
line.long 0x14 "START_ADDR_V_NS_0,WWindow C Shadowed Start Address for V plane"
|
|
line.long 0x18 "ADDR_H_OFFSET_0,Window C Horizontal Address Offset"
|
|
line.long 0x1C "ADDR_H_OFFSET_NS_0,Window C Shadowed Horizontal Address Offset"
|
|
line.long 0x20 "ADDR_V_OFFSET_0,Window C Vertical Address Offset"
|
|
line.long 0x24 "ADDR_V_OFFSET_NS_0,Window C Shadowed Vertical Address Offset"
|
|
group.long 0x2028++0x0B
|
|
line.long 0x00 "UFLOW_STATUS,Window C FIFO Underflow Status Register"
|
|
bitfld.long 0x00 30. " COUNT_OFLOW ,Counter has overflowed" "Not occurred,Occurred"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " UFLOW_COUNT ,Underflow count"
|
|
line.long 0x04 "SURFACE_KIND_0,Window C Surface Kind"
|
|
bitfld.long 0x04 4.--6. " C_BLOCK_HEIGHT ,Block Height" "HEIGHT_1,HEIGHT_2,HEIGHT_4,HEIGHT_8,HEIGHT_16,HEIGHT_32,,"
|
|
bitfld.long 0x04 0.--1. " C_SURFACE_KIND ,Surface kind" "PITCH,TILED,BL_16B2,"
|
|
line.long 0x08 "SURFACE_WEIGHT_0,Window C Surface Weights"
|
|
bitfld.long 0x08 5.--6. " C_SURFACE_WEIGHT_V ,Window C V Surface Weights" "2,4,8,16"
|
|
bitfld.long 0x08 3.--4. " C_SURFACE_WEIGHT_U ,Window C U or UV Surface Weights" "2,4,8,16"
|
|
bitfld.long 0x08 1.--2. " C_SURFACE_WEIGHT_Y ,Window C Y or packed Surface Weights" "2,4,8,16"
|
|
textline " "
|
|
bitfld.long 0x08 0. " C_SURFACE_WEIGHT_OVERRIDE ,Weight Override" "Disabled,Enabled"
|
|
textline " "
|
|
width 22.
|
|
group.long 0x2034++0x17
|
|
line.long 0x00 "START_ADDR_HI_0,Window C Higher 2 bits of Start Address"
|
|
bitfld.long 0x00 0.--1. " C_START_ADDR_HI ,Window C Start Address" "0,1,2,3"
|
|
line.long 0x04 "START_ADDR_HI_NS_0,Window C Higher 2 bits of Start Address"
|
|
bitfld.long 0x04 0.--1. " C_START_ADDR_HI_NS ,Window C Shadowed Start Address" "0,1,2,3"
|
|
line.long 0x08 "START_ADDR_HI_U_0,Window C Higher 2 bits of Start Address"
|
|
bitfld.long 0x08 0.--1. " C_START_ADDR_HI ,Window C Start Address" "0,1,2,3"
|
|
line.long 0x0C "START_ADDR_HI_U_NS_0,Window C Shadowed Higher 2 bits of Start Address for U Plane"
|
|
bitfld.long 0x0C 0.--1. " C_START_ADDR_HI_U_NS ,Window C Shadowed Higher 2 bits of Start Address for U plane" "0,1,2,3"
|
|
line.long 0x10 "START_ADDR_HI_V_0,Window C Higher 2 bits of Start Address for V Plane"
|
|
bitfld.long 0x10 0.--1. " C_START_ADDR_HI_V ,Window C Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
line.long 0x14 "START_ADDR_HI_V_NS_0,Window C Shadowed Higher 2 bits of Start Address for V Plane"
|
|
bitfld.long 0x14 0.--1. " C_START_ADDR_HI_V_NS ,Window C Shadowed Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
textline " "
|
|
width 29.
|
|
group.long 0x204C++0x17
|
|
line.long 0x00 "START_ADDR_FIELD2_0,Window C Start Address"
|
|
line.long 0x04 "START_ADDR_FIELD2_NS_0,Window C Shadowed Start Address"
|
|
line.long 0x08 "START_ADDR_FIELD2_U_0,Window C Start Address for U plane"
|
|
line.long 0x0C "START_ADDR_FIELD2_U_NS_0,Window C Shadowed Start Address for U plane"
|
|
line.long 0x10 "START_ADDR_FIELD2_V_0,Window C Start Address for V plane"
|
|
line.long 0x14 "START_ADDR_FIELD2_V_NS_0,Window C Shadowed Start Address for V plane"
|
|
group.long 0x2064++0x17
|
|
line.long 0x00 "START_ADDR_FIELD2_HI_0,Window C Higher 2 bits of Start Address"
|
|
bitfld.long 0x00 0.--1. " C_START_ADDR_FIELD2_HI ,Window C Start Address" "0,1,2,3"
|
|
line.long 0x04 "START_ADDR_FIELD2_HI_NS_0,Window C Shadowed Higher 2 bits of Start Address"
|
|
bitfld.long 0x04 0.--1. " C_START_ADDR_FIELD2_HI_NS ,Window C Shadowed Start Address" "0,1,2,3"
|
|
line.long 0x08 "START_ADDR_FIELD2_HI_U_0,Window C Higher 2 bits of Start Address for U plane"
|
|
bitfld.long 0x08 0.--1. " C_START_ADDR_FIELD2_HI_U ,Window C Start Address for U plane" "0,1,2,3"
|
|
line.long 0x0C "START_ADDR_FIELD2_HI_U_NS_0,Window C Shadowed Higher 32 bits of Start Address for U plane"
|
|
bitfld.long 0x0C 0.--1. " C_START_ADDR_FIELD2_HI_U_NS ,Window C Shadowed Higher 2 bits of Start Address for U plane" "0,1,2,3"
|
|
line.long 0x10 "START_ADDR_FIELD2_HI_V_0,Window C Higher 2 bits of Start Address for V plane"
|
|
bitfld.long 0x10 0.--1. " C_START_ADDR_FIELD2_HI_V ,Window C Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
line.long 0x14 "START_ADDR_FIELD2_HI_V_NS_0,Window C Shadowed Higher 2 bits of Start Address for V plane"
|
|
bitfld.long 0x14 0.--1. " C_START_ADDR_FIELD2_HI_V_NS ,Window C Shadowed Higher 2 bits of Start Address for V plane" "0,1,2,3"
|
|
group.long 0x207C++0x0F
|
|
line.long 0x00 "ADDR_H_OFFSET_FIELD2_0,Window C Horizontal address offset"
|
|
line.long 0x04 "ADDR_H_OFFSET_FIELD2_NS_0,Window C Shadowed Horizontal address offset"
|
|
line.long 0x08 "ADDR_V_OFFSET_FIELD2_0,Window C Vertical address offset"
|
|
line.long 0x0C "ADDR_V_OFFSET_FIELD2_NS_0,Window C Shadowed Vertical address offset"
|
|
group.long 0x2090++0x03
|
|
line.long 0x00 "UFLOW_CTRL_0,DC WINBUF C uflow ctrl 0"
|
|
bitfld.long 0x00 0. " C_UFLOW_CTRL_DBG_MODE ,C uflow ctrl dbg mode" "Disabled,Enabled"
|
|
textline " "
|
|
width 25.
|
|
group.long 0x2094++0x27
|
|
line.long 0x00 "UFLOW_DBG_PIXEL_0,DC WINBUF C uflow dbg pixel 0"
|
|
line.long 0x04 "UFLOW_THRESHOLD_0,DC WINBUF C uflow threshold 0"
|
|
hexmask.long.word 0x04 0.--12. 1. " C_UFLOW_THRESHOLD ,C uflow threshold"
|
|
line.long 0x08 "SPOOL_UP_0,Spool up time configuration for different windows related logic"
|
|
hexmask.long.word 0x08 16.--28. 1. " C_SPOOL_UP_DURATION ,C spool up duration"
|
|
bitfld.long 0x08 1. " C_SPOOL_UP_EDGE ,C spool up edge" "Negedge,Posedge"
|
|
bitfld.long 0x08 0. " C_SPOOL_UP_CTRL ,C spool up ctrl" "Max,Programmable"
|
|
line.long 0x0C "SCALEFACTOR_THRESHOLD_0,DC WINBUF C SCALEFACTOR THRESHOLD 0"
|
|
hexmask.long.word 0x0C 16.--31. 1. " C_SF_LWM_THRESHOLD ,C sf lwm threshold"
|
|
hexmask.long.word 0x0C 0.--15. 1. " C_SF_HWM_THRESHOLD ,C sf hwm threshold"
|
|
line.long 0x10 "LATENCY_THRESHOLD_0,Register controls the behavior of the rdy4_latency_event from the display to the MC"
|
|
bitfld.long 0x10 31. " C_RDY4LATENCY_THRESHOLD_ENABLE ,C RDY4LATENCY THRESHOLD ENABLE" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " C_RDY4LATENCY_SPOOLUP_CTRL ,C RDY4LATENCY spoolup ctrl" "Disallow,Allow"
|
|
textline " "
|
|
hexmask.long.word 0x10 16.--28. 1. " C_RDY4LATENCY_SPOOLUP_DURATION ,C RDY4LATENCY threshold"
|
|
hexmask.long.word 0x10 0.--15. 1. " C_RDY4LATENCY_THRESHOLD ,C RDY4LATENCY threshold"
|
|
line.long 0x14 "MEMFETCH_DEBUG_STATUS_0,Memfetch Debug Status"
|
|
bitfld.long 0x14 16. " C_DEBUG_ENABLE ,Reg to enable FGCG for flops added to debug signals in memfetch" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " C_ALIGN_FIFO_NON_IDLE ,Align FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 13. " C_PIPE0_FIFO_NON_IDLE ,Pipe0 FIFO idle at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 12. " C_FRAME_FIFO_NON_IDLE ,Frame FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 11. " C_SURFACE_FIFO_NON_IDLE ,Surface FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 10. " C_TAG_FIFO_NON_IDLE ,Tag FIFO idle at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 9. " C_RSP_FIFO_NON_IDLE ,Response FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 8. " C_REQ_FIFO_NON_IDLE ,Request FIFO idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 7. " C_DP_VALID_NON_IDLE ,DP lines valid at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 6. " C_V_SSM_NON_IDLE ,V SSM is non-idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 5. " C_U_SSM_NON_IDLE ,U SSM is non-idle at end of frame" "Idle,No Idle"
|
|
bitfld.long 0x14 4. " C_Y_SSM_NON_IDLE ,Y SSM is non-idle at end of frame" "Idle,No Idle"
|
|
textline " "
|
|
bitfld.long 0x14 3. " C_DP_POOL_AVAIL ,DP thinks there is data in the pool at end of frame" "No data,Data"
|
|
bitfld.long 0x14 2. " C_POOL_NOT_EMPTY ,Status of pool at end of frame" "Empty,Not empty"
|
|
bitfld.long 0x14 1. " C_UNDERFLOW_LINE1 ,Underflow of line0" "No underflow,Line0 underflowed"
|
|
textline " "
|
|
bitfld.long 0x14 0. " C_UNDERFLOW_LINE0 ,Underflow of line0" "No underflow,Line0 underflowed"
|
|
line.long 0x18 "MEMFETCH_CONTROL_0,Memfetch Control Register"
|
|
bitfld.long 0x18 1. " C_MEMFETCH_CLK_GATE_OVERRIDE ,Disable clock-gating of memfetch for a controller" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " C_MEMFETCH_RESET ,Reset memfetch for a controller" "Disabled,Enabled"
|
|
line.long 0x1C "OCCUPANCY_THROTTLE_0,DC WINBUF C OCCUPANCY THROTTLE 0"
|
|
hexmask.long.word 0x1C 16.--31. 1. " C_OCCUPANCY_MAX_THRESHOLD ,C occupancy max threshold"
|
|
bitfld.long 0x1C 0. " C_OCCUPANCY_THROTTLE_MODE ,C occupancy throttle mode" "Disabled,Enabled"
|
|
line.long 0x20 "SCRATCH_REGISTER_0_0,DC WINBUF C scratch register 0 0"
|
|
line.long 0x24 "SCRATCH_REGISTER_1_0,DC WINBUF C scratch register 1 0"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "MIPI-DSI Display serial interference"
|
|
base ad:0x54300000
|
|
width 22.
|
|
tree "MIPI-DSI Registers"
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "INCR_SYNCPT_0,DSI_INCR_SYNCPT_0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " COND ,Condition mapped from raise/wait"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INDX ,Syncpt index value"
|
|
line.long 0x04 "INCR_SYNCPT_CNTRL_0,DSI_INCR_SYNCPT_CNTRL_0"
|
|
bitfld.long 0x04 8. " INCR_SYNCPT_NO_STALL ,The client host interface will be stalled when FIFOs are full" "No full,Full"
|
|
bitfld.long 0x04 0. " INCR_SYNCPT_SOFT_RESET ,All internal states of the client syncpt block will be reset" "No reset,Reset"
|
|
line.long 0x08 "INCR_SYNCPT_ERROR_0,DSI_INCR_SYNCPT_ERROR_0"
|
|
sif (cpuis("TEGRAX2"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CTXSW_NEXT_0,Context Switch Register"
|
|
hexmask.long.word 0x00 10.--19. 1. " NEXT_CHANNEL ,Next requested channel"
|
|
hexmask.long.word 0x00 0.--9. 1. " NEXT_CLASS ,Next requested channel"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CTXSW_0,Context Switch Register"
|
|
rbitfld.long 0x00 28.--31. " NEXT_CHANNEL ,Next requested channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 16.--25. 1. " NEXT_CLASS ,Next requested class"
|
|
bitfld.long 0x00 12.--15. " CURR_CHANNEL ,Current working channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AUTO_ACK ,Automatically acknowledge" "Manual,AutoACK"
|
|
hexmask.long.word 0x00 0.--9. 1. " CURR_CLASS ,Current working class"
|
|
endif
|
|
base ad:0x54300000
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RD_DATA_0,DSI Read Return Data"
|
|
group.long 0x28++0x27
|
|
line.long 0x00 "WR_DATA_0,Host FIFO Write Input"
|
|
line.long 0x04 "POWER_CONTROL_0,Display Power Control. DSI Enable"
|
|
bitfld.long 0x04 0. " LEG_DSI_ENABLE ,DSI interface enable" "Disabled,Enabled"
|
|
line.long 0x08 "INT_ENABLE_0,Interrupt Enable Register"
|
|
bitfld.long 0x08 0. " CTXSW_INT_ENABLE ,Context switch interrupt enable" "Disabled,Enabled"
|
|
line.long 0x0C "INT_STATUS_0,Interrupt Status Register"
|
|
eventfld.long 0x0C 0. " CTXSW_INT ,Context switch interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x10 "INT_MASK_0,Interrupt Mask"
|
|
bitfld.long 0x10 0. " CTXSW_INT_MASK ,Context switch interrupt mask" "Masked,Not masked"
|
|
line.long 0x14 "HOST_DSI_CONTROL_0,DSI Control Register When Input Is From HOST"
|
|
bitfld.long 0x14 21. " FIFO_STAT_RESET ,Clear FIFO underflow/overflow flags" "No occurred,Occurred"
|
|
bitfld.long 0x14 20. " CRC_RESET ,CRC generator reset" "No reset,Reset"
|
|
bitfld.long 0x14 16.--18. " DSI_PHY_CLK_DIV ,Phy clock divider value for byte clock" "/1,/2,?..."
|
|
textline " "
|
|
bitfld.long 0x14 12.--13. " HOST_TX_TRIG_SRC ,Source of the trigger" "SOL,FIFO Level,Immediate,?..."
|
|
bitfld.long 0x14 8.--9. " DSI_ULTRA_LOW_POWER ,Ultra low power" "Normal,Enter ULPM,Exit ULPM,?..."
|
|
bitfld.long 0x14 7. " PERIPH_RESET ,Initiate an escape mode peripheral reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 6. " RAW_DATA ,Host raw data mode" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " DSI_HIGH_SPEED_TRANS ,DSI high speed transmission of packets" "Low,High"
|
|
bitfld.long 0x14 4. " PKT_WR_FIFO_SEL ,Host write FIFO select" "Host,Video"
|
|
textline " "
|
|
bitfld.long 0x14 3. " IMM_BTA ,Generate BTA immediately" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " PKT_BTA ,Generate BTA at the end of host packets" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " CS_ENABLE ,Enable hardware check sum for host packets" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " ECC_ENABLE ,Enable hardware error correction code" "Disabled,Enabled"
|
|
line.long 0x18 "CONTROL_0,General DSI Control Register"
|
|
bitfld.long 0x18 31. " DSI_DBG_ENABLE ,Turn off clock monitoring when enabled for debug" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " DFMT_16BPP_SWAP_EN ,16BPP Swap enabled" "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " DSI_HS_CLK_CTRL ,Control for the HS clock lane" "Continuous,TX Only"
|
|
textline " "
|
|
bitfld.long 0x18 16.--17. " DSI_VIRTUAL_CHANNEL ,Virtual channel ID" "0,1,2,3"
|
|
bitfld.long 0x18 12.--13. " DSI_DATA_FORMAT ,Pixel data format transmitted" "BIT16P,BIT18NP,BIT18P,BIT24P"
|
|
bitfld.long 0x18 8.--9. " VID_TX_TRIG_SRC ,Source of the trigger to start sending packets" "SOL,FIFO Level,Immediate,?..."
|
|
textline " "
|
|
bitfld.long 0x18 4.--5. " DSI_NUM_DATA_LANES ,Number of D-PHY data lanes" "1,2,3,4"
|
|
bitfld.long 0x18 3. " VID_DCS_ENABLE ,Enable for insertion of DCS commands" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " DSI_VID_SOURCE ,Source of video pixels" "Display 0,Display 1"
|
|
textline " "
|
|
bitfld.long 0x18 1. " DSI_VID_ENABLE ,Video DSI interface enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " DSI_HOST_ENABLE ,Host DSI interface enable" "Disabled,Enabled"
|
|
line.long 0x1C "SOL_DELAY_0,Number Of Byte-clock Counts To Wait"
|
|
hexmask.long.word 0x1C 0.--15. 1. " SOL_DELAY ,Start of line before generating output packets"
|
|
line.long 0x20 "MAX_THRESHOLD_0,Maximum Threshold Registers For DSI Related Packets"
|
|
hexmask.long.word 0x20 0.--15. 1. " MAX_THRESHOLD ,Start draining FIFO once this threshold is met"
|
|
line.long 0x24 "TRIGGER_0,Manual Transmissions Trigger Register"
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x24 2. " SKEWCAL_TRIGGER ,SKEWCAL trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x24 1. " DSI_HOST_TRIGGER ,DSI Host trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 0. " DSI_VID_TRIGGER ,DSI VID trigger" "Not triggered,Triggered"
|
|
rgroup.long 0x50++0x07
|
|
line.long 0x00 "TX_CRC_0,Transmission CRC"
|
|
line.long 0x04 "STATUS_0,DSI Status Register"
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x04 13. " DSI_CLOCK_LANE_IDLE ,DSI clock lane" "Busy,Idle"
|
|
bitfld.long 0x04 12. " HRD_FIFO_UNDERFLOW ,Host read data FIFO underflow event occurred" "No underflow,Underflow"
|
|
bitfld.long 0x04 11. " HRD_FIFO_OVERFLOW ,Host read data FIFO overflow event occurred" "No overflow,overflow"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 10. " DSI_IDLE ,DSI is IDLE" "Busy,Idle"
|
|
bitfld.long 0x04 9. " LB_UNDERFLOW ,Line buffer underflow event happened" "No underflow,Underflow"
|
|
bitfld.long 0x04 8. " LB_OVERFLOW ,Line buffer overflow event happened" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " RD_FIFO_COUNT ,Data words left in the host read data return FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif (cpuis("TEGRAX2"))
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DSI_VID_BTA_CONTROL_0,DSI BTA Operation In Video/DCS Mode Control Register"
|
|
bitfld.long 0x00 1.--3. " BTA_VID_LINE_TYPE ,Blank Line type on which BTA operation is to be performed in video/DCS mode" "Type 0,Type 1,Type 2,Type 3,Type 4,Type 5,?..."
|
|
bitfld.long 0x00 0. " BTA_VID_MODE ,Configuration bit to choose if BTA operation has to be done for every frame until disabled (or) only once when triggered" "One time,Continuous"
|
|
endif
|
|
tree.end
|
|
width 20.
|
|
tree "Initialization Sequence Registers"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "INIT_SEQ_CONTROL_0,DSI Initialization Sequence Control"
|
|
sif (cpuis("TEGRAX1"))
|
|
hexmask.long.byte 0x00 8.--14. 1. " DSI_FRAME_INIT_BYTE_COUNT ,Frame initialization sequence byte count"
|
|
elif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24. " DSI_INIT_SEQ_MODE ,Configuration bit to choose if init sequence" "Continuous,Once"
|
|
hexmask.long.byte 0x00 8.--14. 1. " DSI_FRAME_INIT_BYTE_COUNT ,Frame initialization sequence byte count"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--13. " DSI_FRAME_INIT_BYTE_COUNT ,Frame initialization sequence byte count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
bitfld.long 0x00 0. " DSI_SEND_INIT_SEQUENCE ,Send initialization sequence" "Disabled,Enabled"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "INIT_SEQ_DATA_0_0,DSI Init Sequence Write Data 0"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "INIT_SEQ_DATA_1_0,DSI Init Sequence Write Data 1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "INIT_SEQ_DATA_2_0,DSI Init Sequence Write Data 2"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "INIT_SEQ_DATA_3_0,DSI Init Sequence Write Data 3"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "INIT_SEQ_DATA_4_0,DSI Init Sequence Write Data 4"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "INIT_SEQ_DATA_5_0,DSI Init Sequence Write Data 5"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "INIT_SEQ_DATA_6_0,DSI Init Sequence Write Data 6"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "INIT_SEQ_DATA_7_0,DSI Init Sequence Write Data 7"
|
|
tree.end
|
|
width 16.
|
|
tree "Packet Sequence Registers"
|
|
group.long 0x8C++0x07
|
|
line.long 0x00 "PKT_SEQ_0_LO_0,DSI Packet Sequence 0 LO Half"
|
|
bitfld.long 0x00 30. " SEQ_0_FORCE_LP ,Force the D-PHY to go to LP mode after the last packet of the sequence" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PKT_02_EN ,Packet 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23.--28. " PKT_02_ID ,Packet 2 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--22. " PKT_02_SIZE ,Packet 2 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PKT_01_EN ,Packet 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--18. " PKT_01_ID ,Packet 1 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 10.--12. " PKT_01_SIZE ,Packet 1 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PKT_00_EN ,Packet 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--8. " PKT_00_ID ,Packet 0 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--2. " PKT_00_SIZE ,Packet 0 size pointer" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "PKT_SEQ_0_HI_0,DSI Packet Sequence 0 HI Half"
|
|
bitfld.long 0x04 29. " PKT_05_EN ,Packet 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23.--28. " PKT_05_ID ,Packet 5 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 20.--22. " PKT_05_SIZE ,Packet 5 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PKT_04_EN ,Packet 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13.--18. " PKT_04_ID ,Packet 4 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 10.--12. " PKT_04_SIZE ,Packet 4 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PKT_03_EN ,Packet 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--8. " PKT_03_ID ,Packet 3 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 0.--2. " PKT_03_SIZE ,Packet 3 size pointer" "0,1,2,3,4,5,6,7"
|
|
group.long 0x94++0x07
|
|
line.long 0x00 "PKT_SEQ_1_LO_0,DSI Packet Sequence 1 LO Half"
|
|
bitfld.long 0x00 30. " SEQ_1_FORCE_LP ,Force the D-PHY to go to LP mode after the last packet of the sequence" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PKT_12_EN ,Packet 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23.--28. " PKT_12_ID ,Packet 2 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--22. " PKT_12_SIZE ,Packet 2 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PKT_11_EN ,Packet 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--18. " PKT_11_ID ,Packet 1 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 10.--12. " PKT_11_SIZE ,Packet 1 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PKT_10_EN ,Packet 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--8. " PKT_10_ID ,Packet 0 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--2. " PKT_10_SIZE ,Packet 0 size pointer" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "PKT_SEQ_1_HI_0,DSI Packet Sequence 1 HI Half"
|
|
bitfld.long 0x04 29. " PKT_15_EN ,Packet 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23.--28. " PKT_15_ID ,Packet 5 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 20.--22. " PKT_15_SIZE ,Packet 5 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PKT_14_EN ,Packet 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13.--18. " PKT_14_ID ,Packet 4 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 10.--12. " PKT_14_SIZE ,Packet 4 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PKT_13_EN ,Packet 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--8. " PKT_13_ID ,Packet 3 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 0.--2. " PKT_13_SIZE ,Packet 3 size pointer" "0,1,2,3,4,5,6,7"
|
|
group.long 0x9C++0x07
|
|
line.long 0x00 "PKT_SEQ_2_LO_0,DSI Packet Sequence 2 LO Half"
|
|
bitfld.long 0x00 30. " SEQ_2_FORCE_LP ,Force the D-PHY to go to LP mode after the last packet of the sequence" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PKT_22_EN ,Packet 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23.--28. " PKT_22_ID ,Packet 2 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--22. " PKT_22_SIZE ,Packet 2 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PKT_21_EN ,Packet 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--18. " PKT_21_ID ,Packet 1 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 10.--12. " PKT_21_SIZE ,Packet 1 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PKT_20_EN ,Packet 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--8. " PKT_20_ID ,Packet 0 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--2. " PKT_20_SIZE ,Packet 0 size pointer" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "PKT_SEQ_2_HI_0,DSI Packet Sequence 2 HI Half"
|
|
bitfld.long 0x04 29. " PKT_25_EN ,Packet 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23.--28. " PKT_25_ID ,Packet 5 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 20.--22. " PKT_25_SIZE ,Packet 5 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PKT_24_EN ,Packet 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13.--18. " PKT_24_ID ,Packet 4 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 10.--12. " PKT_24_SIZE ,Packet 4 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PKT_23_EN ,Packet 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--8. " PKT_23_ID ,Packet 3 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 0.--2. " PKT_23_SIZE ,Packet 3 size pointer" "0,1,2,3,4,5,6,7"
|
|
group.long 0xA4++0x07
|
|
line.long 0x00 "PKT_SEQ_3_LO_0,DSI Packet Sequence 3 LO Half"
|
|
bitfld.long 0x00 30. " SEQ_3_FORCE_LP ,Force the D-PHY to go to LP mode after the last packet of the sequence" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PKT_32_EN ,Packet 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23.--28. " PKT_32_ID ,Packet 2 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--22. " PKT_32_SIZE ,Packet 2 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PKT_31_EN ,Packet 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--18. " PKT_31_ID ,Packet 1 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 10.--12. " PKT_31_SIZE ,Packet 1 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PKT_30_EN ,Packet 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--8. " PKT_30_ID ,Packet 0 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--2. " PKT_30_SIZE ,Packet 0 size pointer" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "PKT_SEQ_3_HI_0,DSI Packet Sequence 3 HI Half"
|
|
bitfld.long 0x04 29. " PKT_35_EN ,Packet 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23.--28. " PKT_35_ID ,Packet 5 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 20.--22. " PKT_35_SIZE ,Packet 5 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PKT_34_EN ,Packet 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13.--18. " PKT_34_ID ,Packet 4 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 10.--12. " PKT_34_SIZE ,Packet 4 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PKT_33_EN ,Packet 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--8. " PKT_33_ID ,Packet 3 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 0.--2. " PKT_33_SIZE ,Packet 3 size pointer" "0,1,2,3,4,5,6,7"
|
|
group.long 0xAC++0x07
|
|
line.long 0x00 "PKT_SEQ_4_LO_0,DSI Packet Sequence 4 LO Half"
|
|
bitfld.long 0x00 30. " SEQ_4_FORCE_LP ,Force the D-PHY to go to LP mode after the last packet of the sequence" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PKT_42_EN ,Packet 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23.--28. " PKT_42_ID ,Packet 2 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--22. " PKT_42_SIZE ,Packet 2 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PKT_41_EN ,Packet 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--18. " PKT_41_ID ,Packet 1 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 10.--12. " PKT_41_SIZE ,Packet 1 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PKT_40_EN ,Packet 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--8. " PKT_40_ID ,Packet 0 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--2. " PKT_40_SIZE ,Packet 0 size pointer" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "PKT_SEQ_4_HI_0,DSI Packet Sequence 4 HI Half"
|
|
bitfld.long 0x04 29. " PKT_45_EN ,Packet 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23.--28. " PKT_45_ID ,Packet 5 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 20.--22. " PKT_45_SIZE ,Packet 5 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PKT_44_EN ,Packet 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13.--18. " PKT_44_ID ,Packet 4 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 10.--12. " PKT_44_SIZE ,Packet 4 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PKT_43_EN ,Packet 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--8. " PKT_43_ID ,Packet 3 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 0.--2. " PKT_43_SIZE ,Packet 3 size pointer" "0,1,2,3,4,5,6,7"
|
|
group.long 0xB4++0x07
|
|
line.long 0x00 "PKT_SEQ_5_LO_0,DSI Packet Sequence 5 LO Half"
|
|
bitfld.long 0x00 30. " SEQ_5_FORCE_LP ,Force the D-PHY to go to LP mode after the last packet of the sequence" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PKT_52_EN ,Packet 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23.--28. " PKT_52_ID ,Packet 2 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--22. " PKT_52_SIZE ,Packet 2 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PKT_51_EN ,Packet 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--18. " PKT_51_ID ,Packet 1 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 10.--12. " PKT_51_SIZE ,Packet 1 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PKT_50_EN ,Packet 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--8. " PKT_50_ID ,Packet 0 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--2. " PKT_50_SIZE ,Packet 0 size pointer" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "PKT_SEQ_5_HI_0,DSI Packet Sequence 5 HI Half"
|
|
bitfld.long 0x04 29. " PKT_55_EN ,Packet 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23.--28. " PKT_55_ID ,Packet 5 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 20.--22. " PKT_55_SIZE ,Packet 5 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PKT_54_EN ,Packet 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13.--18. " PKT_54_ID ,Packet 4 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 10.--12. " PKT_54_SIZE ,Packet 4 size pointer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 9. " PKT_53_EN ,Packet 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3.--8. " PKT_53_ID ,Packet 3 Packet ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 0.--2. " PKT_53_SIZE ,Packet 3 size pointer" "0,1,2,3,4,5,6,7"
|
|
tree.end
|
|
tree "DCS Command and Packet Length Registers"
|
|
group.long 0xCC++0x13
|
|
line.long 0x00 "DCS_CMDS_0,DCS Command IDs Used For Line Types 3 And 5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " LT5_DCS_CMD ,DCS command for line type 5"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LT3_DCS_CMD ,DCS command for line type 3"
|
|
line.long 0x04 "PKT_LEN_0_1_0,DSI Packet Lengths 0 And 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " LENGTH_1 ,Packet length 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " LENGTH_0 ,Packet length 0"
|
|
line.long 0x08 "PKT_LEN_2_3_0,DSI Packet Lengths 2 And 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " LENGTH_3 ,Packet length 3"
|
|
hexmask.long.word 0x08 0.--15. 1. " LENGTH_2 ,Packet length 2"
|
|
line.long 0x0C "KT_LEN_4_5_0,DSI Packet Lengths 4 And 5"
|
|
hexmask.long.word 0x0C 16.--31. 1. " LENGTH_5 ,Packet length 5"
|
|
hexmask.long.word 0x0C 0.--15. 1. " LENGTH_4 ,Packet length 4"
|
|
line.long 0x10 "PKT_LEN_6_7_0,DSI Packet Lengths 6 And 7"
|
|
hexmask.long.word 0x10 16.--31. 1. " LENGTH_7 ,Packet length 7"
|
|
hexmask.long.word 0x10 0.--15. 1. " LENGTH_6 ,Packet length 6"
|
|
tree.end
|
|
tree "Physical Interface Timing Registers"
|
|
group.long 0xF0++0x0F
|
|
line.long 0x00 "PHY_TIMING_0_0,DSI D-PHY Timing Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DSI_THSDEXIT ,Time to drive LP11 after HS"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DSI_THSTRAIL ,Time to drive HS flipped bit at EOT"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DSI_TDATZERO ,Time to drive HS0 before SOT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DSI_THSPREPR ,Time to drive LP00 before HS data"
|
|
line.long 0x04 "PHY_TIMING_1_0,DSI D-PHY Timing Register 1"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DSI_TCLKTRAIL ,Time to drive HS0 before clock goes to LP11"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DSI_TCLKPOST ,Time to drive clock after the last HS data"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DSI_TCLKZERO ,Time to drive LP00 before HS clock"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DSI_TTLPX ,LP period"
|
|
line.long 0x08 "PHY_TIMING_2_0,DSI D-PHY Timing Register 2"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DSI_TCLKPREPARE ,Time to drive LP0 before CLK_ZERO starts off on clock lane"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DSI_TCLKPRE ,Time to run clock before enabling data lane"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DSI_TWAKEUP ,LP period"
|
|
line.long 0x0C "BTA_TIMING_0,DSI D-PHY Bus-Turn-Around Timing"
|
|
sif (CPUIS("TEGRAX1"))
|
|
hexmask.long.byte 0x0C 24.--31. 1. " DSI_TPKTBTA ,Time delay between end of host packet transmission and generation of PKT BTA"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x0C 16.--23. 1. " DSI_TTAGET ,Time to drive LP00 at end of BTA"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " DSI_TTASURE ,Time to receive LP00 at end of BTA"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " DSI_TTAGO ,Time to drive LP00 at start of BTA"
|
|
tree.end
|
|
tree "Contention Recovery Timers"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TIMEOUT_0_0,DSI Time Out Terminal Count Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " LRXH_TO ,Low power receive time out terminal count"
|
|
hexmask.long.word 0x00 0.--15. 1. " HTX_TO ,High speed transmit time out terminal count"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TIMEOUT_1_0,DSI Time Out Terminal Count Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " PR_TO ,Peripheral reset duration"
|
|
hexmask.long.word 0x00 0.--15. 1. " TA_TO ,Turn around time out terminal count"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TO_TALLY_0,DSI Time Out Tally Register"
|
|
rbitfld.long 0x00 24. " P_RESET_STATUS ,Peripheral reset time out status" "In reset,Ready"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TA_TALLY ,Turn around time out tally"
|
|
hexmask.long.byte 0x00 8.--15. 1. " LRXH_TALLY ,LP Rx time out tally"
|
|
hexmask.long.byte 0x00 0.--7. 1. " HTX_TALLY ,HS Tx time out tally"
|
|
tree.end
|
|
width 23.
|
|
tree "Physical Pad Control Registers"
|
|
group.long 0x12C++0x07
|
|
line.long 0x00 "PAD_CONTROL_0,DSI PHY Configuration Register"
|
|
bitfld.long 0x00 24. " DSI_PAD_PULLDN_CLK_ENAB ,Enable pad pulldown for clock bit at power on" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " DSI_PAD_PULLDN_ENAB ,Pad pulldown on power on" "Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 8. " DSI_PAD_PDIO_CLK ,Power down for clock bit, drivers, receivers and contention detectors" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DSI_PAD_PDIO ,Power down for data bit,drivers,receivers and contention detectors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "PAD_CONTROL_CD_0,Contention Detection Logic Enable Signals"
|
|
bitfld.long 0x04 16.--18. " DSI_PAD_CDDNADJ ,Level adjust on low limit of detection" "0.3V,0.375V,0.45V,0.525V,0.3V,0.225V,0.15V,0.075V"
|
|
bitfld.long 0x04 8. " DSI_PAD_CD_EN_CLK ,Clock bit contention detector enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--3. " DSI_PAD_CD_EN ,Data bits contention detector enable" "Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "PAD_CD_STATUS_0,Contention Detection Status From MIPI PAD"
|
|
bitfld.long 0x00 18. " DSI_PAD_CDN_CLK ,DSI PAD CDN CLK" "0,1"
|
|
bitfld.long 0x00 16. " DSI_PAD_CDP_CLK ,DSI PAD CDP CLK" "0,1"
|
|
bitfld.long 0x00 8.--11. " DSI_PAD_CDN ,DSI PAD CDN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DSI_PAD_CDP ,DSI PAD CDP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x138++0x17
|
|
line.long 0x00 "VID_MODE_CONTROL_0,Host Command Packet During Video Mode"
|
|
bitfld.long 0x00 1.--3. " DSI_LINE_TYPE ,LINE TYPE on which host command packet to be transmitted" "Line type 0,Line type 1,Line type 2,,Line type 4,?..."
|
|
bitfld.long 0x00 0. " DSI_CMD_PKT_VID_ENABLE ,Host command packet during video mode" "Disabled,Enabled"
|
|
line.long 0x04 "PAD_CONTROL_1_0,DSI PHY Configuration Register 1"
|
|
bitfld.long 0x04 12.--14. " DSI_PAD_OUTADJ3 ,Input delay trimmer for data bit 3" "0 ps,40 ps,80 ps,120 ps,160 ps,200 ps,240 ps,280 ps"
|
|
bitfld.long 0x04 8.--10. " DSI_PAD_OUTADJ2 ,Input delay trimmer for data bit 2" "0 ps,40 ps,80 ps,120 ps,160 ps,200 ps,240 ps,280 ps"
|
|
bitfld.long 0x04 4.--6. " DSI_PAD_OUTADJ1 ,Input delay trimmer for data bit 1" "0 ps,40 ps,80 ps,120 ps,160 ps,200 ps,240 ps,280 ps"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " DSI_PAD_OUTADJ0 ,Input delay trimmer for data bit 0" "0 ps,40 ps,80 ps,120 ps,160 ps,200 ps,240 ps,280 ps"
|
|
line.long 0x08 "PAD_CONTROL_2_0,DSI PHY Configuration Register 2"
|
|
bitfld.long 0x08 16.--18. " DSI_PAD_SLEWUPADJ ,Pull-up slew rate adjust" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 12.--14. " DSI_PAD_SLEWDNADJ ,Pull-down slew rate adjust" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 8.--10. " DSI_PAD_LPUPADJ ,Driver pull-up impedance control" "130 ohm,110 ohm,130 ohm,150 ohm,?..."
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " DSI_PAD_LPDNADJ ,Input delay trimmer for data bit 0" "130ohm,110ohm,130ohm,150ohm,?..."
|
|
bitfld.long 0x08 0.--2. " DSI_PAD_OUTADJCLK ,Output trimmer delay for clock bit" "0 ps,40 ps,80 ps,120 ps,160 ps,200 ps,240 ps,280 ps"
|
|
line.long 0x0C "PAD_CONTROL_3_0,DSI PHY Configuration Register 3"
|
|
bitfld.long 0x0C 28. " DSI_PAD_PDVCLAMP ,Power down regulator" "Power Up,Power down"
|
|
bitfld.long 0x0C 16. " DSI_PAD_BANDWD_IN ,Increase bandwidth of differential receiver" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12.--13. " DSI_PAD_PREEMP_PD_CLK ,Clock bit HS driver pull down pre-emphasis" "No preemphasis,,,Maximum"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--9. " DSI_PAD_PREEMP_PU_CLK ,Clock bit HS driver pull up pre-emphasis" "No preemphasis,,,Maximum"
|
|
bitfld.long 0x0C 4.--5. " DSI_PAD_PREEMP_PD ,Clock bit HS driver pull down pre-emphasis" "No preemphasis,,,Maximum"
|
|
bitfld.long 0x0C 0.--1. " DSI_PAD_PREEMP_PU ,Clock bit HS driver pull up pre-emphasis" "No preemphasis,,,Maximum"
|
|
line.long 0x10 "PAD_CONTROL_4_0,DSI PHY Configuration Register 4"
|
|
bitfld.long 0x10 28. " DSI_PAD_HS_BSO_CLK ,Enables BIAS and power regulators on for HS mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 20.--23. " DSI_PAD_HS_BSO ,Enables BIAS and power regulators on for HS mode" "Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x10 16. " DSI_PAD_LP_BSO_CLK ,Enables BIAS and power regulators on for LP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " DSI_PAD_LP_BSO ,Enables BIAS and power regulators on for LP mode" "Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x10 4. " DSI_PAD_TXBW_EN ,Increase bandwidth of output driver" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DSI_PAD_REV_CLK ,Reverse clock polarity" "Not reversed,Reversed"
|
|
line.long 0x14 "GANGED_MODE_CONTROL_0,Mode Control Register 0"
|
|
sif (cpuis("TEGRAX1"))
|
|
bitfld.long 0x14 1.--2. " DUMMY_PIX_LEFT_RIGHT_SIDE ,Dummy pixels side" "Normal,Left,Right,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 0. " DSI_GANGED_MODE_EN ,Ganged mode transaction enabled" "Disabled,Enabled"
|
|
textline " "
|
|
width 27.
|
|
group.long 0x150++0x0F
|
|
line.long 0x00 "GANGED_MODE_START_0,Mode Start Register 0"
|
|
hexmask.long.word 0x00 0.--12. 1. " DSI_GANGED_START_POINTER ,Start pointer for indicating the start of partial active valid pixel data"
|
|
line.long 0x04 "GANGED_MODE_SIZE_0,Mode Size Register 0"
|
|
hexmask.long.word 0x04 16.--28. 1. " DSI_GANGED_VALID_LOW_WIDTH ,Width of partial inactive/ignored pixel data from the valid pixels"
|
|
hexmask.long.word 0x04 0.--12. 1. " DSI_GANGED_VALID_HIGH_WIDTH ,Width of partial active valid pixel data latched from the valid pixels"
|
|
line.long 0x08 "RAW_DATA_BYTE_COUNT_0,Raw Data Counter Register 0"
|
|
hexmask.long.word 0x08 0.--15. 1. " DSI_RAW_DATA_BYTE_COUNT ,Host RAW DATA byte count specifies the total number of bytes to send"
|
|
line.long 0x0C "ULTRA_LOW_POWER_CONTROL_0,Ultra Low Power Sequence Control Register 0"
|
|
bitfld.long 0x0C 8.--9. " DSI_ULTRA_LOW_POWER_DATA_LANE3 ,Ultra low power" "Normal,Enter ULPM,Exit ULPM,?..."
|
|
bitfld.long 0x0C 6.--7. " DSI_ULTRA_LOW_POWER_DATA_LANE2 ,Ultra low power" "Normal,Enter ULPM,Exit ULPM,?..."
|
|
bitfld.long 0x0C 4.--5. " DSI_ULTRA_LOW_POWER_DATA_LANE1 ,Ultra low power" "Normal,Enter ULPM,Exit ULPM,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " DSI_ULTRA_LOW_POWER_DATA_LANE0 ,Ultra low power" "Normal,Enter ULPM,Exit ULPM,?..."
|
|
bitfld.long 0x0C 0.--1. " DSI_ULTRA_LOW_POWER_CLK_LANE ,Ultra low power" "Normal,Enter ULPM,Exit ULPM,?..."
|
|
textline " "
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "INIT_SEQ_DATA_8_0,DSI Init Sequence Write Data 8"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "INIT_SEQ_DATA_9_0,DSI Init Sequence Write Data 9"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "INIT_SEQ_DATA_10_0,DSI Init Sequence Write Data 10"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "INIT_SEQ_DATA_11_0,DSI Init Sequence Write Data 11"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "INIT_SEQ_DATA_12_0,DSI Init Sequence Write Data 12"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "INIT_SEQ_DATA_13_0,DSI Init Sequence Write Data 13"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "INIT_SEQ_DATA_14_0,DSI Init Sequence Write Data 14"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "INIT_SEQ_DATA_15_0,DSI Init Sequence Write Data 15"
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
textline " "
|
|
group.long 0x180++0x07
|
|
line.long 0x00 "DUMMY_PIX_CNT_0,Dummy Pixel Count Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RIGHT_DUMMY_PIX_CNT ,Number of dummy pixels padded to the right of active pixel stream"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LEFT_DUMMY_PIX_CNT ,Number of dummy pixels padded to the left of active pixel stream"
|
|
line.long 0x04 "DSI_DSC_CONTROL_0,Display Stream Compression Control Register"
|
|
bitfld.long 0x04 16.--17. " NUM_COMPRESS_PKTS_PER_ROW ,Number of compressed image packets per row between two sync events" "1,2,,4"
|
|
hexmask.long.word 0x04 2.--11. 1. " COMPRESS_RATE ,Compression bit rate"
|
|
bitfld.long 0x04 0. " COMPRESS_MODE_EN ,Compressed bit stream transport mode enable" "Disabled,Enabled"
|
|
sif (cpuis("TEGRAX2"))
|
|
group.long 0x18C++0x0B
|
|
line.long 0x00 "DSI_LANE_XBAR_CTRL_0,DSI Lane Control Register"
|
|
bitfld.long 0x00 17.--18. " DATA_LANE3_XSEL ,Lane3 selection" "Lane 0,Lane 1,Lane 2,Lane 3"
|
|
bitfld.long 0x00 14.--15. " DATA_LANE2_XSEL ,Lane2 selection" "Lane 0,Lane 1,Lane 2,Lane 3"
|
|
bitfld.long 0x00 11.--12. " DATA_LANE1_XSEL ,Lane1 selection" "Lane 0,Lane 1,Lane 2,Lane 3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " DATA_LANE0_XSEL ,Lane0 selection" "Lane 0,Lane 1,Lane 2,Lane 3"
|
|
bitfld.long 0x00 4. " DATA_LANE3_POLARITY ,Swaps P/N pins polarity of data lane-3" "Normal,Reversed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA_LANE2_POLARITY ,Swaps P/N pins polarity of data lane-2" "Normal,Reversed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DATA_LANE1_POLARITY ,Swaps P/N pins polarity of data lane-1" "Normal,Reversed"
|
|
bitfld.long 0x00 1. " DATA_LANE0_POLARITY ,Swaps P/N pins polarity of data lane-0" "Normal,Reversed"
|
|
bitfld.long 0x00 0. " CLOCK_LANE_POLARITY ,Swaps P/N pins polarity of clock lane" "Normal,Reversed"
|
|
line.long 0x04 "DSI_SKEWCAL_CTRL_0,DSI Deskew Calibration Control Register"
|
|
bitfld.long 0x04 6. " SKEWCAL_SYNCPT_ENABLE ,Syncpt Enable for Skew calibration operation" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " SKEWCAL_CRC_ENABLE ,CRC Enable for Skew calibrating data pattern too along with other DSI packets" "Disabled,Enabled"
|
|
bitfld.long 0x04 2.--4. " SKEWCAL_LINE_TYPE ,Line type selection for Skew calibration" "Line 0,Line 1,Line 2,,Line 4,?..."
|
|
textline " "
|
|
bitfld.long 0x04 1. " SKEWCAL_MODE ,Skew Calibration Mode" "Non-continuous,Continuous"
|
|
bitfld.long 0x04 0. " SKEWCAL_ENABLE ,Skew calibration enable" "Disabled,Enabled"
|
|
line.long 0x08 "DSI_SKEWCAL_TIMING_0,DSI Deskew Calibration Duration Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " SKEWCAL_TIME ,Time that DSI drives the skew calibration data pattern"
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "High-Definition Multimedia Interface (HDMI)"
|
|
base ad:0x54280000
|
|
width 38.
|
|
tree "HDMI Registers"
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "HDMI_CTXSW,Channel IDs"
|
|
bitfld.long 0x00 28.--31. " NEXT_CHANNEL , Next requested channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 16.--25. 1. " NEXT_CLASS , Next requested class"
|
|
bitfld.long 0x00 12.--15. " CURR_CHANNEL , Current working channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. " AUTO_ACK ,Automatically acknowledge any incoming context switch requests" "MANUAL,AUTOACK"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " CURR_CLASS ,Current working class"
|
|
line.long 0x04 "SOR_STATE0,SOR_STATE0_0"
|
|
bitfld.long 0x04 0. " UPDATE ,Writing a 1 to this field causes a 1-cycle pulse" "No effect,Update"
|
|
line.long 0x08 "SOR_STATE1,SOR_STATE1_0"
|
|
bitfld.long 0x08 4. " ARM_SHOW_VGA ,ARM_SHOW_VGA" "No,Yes"
|
|
bitfld.long 0x08 3. " ATTACHED ,ATTACHED" "No,Yes"
|
|
bitfld.long 0x08 2. " ASY_ORMODE ,ASY_ORMODE" "Safe,Normal"
|
|
bitfld.long 0x08 0.--1. " ASY_HEAD_OPMODE ,ASY_HEAD_OPMODE" "SLEEP,SNOOZE,AWAKE,?..."
|
|
line.long 0x0C "SOR_STATE2,SOR_STATE2_0"
|
|
bitfld.long 0x0C 14. " ASY_DEPOL ,ASY_DEPOL" "POSITIVE_TRUE,NEGATIVE_TRUE"
|
|
bitfld.long 0x0C 13. " ASY_VSYNCPOL , VSYNCPOL depends on the video mode" "POSITIVE_TRUE,NEGATIVE_TRUE"
|
|
bitfld.long 0x0C 12. " ASY_HSYNCPOL , HSYNCPOL depends on the video mode" "POSITIVE_TRUE,NEGATIVE_TRUE"
|
|
bitfld.long 0x0C 8.--11. " ASY_PROTOCOL ,ASY_PROTOCOL" ",SINGLE_TMDS_A,,,,,,,,,,,,,,CUSTOM"
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " ASY_CRCMODE , ASY_CRCMODE" "ACTIVE_RASTER,COMPLETE_RASTER,NON_ACTIVE_RASTER,?..."
|
|
bitfld.long 0x0C 4.--5. " ASY_SUBOWNER , ASY_SUBOWNER" "NONE,SUBHEAD0,SUBHEAD1,BOTH"
|
|
bitfld.long 0x0C 0.--3. " ASY_OWNER ,ASY_OWNER" "NONE,HEAD0,?..."
|
|
textline " "
|
|
wgroup.long 0x68++0x03
|
|
line.long 0x00 "HDMI_AUDIO_EMU0,HDMI_AUDIO_EMU: Program the S/PDIF transmitter during RTL simulation and emulation"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "HDMI_AUDIO_EMU_RDATA0,HDMI_AUDIO_EMU_RDATA0_0"
|
|
group.long 0x70++0x0B
|
|
line.long 0x00 "HDMI_AUDIO_EMU1,Control over S/PDIF transmitter clock ratios (Address)"
|
|
bitfld.long 0x00 31. " WRITE ,Enable writing data" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ADDR ,Address"
|
|
line.long 0x04 "HDMI_AUDIO_EMU2,Control over S/PDIF transmitter clock ratios (Data)"
|
|
line.long 0x08 "HDMI_AUDIO_INFOFRAME_CTRL,Controls the frequency and generation of audio InfoFrame packets"
|
|
bitfld.long 0x08 9. " CHKSUM_HW , Hardware provides a way to calculate the checksum for the InfoFrames" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " SINGLE ,Cause InfoFrame to be transmitted exactly once" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " OTHER ,Cause InfoFrame to be transmitted to every other frame" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " ENABLE ,Enable frame generation at the beginning of the next frame" "Disabled,Enabled"
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "HDMI_AUDIO_INFOFRAME_STATUS,HDMI_AUDIO_INFOFRAME_STATUS"
|
|
bitfld.long 0x00 0. " SENT ,Packet is sent" "WAITING,DONE"
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "HDMI_AUDIO_INFOFRAME_HEADER,HDMI Audio InfoFrame header"
|
|
hexmask.long.byte 0x00 16.--23. 1. " HB2 ,Header Byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HB1 ,Header Byte 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " HB0 ,Header Byte 0"
|
|
line.long 0x04 "HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW,Lower 4 bytes of the HDMI Audio InfoFrame"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PB3 ,HDMI Audio InfoFrame Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PB2 ,HDMI Audio InfoFrame Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " PB1 ,HDMI Audio InfoFrame Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PB0 ,HDMI Audio InfoFrame Byte 0"
|
|
line.long 0x08 "HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH,Upper 2 bytes of the HDMI Audio InfoFrame"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PB5 ,HDMI Audio InfoFrame Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PB4 ,HDMI Audio InfoFrame Byte 4"
|
|
textline " "
|
|
line.long 0x0C "HDMI_AVI_INFOFRAME_CTRL,Frequency and generation of AVI InfoFrame packets"
|
|
bitfld.long 0x0C 9. " CHKSUM_HW , Hardware provides a way to calculate the checksum for the InfoFrames" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " SINGLE ,Cause InfoFrame to be transmitted exactly once" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " OTHER ,Cause InfoFrame to be transmitted to every other frame" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " ENABLE ,Enable frame generation at the beginning of the next frame" "Disabled,Enabled"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "HDMI_AVI_INFOFRAME_STATUS,HDMI_AVI_INFOFRAME_STATUS"
|
|
bitfld.long 0x00 0. " SENT ,Packet is sent" "WAITING,DONE"
|
|
group.long 0x94++0x17
|
|
line.long 0x00 "HDMI_AVI_INFOFRAME_HEADER,HDMI AVI InfoFrame header"
|
|
hexmask.long.byte 0x00 16.--23. 1. " HB2 ,Header Byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HB1 ,Header Byte 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " HB0 ,Header Byte 0"
|
|
line.long 0x04 "HDMI_AVI_INFOFRAME_SUBPACK0_LOW,Bytes 0-3 of the HDMI AVI InfoFrame"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PB3 ,HDMI Audio InfoFrame Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PB2 ,HDMI Audio InfoFrame Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " PB1 ,HDMI Audio InfoFrame Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PB0 ,HDMI Audio InfoFrame Byte 0"
|
|
line.long 0x08 "HDMI_AVI_INFOFRAME_SUBPACK0_HIGH,bytes 4-6 of the HDMI AVI InfoFrame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " PB6 ,HDMI Audio InfoFrame Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PB5 ,HDMI Audio InfoFrame Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PB4 ,HDMI Audio InfoFrame Byte 4"
|
|
line.long 0x0C "HDMI_AVI_INFOFRAME_SUBPACK1_LOW,Bytes 7-10 of the HDMI AVI InfoFrame"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " PB10 ,HDMI Audio InfoFrame Byte 10"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " PB9 ,HDMI Audio InfoFrame Byte 9"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " PB8 ,HDMI Audio InfoFrame Byte 8"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PB7 ,HDMI Audio InfoFrame Byte 7"
|
|
line.long 0x10 "HDMI_AVI_INFOFRAME_SUBPACK0_HIGH,bytes 11-13 of the HDMI AVI InfoFrame"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PB13 ,HDMI Audio InfoFrame Byte 13"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PB12 ,HDMI Audio InfoFrame Byte 12"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PB11 ,HDMI Audio InfoFrame Byte 11"
|
|
textline " "
|
|
line.long 0x14 "HDMI_GENERIC_CTRL,HDMI_GENERIC_CTRL"
|
|
bitfld.long 0x14 16. " AUDIO ,Audio packet transmission enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " HBLANK ,Packet will be sent (once) during the next horizontal blanking interval" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " SINGLE ,Cause InfoFrame to be transmitted exactly once" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " OTHER ,Cause InfoFrame to be transmitted to every other frame" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " ENABLE ,Enable frame generation at the beginning of the next frame" "Disabled,Enabled"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "HDMI_GENERIC_STATUS,HDMI_GENERIC_STATUS"
|
|
bitfld.long 0x00 0. " SENT ,Packet is sent" "WAITING,DONE"
|
|
group.long 0xB0++0x23
|
|
line.long 0x00 "HDMI_GENERIC_INFOFRAME_HEADER,HDMI GENERIC InfoFrame header"
|
|
hexmask.long.byte 0x00 16.--23. 1. " HB2 ,Header Byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HB1 ,Header Byte 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " HB0 ,Header Byte 0"
|
|
line.long 0x04 "HDMI_GENERIC_INFOFRAME_SUBPACK0_LOW,Bytes 0-3 of the HDMI GENERIC InfoFrame"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PB3 ,HDMI Audio InfoFrame Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PB2 ,HDMI Audio InfoFrame Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " PB1 ,HDMI Audio InfoFrame Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PB0 ,HDMI Audio InfoFrame Byte 0"
|
|
line.long 0x08 "HDMI_GENERIC_INFOFRAME_SUBPACK0_HIGH,bytes 4-6 of the HDMI GENERIC InfoFrame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " PB6 ,HDMI Audio InfoFrame Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PB5 ,HDMI Audio InfoFrame Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PB4 ,HDMI Audio InfoFrame Byte 4"
|
|
line.long 0x0C "HDMI_GENERIC_INFOFRAME_SUBPACK1_LOW,Bytes 7-10 of the HDMI GENERIC InfoFrame"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " PB10 ,HDMI Audio InfoFrame Byte 10"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " PB9 ,HDMI Audio InfoFrame Byte 9"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " PB8 ,HDMI Audio InfoFrame Byte 8"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PB7 ,HDMI Audio InfoFrame Byte 7"
|
|
line.long 0x10 "HDMI_GENERIC_INFOFRAME_SUBPACK1_HIGH,bytes 11-13 of the HDMI GENERIC InfoFrame"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PB13 ,HDMI Audio InfoFrame Byte 13"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PB12 ,HDMI Audio InfoFrame Byte 12"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PB11 ,HDMI Audio InfoFrame Byte 11"
|
|
line.long 0x14 "HDMI_GENERIC_INFOFRAME_SUBPACK2_LOW,Bytes 14-17 of the HDMI GENERIC InfoFrame"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PB17 ,HDMI Audio InfoFrame Byte 17"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PB16 ,HDMI Audio InfoFrame Byte 16"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PB15 ,HDMI Audio InfoFrame Byte 15"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PB14 ,HDMI Audio InfoFrame Byte 14"
|
|
line.long 0x18 "HDMI_GENERIC_INFOFRAME_SUBPACK2_HIGH,bytes 18-20 of the HDMI GENERIC InfoFrame"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PB20 ,HDMI Audio InfoFrame Byte 20"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PB19 ,HDMI Audio InfoFrame Byte 19"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PB18 ,HDMI Audio InfoFrame Byte 18"
|
|
line.long 0x1C "HDMI_GENERIC_INFOFRAME_SUBPACK3_LOW,Bytes 21-24 of the HDMI GENERIC InfoFrame"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PB24 ,HDMI Audio InfoFrame Byte 24"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PB23 ,HDMI Audio InfoFrame Byte 23"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PB22 ,HDMI Audio InfoFrame Byte 22"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PB21 ,HDMI Audio InfoFrame Byte 21"
|
|
line.long 0x20 "HDMI_GENERIC_INFOFRAME_SUBPACK3_HIGH,bytes 25-27 of the HDMI GENERIC InfoFrame"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PB27 ,HDMI Audio InfoFrame Byte 27"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PB26 ,HDMI Audio InfoFrame Byte 26"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PB25 ,HDMI Audio InfoFrame Byte 25"
|
|
textline " "
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "HDMI_ACR_CTRL,HDMI Audio Clock Regeneration Control"
|
|
bitfld.long 0x00 24.--27. " FREQS ,Audio sampling frequency to be used when FREQS is Enabled" "44_1KHZ,,48KHZ,32KHZ,,,,,88_2KHZ,,96KHZ,,176_4KHZ,,192KHZ,?..."
|
|
bitfld.long 0x00 16. " FREQS_ENABLE ,Use sampling frequency written into FREQS" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MEASURE_ENABLE ,Use sampling frequency measured in the in the audio block" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PACKET_ENABLE ,Use the channel status information read from the incoming SPDIF audio stream" "Disabled,Enabled"
|
|
group.long 0xD4++0x07
|
|
line.long 0x00 "HDMI_ACR_0320_SUBPACK_LOW,Bytes 1-3 of the 32 kHz ACR packet (This is the CTS value)"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SB1 ,HDMI 32 kHz ACR packet Byte 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SB2 ,HDMI 32 kHz ACR packet Byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SB3 ,HDMI 32 kHz ACR packet Byte 3"
|
|
line.long 0x04 "HDMI_ACR_0320_SUBPACK_HIGH,Bytes 4-6 of the 32 kHz ACR packet (This is the N value)"
|
|
bitfld.long 0x04 31. " ENABLE ,Allows this ACR packet to be sent" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SB4 ,HDMI 32 kHz ACR packet Byte 4"
|
|
hexmask.long.byte 0x04 8.--15. 1. " SB5 ,HDMI 32 kHz ACR packet Byte 5"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SB6 ,HDMI 32 kHz ACR packet Byte 6"
|
|
group.long 0xD4++0x07
|
|
line.long 0x00 "HDMI_ACR_0441_SUBPACK_LOW,Bytes 1-3 of the 44.1 kHz ACR packet (This is the CTS value)"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SB1 ,HDMI 44.1 kHz ACR packet Byte 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SB2 ,HDMI 44.1 kHz ACR packet Byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SB3 ,HDMI 44.1 kHz ACR packet Byte 3"
|
|
line.long 0x04 "HDMI_ACR_0441_SUBPACK_HIGH,Bytes 4-6 of the 44.1 kHz ACR packet (This is the N value)"
|
|
bitfld.long 0x04 31. " ENABLE ,Allows this ACR packet to be sent" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SB4 ,HDMI 44.1 kHz ACR packet Byte 4"
|
|
hexmask.long.byte 0x04 8.--15. 1. " SB5 ,HDMI 44.1 kHz ACR packet Byte 5"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SB6 ,HDMI 44.1 kHz ACR packet Byte 6"
|
|
group.long 0xD4++0x07
|
|
line.long 0x00 "HDMI_ACR_0882_SUBPACK_LOW,Bytes 1-3 of the 88.2 kHz ACR packet (This is the CTS value)"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SB1 ,HDMI 88.2 kHz ACR packet Byte 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SB2 ,HDMI 88.2 kHz ACR packet Byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SB3 ,HDMI 88.2 kHz ACR packet Byte 3"
|
|
line.long 0x04 "HDMI_ACR_0882_SUBPACK_HIGH,Bytes 4-6 of the 88.2 kHz ACR packet (This is the N value)"
|
|
bitfld.long 0x04 31. " ENABLE ,Allows this ACR packet to be sent" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SB4 ,HDMI 88.2 kHz ACR packet Byte 4"
|
|
hexmask.long.byte 0x04 8.--15. 1. " SB5 ,HDMI 88.2 kHz ACR packet Byte 5"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SB6 ,HDMI 88.2 kHz ACR packet Byte 6"
|
|
group.long 0xD4++0x07
|
|
line.long 0x00 "HDMI_ACR_1764_SUBPACK_LOW,Bytes 1-3 of the 176.4 kHz ACR packet (This is the CTS value)"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SB1 ,HDMI 176.4 kHz ACR packet Byte 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SB2 ,HDMI 176.4 kHz ACR packet Byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SB3 ,HDMI 176.4 kHz ACR packet Byte 3"
|
|
line.long 0x04 "HDMI_ACR_1764_SUBPACK_HIGH,Bytes 4-6 of the 176.4 kHz ACR packet (This is the N value)"
|
|
bitfld.long 0x04 31. " ENABLE ,Allows this ACR packet to be sent" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SB4 ,HDMI 176.4 kHz ACR packet Byte 4"
|
|
hexmask.long.byte 0x04 8.--15. 1. " SB5 ,HDMI 176.4 kHz ACR packet Byte 5"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SB6 ,HDMI 176.4 kHz ACR packet Byte 6"
|
|
group.long 0xD4++0x07
|
|
line.long 0x00 "HDMI_ACR_0480_SUBPACK_LOW,Bytes 1-3 of the 48 kHz ACR packet (This is the CTS value)"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SB1 ,HDMI 48 kHz ACR packet Byte 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SB2 ,HDMI 48 kHz ACR packet Byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SB3 ,HDMI 48 kHz ACR packet Byte 3"
|
|
line.long 0x04 "HDMI_ACR_0480_SUBPACK_HIGH,Bytes 4-6 of the 48 kHz ACR packet (This is the N value)"
|
|
bitfld.long 0x04 31. " ENABLE ,Allows this ACR packet to be sent" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SB4 ,HDMI 48 kHz ACR packet Byte 4"
|
|
hexmask.long.byte 0x04 8.--15. 1. " SB5 ,HDMI 48 kHz ACR packet Byte 5"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SB6 ,HDMI 48 kHz ACR packet Byte 6"
|
|
group.long 0xD4++0x07
|
|
line.long 0x00 "HDMI_ACR_0960_SUBPACK_LOW,Bytes 1-3 of the 96 kHz ACR packet (This is the CTS value)"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SB1 ,HDMI 96 kHz ACR packet Byte 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SB2 ,HDMI 96 kHz ACR packet Byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SB3 ,HDMI 96 kHz ACR packet Byte 3"
|
|
line.long 0x04 "HDMI_ACR_0960_SUBPACK_HIGH,Bytes 4-6 of the 96 kHz ACR packet (This is the N value)"
|
|
bitfld.long 0x04 31. " ENABLE ,Allows this ACR packet to be sent" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SB4 ,HDMI 96 kHz ACR packet Byte 4"
|
|
hexmask.long.byte 0x04 8.--15. 1. " SB5 ,HDMI 96 kHz ACR packet Byte 5"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SB6 ,HDMI 96 kHz ACR packet Byte 6"
|
|
group.long 0xD4++0x07
|
|
line.long 0x00 "HDMI_ACR_1920_SUBPACK_LOW,Bytes 1-3 of the 192 kHz ACR packet (This is the CTS value)"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SB1 ,HDMI 192 kHz ACR packet Byte 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SB2 ,HDMI 192 kHz ACR packet Byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SB3 ,HDMI 192 kHz ACR packet Byte 3"
|
|
line.long 0x04 "HDMI_ACR_1920_SUBPACK_HIGH,Bytes 4-6 of the 192 kHz ACR packet (This is the N value)"
|
|
bitfld.long 0x04 31. " ENABLE ,Allows this ACR packet to be sent" "Disabled,Enabled"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SB4 ,HDMI 192 kHz ACR packet Byte 4"
|
|
hexmask.long.byte 0x04 8.--15. 1. " SB5 ,HDMI 192 kHz ACR packet Byte 5"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SB6 ,HDMI 192 kHz ACR packet Byte 6"
|
|
textline " "
|
|
group.long 0x110++0x0F
|
|
line.long 0x00 "HDMI_CTRL,HDMI control"
|
|
bitfld.long 0x00 30. " ENABLE ,HDMI head enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CA_SELECT ,Channel allocation SW/SW Based selection" "Software,Hardware"
|
|
bitfld.long 0x00 27. " SS_SELECT ,Sample size SW/SW Based selection" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SF_SELECT ,Sampling frequency SW/SW Based selection" "Software,Hardware"
|
|
bitfld.long 0x00 25. " CC_SELECT ,Channel count select SW/SW Based selection" "Software,Hardware"
|
|
bitfld.long 0x00 24. " CT_SELECT ,Coding type select SW/SW Based selection" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " MAX_AC_PACKET ,Maximum number of 32-pixel packets that will fit in the horizontal blanking interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12. " SAMPLE_FLAT ,Controls the values of (HB2[3:0]) of the Audio Sample Packet Header" "CLR,SET"
|
|
bitfld.long 0x00 10. " AUDIO_LAYOUT_SELECT ,AUDIO_LAYOUT_SELECT" "HW_BASED,SW_BASED"
|
|
textline " "
|
|
bitfld.long 0x00 8. " AUDIO_LAYOUT ,Controls layout (HB1[4]) of the Audio Sample Packet Header" "2CH,8CH"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REKEY ,Number of clocks required for HDCP rekey"
|
|
line.long 0x04 "HDMI_VSYNC_KEEPOUT,Defines the start and end of the VSYNC keepout period"
|
|
bitfld.long 0x04 31. " ENABLE ,Enable Keepout window" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 16.--25. 1. " START ,Start of the keepout period"
|
|
hexmask.long.word 0x04 0.--9. 1. " END ,End of the keepout period"
|
|
line.long 0x08 "HDMI_VSYNC_WINDOW,Defines the start and end of the VSYNC window of opportunity period"
|
|
bitfld.long 0x08 31. " ENABLE ,Enable window of opportunity" "Disabled,Enabled"
|
|
hexmask.long.word 0x08 16.--25. 1. " START ,Start of the window of opportunity"
|
|
hexmask.long.word 0x08 0.--9. 1. " END ,End of the window of opportunity"
|
|
line.long 0x0C "HDMI_GCP_CTRL,Frequency and generation of GCP packets control"
|
|
bitfld.long 0x0C 8. " SINGLE ,Cause GCP packet to be transmitted exactly once" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " OTHER ,Cause GCP packet to be transmitted to every other frame" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " ENABLE ,Enable frame generation at the beginning of the next frame" "Disabled,Enabled"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "HDMI_GCP_STATUS,HDMI_GCP_STATUS"
|
|
bitfld.long 0x00 0. " SENT ,Packet is sent" "WAITING,DONE"
|
|
group.long 0x124++0x13
|
|
line.long 0x00 "HDMI_GCP_SUBPACK,This register should be written with the contents of the general control packet"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SB2 ,HDMI GCP packet Byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SB1 ,HDMI GCP packet Byte 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SB0 ,HDMI GCP packet Byte 0"
|
|
textline " "
|
|
line.long 0x04 "HDMI_CHANNEL_STATUS1,HDMI_CHANNEL_STATUS1"
|
|
bitfld.long 0x04 28.--31. " ACCURACY ,Transmitter Clock accuracy" "High accuracy,Normal accuracy,Variable pitch shifted clock,OTHER,?..."
|
|
bitfld.long 0x04 24.--27. " SFREQ ,The reported sampling frequency of the audio stream" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--23. " CHANNEL ,Channel number of the audio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " SOURCE ,Source number of the audio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x04 8.--15. 1. " CODE ,Category Code of the input device"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ABCDM ,First byte of the channel status information"
|
|
line.long 0x08 "HDMI_CHANNEL_STATUS2,HDMI_CHANNEL_STATUS2"
|
|
bitfld.long 0x08 31. " ENABLE ,Override the channel status data with the value of these registers" "Disabled,Enabled"
|
|
bitfld.long 0x08 4.--7. " ORIGINAL ,Original sampling frequency of the audio stream" "UNDEFINED,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. " LENGTH ,Audio sample word length" "UNDEF,16BITS,18BITS,19BITS,,20BITS,17BITS,,UNDEF,20BITS,22BITS,,23BITS,24BITS,21BITS,?..."
|
|
line.long 0x0C " HDMI_EMU0,EMU0 and 1 do indirect addressing - EMU0 has the address"
|
|
line.long 0x10 " HDMI_EMU1,EMU0 and 1 do indirect addressing - EMU1 has the data"
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 " HDMI_EMU1_RDATA,EMU0 and 1 do indirect addressing - EMU1 has the data"
|
|
group.long 0x140++0x07
|
|
line.long 0x00 "HDMI_SPDIF_CHN_STATUS1,HDMI_SPDIF_CHN_STATUS1"
|
|
bitfld.long 0x00 28.--31. " ACCURACY ,Transmitter Clock accuracy" "High accuracy,Normal accuracy,Variable pitch shifted clock,OTHER,?..."
|
|
bitfld.long 0x00 24.--27. " SFREQ ,The reported sampling frequency of the audio stream" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " CHANNEL ,Channel number of the audio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SOURCE ,Source number of the audio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CODE ,Category Code of the input device"
|
|
bitfld.long 0x00 6.--7. " MODE ,MODE" "0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " D ,PREEMPHASIS" "NO_PREEMPHASIS,PREEMPHASIS,?..."
|
|
bitfld.long 0x00 2. " COPYRIGHT ,Copyright status of the audio" "Yes,No"
|
|
bitfld.long 0x00 1. " TYPE ,Specifies the type of data the audio word represents" "PCM,Other"
|
|
textline " "
|
|
bitfld.long 0x00 0. " USE ,pecifies consumer or professionaluse of the channel status block" "Consumer,Pro"
|
|
textline " "
|
|
line.long 0x04 "HDMI_SPDIF_CHN_STATUS2,HDMI_SPDIF_CHN_STATUS2"
|
|
bitfld.long 0x04 4.--7. " ORIGINAL ,Original sampling frequency of the audio stream" "UNDEFINED,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " LENGTH ,Audio sample word length" "UNDEF,16BITS,18BITS,19BITS,,20BITS,17BITS,,UNDEF,20BITS,22BITS,,23BITS,24BITS,21BITS,?..."
|
|
group.long 0x258++0x37
|
|
line.long 0x00 "CRC_CONTROL,Control the injection of CRC enable bit at the top of the pipeline"
|
|
bitfld.long 0x00 0. " ARM_CRC_ENABLE ,Enable computation of CRC" "Disabled,Enabled"
|
|
line.long 0x04 "INPUT_CONTROL,INPUT_CONTROL"
|
|
bitfld.long 0x04 1. " ARM_VIDEO_RANGE ,ARM_VIDEO_RANGE" "FULL,LIMITED"
|
|
bitfld.long 0x04 0. " HDMI_SRC_SELECT ,HDMI_SRC_SELECT" "DISBPLAY,DISPLAYB"
|
|
line.long 0x08 "SCRATCH,Register available for software to store the state or for testing purposes"
|
|
line.long 0x0C "PE_CURRENT,PE_CURRENT"
|
|
bitfld.long 0x0C 24.--27. " PE_CURRENT3 ,PE_CURRENT3" "0.0mA,1.0mA,2.0mA,3.0mA,4.0mA,5.0mA,6.0mA,7.0mA,8.0mA,9.0mA,10.0mA,11.0mA,12.0mA,13.0mA,14.0mA,15.0mA"
|
|
bitfld.long 0x0C 16.--19. " PE_CURRENT2 ,PE_CURRENT2" "0.0mA,1.0mA,2.0mA,3.0mA,4.0mA,5.0mA,6.0mA,7.0mA,8.0mA,9.0mA,10.0mA,11.0mA,12.0mA,13.0mA,14.0mA,15.0mA"
|
|
bitfld.long 0x0C 8.--11. " PE_CURRENT1 ,PE_CURRENT1" "0.0mA,1.0mA,2.0mA,3.0mA,4.0mA,5.0mA,6.0mA,7.0mA,8.0mA,9.0mA,10.0mA,11.0mA,12.0mA,13.0mA,14.0mA,15.0mA"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " PE_CURRENT0 ,PE_CURRENT0" "0.0mA,1.0mA,2.0mA,3.0mA,4.0mA,5.0mA,6.0mA,7.0mA,8.0mA,9.0mA,10.0mA,11.0mA,12.0mA,13.0mA,14.0mA,15.0mA"
|
|
line.long 0x10 "KEY_CTRL,HDCP KEY SRAM Register Control"
|
|
hexmask.long.word 0x10 22.--31. 0x40 " ADDRESS ,Next byte address in the local key store to be written"
|
|
hexmask.long.word 0x10 12.--21. 0x10 " LOAD_ADDRESS ,Address for the WRITE16 function"
|
|
rbitfld.long 0x10 6. " PKEY_LOADED ,Private key value has been received from KFUSE and is ready for use" "Not loaded,Loaded"
|
|
textline " "
|
|
bitfld.long 0x10 5. " PKEY_REQUEST_RELOAD ,Request that the private key be requested again from KFUSE" "IDLE,TRIGGER"
|
|
bitfld.long 0x10 4. " WRITE16 ,Write all 16 bytes of data from the hdcp_key_data bus into the local key store" "IDLE,TRIGGER"
|
|
bitfld.long 0x10 1. " AUTOINC ,Address written by WRITE16 will auto-increment after the operation is complete" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " LOCAL_KEYS ,LOCAL_KEYS" "Disabled,Enabled"
|
|
line.long 0x14 "KEY_CTRL,HDCP KEY SRAM Register Control"
|
|
bitfld.long 0x14 6. " CHECKSUMCMP_HIGH ,CHECKSUMCMP_HIGH" "MISMATCH,MATCH"
|
|
bitfld.long 0x14 5. " CHECKSUMCMP_LOW ,CHECKSUMCMP_LOW" "MISMATCH,MATCH"
|
|
bitfld.long 0x14 4. " CHECKSUM ,CHECKSUM" "DONE,TRIGGERED"
|
|
textline " "
|
|
bitfld.long 0x14 0. " SRAMCLEAR ,SRAMCLEAR" "DONE,TRIGGERED"
|
|
line.long 0x18 "KEY_DEBUG1,KEY_DEBUG1"
|
|
hexmask.long.word 0x18 16.--31. 1. " CHECKSUMVAL_HIGH ,CHECKSUMVAL_HIGH"
|
|
hexmask.long.word 0x18 0.--15. 1. " CHECKSUMVAL_LOW ,CHECKSUMVAL_LOW"
|
|
line.long 0x1C "KEY_DEBUG2,KEY_DEBUG2"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " SRAMDATA ,SRAMDATA"
|
|
hexmask.long.word 0x1C 12.--21. 1. " SRAMADDR ,SRAMADDR"
|
|
bitfld.long 0x1C 4. " SRAMWRITE1 ,SRAMWRITE1" "DONE,TRIGGERED"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " SRAMAUTOINC ,SRAMAUTOINC" "Disabled,Enabled"
|
|
line.long 0x20 "HDCP_KEY,HDCP_KEY_0"
|
|
line.long 0x24 "HDCP_KEY_1,HDCP_KEY_1"
|
|
line.long 0x28 "HDCP_KEY_2,HDCP_KEY_2"
|
|
line.long 0x2C "HDCP_KEY_3,HDCP_KEY_3"
|
|
line.long 0x30 "HDCP_KEY_TRIG,HDCP_KEY_TRIG"
|
|
bitfld.long 0x30 8. " LOAD_HDCP_KEY ,LOAD_HDCP_KEY" "IDLE,TRIGGER"
|
|
line.long 0x34 "SKEY_INDEX,SKEY_INDEX"
|
|
bitfld.long 0x34 0.--3. " IDX_VALUE ,IDX_VALUE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,TEST"
|
|
group.long 0x330++0x0B
|
|
line.long 0x00 "INT_STATUS,Sticky interrupt status"
|
|
eventfld.long 0x00 3. " SCRATCH ,Software has written NV_PDISP_SCRATCH register" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " CP_REQUEST , HDA Codec has written CP_REQUEST register" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " CODEC_SCRATCH1 , HDA Codec has written CODEC_SCRATCH1 register" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " CODEC_SCRATCH0 , HDA Codec has written CODEC_SCRATCH0 register" "No interrupt,Interrupt"
|
|
line.long 0x04 "INT_MASK,Prevent the interrupts from asserting the HDMI interrupt pin to the CPU"
|
|
bitfld.long 0x04 3. " SCRATCH_MASK ,SCRATCH interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 2. " CP_REQUEST_MASK ,CP_REQUEST interrupt mask" "Masked,Unmasked"
|
|
bitfld.long 0x04 1. " CODEC_SCRATCH1_MASK ,CP_REQUEST interrupt mask" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CODEC_SCRATCH0_MASK ,CODEC_SCRATCH0 interrupt mask" "Masked,Unmasked"
|
|
line.long 0x08 "INT_ENABLE,Allow the events to appear in INT_STATUS"
|
|
bitfld.long 0x08 3. " SCRATCH_ENABLE ,SCRATCH interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " CP_REQUEST_ENABLE ,CP_REQUEST interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " CODEC_SCRATCH1_ENABLE ,CP_REQUEST interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CODEC_SCRATCH0_ENABLE ,CODEC_SCRATCH0 interrupt enable" "Disabled,Enabled"
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "HDMI_VSI_CTRL,Frequency and generation of the Vendor Specific infoframe packets control"
|
|
bitfld.long 0x00 16. " VIDEO_FMT ,Video format" "SW_CONTROLLED,HW_CONTROLLED"
|
|
bitfld.long 0x00 9. " CHKSUM_HW , Hardware provides a way to calculate the Checksum for the infoframes" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. 8. " OTHER/SINGLE ,Frequency of infoframe generation" "Every frame,Every other frame,Exactly once,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLE ,ENABLE" "Disabled,Enabled"
|
|
rgroup.long 0x35C++0x03
|
|
line.long 0x00 "HDMI_VSI_STATUS,HDMI_VSI_STATUS"
|
|
bitfld.long 0x00 0. " SENT ,Packet is sent" "WAITING,DONE"
|
|
textline " "
|
|
group.long 0x360++0x23
|
|
line.long 0x00 "HDMI_VSI_INFOFRAME_HEADER,HDMI Audio HDMI_VSI_HEADER header"
|
|
hexmask.long.byte 0x00 16.--23. 1. " HB2 ,Header Byte 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HB1 ,Header Byte 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " HB0 ,Header Byte 0"
|
|
line.long 0x04 "HDMI_VSI_INFOFRAME_SUBPACK0_LOW,Bytes 0-3 of the HDMI VSI InfoFrame"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PB3 ,HDMI VSI InfoFrame Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PB2 ,HDMI VSI InfoFrame Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " PB1 ,HDMI VSI InfoFrame Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PB0 ,HDMI VSI InfoFrame Byte 0"
|
|
line.long 0x08 "HDMI_VSI_INFOFRAME_SUBPACK0_HIGH,bytes 4-6 of the HDMI VSI InfoFrame"
|
|
hexmask.long.byte 0x08 16.--23. 1. " PB6 ,HDMI VSI InfoFrame Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PB5 ,HDMI VSI InfoFrame Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PB4 ,HDMI VSI InfoFrame Byte 4"
|
|
line.long 0x0C "HDMI_VSI_INFOFRAME_SUBPACK1_LOW,Bytes 7-10 of the HDMI VSI InfoFrame"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " PB10 ,HDMI VSI InfoFrame Byte 10"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " PB9 ,HDMI VSI InfoFrame Byte 9"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " PB8 ,HDMI VSI InfoFrame Byte 8"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PB7 ,HDMI VSI InfoFrame Byte 7"
|
|
line.long 0x10 "HDMI_VSI_INFOFRAME_SUBPACK1_HIGH,bytes 11-13 of the HDMI VSI InfoFrame"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PB13 ,HDMI VSI InfoFrame Byte 13"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PB12 ,HDMI VSI InfoFrame Byte 12"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PB11 ,HDMI VSI InfoFrame Byte 11"
|
|
line.long 0x14 "HDMI_VSI_INFOFRAME_SUBPACK2_LOW,Bytes 14-17 of the HDMI VSI InfoFrame"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PB17 ,HDMI VSI InfoFrame Byte 17"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PB16 ,HDMI VSI InfoFrame Byte 16"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PB15 ,HDMI VSI InfoFrame Byte 15"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PB14 ,HDMI VSI InfoFrame Byte 14"
|
|
line.long 0x18 "HDMI_VSI_INFOFRAME_SUBPACK2_HIGH,bytes 18-20 of the HDMI VSI InfoFrame"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PB20 ,HDMI VSI InfoFrame Byte 20"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PB19 ,HDMI VSI InfoFrame Byte 19"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PB18 ,HDMI VSI InfoFrame Byte 18"
|
|
line.long 0x1C "HDMI_VSI_INFOFRAME_SUBPACK3_LOW,Bytes 21-24 of the HDMI VSI InfoFrame"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PB24 ,HDMI VSI InfoFrame Byte 24"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PB23 ,HDMI VSI InfoFrame Byte 23"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PB22 ,HDMI VSI InfoFrame Byte 22"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PB21 ,HDMI VSI InfoFrame Byte 21"
|
|
line.long 0x20 "HDMI_VSI_INFOFRAME_SUBPACK3_HIGH,bytes 25-27 of the HDMI VSI InfoFrame"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PB27 ,HDMI VSI InfoFrame Byte 27"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PB26 ,HDMI VSI InfoFrame Byte 26"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PB25 ,HDMI VSI InfoFrame Byte 25"
|
|
tree.end
|
|
width 14.
|
|
tree "Serial Output Resource Registers"
|
|
group.long 0x154++0x2B
|
|
line.long 0x00 "SOR_PWR,Power state of the SOR"
|
|
bitfld.long 0x00 31. " SETTING_NEW ,Trigger a new setting of power mode to take effect" "Done,Triggered"
|
|
rbitfld.long 0x00 28. " MODE ,Mode" "Normal,Safe"
|
|
rbitfld.long 0x00 24. " HALT_DELAY ,Halt delay" "Done,Avtive"
|
|
bitfld.long 0x00 17. " SAFE_START ,Safe start" "Normal,ALT"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SAFE_STATE ,Safe operating state" "PD,PU"
|
|
bitfld.long 0x00 1. " NORMAL_START ,Normal start" "Normal,Alt"
|
|
bitfld.long 0x00 0. " NORMAL_STATE ,Normal state" "PD,PU"
|
|
line.long 0x04 "SOR_TEST,Serial Output Resource"
|
|
hexmask.long.byte 0x04 24.--31. 1. " TESTMUX ,TESTMUX"
|
|
bitfld.long 0x04 23. " CRC ,The source of the data for CRC computation" "Pre serialize,Post deserialize"
|
|
bitfld.long 0x04 20.--22. " TPAT ,Test generator pattern" "LO,TDAT,RAMP,WALK,MAXSTEP,MINSTEP,?..."
|
|
bitfld.long 0x04 16.--17. " DSRC ,Data source" "Normal,Debug,TGEN,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10. " ATTACHED ,ATTACHED" "False,True"
|
|
bitfld.long 0x04 8.--9. " ACT_HEAD_OPMODE ,ACT_HEAD_OPMODE" "Sleep,Snooze,Awake,?..."
|
|
bitfld.long 0x04 6. " INVD ,Invert the data" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TEST_ENABLE ,TEST_ENABLE" "Normal,Test"
|
|
line.long 0x08 "SOR_PLL0,Serial Output Resource"
|
|
bitfld.long 0x08 28.--29. " TX_REG_LOAD ,TX regulator default loading" "0.5mA,1.0mA,1.5mA,2.0mA"
|
|
bitfld.long 0x08 24.--27. " ICHPMP ,Additions to the charge pump current in steps of 0.375uA" "0,0.375uA,0.75uA,1.125uA,1.5uA,1.875uA,2.25uA,2.625uA,3uA,3.375uA,3.75uA,4.125uA,4.5uA,4.875uA,5.25uA,5.625uA"
|
|
bitfld.long 0x08 16.--19. " FILTER ,Selects the loop filter and adjusts the filter resistor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 12.--15. " BG_V17_S ,Bandgap 1.7V output voltage control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " VCOCAP ,Selects the VCO capacitor and adjusts ring oscillator inter-stage load" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 5. " PULLDOWN ,Weak pulldown enable" "Disabled,2Kohm"
|
|
bitfld.long 0x08 4. " RESISTORSEL ,Selects the internal/external resistor" "Internal,External"
|
|
bitfld.long 0x08 3. " PDPORT ,Powerdown the output drivers" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x08 2. " VCOPD ,Powerdown the VCO" "RESCIND,ASSERT"
|
|
bitfld.long 0x08 1. " PDBG ,Powerdown the bandgap" "On,Off"
|
|
bitfld.long 0x08 0. " PWR ,Powerdown the TMDS pll" "On,Off"
|
|
line.long 0x0C "SOR_PLL1,Serial Output Resource"
|
|
bitfld.long 0x0C 31. " S_D_PIN_PE ,S_D_PIN_PE" "Single,Differential"
|
|
bitfld.long 0x0C 29. " HALF_FULL_PE ,HALF_FULL_PE" "Half,Full"
|
|
bitfld.long 0x0C 28. " PE_EN ,PE_EN" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20.--23. " LOADADJ ,LOADADJ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0C 9.--12. " TMDS_TERMADJ ,TMDS_TERMADJ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 8. " TMDS_TERM ,TMDS_TERM" "Disabled,Enabled"
|
|
line.long 0x10 "SOR_PLL2,Spare registers for TMDS control"
|
|
bitfld.long 0x10 23. " AUX7 ,AUX7" "No rotation,Rotate right 1bit"
|
|
bitfld.long 0x10 22. " AUX6 ,AUX6" "No rotation,Rotate right 1bit"
|
|
bitfld.long 0x10 21. " AUX5 ,AUX5" "No rotation,Rotate right 1bit"
|
|
bitfld.long 0x10 20. " AUX4 ,AUX4" "No rotation,Rotate right 1bit"
|
|
textline " "
|
|
bitfld.long 0x10 19. " AUX3 ,AUX3" "No rotation,Rotate right 1bit"
|
|
bitfld.long 0x10 18. " AUX2 ,AUX2" "No rotation,Rotate right 1bit"
|
|
bitfld.long 0x10 17. " AUX1 ,AUX1" "No rotation,Rotate right 1bit"
|
|
bitfld.long 0x10 16. " AUX0 ,AUX0" "No rotation,Rotate right 1bit"
|
|
textline " "
|
|
line.long 0x14 "SOR_CSTM,Spare registers for TMDS control"
|
|
bitfld.long 0x14 28.--30. " ROTDAT ,ROTDAT" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 24.--27. " ROTCLK ,Skews the TXC clock to come out earlier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 21. " PLLDIV ,PLLDIV" "Divide by 7,Divide by 10"
|
|
bitfld.long 0x14 19. " BALANCED ,Enable balanced encoding" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 18. " NEW_MODE ,For backwards compatibility" "Disabled,Enabled"
|
|
bitfld.long 0x14 17. " DUP_SYNC ,DUP_SYNC" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " LVDS_EN ,LVDS enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " LINKACTB ,Digital logic of link B" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 14. " LINKACTA ,Digital logic of link A" "Disabled,Enabled"
|
|
bitfld.long 0x14 12.--13. " MODE ,Operation mode" "LVDS,TMDS,?..."
|
|
bitfld.long 0x14 11. " UPPER ,UPPER" "False,True"
|
|
bitfld.long 0x14 9. " PD_TXCB ,Powerdown the clock pin of link B" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 8. " PD_TXCA ,Powerdown the clock pin of link A" "Disabled,Enabled"
|
|
bitfld.long 0x14 7. " PD_TXDB_3 ,Bitwise control to powerdown the data pins of link B" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " PD_TXDB_2 ,Bitwise control to powerdown the data pins of link B" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " PD_TXDB_1 ,Bitwise control to powerdown the data pins of link B" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PD_TXDB_0 ,Bitwise control to powerdown the data pins of link B" "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " PD_TXDA_3 ,Bitwise control to powerdown the data pins of link A" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " PD_TXDA_2 ,Bitwise control to powerdown the data pins of link A" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " PD_TXDA_1 ,Bitwise control to powerdown the data pins of link A" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " PD_TXDA_0 ,Bitwise control to powerdown the data pins of link A" "Disabled,Enabled"
|
|
line.long 0x18 "SOR_LVDS,LVDS custom mode"
|
|
bitfld.long 0x18 28.--30. " ROTDAT ,ROTDAT" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 24.--27. " ROTCLK ,Skews the TXC clock to come out earlier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x18 21. " PLLDIV ,PLLDIV" "Divide by 7,"
|
|
bitfld.long 0x18 19. " BALANCED ,Enable balanced encoding" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 18. " NEW_MODE ,For backwards compatibility" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " DUP_SYNC ,DUP_SYNC" "Disabled,Enabled"
|
|
rbitfld.long 0x18 16. " LVDS_EN ,LVDS enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 15. " LINKACTB ,Digital logic of link B" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x18 14. " LINKACTA ,Digital logic of link A" "Disabled,Enabled"
|
|
rbitfld.long 0x18 12.--13. " MODE ,Operation mode" "LVDS,?..."
|
|
rbitfld.long 0x18 11. " UPPER ,UPPER" "False,True"
|
|
bitfld.long 0x18 9. " PD_TXCB ,Powerdown the clock pin of link B" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x18 8. " PD_TXCA ,Powerdown the clock pin of link A" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " PD_TXDB_3 ,Bitwise control to powerdown the data pins of link B" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " PD_TXDB_2 ,Bitwise control to powerdown the data pins of link B" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " PD_TXDB_1 ,Bitwise control to powerdown the data pins of link B" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " PD_TXDB_0 ,Bitwise control to powerdown the data pins of link B" "Disabled,Enabled"
|
|
bitfld.long 0x18 3. " PD_TXDA_3 ,Bitwise control to powerdown the data pins of link A" "Disabled,Enabled"
|
|
rbitfld.long 0x18 2. " PD_TXDA_2 ,Bitwise control to powerdown the data pins of link A" "Disabled,Enabled"
|
|
rbitfld.long 0x18 1. " PD_TXDA_1 ,Bitwise control to powerdown the data pins of link A" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x18 0. " PD_TXDA_0 ,Bitwise control to powerdown the data pins of link A" "Disabled,Enabled"
|
|
line.long 0x1C "SOR_CRCA,Used to fetch CRCs when running VGA mode tests"
|
|
bitfld.long 0x1C 0. " VALID ,VALID" "False,True"
|
|
line.long 0x20 "SOR_CRCB,Used to fetch CRCs when running VGA mode tests"
|
|
line.long 0x24 "SOR_BLANK,Override the SOR output resource pixels with blank data"
|
|
rbitfld.long 0x24 2. " STATUS ,STATUS" "Not blanked,Blanked"
|
|
bitfld.long 0x24 1. " TRANSITION ,Controls the timing of the output resource blank override" "Immediate,Next Vsync"
|
|
bitfld.long 0x24 0. " OVERRIDE ,Override the pixel bus from the rg and output black pixels instead" "False,True"
|
|
line.long 0x28 "SOR_SEQ_CTL,Sequencer control registers for SOR"
|
|
bitfld.long 0x28 30. " WAIT ,WAIT" "Wait,Force"
|
|
bitfld.long 0x28 28. " STATUS ,Indicates if the sequencer is STOPPED or RUNNING" "Stopped,Running"
|
|
bitfld.long 0x28 16.--19. " PC ,Current value of the program counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x28 12.--15. " PD_PC_ALT ,Alternate entry point into the power down program sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x28 8.--11. " PD_PC ,Program counter for the start of the power down program sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x28 4.--7. " PU_PC_ALT ,Alternate entry point into the power up program sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x28 0.--3. " PU_PC ,Program counter for the start of the power up program sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "SOR_SEQ_INST0,SOR_SEQ_INST0_0"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,PLL_PULLDOWN" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,POWERDOWN_MACRO" "Normal,Power down"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESETV ,ASSERT_PLL_RESETV" "Normal,RESETV"
|
|
bitfld.long 0x00 28. " BLANK_V ,BLANK_V" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,BLANK_H" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,BLANK_DE" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,BLACK_DATA" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,TRISTATE_IOS" "Enable pins,Tri-state"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,DRIVE_PWM_OUT_LO" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,PIN_B" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,PIN_A" "Low,High"
|
|
bitfld.long 0x00 15. " HALT ,HALT" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,WAIT_UNITS" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,WAIT_TIME"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "SOR_SEQ_INST1,SOR_SEQ_INST1_0"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,PLL_PULLDOWN" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,POWERDOWN_MACRO" "Normal,Power down"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESETV ,ASSERT_PLL_RESETV" "Normal,RESETV"
|
|
bitfld.long 0x00 28. " BLANK_V ,BLANK_V" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,BLANK_H" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,BLANK_DE" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,BLACK_DATA" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,TRISTATE_IOS" "Enable pins,Tri-state"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,DRIVE_PWM_OUT_LO" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,PIN_B" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,PIN_A" "Low,High"
|
|
bitfld.long 0x00 15. " HALT ,HALT" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,WAIT_UNITS" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,WAIT_TIME"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "SOR_SEQ_INST2,SOR_SEQ_INST2_0"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,PLL_PULLDOWN" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,POWERDOWN_MACRO" "Normal,Power down"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESETV ,ASSERT_PLL_RESETV" "Normal,RESETV"
|
|
bitfld.long 0x00 28. " BLANK_V ,BLANK_V" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,BLANK_H" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,BLANK_DE" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,BLACK_DATA" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,TRISTATE_IOS" "Enable pins,Tri-state"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,DRIVE_PWM_OUT_LO" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,PIN_B" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,PIN_A" "Low,High"
|
|
bitfld.long 0x00 15. " HALT ,HALT" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,WAIT_UNITS" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,WAIT_TIME"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "SOR_SEQ_INST3,SOR_SEQ_INST3_0"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,PLL_PULLDOWN" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,POWERDOWN_MACRO" "Normal,Power down"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESETV ,ASSERT_PLL_RESETV" "Normal,RESETV"
|
|
bitfld.long 0x00 28. " BLANK_V ,BLANK_V" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,BLANK_H" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,BLANK_DE" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,BLACK_DATA" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,TRISTATE_IOS" "Enable pins,Tri-state"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,DRIVE_PWM_OUT_LO" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,PIN_B" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,PIN_A" "Low,High"
|
|
bitfld.long 0x00 15. " HALT ,HALT" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,WAIT_UNITS" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,WAIT_TIME"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "SOR_SEQ_INST4,SOR_SEQ_INST4_0"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,PLL_PULLDOWN" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,POWERDOWN_MACRO" "Normal,Power down"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESETV ,ASSERT_PLL_RESETV" "Normal,RESETV"
|
|
bitfld.long 0x00 28. " BLANK_V ,BLANK_V" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,BLANK_H" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,BLANK_DE" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,BLACK_DATA" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,TRISTATE_IOS" "Enable pins,Tri-state"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,DRIVE_PWM_OUT_LO" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,PIN_B" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,PIN_A" "Low,High"
|
|
bitfld.long 0x00 15. " HALT ,HALT" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,WAIT_UNITS" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,WAIT_TIME"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "SOR_SEQ_INST5,SOR_SEQ_INST5_0"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,PLL_PULLDOWN" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,POWERDOWN_MACRO" "Normal,Power down"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESETV ,ASSERT_PLL_RESETV" "Normal,RESETV"
|
|
bitfld.long 0x00 28. " BLANK_V ,BLANK_V" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,BLANK_H" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,BLANK_DE" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,BLACK_DATA" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,TRISTATE_IOS" "Enable pins,Tri-state"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,DRIVE_PWM_OUT_LO" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,PIN_B" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,PIN_A" "Low,High"
|
|
bitfld.long 0x00 15. " HALT ,HALT" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,WAIT_UNITS" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,WAIT_TIME"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "SOR_SEQ_INST6,SOR_SEQ_INST6_0"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,PLL_PULLDOWN" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,POWERDOWN_MACRO" "Normal,Power down"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESETV ,ASSERT_PLL_RESETV" "Normal,RESETV"
|
|
bitfld.long 0x00 28. " BLANK_V ,BLANK_V" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,BLANK_H" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,BLANK_DE" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,BLACK_DATA" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,TRISTATE_IOS" "Enable pins,Tri-state"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,DRIVE_PWM_OUT_LO" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,PIN_B" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,PIN_A" "Low,High"
|
|
bitfld.long 0x00 15. " HALT ,HALT" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,WAIT_UNITS" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,WAIT_TIME"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "SOR_SEQ_INST7,SOR_SEQ_INST7_0"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,PLL_PULLDOWN" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,POWERDOWN_MACRO" "Normal,Power down"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESETV ,ASSERT_PLL_RESETV" "Normal,RESETV"
|
|
bitfld.long 0x00 28. " BLANK_V ,BLANK_V" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,BLANK_H" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,BLANK_DE" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,BLACK_DATA" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,TRISTATE_IOS" "Enable pins,Tri-state"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,DRIVE_PWM_OUT_LO" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,PIN_B" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,PIN_A" "Low,High"
|
|
bitfld.long 0x00 15. " HALT ,HALT" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,WAIT_UNITS" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,WAIT_TIME"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "SOR_SEQ_INST8,SOR_SEQ_INST8_0"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,PLL_PULLDOWN" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,POWERDOWN_MACRO" "Normal,Power down"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESETV ,ASSERT_PLL_RESETV" "Normal,RESETV"
|
|
bitfld.long 0x00 28. " BLANK_V ,BLANK_V" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,BLANK_H" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,BLANK_DE" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,BLACK_DATA" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,TRISTATE_IOS" "Enable pins,Tri-state"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,DRIVE_PWM_OUT_LO" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,PIN_B" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,PIN_A" "Low,High"
|
|
bitfld.long 0x00 15. " HALT ,HALT" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,WAIT_UNITS" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,WAIT_TIME"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "SOR_SEQ_INST9,SOR_SEQ_INST9_0"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,PLL_PULLDOWN" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,POWERDOWN_MACRO" "Normal,Power down"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESETV ,ASSERT_PLL_RESETV" "Normal,RESETV"
|
|
bitfld.long 0x00 28. " BLANK_V ,BLANK_V" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,BLANK_H" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,BLANK_DE" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,BLACK_DATA" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,TRISTATE_IOS" "Enable pins,Tri-state"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,DRIVE_PWM_OUT_LO" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,PIN_B" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,PIN_A" "Low,High"
|
|
bitfld.long 0x00 15. " HALT ,HALT" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,WAIT_UNITS" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,WAIT_TIME"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "SOR_SEQ_INSTA,SOR_SEQ_INSTA_0"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,PLL_PULLDOWN" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,POWERDOWN_MACRO" "Normal,Power down"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESETV ,ASSERT_PLL_RESETV" "Normal,RESETV"
|
|
bitfld.long 0x00 28. " BLANK_V ,BLANK_V" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,BLANK_H" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,BLANK_DE" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,BLACK_DATA" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,TRISTATE_IOS" "Enable pins,Tri-state"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,DRIVE_PWM_OUT_LO" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,PIN_B" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,PIN_A" "Low,High"
|
|
bitfld.long 0x00 15. " HALT ,HALT" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,WAIT_UNITS" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,WAIT_TIME"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "SOR_SEQ_INSTB,SOR_SEQ_INSTB_0"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,PLL_PULLDOWN" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,POWERDOWN_MACRO" "Normal,Power down"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESETV ,ASSERT_PLL_RESETV" "Normal,RESETV"
|
|
bitfld.long 0x00 28. " BLANK_V ,BLANK_V" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,BLANK_H" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,BLANK_DE" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,BLACK_DATA" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,TRISTATE_IOS" "Enable pins,Tri-state"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,DRIVE_PWM_OUT_LO" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,PIN_B" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,PIN_A" "Low,High"
|
|
bitfld.long 0x00 15. " HALT ,HALT" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,WAIT_UNITS" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,WAIT_TIME"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "SOR_SEQ_INSTC,SOR_SEQ_INSTC_0"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,PLL_PULLDOWN" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,POWERDOWN_MACRO" "Normal,Power down"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESETV ,ASSERT_PLL_RESETV" "Normal,RESETV"
|
|
bitfld.long 0x00 28. " BLANK_V ,BLANK_V" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,BLANK_H" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,BLANK_DE" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,BLACK_DATA" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,TRISTATE_IOS" "Enable pins,Tri-state"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,DRIVE_PWM_OUT_LO" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,PIN_B" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,PIN_A" "Low,High"
|
|
bitfld.long 0x00 15. " HALT ,HALT" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,WAIT_UNITS" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,WAIT_TIME"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "SOR_SEQ_INSTD,SOR_SEQ_INSTD_0"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,PLL_PULLDOWN" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,POWERDOWN_MACRO" "Normal,Power down"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESETV ,ASSERT_PLL_RESETV" "Normal,RESETV"
|
|
bitfld.long 0x00 28. " BLANK_V ,BLANK_V" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,BLANK_H" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,BLANK_DE" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,BLACK_DATA" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,TRISTATE_IOS" "Enable pins,Tri-state"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,DRIVE_PWM_OUT_LO" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,PIN_B" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,PIN_A" "Low,High"
|
|
bitfld.long 0x00 15. " HALT ,HALT" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,WAIT_UNITS" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,WAIT_TIME"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "SOR_SEQ_INSTE,SOR_SEQ_INSTE_0"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,PLL_PULLDOWN" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,POWERDOWN_MACRO" "Normal,Power down"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESETV ,ASSERT_PLL_RESETV" "Normal,RESETV"
|
|
bitfld.long 0x00 28. " BLANK_V ,BLANK_V" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,BLANK_H" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,BLANK_DE" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,BLACK_DATA" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,TRISTATE_IOS" "Enable pins,Tri-state"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,DRIVE_PWM_OUT_LO" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,PIN_B" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,PIN_A" "Low,High"
|
|
bitfld.long 0x00 15. " HALT ,HALT" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,WAIT_UNITS" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,WAIT_TIME"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "SOR_SEQ_INSTF,SOR_SEQ_INSTF_0"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,PLL_PULLDOWN" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,POWERDOWN_MACRO" "Normal,Power down"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESETV ,ASSERT_PLL_RESETV" "Normal,RESETV"
|
|
bitfld.long 0x00 28. " BLANK_V ,BLANK_V" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,BLANK_H" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,BLANK_DE" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,BLACK_DATA" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,TRISTATE_IOS" "Enable pins,Tri-state"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,DRIVE_PWM_OUT_LO" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,PIN_B" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,PIN_A" "Low,High"
|
|
bitfld.long 0x00 15. " HALT ,HALT" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,WAIT_UNITS" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,WAIT_TIME"
|
|
width 24.
|
|
textline " "
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "SOR_LANE_DRIVE_CURRENT,TMDS per-lane I/O current control"
|
|
hexmask.long.byte 0x00 24.--31. 1. " LANE3 ,LANE3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LANE2 ,LANE2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " LANE1 ,LANE1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LANE0 ,LANE0"
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "SOR_REFCLK,SOR_REFCLK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DIV_INT ,DIV_INT"
|
|
hexmask.long.byte 0x00 6.--7. 1. " DIV_FRAC ,DIV_FRAC"
|
|
group.long 0x344++0x0B
|
|
line.long 0x00 "SOR_IO_PEAK_CURRENT,Pad controls for 28nm macro TMDS_X4_HP"
|
|
hexmask.long.byte 0x00 24.--31. 1. " LANE3 ,LANE3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LANE2 ,LANE2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " LANE1 ,LANE1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LANE0 ,LANE0"
|
|
line.long 0x04 "SOR_PAD_CTLS0,SOR_PAD_CTLS0"
|
|
bitfld.long 0x04 31. " FUSE_OVERRIDE ,FUSE_OVERRIDE" "0,1"
|
|
bitfld.long 0x04 25. " LOADADJ_SYNC_EN ,LOADADJ_SYNC_EN" "0,1"
|
|
bitfld.long 0x04 24. " LOADADJ_BYPN ,LOADADJ_BYPN" "0,1"
|
|
bitfld.long 0x04 22. " REG_BYPASS ,REG_BYPASS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 21. " KVCO_2NDVCO ,KVCO_2NDVCO" "0,1"
|
|
bitfld.long 0x04 20. " VCOCALIB_TS0 ,VCOCALIB_TS0" "0,1"
|
|
bitfld.long 0x04 19. " VCOCALIB_OVRWR ,VCOCALIB_OVRWR" "0,1"
|
|
bitfld.long 0x04 18. " VCOCALIB_ENB ,VCOCALIB_ENB" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 17. " VCOLIMIT_DISABLE ,VCOLIMIT_DISABLE" "0,1"
|
|
bitfld.long 0x04 16. " VCOLIMIT_SEL ,VCOLIMIT_SEL" "0,1"
|
|
bitfld.long 0x04 12.--15. " BG_TEMP_COEF ,BG_TEMP_COEF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " BG_VREF_LEVEL ,BG_VREF_LEVEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " AVDD23_LEVEL ,AVDD23_LEVEL" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " AVDD23_LOAD ,AVDD23_LOAD" "0,1,2,3"
|
|
bitfld.long 0x04 2.--3. " AVDD10_LEVEL ,AVDD10_LEVEL" "0,1,2,3"
|
|
bitfld.long 0x04 0.--1. " AVDD10_LOAD ,AVDD10_LOAD" "0,1,2,3"
|
|
line.long 0x08 "SOR_PAD_CTLS1,SOR_PAD_CTLS1"
|
|
bitfld.long 0x08 11. " DIV_RATIO_OVERRIDE ,DIV_RATIO_OVERRIDE" "0,1"
|
|
bitfld.long 0x08 10. " PLL_BYPASS ,PLL_BYPASS" "0,1"
|
|
bitfld.long 0x08 8.--9. " KICKSTART ,KICKSTART" "0,1,2,3"
|
|
bitfld.long 0x08 4.--7. " PLL_NDIV_RATIO ,PLL_NDIV_RATIO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. " PLL_PDIV_RATIO ,PLL_PDIV_RATIO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 13.
|
|
tree "Test and Debug Registers"
|
|
rgroup.long 0x1C8++0x1F
|
|
line.long 0x00 "SOR_VCRCA0,VCRC register for sub-link A"
|
|
hexmask.long.word 0x00 16.--31. 1. " CRCM ,Middle 16-bit chunk"
|
|
hexmask.long.word 0x00 0.--15. 1. " CRCL ,Lower 16-bit chunk"
|
|
line.long 0x04 "SOR_VCRCA1,VCRC register for sub-link A"
|
|
hexmask.long.word 0x04 0.--15. 1. " CRCH ,Upper 16-bit chunk"
|
|
line.long 0x08 "SOR_CCRCA0,CCRC register for sub-link A"
|
|
hexmask.long.word 0x08 16.--31. 1. " CRCM ,Middle 16-bit chunk"
|
|
hexmask.long.word 0x08 0.--15. 1. " CRCL ,Lower 16-bit chunk"
|
|
line.long 0x0C "SOR_CCRCA1,CCRC register for sub-link A"
|
|
hexmask.long.word 0x0C 0.--15. 1. " CRCH ,Upper 16-bit chunk"
|
|
line.long 0x10 "SOR_EDATAA0,EDATA register for sub-link A"
|
|
line.long 0x14 "SOR_EDATAA1,EDATA register for sub-link A"
|
|
hexmask.long.byte 0x14 0.--7. 1. " VAL ,VAL"
|
|
line.long 0x18 "SOR_COUNTA0,Count registers for sub-link A"
|
|
hexmask.long.word 0x18 16.--31. 1. " TX1 ,TX1"
|
|
hexmask.long.word 0x18 0.--15. 1. " TX0 ,TX0"
|
|
line.long 0x1C "SOR_COUNTA1,Count registers for sub-link A"
|
|
hexmask.long.word 0x1C 0.--15. 1. " TX2 ,TX2"
|
|
group.long 0x1E8++0x0F
|
|
line.long 0x00 "SOR_DEBUGA0,Debug registers for sub-link A"
|
|
line.long 0x04 "SOR_DEBUGA1,Debug registers for sub-link A"
|
|
hexmask.long.byte 0x04 0.--7. 1. " VAL ,VAL"
|
|
line.long 0x08 "SOR_TRIG,Number of pixel clock cycles after the previous VSYNC"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " VAL ,VAL"
|
|
line.long 0x0C "SOR_MSCHECK,Mode switch monitor"
|
|
bitfld.long 0x0C 31. " CTL ,CTL" "Clear,Run"
|
|
rbitfld.long 0x0C 12.--15. " DATA_ENABLE_T2F ,DATA_ENABLE_T2F" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x0C 8.--11. " DATA_ENABLE_F2T ,DATA_ENABLE_F2T" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x0C 4.--7. " CRC_ENABLE_T2F ,CRC_ENABLE_T2F" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x0C 0.--3. " CRC_ENABLE_F2T ,CRC_ENABLE_F2T" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 30.
|
|
tree "Audio Registers (HDMI_NV_PDISP_SOR_AUDIO)"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "AUDIO_N,AUDIO_N"
|
|
bitfld.long 0x00 28. " LOOKUP ,hardware will select the appropriate value of N to use" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " GENERATE ,Controls how the audio block generates the 128*fs/N pulse" "Normal,Alternate"
|
|
bitfld.long 0x00 20. " RESETF ,Reset for the N counter" "Deassert,Assert"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,N parameter in HDMI Audio Clock Regeneration Packet"
|
|
group.long 0x2B0++0x07
|
|
line.long 0x00 "SOR_AUDIO_CNTRL0,HD Audio (Azalia) control"
|
|
rbitfld.long 0x00 31. " INPUT_MODE ,Input Mode" "Azalia data,S/PDIF data"
|
|
bitfld.long 0x00 29. " INJECT_NULLSMPL ,INJECT_NULLSMPL" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " SOURCE_SELECT ,Source selection" "Auto,Azalia data,S/PDIF data,?..."
|
|
bitfld.long 0x00 16.--19. " SAMPLING_FREQ ,Sampling frequency" "44_1KHZ,UNKNOWN,48_0KHZ,32_0KHZ,,,,,88_2KHZ,,96_0KHZ,,176_4KHZ,,192_0KHZ,?..."
|
|
line.long 0x04 "SOR_AUDIO_CNTRL0,HD Audio (Azalia) control"
|
|
bitfld.long 0x04 0. " FIFO_ERROR ,FIFO_ERROR" "No,Yes"
|
|
group.long 0x2BC++0x03
|
|
line.long 0x00 "SOR_AUDIO_NVAL_0320,N values for the current pixel clock frequency"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,VAL_0320_VALUE"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "SOR_AUDIO_NVAL_0441,N values for the current pixel clock frequency"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,VAL_0441_VALUE"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "SOR_AUDIO_NVAL_0882,N values for the current pixel clock frequency"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,VAL_0882_VALUE"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "SOR_AUDIO_NVAL_1764,N values for the current pixel clock frequency"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,VAL_1764_VALUE"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "SOR_AUDIO_NVAL_0480,N values for the current pixel clock frequency"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,VAL_0480_VALUE"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "SOR_AUDIO_NVAL_0960,N values for the current pixel clock frequency"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,VAL_0960_VALUE"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "SOR_AUDIO_NVAL_1920,N values for the current pixel clock frequency"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,VAL_1920_VALUE"
|
|
rgroup.long 0x2E8++0x07
|
|
line.long 0x00 "SOR_AUDIO_HDA_CODEC_SCRATCH0,Set by the audio driver using vendor-defined verbs"
|
|
line.long 0x04 "SOR_AUDIO_HDA_CODEC_SCRATCH1,Set by the audio driver using vendor-defined verbs"
|
|
group.long 0x2F0++0x07
|
|
line.long 0x00 "SOR_AUDIO_HDA_ELD_BUFWR,Software Programming Model"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INDEX ,INDEX"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATABYTE ,DATABYTE"
|
|
line.long 0x04 "SOR_AUDIO_HDA_PRESENSE,Reports the HotPlug state and ELD state to the audio driver"
|
|
bitfld.long 0x04 1. " ELDV ,ELD buffer is valid and ready to read" "Invalid,Valid"
|
|
bitfld.long 0x04 0. " PD ,Presence Detect" "Not present,Present"
|
|
textline " "
|
|
rgroup.long 0x2F8++0x03
|
|
line.long 0x00 "SOR_AUDIO_HDA_CP,Content Protection state requested by the Audio driver"
|
|
bitfld.long 0x00 2. " REQUEST_STATE_VALID ,REQUEST_STATE_VALID" "0,1"
|
|
bitfld.long 0x00 0.--1. " REQUEST_STATE ,REQUEST_STATE" "Don't care,,Protection Off,Protection On"
|
|
textline " "
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "SOR_AUDIO_AVAL_0320,The correct A value for 32 kHz audio at the current pixel clock frequency"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,VALUE"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "SOR_AUDIO_AVAL_0441,The correct A value for 44.1 kHz audio at the current pixel clock frequency"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,VALUE"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "SOR_AUDIO_AVAL_0882,The correct A value for 88.2 kHz audio at the current pixel clock frequency"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,VALUE"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "SOR_AUDIO_AVAL_1764,The correct A value for 176.4 kHz audio at the current pixel clock frequency"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,VALUE"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "SOR_AUDIO_AVAL_0480,The correct A value for 48 kHz audio at the current pixel clock frequency"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,VALUE"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "SOR_AUDIO_AVAL_0960,The correct A value for 96 kHz audio at the current pixel clock frequency"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,VALUE"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "SOR_AUDIO_AVAL_1920,The correct A value for 192 kHz audio at the current pixel clock frequency"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,VALUE"
|
|
group.long 0x318++0x07
|
|
line.long 0x00 "SOR_AUDIO_AVAL_DEFAULT,Default A value if the Azalia codec sampling frequency does not match any of the above"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,VALUE"
|
|
line.long 0x04 "SOR_AUDIO_GEN_CTRL,GEN_CTRL"
|
|
hexmask.long.word 0x04 16.--31. 1. " DEV_ID ,Device ID to identify the current chip"
|
|
hexmask.long.byte 0x04 0.--7. 1. " REV_ID ,Rev ID for the Codec"
|
|
textline " "
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "HDACODEC_AUDIO_GEN_CTL,CHSTS_FS_3840"
|
|
bitfld.long 0x00 4. " COPY_POLARITY ,COPY_POLARITY" "OLD,NEW"
|
|
bitfld.long 0x00 0.--3. " CHSTS_FS_3840 ,Currently the 4-bit coding for 384 kHz sampling rate is not available in the IEC-61937 specification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "LVDS/EDP Display output"
|
|
tree "LCDS/eDP Registers"
|
|
base ad:0x54540000
|
|
width 26.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTXSW_0,Context switch register"
|
|
rbitfld.long 0x00 28.--31. " NEXT_CHANNEL ,Next requested channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 16.--25. 1. " NEXT_CLASS ,Next requested class"
|
|
bitfld.long 0x00 12.--15. " CURR_CHANNEL ,Current working channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. " AUTO_ACK ,Automatically acknowledge any incoming context switch requests" "MANUAL,AUTOACK"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " CURR_CLASS ,Current working class"
|
|
line.long 0x04 "PDISP_SOR_SUPER_STATE0_0,SOR update state 0"
|
|
bitfld.long 0x04 0. " UPDATE ,UPDATE: Writing a 1 to this field cause a 1 cycle pulse" "No update,Update"
|
|
line.long 0x08 "PDISP_SOR_SUPER_STATE1_0,SOR update state 1"
|
|
bitfld.long 0x08 3. " ATTACHED ,Attach SOR to a display head" "No,Yes"
|
|
bitfld.long 0x08 2. " ASY_ORMODE ,SOR sending data mode" "Safe,Normal"
|
|
bitfld.long 0x08 0.--1. " ASY_HEAD_OPMODE ,Display sending active pixels to SOR mode" "SLEEP,SNOOZE,AWAKE,?..."
|
|
textline " "
|
|
width 21.
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "PDISP_SOR_STATE0_0,SOR update state 0"
|
|
bitfld.long 0x00 0. " UPDATE ,UPDATE: Writing a 1 to this field cause a 1 cycle pulse" "No update,Update"
|
|
line.long 0x04 "PDISP_SOR_STATE1_0,SOR update state 1"
|
|
bitfld.long 0x04 17.--20. " ASY_PIXELDEPTH ,Pixel depth" ",,BPP_18_444,,,BPP_24_444,?..."
|
|
bitfld.long 0x04 15.--16. " ASY_REPLICATE ,Enable pixel replication for HDMI" "Off,x2,x4,?..."
|
|
bitfld.long 0x04 14. " ASY_DEPOL ,Set based on the DE polarity" "POSITIVE_TRUE,NEGATIVE_TRUE"
|
|
bitfld.long 0x04 13. " ASY_VSYNCPOL ,Set based on the VSYNC polarity" "POSITIVE_TRUE,NEGATIVE_TRUE"
|
|
textline " "
|
|
bitfld.long 0x04 12. " ASY_HSYNCPOL ,Set based on the HSYNC" "POSITIVE_TRUE,NEGATIVE_TRUE"
|
|
bitfld.long 0x04 8.--11. " ASY_PROTOCOL ,Protocol" "LVDS_CUSTOM,,,,,,,,DP_A,DP_B,,,,,,CUSTOM"
|
|
bitfld.long 0x04 6.--7. " ASY_CRCMODE ,Controls the pixels (LVDS) or symbols (eDP) that get CRCed" "ACTIVE_RASTER,COMPLETE_RASTER,NON_ACTIVE_RASTER,?..."
|
|
bitfld.long 0x04 4.--5. " ASY_SUBOWNER ,Sub owner" "NONE,SUBHEAD0,SUBHEAD1,BOTH"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " ASY_OWNER ,Controls the display pipe connected to the SOR" "NONE,HEAD0,HEAD1,?..."
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "PDISP_HEAD_STATE0_0,Head Control Register"
|
|
bitfld.long 0x00 4.--5. " INTERLACED ,Interlaced mode" "PROGRESSIVE,INTERLACED,?..."
|
|
bitfld.long 0x00 3. " RANGECOMPRESS ,Compresses the range of an RGB signal" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DYNRANGE ,Dynamic range for the output" "VESA,CEA"
|
|
bitfld.long 0x00 0.--1. " COLORSPACE ,Colour space" "RGB,YUV_601,YUV_709,?..."
|
|
line.long 0x04 "PDISP_HEAD_STATE0_0,Head Control Register"
|
|
bitfld.long 0x04 4.--5. " INTERLACED ,Interlaced mode" "PROGRESSIVE,INTERLACED,?..."
|
|
bitfld.long 0x04 3. " RANGECOMPRESS ,Compresses the range of an RGB signal" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " DYNRANGE ,Dynamic range for the output" "VESA,CEA"
|
|
bitfld.long 0x04 0.--1. " COLORSPACE ,Colour space" "RGB,YUV_601,YUV_709,?..."
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "PDISP_HEAD_STATE1_0,Register sets the size of the raster"
|
|
hexmask.long.word 0x00 16.--30. 1. " VTOTAL ,Total number of lines in a frame of the raster"
|
|
hexmask.long.word 0x00 0.--14. 1. " HTOTAL ,Total number of pixels in a line of the raster"
|
|
line.long 0x04 "PDISP_HEAD_STATE1_0,Register sets the size of the raster"
|
|
hexmask.long.word 0x04 16.--30. 1. " VTOTAL ,Total number of lines in a frame of the raster"
|
|
hexmask.long.word 0x04 0.--14. 1. " HTOTAL ,Total number of pixels in a line of the raster"
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "PDISP_HEAD_STATE2_0,Register sets the location of the horizontal and vertical sync end"
|
|
hexmask.long.word 0x00 16.--30. 1. " VSYNC_END ,total number of lines after which vertical sync ends"
|
|
hexmask.long.word 0x00 0.--14. 1. " HSYNC_END ,total number of pixels after which horizontal sync ends"
|
|
line.long 0x04 "PDISP_HEAD_STATE2_0,Register sets the location of the horizontal and vertical sync end"
|
|
hexmask.long.word 0x04 16.--30. 1. " VSYNC_END ,total number of lines after which vertical sync ends"
|
|
hexmask.long.word 0x04 0.--14. 1. " HSYNC_END ,total number of pixels after which horizontal sync ends"
|
|
group.long 0x2C++0x07
|
|
line.long 0x00 "PDISP_HEAD_STATE3_0,Register sets the location of horizontal and vertical blank end"
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|
hexmask.long.word 0x00 16.--30. 1. " VBLANK_END ,total number of lines after which vertical sync ends"
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|
hexmask.long.word 0x00 0.--14. 1. " HBLANK_END ,Total number of pixels after which horizontal sync ends"
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|
line.long 0x04 "PDISP_HEAD_STATE3_0,Register sets the location of the horizontal and vertical sync end"
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|
hexmask.long.word 0x04 16.--30. 1. " VBLANK_END ,total number of lines after which vertical sync ends"
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|
hexmask.long.word 0x04 0.--14. 1. " HBLANK_END ,Total number of pixels after which horizontal sync ends"
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|
group.long 0x34++0x07
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|
line.long 0x00 "PDISP_HEAD_STATE4_0,Register sets the location of horizontal and vertical blank start"
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|
hexmask.long.word 0x00 16.--30. 1. " VBLANK_START ,total number of lines after which vertical sync start"
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hexmask.long.word 0x00 0.--14. 1. " HBLANK_START ,Total number of pixels after which horizontal sync start"
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line.long 0x04 "PDISP_HEAD_STATE4_0,Register sets the location of the horizontal and vertical sync start"
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|
hexmask.long.word 0x04 16.--30. 1. " VBLANK_START ,total number of lines after which vertical sync start"
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|
hexmask.long.word 0x04 0.--14. 1. " HBLANK_START ,Total number of pixels after which horizontal sync start"
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|
group.long 0x3C++0x07
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|
line.long 0x00 "PDISP_HEAD_STATE5_0,Register sets the location of horizontal and vertical blank ends (interlaced mode)"
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|
hexmask.long.word 0x00 16.--30. 1. " VBLANK_END_2 ,total number of lines after which vertical sync ends (interlaced mode)"
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|
hexmask.long.word 0x00 0.--14. 1. " HBLANK_END_2 ,Total number of pixels after which horizontal sync ends (interlaced mode)"
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|
line.long 0x04 "PDISP_HEAD_STATE5_0,Register sets the location of the horizontal and vertical sync ends2"
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|
hexmask.long.word 0x04 16.--30. 1. " VBLANK_END_2 ,total number of lines after which vertical sync ends (interlaced mode)"
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|
hexmask.long.word 0x04 0.--14. 1. " HBLANK_END_2 ,Total number of pixels after which horizontal sync ends (interlaced mode)"
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|
group.long 0x44++0x03
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|
line.long 0x00 "PDISP_SOR_CRC_CNTRL_0,CRC Control"
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|
bitfld.long 0x00 0. " ARM_CRC_ENABLE ,Enables computation of CRC" "Disabled,Enabled"
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|
textline " "
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|
width 27.
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|
rgroup.long 0x48++0x03
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|
line.long 0x00 "PDISP_SOR_DP_DEBUG_MVID_0,Report the MVID value calculated by HW"
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|
hexmask.long.tbyte 0x00 0.--23. 1. " VALUE ,MVID value calculated by HW"
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|
textline " "
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width 23.
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group.long 0x4C++0x03
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|
line.long 0x00 "PDISP_SOR_CLK_CNTRL_0,SOR clock control"
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|
bitfld.long 0x00 2.--6. " DP_LINK_SPEED ,Selects the multiplier used by the analog macro PLL" ",,,,,,G1_62,LVDS,,,G2_7,,,,,,,,,,G5_4,?..."
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|
bitfld.long 0x00 0.--1. " DP_CLK_SEL ,Selects which clock is used for the internal logic" "SINGLE_PCLK,DIFF_PCLK,SINGLE_DPCLK,DIFF_DPCLK"
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|
rgroup.long 0x50++0x03
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|
line.long 0x00 "PDISP_SOR_CAP_0,Register reports the innate capabilities of the SOR"
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|
bitfld.long 0x00 31. " LVDS_ONLY ,LVDS only" "False,True"
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|
bitfld.long 0x00 25. " DP_B ,DP B" "False,True"
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|
bitfld.long 0x00 24. " DP_A ,DP A" "False,True"
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|
bitfld.long 0x00 20. " DDI ,DDI" "False,True"
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|
textline " "
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|
bitfld.long 0x00 16. " SDI ,SDI" "False,True"
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|
bitfld.long 0x00 13. " DISPLAY_OVER_PCIE ,Display over PCIE" "False,True"
|
|
bitfld.long 0x00 12. " SINGLE_TMDS_225_MHZ ,Single tmds 225 Mhz" "False,True"
|
|
bitfld.long 0x00 11. " DUAL_TMDS ,Dual tmds" "False,True"
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|
textline " "
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|
bitfld.long 0x00 10. " DUAL_SINGLE_TMDS ,Dual single TMDS" "False,True"
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|
bitfld.long 0x00 9. " SINGLE_TMDS_B ,Single TMDS B" "False,True"
|
|
bitfld.long 0x00 8. " SINGLE_TMDS_A ,Single TMDS A" "False,True"
|
|
bitfld.long 0x00 3. " DUAL_LVDS_24 ,Dual LVDS 24" "False,True"
|
|
textline " "
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|
bitfld.long 0x00 2. " DUAL_LVDS_18 ,Dual LVDS 18" "False,True"
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|
bitfld.long 0x00 1. " SINGLE_LVDS_24 ,Single LVDS 24" "False,True"
|
|
bitfld.long 0x00 0. " SINGLE_LVDS_1 ,Single LVDS 1" "False,True"
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|
group.long 0x54++0x17
|
|
line.long 0x00 "PDISP_SOR_PWR_0,This register contains bits that control the power state of the SOR"
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|
eventfld.long 0x00 31. " SETTING_NEW ,This bit is used to trigger a new setting of power mode to take effect" "Done,Pending"
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|
rbitfld.long 0x00 28. " MODE ,The currently active state, normal or safe" "Normal,Safe"
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|
rbitfld.long 0x00 24. " HALT_DELAY ,Halt delay" "Done,Active"
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|
bitfld.long 0x00 17. " SAFE_START ,The execution of the powerup and powerdown sequence" "NORMAL,ALT"
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|
textline " "
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bitfld.long 0x00 16. " SAFE_STATE ,Sets the safe operating state" "PD,PU"
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|
bitfld.long 0x00 1. " NORMAL_START ,The execution of the powerup and powerdown sequence" "NORMAL,ALT"
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|
bitfld.long 0x00 0. " NORMAL_STATE ,Sets the normal operating state" "PD,PU"
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|
line.long 0x04 "NV_PDISP_SOR_TEST_0,These registers configure the main SOR PLL and other frequency dependent controls"
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|
hexmask.long.byte 0x04 24.--31. 1. " TESTMUX ,Test MUX select"
|
|
bitfld.long 0x04 23. " CRC ,The source of the data for CRC computation" "PRE_SERIALIZE,POST_DESERIALIZE"
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|
bitfld.long 0x04 20.--22. " TPAT ,Selects the test generator pattern" "LO,TDAT,RAMP,WALK,MAXSTEP,MINSTEP,?..."
|
|
bitfld.long 0x04 16.--17. " DSRC ,Serializes behave and use the encoded RGB data" "NORMAL,DEBUG,TGEN,?..."
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|
textline " "
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|
rbitfld.long 0x04 12.--15. " HEAD_NUMBER ,Report the display controller that the SOR is currently attached to" "NONE,HEAD0,HEAD1,?..."
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|
rbitfld.long 0x04 10. " ATTACHED ,Report whether the OR is currently attached to a head" "False,True"
|
|
rbitfld.long 0x04 8.--9. " ACT_HEAD_OPMODE ,Report the current OR operating mode" "SLEEP,SNOOZE,AWAKE,?..."
|
|
bitfld.long 0x04 6. " INVD ,Invert the data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TEST_ENABLE ,To enable testing" "Disabled,Enabled"
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|
line.long 0x08 "PDISP_SOR_PLL0_0,Configure SOR PLL and other frequency dependent controls register 0"
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bitfld.long 0x08 24.--27. " ICHPMP ,Specifies additions to the charge pump current in steps" "0.0uA,0.375uA,0.75uA,1.125uA,1.5uA,1.875uA,2.25uA,2.625uA,3.0uA,3.375uA,3.75uA,4.125uA,4.5uA,4.875uA,5.25uA,RST"
|
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bitfld.long 0x08 19. " FILTER[3] ,Controls the VCO startup bit for the TMDS_DUAL macro" "Normal operation,VCO oscillation mode"
|
|
bitfld.long 0x08 16.--18. " FILTER[2:0] ,Celect the loop filter and adjusts the filter resistor value" "RST,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 12.--13. " TXREG_LEVEL ,TXREG level" "V25,V15,V35,V45"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " VCOCAP ,Selects the VCO capacitor and adjusts ring oscillator inter-stage load" "0,1,2,RST,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 6.--7. " PLLREG_LEVEL ,PLLREG Level" "V25,V15,V35,V45"
|
|
bitfld.long 0x08 5. " PULLDOWN ,Weak pulldown enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " RESISTORSEL ,RESISTORSEL" "INT,EXT"
|
|
textline " "
|
|
bitfld.long 0x08 1. " VCOPD ,Powerdown the VCO" "RESCIND,ASSERT"
|
|
bitfld.long 0x08 0. " PWR ,Powerdown the TMDS PLL" "ON,OFF"
|
|
line.long 0x0C "PDISP_SOR_PLL1_0,Configure SOR PLL and other frequency dependent controls register 1"
|
|
bitfld.long 0x0C 29. " COHERENTMODE ,Output reference clock selector" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24.--25. " LVDSCM ,Common mode control for LVDS" "1.25V,1.30V,1.35V,1.20V"
|
|
bitfld.long 0x0C 20.--23. " LOADADJ ,Load pulse position adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
rbitfld.long 0x0C 15. " TERM_COMPOUT ,Termination calibration status" "Low,High"
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|
textline " "
|
|
bitfld.long 0x0C 9.--12. " TMDS_TERMADJ ,Termination resistance control" "Lowest,1,2,3,4,5,6,7,OHM500,9,10,11,12,13,14,Highest"
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bitfld.long 0x0C 8. " TMDS_TERM ,Enable termination" "Disabled,Enabled"
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|
bitfld.long 0x0C 0.--5. " IOCURRENT ,Used for I/O control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x10 "PDISP_SOR_PLL2_0,Configure SOR PLL and other frequency dependent controls register 2"
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bitfld.long 0x10 25. " AUX9 ,AUX9 (Overrides LVDSEN programmed by priv register)" "Allow,Override"
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bitfld.long 0x10 24. " AUX8 ,AUX8 (Power on enforcement for PLLCAPPD" "Disabled,Enabled)"
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bitfld.long 0x10 23. " AUX7 ,AUX7 (Controls PDPORT in the analog macro which powers down all the output links/lanes)" "Disabled,Enabled"
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bitfld.long 0x10 22. " AUX6 ,AUX6 (Main power down for bandgap and reference current setting circuitry)" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 21. " AUX5 ,AUX5 (Distinguish between single link and dual link LVDS)" "Single,Dual"
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bitfld.long 0x10 20. " AUX4 ,AUX4 (Enable duplicate controls for the Dual link HDCP)" "Disabled,Enabled"
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bitfld.long 0x10 19. " AUX3 ,AUX3 (Rotate grn channel by 1 bit to reduce tmds EMI)" "Disabled,Enabled"
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bitfld.long 0x10 18. " AUX2 ,AUX2 (Gate PDBG from sequencer_pd_macro)" "Override,Allow"
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textline " "
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bitfld.long 0x10 17. " AUX1 ,AUX1 (Power on override for PLLCAPPD)" "Allow,Override"
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bitfld.long 0x10 16. " AUX0 ,AUX0 (gate seq_2all_pll_pulldown from PULLDOWN)" "Allow,Override"
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bitfld.long 0x10 12.--15. " PLL_MDIV ,PLL MDIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8.--11. " PLL_NDIV ,PLL NDIV" "BY_3,BY_5,BY_6,BY_7,BY10,?..."
|
|
textline " "
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bitfld.long 0x10 4.--7. " PLL_PDIV ,PLL PDIV" "BY_1,BY_2,BY_2B,BY_4,?..."
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bitfld.long 0x10 1. " DIV_RATIO_OVERRIDE ,DIV ratio override," "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DCIR_PLL_RESET ,DCIR PLL reset" "Override,Allow"
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line.long 0x14 "PDISP_SOR_PLL3_0,Configure SOR PLL and other frequency dependent controls register 3"
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bitfld.long 0x14 28.--31. " BG_TEMP_COEF ,Control bits for the bandgap's temperature coefficient" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 24.--27. " BG_VREF_LEVEL ,Control bits for the bandgap's output voltages" "0.588V,0.602V,0.616V,0.630V,0.644V,0.658,0.672V,0.686,0.700V,0.714V,0.728V,0.742V,0.756V,0.770V,0.784V,0.798V"
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hexmask.long.byte 0x14 16.--23. 1. " TEST_REFCLK_EN ,Enable the TEST_REFCLK"
|
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bitfld.long 0x14 14. " PLL_BYPASS ,Enable the PLL bypass mode" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x14 13. " PLLVDD_MODE ,PLL voltage" "V1_8,V3_3"
|
|
bitfld.long 0x14 12. " CLKDIST_MODE ," "CMOS,CML"
|
|
bitfld.long 0x14 8.--11. " AVDD10_LEVEL ,Internal regulated 1.0V voltage level control bits" "V0_95,V1_00,V1_05,V1_10,?..."
|
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bitfld.long 0x14 4.--7. " AVDD14_LEVEL ,Internal regulated 1.4V voltage level control bits" "V1_35,V1_40,V1_45,V1_50,?..."
|
|
textline " "
|
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bitfld.long 0x14 0.--1. " KICKSTART ,Kickstart" "Disabled,LOOP_40,LOOP_50,LOOP_60"
|
|
if ((d.l(ad:0x54540000+0x50)&0x8000000)==0x00)
|
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group.long 0x6C++0x03
|
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line.long 0x00 "PDISP_SOR_CSTM_0,Configuration register modes for the SOR"
|
|
bitfld.long 0x00 28.--30. " ROTDAT ,Specifies input channel data" "0,1,2,3,4,5,6,7"
|
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bitfld.long 0x00 24.--27. " ROTCLK ,Specifies the number of sclk cycles which the output clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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bitfld.long 0x00 21. " PLLDIV ,Controls the internal clock dividers of the TMDS_MACRO" "BY_7,BY_10"
|
|
bitfld.long 0x00 19. " BALANCED ,Enables balanced encoding Balanced mode" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x00 18. " NEW_MODE ,Enable New Mode" "Disabled,Enabled"
|
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bitfld.long 0x00 17. " DUP_SYNC ,Forces the link to use DE, HSYNC, and VSYNC enable in LVDS mode" "Disabled,Enabled"
|
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bitfld.long 0x00 16. " LVDS_EN ,Encoding of the data and the output" "TMDS,LVDS"
|
|
bitfld.long 0x00 15. " LINKACTB ,Enable the digital logic of links B" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x00 14. " LINKACTA ,Enable the digital logic of links A" "Disabled,Enabled"
|
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bitfld.long 0x00 12.--13. " MODE ,Controls the digital output encoding applied to the data stream in custom mode" "LVDS,DP,?..."
|
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bitfld.long 0x00 11. " UPPER ,Designates whether LVDS bank A is the upper, odd, or first pixel" "False,True"
|
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bitfld.long 0x00 9. " PD_TXCB ,Power down the clock pin of link B" "Power up,Power down"
|
|
textline " "
|
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bitfld.long 0x00 8. " PD_TXCA ,Power down the clock pin of link A" "Power up,Power down"
|
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bitfld.long 0x00 7. " PD_TXDB_3 ,Bitwise control to power down the data pins 3 of link B" "Power up,Power down"
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bitfld.long 0x00 6. " PD_TXDB_2 ,Bitwise control to power down the data pins 2 of link B" "Power up,Power down"
|
|
bitfld.long 0x00 5. " PD_TXDB_1 ,Bitwise control to power down the data pins 1 of link B" "Power up,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PD_TXDB_0 ,Bitwise control to power down the data pins 0 of link B" "Power up,Power down"
|
|
bitfld.long 0x00 3. " PD_TXDA_3 ,Bitwise control to power down the data pins 3 of link A" "Power up,Power down"
|
|
bitfld.long 0x00 2. " PD_TXDA_2 ,Bitwise control to power down the data pins 2 of link A" "Power up,Power down"
|
|
bitfld.long 0x00 1. " PD_TXDA_1 ,Bitwise control to power down the data pins 1 of link A" "Power up,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PD_TXDA_0 ,Bitwise control to power down the data pins 0 of link A" "Power up,Power down"
|
|
else
|
|
hgroup.long 0x6C++0x0B
|
|
hide.long 0x00 "PDISP_SOR_CSTM_0,Configuration register modes for the SOR"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "PDISP_SOR_LVDS_0,The second register defines the LVDS custom mode"
|
|
bitfld.long 0x00 28.--30. " ROTDAT ,Specifies input channel data" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--27. " ROTCLK ,Specifies the number of sclk cycles which the output clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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rbitfld.long 0x00 21. " PLLDIV ,Controls the internal clock dividers of the TMDS_MACRO" "BY_7,BY_10"
|
|
bitfld.long 0x00 19. " BALANCED ,Enables balanced encoding Balanced mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " NEW_MODE ,Enable New Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DUP_SYNC ,Forces the link to use DE, HSYNC, and VSYNC enable in LVDS mode" "Not SYNC,SYNC"
|
|
rbitfld.long 0x00 16. " LVDS_EN ,Encoding of the data and the output" "TMDS,LVDS"
|
|
bitfld.long 0x00 15. " LINKACTB ,Enable the digital logic of links B" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 14. " LINKACTA ,Enable the digital logic of links A" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12.--13. " MODE ,Controls the digital output encoding applied to the data stream in custom mode" "LVDS,?..."
|
|
rbitfld.long 0x00 11. " UPPER ,Designates whether LVDS bank A is the upper, odd, or first pixel" "False,True"
|
|
bitfld.long 0x00 9. " PD_TXCB ,Power down the clock pin of link B" "Power up,Power down"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " PD_TXCA ,Power down the clock pin of link A" "Power up,Power down"
|
|
bitfld.long 0x00 7. " PD_TXDB_3 ,Bitwise control to power down the data pins 3 of link B" "Power up,Power down"
|
|
bitfld.long 0x00 6. " PD_TXDB_2 ,Bitwise control to power down the data pins 2 of link B" "Power up,Power down"
|
|
bitfld.long 0x00 5. " PD_TXDB_1 ,Bitwise control to power down the data pins 1 of link B" "Power up,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PD_TXDB_0 ,Bitwise control to power down the data pins 0 of link B" "Power up,Power down"
|
|
bitfld.long 0x00 3. " PD_TXDA_3 ,Bitwise control to power down the data pins 3 of link A" "Power up,Power down"
|
|
rbitfld.long 0x00 2. " PD_TXDA_2 ,Bitwise control to power down the data pins 2 of link A" "Power up,Power down"
|
|
rbitfld.long 0x00 1. " PD_TXDA_1 ,Bitwise control to power down the data pins 1 of link A" "Power up,Power down"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " PD_TXDA_0 ,Bitwise control to power down the data pins 0 of link A" "Power up,Power down"
|
|
line.long 0x04 "PDISP_SOR_CRCA_0,Registers A are used to fetch CRC"
|
|
eventfld.long 0x04 0. " VALID ,Valid" "False,True"
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "CRC,PDISP_SOR_CRCB_0,Registers B are used to fetch CRC"
|
|
textline " "
|
|
width 26.
|
|
group.long 0x7C++0xb
|
|
line.long 0x00 "PDISP_SOR_BLANK_0,Register used to override the SOR output resource pixels with blank data"
|
|
rbitfld.long 0x00 2. " STATUS ,Status of output resource" "Not blanked,Blanked"
|
|
bitfld.long 0x00 1. " TRANSITION ,Controls the timing of the output resource blank override" "IMMEDIATE,NEXT_VSYNC"
|
|
bitfld.long 0x00 0. " OVERRIDE ,Override the pixel bus from the RG and output black pixels instead" "Not blanked,Blanked"
|
|
line.long 0x04 "PDISP_SOR_SEQ_CTL_0,Sequencer control registers for SOR"
|
|
bitfld.long 0x04 30. " SWITCH ,SWITCH" "Wait,Force"
|
|
rbitfld.long 0x04 28. " STATUS ,Indicates if the sequencer is STOPPED or RUNNING" "Stopped,Running"
|
|
rbitfld.long 0x04 16.--19. " PC ,The current value of the program counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 12.--15. " PD_PC_ALT ,The alternate entry point into the powerdown program sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " PD_PC ,The program counter for the start of the powerdown program sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " PU_PC_ALT ,The alternate entry point into the powerup program sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PDISP_SOR_LANE_SEQ_CTL_0,Register is used to control the operation of the SOR lane sequencer"
|
|
bitfld.long 0x08 31. " SETTING_NEW ,Run this sequencer outside of the normal SOR sequencer operation" "Done,Pending"
|
|
rbitfld.long 0x08 28. " SEQ_STATE ,Whenever this sequencer is running this field will be set to BUSY" "Idle,Busy"
|
|
bitfld.long 0x08 20. " SEQUENCE ,Controls the direction of the power up or power down sequence" "Up,Down"
|
|
bitfld.long 0x08 16. " NEW_POWER_STATE ,Controls whether the lanes should be powered up or powered down" "PU,PD"
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " DELAY ,Number of microseconds to delay between each lanes' power state change" "0us,1us,2us,3us,4us,5us,6us,7us,8us,9us,10us,11us,12us,13us,14us,15us"
|
|
rbitfld.long 0x08 9. " LANE9_STATE ,Status of 9 lane's power" "Power up,Power down"
|
|
rbitfld.long 0x08 8. " LANE8_STATE ,Status of 8 lane's power" "Power up,Power down"
|
|
rbitfld.long 0x08 7. " LANE7_STATE ,Status of 7 lane's power" "Power up,Power down"
|
|
textline " "
|
|
rbitfld.long 0x08 6. " LANE6_STATE ,Status of 6 lane's power" "Power up,Power down"
|
|
rbitfld.long 0x08 5. " LANE5_STATE ,Status of 5 lane's power" "Power up,Power down"
|
|
rbitfld.long 0x08 4. " LANE4_STATE ,Status of 4 lane's power" "Power up,Power down"
|
|
rbitfld.long 0x08 3. " LANE3_STATE ,Status of 3 lane's power" "Power up,Power down"
|
|
textline " "
|
|
rbitfld.long 0x08 2. " LANE2_STATE ,Status of 2 lane's power" "Power up,Power down"
|
|
rbitfld.long 0x08 1. " LANE1_STATE ,Status of 1 lane's power" "Power up,Power down"
|
|
rbitfld.long 0x08 0. " LANE0_STATE ,Status of 0 lane's power" "Power up,Power down"
|
|
width 23.
|
|
tree "Power up/down sequencer registers"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PDISP_SOR_SEQ_INST0_0,Preload the power-up and power-down sequences register 0"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,Weak pulldown enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,Override LINKACTA LINKACTB and force LVDS/TMDS macro to powerdown state" "Normal,Powerdown"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESET ,Assert reset to the PLL" "Normal,RST"
|
|
bitfld.long 0x00 28. " BLANK_V ,Override the vsync signals from the rg" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,Override the hsync signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,Override the de signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,Override the pixel bus from the RG and replace the pixels with black" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,Force all output pins to tristate" "Enable Pins,Tristate"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,Drive the PWM circuit output low" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,State to drive the external pin B to" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,State to drive the external pin A to" "Low,High"
|
|
bitfld.long 0x00 19. " SEQUENCE ,Controls the direction of the lane power up or power down sequence" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LANE_SEQ ,When set to _RUN, the sequencer will kick off the Lane Sequencer" "Stop,Run"
|
|
bitfld.long 0x00 17. " PDPORT ,Asserts the PDPORT port on the SOR analog macro" "No,yes"
|
|
bitfld.long 0x00 16. " PDPLL ,Asserts the PDPLL port on the analog macro, powering down the PLL" "No,yes"
|
|
bitfld.long 0x00 15. " HALT ,Halt" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,Wait delay mode, us, ms, vsync" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,Amount of time to wait"
|
|
textline " "
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PDISP_SOR_SEQ_INST1_0,Preload the power-up and power-down sequences register 1"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,Weak pulldown enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,Override LINKACTA LINKACTB and force LVDS/TMDS macro to powerdown state" "Normal,Powerdown"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESET ,Assert reset to the PLL" "Normal,RST"
|
|
bitfld.long 0x00 28. " BLANK_V ,Override the vsync signals from the rg" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,Override the hsync signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,Override the de signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,Override the pixel bus from the RG and replace the pixels with black" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,Force all output pins to tristate" "Enable Pins,Tristate"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,Drive the PWM circuit output low" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,State to drive the external pin B to" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,State to drive the external pin A to" "Low,High"
|
|
bitfld.long 0x00 19. " SEQUENCE ,Controls the direction of the lane power up or power down sequence" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LANE_SEQ ,When set to _RUN, the sequencer will kick off the Lane Sequencer" "Stop,Run"
|
|
bitfld.long 0x00 17. " PDPORT ,Asserts the PDPORT port on the SOR analog macro" "No,yes"
|
|
bitfld.long 0x00 16. " PDPLL ,Asserts the PDPLL port on the analog macro, powering down the PLL" "No,yes"
|
|
bitfld.long 0x00 15. " HALT ,Halt" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,Wait delay mode, us, ms, vsync" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,Amount of time to wait"
|
|
textline " "
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PDISP_SOR_SEQ_INST2_0,Preload the power-up and power-down sequences register 2"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,Weak pulldown enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,Override LINKACTA LINKACTB and force LVDS/TMDS macro to powerdown state" "Normal,Powerdown"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESET ,Assert reset to the PLL" "Normal,RST"
|
|
bitfld.long 0x00 28. " BLANK_V ,Override the vsync signals from the rg" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,Override the hsync signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,Override the de signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,Override the pixel bus from the RG and replace the pixels with black" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,Force all output pins to tristate" "Enable Pins,Tristate"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,Drive the PWM circuit output low" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,State to drive the external pin B to" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,State to drive the external pin A to" "Low,High"
|
|
bitfld.long 0x00 19. " SEQUENCE ,Controls the direction of the lane power up or power down sequence" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LANE_SEQ ,When set to _RUN, the sequencer will kick off the Lane Sequencer" "Stop,Run"
|
|
bitfld.long 0x00 17. " PDPORT ,Asserts the PDPORT port on the SOR analog macro" "No,yes"
|
|
bitfld.long 0x00 16. " PDPLL ,Asserts the PDPLL port on the analog macro, powering down the PLL" "No,yes"
|
|
bitfld.long 0x00 15. " HALT ,Halt" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,Wait delay mode, us, ms, vsync" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,Amount of time to wait"
|
|
textline " "
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "PDISP_SOR_SEQ_INST3_0,Preload the power-up and power-down sequences register 3"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,Weak pulldown enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,Override LINKACTA LINKACTB and force LVDS/TMDS macro to powerdown state" "Normal,Powerdown"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESET ,Assert reset to the PLL" "Normal,RST"
|
|
bitfld.long 0x00 28. " BLANK_V ,Override the vsync signals from the rg" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,Override the hsync signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,Override the de signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,Override the pixel bus from the RG and replace the pixels with black" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,Force all output pins to tristate" "Enable Pins,Tristate"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,Drive the PWM circuit output low" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,State to drive the external pin B to" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,State to drive the external pin A to" "Low,High"
|
|
bitfld.long 0x00 19. " SEQUENCE ,Controls the direction of the lane power up or power down sequence" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LANE_SEQ ,When set to _RUN, the sequencer will kick off the Lane Sequencer" "Stop,Run"
|
|
bitfld.long 0x00 17. " PDPORT ,Asserts the PDPORT port on the SOR analog macro" "No,yes"
|
|
bitfld.long 0x00 16. " PDPLL ,Asserts the PDPLL port on the analog macro, powering down the PLL" "No,yes"
|
|
bitfld.long 0x00 15. " HALT ,Halt" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,Wait delay mode, us, ms, vsync" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,Amount of time to wait"
|
|
textline " "
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PDISP_SOR_SEQ_INST4_0,Preload the power-up and power-down sequences register 4"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,Weak pulldown enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,Override LINKACTA LINKACTB and force LVDS/TMDS macro to powerdown state" "Normal,Powerdown"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESET ,Assert reset to the PLL" "Normal,RST"
|
|
bitfld.long 0x00 28. " BLANK_V ,Override the vsync signals from the rg" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,Override the hsync signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,Override the de signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,Override the pixel bus from the RG and replace the pixels with black" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,Force all output pins to tristate" "Enable Pins,Tristate"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,Drive the PWM circuit output low" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,State to drive the external pin B to" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,State to drive the external pin A to" "Low,High"
|
|
bitfld.long 0x00 19. " SEQUENCE ,Controls the direction of the lane power up or power down sequence" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LANE_SEQ ,When set to _RUN, the sequencer will kick off the Lane Sequencer" "Stop,Run"
|
|
bitfld.long 0x00 17. " PDPORT ,Asserts the PDPORT port on the SOR analog macro" "No,yes"
|
|
bitfld.long 0x00 16. " PDPLL ,Asserts the PDPLL port on the analog macro, powering down the PLL" "No,yes"
|
|
bitfld.long 0x00 15. " HALT ,Halt" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,Wait delay mode, us, ms, vsync" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,Amount of time to wait"
|
|
textline " "
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "PDISP_SOR_SEQ_INST5_0,Preload the power-up and power-down sequences register 5"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,Weak pulldown enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,Override LINKACTA LINKACTB and force LVDS/TMDS macro to powerdown state" "Normal,Powerdown"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESET ,Assert reset to the PLL" "Normal,RST"
|
|
bitfld.long 0x00 28. " BLANK_V ,Override the vsync signals from the rg" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,Override the hsync signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,Override the de signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,Override the pixel bus from the RG and replace the pixels with black" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,Force all output pins to tristate" "Enable Pins,Tristate"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,Drive the PWM circuit output low" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,State to drive the external pin B to" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,State to drive the external pin A to" "Low,High"
|
|
bitfld.long 0x00 19. " SEQUENCE ,Controls the direction of the lane power up or power down sequence" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LANE_SEQ ,When set to _RUN, the sequencer will kick off the Lane Sequencer" "Stop,Run"
|
|
bitfld.long 0x00 17. " PDPORT ,Asserts the PDPORT port on the SOR analog macro" "No,yes"
|
|
bitfld.long 0x00 16. " PDPLL ,Asserts the PDPLL port on the analog macro, powering down the PLL" "No,yes"
|
|
bitfld.long 0x00 15. " HALT ,Halt" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,Wait delay mode, us, ms, vsync" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,Amount of time to wait"
|
|
textline " "
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PDISP_SOR_SEQ_INST6_0,Preload the power-up and power-down sequences register 6"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,Weak pulldown enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,Override LINKACTA LINKACTB and force LVDS/TMDS macro to powerdown state" "Normal,Powerdown"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESET ,Assert reset to the PLL" "Normal,RST"
|
|
bitfld.long 0x00 28. " BLANK_V ,Override the vsync signals from the rg" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,Override the hsync signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,Override the de signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,Override the pixel bus from the RG and replace the pixels with black" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,Force all output pins to tristate" "Enable Pins,Tristate"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,Drive the PWM circuit output low" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,State to drive the external pin B to" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,State to drive the external pin A to" "Low,High"
|
|
bitfld.long 0x00 19. " SEQUENCE ,Controls the direction of the lane power up or power down sequence" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LANE_SEQ ,When set to _RUN, the sequencer will kick off the Lane Sequencer" "Stop,Run"
|
|
bitfld.long 0x00 17. " PDPORT ,Asserts the PDPORT port on the SOR analog macro" "No,yes"
|
|
bitfld.long 0x00 16. " PDPLL ,Asserts the PDPLL port on the analog macro, powering down the PLL" "No,yes"
|
|
bitfld.long 0x00 15. " HALT ,Halt" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,Wait delay mode, us, ms, vsync" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,Amount of time to wait"
|
|
textline " "
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "PDISP_SOR_SEQ_INST7_0,Preload the power-up and power-down sequences register 7"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,Weak pulldown enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,Override LINKACTA LINKACTB and force LVDS/TMDS macro to powerdown state" "Normal,Powerdown"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESET ,Assert reset to the PLL" "Normal,RST"
|
|
bitfld.long 0x00 28. " BLANK_V ,Override the vsync signals from the rg" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,Override the hsync signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,Override the de signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,Override the pixel bus from the RG and replace the pixels with black" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,Force all output pins to tristate" "Enable Pins,Tristate"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,Drive the PWM circuit output low" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,State to drive the external pin B to" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,State to drive the external pin A to" "Low,High"
|
|
bitfld.long 0x00 19. " SEQUENCE ,Controls the direction of the lane power up or power down sequence" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LANE_SEQ ,When set to _RUN, the sequencer will kick off the Lane Sequencer" "Stop,Run"
|
|
bitfld.long 0x00 17. " PDPORT ,Asserts the PDPORT port on the SOR analog macro" "No,yes"
|
|
bitfld.long 0x00 16. " PDPLL ,Asserts the PDPLL port on the analog macro, powering down the PLL" "No,yes"
|
|
bitfld.long 0x00 15. " HALT ,Halt" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,Wait delay mode, us, ms, vsync" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,Amount of time to wait"
|
|
textline " "
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PDISP_SOR_SEQ_INST8_0,Preload the power-up and power-down sequences register 8"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,Weak pulldown enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,Override LINKACTA LINKACTB and force LVDS/TMDS macro to powerdown state" "Normal,Powerdown"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESET ,Assert reset to the PLL" "Normal,RST"
|
|
bitfld.long 0x00 28. " BLANK_V ,Override the vsync signals from the rg" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,Override the hsync signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,Override the de signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,Override the pixel bus from the RG and replace the pixels with black" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,Force all output pins to tristate" "Enable Pins,Tristate"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,Drive the PWM circuit output low" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,State to drive the external pin B to" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,State to drive the external pin A to" "Low,High"
|
|
bitfld.long 0x00 19. " SEQUENCE ,Controls the direction of the lane power up or power down sequence" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LANE_SEQ ,When set to _RUN, the sequencer will kick off the Lane Sequencer" "Stop,Run"
|
|
bitfld.long 0x00 17. " PDPORT ,Asserts the PDPORT port on the SOR analog macro" "No,yes"
|
|
bitfld.long 0x00 16. " PDPLL ,Asserts the PDPLL port on the analog macro, powering down the PLL" "No,yes"
|
|
bitfld.long 0x00 15. " HALT ,Halt" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,Wait delay mode, us, ms, vsync" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,Amount of time to wait"
|
|
textline " "
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "PDISP_SOR_SEQ_INST9_0,Preload the power-up and power-down sequences register 9"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,Weak pulldown enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,Override LINKACTA LINKACTB and force LVDS/TMDS macro to powerdown state" "Normal,Powerdown"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESET ,Assert reset to the PLL" "Normal,RST"
|
|
bitfld.long 0x00 28. " BLANK_V ,Override the vsync signals from the rg" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,Override the hsync signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,Override the de signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,Override the pixel bus from the RG and replace the pixels with black" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,Force all output pins to tristate" "Enable Pins,Tristate"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,Drive the PWM circuit output low" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,State to drive the external pin B to" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,State to drive the external pin A to" "Low,High"
|
|
bitfld.long 0x00 19. " SEQUENCE ,Controls the direction of the lane power up or power down sequence" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LANE_SEQ ,When set to _RUN, the sequencer will kick off the Lane Sequencer" "Stop,Run"
|
|
bitfld.long 0x00 17. " PDPORT ,Asserts the PDPORT port on the SOR analog macro" "No,yes"
|
|
bitfld.long 0x00 16. " PDPLL ,Asserts the PDPLL port on the analog macro, powering down the PLL" "No,yes"
|
|
bitfld.long 0x00 15. " HALT ,Halt" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,Wait delay mode, us, ms, vsync" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,Amount of time to wait"
|
|
textline " "
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "PDISP_SOR_SEQ_INSTA_0,Preload the power-up and power-down sequences register A"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,Weak pulldown enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,Override LINKACTA LINKACTB and force LVDS/TMDS macro to powerdown state" "Normal,Powerdown"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESET ,Assert reset to the PLL" "Normal,RST"
|
|
bitfld.long 0x00 28. " BLANK_V ,Override the vsync signals from the rg" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,Override the hsync signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,Override the de signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,Override the pixel bus from the RG and replace the pixels with black" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,Force all output pins to tristate" "Enable Pins,Tristate"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,Drive the PWM circuit output low" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,State to drive the external pin B to" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,State to drive the external pin A to" "Low,High"
|
|
bitfld.long 0x00 19. " SEQUENCE ,Controls the direction of the lane power up or power down sequence" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LANE_SEQ ,When set to _RUN, the sequencer will kick off the Lane Sequencer" "Stop,Run"
|
|
bitfld.long 0x00 17. " PDPORT ,Asserts the PDPORT port on the SOR analog macro" "No,yes"
|
|
bitfld.long 0x00 16. " PDPLL ,Asserts the PDPLL port on the analog macro, powering down the PLL" "No,yes"
|
|
bitfld.long 0x00 15. " HALT ,Halt" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,Wait delay mode, us, ms, vsync" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,Amount of time to wait"
|
|
textline " "
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "PDISP_SOR_SEQ_INSTB_0,Preload the power-up and power-down sequences register B"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,Weak pulldown enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,Override LINKACTA LINKACTB and force LVDS/TMDS macro to powerdown state" "Normal,Powerdown"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESET ,Assert reset to the PLL" "Normal,RST"
|
|
bitfld.long 0x00 28. " BLANK_V ,Override the vsync signals from the rg" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,Override the hsync signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,Override the de signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,Override the pixel bus from the RG and replace the pixels with black" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,Force all output pins to tristate" "Enable Pins,Tristate"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,Drive the PWM circuit output low" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,State to drive the external pin B to" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,State to drive the external pin A to" "Low,High"
|
|
bitfld.long 0x00 19. " SEQUENCE ,Controls the direction of the lane power up or power down sequence" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LANE_SEQ ,When set to _RUN, the sequencer will kick off the Lane Sequencer" "Stop,Run"
|
|
bitfld.long 0x00 17. " PDPORT ,Asserts the PDPORT port on the SOR analog macro" "No,yes"
|
|
bitfld.long 0x00 16. " PDPLL ,Asserts the PDPLL port on the analog macro, powering down the PLL" "No,yes"
|
|
bitfld.long 0x00 15. " HALT ,Halt" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,Wait delay mode, us, ms, vsync" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,Amount of time to wait"
|
|
textline " "
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PDISP_SOR_SEQ_INSTC_0,Preload the power-up and power-down sequences register C"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,Weak pulldown enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,Override LINKACTA LINKACTB and force LVDS/TMDS macro to powerdown state" "Normal,Powerdown"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESET ,Assert reset to the PLL" "Normal,RST"
|
|
bitfld.long 0x00 28. " BLANK_V ,Override the vsync signals from the rg" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,Override the hsync signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,Override the de signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,Override the pixel bus from the RG and replace the pixels with black" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,Force all output pins to tristate" "Enable Pins,Tristate"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,Drive the PWM circuit output low" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,State to drive the external pin B to" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,State to drive the external pin A to" "Low,High"
|
|
bitfld.long 0x00 19. " SEQUENCE ,Controls the direction of the lane power up or power down sequence" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LANE_SEQ ,When set to _RUN, the sequencer will kick off the Lane Sequencer" "Stop,Run"
|
|
bitfld.long 0x00 17. " PDPORT ,Asserts the PDPORT port on the SOR analog macro" "No,yes"
|
|
bitfld.long 0x00 16. " PDPLL ,Asserts the PDPLL port on the analog macro, powering down the PLL" "No,yes"
|
|
bitfld.long 0x00 15. " HALT ,Halt" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,Wait delay mode, us, ms, vsync" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,Amount of time to wait"
|
|
textline " "
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "PDISP_SOR_SEQ_INSTD_0,Preload the power-up and power-down sequences register D"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,Weak pulldown enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,Override LINKACTA LINKACTB and force LVDS/TMDS macro to powerdown state" "Normal,Powerdown"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESET ,Assert reset to the PLL" "Normal,RST"
|
|
bitfld.long 0x00 28. " BLANK_V ,Override the vsync signals from the rg" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,Override the hsync signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,Override the de signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,Override the pixel bus from the RG and replace the pixels with black" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,Force all output pins to tristate" "Enable Pins,Tristate"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,Drive the PWM circuit output low" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,State to drive the external pin B to" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,State to drive the external pin A to" "Low,High"
|
|
bitfld.long 0x00 19. " SEQUENCE ,Controls the direction of the lane power up or power down sequence" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LANE_SEQ ,When set to _RUN, the sequencer will kick off the Lane Sequencer" "Stop,Run"
|
|
bitfld.long 0x00 17. " PDPORT ,Asserts the PDPORT port on the SOR analog macro" "No,yes"
|
|
bitfld.long 0x00 16. " PDPLL ,Asserts the PDPLL port on the analog macro, powering down the PLL" "No,yes"
|
|
bitfld.long 0x00 15. " HALT ,Halt" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,Wait delay mode, us, ms, vsync" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,Amount of time to wait"
|
|
textline " "
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "PDISP_SOR_SEQ_INSTE_0,Preload the power-up and power-down sequences register E"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,Weak pulldown enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,Override LINKACTA LINKACTB and force LVDS/TMDS macro to powerdown state" "Normal,Powerdown"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESET ,Assert reset to the PLL" "Normal,RST"
|
|
bitfld.long 0x00 28. " BLANK_V ,Override the vsync signals from the rg" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,Override the hsync signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,Override the de signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,Override the pixel bus from the RG and replace the pixels with black" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,Force all output pins to tristate" "Enable Pins,Tristate"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,Drive the PWM circuit output low" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,State to drive the external pin B to" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,State to drive the external pin A to" "Low,High"
|
|
bitfld.long 0x00 19. " SEQUENCE ,Controls the direction of the lane power up or power down sequence" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LANE_SEQ ,When set to _RUN, the sequencer will kick off the Lane Sequencer" "Stop,Run"
|
|
bitfld.long 0x00 17. " PDPORT ,Asserts the PDPORT port on the SOR analog macro" "No,yes"
|
|
bitfld.long 0x00 16. " PDPLL ,Asserts the PDPLL port on the analog macro, powering down the PLL" "No,yes"
|
|
bitfld.long 0x00 15. " HALT ,Halt" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,Wait delay mode, us, ms, vsync" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,Amount of time to wait"
|
|
textline " "
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "PDISP_SOR_SEQ_INSTF_0,Preload the power-up and power-down sequences register F"
|
|
bitfld.long 0x00 31. " PLL_PULLDOWN ,Weak pulldown enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " POWERDOWN_MACRO ,Override LINKACTA LINKACTB and force LVDS/TMDS macro to powerdown state" "Normal,Powerdown"
|
|
bitfld.long 0x00 29. " ASSERT_PLL_RESET ,Assert reset to the PLL" "Normal,RST"
|
|
bitfld.long 0x00 28. " BLANK_V ,Override the vsync signals from the rg" "Normal,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BLANK_H ,Override the hsync signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 26. " BLANK_DE ,Override the de signals from the rg" "Normal,Inactive"
|
|
bitfld.long 0x00 25. " BLACK_DATA ,Override the pixel bus from the RG and replace the pixels with black" "Normal,Black"
|
|
bitfld.long 0x00 24. " TRISTATE_IOS ,Force all output pins to tristate" "Enable Pins,Tristate"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DRIVE_PWM_OUT_LO ,Drive the PWM circuit output low" "False,True"
|
|
bitfld.long 0x00 22. " PIN_B ,State to drive the external pin B to" "Low,High"
|
|
bitfld.long 0x00 21. " PIN_A ,State to drive the external pin A to" "Low,High"
|
|
bitfld.long 0x00 19. " SEQUENCE ,Controls the direction of the lane power up or power down sequence" "Up,Down"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LANE_SEQ ,When set to _RUN, the sequencer will kick off the Lane Sequencer" "Stop,Run"
|
|
bitfld.long 0x00 17. " PDPORT ,Asserts the PDPORT port on the SOR analog macro" "No,yes"
|
|
bitfld.long 0x00 16. " PDPLL ,Asserts the PDPLL port on the analog macro, powering down the PLL" "No,yes"
|
|
bitfld.long 0x00 15. " HALT ,Halt" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " WAIT_UNITS ,Wait delay mode, us, ms, vsync" "US,MS,VSYNC,"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAIT_TIME ,Amount of time to wait"
|
|
textline " "
|
|
group.long 0xC8++0x07
|
|
line.long 0x00 "PDISP_SOR_PWM_DIV_0,register prescales the crystal clock and sets the resolution range"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " DIVIDE ,Period of the PWM output"
|
|
line.long 0x04 "PDISP_SOR_PWM_CTL_0,Control the optional PWM function for backlight intensity control"
|
|
bitfld.long 0x04 31. " SETTING_NEW ,Mechanism to trigger a new configuration for both registers" "Done,Pending"
|
|
bitfld.long 0x04 30. " CLKSEL ,SOR PWM can be run at pixel clock" "PCLK,XTAL"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUTY_CYCLE ,Duty cycle of the PWM output"
|
|
tree.end
|
|
width 22.
|
|
tree "Test and debug registers"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "PDISP_SOR_VCRCA0_0,The VCRCA registers for sub-link"
|
|
hexmask.long.word 0x00 16.--31. 1. " CRCM ,CRCM Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CRCL ,CRCL Value"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "PDISP_SOR_VCRCB0_0,The VCRCB registers for sub-link"
|
|
hexmask.long.word 0x00 16.--31. 1. " CRCM ,CRCM Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CRCL ,CRCL Value"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "PDISP_SOR_CCRCA0_0,The CCRCA registers for sub-link"
|
|
hexmask.long.word 0x00 16.--31. 1. " CRCM ,CRCM Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CRCL ,CRCL Value"
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "PDISP_SOR_CCRCB0_0,The CCRCB registers for sub-link"
|
|
hexmask.long.word 0x00 16.--31. 1. " CRCM ,CRCM Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CRCL ,CRCL Value"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "PDISP_SOR_EDATAA0_0,The EDATA registers for sub-link A"
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "PDISP_SOR_EDATAB0_0,The EDATA registers for sub-link B"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "PDISP_SOR_COUNTA0_0,The count registers for sub-link A"
|
|
hexmask.long.word 0x00 16.--31. 1. " TX1 ,TX1 Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " TX0 ,TX0 Counter"
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "PDISP_SOR_COUNTB0_0,The count registers for sub-link B"
|
|
hexmask.long.word 0x00 16.--31. 1. " TX1 ,TX1 Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " TX0 ,TX0 Counter"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PDISP_SOR_DEBUGA0_0,The debug registers for sub-link A"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "PDISP_SOR_DEBUGB0_0,The debug registers for sub-link B"
|
|
group.long 0x120++0x07
|
|
line.long 0x00 "PDISP_SOR_TRIG_0,TRIG specifies the number of pixel clock cycles was detected to capture state data"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " VAL ,Number of pixel clock cycles"
|
|
line.long 0x04 "PDISP_SOR_MSCHECK_0,Mode switch monitor"
|
|
bitfld.long 0x04 31. " CTL ,Control test bit" "Clear,Run"
|
|
rbitfld.long 0x04 12.--15. " DATA_ENABLE_T2F ,data enable went from true to false" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 8.--11. " DATA_ENABLE_F2T ,data enable went from false to true" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 4.--7. " CRC_ENABLE_T2F ,CRC enable went from true to false" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 0.--3. " CRC_ENABLE_F2T ,CRC enable went from false to true" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 23.
|
|
textline " "
|
|
group.long 0x128++0x07
|
|
line.long 0x00 "PDISP_SOR_XBAR_CTRL_0,Register controls the crossbar between the SOR and the TMDS analog macro"
|
|
bitfld.long 0x00 29.--31. " LINK1_XSEL_4 ,Crossbar output driver" "0,1,2,3,4,5,6,0"
|
|
bitfld.long 0x00 26.--28. " LINK1_XSEL_3 ,Crossbar output driver" "0,1,2,3,4,5,6,0"
|
|
bitfld.long 0x00 23.--25. " LINK1_XSEL_2 ,Crossbar output driver" "0,1,2,3,4,5,6,0"
|
|
bitfld.long 0x00 20.--22. " LINK1_XSEL_1 ,Crossbar output driver" "0,1,2,3,4,5,6,0"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " LINK1_XSEL_0 ,Crossbar output driver" "0,1,2,3,4,5,6,0"
|
|
bitfld.long 0x00 14.--16. " LINK0_XSEL_4 ,Crossbar output driver" "0,1,2,3,4,5,6,0"
|
|
bitfld.long 0x00 11.--13. " LINK0_XSEL_3 ,Crossbar output driver" "0,1,2,3,4,5,6,0"
|
|
bitfld.long 0x00 8.--10. " LINK0_XSEL_2 ,Crossbar output driver" "0,1,2,3,4,5,6,0"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " LINK0_XSEL_1 ,Crossbar output driver" "0,1,2,3,4,5,6,0"
|
|
bitfld.long 0x00 2.--4. " LINK0_XSEL_0 ,Crossbar output driver" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " LINK_SWAP ,Setting LINK_SWAP" "Not swapped,Swapped"
|
|
bitfld.long 0x00 0. " BYPASS ,Crossbar bypass" "No bypassed,Bypassed"
|
|
line.long 0x04 "PDISP_SOR_XBAR_POL_0,Controls the polarity of the channels going into the crossbar"
|
|
bitfld.long 0x04 9. " POL_LINK1_4 ,LINK1 channel 4 polarity" "Normal,Invert"
|
|
bitfld.long 0x04 8. " POL_LINK1_3 ,LINK1 channel 3 polarity" "Normal,Invert"
|
|
bitfld.long 0x04 7. " POL_LINK1_2 ,LINK1 channel 2 polarity" "Normal,Invert"
|
|
bitfld.long 0x04 6. " POL_LINK1_1 ,LINK1 channel 1 polarity" "Normal,Invert"
|
|
textline " "
|
|
bitfld.long 0x04 5. " POL_LINK1_0 ,LINK1 channel 0 polarity" "Normal,Invert"
|
|
bitfld.long 0x04 4. " POL_LINK0_4 ,LINK0 channel 4 polarity" "Normal,Invert"
|
|
bitfld.long 0x04 3. " POL_LINK0_3 ,LINK0 channel 3 polarity" "Normal,Invert"
|
|
bitfld.long 0x04 2. " POL_LINK0_2 ,LINK0 channel 2 polarity" "Normal,Invert"
|
|
textline " "
|
|
bitfld.long 0x04 1. " POL_LINK0_1 ,LINK0 channel 1 polarity" "Normal,Invert"
|
|
bitfld.long 0x04 0. " POL_LINK0_0 ,LINK0 channel 0 polarity" "Normal,Invert"
|
|
textline " "
|
|
width 34.
|
|
group.long 0x130++0x07
|
|
line.long 0x00 "PDISP_SOR_DP_LINKCTL0_0,Register for select the SOR"
|
|
bitfld.long 0x00 31. " FORCE_IDLEPTTRN ,Force Idle Pattern" "No,Yes"
|
|
bitfld.long 0x00 16.--20. " LANECOUNT ,Controls the lane configuration of the DP datapath" "0,1,,2,,,,,,,,,,,,4,?..."
|
|
bitfld.long 0x00 14. " ENHANCEDFRAME ,Enhanced frame" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SYNCMODE ,Synchronous mode (The link clock and pixel clock are synchronous)" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--8. 0x04 " TUSIZE ,Transfer unit size"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable current DP port" "No,Yes"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "PDISP_SOR_LANE_DRIVE_CURRENT0_0,Transmitter main output drive level"
|
|
hexmask.long.byte 0x00 24.--30. 1. " LANE3_DP_LANE3 ,Value to set for lane3"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LANE2_DP_LANE0 ,Value to set for lane0"
|
|
hexmask.long.byte 0x00 8.--14. 1. " LANE1_DP_LANE1 ,Value to set for lane1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " LANE0_DP_LANE2 ,Value to set for lane2"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "PDISP_SOR_LANE4_DRIVE_CURRENT0_0,Non-DP SORs contain five total lanes"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LANE4 ,LANE4 controls the fifth lane"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "PDISP_SOR_LANE_PREEMPHASIS0_0,Transmitter main output pre-emphasis for each of the four lanes"
|
|
hexmask.long.byte 0x00 24.--30. 1. " LANE3_DP_LANE3 ,Value to set for lane3"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LANE2_DP_LANE0 ,Value to set for lane0"
|
|
hexmask.long.byte 0x00 8.--14. 1. " LANE1_DP_LANE1 ,Value to set for lane1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " LANE0_DP_LANE2 ,Value to set for lane2"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PDISP_SOR_LANE4_PREEMPHASIS0_0,Transmitter main output pre-emphasis for lane4 of each link"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LANE4 ,LANE4 controls the fifth lane"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "PDISP_SOR_POSTCURSOR0_0,Controls Post-cursor2 amplitude for each lane"
|
|
bitfld.long 0x00 24.--28. " LANE3_DP_LANE3 ,Value to set for lane3" "0mA,0.2mA,0.4mA,0.6mA,0.8mA,1mA,1.2mA,1.4mA,1.6mA,1.8mA,2mA,2.2mA,2.4mA,2.6mA,2.8mA,3mA,3.2mA,3.4mA,3.6mA,3.8mA,4mA,4.2mA,4.4mA,4.6mA,4.8mA,5mA,5.2mA,5.4mA,5.6mA,5.8mA,6mA,6.2mA"
|
|
bitfld.long 0x00 16.--20. " LANE2_DP_LANE0 ,Value to set for lane0" "0mA,0.2mA,0.4mA,0.6mA,0.8mA,1mA,1.2mA,1.4mA,1.6mA,1.8mA,2mA,2.2mA,2.4mA,2.6mA,2.8mA,3mA,3.2mA,3.4mA,3.6mA,3.8mA,4mA,4.2mA,4.4mA,4.6mA,4.8mA,5mA,5.2mA,5.4mA,5.6mA,5.8mA,6mA,6.2mA"
|
|
bitfld.long 0x00 8.--12. " LANE1_DP_LANE1 ,Value to set for lane1" "0mA,0.2mA,0.4mA,0.6mA,0.8mA,1mA,1.2mA,1.4mA,1.6mA,1.8mA,2mA,2.2mA,2.4mA,2.6mA,2.8mA,3mA,3.2mA,3.4mA,3.6mA,3.8mA,4mA,4.2mA,4.4mA,4.6mA,4.8mA,5mA,5.2mA,5.4mA,5.6mA,5.8mA,6mA,6.2mA"
|
|
bitfld.long 0x00 0.--4. " LANE0_DP_LANE2 ,Value to set for lane2" "0mA,0.2mA,0.4mA,0.6mA,0.8mA,1mA,1.2mA,1.4mA,1.6mA,1.8mA,2mA,2.2mA,2.4mA,2.6mA,2.8mA,3mA,3.2mA,3.4mA,3.6mA,3.8mA,4mA,4.2mA,4.4mA,4.6mA,4.8mA,5mA,5.2mA,5.4mA,5.6mA,5.8mA,6mA,6.2mA"
|
|
textline " "
|
|
width 25.
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "PDISP_SOR_DP_CONFIG0_0,This register contains various other controls which affect the behaviour of the DP logic"
|
|
eventfld.long 0x00 31. " RD_RESET_VAL ,Defines that the disparity state of the first symbol sent" "Negative,Positive"
|
|
eventfld.long 0x00 28. " IDLE_BEFORE_ATTACH ,Enable idle patterns after attach" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " ACTIVESYM_CNTL ,Control the number of active" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ACTIVESYM_POLARITY ,Control the number of active symbols per TU" "Negative,Positive"
|
|
bitfld.long 0x00 16.--19. " ACTIVESYM_FRAC ,Control the number of active fraction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--14. 1. " ACTIVESYM_COUNT ,Control the number of symbols sent out in transfer irrespective of the tu count"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " WATERMARK ,Number of symbols that the DP logic will wait for at the beginning of a line before ending blanking" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "PDISP_SOR_DP_MN0_0,Controls to tweak the values used for M and N in the Main Stream Attribute data"
|
|
bitfld.long 0x00 30.--31. " M_MOD ,M_DELTA mode" "NONE,INC,DEC,"
|
|
bitfld.long 0x00 24.--27. " M_DELTA ,Defines an offset that will be used to modify the calculated M value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " N_VAL ,value that will be used for calculating M"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "PDISP_SOR_DP_PADCTL0_0,Controls the DP pads"
|
|
bitfld.long 0x00 31. " SPARE_7 ,Enable the VCO-protection clamp (Maps to VCOLIMIT_DISABLE)" "96 cycles,128 cycles"
|
|
bitfld.long 0x00 30. " SPARE_6 ,Vco-calibration block (Maps to VCOCALIB_TS0)" "Enabled,Disabled"
|
|
bitfld.long 0x00 29. " SPARE_5 ,Enable the vco-calibration block (Maps to VCOCALIB_OVERWRB)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SPARE_4 ,Reset the vco-calibration block (Maps to VCOCALIB_ENB)" "No reset,Reset"
|
|
bitfld.long 0x00 27. " SPARE_3 ,Loadadj-calibration block (Maps to LOADADJ_BYPN)" "Not used,Used"
|
|
bitfld.long 0x00 26. " SPARE_2 ,Loadadj-calibration code is swept (Maps to LOADADJ_SYNC_EN)" "Not swept,Swept"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SPARE_1 ,Clamp counter counts (Maps to VCOLIMIT_SEL)" "128 cycles,32 cycles"
|
|
bitfld.long 0x00 24. " VCO_2X ,VCO startup diagnostics control input to the DP analog macro" "Disabled,Enabled"
|
|
eventfld.long 0x00 23. " PAD_CAL_PD ,Powerdown control for the pad calibration logic" "Power up,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TX_PU ,Pull-up current sources enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " REG_CTRL ,Internal regulator control" "0,1,2,3"
|
|
bitfld.long 0x00 16.--19. " VCMMODE ,VCM pin mode select" "TRISTATE,TEST_MUX,WEAK_PULLDOWN,,STRONG_PULLDOWN,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TX_PU_VALUE ,Clamp counter counts"
|
|
bitfld.long 0x00 7. " COMMONMODE_TXD_3_DP_TXD_3 ,Force the lanes 3 to output the common mode voltage" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " COMMONMODE_TXD_2_DP_TXD_0 ,Force the lanes 0 to output the common mode voltage" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " COMMONMODE_TXD_1_DP_TXD_1 ,Force the lanes 1 to output the common mode voltage" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " COMMONMODE_TXD_0_DP_TXD_2 ,Force the lanes 2 to output the common mode voltage" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PD_TXD_3 ,Individual controls to power down the lanes 3" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PD_TXD_0 ,Individual controls to power down the lanes 0" "No,Yes"
|
|
bitfld.long 0x00 1. " PD_TXD_1 ,Individual controls to power down the lanes 1" "No,Yes"
|
|
bitfld.long 0x00 0. " PD_TXD_2 ,Individual controls to power down the lanes 2" "No,Yes"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "PDISP_SOR_DP_DEBUG0_0,Register meant for debug purposes"
|
|
eventfld.long 0x00 16. " LANE3_FIFO_OVERFLOW ,FIFOs overflow lane 3" "No,Yes"
|
|
eventfld.long 0x00 15. " LANE2_FIFO_OVERFLOW ,FIFOs overflow lane 2" "No,Yes"
|
|
eventfld.long 0x00 14. " LANE1_FIFO_OVERFLOW ,FIFOs overflow lane 1" "No,Yes"
|
|
textline " "
|
|
eventfld.long 0x00 13. " LANE0_FIFO_OVERFLOW ,FIFOs overflow lane 0" "No,Yes"
|
|
eventfld.long 0x00 12. " SPKT_OVERRUN ,Watermark is attained while a secondary packet is still being scanned" "No,Yes"
|
|
eventfld.long 0x00 11. " LANE3_STEER_ERROR ,Indicate that an unexpected error for lane 3 has occurred" "No,Yes"
|
|
textline " "
|
|
eventfld.long 0x00 10. " LANE2_STEER_ERROR ,Indicate that an unexpected error for lane 2 has occurred" "No,Yes"
|
|
eventfld.long 0x00 9. " LANE1_STEER_ERROR ,Indicate that an unexpected error for lane 1 has occurred" "No,Yes"
|
|
eventfld.long 0x00 8. " LANE0_STEER_ERROR ,Indicate that an unexpected error for lane 0 has occurred" "No,Yes"
|
|
textline " "
|
|
eventfld.long 0x00 7. " LANE3_PIXPACK_OVERFLOW ,Error indicates pixel packing registers have overflowed for lane 3" "No,Yes"
|
|
eventfld.long 0x00 6. " LANE2_PIXPACK_OVERFLOW ,Error indicates pixel packing registers have overflowed for lane 2" "No,Yes"
|
|
eventfld.long 0x00 5. " LANE1_PIXPACK_OVERFLOW ,Error indicates pixel packing registers have overflowed for lane 1" "No,Yes"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LANE0_PIXPACK_OVERFLOW ,Error indicates pixel packing registers have overflowed for lane 0" "No,Yes"
|
|
eventfld.long 0x00 3. " LANE3_FIFO_UNDERFLOW ,Error when active symbol control is enabled and lane 3 FIFOs underflow" "No,Yes"
|
|
eventfld.long 0x00 2. " LANE2_FIFO_UNDERFLOW ,Error when active symbol control is enabled and lane 2 FIFOs underflow" "No,Yes"
|
|
textline " "
|
|
eventfld.long 0x00 1. " LANE1_FIFO_UNDERFLOW ,Error when active symbol control is enabled and lane 1 FIFOs underflow" "No,Yes"
|
|
eventfld.long 0x00 0. " LANE0_FIFO_UNDERFLOW ,Error when active symbol control is enabled and lane 0 FIFOs underflow" "No,Yes"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "PDISP_SOR_DP_SPARE0_0,Register in the DP SORs that can be used for future features"
|
|
hexmask.long 0x00 3.--31. 0x8 " REG ,Reg"
|
|
bitfld.long 0x00 2. " SOR_CLK_SEL ,Specify whether to use a safe clock or the macro clock as the SOR clock" "SAFE_SORCLK,MACRO_SORCLK"
|
|
bitfld.long 0x00 1. " PANEL ,Specify whether the DP panel is external or internal" "EXTERNAL,INTERNAL"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SEQ_ENABLE ,Used to enable the sequencer in DP mode" "No,Yes"
|
|
textline " "
|
|
width 27.
|
|
if (((d.l(ad:0x54540000+0x188))&0x80000000)==0x00)
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "PDISP_SOR_DP_AUDIO_CTRL_0,Control Audio over DisplayPort"
|
|
eventfld.long 0x00 31. " NEW_SETTINGS ,Allow to make changes in this register" "Done,Pending"
|
|
bitfld.long 0x00 21. " MUTE_STATUS ,Mute status" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " CA_SELECT ,Channel/Speaker Allocation" "Software,Hardware"
|
|
bitfld.long 0x00 19. " SS_SELECT ,Control of the values of Sample Size" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SF_SELECT ,Control of the values of Sampling Frequency" "Software,Hardware"
|
|
bitfld.long 0x00 17. " CC_SELECT ,Control of the values of Channel Count" "Software,Hardware"
|
|
bitfld.long 0x00 16. " CT_SELECT ,Control the values of Coding Type" "Software,Hardware"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PACKET_ID ,Data packets ID in the header"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GENERIC_INFOFRAME_ENABLE ,Allows software to send infoframes" "No,Yes"
|
|
bitfld.long 0x00 6. " INFOFRAME_HEADER_OVERRIDE ,HB1-HB3 are fixed values as defined by the DisplayPort specification" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " MUTE ,Controls the AudioMute_Flag in the VB-ID" "Auto,Disabled,Enabled,"
|
|
bitfld.long 0x00 0. " ENABLE ,Global enable/disable field for Audio over DisplayPort" "No,Yes"
|
|
else
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "PDISP_SOR_DP_AUDIO_CTRL_0,Control Audio over DisplayPort"
|
|
eventfld.long 0x00 31. " NEW_SETTINGS ,Allow to make changes in this register" "Done,Pending"
|
|
rbitfld.long 0x00 21. " MUTE_STATUS ,Mute status" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " CA_SELECT ,Channel/Speaker Allocation" "Software,Hardware"
|
|
rbitfld.long 0x00 19. " SS_SELECT ,Control of the values of Sample Size" "Software,Hardware"
|
|
textline " "
|
|
rbitfld.long 0x00 18. " SF_SELECT ,Control of the values of Sampling Frequency" "Software,Hardware"
|
|
rbitfld.long 0x00 17. " CC_SELECT ,Control of the values of Channel Count" "Software,Hardware"
|
|
rbitfld.long 0x00 16. " CT_SELECT ,Control of the values of Coding Type" "Software,Hardware"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PACKET_ID ,Data packets ID in the header"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " GENERIC_INFOFRAME_ENABLE ,Allows software to send infoframes" "No,Yes"
|
|
rbitfld.long 0x00 6. " INFOFRAME_HEADER_OVERRIDE ,HB1-HB3 are fixed values as defined by the DisplayPort specification" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2.--3. " MUTE ,Controls the AudioMute_Flag in the VB-ID" "Auto,Disabled,Enabled,"
|
|
rbitfld.long 0x00 0. " ENABLE ,Global enable/disable field for Audio over DisplayPort" "Disabled,Enabled"
|
|
endif
|
|
width 43.
|
|
textline " "
|
|
group.long 0x18C++0x0b
|
|
line.long 0x00 "PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0,Length of the hblank period"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " VALUE ,Number of audio packets"
|
|
line.long 0x04 "PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0,Length of a line during VBLANK"
|
|
hexmask.long.tbyte 0x04 0.--20. 1. " VALUE ,Number of line in vblank"
|
|
line.long 0x08 "PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0,Value of the DP InfoFrame header"
|
|
hexmask.long.byte 0x08 24.--31. 1. " HB3 ,Header 3 value"
|
|
hexmask.long.byte 0x08 16.--23. 1. " HB2 ,Header 2 value"
|
|
hexmask.long.byte 0x08 8.--15. 1. " HB1 ,Header 1 value"
|
|
hexmask.long.byte 0x08 0.--7. 1. " HB0 ,Header 0 value"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0,DP Infoframe packet data register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DB3 ,Data 3 value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DB2 ,Data 2 value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DB1 ,Data 1 value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DB0 ,Data 0 value"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0,DP Infoframe packet data register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DB3 ,Data 7 value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DB2 ,Data 6 value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DB1 ,Data 5 value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DB0 ,Data 4 value"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK8_0,DP Infoframe packet data register 8"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DB3 ,Data 11 value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DB2 ,Data 10 value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DB1 ,Data 9 value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DB0 ,Data 8 value"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK12_0,DP Infoframe packet data register 12"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DB3 ,Data 15 value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DB2 ,Data 14 value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DB1 ,Data 13 value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DB0 ,Data 12 value"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK16_0,DP Infoframe packet data register 16"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DB3 ,Data 19 value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DB2 ,Data 18 value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DB1 ,Data 17 value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DB0 ,Data 16 value"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK20_0,DP Infoframe packet data register 20"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DB3 ,Data 23 value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DB2 ,Data 22 value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DB1 ,Data 21 value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DB0 ,Data 20 value"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK24_0,DP Infoframe packet data register 24"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DB3 ,Data 27 value"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DB2 ,Data 26 value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DB1 ,Data 25 value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DB0 ,Data 24 value"
|
|
textline " "
|
|
width 27.
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "PDISP_SOR_DP_TPG_0,Control the training patterns needed during link training"
|
|
bitfld.long 0x00 30. " LANE3_CHANNELCODING ," "Disable,Enable"
|
|
bitfld.long 0x00 28.--29. " LANE3_SCRAMBLEREN ," "Disable,Enable GALIOS,Enable FIBONACCI,"
|
|
bitfld.long 0x00 24.--27. " LANE3_PATTERN ," "NOPATTERN,TRAINING1,TRAINING2,TRAINING3,D102,SBLERRRATE,PRBS7,CSTM,HBR2_COMPLIANCE,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " LANE2_CHANNELCODING ," "Disable,Enable"
|
|
bitfld.long 0x00 20.--21. " LANE2_SCRAMBLEREN ," "Disable,Enable GALIOS,Enable FIBONACCI,"
|
|
bitfld.long 0x00 16.--19. " LANE2_PATTERN ," "NOPATTERN,TRAINING1,TRAINING2,TRAINING3,D102,SBLERRRATE,PRBS7,CSTM,HBR2_COMPLIANCE,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14. " LANE1_CHANNELCODING ," "Disable,Enable"
|
|
bitfld.long 0x00 12.--13. " LANE1_SCRAMBLEREN ," "Disable,Enable GALIOS,Enable FIBONACCI,"
|
|
bitfld.long 0x00 8.--11. " LANE1_PATTERN ," "NOPATTERN,TRAINING1,TRAINING2,TRAINING3,D102,SBLERRRATE,PRBS7,CSTM,HBR2_COMPLIANCE,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " LANE0_CHANNELCODING ," "Disable,Enable"
|
|
bitfld.long 0x00 4.--5. " LANE0_SCRAMBLEREN ," "Disable,Enable GALIOS,Enable FIBONACCI,"
|
|
bitfld.long 0x00 0.--3. " LANE0_PATTERN ," "NOPATTERN,TRAINING1,TRAINING2,?..."
|
|
group.long 0x1B8++0x0F
|
|
line.long 0x00 "PDISP_SOR_DP_TPG_CONFIG_0,Additional controls for the DP Test Pattern Generator"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " HBR2_COMPLIANCE_PERIOD ,The HBR2 compliance pattern"
|
|
line.long 0x04 "PDISP_SOR_DP_LQ_CSTM0_0,Registers contains bits 31:0 for test pattern"
|
|
line.long 0x08 "PDISP_SOR_DP_LQ_CSTM1_0,Registers contains bits 63:32 for test pattern"
|
|
line.long 0x0C "PDISP_SOR_DP_LQ_CSTM2_0,Registers contains bits 79:64 for test pattern"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DPAUX DisplayPort AUX"
|
|
base ad:0x545C0000
|
|
width 22.
|
|
group.long 0x00++0xb
|
|
line.long 0x00 "CTXSW_0,Context switch register"
|
|
rbitfld.long 0x00 28.--31. " NEXT_CHANNEL ,Next requested channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 16.--25. 1. " NEXT_CLASS ,Next requested class"
|
|
bitfld.long 0x00 12.--15. " CURR_CHANNEL ,Current working channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. " AUTO_ACK ,Automatically acknowledge any incoming context switch requests" "MANUAL,AUTOACK"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " CURR_CLASS ,Current working class"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "INTR_EN_AUX_0,A DP SOR port 0 can generate 4 types of interrupts"
|
|
bitfld.long 0x00 3. " AUX_DONE ,Enable interrupt for Completion of an AUX transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IRQ_EVENT ,Enable interrupt for DP device has been connection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " UNPLUG_EVENT ,Enable interrupt for The HPD line being low" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PLUG_EVENT ,Enable interrupt for The HPD line being high" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "INTR_AUX_0,Interrupt status generated"
|
|
bitfld.long 0x00 3. " AUX_DONE ,Completion of an AUX transaction" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " IRQ_EVENT ,DP device has been connected" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " UNPLUG_EVENT ,The HPD line has been low" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " PLUG_EVENT ,The HPD line has been high" "Not pending,Pending"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DP_AUXDATA_WRITE_W1_0,Data register 0 array for DisplayPort 0 writes"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DP_AUXDATA_WRITE_W2_0,Data register 1 array for DisplayPort 0 writes"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DP_AUXDATA_WRITE_W3_0,Data register 2 array for DisplayPort 0 writes"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DP_AUXDATA_WRITE_W4_0,Data register 3 array for DisplayPort 0 writes"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "DP_AUXDATA_READ_W1_0,Data register 0 array for DisplayPort 0 reads"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "DP_AUXDATA_READ_W2_0,Data register 1 array for DisplayPort 0 reads"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "DP_AUXDATA_READ_W3_0,Data register 2 array for DisplayPort 0 reads"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "DP_AUXDATA_READ_W4_0,Data register 3 array for DisplayPort 0 reads"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "DP_AUXADDR_0,AUX register address space"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " REG ,Address space"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "DP_AUXCTL_0,Main control register for AUX transactions"
|
|
bitfld.long 0x00 31. " RST ,reset AUX channel 0" "DEASSERT,ASSERT"
|
|
rbitfld.long 0x00 24.--25. " SEMA_GRANT ,Check the value of AUXCTL_SEMA_GRANT" "NONE,RM,VBIOS,PMU"
|
|
bitfld.long 0x00 20.--21. " SEMA_REQUEST ,AUX semaphore" "RELEASE,RM,VBIOS,PMU"
|
|
bitfld.long 0x00 16. " TRANSACTREQ ,Request an AUX channel 0 transaction" "Done,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CMD ,AUX Command" "I2CWR,I2CRD,I2CREQWSTAT,,MOTWR,MOTRD,MOTREQWSTAT,AUXWR,AUXRD,?..."
|
|
bitfld.long 0x00 8. " ADDRESS_ONLY ,Bit modifies any AUX transaction into an address only transaction" "No,Yes"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMDLEN ,Bits determine the number of data bytes an AUX channel transaction writes or reads"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DP_AUXSTAT_0,Main control register 0 for AUX transactions"
|
|
rbitfld.long 0x00 28. " HPD_STATUS ,Reports the current state of the HPD line" "UNPLUG,PLUGGED"
|
|
rbitfld.long 0x00 20.--23. " AUXCTL_STATE ,Reports the current state of the AUXCTL state machine" "IDLE,SYNC,START1,COMMAND,ADDRESS,LENGTH,WRITE1,READ1,GET_M,STOP1,STOP2,REPLY,CLEANUP,?..."
|
|
rbitfld.long 0x00 16.--19. " REPLYTYPE ,Status and describe the reply type of the AUX channel 0 command" "ACK,NACK,DEFER,,I2CNACK,,,,I2CDEFER,?..."
|
|
bitfld.long 0x00 11. " NO_STOP_ERROR ,AUX reply from the Sink device did properly terminate with a STOP signal" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SINKSTAT_ERROR ,Sink device does not respond with an ACK" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " RX_ERROR ,Error detected by AUX channel 0" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " TIMEOUT_ERROR ,Reporting when a timeout has occurred while waiting for a reply" "Not pending,Pending"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REPLY_M ,Number of data bytes an AUX channel 0 transaction"
|
|
textline " "
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "DP_AUX_SINKSTATLO_0,Contains sink/link status information from AUX address space"
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "P_AUX_SINKSTATHI_0,Buffer contains sink/link status information from AUX address space"
|
|
hexmask.long.word 0x00 0.--15. 1. " REG ,Information from AUX address space"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "HPD_CONFIG_0,Configure the behavior of the HPD plug/unplug events"
|
|
hexmask.long.word 0x00 16.--31. 1. " UNPLUG_MIN_TIME ,The HPD line must be low for this long before it is considered an unplug event"
|
|
hexmask.long.word 0x00 0.--15. 1. " PLUG_MIN_TIME ,The HPD line must be high for this long to be considered a plug event"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "HPD_IRQ_CONFIG_0,AUX_CONFIG contains miscellaneous configuration parameters for the AUX channel 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " MIN_LOW_TIME ,IRQ minimum time"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "DP_AUX_CONFIG_0,AUX_CONFIG contains miscellaneous configuration parameters for the AUX channel 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMEOUT ,Wait time before an AUX transaction will abort and report"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "HYBRID_PADCTL_0,Configuration for the hybrid pads that can be used as AUX/I2C"
|
|
bitfld.long 0x00 15. " I2C_SDA_INPUT_RCV ,Active high receiver enable for the I2C pad's DATA channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " I2C_SCL_INPUT_RCV ,Active high receiver enable for the I2C pad's CLK channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " AUX_CMH ,Active high 1.0V signal to control the output common mode voltage" "V0_60,V0_64,V0_70,V0_56"
|
|
bitfld.long 0x00 8.--10. " AUX_DRVZ ,Active high driver output impedance control" "OHM_78,OHM_60,OHM_54,OHM_45,OHM_50,OHM_42,OHM_39,OHM_34"
|
|
textline " "
|
|
bitfld.long 0x00 2.--7. " AUX_DRVI ,Active high output driver current control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
eventfld.long 0x00 1. " AUX_INPUT_RCV ,Active high receiver enable for the AUX CH pad" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MODE ,Controls whether the pad is in I2C or AUX mode" "AUX,I2C"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "HYBRID_SPARE_0,"
|
|
bitfld.long 0x00 0. " PAD_PWR ,Controls the E_PWRD port of the hybrid pad" "Power up,Power down"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "SCRATCH_REG0_0,Sor_wrap to control the BFM parameters"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "SCRATCH_REG1_0,Loading data/address/cmd_type/data_count values"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "SCRATCH_REG2_0,Provide data back to the tcl tests in cases where tests wait/poll for a particular value"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "HDMI Consumer Electronics Control (CEC)"
|
|
base ad:0x70015000
|
|
width 16.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SW_CONTROL_0,SW control"
|
|
bitfld.long 0x00 31. " MODE ,SW Controlled Mode (Not supported)" "Disabled,"
|
|
bitfld.long 0x00 4. " FILTERED_RX_DATA_PIN , Filtered Rx data pin" "0,1"
|
|
bitfld.long 0x00 0. " RAW_INPUT_DATA_PIN , Raw input data pin" "0,1"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "HW_CONTROL_0,HW control"
|
|
bitfld.long 0x00 31. " TX_RX_MODE ,Enable the operation of the HW CEC engine" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " FAST_SIM_MODE ,Fast sim mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " TX_NAK_MODE ,TX NAK mode" "Block,Frame"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RX_NAK_MODE ,RX NAK mode" "Block,Frame"
|
|
bitfld.long 0x00 15. " RX_SNOOP ,Intercept and forward to software all traffic on the CEC bus" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--14. 1. " RX_LOGICAL_ADDRS ,All logical addresses that should be matched"
|
|
line.long 0x04 "INPUT_FILTER_0,Configure the HW filtering"
|
|
bitfld.long 0x04 31. " MODE ,Mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--5. " FIFO_LENGTH ,FIFO length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TX_REGISTER_0,CEC_HW_TX_REGISTER register"
|
|
bitfld.long 0x00 17. " RETRY_FRAME ,Retry Frame" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " GENERATE_START_BIT ,Generate start bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ADDRESS_MODE ,Address mode" "Direct,Broadcast"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EOM ,End of message bit for this block of data" "No setted,Setted"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,The actual 8 bits of address/data to be transmitted on the bus"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RX_REGISTER_0,CEC_HW_RX_REGISTER register"
|
|
bitfld.long 0x00 9. " ACK_NAK ,The ACK/NAK bit as read from the bus" "0,1"
|
|
bitfld.long 0x00 8. " EOM ,EOM bit read from the bus" "0,1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,The 8 bits of data that were read from the bus"
|
|
textline " "
|
|
group.long 0x18++0x1F
|
|
line.long 0x00 "RX_TIMING_0_0,CEC_HW_RX_TIMING0 register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RX_START_BIT_MIN_DURATION ,The minimum total duration of the start bit"
|
|
hexmask.long.byte 0x00 16.--23. 1. " RX_START_BIT_MAX_DURATIO ,The maximum total duration of the start bit"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " RX_START_BIT_MIN_LO_TIME ,The minimum time the received bus can remain low"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_START_BIT_MAX_LO_TIME ,The maximum time the received bus can remain low"
|
|
line.long 0x04 "RX_TIMING_1_0,CEC_HW_RX_TIMING1 register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " RX_DATA_BIT_MIN_DURATION ,The minimum total duration of the DATA bit"
|
|
hexmask.long.byte 0x04 16.--23. 1. " RX_DATA_BIT_MAX_DURATIO ,The maximum total duration of the DATA bit"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " RX_DATA_BIT_MIN_LO_TIME ,The minimum time the received bus can remain low"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RX_DATA_BIT_MAX_LO_TIME ,The maximum time the received bus can remain low"
|
|
line.long 0x08 "RX_TIMING_2_0,CEC_HW_RX_TIMING2 register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " RX_END_OF_BLOCK_TIME ,Time to wait after the start of the final ACK/NAK phase before returning to idle state"
|
|
line.long 0x0C "TX_TIMING_0_0,CEC_HW_TX_TIMING0 register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " TX_BUS_ERROR_LO_TIME ,How long to hold the bus lo during the start bit"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " TX_BUS_XITION_TIME ,Time to wait for bus to settle after transitioning output"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 8.--15. 1. " TX_START_BIT_DURATION ,The total duration of the start bit"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " TX_START_BIT_LO_TIME ,Time to drive bus low when bus error must be signaled on the bus"
|
|
line.long 0x10 "TX_TIMING_1_0,CEC_HW_TX_TIMING1 register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " TX_ACK_NAK_BIT_SAMPLE_TIME ,The time to sample that ACK/NAK bit"
|
|
hexmask.long.byte 0x10 16.--23. 1. " TX_DATA_BIT_DURATION ,The total duration of a data or ACK/NAK bit"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--15. 1. " TX_HI_DATA_BIT_LO_TIME ,How long to hold the bus low when transmitting a '1'"
|
|
hexmask.long.byte 0x10 0.--7. 1. " TX_LO_DATA_BIT_LO_TIME ,How long to hold the bus low when transmitting a '0'"
|
|
line.long 0x14 "TC_TIMING_2_0,CEC_HW_TX_TIMING2 register"
|
|
bitfld.long 0x14 8.--11. " BUS_IDLE_TIME_RETRY_FRAME ,The amount of time the bus needs to be idle before the same frame can be resent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 4.--7. " BUS_IDLE_TIME_NEW_FRAME ,The amount of time the bus needs to be idle before a new frame can be sent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " BUS_IDLE_TIME_ADDITIONAL_FRAME ,The amount of time the bus needs to be idle before a new frame can be sent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "INT_STAT_0,Individual interrupt and status bits for the CEC HW unit"
|
|
eventfld.long 0x18 14. " FILTERED_RX_DATA_PIN_TRANSITION_L2H ,Filtered RX data on 1 to 0 transition" "No interrupt,Interrupt"
|
|
eventfld.long 0x18 13. " FILTERED_RX_DATA_PIN_TRANSITION_H2L ,Filtered RX data on 0 to 1 transition" "No interrupt,Interrupt"
|
|
eventfld.long 0x18 12. " RX_BUS_ERROR_DETECTED ,RX Bus error detected" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x18 11. " RX_BUS_ANOMALY_DETECTED ,Detected anomaly on RX Bus" "No interrupt,Interrupt"
|
|
eventfld.long 0x18 10. " RX_START_BIT_DETECTED ,Detected RX start bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x18 9. " RX_REGISTER_OVERRUN ,RX register overrun" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x18 8. " RX_REGISTER_FULL ,RX register full detected" "No interrupt,Interrupt"
|
|
eventfld.long 0x18 5. " TX_FRAME_TRANSMITTED ,The ACK bit of the last block is sent" "No interrupt,Interrupt"
|
|
eventfld.long 0x18 4. " TX_BUS_ANOMALY_DETECTED ,Detected anomalous behaviour on the TX Bus" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x18 3. " TX_ARBITRATION_FAILED ,TX Arbitration failed" "No interrupt,Interrupt"
|
|
eventfld.long 0x18 2. " TX_FRAME_OR_BLOCK_NAKD ,TX Block/frame is NAK" "No interrupt,Interrupt"
|
|
eventfld.long 0x18 1. " TX_REGISTER_UNDERRUN ,TX register was empty at the time the transmit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x18 0. " TX_REGISTER_EMPTY ,TX register is empty" "No interrupt,Interrupt"
|
|
line.long 0x1C "INT_MASK_0,Mask register for interrupts"
|
|
bitfld.long 0x1C 14. " FILTERED_RX_DATA_PIN_TRANSITION_L2H ,Interrupt mask for FILTERED_RX_DATA_PIN_TRANSITION_L2H" "Masked,Unmasked"
|
|
bitfld.long 0x1C 13. " FILTERED_RX_DATA_PIN_TRANSITION_H2L ,Interrupt mask for FILTERED_RX_DATA_PIN_TRANSITION_H2L" "Masked,Unmasked"
|
|
bitfld.long 0x1C 12. " RX_BUS_ERROR_DETECTED ,Interrupt mask for RX_BUS_ERROR_DETECTED" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " RX_BUS_ANOMALY_DETECTED ,Interrupt mask for RX_BUS_ANOMALY_DETECTED" "Masked,Unmasked"
|
|
bitfld.long 0x1C 10. " RX_START_BIT_DETECTED ,Interrupt mask for RX_START_BIT_DETECTED" "Masked,Unmasked"
|
|
bitfld.long 0x1C 9. " RX_REGISTER_OVERRUN ,Interrupt mask for RX_REGISTER_OVERRUN" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " RX_REGISTER_FULL ,Interrupt mask for RX_REGISTER_FULL" "Masked,Unmasked"
|
|
bitfld.long 0x1C 5. " TX_FRAME_TRANSMITTED ,Interrupt mask for TX_FRAME_TRANSMITTED" "Masked,Unmasked"
|
|
bitfld.long 0x1C 4. " TX_BUS_ANOMALY_DETECTED ,Interrupt mask for TX_BUS_ANOMALY_DETECTED" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " TX_ARBITRATION_FAILED ,Interrupt mask for TX_ARBITRATION_FAILED" "Masked,Unmasked"
|
|
bitfld.long 0x1C 2. " TX_FRAME_OR_BLOCK_NAKD ,Interrupt mask for TX_FRAME_OR_BLOCK_NAKD" "Masked,Unmasked"
|
|
bitfld.long 0x1C 1. " TX_REGISTER_UNDERRUN ,Interrupt mask for TX_REGISTER_UNDERRUN" "Masked,Unmasked"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " TX_REGISTER_EMPTY ,Interrupt mask for TX_REGISTER_EMPTY" "Masked,Unmasked"
|
|
rgroup.long 0x38++0x0B
|
|
line.long 0x00 "HW_DEBUG_RX_0,Rx debug"
|
|
bitfld.long 0x00 27. " RXDATABIT_SAMPLE_TIMER ,RX DATA BIT SAMPLE TIMER" "0,1"
|
|
bitfld.long 0x00 26. " LOGICADDR_MATCH ,LOGIC ADDR MATCH" "0,1"
|
|
bitfld.long 0x00 25. " FORCELOOUT ,FORCELOOUT" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21.--24. " STATE ,State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 17.--20. " RXBIT_COUNT ,Rx bit counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " DURATION_COUNT ,Duration counter"
|
|
line.long 0x04 "HW_DEBUG_TX_0,TX debug"
|
|
bitfld.long 0x04 26. " TXDATABIT_SAMPLE_TIMER ,TXDATABIT SAMPLE TIMER" "0,1"
|
|
bitfld.long 0x04 25. " FORCELOOUT ,Forceloout" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 21.--24. " STATE ,State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 17.--20. " TXBIT_COUNT ,TX bit counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " DURATION_COUNT ,Duration counter"
|
|
line.long 0x08 "HW_SPARE_0_0,HW spare"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MIPI-CSI Camera serial interface"
|
|
base ad:0x54080000
|
|
width 28.
|
|
Tree "Sensor A"
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "INPUT_STREAM_A_CONTROL_0,CSI Input Stream A Control"
|
|
hexmask.long.word 0x00 16.--24. 1. " CSI_A_SKIP_PACKET_THRESHOLD ,CSI-A Skip Packet Threshold"
|
|
bitfld.long 0x00 4. " A_SKIP_PACKET_THRESHOLD_ENABLE ,Enables skip packet threshold feature" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " A_BYPASS_ALIGN ,Bypass aligning CSIA and CSIB lanes" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 0.--1. " A_DATA_LANE ,CSI-A Data Lane" "1 data lane,2 data lanes,3 data lanes,4 data lanes"
|
|
group.long 0x83c++0x03
|
|
line.long 0x00 "PIXEL_STREAM_A_CONTROL0_0,CSI Pixel Stream A Control 0"
|
|
bitfld.long 0x00 28.--29. " PPA_PAD_FRAME ,CSI Pixel Parser A Pad Frame" "PAD0S,PAD1S,NOPAD,"
|
|
bitfld.long 0x00 27. " PPA_HEADER_EC_ENABLE ,CSI Pixel Parser A Packet Header Error Correction Enable" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " PPA_PAD_SHORT_LINE ,CSI Pixel Parser A Pad Short Line" "PAD0S,PAD1S,NOPAD,"
|
|
bitfld.long 0x00 20.--21. " PPA_EMBEDDED_DATA_OPTIONS ,CSI Pixel Parser A Embedded Data Options" "Discard,Embedded,,"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PPA_OUTPUT_FORMAT_OPTIONS ,CSI Pixel Parser A Output Format Options" "Arbitrary,Pixel,Pixel_Rep,Store,,,,,,,,,,,,"
|
|
bitfld.long 0x00 8. " PPA_WC_CHECK ,CSI Pixel Parser A Data WC Check" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PPA_CRC_CHECK ,CSI Pixel Parser A Data CRC Check" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PPA_WORD_COUNT_SELECT ,CSI Pixel Parser A Word Count Select" "REGISTER,HEADER"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PPA_DATA_IDENTIFIER ,CSI Pixel Parser A Data Identifier byte processing" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PPA_PACKET_HEADER ,CSI Pixel Parser A Packet Header processing" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PPA_STREAM_SOURCE ,CSI Pixel Parser A Stream Source Host" "CSI Interface A,CSI Interface B,,,,,,"
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "PIXEL_STREAM_A_CONTROL1_0,CSI Pixel Stream A Control 1"
|
|
bitfld.long 0x00 4.--7. " PPA_TOP_FIELD_FRAME_MASK ,CSI Pixel Parser A Top Field Frame Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " PPA_TOP_FIELD_FRAME ,CSI Pixel Parser A Top Field Frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x844++0x03
|
|
line.long 0x00 "PIXEL_STREAM_A_GAP_0,CSI Pixel Stream A Gap"
|
|
hexmask.long.word 0x00 16.--31. 1. " PPA_FRAME_MIN_GAP ,Minimum number of viclk cycles from end of frame to start of next frame"
|
|
hexmask.long.word 0x00 0.--15. 1. " PPA_LINE_MIN_GAP ,Minimum number of viclk cycles from end of previous line to start of next line"
|
|
group.long 0x848++0x03
|
|
line.long 0x00 "PIXEL_STREAM_PPA_COMMAND_0,CSI Pixel Parser A Command"
|
|
bitfld.long 0x00 12.--15. " PPA_START_MARKER_FRAME_MAX ,CSI Pixel Parser A Start Marker Maximum Start Frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " PPA_START_MARKER_FRAME_MIN ,CSI Pixel Parser A Start Marker Minimum Start Frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PPA_VSYNC_START_MARKER ,CSI Pixel Parser A VSYNC Start Marker" "FSPKT,VSYNC"
|
|
bitfld.long 0x00 2. " PPA_SINGLE_SHOT ,CSI Pixel Parser A Single Shot Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PPA_ENABLE ,CSI Pixel Parser A Enable" "No operation,Enabled,Disabled,RST"
|
|
textline " "
|
|
width 33.
|
|
group.long 0x84C++0x07
|
|
line.long 0x00 "PIXEL_STREAM_A_EXPECTED_FRAME_0,CSI Pixel Stream A Expected Frame"
|
|
hexmask.long.word 0x00 4.--15. 1. " PPA_MAX_CLOCKS ,Maximum Number of viclk clock cycles between line start requests"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PPA_ENABLE_LINE_TIMEOUT ,PPA_ENABLE_LINE_TIMEOUT" "Disabled,Enabled"
|
|
line.long 0x04 "PIXEL_PARSER_A_INTERRUPT_MASK_0,CSI Pixel Parser A Interrupt Mask"
|
|
bitfld.long 0x04 14. " HPA_UNC_HDR_ERR_INT_MASK ,Interrupt Mask for HPA_UNC_HDR_ERR" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " PPA_SPARE_STATUS_1_INT_MASK ,Interrupt Mask for PPA_SPARE_STATUS_1" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PPA_INTERFRAME_LINE_INT_MASK ,Interrupt Mask for PPA_INTERFRAME_LINE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PPA_EXTRA_SF_INT_MASK ,Interrupt Mask for PPA_EXTRA_SF" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PPA_SHORT_FRAME_INT_MASK ,Interrupt Mask for PPA_SHORT_FRAME" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " PPA_STMERR_INT_MASK ,Interrupt Mask for PPA_STMERR" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " HPPA_FIFO_OVRF_INT_MASK ,Interrupt Mask for PPA_FIFO_OVRF" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " PPA_PL_CRC_ERR_INT_MASK ,Interrupt Mask for PPA_PL_CRC_ERR" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " PPA_SL_PKT_DROPPED_INT_MASK ,Interrupt Mask for PPA_SL_PKT_DROPPED" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " PPA_SL_PROCESSED_INT_MASK ,Interrupt Mask for PPA_SL_PROCESSED" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PPA_ILL_WD_CNT_INT_MASK ,Interrupt Mask for PPA_ILL_WD_CNT" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PPA_HDR_ERR_COR_INT_MASK ,Interrupt Mask for PPA_HDR_ERR_COR" "Disabled,Enabled"
|
|
rgroup.long 0x854++0x03
|
|
line.long 0x00 "PIXEL_PARSER_A_STATUS_0,Pixel Parser A Status"
|
|
bitfld.long 0x00 14. " HPA_UNC_HDR_ERR ,Uncorrectable Header Error" "No error,Error"
|
|
bitfld.long 0x00 10. " PPA_SPARE_STATUS_1 ,PPA Spare Status bit" "No line timeout,Line timeout"
|
|
bitfld.long 0x00 9. " PPA_INTERFRAME_LINE ,Set when CSI-PPA receives a request to output a line that is not in the active part of the frame output" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPA_EXTRA_SF ,Set when CSI-PPA receives a SF when it is expecting an EF" "Not corrupted,corrupted"
|
|
bitfld.long 0x00 7. " PPA_SHORT_FRAME ,Set when CSI-PPA receives a short frame" ",Short Frame"
|
|
bitfld.long 0x00 6. " PPA_STMERR ,Stream Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PPA_FIFO_OVRF ,FIFO Overflow" "Not overflow,Overflow"
|
|
bitfld.long 0x00 4. " PPA_PL_CRC_ERR ,PayLoad CRC Error" "No error,Error"
|
|
bitfld.long 0x00 3. " PPA_SL_PKT_DROPPED ,Short Line Packet Dropped" "Not dropped,Dropped"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PPA_SL_PROCESSED ,Short Line Processed" "Equal/longer,Shorter"
|
|
bitfld.long 0x00 1. " PPA_ILL_WD_CNT ,Illegal Word Count" "No,Yes"
|
|
bitfld.long 0x00 0. " PPA_HDR_ERR_COR ,Header Error Corrected" "No error,Error"
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "SW_SENSOR_A_RESET_0,SW sensor A"
|
|
bitfld.long 0x00 0. " SENSOR_A_RESET ,Reset CSI sensor A" "No reset,Reset"
|
|
tree.end
|
|
tree "Sensor B"
|
|
width 28.
|
|
group.long 0x86c++0x03
|
|
line.long 0x00 "INPUT_STREAM_B_CONTROL_0,CSI Input Stream B Control"
|
|
hexmask.long.word 0x00 16.--24. 1. " B_SKIP_PACKET_THRESHOLD ,CSI-B Skip Packet Threshold"
|
|
bitfld.long 0x00 4. " B_SKIP_PACKET_THRESHOLD_ENABLE ,Enables skip packet threshold feature" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " B_BYPASS_ALIGN ,Bypass aligning CSIB lanes" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 0.--1. " B_DATA_LANE ,CSI-B Data Lane" "1 data lane,2 data lanes,3 data lanes,4 data lanes"
|
|
group.long 0x870++0x03
|
|
line.long 0x00 "PIXEL_STREAM_B_CONTROL0_0,CSI Pixel Stream B Control 0"
|
|
bitfld.long 0x00 28.--29. " PPA_PAD_FRAME ,CSI Pixel Parser B Pad Frame" "PAD0S,PAD1S,NOPAD,"
|
|
bitfld.long 0x00 27. " PPA_HEADER_EC_ENABLE ,CSI Pixel Parser B Packet Header Error Correction Enable" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " PPA_PAD_SHORT_LINE ,CSI Pixel Parser B Pad Short Line" "PAD0S,PAD1S,NOPAD,"
|
|
bitfld.long 0x00 20.--21. " PPA_EMBEDDED_DATA_OPTIONS ,CSI Pixel Parser B Embedded Data Options" "Discard,Embedded,,"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " PPA_OUTPUT_FORMAT_OPTIONS ,CSI Pixel Parser B Output Format Options" "Arbitrary,Pixel,Pixel_Rep,Store,,,,,,,,,,,,"
|
|
bitfld.long 0x00 8. " PPB_WC_CHECK ,CSI Pixel Parser B Data WC Check" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PPA_CRC_CHECK ,CSI Pixel Parser B Data CRC Check" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PPA_WORD_COUNT_SELECT ,CSI Pixel Parser B Word Count Select" "REGISTER,HEADER"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PPA_DATA_IDENTIFIER ,CSI Pixel Parser B Data Identifier byte processing" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PPA_PACKET_HEADER ,CSI Pixel Parser B Packet Header processing" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PPA_STREAM_SOURCE ,CSI Pixel Parser B Stream Source Host" "CSI Interface A,CSI Interface B,,,,,,"
|
|
group.long 0x874++0x03
|
|
line.long 0x00 "PIXEL_STREAM_B_CONTROL1_0,CSI Pixel Stream B Control 1"
|
|
bitfld.long 0x00 4.--7. " PPA_TOP_FIELD_FRAME_MASK ,CSI Pixel Parser B Top Field Frame Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " PPA_TOP_FIELD_FRAME ,CSI Pixel Parser B Top Field Frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x878++0x03
|
|
line.long 0x00 "PIXEL_STREAM_B_GAP_0,CSI Pixel Stream B Gap"
|
|
hexmask.long.word 0x00 16.--31. 1. " PPA_FRAME_MIN_GAP ,Minimum number of viclk cycles from end of frame to start of next frame"
|
|
hexmask.long.word 0x00 0.--15. 1. " PPA_LINE_MIN_GAP ,Minimum number of viclk cycles from end of previous line to start of next line"
|
|
group.long 0x87C++0x03
|
|
line.long 0x00 "PIXEL_STREAM_PPB_COMMAND_0,CSI Pixel Parser B Command"
|
|
bitfld.long 0x00 12.--15. " PPB_START_MARKER_FRAME_MAX ,CSI Pixel Parser B Start Marker Maximum Start Frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " PPB_START_MARKER_FRAME_MIN ,CSI Pixel Parser B Start Marker Minimum Start Frame" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PPB_VSYNC_START_MARKER ,CSI Pixel Parser B VSYNC Start Marker" "FSPKT,VSYNC"
|
|
bitfld.long 0x00 2. " PPB_SINGLE_SHOT ,CSI Pixel Parser B Single Shot Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PPB_ENABLE ,CSI Pixel Parser B Enable" "No operation,Enabled,Disabled,RST"
|
|
textline " "
|
|
width 33.
|
|
group.long 0x880++0x07
|
|
line.long 0x00 "PIXEL_STREAM_B_EXPECTED_FRAME_0,CSI Pixel Stream B Expected Frame"
|
|
hexmask.long.word 0x00 4.--15. 1. " PPA_MAX_CLOCKS ,Maximum Number of viclk clock cycles between line start requests"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PPB_ENABLE_LINE_TIMEOUT ,PPB_ENABLE_LINE_TIMEOUT" "Disabled,Enabled"
|
|
line.long 0x04 "PIXEL_PARSER_B_INTERRUPT_MASK_0,CSI Pixel Parser B Interrupt Mask"
|
|
bitfld.long 0x04 14. " HPB_UNC_HDR_ERR_INT_MASK ,Interrupt Mask for HPB_UNC_HDR_ERR" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " PPB_SPARE_STATUS_1_INT_MASK ,Interrupt Mask for PPB_SPARE_STATUS_1" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PPB_INTERFRAME_LINE_INT_MASK ,Interrupt Mask for PPB_INTERFRAME_LINE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PPB_EXTRA_SF_INT_MASK ,Interrupt Mask for PPB_EXTRA_SF" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PPB_SHORT_FRAME_INT_MASK ,Interrupt Mask for PPB_SHORT_FRAME" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " PPB_STMERR_INT_MASK ,Interrupt Mask for PPB_STMERR" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " HPPB_FIFO_OVRF_INT_MASK ,Interrupt Mask for PPB_FIFO_OVRF" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " PPB_PL_CRC_ERR_INT_MASK ,Interrupt Mask for PPB_PL_CRC_ERR" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " PPB_SL_PKT_DROPPED_INT_MASK ,Interrupt Mask for PPB_SL_PKT_DROPPED" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " PPB_SL_PROCESSED_INT_MASK ,Interrupt Mask for PPB_SL_PROCESSED" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PPB_ILL_WD_CNT_INT_MASK ,Interrupt Mask for PPB_ILL_WD_CNT" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PPB_HDR_ERR_COR_INT_MASK ,Interrupt Mask for PPB_HDR_ERR_COR" "Disabled,Enabled"
|
|
rgroup.long 0x854++0x03
|
|
line.long 0x00 "PIXEL_PARSER_B_STATUS_0,Pixel Parser B Status"
|
|
bitfld.long 0x00 14. " HPB_UNC_HDR_ERR ,Uncorrectable Header Error" "No error,Error"
|
|
bitfld.long 0x00 10. " PPB_SPARE_STATUS_1 ,PPB Spare Status bit" "No line timeout,Line timeout"
|
|
bitfld.long 0x00 9. " PPB_INTERFRAME_LINE ,Set when CSI-PPB receives a request to output a line that is not in the active part of the frame output" "No active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPB_EXTRA_SF ,Set when CSI-PPB receives a SF when it is expecting an EF" "Not corrupted,corrupted"
|
|
bitfld.long 0x00 7. " PPB_SHORT_FRAME ,Set when CSI-PPB receives a short frame" "0,Short Frame"
|
|
bitfld.long 0x00 6. " PPB_STMERR ,Stream Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PPB_FIFO_OVRF ,FIFO Overflow" "Not overflow,Overflow"
|
|
bitfld.long 0x00 4. " PPB_PL_CRC_ERR ,PayLoad CRC Error" "No error,Error"
|
|
bitfld.long 0x00 3. " PPB_SL_PKT_DROPPED ,Short Line Packet Dropped" "Not dropped,Dropped"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PPB_SL_PROCESSED ,Short Line Processed" "Equal/longer,Shorter"
|
|
bitfld.long 0x00 1. " PPB_ILL_WD_CNT ,Illegal Word Count" "No,Yes"
|
|
bitfld.long 0x00 0. " PPB_HDR_ERR_COR ,Header Error Corrected" "No error,Error"
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "SW_SENSOR_B_RESET_0,SW sensor B"
|
|
bitfld.long 0x00 0. " SENSOR_B_RESET ,Reset CSI sensor B" "No reset,Reset"
|
|
tree.end
|
|
textline " "
|
|
width 25.
|
|
group.long 0x908++0x07
|
|
line.long 0x00 "PHY_CIL_COMMAND_0,CSI Phy and CIL Command"
|
|
bitfld.long 0x00 28.--29. " CSI_E_PHY_CIL_ENABLE ,CSI E PHY and CIL Enable" "No operation,Disabled,Enabled,"
|
|
bitfld.long 0x00 24.--25. " CSI_D_PHY_CIL_ENABLE ,CSI D PHY and CIL Enable" "No operation,Disabled,Enabled,"
|
|
bitfld.long 0x00 16.--17. " CSI_B_PHY_CIL_ENABLE ,CSI B Phy and CIL" "No operation,Enable,Disable,"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CSI_B_PHY_CIL_ENABLE ,CSI B PHY and CIL Enable" "No operation,Enable,Disable,"
|
|
bitfld.long 0x00 0.--1. " CSI_A_PHY_CIL_ENABLE ,CSI A Phy and CIL" "No operation,Enable,Disable,"
|
|
line.long 0x04 "CIL_PAD_CONFIG0_0,CIL Pad Configuration 0"
|
|
hexmask.long.byte 0x04 8.--15. 1. " PAD_CIL_SPARE ,Spare bit for CIL BIAS Config"
|
|
textline " "
|
|
tree "CILA"
|
|
group.long 0x92c++0x03
|
|
line.long 0x00 "PAD_CONFIG0_0,CIL-A Pad Configuration 0"
|
|
bitfld.long 0x00 31. " PAD_CILA_E_TXBW ,Enable VCLAMP regulator" "Enabled,Disabled"
|
|
bitfld.long 0x00 28.--30. " PAD_CILA_SLEWDNADJ ,Pull down slew rate adjust" "0,1,2,3,0,-1,-2,-3"
|
|
bitfld.long 0x00 24.--26. " PAD_CILA_SLEWUPADJ ,Pull up slew rate adjust" "0,1,2,3,0,-1,-2,-3"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " PAD_CILA_LPDNADJ ,Driver pull down impedance control" "130ohm,110ohm,130ohm,150ohm,,,,"
|
|
bitfld.long 0x00 18.--20. " PAD_CILA_LPUPADJ ,Driver pull up impedance control" "130ohm,110ohm,130ohm,150ohm,,,,"
|
|
bitfld.long 0x00 16.--17. " PAD_AB_BK_MODE ,PAD_AB_BK_MODE" "two 2x bricks,one 4x brick (A),one 4x brick (B),Illegal"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PAD_CILA_BANDWD_IN ,Increase bandwidth of differential receiver" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PAD_CILA_INADJ1 ,bit 1 input delay trimmer" "0,20ps,40ps,60ps,80ps,100ps,120ps,140ps"
|
|
bitfld.long 0x00 8.--10. " PAD_CILA_INADJ0 ,bit 0 input delay trimmer" "0,20ps,40ps,60ps,80ps,100ps,120ps,140ps"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PAD_CILA_INADJCLK ,Clock bit input delay trimmer" "0,20ps,40ps,60ps,80ps,100ps,120ps,140ps"
|
|
bitfld.long 0x00 3. " PAD_CILA_PDVCLAMP ,Power down regulator which supplies current to serializer/deserializer logic" "Serializer,Deserializer"
|
|
bitfld.long 0x00 2. " PAD_CILA_PDIO_CLK ,Power down for clock bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PAD_CILA_PDIO ,Power down for each data bit" "b'00,b'01,b'10,b'11"
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "PAD_CONFIG1_0,CIL-A Pad Configuration 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " PAD_CILA_SPARE_RO ,Spare Read only bits for CILA Config"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PAD_CILA_SPARE ,Spare bits for CILA"
|
|
bitfld.long 0x00 6.--7. " PAD_CILA_PEMPD_CLK ,Enable data bit HS driver pull down pre-emphasis" "No pre-emphasis,,,Max"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PAD_CILA_PEMPU_CLK ,Enable data bit HS driver pull up pre-emphasis" "No pre-emphasis,,,Max"
|
|
bitfld.long 0x00 2.--3. " PAD_CILA_PEMPD ,Enable data bit HS driver pull down pre-emphasis" "No pre-emphasis,,,Max"
|
|
bitfld.long 0x00 0.--1. " PAD_CILA_PEMPU ,Enable data bit HS driver pull up pre-emphasis," "No pre-emphasis,,,Max"
|
|
textline ""
|
|
width 28.
|
|
group.long 0x934++0x07
|
|
line.long 0x00 "PHY_CILA_CONTROL0_0,CSI-A Phy and CIL Control"
|
|
bitfld.long 0x00 8.--13. " CLK_SETTLE ,Settle time for clk lane when moving from LP to HS" "15 cilclk cycles,8 cilclk cycles,9 cilclk cycles,10 cilclk cycles,11 cilclk cycles,12 cilclk cycles,13 cilclk cycles,14 cilclk cycles,Default internal delay,16 cilclk cycles,17 cilclk cycles,18 cilclk cycles,19 cilclk cycles,20 cilclk cycles,21 cilclk cycles,22 cilclk cycles,23 cilclk cycles,24 cilclk cycles,25 cilclk cycles,26 cilclk cycles,27 cilclk cycles,28 cilclk cycles,29 cilclk cycles,30 cilclk cycles,31 cilclk cycles,32 cilclk cycles,33 cilclk cycles,34 cilclk cycles,35 cilclk cycles,36 cilclk cycles,37 cilclk cycles,38 cilclk cycles,39 cilclk cycles,40 cilclk cycles,41 cilclk cycles,42 cilclk cycles,43 cilclk cycles,44 cilclk cycles,45 cilclk cycles,46 cilclk cycles,47 cilclk cycles,48 cilclk cycles,49 cilclk cycles,50 cilclk cycles,51 cilclk cycles,52 cilclk cycles,53 cilclk cycles,54 cilclk cycles,55 cilclk cycles,56 cilclk cycles,57 cilclk cycles,58 cilclk cycles,59 cilclk cycles,60 cilclk cycles,61 cilclk cycles,62 cilclk cycles,63 cilclk cycles,64 cilclk cycles,,,,,,"
|
|
bitfld.long 0x00 6. " BYPASS_LP_SEQ ,CILA_BYPASS_LP_SEQ" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " THS_SETTLE ,Settle time for data lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "INTERRUPT_MASK_0,CSI Control and Interface Logic A Interrupt Mask"
|
|
bitfld.long 0x04 9. " CLK_LANE_CTRL_ERR_INT_MASK ,Interrupt Mask for CILA_CLK_CTRL_ERR" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " ESC_DATA_REC_INT_MASK ,Interrupt Mask for CILA_ESC_DATA_REC" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " ESC_CMD_REC_INT_MASK ,Interrupt Mask for CILA_ESC_CMD_REC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CTRL_ERR_INT_MASK ,Interrupt Mask for CILA_CTRL_ERR" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SYNC_ESC_ERR_INT_MASK ,Interrupt Mask for CILA_SYNC_ESC_ERR" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " SOT_MB_ERR_INT_MASK ,Interrupt Mask for CILA_SOT_MB_ERR" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SOT_SB_ERR_INT_MASK ,Interrupt Mask for CILA_SOT_SB_ERR" "Disabled,Enabled"
|
|
rgroup.long 0x93c++0x07
|
|
line.long 0x00 "STATUS_0,CSI Control and Interface Logic A Status"
|
|
bitfld.long 0x00 6. " CILA_ESC_DATA_REC ,Escape Mode Data Received" "No received,Received"
|
|
bitfld.long 0x00 5. " ESC_CMD_REC ,Escape Mode Command Received" "No received,Received"
|
|
bitfld.long 0x00 4. " CTRL_ERR ,Control Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CILA_SYNC_ESC_ERR ,Sync Escape Error" "No error,Error"
|
|
bitfld.long 0x00 1. " SOT_MB_ERR ,Start of Transmission Multi Bit Error" "No error,Error"
|
|
bitfld.long 0x00 0. " SOT_SB_ERR ,Start of Transmission Single Bit Error" "No error,Error"
|
|
line.long 0x04 "TATUS_0,CSI-CILA Control and Interface Logic Status"
|
|
bitfld.long 0x04 18. " DATA_LANE1_CTRL_ERR ,Control Error" "No error,Error"
|
|
bitfld.long 0x04 17. " DATA_LANE1_SOT_MB_ERR ,Start of Transmission Multi Bit Error" "No error,Error"
|
|
bitfld.long 0x04 16. " DATA_LANE1_SOT_SB_ERR ,Start of Transmission Single Bit Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DATA_LANE0_CTRL_ERR ,Control Error" "No error,Error"
|
|
bitfld.long 0x04 5. " DATA_LANE0_SOT_MB_ERR ,Start of Transmission Multi Bit Error" "No error,Error"
|
|
bitfld.long 0x04 4. " DATA_LANE0_SOT_SB_ERR ,Start of Transmission Single Bit Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CLK_LANE_CTRL_ERR ,Control Error" "No error,Error"
|
|
if (((d.l(ad:0x54080000+0x93c))&0x20)==0x20)
|
|
rgroup.long 0x944++0x03
|
|
line.long 0x00 "ESCAPE_MODE_COMMAND_0,Escape Mode Command"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CILA_ESC_CMD_BYTE ,CIL-A Escape Mode Command Byte"
|
|
endif
|
|
if (((d.l(ad:0x54080000+0x93c))&0x40)==0x40)
|
|
rgroup.long 0x948++0x03
|
|
line.long 0x00 "ESCAPE_MODE_DATA_0,Escape Mode Data"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CILA_ESC_DATA_BYTE ,CIL-A Escape Mode Data Byte"
|
|
endif
|
|
group.long 0x94c++0x03
|
|
line.long 0x00 "CSICIL_SW_SENSOR_A_RESET_0,Sensor A Reset"
|
|
bitfld.long 0x00 0. " CSICIL_SENSOR_A_RESET ,Reset CSICIL sensor A" "No reset,Reset"
|
|
textline " "
|
|
tree.end
|
|
tree "CILB"
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "PAD_CONFIG0_0,CIL-B Pad Configuration 0"
|
|
bitfld.long 0x00 31. " PAD_CILB_E_TXBW ,Enable VCLAMP regulator" "Enabled,Disabled"
|
|
bitfld.long 0x00 28.--30. " PAD_CILB_SLEWDNADJ ,Pull down slew rate adjust" "0,1,2,3,0,-1,-2,-3"
|
|
bitfld.long 0x00 24.--26. " PAD_CILB_SLEWUPADJ ,Pull up slew rate adjust" "0,1,2,3,0,-1,-2,-3"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " PAD_CILB_LPDNADJ ,Driver pull down impedance control" "130ohm,110ohm,130ohm,150ohm,,,,"
|
|
bitfld.long 0x00 18.--20. " PAD_CILB_LPUPADJ ,Driver pull up impedance control" "130ohm,110ohm,130ohm,150ohm,,,,"
|
|
bitfld.long 0x00 15. " PAD_CILB_BANDWD_IN ,Increase bandwidth of differential receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PAD_CILB_INADJ1 ,bit 1 input delay trimmer" "0,20ps,40ps,60ps,80ps,100ps,120ps,140ps"
|
|
bitfld.long 0x00 8.--10. " PAD_CILB_INADJ0 ,bit 0 input delay trimmer" "0,20ps,40ps,60ps,80ps,100ps,120ps,140ps"
|
|
bitfld.long 0x00 4.--6. " PAD_CILB_INADJCLK ,Clock bit input delay trimmer" "0,20ps,40ps,60ps,80ps,100ps,120ps,140ps"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PAD_CILB_PDVCLAMP ,Power down regulator which supplies current to serializer/deserializer logic" "Serializer,Deserializer"
|
|
bitfld.long 0x00 2. " PAD_CILB_PDIO_CLK ,Power down for clock bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " PAD_CILB_PDIO ,Power down for each data bit" "b'00,b'01,b'10,b'11"
|
|
group.long 0x964++0x03
|
|
line.long 0x00 "PAD_CONFIG1_0,CIL-B Pad Configuration 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " PAD_CILB_SPARE_RO ,Spare Read only bits for CILB Config"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PAD_CILB_SPARE ,Spare bits for CILB"
|
|
bitfld.long 0x00 6.--7. " PAD_CILB_PEMPD_CLK ,Enable data bit HS driver pull down pre-emphasis" "No pre-emphasis,,,Max"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PAD_CILB_PEMPU_CLK ,Enable data bit HS driver pull up pre-emphasis" "No pre-emphasis,,,Max"
|
|
bitfld.long 0x00 2.--3. " PAD_CILB_PEMPD ,Enable data bit HS driver pull down pre-emphasis" "No pre-emphasis,,,Max"
|
|
bitfld.long 0x00 0.--1. " PAD_CILB_PEMPU ,Enable data bit HS driver pull up pre-emphasis," "No pre-emphasis,,,Max"
|
|
group.long 0x968++0x07
|
|
line.long 0x00 "PHY_CILB_CONTROL0_0,CSI-B Phy and CIL Control"
|
|
bitfld.long 0x00 8.--13. " CLK_SETTLE ,Settle time for clk lane when moving from LP to HS" "15 cilclk cycles,8 cilclk cycles,9 cilclk cycles,10 cilclk cycles,11 cilclk cycles,12 cilclk cycles,13 cilclk cycles,14 cilclk cycles,Default internal delay,16 cilclk cycles,17 cilclk cycles,18 cilclk cycles,19 cilclk cycles,20 cilclk cycles,21 cilclk cycles,22 cilclk cycles,23 cilclk cycles,24 cilclk cycles,25 cilclk cycles,26 cilclk cycles,27 cilclk cycles,28 cilclk cycles,29 cilclk cycles,30 cilclk cycles,31 cilclk cycles,32 cilclk cycles,33 cilclk cycles,34 cilclk cycles,35 cilclk cycles,36 cilclk cycles,37 cilclk cycles,38 cilclk cycles,39 cilclk cycles,40 cilclk cycles,41 cilclk cycles,42 cilclk cycles,43 cilclk cycles,44 cilclk cycles,45 cilclk cycles,46 cilclk cycles,47 cilclk cycles,48 cilclk cycles,49 cilclk cycles,50 cilclk cycles,51 cilclk cycles,52 cilclk cycles,53 cilclk cycles,54 cilclk cycles,55 cilclk cycles,56 cilclk cycles,57 cilclk cycles,58 cilclk cycles,59 cilclk cycles,60 cilclk cycles,61 cilclk cycles,62 cilclk cycles,63 cilclk cycles,64 cilclk cycles,,,,,,"
|
|
bitfld.long 0x00 6. " BYPASS_LP_SEQ ,CILB_BYPASS_LP_SEQ" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " THS_SETTLE ,Settle time for data lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "CIL_B_INTERRUPT_MASK_0,CSI Control and Interface Logic B Interrupt Mask"
|
|
bitfld.long 0x04 6. " ESC_DATA_REC_INT_MASK ,Interrupt Mask for CILB_ESC_DATA_REC" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " ESC_CMD_REC_INT_MASK ,Interrupt Mask for CILB_ESC_CMD_REC" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CTRL_ERR_INT_MASK ,Interrupt Mask for CILB_CTRL_ERR" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SYNC_ESC_ERR_INT_MASK ,Interrupt Mask for CILB_SYNC_ESC_ERR" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " SOT_MB_ERR_INT_MASK ,Interrupt Mask for CILB_SOT_MB_ERR" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SOT_SB_ERR_INT_MASK ,Interrupt Mask for CILB_SOT_SB_ERR" "Disabled,Enabled"
|
|
rgroup.long 0x970++0x07
|
|
line.long 0x00 "STATUS_0,CSI Control and Interface Logic B Status"
|
|
bitfld.long 0x00 6. " ESC_DATA_REC ,Escape Mode Data Received" "No received,Received"
|
|
bitfld.long 0x00 5. " ESC_CMD_REC ,Escape Mode Command Received" "No received,Received"
|
|
bitfld.long 0x00 4. " CTRL_ERR ,Control Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNC_ESC_ERR ,Sync Escape Error" "No error,Error"
|
|
bitfld.long 0x00 1. " SOT_MB_ERR ,Start of Transmission Multi Bit Error" "No error,Error"
|
|
bitfld.long 0x00 0. " SOT_SB_ERR ,Start of Transmission Single Bit Error" "No error,Error"
|
|
line.long 0x04 "STATUS_0,CSI-CILB Control and Interface Logic Status"
|
|
bitfld.long 0x04 18. " DATA_LANE1_CTRL_ERR ,Control Error" "No error,Error"
|
|
bitfld.long 0x04 17. " DATA_LANE1_SOT_MB_ERR ,Start of Transmission Multi Bit Error" "No error,Error"
|
|
bitfld.long 0x04 16. " DATA_LANE1_SOT_SB_ERR ,Start of Transmission Single Bit Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DATA_LANE0_CTRL_ERR ,Control Error" "No error,Error"
|
|
bitfld.long 0x04 5. " DATA_LANE0_SOT_MB_ERR ,Start of Transmission Multi Bit Error" "No error,Error"
|
|
bitfld.long 0x04 4. " DATA_LANE0_SOT_SB_ERR ,Start of Transmission Single Bit Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CLK_LANE_CTRL_ERR ,Control Error" "No error,Error"
|
|
if (((d.l(ad:0x54080000+0x970))&0x20)==0x20)
|
|
rgroup.long 0x978++0x03
|
|
line.long 0x00 "ESCAPE_MODE_COMMAND_0,Escape Mode Command"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ESC_CMD_BYTE ,CIL-B Escape Mode Command Byte"
|
|
endif
|
|
if (((d.l(ad:0x54080000+0x970))&0x40)==0x40)
|
|
rgroup.long 0x97C++0x03
|
|
line.long 0x00 "ESCAPE_MODE_DATA_0,Escape Mode Data"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ESC_DATA_BYTE ,CIL-B Escape Mode Data Byte"
|
|
endif
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "CSICIL_SW_SENSOR_B_RESET_0,Sensor B Reset"
|
|
bitfld.long 0x00 0. " CSICIL_SENSOR_B_RESET ,Reset CSICIL sensor B" "No reset,Reset"
|
|
textline " "
|
|
tree.end
|
|
tree "CILC"
|
|
group.long 0x994++0x03
|
|
line.long 0x00 "PAD_CONFIG0_0,CIL-C Pad Configuration 0"
|
|
bitfld.long 0x00 31. " PAD_CILC_E_TXBW ,Enable VCLAMP regulator" "Enabled,Disabled"
|
|
bitfld.long 0x00 28.--30. " PAD_CILC_SLEWDNADJ ,Pull down slew rate adjust" "0,1,2,3,0,-1,-2,-3"
|
|
bitfld.long 0x00 24.--26. " PAD_CILC_SLEWUPADJ ,Pull up slew rate adjust" "0,1,2,3,0,-1,-2,-3"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " PAD_CILC_LPDNADJ ,Driver pull down impedance control" "130ohm,110ohm,130ohm,150ohm,,,,"
|
|
bitfld.long 0x00 18.--20. " PAD_CILC_LPUPADJ ,Driver pull up impedance control" "130ohm,110ohm,130ohm,150ohm,,,,"
|
|
bitfld.long 0x00 16.--17. " PAD_CD_BK_MODE ,PAD_AB_BK_MODE" "two 2x bricks,one 4x brick (A),one 4x brick (B),Illegal"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PAD_CILC_BANDWD_IN ,Increase bandwidth of differential receiver" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " PAD_CILC_INADJ1 ,bit 1 input delay trimmer" "0,20ps,40ps,60ps,80ps,100ps,120ps,140ps"
|
|
bitfld.long 0x00 8.--10. " PAD_CILC_INADJ0 ,bit 0 input delay trimmer" "0,20ps,40ps,60ps,80ps,100ps,120ps,140ps"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PAD_CILC_INADJCLK ,Clock bit input delay trimmer" "0,20ps,40ps,60ps,80ps,100ps,120ps,140ps"
|
|
bitfld.long 0x00 3. " PAD_CILC_PDVCLAMP ,Power down regulator which supplies current to serializer/deserializer logic" "Serializer,Deserializer"
|
|
bitfld.long 0x00 2. " PAD_CILC_PDIO_CLK ,Power down for clock bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PAD_CILC_PDIO ,Power down for each data bit" "b'00,b'01,b'10,b'11"
|
|
group.long 0x998++0x03
|
|
line.long 0x00 "PAD_CONFIG1_0,CIL-C Pad Configuration 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " PAD_CILC_SPARE_RO ,Spare Read only bits for CILC Config"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PAD_CILC_SPARE ,Spare bits for CILC"
|
|
bitfld.long 0x00 6.--7. " PAD_CILC_PEMPD_CLK ,Enable data bit HS driver pull down pre-emphasis" "No pre-emphasis,,,Max"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PAD_CILC_PEMPU_CLK ,Enable data bit HS driver pull up pre-emphasis" "No pre-emphasis,,,Max"
|
|
bitfld.long 0x00 2.--3. " PAD_CILC_PEMPD ,Enable data bit HS driver pull down pre-emphasis" "No pre-emphasis,,,Max"
|
|
bitfld.long 0x00 0.--1. " PAD_CILC_PEMPU ,Enable data bit HS driver pull up pre-emphasis," "No pre-emphasis,,,Max"
|
|
group.long 0x99C++0x07
|
|
line.long 0x00 "PHY_CILC_CONTROL0_0,CSI-C Phy and CIL Control"
|
|
bitfld.long 0x00 8.--13. " CLK_SETTLE ,Settle time for clk lane when moving from LP to HS" "15 cilclk cycles,8 cilclk cycles,9 cilclk cycles,10 cilclk cycles,11 cilclk cycles,12 cilclk cycles,13 cilclk cycles,14 cilclk cycles,Default internal delay,16 cilclk cycles,17 cilclk cycles,18 cilclk cycles,19 cilclk cycles,20 cilclk cycles,21 cilclk cycles,22 cilclk cycles,23 cilclk cycles,24 cilclk cycles,25 cilclk cycles,26 cilclk cycles,27 cilclk cycles,28 cilclk cycles,29 cilclk cycles,30 cilclk cycles,31 cilclk cycles,32 cilclk cycles,33 cilclk cycles,34 cilclk cycles,35 cilclk cycles,36 cilclk cycles,37 cilclk cycles,38 cilclk cycles,39 cilclk cycles,40 cilclk cycles,41 cilclk cycles,42 cilclk cycles,43 cilclk cycles,44 cilclk cycles,45 cilclk cycles,46 cilclk cycles,47 cilclk cycles,48 cilclk cycles,49 cilclk cycles,50 cilclk cycles,51 cilclk cycles,52 cilclk cycles,53 cilclk cycles,54 cilclk cycles,55 cilclk cycles,56 cilclk cycles,57 cilclk cycles,58 cilclk cycles,59 cilclk cycles,60 cilclk cycles,61 cilclk cycles,62 cilclk cycles,63 cilclk cycles,64 cilclk cycles,,,,,,"
|
|
bitfld.long 0x00 6. " BYPASS_LP_SEQ ,CILC_BYPASS_LP_SEQ" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " THS_SETTLE ,Settle time for data lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "C_INTERRUPT_MASK_0,CSI Control and Interface Logic C Interrupt Mask"
|
|
bitfld.long 0x04 9. " CLK_LANE_CTRL_ERR_INT_MASK ,Interrupt Mask for CILC_CLK_CTRL_ERR" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " ESC_DATA_REC_INT_MASK ,Interrupt Mask for CILC_ESC_DATA_REC" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " ESC_CMD_REC_INT_MASK ,Interrupt Mask for CILC_ESC_CMD_REC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CTRL_ERR_INT_MASK ,Interrupt Mask for CILC_CTRL_ERR" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SYNC_ESC_ERR_INT_MASK ,Interrupt Mask for CILC_SYNC_ESC_ERR" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " SOT_MB_ERR_INT_MASK ,Interrupt Mask for CILC_SOT_MB_ERR" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SOT_SB_ERR_INT_MASK ,Interrupt Mask for CILC_SOT_SB_ERR" "Disabled,Enabled"
|
|
rgroup.long 0x9a4++0x07
|
|
line.long 0x00 "STATUS_0,CSI Control and Interface Logic C Status"
|
|
bitfld.long 0x00 6. " ESC_DATA_REC ,Escape Mode Data Received" "No received,Received"
|
|
bitfld.long 0x00 5. " ESC_CMD_REC ,Escape Mode Command Received" "No received,Received"
|
|
bitfld.long 0x00 4. " CTRL_ERR ,Control Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNC_ESC_ERR ,Sync Escape Error" "No error,Error"
|
|
bitfld.long 0x00 1. " SOT_MB_ERR ,Start of Transmission Multi Bit Error" "No error,Error"
|
|
bitfld.long 0x00 0. " SOT_SB_ERR ,Start of Transmission Single Bit Error" "No error,Error"
|
|
line.long 0x04 "STATUS_0,CSI-CILC Control and Interface Logic Status"
|
|
bitfld.long 0x04 18. " DATA_LANE1_CTRL_ERR ,Control Error" "No error,Error"
|
|
bitfld.long 0x04 17. " DATA_LANE1_SOT_MB_ERR ,Start of Transmission Multi Bit Error" "No error,Error"
|
|
bitfld.long 0x04 16. " DATA_LANE1_SOT_SB_ERR ,Start of Transmission Single Bit Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DATA_LANE0_CTRL_ERR ,Control Error" "No error,Error"
|
|
bitfld.long 0x04 5. " DATA_LANE0_SOT_MB_ERR ,Start of Transmission Multi Bit Error" "No error,Error"
|
|
bitfld.long 0x04 4. " DATA_LANE0_SOT_SB_ERR ,Start of Transmission Single Bit Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CLK_LANE_CTRL_ERR ,Control Error" "No error,Error"
|
|
if (((d.l(ad:0x54080000+0x9a4))&0x20)==0x20)
|
|
rgroup.long 0x9ac++0x03
|
|
line.long 0x00 "ESCAPE_MODE_COMMAND_0,Escape Mode Command"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ESC_CMD_BYTE ,CIL-C Escape Mode Command Byte"
|
|
endif
|
|
if (((d.l(ad:0x54080000+0x9a4))&0x40)==0x40)
|
|
rgroup.long 0x9b0++0x03
|
|
line.long 0x00 "ESCAPE_MODE_DATA_0,Escape Mode Data"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ESC_DATA_BYTE ,CIL-C Escape Mode Data Byte"
|
|
endif
|
|
group.long 0x9b4++0x03
|
|
line.long 0x00 "CSICIL_SW_SENSOR_C_RESET_0,Sensor C Reset"
|
|
bitfld.long 0x00 0. " CSICIL_SENSOR_B_RESET ,Reset CSICIL sensor C" "No reset,Reset"
|
|
textline " "
|
|
tree.end
|
|
tree "CILD"
|
|
group.long 0x9c8++0x03
|
|
line.long 0x00 "PAD_CONFIG0_0,CIL-D Pad Configuration 0"
|
|
bitfld.long 0x00 31. " PAD_CILD_E_TXBW ,Enable VCLAMP regulator" "Enabled,Disabled"
|
|
bitfld.long 0x00 28.--30. " PAD_CILD_SLEWDNADJ ,Pull down slew rate adjust" "0,1,2,3,0,-1,-2,-3"
|
|
bitfld.long 0x00 24.--26. " PAD_CILD_SLEWUPADJ ,Pull up slew rate adjust" "0,1,2,3,0,-1,-2,-3"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " PAD_CILD_LPDNADJ ,Driver pull down impedance control" "130ohm,110ohm,130ohm,150ohm,,,,"
|
|
bitfld.long 0x00 18.--20. " PAD_CILD_LPUPADJ ,Driver pull up impedance control" "130ohm,110ohm,130ohm,150ohm,,,,"
|
|
bitfld.long 0x00 15. " PAD_CILD_BANDWD_IN ,Increase bandwidth of differential receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " PAD_CILD_INADJ1 ,bit 1 input delay trimmer" "0,20ps,40ps,60ps,80ps,100ps,120ps,140ps"
|
|
bitfld.long 0x00 8.--10. " PAD_CILD_INADJ0 ,bit 0 input delay trimmer" "0,20ps,40ps,60ps,80ps,100ps,120ps,140ps"
|
|
bitfld.long 0x00 4.--6. " PAD_CILD_INADJCLK ,Clock bit input delay trimmer" "0,20ps,40ps,60ps,80ps,100ps,120ps,140ps"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PAD_CILD_PDVCLAMP ,Power down regulator which supplies current to serializer/deserializer logic" "Serializer,Deserializer"
|
|
bitfld.long 0x00 2. " PAD_CILD_PDIO_CLK ,Power down for clock bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " PAD_CILD_PDIO ,Power down for each data bit" "b'00,b'01,b'10,b'11"
|
|
group.long 0x9cc++0x03
|
|
line.long 0x00 "PAD_CONFIG1_0,CIL-D Pad Configuration 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " PAD_CILD_SPARE_RO ,Spare Read only bits for CILD Config"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PAD_CILD_SPARE ,Spare bits for CILD"
|
|
bitfld.long 0x00 6.--7. " PAD_CILD_PEMPD_CLK ,Enable data bit HS driver pull down pre-emphasis" "No pre-emphasis,,,Max"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PAD_CILD_PEMPU_CLK ,Enable data bit HS driver pull up pre-emphasis" "No pre-emphasis,,,Max"
|
|
bitfld.long 0x00 2.--3. " PAD_CILD_PEMPD ,Enable data bit HS driver pull down pre-emphasis" "No pre-emphasis,,,Max"
|
|
bitfld.long 0x00 0.--1. " PAD_CILD_PEMPU ,Enable data bit HS driver pull up pre-emphasis," "No pre-emphasis,,,Max"
|
|
group.long 0x9d0++0x07
|
|
line.long 0x00 "PHY_CILD_CONTROL0_0,CSI-D Phy and CIL Control"
|
|
bitfld.long 0x00 8.--13. " CLK_SETTLE ,Settle time for clk lane when moving from LP to HS" "15 cilclk cycles,8 cilclk cycles,9 cilclk cycles,10 cilclk cycles,11 cilclk cycles,12 cilclk cycles,13 cilclk cycles,14 cilclk cycles,Default internal delay,16 cilclk cycles,17 cilclk cycles,18 cilclk cycles,19 cilclk cycles,20 cilclk cycles,21 cilclk cycles,22 cilclk cycles,23 cilclk cycles,24 cilclk cycles,25 cilclk cycles,26 cilclk cycles,27 cilclk cycles,28 cilclk cycles,29 cilclk cycles,30 cilclk cycles,31 cilclk cycles,32 cilclk cycles,33 cilclk cycles,34 cilclk cycles,35 cilclk cycles,36 cilclk cycles,37 cilclk cycles,38 cilclk cycles,39 cilclk cycles,40 cilclk cycles,41 cilclk cycles,42 cilclk cycles,43 cilclk cycles,44 cilclk cycles,45 cilclk cycles,46 cilclk cycles,47 cilclk cycles,48 cilclk cycles,49 cilclk cycles,50 cilclk cycles,51 cilclk cycles,52 cilclk cycles,53 cilclk cycles,54 cilclk cycles,55 cilclk cycles,56 cilclk cycles,57 cilclk cycles,58 cilclk cycles,59 cilclk cycles,60 cilclk cycles,61 cilclk cycles,62 cilclk cycles,63 cilclk cycles,64 cilclk cycles,,,,,,"
|
|
bitfld.long 0x00 6. " BYPASS_LP_SEQ ,CILD_BYPASS_LP_SEQ" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " THS_SETTLE ,Settle time for data lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "INTERRUPT_MASK_0,CSI Control and Interface Logic D Interrupt Mask"
|
|
bitfld.long 0x04 6. " ESC_DATA_REC_INT_MASK ,Interrupt Mask for CILD_ESC_DATA_REC" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " ESC_CMD_REC_INT_MASK ,Interrupt Mask for CILD_ESC_CMD_REC" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CTRL_ERR_INT_MASK ,Interrupt Mask for CILD_CTRL_ERR" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SYNC_ESC_ERR_INT_MASK ,Interrupt Mask for CILD_SYNC_ESC_ERR" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " SOT_MB_ERR_INT_MASK ,Interrupt Mask for CILD_SOT_MB_ERR" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SOT_SB_ERR_INT_MASK ,Interrupt Mask for CILD_SOT_SB_ERR" "Disabled,Enabled"
|
|
rgroup.long 0x9d8++0x07
|
|
line.long 0x00 "STATUS_0,CSI Control and Interface Logic D Status"
|
|
bitfld.long 0x00 6. " ESC_DATA_REC ,Escape Mode Data Received" "No received,Received"
|
|
bitfld.long 0x00 5. " ESC_CMD_REC ,Escape Mode Command Received" "No received,Received"
|
|
bitfld.long 0x00 4. " CTRL_ERR ,Control Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYNC_ESC_ERR ,Sync Escape Error" "No error,Error"
|
|
bitfld.long 0x00 1. " SOT_MB_ERR ,Start of Transmission Multi Bit Error" "No error,Error"
|
|
bitfld.long 0x00 0. " SOT_SB_ERR ,Start of Transmission Single Bit Error" "No error,Error"
|
|
line.long 0x04 "STATUS_0,CSI-CILD Control and Interface Logic Status"
|
|
bitfld.long 0x04 18. " DATA_LANE1_CTRL_ERR ,Control Error" "No error,Error"
|
|
bitfld.long 0x04 17. " DATA_LANE1_SOT_MB_ERR ,Start of Transmission Multi Bit Error" "No error,Error"
|
|
bitfld.long 0x04 16. " DATA_LANE1_SOT_SB_ERR ,Start of Transmission Single Bit Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DATA_LANE0_CTRL_ERR ,Control Error" "No error,Error"
|
|
bitfld.long 0x04 5. " DATA_LANE0_SOT_MB_ERR ,Start of Transmission Multi Bit Error" "No error,Error"
|
|
bitfld.long 0x04 4. " DATA_LANE0_SOT_SB_ERR ,Start of Transmission Single Bit Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CLK_LANE_CTRL_ERR ,Control Error" "No error,Error"
|
|
if (((d.l(ad:0x54080000+0x9d8))&0x20)==0x20)
|
|
rgroup.long 0x9ec++0x03
|
|
line.long 0x00 "ESCAPE_MODE_COMMAND_0,Escape Mode Command"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ESC_CMD_BYTE ,CIL-D Escape Mode Command Byte"
|
|
endif
|
|
if (((d.l(ad:0x54080000+0x9d8))&0x40)==0x40)
|
|
rgroup.long 0x9f0++0x03
|
|
line.long 0x00 "ESCAPE_MODE_DATA_0,Escape Mode Data"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ESC_DATA_BYTE ,CIL-D Escape Mode Data Byte"
|
|
endif
|
|
group.long 0x9f4++0x03
|
|
line.long 0x00 "CSICIL_SW_SENSOR_D_RESET_0,Sensor D Reset"
|
|
bitfld.long 0x00 0. " CSICIL_SENSOR_D_RESET ,Reset CSICIL sensor D" "No reset,Reset"
|
|
textline " "
|
|
tree.end
|
|
tree "CLIE"
|
|
group.long 0xa08++0x03
|
|
line.long 0x00 "PAD_CONFIG0_0,CIL-E Pad Configuration 0"
|
|
bitfld.long 0x00 31. " PAD_CILE_E_TXBW ,Enable VCLAMP regulator" "Enabled,Disabled"
|
|
bitfld.long 0x00 28.--30. " PAD_CILE_SLEWDNADJ ,Pull down slew rate adjust" "0,1,2,3,0,-1,-2,-3"
|
|
bitfld.long 0x00 24.--26. " PAD_CILE_SLEWUPADJ ,Pull up slew rate adjust" "0,1,2,3,0,-1,-2,-3"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " PAD_CILE_LPDNADJ ,Driver pull down impedance control" "130ohm,110ohm,130ohm,150ohm,,,,"
|
|
bitfld.long 0x00 18.--20. " PAD_CILE_LPUPADJ ,Driver pull up impedance control" "130ohm,110ohm,130ohm,150ohm,,,,"
|
|
bitfld.long 0x00 15. " PAD_CILE_BANDWD_IN ,Increase bandwidth of differential receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PAD_CILE_INADJ0 ,bit 0 input delay trimmer" "0,20ps,40ps,60ps,80ps,100ps,120ps,140ps"
|
|
bitfld.long 0x00 4.--6. " PAD_CILE_INADJCLK ,Clock bit input delay trimmer" "0,20ps,40ps,60ps,80ps,100ps,120ps,140ps"
|
|
bitfld.long 0x00 3. " PAD_CILE_PDVCLAMP ,Power down regulator which supplies current to serializer/deserializer logic" "Serializer,Deserializer"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PAD_CILE_PDIO_CLK ,Power down for clock bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " PAD_CILE_PDIO ,Power down for each data bit" "b'00,b'01,b'10,b'11"
|
|
group.long 0xa0c++0x03
|
|
line.long 0x00 "PAD_CONFIG1_0,CIL-E Pad Configuration 4"
|
|
bitfld.long 0x00 6.--7. " PAD_CILE_PEMPD_CLK ,Enable data bit HS driver pull down pre-emphasis" "No pre-emphasis,,,Max"
|
|
bitfld.long 0x00 4.--5. " PAD_CILE_PEMPU_CLK ,Enable data bit HS driver pull up pre-emphasis" "No pre-emphasis,,,Max"
|
|
bitfld.long 0x00 2.--3. " PAD_CILE_PEMPD ,Enable data bit HS driver pull down pre-emphasis" "No pre-emphasis,,,Max"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PAD_CILE_PEMPU ,Enable data bit HS driver pull up pre-emphasis," "No pre-emphasis,,,Max"
|
|
group.long 0xa10++0x07
|
|
line.long 0x00 "PHY_CILE_CONTROL0_0,CSI-E Phy and CIL Control"
|
|
bitfld.long 0x00 8.--13. " CLK_SETTLE ,Settle time for clk lane when moving from LP to HS" "15 cilclk cycles,8 cilclk cycles,9 cilclk cycles,10 cilclk cycles,11 cilclk cycles,12 cilclk cycles,13 cilclk cycles,14 cilclk cycles,Default internal delay,16 cilclk cycles,17 cilclk cycles,18 cilclk cycles,19 cilclk cycles,20 cilclk cycles,21 cilclk cycles,22 cilclk cycles,23 cilclk cycles,24 cilclk cycles,25 cilclk cycles,26 cilclk cycles,27 cilclk cycles,28 cilclk cycles,29 cilclk cycles,30 cilclk cycles,31 cilclk cycles,32 cilclk cycles,33 cilclk cycles,34 cilclk cycles,35 cilclk cycles,36 cilclk cycles,37 cilclk cycles,38 cilclk cycles,39 cilclk cycles,40 cilclk cycles,41 cilclk cycles,42 cilclk cycles,43 cilclk cycles,44 cilclk cycles,45 cilclk cycles,46 cilclk cycles,47 cilclk cycles,48 cilclk cycles,49 cilclk cycles,50 cilclk cycles,51 cilclk cycles,52 cilclk cycles,53 cilclk cycles,54 cilclk cycles,55 cilclk cycles,56 cilclk cycles,57 cilclk cycles,58 cilclk cycles,59 cilclk cycles,60 cilclk cycles,61 cilclk cycles,62 cilclk cycles,63 cilclk cycles,64 cilclk cycles,,,,,,"
|
|
bitfld.long 0x00 6. " BYPASS_LP_SEQ ,CILE_BYPASS_LP_SEQ" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " THS_SETTLE ,Settle time for data lane" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "INTERRUPT_MASK_0,CSI Control and Interface Logic E Interrupt Mask"
|
|
bitfld.long 0x04 9. " CLK_LANE_CTRL_ERR_INT_MASK ,Interrupt Mask for CILE_CLK_CTRL_ERR" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " SPARE_STATUS_1_INT_MASK ,Interrupt Mask for CILE_SPARE_STATUS_1" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " ESC_DATA_REC_INT_MASK ,Interrupt Mask for CILE_ESC_DATA_REC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ESC_CMD_REC_INT_MASK ,Interrupt Mask for CILE_ESC_CMD_REC" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CTRL_ERR_INT_MASK ,Interrupt Mask for CILE_CTRL_ERR" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SYNC_ESC_ERR_INT_MASK ,Interrupt Mask for CILE_SYNC_ESC_ERR" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SOT_MB_ERR_INT_MASK ,Interrupt Mask for CILE_SOT_MB_ERR" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SOT_SB_ERR_INT_MASK ,Interrupt Mask for CILE_SOT_SB_ERR" "Disabled,Enabled"
|
|
rgroup.long 0xa18++0x03
|
|
line.long 0x00 "STATUS_0,CSI Control and Interface Logic E Status"
|
|
bitfld.long 0x00 8. " CLK_LANE_CTRL_ERR ,Control Error" "No error,Error"
|
|
bitfld.long 0x00 6. " ESC_DATA_REC ,Escape Mode Data Received" "No received,Received"
|
|
bitfld.long 0x00 5. " ESC_CMD_REC ,Escape Mode Command Received" "No received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CTRL_ERR ,Control Error" "No error,Error"
|
|
bitfld.long 0x00 2. " SYNC_ESC_ERR ,Sync Escape Error" "No error,Error"
|
|
bitfld.long 0x00 1. " SOT_MB_ERR ,Start of Transmission Multi Bit Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOT_SB_ERR ,Start of Transmission Single Bit Error" "No error,Error"
|
|
if (((d.l(ad:0x54080000+0xa18))&0x20)==0x20)
|
|
rgroup.long 0xa1c++0x03
|
|
line.long 0x00 "ESCAPE_MODE_COMMAND_0,Escape Mode Command"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ESC_CMD_BYTE ,CIL-E Escape Mode Command Byte"
|
|
endif
|
|
if (((d.l(ad:0x54080000+0xa18))&0x40)==0x40)
|
|
rgroup.long 0xa20++0x03
|
|
line.long 0x00 "ESCAPE_MODE_DATA_0,Escape Mode Data"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ESC_DATA_BYTE ,CIL-E Escape Mode Data Byte"
|
|
endif
|
|
group.long 0xa24++0x03
|
|
line.long 0x00 "CSICIL_SW_SENSOR_E_RESET_0,Sensor E Reset"
|
|
bitfld.long 0x00 0. " CSICIL_SENSOR_E_RESET ,Reset CSICIL sensor E" "No reset,Reset"
|
|
tree.end
|
|
textline " "
|
|
tree "PATTERN GENERATOR"
|
|
width 21.
|
|
group.long 0xa68++0x23
|
|
line.long 0x00 "CTRL_A_0,Generator Control A"
|
|
bitfld.long 0x00 2.--3. " MODE_A ,Mode for Sensor A" "DIRECT,PATCH,RSVD,"
|
|
bitfld.long 0x00 1. " AUTO_INC_A ,Automatic phase increment mode for sensor A" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE_A ,Enable Pattern Generator for sensor A" "Disabled,Enabled"
|
|
line.long 0x04 "BLANK_A_0,Blanking for PG"
|
|
hexmask.long.word 0x04 16.--31. 1. " VBLANK_A ,Vertical Blanking for PG"
|
|
hexmask.long.word 0x04 0.--15. 1. " HBLANK_A ,Horizontal Blanking for PG"
|
|
line.long 0x08 "PHASE_A_0,Phase"
|
|
hexmask.long.word 0x08 0.--13. 1. " PHASE_A ,Initial Phase"
|
|
line.long 0x0C "RED_FREQ_A_0,Initial frequency"
|
|
hexmask.long.word 0x0C 16.--29. 1. " RED_VERT_INIT_FREQ_A ,Initial vertical frequency"
|
|
hexmask.long.word 0x0C 0.--13. 1. " RED_HOR_INIT_FREQ_A ,Initial horizontal frequency"
|
|
line.long 0x10 "RED_FREQ_RATE_A_0,Rate of change frequency"
|
|
hexmask.long.byte 0x10 8.--15. 1. " RED_VERT_FREQ_RATE_A ,Rate of change of vertical frequency"
|
|
hexmask.long.byte 0x10 0.--7. 1. " RED_HOR_FREQ_RATE_A ,Rate of change of horizontal frequency"
|
|
line.long 0x14 "GREEN_FREQ_A_0,Initial frequency"
|
|
hexmask.long.word 0x14 16.--29. 1. " GREEN_VERT_INIT_FREQ_A ,Initial vertical frequency"
|
|
hexmask.long.word 0x14 0.--13. 1. " GREEN_HOR_INIT_FREQ_A ,Initial horizontal frequency"
|
|
line.long 0x18 "GREEN_FREQ_RATE_A_0,Rate of change frequency"
|
|
hexmask.long.byte 0x18 8.--15. 1. " GREEN_VERT_FREQ_RATE_A ,Rate of change of vertical frequency"
|
|
hexmask.long.byte 0x18 0.--7. 1. " GREEN_HOR_FREQ_RATE_A ,Rate of change of horizontal frequency"
|
|
line.long 0x1C "BLUE_FREQ_A_0,Initial frequency"
|
|
hexmask.long.word 0x1C 16.--29. 1. " BLUE_VERT_INIT_FREQ_A ,Initial vertical frequency"
|
|
hexmask.long.word 0x1C 0.--13. 1. " BLUE_HOR_INIT_FREQ_A ,Initial horizontal frequency"
|
|
line.long 0x20 "BLUE_FREQ_RATE_A_0,Rate of change frequency"
|
|
hexmask.long.byte 0x20 8.--15. 1. " BLUE_VERT_FREQ_RATE_A ,Rate of change of vertical frequency"
|
|
hexmask.long.byte 0x20 0.--7. 1. " BLUE_HOR_FREQ_RATE_A ,Rate of change of horizontal frequency"
|
|
textline " "
|
|
group.long 0xa9c++0x23
|
|
line.long 0x00 "CTRL_B_0,Generator Control B"
|
|
bitfld.long 0x00 2.--3. " MODE_B ,Mode for Sensor A" "DIRECT,PATCH,RSVD,"
|
|
bitfld.long 0x00 1. " BUTO_INC_B ,Automatic phase increment mode for sensor A" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE_B ,Enable Pattern Generator for sensor A" "Disabled,Enabled"
|
|
line.long 0x04 "BLANK_B_0,Blanking for PG"
|
|
hexmask.long.word 0x04 16.--31. 1. " VBLANK_B ,Vertical Blanking for PG"
|
|
hexmask.long.word 0x04 0.--15. 1. " HBLANK_B ,Horizontal Blanking for PG"
|
|
line.long 0x08 "PHASE_B_0,Phase"
|
|
hexmask.long.word 0x08 0.--13. 1. " PHASE_B ,Initial Phase"
|
|
line.long 0x0C "RED_FREQ_B_0,Initial frequency"
|
|
hexmask.long.word 0x0C 16.--29. 1. " RED_VERT_INIT_FREQ_B ,Initial vertical frequency"
|
|
hexmask.long.word 0x0C 0.--13. 1. " RED_HOR_INIT_FREQ_B ,Initial horizontal frequency"
|
|
line.long 0x10 "RED_FREQ_RATE_B_0,Rate of change frequency"
|
|
hexmask.long.byte 0x10 8.--15. 1. " RED_VERT_FREQ_RATE_B ,Rate of change of vertical frequency"
|
|
hexmask.long.byte 0x10 0.--7. 1. " RED_HOR_FREQ_RATE_B ,Rate of change of horizontal frequency"
|
|
line.long 0x14 "GREEN_FREQ_B_0,Initial frequency"
|
|
hexmask.long.word 0x14 16.--29. 1. " GREEN_VERT_INIT_FREQ_B ,Initial vertical frequency"
|
|
hexmask.long.word 0x14 0.--13. 1. " GREEN_HOR_INIT_FREQ_B ,Initial horizontal frequency"
|
|
line.long 0x18 "GREEN_FREQ_RATE_B_0,Rate of change frequency"
|
|
hexmask.long.byte 0x18 8.--15. 1. " GREEN_VERT_FREQ_RATE_B ,Rate of change of vertical frequency"
|
|
hexmask.long.byte 0x18 0.--7. 1. " GREEN_HOR_FREQ_RATE_B ,Rate of change of horizontal frequency"
|
|
line.long 0x1C "BLUE_FREQ_B_0,Initial frequency"
|
|
hexmask.long.word 0x1C 16.--29. 1. " BLUE_VERT_INIT_FREQ_B ,Initial vertical frequency"
|
|
hexmask.long.word 0x1C 0.--13. 1. " BLUE_HOR_INIT_FREQ_B ,Initial horizontal frequency"
|
|
line.long 0x20 "BLUE_FREQ_RATE_B_0,Rate of change frequency"
|
|
hexmask.long.byte 0x20 8.--15. 1. " BLUE_VERT_FREQ_RATE_B ,Rate of change of vertical frequency"
|
|
hexmask.long.byte 0x20 0.--7. 1. " BLUE_HOR_FREQ_RATE_B ,Rate of change of horizontal frequency"
|
|
textline " "
|
|
tree.end
|
|
width 19.
|
|
group.long 0xad0++0x07
|
|
line.long 0x00 "DPCM_CTRL_A_0,DPCM control A"
|
|
bitfld.long 0x00 8.--11. " DPCM_COMPRESSION_RATIO_A ,DPCM A compression ratio" "BYPASS,10_8_10,10_7_10,10_6_10,12_8_12,12_7_12,12_6_12,14_10_14,14_8_14,,,,,,,"
|
|
bitfld.long 0x00 0. " DPCM_PREDICTOR_A ,DPCM A predictor" "Predictor1,Predictor2"
|
|
textline " "
|
|
line.long 0x04 "DPCM_CTRL_B_0,DPCM control B"
|
|
bitfld.long 0x04 8.--11. " DPCM_COMPRESSION_RATIO_B ,DPCM B compression ratio" "BYPASS,10_8_10,10_7_10,10_6_10,12_8_12,12_7_12,12_6_12,14_10_14,14_8_14,,,,,,,"
|
|
bitfld.long 0x04 0. " DPCM_PREDICTOR_B ,DPCM B predictor" "Predictor1,Predictor2"
|
|
group.long 0xae8++0x03
|
|
line.long 0x00 "STALL_COUNTER_0,Counter"
|
|
hexmask.long.byte 0x00 8.--15. 1. " STALL_SENSOR_B_COUNT ,Number of cycles to stall sensor B after every EOF"
|
|
hexmask.long.byte 0x00 0.--7. 1. " STALL_SENSOR_A_COUNT ,Number of cycles to stall sensor A after every EOF"
|
|
rgroup.long 0xaec++0x03
|
|
line.long 0x00 "READONLY_STATUS_0,CSI Read Only Status"
|
|
bitfld.long 0x00 1. " CSI_PPB_ACTIVE ,One only when Pixel Parser B is capturing frame data" "No active,Active"
|
|
bitfld.long 0x00 0. " CSI_PPA_ACTIVE ,One only when Pixel Parser A is capturing frame data" "No active,Active"
|
|
group.long 0xaf0++0x07
|
|
line.long 0x00 "SW_STATUS_RESET_0,Status reset"
|
|
bitfld.long 0x00 0. " CSI_STATUS_RESET ,Reset CSI status and dbgcnt registers" "No reset,Reset"
|
|
line.long 0x04 "CLKEN_OVERRIDE_0,Second-level clock enable override register"
|
|
bitfld.long 0x04 21. " CILE_CLKEN_OVR ,CILE clock enable override" "CLK_GATED,CLK_ALWAYS_ON"
|
|
bitfld.long 0x04 20. " CILD_CLKEN_OVR ,CILD clock enable override" "CLK_GATED,CLK_ALWAYS_ON"
|
|
bitfld.long 0x04 19. " CILC_CLKEN_OVR ,CILC clock enable override" "CLK_GATED,CLK_ALWAYS_ON"
|
|
textline " "
|
|
bitfld.long 0x04 18. " CILB_CLKEN_OVR ,CILB clock enable override" "CLK_GATED,CLK_ALWAYS_ON"
|
|
bitfld.long 0x04 17. " CILA_CLKEN_OVR ,CILA clock enable override" "CLK_GATED,CLK_ALWAYS_ON"
|
|
textline " "
|
|
bitfld.long 0x04 14. " PPB_CLKEN_OVR ,PPBclock enable override" "CLK_GATED,CLK_ALWAYS_ON"
|
|
bitfld.long 0x04 13. " PPA_CLKEN_OVR ,PPA clock enable override" "CLK_GATED,CLK_ALWAYS_ON"
|
|
textline " "
|
|
bitfld.long 0x04 9. " HPB_CLKEN_OVR ,HPB clock enable override" "CLK_GATED,CLK_ALWAYS_ON"
|
|
bitfld.long 0x04 8. " HPA_CLKEN_OVR ,HPA clock enable override" "CLK_GATED,CLK_ALWAYS_ON"
|
|
textline " "
|
|
bitfld.long 0x04 4. " FB_CLKEN_OVR ,FB clock enable override" "CLK_GATED,CLK_ALWAYS_ON"
|
|
bitfld.long 0x04 3. " FA_CLKEN_OVR ,FA clock enable override" "CLK_GATED,CLK_ALWAYS_ON"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DBG_CLKEN_OVR ,DBG clock enable override" "CLK_GATED,CLK_ALWAYS_ON"
|
|
bitfld.long 0x04 0. " CLKEN_OVR ,Clock enable override" "CLK_GATED,CLK_ALWAYS_ON"
|
|
group.long 0xaf8++0x03
|
|
line.long 0x00 "DEBUG_CONTROL_0,Debug Control"
|
|
rbitfld.long 0x00 31. " DBG_CNT_ROLLED_2 ,Incremented past max count" "No increment,Increment"
|
|
hexmask.long.byte 0x00 24.--30. 1. " DBG_CNT_SEL_2 ,Debug Count Select 2"
|
|
textline " "
|
|
rbitfld.long 0x00 23. " DBG_CNT_ROLLED_1 ,Incremented past max count" "No increment,Increment"
|
|
hexmask.long.byte 0x00 16.--22. 1. " DBG_CNT_SEL_1 ,Debug Count Select 1"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " DBG_CNT_ROLLED_1 ,Incremented past max count" "No increment,Increment"
|
|
hexmask.long.byte 0x00 8.--14. 1. " DBG_CNT_SEL_1 ,Debug Count Select 1"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " CLR_DBG_CNT_2 ,Clear Debug Counter 2" "No effect,Clare"
|
|
rbitfld.long 0x00 6. " CLR_DBG_CNT_1 ,Clear Debug Counter 1" "No effect,Clare"
|
|
rbitfld.long 0x00 5. " CLR_DBG_CNT_0 ,Clear Debug Counter 0" "No effect,Clare"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " CSIB_DBG_SF ,Indicates start frame (SF) or end frame (EF)" "No generated,Generated"
|
|
rbitfld.long 0x00 1. " CSIA_DBG_SF ,Indicates start frame (SF) or end frame (EF)" "No generated,Generated"
|
|
bitfld.long 0x00 0. " DEBUG_EN ,Debug Enable Second level CSI Debug clock is enabled" "Disabled,Enabled"
|
|
rgroup.long 0xAFC++0x03
|
|
line.long 0x00 "DEBUG_COUNTER_0_0,Debug Counter 0"
|
|
rgroup.long 0xB00++0x03
|
|
line.long 0x00 "DEBUG_COUNTER_1_0,Debug Counter 1"
|
|
rgroup.long 0xB04++0x03
|
|
line.long 0x00 "DEBUG_COUNTER_2_0,Debug Counter 2"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MIPI D-PHY Calibration for CSI and DSI (MIPI_CAL)"
|
|
base ad:0x700E3000
|
|
width 25.
|
|
if (((d.l(ad:0x700E3000+0x00))&0x3000000)==0x00)
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "MIPI_CAL_CTRL_0,Calibration Control Register"
|
|
bitfld.long 0x00 26.--29. " MIPI_CAL_NOISE_FLT ,Sensitivity of the noise filter" ",,2,3,4,5,?..."
|
|
bitfld.long 0x00 24.--25. " MIPI_CAL_PRESCALE ,Auto-Cal calibration step prescale" "0.1us,0.5us,1.0us,1.5us"
|
|
bitfld.long 0x00 4. " MIPI_CAL_CLKEN_OVR ,Clock Enable Overflow" "GATED,ALWAYS_ON"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MIPI_CAL_AUTOCAL_EN ,When set, calibration is triggered periodically" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MIPI_CAL_STARTCAL ,Writing a one to this bit starts the Calibration State machine" "Disabled,Enabled"
|
|
line.long 0x04 "AUTOCAL_CTRL0_0,Auto-calibration period in number of APB sys clk cycles"
|
|
else
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "MIPI_CAL_CTRL_0,Calibration Control Register"
|
|
bitfld.long 0x00 26.--29. " MIPI_CAL_NOISE_FLT ,Sensitivity of the noise filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--25. " MIPI_CAL_PRESCALE ,Auto-Cal calibration step prescale" "0.1us,0.5us,1.0us,1.5us"
|
|
bitfld.long 0x00 4. " MIPI_CAL_CLKEN_OVR ,Clock Enable Overflow" "GATED,ALWAYS_ON"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MIPI_CAL_AUTOCAL_EN ,When set, calibration is triggered periodically" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MIPI_CAL_STARTCAL ,Writing a one to this bit starts the Calibration State machine" "Disabled,Enabled"
|
|
line.long 0x04 "AUTOCAL_CTRL0_0,Auto-calibration period in number of APB sys clk cycles"
|
|
endif
|
|
if (((d.l(ad:0x700E3000+0x08))&0x1)==0x00)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CIL_MIPI_CAL_STATUS_0,CIL MIPI Calibrate Status"
|
|
bitfld.long 0x00 29. " MIPI_AUTO_CAL_DONE_DSIB ,MIPI Auto Calibrate done for DSIB" "In progress,Done"
|
|
bitfld.long 0x00 28. " MIPI_AUTO_CAL_DONE_DSIA ,MIPI Auto Calibrate done for DSI" "In progress,Done"
|
|
bitfld.long 0x00 24. " MIPI_AUTO_CAL_DONE_DSIE ,MIPI Auto Calibrate done for CSI" "In progress,Done"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MIPI_AUTO_CAL_DONE_CSID ,MIPI Auto Calibrate done for CSI" "In progress,Done"
|
|
bitfld.long 0x00 22. " MIPI_AUTO_CAL_DONE_CSIC ,Debug bit MIPI Auto Calibrate done for CSI" "In progress,Done"
|
|
bitfld.long 0x00 21. " MIPI_AUTO_CAL_DONE_CSIB ,MIPI Auto Calibrate done for CSI" "In progress,Done"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MIPI_AUTO_CAL_DONE_CSIA ,MIPI Auto Calibrate done for CSI" "In progress,Done"
|
|
bitfld.long 0x00 16. " MIPI_AUTO_CAL_DONE ,MIPI Auto Calibrate done" "In progress,Done"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MIPI_CAL_DRIV_DN_ADJ ,Driver Pull-down calibration code generated by MIPI auto calibrate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " MIPI_CAL_DRIV_UP_ADJ ,Driver Pull up calibration code generated by MIPI auto calibrate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " MIPI_CAL_TERMADJ ,Termination code generated by MIPI auto calibrate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MIPI_CAL_ACTIVE ,Auto calibrate is active" "Not active,Active"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CIL_MIPI_CAL_STATUS_0,CIL MIPI Calibrate Status"
|
|
bitfld.long 0x00 29. " MIPI_AUTO_CAL_DONE_DSIB ,MIPI Auto Calibrate done for DSIB" "In progress,Done"
|
|
bitfld.long 0x00 28. " MIPI_AUTO_CAL_DONE_DSIA ,MIPI Auto Calibrate done for DSI" "In progress,Done"
|
|
bitfld.long 0x00 24. " MIPI_AUTO_CAL_DONE_DSIE ,MIPI Auto Calibrate done for CSI" "In progress,Done"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MIPI_AUTO_CAL_DONE_CSID ,MIPI Auto Calibrate done for CSI" "In progress,Done"
|
|
bitfld.long 0x00 22. " MIPI_AUTO_CAL_DONE_CSIC ,Debug bit MIPI Auto Calibrate done for CSI" "In progress,Done"
|
|
bitfld.long 0x00 21. " MIPI_AUTO_CAL_DONE_CSIB ,MIPI Auto Calibrate done for CSI" "In progress,Done"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MIPI_AUTO_CAL_DONE_CSIA ,MIPI Auto Calibrate done for CSI" "In progress,Done"
|
|
bitfld.long 0x00 16. " MIPI_AUTO_CAL_DONE ,MIPI Auto Calibrate done" "In progress,Done"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 0. " MIPI_CAL_ACTIVE ,Auto calibrate is active" "Not active,Active"
|
|
endif
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CIL_MIPI_CAL_STATUS_2_0,MIPI CLK Calibration Status 2"
|
|
bitfld.long 0x00 4. " MIPI_CLK_AUTO_CAL_DONE_DSIB ,MIPI CLK Auto Calibrate done for DSIB" "In progress,Done"
|
|
bitfld.long 0x00 3. " MIPI_CLK_AUTO_CAL_DONE_DSIA ,MIPI CLK Auto Calibrate done for DSIA" "In progress,Done"
|
|
bitfld.long 0x00 2. " MIPI_CLK_AUTO_CAL_DONE_CSIE ,MIPI CLK Auto Calibrate done for CSIE" "In progress,Done"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MIPI_CLK_AUTO_CAL_DONE_CSID ,MIPI CLK Auto Calibrate done for CSID" "In progress,Done"
|
|
bitfld.long 0x00 0. " MIPI_CLK_AUTO_CAL_DONE_CSIC ,MIPI CLK Auto Calibrate done for CSIC" "In progress,Done"
|
|
textline " "
|
|
width 27.
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CILA_MIPI_CAL_CONFIG_0,Calibration Settings for CIL-A MIPI Pads"
|
|
bitfld.long 0x00 30. " MIPI_CAL_OVERIDEA ,Calibration State machine setting for channel A" "Normal operation,Use the register values"
|
|
bitfld.long 0x00 21. " MIPI_CAL_SELA ,Select the CSIA pads for auto calibration" "No selected,Selected"
|
|
bitfld.long 0x00 16.--20. " MIPI_CAL_HSPDOSA ,Offset for HSPDADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " MIPI_CAL_HSPUOSA ,Offset for HSPUADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x00 0.--4. " MIPI_CAL_TERMOSA ,Offset for TERMADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CILB_MIPI_CAL_CONFIG_0,Calibration Settings for CIL-B MIPI Pads"
|
|
bitfld.long 0x00 30. " MIPI_CAL_OVERIDEB ,Calibration State machine setting for channel B" "Normal operation,Use the register values"
|
|
bitfld.long 0x00 21. " MIPI_CAL_SELB ,Select the CSIB pads for auto calibration" "No selected,Selected"
|
|
bitfld.long 0x00 16.--20. " MIPI_CAL_HSPDOSB ,Offset for HSPDADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " MIPI_CAL_HSPUOSB ,Offset for HSPUADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x00 0.--4. " MIPI_CAL_TERMOSB ,Offset for TERMADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CILC_MIPI_CAL_CONFIG_0,Calibration Settings for CIL-C MIPI Pads"
|
|
bitfld.long 0x00 30. " MIPI_CAL_OVERIDEC ,Calibration State machine setting for channel C" "Normal operation,Use the register values"
|
|
bitfld.long 0x00 21. " MIPI_CAL_SELC ,Select the CSIC pads for auto calibration" "No selected,Selected"
|
|
bitfld.long 0x00 16.--20. " MIPI_CAL_HSPDOSC ,Offset for HSPDADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " MIPI_CAL_HSPUOSC ,Offset for HSPUADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x00 0.--4. " MIPI_CAL_TERMOSC ,Offset for TERMADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CILD_MIPI_CAL_CONFIG_0,Calibration Settings for CIL-D MIPI Pads"
|
|
bitfld.long 0x00 30. " MIPI_CAL_OVERIDED ,Calibration State machine setting for channel D" "Normal operation,Use the register values"
|
|
bitfld.long 0x00 21. " MIPI_CAL_SELD ,Select the CSID pads for auto calibration" "No selected,Selected"
|
|
bitfld.long 0x00 16.--20. " MIPI_CAL_HSPDOSD ,Offset for HSPDADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " MIPI_CAL_HSPUOSD ,Offset for HSPUADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x00 0.--4. " MIPI_CAL_TERMOSD ,Offset for TERMADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CILE_MIPI_CAL_CONFIG_0,Calibration Settings for CIL-E MIPI Pads"
|
|
bitfld.long 0x00 30. " MIPI_CAL_OVERIDEE ,Calibration State machine setting for channel E" "Normal operation,Use the register values"
|
|
bitfld.long 0x00 21. " MIPI_CAL_SELE ,Select the CSIE pads for auto calibration" "No selected,Selected"
|
|
bitfld.long 0x00 16.--20. " MIPI_CAL_HSPDOSE ,Offset for HSPDADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " MIPI_CAL_HSPUOSE ,Offset for HSPUADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x00 0.--4. " MIPI_CAL_TERMOSE ,Offset for TERMADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "CILDSIA_MIPI_CAL_CONFIG_0,Calibration Settings for DSIA MIPI Pads"
|
|
bitfld.long 0x00 30. " MIPI_CAL_OVERIDEDSIA ,Calibration State machine setting for channel DSIA" "Normal operation,Use registers values"
|
|
bitfld.long 0x00 21. " MIPI_CAL_SELDSIA ,Select the DSIA pads for auto calibration" "No selected,Selected"
|
|
bitfld.long 0x00 16.--20. " MIPI_CAL_HSPDOSDSIA ,Offset for HSPDADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " MIPI_CAL_HSPUOSDSIA ,Offset for HSPUADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x00 0.--4. " MIPI_CAL_TERMOSDSIA ,Offset for TERMADJ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
line.long 0x04 "CILDSIB_MIPI_CAL_CONFIG_0,Calibration Settings for DSIB MIPI Pads"
|
|
bitfld.long 0x04 30. " MIPI_CAL_OVERIDEDSIB ,Calibration State machine setting for channel DSIB" "Normal operation,Use registers values"
|
|
bitfld.long 0x04 21. " MIPI_CAL_SELDSIB ,Select the DSIB pads for auto calibration" "No selected,Selected"
|
|
bitfld.long 0x04 16.--20. " MIPI_CAL_HSPDOSDSIB ,Offset for HSPDADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--12. " MIPI_CAL_HSPUOSDSIB ,Offset for HSPUADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x04 0.--4. " MIPI_CAL_TERMOSDSIB ,Offset for TERMADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
group.long 0x58++0x1F
|
|
line.long 0x00 "BIAS_PAD_CFG0_0,MIPI Bias Pad Configuration Register"
|
|
bitfld.long 0x00 1. " MIPI_BIAS_PAD_PDVCLAMP ,Power down regulator which supplies current to pre-driver logic" "Power Up,Power down"
|
|
bitfld.long 0x00 0. " MIPI_BIAS_PAD_E_VCLAMP_REF ,Enable VCLAMP reference voltage" "Disabled,Enabled"
|
|
line.long 0x04 "MIPI_BIAS_PAD_CFG1_0,MIPI Bias Pad Configuration Register"
|
|
bitfld.long 0x04 24.--26. " PAD_TEST_SEL ,Controls which signal to be routed to TEST_OUT" "VAUXP,RUP,RDN,VREG,?..."
|
|
bitfld.long 0x04 16.--18. " PAD_DRIV_DN_REF ,Adjust internal reference level for drive pull-down calibration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 8.--10. " PAD_DRIV_UP_REF ,Adjust internal reference level for drive pull-up calibration" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " PAD_TERM_REF ,Adjust internal reference level for termination calibration" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "CAL_MIPI_BIAS_PAD_CFG2_0,MIPI Bias Pad Configuration Register 2"
|
|
bitfld.long 0x08 16.--18. " PAD_VCLAMP_LEVEL ,VCLAMP level adjustment" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PAD_SPARE ,Spare bit for MIPI Bias Config"
|
|
bitfld.long 0x08 4.--6. " PAD_VAUXP_LEVEL ,VAUXP level adjustment" "No adjustment,105%,110%,115%,No adjustment,95%,90%,85%"
|
|
textline " "
|
|
bitfld.long 0x08 2. " PAD_E_TXBW ,This bit should be set to 0" "0,"
|
|
bitfld.long 0x08 1. " PAD_PDVREG ,Power down voltage regulator" "Power Up,Power down"
|
|
bitfld.long 0x08 0. " PAD_VBYPASS ,Bypass bang gap voltage reference" "Not bypassed,Bypassed"
|
|
line.long 0x0C "DSIA_MIPI_CAL_CONFIG_2_0,Calibration settings for DSIA pad Channel A"
|
|
bitfld.long 0x0C 30. " MIPI_CAL_CLKSELDSIA ,Calibration State machine setting for channel DSIA" "Normal operation,Use the register values"
|
|
bitfld.long 0x0C 21. " MIPI_CAL_SELDSIA ,Select the DSIA PAD Channel A for clock lane auto calibration" "No selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--12. " MIPI_CAL_HSCLKPDOSDSIA ,Offset for HSCLKPDADJ going to Channel B (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x0C 0.--4. " MIPI_CAL_HSCLKPUOSDSIA ,Offset for HSCLKPUADJ going to Channel A (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
line.long 0x10 "DSIB_MIPI_CAL_CONFIG_2_0,Calibration settings for DSIB pad Channel B"
|
|
bitfld.long 0x10 30. " MIPI_CAL_CLKOVERIDEDSIB ,Calibration State machine setting for channel B" "Normal operation,Use the register values"
|
|
bitfld.long 0x10 21. " MIPI_CAL_SELDSIB ,Select the DSIB PAD Channel B for clock lane auto calibration" "No selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x10 8.--12. " MIPI_CAL_HSCLKPDOSDSIB ,Offset for HSCLKPDADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x10 0.--4. " MIPI_CAL_HSCLKPUOSDSIB ,Offset for HSCLKPUADJ (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
line.long 0x14 "CILC_MIPI_CAL_CONFIG_2_0,Calibration settings for DSIB/CSICD pad"
|
|
bitfld.long 0x14 30. " MIPI_CAL_CLKOVERIDEC ,Calibration State machine setting for channel A" "Normal operation,Use the register values"
|
|
bitfld.long 0x14 21. " MIPI_CAL_SELC ,Select the DSIB PAD Channel C for clock lane auto calibration" "No selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x14 8.--12. " MIPI_CAL_HSCLKPDOSC ,Offset for HSCLKPDADJ going to channel A (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x14 0.--4. " MIPI_CAL_HSCLKPUOSC ,Offset for HSCLKPUADJ going to channel A (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
line.long 0x18 "CILD_MIPI_CAL_CONFIG_2_0,Calibration settings for DSIB/CSICD pad"
|
|
bitfld.long 0x18 30. " MIPI_CAL_CLKOVERIDED ,Calibration State machine setting for channel B" "Normal operation,Use the register values"
|
|
bitfld.long 0x18 21. " MIPI_CAL_SELD ,Select the DSIB PAD Channel C for clock lane auto calibration" "No selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x18 8.--12. " MIPI_CAL_HSCLKPDOSD ,Offset for HSCLKPDADJ going to channel B (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x18 0.--4. " MIPI_CAL_HSCLKPUOSD ,Offset for HSCLKPUADJ going to channel B (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
line.long 0x1C "CSIE_MIPI_CAL_CONFIG_2_0,Calibration settings for CSIE MIPI pad"
|
|
bitfld.long 0x1C 30. " MIPI_CAL_CLKOVERIDEE ,Calibration State machine setting for channel A" "Normal operation,Use the register values"
|
|
bitfld.long 0x1C 21. " MIPI_CAL_CLKSELE ,Select the CSIE PAD for clock lane auto calibration." "No selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x1C 8.--12. " MIPI_CAL_HSCLKPDOSE ,Offset for HSCLKPDADJ going to channel B (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
bitfld.long 0x1C 0.--4. " MIPI_CAL_HSCLKPUOSE ,Offset for HSCLKPUADJ going to channel B (2's complement)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "Video Input (VI)"
|
|
base ad:0x54080000
|
|
tree "VI Configuration"
|
|
width 28.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CFG_VI_INCR_SYNCPT_0,CFG_VI_INCR_SYNCPT_0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VI_I2C_COND ,Condition mapped from raise/wait"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VI_I2C_INDX ,Syncpt index value"
|
|
line.long 0x04 "CFG_VI_INCR_SYNCPT_CNTRL_0,CFG_VI_INCR_SYNCPT_CNTRL_0"
|
|
bitfld.long 0x04 8. " VI_INCR_SYNCPT_NO_STALL ,VI INCR SYNCPT NO STALL" "Not running,Running"
|
|
bitfld.long 0x04 0. " INCR_SYNCPT_SOFT_RESET ,Reset all internal state of the client syncpt block" "No reset,Reset"
|
|
line.long 0x08 "CFG_VI_INCR_SYNCPT_ERROR_0,CFG_VI_INCR_SYNCPT_ERROR_0"
|
|
textline " "
|
|
width 25.
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "CTXSW_0,Context Switch Register"
|
|
rbitfld.long 0x00 28.--31. " NEXT_CHANNEL ,Next requested channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 16.--25. 1. " NEXT_CLASS ,Next requested class"
|
|
bitfld.long 0x00 12.--15. " CURR_CHANNEL ,Current working channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AUTO_ACK ,Automatically acknowledge any incoming context switch requests" "Manual,AutoACK"
|
|
hexmask.long.word 0x00 0.--9. 1. " CURR_CLASS ,Current working class"
|
|
line.long 0x04 "INTSTATUS_0,Context Switch Register"
|
|
eventfld.long 0x04 0. " CTXSW_INT ,Context switch interrupt status" "No interrupt,Interrupt"
|
|
group.long 0x38++0x0B
|
|
line.long 0x00 "PWM_CONTROL_0,VI Pulse Width Modulation Control"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PWM_COUNTER ,PWM Counter 8-bit value"
|
|
bitfld.long 0x00 20.--21. " PWM_MODE ,PWM Mode Continuous" "Continuous,Single,Counter,?..."
|
|
bitfld.long 0x00 4. " PWM_DIRECTION ,PWM Direction" "Incrementing,Decrementing"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PWM_ENABLE ,PWM Enable" "Disabled,Enabled"
|
|
line.long 0x04 "CFG_PWM_HIGH_PULSE_0,PWM High Pulse Period"
|
|
line.long 0x08 "CFG_PWM_LOW_PULSE_0,PWM Low Pulse Period"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PWM_SELECT_PULSE_A_0,PWM Pulse Select A"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PWM_SELECT_PULSE_B_0,PWM Pulse Select B"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PWM_SELECT_PULSE_C_0,PWM Pulse Select C"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PWM_SELECT_PULSE_D_0,PWM Pulse Select D"
|
|
if (((per.l(ad:0x54080000+0x64))&0x1030000)==0x1030000)
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CFG_VGP1_0,VI VGP1 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP1_INPUT_ENABLE ,VGP1 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP1 ,Pin Output Select VGP1" "VGP1_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP1_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " VGP1_INPUT_DATA ,VGP1 pin Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " VGP1_OUTPUT_DATA ,VGP1 pin Output Data" "Low,High"
|
|
elif (((per.l(ad:0x54080000+0x64))&0x1030000)==(0x1000000||0x1010000||0x1020000))
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CFG_VGP1_0,VI VGP1 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP1_INPUT_ENABLE ,VGP1 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP1 ,Pin Output Select VGP1" "VGP1_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP1_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " VGP1_INPUT_DATA ,VGP1 pin Input Data" "Low,High"
|
|
elif (((per.l(ad:0x54080000+0x64))&0x1030000)==0x30000)
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CFG_VGP1_0,VI VGP1 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP1_INPUT_ENABLE ,VGP1 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP1 ,Pin Output Select VGP1" "VGP1_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP1_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VGP1_OUTPUT_DATA ,VGP1 pin Output Data" "Low,High"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CFG_VGP1_0,VI VGP1 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP1_INPUT_ENABLE ,VGP1 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP1 ,Pin Output Select VGP1" "VGP1_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP1_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x54080000+0x68))&0x1030000)==0x1030000)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CFG_VGP2_0,VI VGP2 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP2_INPUT_ENABLE ,VGP2 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP2 ,Pin Output Select VGP2" "VGP2_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP2_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " VGP2_INPUT_DATA ,VGP2 pin Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " VGP2_OUTPUT_DATA ,VGP2 pin Output Data" "Low,High"
|
|
elif (((per.l(ad:0x54080000+0x68))&0x1030000)==(0x1000000||0x1010000||0x1020000))
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CFG_VGP2_0,VI VGP2 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP2_INPUT_ENABLE ,VGP2 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP2 ,Pin Output Select VGP2" "VGP2_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP2_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " VGP2_INPUT_DATA ,VGP2 pin Input Data" "Low,High"
|
|
elif (((per.l(ad:0x54080000+0x68))&0x1030000)==0x30000)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CFG_VGP2_0,VI VGP2 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP2_INPUT_ENABLE ,VGP2 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP2 ,Pin Output Select VGP2" "VGP2_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP2_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VGP2_OUTPUT_DATA ,VGP2 pin Output Data" "Low,High"
|
|
else
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CFG_VGP2_0,VI VGP2 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP2_INPUT_ENABLE ,VGP2 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP2 ,Pin Output Select VGP2" "VGP2_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP2_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x54080000+0x6C))&0x1030000)==0x1030000)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CFG_VGP3_0,VI VGP3 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP3_INPUT_ENABLE ,VGP3 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP3 ,Pin Output Select VGP3" "VGP3_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP3_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " VGP3_INPUT_DATA ,VGP3 pin Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " VGP3_OUTPUT_DATA ,VGP3 pin Output Data" "Low,High"
|
|
elif (((per.l(ad:0x54080000+0x6C))&0x1030000)==(0x1000000||0x1010000||0x1020000))
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CFG_VGP3_0,VI VGP3 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP3_INPUT_ENABLE ,VGP3 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP3 ,Pin Output Select VGP3" "VGP3_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP3_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " VGP3_INPUT_DATA ,VGP3 pin Input Data" "Low,High"
|
|
elif (((per.l(ad:0x54080000+0x6C))&0x1030000)==0x30000)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CFG_VGP3_0,VI VGP3 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP3_INPUT_ENABLE ,VGP3 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP3 ,Pin Output Select VGP3" "VGP3_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP3_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VGP3_OUTPUT_DATA ,VGP3 pin Output Data" "Low,High"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CFG_VGP3_0,VI VGP3 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP3_INPUT_ENABLE ,VGP3 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP3 ,Pin Output Select VGP3" "VGP3_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP3_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x54080000+0x70))&0x1030000)==0x1030000)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CFG_VGP4_0,VI VGP4 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP4_INPUT_ENABLE ,VGP4 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP4 ,Pin Output Select VGP4" "VGP4_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP4_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " VGP4_INPUT_DATA ,VGP4 pin Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " VGP4_OUTPUT_DATA ,VGP4 pin Output Data" "Low,High"
|
|
elif (((per.l(ad:0x54080000+0x70))&0x1030000)==(0x1000000||0x1010000||0x1020000))
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CFG_VGP4_0,VI VGP4 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP4_INPUT_ENABLE ,VGP4 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP4 ,Pin Output Select VGP4" "VGP4_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP4_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " VGP4_INPUT_DATA ,VGP4 pin Input Data" "Low,High"
|
|
elif (((per.l(ad:0x54080000+0x70))&0x1030000)==0x30000)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CFG_VGP4_0,VI VGP4 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP4_INPUT_ENABLE ,VGP4 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP4 ,Pin Output Select VGP4" "VGP4_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP4_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VGP4_OUTPUT_DATA ,VGP4 pin Output Data" "Low,High"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CFG_VGP4_0,VI VGP4 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP4_INPUT_ENABLE ,VGP4 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP4 ,Pin Output Select VGP4" "VGP4_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP4_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x54080000+0x74))&0x1030000)==0x1030000)
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CFG_VGP5_0,VI VGP5 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP5_INPUT_ENABLE ,VGP5 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP5 ,Pin Output Select VGP5" "VGP5_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP5_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " VGP5_INPUT_DATA ,VGP5 pin Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " VGP5_OUTPUT_DATA ,VGP5 pin Output Data" "Low,High"
|
|
elif (((per.l(ad:0x54080000+0x74))&0x1030000)==(0x1000000||0x1010000||0x1020000))
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CFG_VGP5_0,VI VGP5 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP5_INPUT_ENABLE ,VGP5 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP5 ,Pin Output Select VGP5" "VGP5_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP5_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " VGP5_INPUT_DATA ,VGP5 pin Input Data" "Low,High"
|
|
elif (((per.l(ad:0x54080000+0x74))&0x1030000)==0x30000)
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CFG_VGP5_0,VI VGP5 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP5_INPUT_ENABLE ,VGP5 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP5 ,Pin Output Select VGP5" "VGP5_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP5_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VGP5_OUTPUT_DATA ,VGP5 pin Output Data" "Low,High"
|
|
else
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CFG_VGP5_0,VI VGP5 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP5_INPUT_ENABLE ,VGP5 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP5 ,Pin Output Select VGP5" "VGP5_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP5_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x54080000+0x78))&0x1030000)==0x1030000)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CFG_VGP6_0,VI VGP6 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP6_INPUT_ENABLE ,VGP6 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP6 ,Pin Output Select VGP6" "VGP6_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP6_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " VGP6_INPUT_DATA ,VGP6 pin Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " VGP6_OUTPUT_DATA ,VGP6 pin Output Data" "Low,High"
|
|
elif (((per.l(ad:0x54080000+0x78))&0x1030000)==(0x1000000||0x1010000||0x1020000))
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CFG_VGP6_0,VI VGP6 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP6_INPUT_ENABLE ,VGP6 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP6 ,Pin Output Select VGP6" "VGP6_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP6_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " VGP6_INPUT_DATA ,VGP6 pin Input Data" "Low,High"
|
|
elif (((per.l(ad:0x54080000+0x78))&0x1030000)==0x30000)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CFG_VGP6_0,VI VGP6 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP6_INPUT_ENABLE ,VGP6 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP6 ,Pin Output Select VGP6" "VGP6_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP6_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VGP6_OUTPUT_DATA ,VGP6 pin Output Data" "Low,High"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CFG_VGP6_0,VI VGP6 Input/Output Config/Data"
|
|
bitfld.long 0x00 24. " VGP6_INPUT_ENABLE ,VGP6 pin Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PIN_OUTPUT_SELECT_VGP6 ,Pin Output Select VGP6" "VGP6_OUTPUT_DATA,1"
|
|
bitfld.long 0x00 16. " VGP6_OUTPUT_ENABLE ,VGPn pin Output Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
width 33.
|
|
group.long 0x8C++0x07
|
|
line.long 0x00 "CFG_INTERRUPT_MASK_0,Interrupt Mask"
|
|
bitfld.long 0x00 6. " VGP6_INT_MASK ,VGP6 pin Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VGP5_INT_MASK ,VGP5 pin Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VGP4_INT_MASK ,VGP4 pin Interrupt Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VGP3_INT_MASK ,VGP3 pin Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " VGP2_INT_MASK ,VGP2 pin Interrupt Mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " VGP1_INT_MASK ,VGP1 pin Interrupt Mask" "Disabled,Enabled"
|
|
line.long 0x04 "CFG_INTERRUPT_TYPE_SELECT_0,Interrupt Type Select"
|
|
bitfld.long 0x04 6. " VGP6_INT_POLARITY ,VGP6 pin Interrupt Type" "Low,High"
|
|
bitfld.long 0x04 5. " VGP5_INT_POLARITY ,VGP5 pin Interrupt Type" "Low,High"
|
|
bitfld.long 0x04 4. " VGP4_INT_POLARITY ,VGP4 pin Interrupt Type" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 3. " VGP3_INT_POLARITY ,VGP3 pin Interrupt Type" "Low,High"
|
|
bitfld.long 0x04 2. " VGP2_INT_POLARITY ,VGP2 pin Interrupt Type" "Low,High"
|
|
bitfld.long 0x04 1. " VGP1_INT_POLARITY ,VGP1 pin Interrupt Type" "Low,High"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CFG_INTERRUPT_POLARITY_SELECT_0,Interrupt Polarity Select"
|
|
bitfld.long 0x00 6. " VGP6_INT_POLARITY ,VGP6 pin Interrupt Type" "Low,High"
|
|
bitfld.long 0x00 5. " VGP5_INT_POLARITY ,VGP5 pin Interrupt Type" "Low,High"
|
|
bitfld.long 0x00 4. " VGP4_INT_POLARITY ,VGP4 pin Interrupt Type" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VGP3_INT_POLARITY ,VGP3 pin Interrupt Type" "Low,High"
|
|
bitfld.long 0x00 2. " VGP2_INT_POLARITY ,VGP2 pin Interrupt Type" "Low,High"
|
|
bitfld.long 0x00 1. " VGP1_INT_POLARITY ,VGP1 pin Interrupt Type" "Low,High"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "CFG_INTERRUPT_STATUS_0,Interrupt Enable"
|
|
bitfld.long 0x00 6. " VGP6_INT_STATUS ,VGP6 pin Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " VGP5_INT_STATUS ,VGP5 pin Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " VGP4_INT_STATUS ,VGP4 pin Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VGP3_INT_STATUS ,VGP3 pin Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " VGP2_INT_STATUS ,VGP2 pin Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " VGP1_INT_STATUS ,VGP1 pin Interrupt Status" "No interrupt,Interrupt"
|
|
group.long 0xac++0x03
|
|
line.long 0x00 "CFG_VGP_SYNCPT_CONFIG_0,VGP syncpt config"
|
|
bitfld.long 0x00 4.--6. " SYNCPT_VGPY_SELECT ,Selects the VGP for SYNCPT condition VGP_1_RECD" "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x00 0.--2. " SYNCPT_VGPX_SELECT ,Selects the VGP for SYNCPT condition VGP_0_RECD" "1,2,3,4,5,6,?..."
|
|
group.long 0xb4++0x07
|
|
line.long 0x00 "CFG_VI_SW_RESET_0,SW Reset"
|
|
bitfld.long 0x00 0. " MCCIF_RESET ,Resets the MCCIF interface" "No reset,Reset"
|
|
line.long 0x04 "CFG_CG_CTRL_0,CG Control"
|
|
bitfld.long 0x04 0. " CG_2ND_LEVEL_EN ,Second-level clock gating control" "Disabled,Enabled"
|
|
sif (cpu()=="TEGRAX1")
|
|
group.long 0xDC++0x07
|
|
line.long 0x00 "CFG_VI_MCCIF_FIFOCTRL_0,Memory Client Interface FIFO Control Register"
|
|
bitfld.long 0x00 20. " VI_RCLK_OVR_MODE ,VI_RCLK_OVR_MODE" "LEGACY,ON"
|
|
bitfld.long 0x00 19. " VI_WCLK_OVR_MODE ,VI_WCLK_OVR_MODE" "LEGACY,ON"
|
|
bitfld.long 0x00 18. " VI_CCLK_OVERRIDE ,VI_CCLK_OVERRIDE" "Not override,Override"
|
|
textline " "
|
|
bitfld.long 0x00 17. " VI_RCLK_OVERRIDE ,VI_RCLK_OVERRIDE" "Not override,Override"
|
|
bitfld.long 0x00 16. " VI_WCLK_OVERRIDE ,VI_WCLK_OVERRIDE" "Not override,Override"
|
|
bitfld.long 0x00 1. " VI_MCCIF_RDMC_RDFAST ,VI_MCCIF_RDMC_RDFAST" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VI_MCCIF_WRCL_MCLE2X ,VI_MCCIF_WRCL_MCLE2X" "Disabled,Enabled"
|
|
line.long 0x04 "CFG_TIMEOUT_WCOAL_VI_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " VIWSB_WCOAL_TMVAL ,VIWSB_WCOAL_TMVAL"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "CFG_DVFS_0,Dynamic Voltage Frequency Shift Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " SENSORB_LB_THRESHOLD ,Defines the DVFS threshold for the VI Line buffer for Sensor B"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SENSORA_LB_THRESHOLD ,Defines the DVFS threshold for the VI Line buffer for Sensor A"
|
|
hexmask.long.word 0x00 0.--8. 1. " MCCIF_THRESHOLD ,This field defines the DVFS threshold for the MCCIF FIFO"
|
|
group.long 0xF0++0x07
|
|
line.long 0x00 "CFG_DVFS_1_0,Dynamic Voltage Frequency Shift Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " SENSORF_LB_THRESHOLD ,Defines the DVFS threshold for VI Line buffer for Sensor B"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SENSORE_LB_THRESHOLD ,Defines the DVFS threshold for VI Line buffer for Sensor B"
|
|
hexmask.long.byte 0x00 8.--14. 1. " SENSORD_LB_THRESHOLD ,Defines the DVFS threshold for VI Line buffer for Sensor B"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " SENSORC_LB_THRESHOLD ,Defines the DVFS threshold for VI Line buffer for Sensor A"
|
|
line.long 0x04 "CFG_DVFSFIFO_CNTRL_0,CFG DVFSFIFO CNTRL 0"
|
|
hexmask.long.word 0x04 0.--8. 1. " DVFS_WR_LIMIT_VAL ,DVFS_WR_LIMIT_VAL"
|
|
else
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CFG_VI_MCCIF_FIFOCTRL_0,Memory Client Interface FIFO Control Register and Clock Gating Control"
|
|
bitfld.long 0x00 20. " VI_RCLK_OVR_MODE ,VI_RCLK_OVR_MODE" "LEGANCY,ON"
|
|
bitfld.long 0x00 19. " VI_WCLK_OVR_MODE ,VI_WCLK_OVR_MODE" "LEGANCY,ON"
|
|
bitfld.long 0x00 18. " VI_CCLK_OVERRIDE ,VI_CCLK_OVERRIDE" "Not override,Override"
|
|
textline " "
|
|
bitfld.long 0x00 17. " VI_RCLK_OVERRIDE ,VI_RCLK_OVERRIDE" "Not override,Override"
|
|
bitfld.long 0x00 16. " VI_WCLK_OVERRIDE ,VI_WCLK_OVERRIDE" "Not override,Override"
|
|
bitfld.long 0x00 1. " VI_MCCIF_RDMC_RDFAST ,VI_MCCIF_RDMC_RDFAST" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VI_MCCIF_WRCL_MCLE2X ,VI_MCCIF_WRCL_MCLE2X" "Disabled,Enabled"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CFG_DVFS_0,Dynamic Voltage Frequency Shift Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " SENSORB_LB_THRESHOLD ,Defines the DVFS threshold for the VI Line buffer for Sensor B"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SENSORA_LB_THRESHOLD ,Defines the DVFS threshold for the VI Line buffer for Sensor A"
|
|
hexmask.long.byte 0x00 0.--6. 1. " MCCIF_THRESHOLD ,Defines the DVFS threshold for the MCCIF FIFO"
|
|
endif
|
|
tree.end
|
|
tree "VI Input CSI Interface Registers"
|
|
tree "CSI 0"
|
|
width 18.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CSI_0_SW_RESET_0,SW reset"
|
|
bitfld.long 0x00 4. " ISPINTF_RESET ,Reset ISP interface" "No reset,Reset"
|
|
bitfld.long 0x00 3. " MCINTF_RESET ,Reset Memory Client i/f logic" "No reset,Reset"
|
|
bitfld.long 0x00 2. " PF_RESET ,Reset Pixel format logic" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SENSORCTL_RESET ,Reset Sensor control logic" "No reset,Reset"
|
|
bitfld.long 0x00 0. " SHADOW_RESET ,Reset Shadow copy logic" "No reset,Reset"
|
|
textline " "
|
|
width 34.
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "CSI_0_SINGLE_SHOT_0,Single shot state"
|
|
bitfld.long 0x00 0. " CAPTURE ,single shot capture for the VI channel" "No active,Active"
|
|
group.long 0x108++0x1B
|
|
line.long 0x00 "CSI_0_SINGLE_SHOT_STATE_UPDATE_0,Single shot state update"
|
|
bitfld.long 0x00 0. " CAPTURE_GOOD_FRAME ,State of previous frame" "Not correct,Correct"
|
|
line.long 0x04 "CSI_0_IMAGE_DEF_0,CSI 0 IMAGE DEF 0"
|
|
bitfld.long 0x04 24. " BYPASS_PXL_TRANSFORM ,Bypass pixel transformation VI" "Not bypassed,Bypassed"
|
|
hexmask.long.byte 0x04 16.--23. 1. " FORMAT ,Pixel memory format for the VI channel In the enums below"
|
|
bitfld.long 0x04 8. " INTERLEAVING_MODE ,Enable Inverting Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DEST_ISPB ,Send VI channel data to ISPB" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " DEST_ISPA ,Send VI channel data to ISPA" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " DEST_MEM ,Send VI channel data to MEM" "Disabled,Enabled"
|
|
line.long 0x08 "CSI_0_RGB2Y_CTRL_0,RGB Control"
|
|
bitfld.long 0x08 18.--23. " B2Y_COEFF ,Blue coefficient used to convert RGB pixel data to Y for writing to Memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 10.--15. " G2Y_COEFF ,Green coefficient used to convert RGB pixel data to Y for writing to Memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 2.--7. " R2Y_COEFF ,Red coefficient used to convert RGB pixel data to Y for writing to Memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "CSI_0_MEM_TILING_0,Memory Tiling"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " TILING_FORMAT ,VI channel memory surface tiling format"
|
|
line.long 0x10 "CSI_0_CSI_IMAGE_SIZE_0,Image size"
|
|
hexmask.long.word 0x10 16.--31. 1. " HEIGHT ,Height of VI channel frame in Lines"
|
|
hexmask.long.word 0x10 0.--15. 1. " WIDTH ,Width of VI channel frame in Lines"
|
|
line.long 0x14 "CSI_0_CSI_IMAGE_SIZE_WC_0,Image size"
|
|
hexmask.long.word 0x14 0.--15. 1. " WORDCOUNT ,VI channel word count for the Image"
|
|
line.long 0x18 "CSI_0_CSI_IMAGE_DT_0,CSI 0 CSI IMAGE DT 0"
|
|
bitfld.long 0x18 12. " INTERLACED_VIDEO ,VI channel interlaced video format enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 8.--9. " VC ,VI channel virtual channel ID" "0,1,2,3"
|
|
bitfld.long 0x18 0.--5. " DATA_TYPE ,VI channel input data type" ",,,,,,,,,,,,,,,,,,EMBED,,,,,,YUV420_8,YUV420_10,LEG_YUV420_8,,YUV420CSPS_8,YUV420CSPS_10,YUV422_8,YUV422_10,RGB444,RGB555,RGB565,RGB666,RGB888,,,,RAW6,RAW7,RAW8,RAW10,RAW12,RAW14,,,ARB_DT1,ARB_DT2,ARB_DT3,ARB_DT4,,,,,,,,,,,,"
|
|
group.long 0x124++0x07
|
|
line.long 0x00 "CSI_0_SURFACE0_OFFSET_MSB_0,Base address MSB"
|
|
bitfld.long 0x00 0.--1. " OFFSET_MSB_0 ,Base address MSB for Surface 0 in Memory" "0,1,2,3"
|
|
line.long 0x04 "CSI_0_SURFACE0_OFFSET_LSB_0,Base address LSB"
|
|
group.long 0x12C++0x07
|
|
line.long 0x00 "CSI_0_SURFACE1_OFFSET_MSB_0,Base address MSB"
|
|
bitfld.long 0x00 0.--1. " OFFSET_MSB_0 ,Base address MSB for Surface 0 in Memory" "0,1,2,3"
|
|
line.long 0x04 "CSI_0_SURFACE1_OFFSET_LSB_0,Base address LSB"
|
|
group.long 0x134++0x07
|
|
line.long 0x00 "CSI_0_SURFACE2_OFFSET_MSB_0,Base address MSB"
|
|
bitfld.long 0x00 0.--1. " OFFSET_MSB_0 ,Base address MSB for Surface 0 in Memory" "0,1,2,3"
|
|
line.long 0x04 "CSI_0_SURFACE2_OFFSET_LSB_0,Base address LSB"
|
|
group.long 0x13C++0x07
|
|
line.long 0x00 "CSI_0_SURFACE0_BF_OFFSET_MSB_0,Base address MSB"
|
|
bitfld.long 0x00 0.--1. " OFFSET_MSB_0 ,Base address MSB for Surface 0 in Memory" "0,1,2,3"
|
|
line.long 0x04 "CSI_0_SURFACE0_BF_OFFSET_LSB_0,Base address LSB"
|
|
group.long 0x144++0x07
|
|
line.long 0x00 "CSI_0_SURFACE1_BF_OFFSET_MSB_0,Base address MSB"
|
|
bitfld.long 0x00 0.--1. " OFFSET_MSB_0 ,Base address MSB for Surface 0 in Memory" "0,1,2,3"
|
|
line.long 0x04 "CSI_0_SURFACE1_BF_OFFSET_LSB_0,Base address LSB"
|
|
group.long 0x14C++0x07
|
|
line.long 0x00 "CSI_0_SURFACE2_BF_OFFSET_MSB_0,Base address MSB"
|
|
bitfld.long 0x00 0.--1. " OFFSET_MSB_0 ,Base address MSB for Surface 0 in Memory" "0,1,2,3"
|
|
line.long 0x04 "CSI_0_SURFACE2_BF_OFFSET_LSB_0,Base address LSB"
|
|
textline " "
|
|
width 25.
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "CSI_0_SURFACE0_STRIDE_0,CSI_0_SURFACE0_STRIDE_0"
|
|
hexmask.long.word 0x00 0.--15. 1. " STRIDE_0 ,Stride for Surface 0 in Memory"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "CSI_0_SURFACE1_STRIDE_0,CSI_0_SURFACE1_STRIDE_0"
|
|
hexmask.long.word 0x00 0.--15. 1. " STRIDE_1 ,Stride for Surface 1 in Memory"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "CSI_0_SURFACE2_STRIDE_0,CSI_0_SURFACE2_STRIDE_0"
|
|
hexmask.long.word 0x00 0.--15. 1. " STRIDE_2 ,Stride for Surface 2 in Memory"
|
|
group.long 0x160++0x07
|
|
line.long 0x00 "CSI_0_SURFACE_HEIGHT0_0,Surface Height"
|
|
bitfld.long 0x00 0.--3. " GOBS ,Number of GOBs stacked verically to form a block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CSI_0_ISPINTF_CONFIG_0,ISP Configure"
|
|
bitfld.long 0x04 1.--2. " CHROMA_POS ,Stream format" "MPEG1,MPEG2,,"
|
|
bitfld.long 0x04 0. " DO_YUV_INTERP ,Chroma Interpolator" "Bypass,Run YUV"
|
|
textline " "
|
|
width 24.
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "CSI_1_ERROR_STATUS_0,Error Status"
|
|
eventfld.long 0x00 5. " WATCHDOG_INT ,Occurs when Watchdog timer expires" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " CSI_FRAME_ERROR ,Flagged if EOF field from CSI has FRAME_ERROR" "No error,Error"
|
|
eventfld.long 0x00 3. " FRAME_HEIGHT_LONG_ERROR ,Flagged if frame height is larger than HEIGHT" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 2. " FRAME_HEIGHT_SHORT_ERROR ,Flagged if frame height is smaller than HEIGHT" "No error,Error"
|
|
eventfld.long 0x00 1. " LINE_WIDTH_LONG_ERROR ,Flagged if frame line width is larger than WIDTH" "No error,Error"
|
|
eventfld.long 0x00 0. " LINE_WIDTH_SHORT_ERROR ,Flagged if frame line width is smaller than WIDTH" "No error,Error"
|
|
rgroup.long 0x188++0x0B
|
|
line.long 0x00 "CSI_0_ERROR_INT_MASK_0,Error Interrupt Mask"
|
|
bitfld.long 0x00 5. " WATCHDOG_INT_MASK ,Watchdog Timer 0 Interrupt Mask This controls interrupt when WATCHDOG trigger event occurs" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CSI_FRAME_INT_MASK ,CSI error interrupt mask" "No error,Error"
|
|
bitfld.long 0x00 3. " FRAME_HEIGHT_LONG_INT_MASK ,Frame height long error interrupt mask" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FRAME_HEIGHT_SHORT_INT_MASK ,Frame height short error interrupt mask" "No error,Error"
|
|
bitfld.long 0x00 1. " LINE_WIDTH_LONG_INT_MASK ,Line width long error interrupt mask" "No error,Error"
|
|
bitfld.long 0x00 0. " LINE_WIDTH_SHORT_INT_MASK ,Line width short error interrupt mask" "No error,Error"
|
|
line.long 0x04 "CSI_0_WD_CTRL_0,Watch Dog Timer Control Register"
|
|
bitfld.long 0x04 0. " WD_ENABLE ,Watch Dog Timer Enable" "Disabled,Enabled"
|
|
line.long 0x08 "CSI_0_WD_PERIOD_0,Watch Dog Timer Period"
|
|
tree.end
|
|
tree "CSI 1"
|
|
width 18.
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "CSI_1_SW_RESET_0,SW reset"
|
|
bitfld.long 0x00 4. " ISPINTF_RESET ,Reset ISP interface" "No reset,Reset"
|
|
bitfld.long 0x00 3. " MCINTF_RESET ,Reset Memory Client i/f logic" "No reset,Reset"
|
|
bitfld.long 0x00 2. " PF_RESET ,Reset Pixel format logic" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SENSORCTL_RESET ,Reset Sensor control logic" "No reset,Reset"
|
|
bitfld.long 0x00 0. " SHADOW_RESET ,Reset Shadow copy logic" "No reset,Reset"
|
|
textline " "
|
|
width 34.
|
|
rgroup.long 0x204++0x03
|
|
line.long 0x00 "CSI_1_SINGLE_SHOT_0,Single shot state"
|
|
bitfld.long 0x00 0. " CAPTURE ,single shot capture for the VI channel" "No active,Active"
|
|
group.long 0x208++0x1B
|
|
line.long 0x00 "CSI_1_SINGLE_SHOT_STATE_UPDATE_0,Single shot state update"
|
|
bitfld.long 0x00 0. " CAPTURE_GOOD_FRAME ,State of previous frame" "Not correct,Correct"
|
|
line.long 0x04 "CSI_1_IMAGE_DEF_0,CSI_1_IMAGE_DEF_0"
|
|
bitfld.long 0x04 24. " BYPASS_PXL_TRANSFORM ,Bypass pixel transformation VI" "Not bypassed,Bypassed"
|
|
hexmask.long.byte 0x04 16.--23. 1. " FORMAT ,Pixel memory format for the VI channel In the enums below"
|
|
bitfld.long 0x04 8. " INTERLEAVING_MODE ,Enable Inverting Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DEST_ISPB ,Send VI channel data to ISPB" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " DEST_ISPA ,Send VI channel data to ISPA" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " DEST_MEM ,Send VI channel data to MEM" "Disabled,Enabled"
|
|
line.long 0x08 "CSI_1_RGB2Y_CTRL_0,RGB Control"
|
|
bitfld.long 0x08 18.--23. " B2Y_COEFF ,Blue coefficient used to convert RGB pixel data to Y for writing to Memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 10.--15. " G2Y_COEFF ,Green coefficient used to convert RGB pixel data to Y for writing to Memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 2.--7. " R2Y_COEFF ,Red coefficient used to convert RGB pixel data to Y for writing to Memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "CSI_1_MEM_TILING_0,Memory Tiling"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " TILING_FORMAT ,VI channel memory surface tiling format"
|
|
line.long 0x10 "CSI_1_CSI_IMAGE_SIZE_0,Image size"
|
|
hexmask.long.word 0x10 16.--31. 1. " HEIGHT ,Height of VI channel frame in Lines"
|
|
hexmask.long.word 0x10 0.--15. 1. " WIDTH ,Width of VI channel frame in Lines"
|
|
line.long 0x14 "CSI_1_CSI_IMAGE_SIZE_WC_0,Image size"
|
|
hexmask.long.word 0x14 0.--15. 1. " WORDCOUNT ,VI channel word count for the Image"
|
|
line.long 0x18 "CSI_1_CSI_IMAGE_DT_0,CSI_1_CSI_IMAGE_DT_0"
|
|
bitfld.long 0x18 12. " INTERLACED_VIDEO ,VI channel interlaced video format enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 8.--9. " VC ,VI channel virtual channel ID" "0,1,2,3"
|
|
bitfld.long 0x18 0.--5. " DATA_TYPE ,VI channel input data type" ",,,,,,,,,,,,,,,,,,EMBED,,,,,,YUV420_8,YUV420_10,LEG_YUV420_8,,YUV420CSPS_8,YUV420CSPS_10,YUV422_8,YUV422_10,RGB444,RGB555,RGB565,RGB666,RGB888,,,,RAW6,RAW7,RAW8,RAW10,RAW12,RAW14,,,ARB_DT1,ARB_DT2,ARB_DT3,ARB_DT4,,,,,,,,,,,,"
|
|
group.long 0x224++0x07
|
|
line.long 0x00 "CSI_1_SURFACE0_OFFSET_MSB_0,Base address MSB"
|
|
bitfld.long 0x00 0.--1. " OFFSET_MSB_0 ,Base address MSB for Surface 0 in Memory" "0,1,2,3"
|
|
line.long 0x04 "CSI_1_SURFACE0_OFFSET_LSB_0,Base address LSB"
|
|
group.long 0x22C++0x07
|
|
line.long 0x00 "CSI_1_SURFACE1_OFFSET_MSB_0,Base address MSB"
|
|
bitfld.long 0x00 0.--1. " OFFSET_MSB_0 ,Base address MSB for Surface 0 in Memory" "0,1,2,3"
|
|
line.long 0x04 "CSI_1_SURFACE1_OFFSET_LSB_0,Base address LSB"
|
|
group.long 0x234++0x07
|
|
line.long 0x00 "CSI_1_SURFACE2_OFFSET_MSB_0,Base address MSB"
|
|
bitfld.long 0x00 0.--1. " OFFSET_MSB_0 ,Base address MSB for Surface 0 in Memory" "0,1,2,3"
|
|
line.long 0x04 "CSI_1_SURFACE2_OFFSET_LSB_0,Base address LSB"
|
|
group.long 0x23C++0x07
|
|
line.long 0x00 "CSI_1_SURFACE0_BF_OFFSET_MSB_0,Base address MSB"
|
|
bitfld.long 0x00 0.--1. " OFFSET_MSB_0 ,Base address MSB for Surface 0 in Memory" "0,1,2,3"
|
|
line.long 0x04 "CSI_1_SURFACE0_BF_OFFSET_LSB_0,Base address LSB"
|
|
group.long 0x244++0x07
|
|
line.long 0x00 "CSI_1_SURFACE1_BF_OFFSET_MSB_0,Base address MSB"
|
|
bitfld.long 0x00 0.--1. " OFFSET_MSB_0 ,Base address MSB for Surface 0 in Memory" "0,1,2,3"
|
|
line.long 0x04 "CSI_1_SURFACE1_BF_OFFSET_LSB_0,Base address LSB"
|
|
group.long 0x24C++0x07
|
|
line.long 0x00 "CSI_1_SURFACE2_BF_OFFSET_MSB_0,Base address MSB"
|
|
bitfld.long 0x00 0.--1. " OFFSET_MSB_0 ,Base address MSB for Surface 0 in Memory" "0,1,2,3"
|
|
line.long 0x04 "CSI_1_SURFACE2_BF_OFFSET_LSB_0,Base address LSB"
|
|
textline " "
|
|
width 25.
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "CSI_1_SURFACE0_STRIDE_0,CSI_1_SURFACE0_STRIDE_0"
|
|
hexmask.long.word 0x00 0.--15. 1. " STRIDE_0 ,Stride for Surface 0 in Memory"
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "CSI_1_SURFACE1_STRIDE_0,CSI_1_SURFACE1_STRIDE_0"
|
|
hexmask.long.word 0x00 0.--15. 1. " STRIDE_1 ,Stride for Surface 1 in Memory"
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "CSI_1_SURFACE2_STRIDE_0,CSI_1_SURFACE2_STRIDE_0"
|
|
hexmask.long.word 0x00 0.--15. 1. " STRIDE_2 ,Stride for Surface 2 in Memory"
|
|
group.long 0x260++0x07
|
|
line.long 0x00 "CSI_1_SURFACE_HEIGHT0_0,Surface Height"
|
|
bitfld.long 0x00 0.--3. " GOBS ,Number of GOBs stacked verically to form a block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CSI_1_ISPINTF_CONFIG_0,ISP Configure"
|
|
bitfld.long 0x04 1.--2. " CHROMA_POS ,Stream format" "MPEG1,MPEG2,,"
|
|
bitfld.long 0x04 0. " DO_YUV_INTERP ,Chroma Interpolator" "Bypass,Run YUV"
|
|
textline " "
|
|
width 24.
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "CSI_1_ERROR_STATUS_0,Error Status"
|
|
rbitfld.long 0x00 5. " WATCHDOG_INT ,Occurs when Watchdog timer expires" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 4. " CSI_FRAME_ERROR ,Flagged if EOF field from CSI has FRAME_ERROR" "No error,Error"
|
|
eventfld.long 0x00 3. " FRAME_HEIGHT_LONG_ERROR ,Flagged if frame height is larger than HEIGHT" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 2. " FRAME_HEIGHT_SHORT_ERROR ,Flagged if frame height is smaller than HEIGHT" "No error,Error"
|
|
eventfld.long 0x00 1. " LINE_WIDTH_LONG_ERROR ,Flagged if frame line width is larger than WIDTH" "No error,Error"
|
|
eventfld.long 0x00 0. " LINE_WIDTH_SHORT_ERROR ,Flagged if frame line width is smaller than WIDTH" "No error,Error"
|
|
rgroup.long 0x288++0x0B
|
|
line.long 0x00 "CSI_1_ERROR_INT_MASK_0,Error Interrupt Mask"
|
|
bitfld.long 0x00 5. " WATCHDOG_INT_MASK ,Watchdog Timer 0 Interrupt Mask This controls interrupt when WATCHDOG trigger event occurs" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CSI_FRAME_INT_MASK ,CSI error interrupt mask" "No error,Error"
|
|
bitfld.long 0x00 3. " FRAME_HEIGHT_LONG_INT_MASK ,Frame height long error interrupt mask" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FRAME_HEIGHT_SHORT_INT_MASK ,Frame height short error interrupt mask" "No error,Error"
|
|
bitfld.long 0x00 1. " LINE_WIDTH_LONG_INT_MASK ,Line width long error interrupt mask" "No error,Error"
|
|
bitfld.long 0x00 0. " LINE_WIDTH_SHORT_INT_MASK ,Line width short error interrupt mask" "No error,Error"
|
|
line.long 0x04 "CSI_1_WD_CTRL_0,Watch Dog Timer Control Register"
|
|
bitfld.long 0x04 0. " WD_ENABLE ,Watch Dog Timer Enable" "Disabled,Enabled"
|
|
line.long 0x08 "CSI_1_WD_PERIOD_0,Watch Dog Timer Period"
|
|
tree.end
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "SNOR (GMI) Controller"
|
|
base ad:0x70009000
|
|
width 16.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "CONFIG_0,SNOR Configuration Register"
|
|
bitfld.long 0x00 31. " GO_NOR ,When set a NOR operation commences" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " WORDWIDE_GMI ,NOR Device DataBus width Configuration Bit" "NOR16BIT,NOR32BIT"
|
|
bitfld.long 0x00 29. " NOR_DEVICE_TYPE ,External NOR Memory Type" "SNOR,"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MUXMODE_GMI ,NOR Device Address-Data Configuration Bit" "AD_NONMUX,AD_MUX"
|
|
bitfld.long 0x00 26.--27. " BURST_LENGTH ,Burst Length" "Continuous Burst,8 Words,16 Words,32 Words"
|
|
bitfld.long 0x00 24. " RDY_ACTIVE ,Device RDY Active Status" "With Data,1 Cycle Before Data"
|
|
textline " "
|
|
bitfld.long 0x00 23. " RDY_POLARITY ,Ready signal polarity" "Active low,Active high"
|
|
bitfld.long 0x00 22. " ADV_POLARITY ,ADV pulse polarity" "Active low,Active high"
|
|
bitfld.long 0x00 21. " OE_WE_POLARITY ,OE/WE polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CS_POLARITY ,Chip Select polarity" "Active low,Active high"
|
|
bitfld.long 0x00 19. " NOR_DPD ,Indicates the Power Down Mode enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " NOR_WP ,Sets the NOR Write protect enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " NMUX_ASYNC_IO ,Sets the non-mux async IO mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " PAGE_SIZE ,Sets the number of words in a page if page mode is selected" ",PG4WORD,PG8WORD,PG16WORD,?..."
|
|
bitfld.long 0x00 7. " MST_ENB ,Selection bit between Master DMA and Slave Interface" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " SNOR_SEL ,SNOR 8 chip selects combinations" "CS0,CS1,CS2,CS3,CS4,CS5,CS6,CS7"
|
|
bitfld.long 0x00 3. " CE_LAST ,Indicates if the ADV gets asserted before CE" "Disabled,"
|
|
bitfld.long 0x00 2. " CE_FIRST ,Indicates if the CE gets asserted before ADV" "Disabled,"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DEVICE_MODE ,Specifies the Mode of Operation for SYNC Memories" "ASYNC,PAGE,BURST,"
|
|
line.long 0x04 "STA_0,SNOR Status Register"
|
|
rbitfld.long 0x04 31. " DEVICE_BSY ,Device status" "Idle,Busy"
|
|
bitfld.long 0x04 30. " SLAVE_DONE ,Indicates that the slave access is completed" "Not completed,Completed"
|
|
bitfld.long 0x04 28. " CONT_OVERFLOW ,Overflow during continuous mode" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x04 25. " DEVICE_INTR_2_ENB ,Device Interrupt-2 Enable Bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " DEVICE_INTR_1_ENB ,Device Interrupt-1 Enable Bit" "Disabled,Enabled"
|
|
rbitfld.long 0x04 23. " SLV_FIFO_FULL ,SLV FIFO full status" "Not full,Full"
|
|
textline " "
|
|
rbitfld.long 0x04 22. " SLV_FIFO_EMPTY ,SLV FIFO empty status" "Not empty,Empty"
|
|
rbitfld.long 0x04 21. " MST_FIFO_FULL ,MST FIFO full status" "Not full,Full"
|
|
rbitfld.long 0x04 20. " MST_FIFO_EMPTY ,MST FIFO empty status" "Not empty,Empty"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " DMA_DATA_CNT ,Number of Data to be transferred"
|
|
line.long 0x08 "NOR_ADDR_PTR_0,Starting address of the NOR access"
|
|
line.long 0x0C "AHB_ADDR_PTR_0,Starting address of the AHB access"
|
|
line.long 0x10 "TIMING0_0,SNOR Timing0 Register"
|
|
bitfld.long 0x10 28.--31. " PAGE_RDY_WIDTH ,Number of wait clock cycles from address to 1st data ready" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 20.--23. " PAGE_SEQ_WIDTH ,Page Sequential width" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 12.--15. " MUXED_WIDTH ,Number of cycles MUX address/data asserted on the bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " HOLD_WIDTH ,Number of cycles CE stays asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 4.--7. " ADV_WIDTH ,Number of cycles during which ADV stays asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " CE_WIDTH ,Number of cycles before CE is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "TIMING1_0,SNOR Timing1 Register"
|
|
bitfld.long 0x14 26.--31. " SNOR_TAP_DELAY ,Tap delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x14 24. " SNOR_CE ,Clock Override" "No override,Override"
|
|
hexmask.long.byte 0x14 16.--23. 1. " WE_WIDTH ,Write access time"
|
|
textline " "
|
|
hexmask.long.byte 0x14 8.--15. 1. " OE_WIDTH ,Read access time"
|
|
hexmask.long.byte 0x14 0.--7. 1. " WAIT_WIDTH ,Number of wait states before when READY is issued"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DMA_CFG_0,SNOR DMA Configuration Register"
|
|
bitfld.long 0x00 31. " DMA_GO ,Enable DMA" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " BSY ,DMA status" "Idle,Busy"
|
|
bitfld.long 0x00 29. " DIR ,Direction of DMA data transfer" "NOR2AHB,AHB2NOR"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IE_DMA_DONE ,Interrupt Enable on DMA transfer completion" "Disabled,Enabled"
|
|
eventfld.long 0x00 27. " IS_DMA_DONE ,Interrupt Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--26. " BURST_SIZE ,DMA burst size" ",,,,1 Word,4 Words,8 Words,"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CONTINUOUS ,Continuous DMA transfer" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " WORD_COUNT ,Number of words that need to be transferred"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TIMING2_0,Tap Delay programming for the Trimmer on the Input path"
|
|
bitfld.long 0x00 0.--5. " SNOR_IN_TAP_DELAY ,Tap delay for the trimmer on the input path" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "SD/MMC Controller"
|
|
tree "SDMMC-1"
|
|
base ad:0x700B0000
|
|
tree.open "Standard Registers"
|
|
width 27.
|
|
sif !cpuis("TEGRAX1")&&!cpuis("TEGRAX2")
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "PSR,Present State Register"
|
|
bitfld.long 0x00 25.--28. " DAT_7_4_LINE_LEVEL ,This status reflects the DAT[7:4] lines state for debug" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif !cpuis("TEGRAX2")
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " BOOT_ACK_ERR ,Boot ack status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " BOOT_ACK_TIMEOUT_ERR ,Boot Ack is not received" "Not occurred,Occurred"
|
|
line.long 0x04 "ISTAER,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor Ack_Timeout and Ack error status" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
line.long 0x08 "ISIGR,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor specification error" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
else
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "INTERRUPT_STATUS_0,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " BOOT_ACK_ERR ,Boot ack status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " BOOT_ACK_TIMEOUT_ERR ,Boot Ack is not received" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BUFFER_READ_READY ,Buffer read ready" "NO_INT,GEN_INT"
|
|
line.long 0x04 "INTERRUPT_STATUS_ENABLE_0,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor Ack_Timeout and Ack error status" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BUFFER_READ_READY ,Buffer read ready" "Disabled,Enabled"
|
|
line.long 0x08 "INTERRUPT_SIGNAL_ENABLE_0,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor specification error" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
textline " "
|
|
bitfld.long 0x08 5. " BUFFER_READ_READY ,Buffer read ready" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("TEGRAX1")
|
|
group.long 0x3C++0x0B
|
|
line.long 0x00 "AUTO_CMD12_ERR_STATUS_0,Auto cmd12 err status 0"
|
|
bitfld.long 0x00 16.--18. " UHS_MODE_SEL ,UHS Mode Select" "LEGACY,HIGH,SDR50,SDR104,DDR50,HS400,?..."
|
|
endif
|
|
sif !cpuis("TEGRAX2")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FER,Force Event Register"
|
|
bitfld.long 0x00 30.--31. " VENDOR_SPECIFIC_ERR_STATUS ,Vendor specific error status" "No effect,ACK_TIMEOUT_ERR,ACK_ERR,Both"
|
|
endif
|
|
tree.end
|
|
tree.open "Vendor-Specific Registers"
|
|
width 27.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "VENDOR_CLOCK_CNTRL_0,Vendor Clock Control Register"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 29. " DIFF_CLK_SEL ,Selects differential CLK and DQS" "0,1"
|
|
bitfld.long 0x00 24.--28. " TRIM_VAL ,Tap value for output data path trimmer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " TAP_VAL ,Tap value for input data path trimmer"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BASE_CLK_FREQ ,SD/MMC clock frequency"
|
|
textline " "
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 6. " LEGACY_CLKEN_OVERRIDE ,Override for sdmmc_legacy_g_clk clken" "Normal,Override"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " SDR50_TUNING_OVERRIDE ,Override the SDR50_TUNING capabilities bit" "Normal,Override"
|
|
textline " "
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 4. " UHS2_CAPABILITY_OVERRIDE ,Override the UHS-II capabilities bit" "Normal,Override"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " PADPIPE_CLKEN_OVERRIDE ,Override for padmacro and pipemacro clken" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SPI_MODE_CLKEN_OVERRIDE ,Override for CLKEN during SPI_MODE during sw_reset" "Normal,Override"
|
|
bitfld.long 0x00 1. " INPUT_IO_CLK ,Input I/O clock" "Feedback,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SDMMC_CLK ,Set when sdmmc_clk is supplied by the CAR module prior to sdmmc_clk switch OFF" "Disabled,Enabled"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
if (((d.l(ad:0x700B0000+0x104))&0x40000000)==0x40000000)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 31. " ENHANCED_STROBE_MODE ,Enables enhanced strobe mode in HS400/HS667 mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT ,Uses TMCLK data timeout counter for generating wr_crc_status data-timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " USE_NCRC_FOR_WR_CRC_STATUS_TIMEOUT_VAL ,Uses data timeout value as wr CRC/NCRC status timeout value" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " USE_TMCLK_FOR_DATA_TIMEOUT ,Uses TMCLK data timeout counter for generating legacy data timeout error" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,This register field is used to load wait_cycles counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,Busy should be sampled using clock instead DQS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 23. " ALLOW_CARD_CLK_STALLS_IN_WR ,Allows card clock stopping during transfer of data within a block in HIGH SPEED DDR/HS400 writes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EMMC_IOBRICK_CLK_DATA ,Used to drive AP_CLK and AN_CLK input of iobrick" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " QUALIFY_WITH_RD_DATA_VLD ,Async FIFOs in both cmd_in and dat_in paths in padmacro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,TUNING_SYS interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8.--11. " TUNING_ASYNC_FIFO_ADDNL_DELAY ,DATA/CMD IB path uses async FIFO which contributes additional delay to CMD/RESP and WDATA/CRC token round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,SD_BUS_POWER_ON_OFF interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,VOLT_SWITCH interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,TUNING_SYS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IO_TRIM_BYPASS ,Override bit for selecting between core trimmer and I/O trimmer in IB clock path" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 31. " ENHANCED_STROBE_MODE ,Enables enhanced strobe mode in HS400/HS667 mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT , Uses TMCLK data timeout counter for generating wr_crc_status data-timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " USE_TMCLK_FOR_DATA_TIMEOUT ,Uses TMCLK data timeout counter for generating legacy data timeout error" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,This register field is used to load wait_cycles counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,Busy should be sampled using clock instead DQS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 23. " ALLOW_CARD_CLK_STALLS_IN_WR ,allows card clock stopping during transfer of data within a block in HIGH SPEED DDR/HS400 writes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EMMC_IOBRICK_CLK_DATA ,Used to drive AP_CLK and AN_CLK input of iobrick" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " QUALIFY_WITH_RD_DATA_VLD ,Async FIFOs in both cmd_in and dat_in paths in padmacro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,TUNING_SYS interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8.--11. " TUNING_ASYNC_FIFO_ADDNL_DELAY ,DATA/CMD IB path uses async FIFO which contributes additional delay to CMD/RESP and WDATA/CRC token round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,SD_BUS_POWER_ON_OFF interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,VOLT_SWITCH interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,TUNING_SYS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IO_TRIM_BYPASS ,Override bit for selecting between core trimmer and I/O trimmer in IB clock path" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "VENDOR_ERR_INTR_STATUS_0,Legacy Interrupt Status Register"
|
|
bitfld.long 0x00 18. " SDMMC_LEGACY_CTLR_IDLE ,Indicates legacy SD interface controller is idle" "0,1"
|
|
bitfld.long 0x00 17. " READ_DATA_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " WRITE_CRC_STATUS_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
bitfld.long 0x00 15. " WRITE_BUSY_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RESP_BUSY_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
bitfld.long 0x00 13. " SPI_WRITE_BUSY_TIMEOUT ,SPI_WRITE_BUSY timeout" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SPI_RX_START_TOKEN_TIMEOUT ,SPI_RX_START_TOKEN timeout" "0,1"
|
|
bitfld.long 0x00 5.--8. " SPI_DAT_ERR_TOKEN ,Data Error Token while read from card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SPI_DAT_RESPONSE ,Data Response while write to card" ",,,,,DATA_ACCEPTED,,,,,,CRC_ERR,,WRITE_ERR,?..."
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER was changed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN was changed" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,CMD19 was issued while EXECUTE_TUNING was set" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10C++0x17
|
|
line.long 0x00 "VENDOR_CAP_OVERRIDES_0,Capabilities Override Bits"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
sif !cpuis("TEGRAX2")
|
|
bitfld.long 0x00 28. " CMD_QUEUING_MODE_EN ,Useful for eMMC5.x devices which support CMD queuing" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--13. " DQS_TRIM_VAL ,Tap value for incoming DQS path trimmer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DRV_LPBK_CLK_ON_CMD_LINE ,Loopback trimmed clock will be driven onto cmd line" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " VOLTAGE_3_3_V_SUPPORT_OVERRIDE ,Voltage support 3_3_V override" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " VOLTAGE_3_0_V_SUPPORT_OVERRIDE ,Voltage support 3_0_V override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VOLTAGE_1_8_V_SUPPORT_OVERRIDE ,Voltage support 1_8_V override" "Disabled,Enabled"
|
|
line.long 0x04 "VENDOR_BOOT_CNTRL_0,Vendor Boot Control Register"
|
|
bitfld.long 0x04 1. " BOOT_ACK ,Used to support Boot Option in MMC 4.3 version cards" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " BOOT ,Boot Option 1" "Disabled,Enabled"
|
|
line.long 0x08 "VENDOR_BOOT_ACK_TIMEOUT_0,Vendor Boot Acknowledgement Timeout Register"
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " VALUE ,Boot Acknowledgment timeout value"
|
|
line.long 0x0C "VENDOR_BOOT_DAT_TIMEOUT_0,Boot Data Timeout Register"
|
|
hexmask.long 0x0C 0.--24. 1. " VALUE ,Boot Data timeout value"
|
|
line.long 0x10 "VENDOR_DEBOUNCE_COUNT_0,Debounce Counter Value Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " VALUE ,The number of 32KHz clock cycles is programmed to meet the debounce period of the card slot"
|
|
line.long 0x14 "VENDOR_MISC_CNTRL_0,Miscellaneous Vendor Control Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " SDMMC_SPARE_1 ,Spare register bits with reset value of 1"
|
|
hexmask.long.word 0x14 1.--15. 1. " SDMMC_SPARE_0 ,Spare register bits with reset value of 0x40"
|
|
textline " "
|
|
bitfld.long 0x14 0. " ERASE_TIMEOUT_LIMIT ,Erase timeout value" "Finite,Infinite"
|
|
sif cpuis("TEGRAX2")
|
|
group.long 0x124++0x1F
|
|
line.long 0x00 "VENDOR_MISC_CNTRL1_0,Misc Vendor Control Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " OVERRIDE_FOR_1_8V ,Maximum override for 1.8V VDD1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OVERRIDE_FOR_3_0V ,Maximum override for 3.0V VDD1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OVERRIDE_FOR_3_3V ,Maximum override for 3.3V VDD1"
|
|
line.long 0x04 "VENDOR_MISC_CNTRL2_0,Misc Vendor Control Register 2"
|
|
bitfld.long 0x04 31. " VGPIO_MODE_EN ,VGPIO_MODE enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " SDMMC_CLK_OVR_ON ,Master clk en Override bit for all SLCGs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " SD_CARD_DETECT_STATUS_N ,SD card detect status n" "Detected,Not detected"
|
|
bitfld.long 0x04 28. " SD_CARD_WP_STATUS ,SD card wp status" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 27. " CMD_TFIFO_HOT_RESET ,CMD TFIFO hot reset" "No reset,Reset"
|
|
bitfld.long 0x04 26. " DAT_TFIFO_HOT_RESET ,DAT TFIFO hot reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ADMA3_CLKEN_OVERRIDE ,Override for sdmmc_adma3_g_clk clken" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x04 22. " ADMA3_DESC_PREFETCH_EN ,ADMA3 descriptors prefetch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " ADMA2_DESC_PREFETCH_EN ,ADMA2 descriptors prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--19. " DATA_TIMEOUT_VAL_MULTIPLIER ,Data timeout value multiplier" "No multiplier,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " DAT_TUNING_ASYNC_FIFO_ADDNL_DELAY ,Holds the additional delay in cycles which should be added to round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " ADDITIONAL_NCR_CYCLES ,Additional NCR wait time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " OVERRIDE_FOR_1_8V_VDD2 ,Maximum override for 1.8V VDD2"
|
|
textline " "
|
|
else
|
|
group.long 0x124++0x1F
|
|
line.long 0x00 "MAX_CURR_OVER_0,Maximum Current Override 0 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " OVERRIDE_FOR_1_8V ,Maximum override for 1.8V VDD1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OVERRIDE_FOR_3_0V ,Maximum override for 3.0V VDD1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OVERRIDE_FOR_3_3V ,Maximum override for 3.3V VDD1"
|
|
line.long 0x04 "MAX_CURR_OVER_HI_0,Maximum Current Override High 0 Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " OVERRIDE_FOR_1_8V_VDD2 ,Maximum override for 1.8V VDD2"
|
|
textline " "
|
|
endif
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "VENDOR_IO_TRIM_CNTRL_0,Vendor I/O Trimmer Control Register"
|
|
sif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 6.--7. " TRIM_SEL_ATEST ,Select analog test signals to send to comp pad" "No used,Input,Output before analog mux,Output after analog mux"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " TRIM_PWRSAVE ,Enables power saving mode by clock gating the unused taps in delay chain" "No,Yes"
|
|
bitfld.long 0x00 3.--4. " SEL_VREF_LEVEL ,Selects Vref voltage level" "VREF_875_MV,VREF_900_MV,VREF_925_MV,VREF_950_MV"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEL_VREG ,Select voltage supply for delay chain present in both Trimmer and DLLPROD value" "Regulated reference voltage,VAUXC"
|
|
bitfld.long 0x00 1. " SEL_VREF ,Select reference voltage for voltage regulator" "Bandgap Voltage Reference,Resistor divider voltage"
|
|
sif cpuis("TEGRAX2")
|
|
else
|
|
endif
|
|
group.long 0x1C0++0x07
|
|
line.long 0x00 "VENDOR_TUNING_CNTRL0_0,Vendor Tuning Control 0 Register"
|
|
bitfld.long 0x00 30. " RD_DATA_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on read data CRC error" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " WR_DATA_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on write CRC error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " CMD_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on cmd CRC error" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RETUNING_REQ_EN_ON_CRC_ERR_DETECTION ,Generates re-tuning request" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TUNING_ERR_EN_ON_CRC_ERR_DETECTION ,Generates tuning error" "Not generated,Generated"
|
|
hexmask.long.byte 0x00 18.--25. 1. " START_TAP_VAL ,Start tap value to be used by tuning"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TAP_VAL_UPDATED_BY_HW ,Software can choose to update the tap value by itself" "Not updated,Updated"
|
|
bitfld.long 0x00 13.--15. " NUM_TUNING_ITERATIONS ,The number of tuning iterations to be used by tuning circuit" "TRIES_40,TRIES_64,TRIES_128,TRIES_192,TRIES_256,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 6.--12. 1. " MUL_M ,Implements a multiplier"
|
|
bitfld.long 0x00 3.--5. " DIV_N ,Implements a divider" "1,2,4,8,16,32,64,128"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TUNING_WORD_SEL ,Selects desired word from 256-bit tuning status bitmap status_word" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "VENDOR_TUNING_CNTRL1_0,Vendor Tuning Control 1 Register"
|
|
bitfld.long 0x04 4.--6. " STEP_SIZE_SDR104_HS200 ,TAP_VAL is incremented by step_size for every tuning iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " STEP_SIZE_SDR50 ,TAP_VAL is incremented by step_size for every tuning iteration" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1C8++0x07
|
|
line.long 0x00 "VENDOR_TUNING_STATUS0_0,Vendor Tuning Status 0 Register"
|
|
line.long 0x04 "VENDOR_TUNING_STATUS1_0,Vendor Tuning Status 1 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PASS_WINDOW_END_BEFORE_FINE_TUNING , End tap value of best PASS window found by scan FSM"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PASS_WINDOW_START_BEFORE_FINE_TUNING ,Start tap value of best PASS window found by scan FSM"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " PASS_WINDOW_END_AFTER_FINE_TUNING ,End tap value of best PASS window after fine tuning"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PASS_WINDOW_START_AFTER_FINE_TUNING ,Start tap value of best PASS window after fine tuning"
|
|
textline " "
|
|
endif
|
|
width 28.
|
|
group.long 0x1D0++0x0F
|
|
line.long 0x00 "VENDOR_CLK_GATE_HYST_CNT_0,Vendor Clock Gating Hysteresis Counter Initial Value"
|
|
bitfld.long 0x00 0.--5. " CLK_COUNT ,CLK count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "VENDOR_PRESET_VAL0_0,Vendor Preset Value Register 0"
|
|
hexmask.long.word 0x04 20.--29. 1. " SDCLK_FREQ_SEL_HIGH_SPEED ,10-bit divider value to generate an SD clock in default speed mode (<50 MHz)"
|
|
hexmask.long.word 0x04 10.--19. 1. " SDCLK_FREQ_SEL_DEFAULT ,10-bit divider value to generate an SD clock in default speed mode (<25 MHz)"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--9. 1. " SDCLK_FREQ_SEL_INIT ,10-bit divider value to generate the desired SD clock frequency during initialization"
|
|
line.long 0x08 "VENDOR_PRESET_VAL1_0,Vendor Preset Value Register 1"
|
|
hexmask.long.word 0x08 20.--29. 1. " SDCLK_FREQ_SEL_SDR50 ,10-bit divider value to generate the SD clock in SDR50 mode"
|
|
hexmask.long.word 0x08 10.--19. 1. " SDCLK_FREQ_SEL_SDR25 ,10-bit divider value to generate the SD clock in SDR25 mode"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--9. 1. " SDCLK_FREQ_SEL_SDR12 ,10-bit divider value to generate the SD clock in SDR12 mode"
|
|
line.long 0x0C "VENDOR_PRESET_VAL2_0,Vendor Preset Value Register 2"
|
|
hexmask.long.word 0x0C 10.--19. 1. " SDCLK_FREQ_SEL_DDR50 ,10-bit divider value to generate the SD clock in DDR50 mode"
|
|
hexmask.long.word 0x0C 0.--9. 1. " SDCLK_FREQ_SEL_SDR104 ,10-bit divider value to generate the SD clock in SDR104 mode"
|
|
sif cpuis("TEGRAX2")
|
|
if (((d.l(ad:0x700B0000+0x1E4))&0x20000000)==0x20000000)
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_E_PBIAS_BUF ,Enables internally generated bias levels for driver PMOS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Select different bias levels for driver PMOS when E_PBIAS_BUF=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_E_PBIAS_BUF ,Enables internally generated bias levels for driver PMOS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
hexmask.long.byte 0x00 20.--26. 1. " COMP_PAD_DRVUP_OVR ,Used to drive DRVUP input of COMP pad"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--18. 1. " COMP_PAD_DRVDN_OVR ,Used to drive DRVDN input of COMP pad"
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Select different bias levels for driver PMOS when E_PBIAS_BUF=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
elif cpuis("TEGRAX1")
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_REG_ON ,Turns ON regulator in comp pad" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 10. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Used to control vref_sel input of COMP pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if (((d.l(ad:0x700B0000+0x1E4))&0x20000000)==0x20000000)
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 29.--30. " PU_PAD_DRV_TYPE ,Pu pad drv type" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " PD_PAD_DRV_TYPE ,Pd pad drv type" "0,1,2,3"
|
|
bitfld.long 0x00 11. " PU_PAD_E_TEST_OUT ,Pu pad E test out" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PD_PAD_E_TEST_OUT ,Pd pad E test out" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " PU_PAD_TEST_SEL ,pu pad test sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PD_PAD_TEST_SEL ,Pd pad test sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,sdmmc2tmc cfg Sdmemcomp vref sel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 29.--30. " PU_PAD_DRV_TYPE ,PU PAD DRV TYPE" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " PD_PAD_DRV_TYPE ,PD PAD DRV TYPE" "0,1,2,3"
|
|
hexmask.long.byte 0x00 20.--26. 1. " CFG_SDMEMCOMP_DRVUP ,SDMMC pads drive up/down control"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--18. 1. " CFG_SDMEMCOMP_DRVDN ,SDMMC pads drive up/down control"
|
|
bitfld.long 0x00 11. " PU_PAD_E_TEST_OUT ,PU PAD E TEST OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PD_PAD_E_TEST_OUT ,PD_PAD_E_TEST_OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " PU_PAD_TEST_SEL ,PU PAD TEST SEL" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PD_PAD_TEST_SEL ,PD PAD TEST SEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,SDMMC2TMC CFG SDMEMCOMP VREF SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long 0x1E4++0x07
|
|
line.long 0x00 "AUTO_CAL_CFG_0,SDMEMCOMP Pad Auto-Calibration Settings"
|
|
bitfld.long 0x00 31. " AUTO_CAL_START ,Calibration state machine" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " AUTO_CAL_OVERRIDE ,AUTOCAL override" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 29. " AUTO_CAL_ENABLE ,AUTOCAL enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " AUTO_CAL_SLW_OVERRIDE ,AUTOCAL slew rate override" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " AUTO_CAL_STEP ,Calibration step interval" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PD_OFFSET ,2's complement offset for pull-down value"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PU_OFFSET ,2's complement offset for pull-up value"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
group.long 0x1E8++0x07
|
|
line.long 0x00 "AUTO_CAL_INTERVAL_0,SDMEMCOMP Pad Calibration Interval"
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "AUTO_CAL_STATUS_0,SDMEMCOMP Pad Calibration Status"
|
|
bitfld.long 0x00 31. " AUTO_CAL_ACTIVE ,Auto cal active" "Inactive,Active"
|
|
hexmask.long.byte 0x00 24.--30. 1. " AUTO_CAL_PULLDOWN_ADJ ,Pulldown code sent to pads"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " AUTO_CAL_PULLUP_ADJ ,Pullup code sent to pads"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PULLDOWN ,Pulldown code generated by auto-calibration"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PULLUP ,Pullup code generated by auto-calibration"
|
|
else
|
|
group.long 0x1E8++0x07
|
|
line.long 0x00 "AUTO_CAL_INTERVAL_0,SDMEMCOMP Pad Calibration Interval"
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "AUTO_CAL_STATUS_0,SDMEMCOMP Pad Calibration Status"
|
|
bitfld.long 0x00 31. " AUTO_CAL_ACTIVE ,Auto cal active" "Inactive,Active"
|
|
hexmask.long.byte 0x00 24.--30. 1. " AUTO_CAL_PULLDOWN_ADJ ,Pulldown code sent to pads"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " AUTO_CAL_PULLUP_ADJ ,Pullup code sent to pads"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PULLDOWN ,Pulldown code generated by auto-calibration"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PULLUP ,Pullup code generated by auto-calibration"
|
|
endif
|
|
sif cpuis("TEGRAX1")
|
|
group.long 0x1F0++0x07
|
|
line.long 0x00 "IO_SPARE_0,Memory Client Interface FIFO Control"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPARE_OUT ,PROD value"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPARE_IN ,PROD value"
|
|
endif
|
|
sif cpuis("TEGRAX2")
|
|
textline " "
|
|
group.long 0x1FC++0x0B
|
|
line.long 0x00 "CIF2AXI_CTRL_0,SD/MMC CIF2AXI Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MC_WRITE_REQ_STREAM_ID ,MC write transaction stream ID"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MC_READ_REQ_STREAM_ID ,MC read transaction stream ID"
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "TZ_DMA_CTRL_0,SD/MMC DMA Requests Security Attribute Control Register"
|
|
bitfld.long 0x00 1. " MC_WRITE_REQ_TZ_ACCESS_EN ,MC_WRITE_REQ_TZ_ACCESS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MC_READ_REQ_TZ_ACCESS_EN ,MC_READ_REQ_TZ_ACCESS enable" "Disabled,Enabled"
|
|
line.long 0x04 "VENDOR_MISC_CNTRL3_0,Misc Vendor Control Register 3"
|
|
bitfld.long 0x04 30. " STOP_TRIM_IN_CLK_DURING_TUNING ,Stops rx clk trimmer and rx FIFOs input clock during tuning" "Not stopped,Stopped"
|
|
bitfld.long 0x04 24.--29. " TUNING_TRIMMER_RECOVERY_TIME ,TUNING TRIMMER RECOVERY TIME" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " E_DIFF_DQ , Diff/Vref rx selection for DAT[7:0]"
|
|
bitfld.long 0x04 4. " E_DIFF_CMD ,Diff/Vref rx selection for CMD" "Stopped,Not stopped"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DAT_OE_POSTAMBLE_EN ,DAT pads output driver one cycle after disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " DAT_OE_PREAMBLE_EN ,DAT pads output driver one cycle before enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CMD_OE_POSTAMBLE_EN ,CMD pad output driver one cycle after disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CMD_OE_PREAMBLE_EN ,CMD pad output driver one cycle before enable" "Disabled,Enabled"
|
|
group.long 0x20C++0x07
|
|
line.long 0x00 "VENDOR_MISC_CNTRL4_0,Misc Vendor Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " SDMMC_SPARE3 ,Spare register bits with reset value of 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDMMC_SPARE2 ,Spare register bits with reset value of 0"
|
|
else
|
|
group.long 0x1F4++0x07
|
|
line.long 0x00 "SDMMC_MCCIF_FIFOCTRL_0,Memory Client Interface FIFO Control"
|
|
bitfld.long 0x00 20. " SDMMC_RCLK_OVR_MODE ,SDMMC RCLK OVR MODE" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SDMMC_WCLK_OVR_MODE ,SDMMC WCLK OVR MODE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SDMMC_CCLK_OVERRIDE ,SDMMC CCLK OVERRIDE" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SDMMC_RCLK_OVERRIDE ,SDMMC RCLK OVERRIDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SDMMC_WCLK_OVERRIDE ,SDMMC WCLK OVERRIDE" "Disabled,Enabled"
|
|
line.long 0x04 "TIMEOUT_WCOAL_SDMMC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SDMMCW_WCOAL_TMVAL ,SDMMCW WCOAL TMVAL"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "SDMMC-1B"
|
|
base ad:0x700B1000
|
|
tree.open "Standard Registers"
|
|
width 27.
|
|
sif !cpuis("TEGRAX1")&&!cpuis("TEGRAX2")
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "PSR,Present State Register"
|
|
bitfld.long 0x00 25.--28. " DAT_7_4_LINE_LEVEL ,This status reflects the DAT[7:4] lines state for debug" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif !cpuis("TEGRAX2")
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " BOOT_ACK_ERR ,Boot ack status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " BOOT_ACK_TIMEOUT_ERR ,Boot Ack is not received" "Not occurred,Occurred"
|
|
line.long 0x04 "ISTAER,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor Ack_Timeout and Ack error status" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
line.long 0x08 "ISIGR,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor specification error" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
else
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "INTERRUPT_STATUS_0,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " BOOT_ACK_ERR ,Boot ack status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " BOOT_ACK_TIMEOUT_ERR ,Boot Ack is not received" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BUFFER_READ_READY ,Buffer read ready" "NO_INT,GEN_INT"
|
|
line.long 0x04 "INTERRUPT_STATUS_ENABLE_0,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor Ack_Timeout and Ack error status" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BUFFER_READ_READY ,Buffer read ready" "Disabled,Enabled"
|
|
line.long 0x08 "INTERRUPT_SIGNAL_ENABLE_0,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor specification error" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
textline " "
|
|
bitfld.long 0x08 5. " BUFFER_READ_READY ,Buffer read ready" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("TEGRAX1")
|
|
group.long 0x3C++0x0B
|
|
line.long 0x00 "AUTO_CMD12_ERR_STATUS_0,Auto cmd12 err status 0"
|
|
bitfld.long 0x00 16.--18. " UHS_MODE_SEL ,UHS Mode Select" "LEGACY,HIGH,SDR50,SDR104,DDR50,HS400,?..."
|
|
endif
|
|
sif !cpuis("TEGRAX2")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FER,Force Event Register"
|
|
bitfld.long 0x00 30.--31. " VENDOR_SPECIFIC_ERR_STATUS ,Vendor specific error status" "No effect,ACK_TIMEOUT_ERR,ACK_ERR,Both"
|
|
endif
|
|
tree.end
|
|
tree.open "Vendor-Specific Registers"
|
|
width 27.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "VENDOR_CLOCK_CNTRL_0,Vendor Clock Control Register"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 29. " DIFF_CLK_SEL ,Selects differential CLK and DQS" "0,1"
|
|
bitfld.long 0x00 24.--28. " TRIM_VAL ,Tap value for output data path trimmer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " TAP_VAL ,Tap value for input data path trimmer"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BASE_CLK_FREQ ,SD/MMC clock frequency"
|
|
textline " "
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 6. " LEGACY_CLKEN_OVERRIDE ,Override for sdmmc_legacy_g_clk clken" "Normal,Override"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " SDR50_TUNING_OVERRIDE ,Override the SDR50_TUNING capabilities bit" "Normal,Override"
|
|
textline " "
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 4. " UHS2_CAPABILITY_OVERRIDE ,Override the UHS-II capabilities bit" "Normal,Override"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " PADPIPE_CLKEN_OVERRIDE ,Override for padmacro and pipemacro clken" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SPI_MODE_CLKEN_OVERRIDE ,Override for CLKEN during SPI_MODE during sw_reset" "Normal,Override"
|
|
bitfld.long 0x00 1. " INPUT_IO_CLK ,Input I/O clock" "Feedback,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SDMMC_CLK ,Set when sdmmc_clk is supplied by the CAR module prior to sdmmc_clk switch OFF" "Disabled,Enabled"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
if (((d.l(ad:0x700B1000+0x104))&0x40000000)==0x40000000)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 31. " ENHANCED_STROBE_MODE ,Enables enhanced strobe mode in HS400/HS667 mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT ,Uses TMCLK data timeout counter for generating wr_crc_status data-timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " USE_NCRC_FOR_WR_CRC_STATUS_TIMEOUT_VAL ,Uses data timeout value as wr CRC/NCRC status timeout value" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " USE_TMCLK_FOR_DATA_TIMEOUT ,Uses TMCLK data timeout counter for generating legacy data timeout error" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,This register field is used to load wait_cycles counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,Busy should be sampled using clock instead DQS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 23. " ALLOW_CARD_CLK_STALLS_IN_WR ,Allows card clock stopping during transfer of data within a block in HIGH SPEED DDR/HS400 writes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EMMC_IOBRICK_CLK_DATA ,Used to drive AP_CLK and AN_CLK input of iobrick" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " QUALIFY_WITH_RD_DATA_VLD ,Async FIFOs in both cmd_in and dat_in paths in padmacro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,TUNING_SYS interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8.--11. " TUNING_ASYNC_FIFO_ADDNL_DELAY ,DATA/CMD IB path uses async FIFO which contributes additional delay to CMD/RESP and WDATA/CRC token round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,SD_BUS_POWER_ON_OFF interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,VOLT_SWITCH interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,TUNING_SYS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IO_TRIM_BYPASS ,Override bit for selecting between core trimmer and I/O trimmer in IB clock path" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 31. " ENHANCED_STROBE_MODE ,Enables enhanced strobe mode in HS400/HS667 mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT , Uses TMCLK data timeout counter for generating wr_crc_status data-timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " USE_TMCLK_FOR_DATA_TIMEOUT ,Uses TMCLK data timeout counter for generating legacy data timeout error" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,This register field is used to load wait_cycles counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,Busy should be sampled using clock instead DQS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 23. " ALLOW_CARD_CLK_STALLS_IN_WR ,allows card clock stopping during transfer of data within a block in HIGH SPEED DDR/HS400 writes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EMMC_IOBRICK_CLK_DATA ,Used to drive AP_CLK and AN_CLK input of iobrick" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " QUALIFY_WITH_RD_DATA_VLD ,Async FIFOs in both cmd_in and dat_in paths in padmacro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,TUNING_SYS interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8.--11. " TUNING_ASYNC_FIFO_ADDNL_DELAY ,DATA/CMD IB path uses async FIFO which contributes additional delay to CMD/RESP and WDATA/CRC token round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,SD_BUS_POWER_ON_OFF interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,VOLT_SWITCH interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,TUNING_SYS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IO_TRIM_BYPASS ,Override bit for selecting between core trimmer and I/O trimmer in IB clock path" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "VENDOR_ERR_INTR_STATUS_0,Legacy Interrupt Status Register"
|
|
bitfld.long 0x00 18. " SDMMC_LEGACY_CTLR_IDLE ,Indicates legacy SD interface controller is idle" "0,1"
|
|
bitfld.long 0x00 17. " READ_DATA_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " WRITE_CRC_STATUS_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
bitfld.long 0x00 15. " WRITE_BUSY_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RESP_BUSY_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
bitfld.long 0x00 13. " SPI_WRITE_BUSY_TIMEOUT ,SPI_WRITE_BUSY timeout" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SPI_RX_START_TOKEN_TIMEOUT ,SPI_RX_START_TOKEN timeout" "0,1"
|
|
bitfld.long 0x00 5.--8. " SPI_DAT_ERR_TOKEN ,Data Error Token while read from card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SPI_DAT_RESPONSE ,Data Response while write to card" ",,,,,DATA_ACCEPTED,,,,,,CRC_ERR,,WRITE_ERR,?..."
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER was changed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN was changed" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,CMD19 was issued while EXECUTE_TUNING was set" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10C++0x17
|
|
line.long 0x00 "VENDOR_CAP_OVERRIDES_0,Capabilities Override Bits"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
sif !cpuis("TEGRAX2")
|
|
bitfld.long 0x00 28. " CMD_QUEUING_MODE_EN ,Useful for eMMC5.x devices which support CMD queuing" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--13. " DQS_TRIM_VAL ,Tap value for incoming DQS path trimmer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DRV_LPBK_CLK_ON_CMD_LINE ,Loopback trimmed clock will be driven onto cmd line" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " VOLTAGE_3_3_V_SUPPORT_OVERRIDE ,Voltage support 3_3_V override" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " VOLTAGE_3_0_V_SUPPORT_OVERRIDE ,Voltage support 3_0_V override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VOLTAGE_1_8_V_SUPPORT_OVERRIDE ,Voltage support 1_8_V override" "Disabled,Enabled"
|
|
line.long 0x04 "VENDOR_BOOT_CNTRL_0,Vendor Boot Control Register"
|
|
bitfld.long 0x04 1. " BOOT_ACK ,Used to support Boot Option in MMC 4.3 version cards" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " BOOT ,Boot Option 1" "Disabled,Enabled"
|
|
line.long 0x08 "VENDOR_BOOT_ACK_TIMEOUT_0,Vendor Boot Acknowledgement Timeout Register"
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " VALUE ,Boot Acknowledgment timeout value"
|
|
line.long 0x0C "VENDOR_BOOT_DAT_TIMEOUT_0,Boot Data Timeout Register"
|
|
hexmask.long 0x0C 0.--24. 1. " VALUE ,Boot Data timeout value"
|
|
line.long 0x10 "VENDOR_DEBOUNCE_COUNT_0,Debounce Counter Value Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " VALUE ,The number of 32KHz clock cycles is programmed to meet the debounce period of the card slot"
|
|
line.long 0x14 "VENDOR_MISC_CNTRL_0,Miscellaneous Vendor Control Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " SDMMC_SPARE_1 ,Spare register bits with reset value of 1"
|
|
hexmask.long.word 0x14 1.--15. 1. " SDMMC_SPARE_0 ,Spare register bits with reset value of 0x40"
|
|
textline " "
|
|
bitfld.long 0x14 0. " ERASE_TIMEOUT_LIMIT ,Erase timeout value" "Finite,Infinite"
|
|
sif cpuis("TEGRAX2")
|
|
group.long 0x124++0x1F
|
|
line.long 0x00 "VENDOR_MISC_CNTRL1_0,Misc Vendor Control Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " OVERRIDE_FOR_1_8V ,Maximum override for 1.8V VDD1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OVERRIDE_FOR_3_0V ,Maximum override for 3.0V VDD1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OVERRIDE_FOR_3_3V ,Maximum override for 3.3V VDD1"
|
|
line.long 0x04 "VENDOR_MISC_CNTRL2_0,Misc Vendor Control Register 2"
|
|
bitfld.long 0x04 31. " VGPIO_MODE_EN ,VGPIO_MODE enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " SDMMC_CLK_OVR_ON ,Master clk en Override bit for all SLCGs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " SD_CARD_DETECT_STATUS_N ,SD card detect status n" "Detected,Not detected"
|
|
bitfld.long 0x04 28. " SD_CARD_WP_STATUS ,SD card wp status" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 27. " CMD_TFIFO_HOT_RESET ,CMD TFIFO hot reset" "No reset,Reset"
|
|
bitfld.long 0x04 26. " DAT_TFIFO_HOT_RESET ,DAT TFIFO hot reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ADMA3_CLKEN_OVERRIDE ,Override for sdmmc_adma3_g_clk clken" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x04 22. " ADMA3_DESC_PREFETCH_EN ,ADMA3 descriptors prefetch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " ADMA2_DESC_PREFETCH_EN ,ADMA2 descriptors prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--19. " DATA_TIMEOUT_VAL_MULTIPLIER ,Data timeout value multiplier" "No multiplier,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " DAT_TUNING_ASYNC_FIFO_ADDNL_DELAY ,Holds the additional delay in cycles which should be added to round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " ADDITIONAL_NCR_CYCLES ,Additional NCR wait time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " OVERRIDE_FOR_1_8V_VDD2 ,Maximum override for 1.8V VDD2"
|
|
textline " "
|
|
else
|
|
group.long 0x124++0x1F
|
|
line.long 0x00 "MAX_CURR_OVER_0,Maximum Current Override 0 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " OVERRIDE_FOR_1_8V ,Maximum override for 1.8V VDD1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OVERRIDE_FOR_3_0V ,Maximum override for 3.0V VDD1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OVERRIDE_FOR_3_3V ,Maximum override for 3.3V VDD1"
|
|
line.long 0x04 "MAX_CURR_OVER_HI_0,Maximum Current Override High 0 Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " OVERRIDE_FOR_1_8V_VDD2 ,Maximum override for 1.8V VDD2"
|
|
textline " "
|
|
endif
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "VENDOR_IO_TRIM_CNTRL_0,Vendor I/O Trimmer Control Register"
|
|
sif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 6.--7. " TRIM_SEL_ATEST ,Select analog test signals to send to comp pad" "No used,Input,Output before analog mux,Output after analog mux"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " TRIM_PWRSAVE ,Enables power saving mode by clock gating the unused taps in delay chain" "No,Yes"
|
|
bitfld.long 0x00 3.--4. " SEL_VREF_LEVEL ,Selects Vref voltage level" "VREF_875_MV,VREF_900_MV,VREF_925_MV,VREF_950_MV"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEL_VREG ,Select voltage supply for delay chain present in both Trimmer and DLLPROD value" "Regulated reference voltage,VAUXC"
|
|
bitfld.long 0x00 1. " SEL_VREF ,Select reference voltage for voltage regulator" "Bandgap Voltage Reference,Resistor divider voltage"
|
|
sif cpuis("TEGRAX2")
|
|
else
|
|
endif
|
|
group.long 0x1C0++0x07
|
|
line.long 0x00 "VENDOR_TUNING_CNTRL0_0,Vendor Tuning Control 0 Register"
|
|
bitfld.long 0x00 30. " RD_DATA_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on read data CRC error" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " WR_DATA_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on write CRC error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " CMD_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on cmd CRC error" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RETUNING_REQ_EN_ON_CRC_ERR_DETECTION ,Generates re-tuning request" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TUNING_ERR_EN_ON_CRC_ERR_DETECTION ,Generates tuning error" "Not generated,Generated"
|
|
hexmask.long.byte 0x00 18.--25. 1. " START_TAP_VAL ,Start tap value to be used by tuning"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TAP_VAL_UPDATED_BY_HW ,Software can choose to update the tap value by itself" "Not updated,Updated"
|
|
bitfld.long 0x00 13.--15. " NUM_TUNING_ITERATIONS ,The number of tuning iterations to be used by tuning circuit" "TRIES_40,TRIES_64,TRIES_128,TRIES_192,TRIES_256,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 6.--12. 1. " MUL_M ,Implements a multiplier"
|
|
bitfld.long 0x00 3.--5. " DIV_N ,Implements a divider" "1,2,4,8,16,32,64,128"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TUNING_WORD_SEL ,Selects desired word from 256-bit tuning status bitmap status_word" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "VENDOR_TUNING_CNTRL1_0,Vendor Tuning Control 1 Register"
|
|
bitfld.long 0x04 4.--6. " STEP_SIZE_SDR104_HS200 ,TAP_VAL is incremented by step_size for every tuning iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " STEP_SIZE_SDR50 ,TAP_VAL is incremented by step_size for every tuning iteration" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1C8++0x07
|
|
line.long 0x00 "VENDOR_TUNING_STATUS0_0,Vendor Tuning Status 0 Register"
|
|
line.long 0x04 "VENDOR_TUNING_STATUS1_0,Vendor Tuning Status 1 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PASS_WINDOW_END_BEFORE_FINE_TUNING , End tap value of best PASS window found by scan FSM"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PASS_WINDOW_START_BEFORE_FINE_TUNING ,Start tap value of best PASS window found by scan FSM"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " PASS_WINDOW_END_AFTER_FINE_TUNING ,End tap value of best PASS window after fine tuning"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PASS_WINDOW_START_AFTER_FINE_TUNING ,Start tap value of best PASS window after fine tuning"
|
|
textline " "
|
|
endif
|
|
width 28.
|
|
group.long 0x1D0++0x0F
|
|
line.long 0x00 "VENDOR_CLK_GATE_HYST_CNT_0,Vendor Clock Gating Hysteresis Counter Initial Value"
|
|
bitfld.long 0x00 0.--5. " CLK_COUNT ,CLK count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "VENDOR_PRESET_VAL0_0,Vendor Preset Value Register 0"
|
|
hexmask.long.word 0x04 20.--29. 1. " SDCLK_FREQ_SEL_HIGH_SPEED ,10-bit divider value to generate an SD clock in default speed mode (<50 MHz)"
|
|
hexmask.long.word 0x04 10.--19. 1. " SDCLK_FREQ_SEL_DEFAULT ,10-bit divider value to generate an SD clock in default speed mode (<25 MHz)"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--9. 1. " SDCLK_FREQ_SEL_INIT ,10-bit divider value to generate the desired SD clock frequency during initialization"
|
|
line.long 0x08 "VENDOR_PRESET_VAL1_0,Vendor Preset Value Register 1"
|
|
hexmask.long.word 0x08 20.--29. 1. " SDCLK_FREQ_SEL_SDR50 ,10-bit divider value to generate the SD clock in SDR50 mode"
|
|
hexmask.long.word 0x08 10.--19. 1. " SDCLK_FREQ_SEL_SDR25 ,10-bit divider value to generate the SD clock in SDR25 mode"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--9. 1. " SDCLK_FREQ_SEL_SDR12 ,10-bit divider value to generate the SD clock in SDR12 mode"
|
|
line.long 0x0C "VENDOR_PRESET_VAL2_0,Vendor Preset Value Register 2"
|
|
hexmask.long.word 0x0C 10.--19. 1. " SDCLK_FREQ_SEL_DDR50 ,10-bit divider value to generate the SD clock in DDR50 mode"
|
|
hexmask.long.word 0x0C 0.--9. 1. " SDCLK_FREQ_SEL_SDR104 ,10-bit divider value to generate the SD clock in SDR104 mode"
|
|
sif cpuis("TEGRAX2")
|
|
if (((d.l(ad:0x700B1000+0x1E4))&0x20000000)==0x20000000)
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_E_PBIAS_BUF ,Enables internally generated bias levels for driver PMOS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Select different bias levels for driver PMOS when E_PBIAS_BUF=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_E_PBIAS_BUF ,Enables internally generated bias levels for driver PMOS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
hexmask.long.byte 0x00 20.--26. 1. " COMP_PAD_DRVUP_OVR ,Used to drive DRVUP input of COMP pad"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--18. 1. " COMP_PAD_DRVDN_OVR ,Used to drive DRVDN input of COMP pad"
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Select different bias levels for driver PMOS when E_PBIAS_BUF=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
elif cpuis("TEGRAX1")
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_REG_ON ,Turns ON regulator in comp pad" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 10. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Used to control vref_sel input of COMP pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if (((d.l(ad:0x700B1000+0x1E4))&0x20000000)==0x20000000)
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 29.--30. " PU_PAD_DRV_TYPE ,Pu pad drv type" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " PD_PAD_DRV_TYPE ,Pd pad drv type" "0,1,2,3"
|
|
bitfld.long 0x00 11. " PU_PAD_E_TEST_OUT ,Pu pad E test out" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PD_PAD_E_TEST_OUT ,Pd pad E test out" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " PU_PAD_TEST_SEL ,pu pad test sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PD_PAD_TEST_SEL ,Pd pad test sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,sdmmc2tmc cfg Sdmemcomp vref sel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 29.--30. " PU_PAD_DRV_TYPE ,PU PAD DRV TYPE" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " PD_PAD_DRV_TYPE ,PD PAD DRV TYPE" "0,1,2,3"
|
|
hexmask.long.byte 0x00 20.--26. 1. " CFG_SDMEMCOMP_DRVUP ,SDMMC pads drive up/down control"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--18. 1. " CFG_SDMEMCOMP_DRVDN ,SDMMC pads drive up/down control"
|
|
bitfld.long 0x00 11. " PU_PAD_E_TEST_OUT ,PU PAD E TEST OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PD_PAD_E_TEST_OUT ,PD_PAD_E_TEST_OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " PU_PAD_TEST_SEL ,PU PAD TEST SEL" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PD_PAD_TEST_SEL ,PD PAD TEST SEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,SDMMC2TMC CFG SDMEMCOMP VREF SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long 0x1E4++0x07
|
|
line.long 0x00 "AUTO_CAL_CFG_0,SDMEMCOMP Pad Auto-Calibration Settings"
|
|
bitfld.long 0x00 31. " AUTO_CAL_START ,Calibration state machine" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " AUTO_CAL_OVERRIDE ,AUTOCAL override" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 29. " AUTO_CAL_ENABLE ,AUTOCAL enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " AUTO_CAL_SLW_OVERRIDE ,AUTOCAL slew rate override" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " AUTO_CAL_STEP ,Calibration step interval" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PD_OFFSET ,2's complement offset for pull-down value"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PU_OFFSET ,2's complement offset for pull-up value"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
group.long 0x1E8++0x07
|
|
line.long 0x00 "AUTO_CAL_INTERVAL_0,SDMEMCOMP Pad Calibration Interval"
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "AUTO_CAL_STATUS_0,SDMEMCOMP Pad Calibration Status"
|
|
bitfld.long 0x00 31. " AUTO_CAL_ACTIVE ,Auto cal active" "Inactive,Active"
|
|
hexmask.long.byte 0x00 24.--30. 1. " AUTO_CAL_PULLDOWN_ADJ ,Pulldown code sent to pads"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " AUTO_CAL_PULLUP_ADJ ,Pullup code sent to pads"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PULLDOWN ,Pulldown code generated by auto-calibration"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PULLUP ,Pullup code generated by auto-calibration"
|
|
else
|
|
group.long 0x1E8++0x07
|
|
line.long 0x00 "AUTO_CAL_INTERVAL_0,SDMEMCOMP Pad Calibration Interval"
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "AUTO_CAL_STATUS_0,SDMEMCOMP Pad Calibration Status"
|
|
bitfld.long 0x00 31. " AUTO_CAL_ACTIVE ,Auto cal active" "Inactive,Active"
|
|
hexmask.long.byte 0x00 24.--30. 1. " AUTO_CAL_PULLDOWN_ADJ ,Pulldown code sent to pads"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " AUTO_CAL_PULLUP_ADJ ,Pullup code sent to pads"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PULLDOWN ,Pulldown code generated by auto-calibration"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PULLUP ,Pullup code generated by auto-calibration"
|
|
endif
|
|
sif cpuis("TEGRAX1")
|
|
group.long 0x1F0++0x07
|
|
line.long 0x00 "IO_SPARE_0,Memory Client Interface FIFO Control"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPARE_OUT ,PROD value"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPARE_IN ,PROD value"
|
|
endif
|
|
sif cpuis("TEGRAX2")
|
|
textline " "
|
|
group.long 0x1FC++0x0B
|
|
line.long 0x00 "CIF2AXI_CTRL_0,SD/MMC CIF2AXI Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MC_WRITE_REQ_STREAM_ID ,MC write transaction stream ID"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MC_READ_REQ_STREAM_ID ,MC read transaction stream ID"
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "TZ_DMA_CTRL_0,SD/MMC DMA Requests Security Attribute Control Register"
|
|
bitfld.long 0x00 1. " MC_WRITE_REQ_TZ_ACCESS_EN ,MC_WRITE_REQ_TZ_ACCESS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MC_READ_REQ_TZ_ACCESS_EN ,MC_READ_REQ_TZ_ACCESS enable" "Disabled,Enabled"
|
|
line.long 0x04 "VENDOR_MISC_CNTRL3_0,Misc Vendor Control Register 3"
|
|
bitfld.long 0x04 30. " STOP_TRIM_IN_CLK_DURING_TUNING ,Stops rx clk trimmer and rx FIFOs input clock during tuning" "Not stopped,Stopped"
|
|
bitfld.long 0x04 24.--29. " TUNING_TRIMMER_RECOVERY_TIME ,TUNING TRIMMER RECOVERY TIME" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " E_DIFF_DQ , Diff/Vref rx selection for DAT[7:0]"
|
|
bitfld.long 0x04 4. " E_DIFF_CMD ,Diff/Vref rx selection for CMD" "Stopped,Not stopped"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DAT_OE_POSTAMBLE_EN ,DAT pads output driver one cycle after disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " DAT_OE_PREAMBLE_EN ,DAT pads output driver one cycle before enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CMD_OE_POSTAMBLE_EN ,CMD pad output driver one cycle after disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CMD_OE_PREAMBLE_EN ,CMD pad output driver one cycle before enable" "Disabled,Enabled"
|
|
group.long 0x20C++0x07
|
|
line.long 0x00 "VENDOR_MISC_CNTRL4_0,Misc Vendor Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " SDMMC_SPARE3 ,Spare register bits with reset value of 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDMMC_SPARE2 ,Spare register bits with reset value of 0"
|
|
else
|
|
group.long 0x1F4++0x07
|
|
line.long 0x00 "SDMMC_MCCIF_FIFOCTRL_0,Memory Client Interface FIFO Control"
|
|
bitfld.long 0x00 20. " SDMMC_RCLK_OVR_MODE ,SDMMC RCLK OVR MODE" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SDMMC_WCLK_OVR_MODE ,SDMMC WCLK OVR MODE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SDMMC_CCLK_OVERRIDE ,SDMMC CCLK OVERRIDE" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SDMMC_RCLK_OVERRIDE ,SDMMC RCLK OVERRIDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SDMMC_WCLK_OVERRIDE ,SDMMC WCLK OVERRIDE" "Disabled,Enabled"
|
|
line.long 0x04 "TIMEOUT_WCOAL_SDMMC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SDMMCW_WCOAL_TMVAL ,SDMMCW WCOAL TMVAL"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "SDMMC-2"
|
|
base ad:0x700B0200
|
|
tree.open "Standard Registers"
|
|
width 27.
|
|
sif !cpuis("TEGRAX1")&&!cpuis("TEGRAX2")
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "PSR,Present State Register"
|
|
bitfld.long 0x00 25.--28. " DAT_7_4_LINE_LEVEL ,This status reflects the DAT[7:4] lines state for debug" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif !cpuis("TEGRAX2")
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " BOOT_ACK_ERR ,Boot ack status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " BOOT_ACK_TIMEOUT_ERR ,Boot Ack is not received" "Not occurred,Occurred"
|
|
line.long 0x04 "ISTAER,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor Ack_Timeout and Ack error status" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
line.long 0x08 "ISIGR,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor specification error" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
else
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "INTERRUPT_STATUS_0,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " BOOT_ACK_ERR ,Boot ack status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " BOOT_ACK_TIMEOUT_ERR ,Boot Ack is not received" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BUFFER_READ_READY ,Buffer read ready" "NO_INT,GEN_INT"
|
|
line.long 0x04 "INTERRUPT_STATUS_ENABLE_0,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor Ack_Timeout and Ack error status" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BUFFER_READ_READY ,Buffer read ready" "Disabled,Enabled"
|
|
line.long 0x08 "INTERRUPT_SIGNAL_ENABLE_0,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor specification error" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
textline " "
|
|
bitfld.long 0x08 5. " BUFFER_READ_READY ,Buffer read ready" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("TEGRAX1")
|
|
group.long 0x3C++0x0B
|
|
line.long 0x00 "AUTO_CMD12_ERR_STATUS_0,Auto cmd12 err status 0"
|
|
bitfld.long 0x00 16.--18. " UHS_MODE_SEL ,UHS Mode Select" "LEGACY,HIGH,SDR50,SDR104,DDR50,HS400,?..."
|
|
endif
|
|
sif !cpuis("TEGRAX2")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FER,Force Event Register"
|
|
bitfld.long 0x00 30.--31. " VENDOR_SPECIFIC_ERR_STATUS ,Vendor specific error status" "No effect,ACK_TIMEOUT_ERR,ACK_ERR,Both"
|
|
endif
|
|
tree.end
|
|
tree.open "Vendor-Specific Registers"
|
|
width 27.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "VENDOR_CLOCK_CNTRL_0,Vendor Clock Control Register"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 29. " DIFF_CLK_SEL ,Selects differential CLK and DQS" "0,1"
|
|
bitfld.long 0x00 24.--28. " TRIM_VAL ,Tap value for output data path trimmer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " TAP_VAL ,Tap value for input data path trimmer"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BASE_CLK_FREQ ,SD/MMC clock frequency"
|
|
textline " "
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 6. " LEGACY_CLKEN_OVERRIDE ,Override for sdmmc_legacy_g_clk clken" "Normal,Override"
|
|
textline " "
|
|
endif
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 4. " UHS2_CAPABILITY_OVERRIDE ,Override the UHS-II capabilities bit" "Normal,Override"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " PADPIPE_CLKEN_OVERRIDE ,Override for padmacro and pipemacro clken" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SPI_MODE_CLKEN_OVERRIDE ,Override for CLKEN during SPI_MODE during sw_reset" "Normal,Override"
|
|
bitfld.long 0x00 1. " INPUT_IO_CLK ,Input I/O clock" "Feedback,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SDMMC_CLK ,Set when sdmmc_clk is supplied by the CAR module prior to sdmmc_clk switch OFF" "Disabled,Enabled"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
if (((d.l(ad:0x700B0200+0x104))&0x40000000)==0x40000000)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 31. " ENHANCED_STROBE_MODE ,Enables enhanced strobe mode in HS400/HS667 mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT ,Uses TMCLK data timeout counter for generating wr_crc_status data-timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " USE_NCRC_FOR_WR_CRC_STATUS_TIMEOUT_VAL ,Uses data timeout value as wr CRC/NCRC status timeout value" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " USE_TMCLK_FOR_DATA_TIMEOUT ,Uses TMCLK data timeout counter for generating legacy data timeout error" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,This register field is used to load wait_cycles counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,Busy should be sampled using clock instead DQS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 23. " ALLOW_CARD_CLK_STALLS_IN_WR ,Allows card clock stopping during transfer of data within a block in HIGH SPEED DDR/HS400 writes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EMMC_IOBRICK_CLK_DATA ,Used to drive AP_CLK and AN_CLK input of iobrick" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " QUALIFY_WITH_RD_DATA_VLD ,Async FIFOs in both cmd_in and dat_in paths in padmacro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,TUNING_SYS interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8.--11. " TUNING_ASYNC_FIFO_ADDNL_DELAY ,DATA/CMD IB path uses async FIFO which contributes additional delay to CMD/RESP and WDATA/CRC token round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,SD_BUS_POWER_ON_OFF interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,VOLT_SWITCH interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,TUNING_SYS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IO_TRIM_BYPASS ,Override bit for selecting between core trimmer and I/O trimmer in IB clock path" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 31. " ENHANCED_STROBE_MODE ,Enables enhanced strobe mode in HS400/HS667 mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT , Uses TMCLK data timeout counter for generating wr_crc_status data-timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " USE_TMCLK_FOR_DATA_TIMEOUT ,Uses TMCLK data timeout counter for generating legacy data timeout error" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,This register field is used to load wait_cycles counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,Busy should be sampled using clock instead DQS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 23. " ALLOW_CARD_CLK_STALLS_IN_WR ,allows card clock stopping during transfer of data within a block in HIGH SPEED DDR/HS400 writes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EMMC_IOBRICK_CLK_DATA ,Used to drive AP_CLK and AN_CLK input of iobrick" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " QUALIFY_WITH_RD_DATA_VLD ,Async FIFOs in both cmd_in and dat_in paths in padmacro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,TUNING_SYS interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8.--11. " TUNING_ASYNC_FIFO_ADDNL_DELAY ,DATA/CMD IB path uses async FIFO which contributes additional delay to CMD/RESP and WDATA/CRC token round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,SD_BUS_POWER_ON_OFF interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,VOLT_SWITCH interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,TUNING_SYS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IO_TRIM_BYPASS ,Override bit for selecting between core trimmer and I/O trimmer in IB clock path" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "VENDOR_ERR_INTR_STATUS_0,Legacy Interrupt Status Register"
|
|
bitfld.long 0x00 18. " SDMMC_LEGACY_CTLR_IDLE ,Indicates legacy SD interface controller is idle" "0,1"
|
|
bitfld.long 0x00 17. " READ_DATA_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " WRITE_CRC_STATUS_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
bitfld.long 0x00 15. " WRITE_BUSY_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RESP_BUSY_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
bitfld.long 0x00 13. " SPI_WRITE_BUSY_TIMEOUT ,SPI_WRITE_BUSY timeout" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SPI_RX_START_TOKEN_TIMEOUT ,SPI_RX_START_TOKEN timeout" "0,1"
|
|
bitfld.long 0x00 5.--8. " SPI_DAT_ERR_TOKEN ,Data Error Token while read from card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SPI_DAT_RESPONSE ,Data Response while write to card" ",,,,,DATA_ACCEPTED,,,,,,CRC_ERR,,WRITE_ERR,?..."
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER was changed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN was changed" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,CMD19 was issued while EXECUTE_TUNING was set" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10C++0x17
|
|
line.long 0x00 "VENDOR_CAP_OVERRIDES_0,Capabilities Override Bits"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
sif !cpuis("TEGRAX2")
|
|
bitfld.long 0x00 28. " CMD_QUEUING_MODE_EN ,Useful for eMMC5.x devices which support CMD queuing" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--13. " DQS_TRIM_VAL ,Tap value for incoming DQS path trimmer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DRV_LPBK_CLK_ON_CMD_LINE ,Loopback trimmed clock will be driven onto cmd line" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " VOLTAGE_3_3_V_SUPPORT_OVERRIDE ,Voltage support 3_3_V override" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " VOLTAGE_3_0_V_SUPPORT_OVERRIDE ,Voltage support 3_0_V override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VOLTAGE_1_8_V_SUPPORT_OVERRIDE ,Voltage support 1_8_V override" "Disabled,Enabled"
|
|
line.long 0x04 "VENDOR_BOOT_CNTRL_0,Vendor Boot Control Register"
|
|
bitfld.long 0x04 1. " BOOT_ACK ,Used to support Boot Option in MMC 4.3 version cards" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " BOOT ,Boot Option 1" "Disabled,Enabled"
|
|
line.long 0x08 "VENDOR_BOOT_ACK_TIMEOUT_0,Vendor Boot Acknowledgement Timeout Register"
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " VALUE ,Boot Acknowledgment timeout value"
|
|
line.long 0x0C "VENDOR_BOOT_DAT_TIMEOUT_0,Boot Data Timeout Register"
|
|
hexmask.long 0x0C 0.--24. 1. " VALUE ,Boot Data timeout value"
|
|
line.long 0x10 "VENDOR_DEBOUNCE_COUNT_0,Debounce Counter Value Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " VALUE ,The number of 32KHz clock cycles is programmed to meet the debounce period of the card slot"
|
|
line.long 0x14 "VENDOR_MISC_CNTRL_0,Miscellaneous Vendor Control Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " SDMMC_SPARE_1 ,Spare register bits with reset value of 1"
|
|
hexmask.long.word 0x14 1.--15. 1. " SDMMC_SPARE_0 ,Spare register bits with reset value of 0x40"
|
|
textline " "
|
|
bitfld.long 0x14 0. " ERASE_TIMEOUT_LIMIT ,Erase timeout value" "Finite,Infinite"
|
|
sif cpuis("TEGRAX2")
|
|
group.long 0x124++0x1F
|
|
line.long 0x00 "VENDOR_MISC_CNTRL1_0,Misc Vendor Control Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " OVERRIDE_FOR_1_8V ,Maximum override for 1.8V VDD1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OVERRIDE_FOR_3_0V ,Maximum override for 3.0V VDD1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OVERRIDE_FOR_3_3V ,Maximum override for 3.3V VDD1"
|
|
line.long 0x04 "VENDOR_MISC_CNTRL2_0,Misc Vendor Control Register 2"
|
|
bitfld.long 0x04 31. " VGPIO_MODE_EN ,VGPIO_MODE enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " SDMMC_CLK_OVR_ON ,Master clk en Override bit for all SLCGs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " SD_CARD_DETECT_STATUS_N ,SD card detect status n" "Detected,Not detected"
|
|
bitfld.long 0x04 28. " SD_CARD_WP_STATUS ,SD card wp status" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 27. " CMD_TFIFO_HOT_RESET ,CMD TFIFO hot reset" "No reset,Reset"
|
|
bitfld.long 0x04 26. " DAT_TFIFO_HOT_RESET ,DAT TFIFO hot reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ADMA3_CLKEN_OVERRIDE ,Override for sdmmc_adma3_g_clk clken" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x04 22. " ADMA3_DESC_PREFETCH_EN ,ADMA3 descriptors prefetch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " ADMA2_DESC_PREFETCH_EN ,ADMA2 descriptors prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--19. " DATA_TIMEOUT_VAL_MULTIPLIER ,Data timeout value multiplier" "No multiplier,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " DAT_TUNING_ASYNC_FIFO_ADDNL_DELAY ,Holds the additional delay in cycles which should be added to round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " ADDITIONAL_NCR_CYCLES ,Additional NCR wait time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " OVERRIDE_FOR_1_8V_VDD2 ,Maximum override for 1.8V VDD2"
|
|
textline " "
|
|
else
|
|
group.long 0x124++0x1F
|
|
line.long 0x00 "MAX_CURR_OVER_0,Maximum Current Override 0 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " OVERRIDE_FOR_1_8V ,Maximum override for 1.8V VDD1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OVERRIDE_FOR_3_0V ,Maximum override for 3.0V VDD1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OVERRIDE_FOR_3_3V ,Maximum override for 3.3V VDD1"
|
|
line.long 0x04 "MAX_CURR_OVER_HI_0,Maximum Current Override High 0 Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " OVERRIDE_FOR_1_8V_VDD2 ,Maximum override for 1.8V VDD2"
|
|
textline " "
|
|
endif
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "VENDOR_IO_TRIM_CNTRL_0,Vendor I/O Trimmer Control Register"
|
|
sif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 6.--7. " TRIM_SEL_ATEST ,Select analog test signals to send to comp pad" "No used,Input,Output before analog mux,Output after analog mux"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " TRIM_PWRSAVE ,Enables power saving mode by clock gating the unused taps in delay chain" "No,Yes"
|
|
bitfld.long 0x00 3.--4. " SEL_VREF_LEVEL ,Selects Vref voltage level" "VREF_875_MV,VREF_900_MV,VREF_925_MV,VREF_950_MV"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEL_VREG ,Select voltage supply for delay chain present in both Trimmer and DLLPROD value" "Regulated reference voltage,VAUXC"
|
|
bitfld.long 0x00 1. " SEL_VREF ,Select reference voltage for voltage regulator" "Bandgap Voltage Reference,Resistor divider voltage"
|
|
sif cpuis("TEGRAX2")
|
|
else
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "VENDOR_DLLCAL_CFG_0,Vendor DLL Calibration Configuration Register"
|
|
bitfld.long 0x00 31. " CALIBRATE ,Used to start a DLL calibration process" "Not started,Started"
|
|
bitfld.long 0x00 25.--29. " END_COUNT ,Determines the end condition of the calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 24. " USE_STATIC_CYCLES ,Calibration will be stopped when num static cycles reaches END_COUNT" "Not stopped,Stopped"
|
|
bitfld.long 0x00 23. " IGNORE_START_TRIM ,Used to ignore the START_TRM value" "Not ignored,Ignored"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " START_TRIM ,Specifies the starting trimmer value to calibrate the with"
|
|
bitfld.long 0x00 12.--15. " FILTER_BITS ,LSB of the counter to use for updating the trimmer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " SAMPLE_COUNT ,Number of times the phase detector is sampled before going onto the next set of trimmer values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAMPLE_DELAY ,Number of SDMMC host clks from changing the trimmer value"
|
|
line.long 0x04 "VENDOR_DLL_CTRL0_0,Vendor DLL Control Register 0"
|
|
bitfld.long 0x04 31. " MST_DLL_CLK_EN_OVERRIDE ,Master DLL CLK_IN enable override" "Normal,Override"
|
|
bitfld.long 0x04 30. " TX_SLV_DLL_PWRSAVE ,Active low signal" "No clock,Clock"
|
|
textline " "
|
|
bitfld.long 0x04 29. " RX_SLV_DLL_PWRSAVE ,Active low signal" "No clock,Clock"
|
|
hexmask.long.byte 0x04 22.--28. 1. " TX_SLV_DLL_DLY_CODE ,7-bit delay code to be applied to TX slave DLL"
|
|
textline " "
|
|
hexmask.long.byte 0x04 15.--21. 1. " RX_SLV_DLL_DLY_CODE ,7-bit delay code to be applied to RX slave DLL"
|
|
bitfld.long 0x04 14. " DLLCAL_BYPASS ,DLL calibration bypass enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x04 7.--13. 1. " TX_DLY_CODE_OFFSET ,Two-s complement offset will be added to delay code generated by calibration controller and sent to TX slv DLL"
|
|
hexmask.long.byte 0x04 0.--6. 1. " RX_DLY_CODE_OFFSET ,Two-s complement offset will be added to delay code generated by calibration controller and sent to RX slv DLL"
|
|
line.long 0x08 "VENDOR_DLL_CTRL1_0,Vendor DLL Control Register 1"
|
|
hexmask.long.byte 0x08 24.--30. 1. " REQD_DELAY_STEPS_TX ,Delay required in steps of 1/64 UI - 0 to 63 steps MST DLL is half cycle locked"
|
|
hexmask.long.byte 0x08 16.--22. 1. " REQD_DELAY_STEPS_RX ,Delay required in steps of 1/64 UI - 0 to 63 steps MST DLL is half cycle locked"
|
|
textline " "
|
|
bitfld.long 0x08 11.--15. " MST_DLL_RESET_TIME ,Master DLL CLK_IN enable override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 7.--10. " SLV_DLL_SETTLE_TIME ,Slave DLL requires 4 cycles settle time when dly code is changed for providing stable output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--6. 1. " MST_DLL_DLY_CODE ,7-bit delay code (128 taps) to be applied to master DLL"
|
|
line.long 0x0C "VENDOR_DLLCAL_CFG_STA_0,Vendor DLL Calibration Configuration Register"
|
|
bitfld.long 0x0C 31. " DLL_CAL_ACTIVE ,Calibration process status software has to wait for DONE once calibrate bit is cleared and before starting data transfers on eMMC interface" "Done,Running"
|
|
bitfld.long 0x0C 30. " DLL_PD ,Master DLL Phase detector output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " MST_DLL_RST_OVERRIDE_EN ,Master DLL reset is controlled by programming MST_DLL_RST/DLL controller" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " MST_DLL_RST ,Master DLL reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " SLV_DLL_CLK_OUT_DIS_OVERRIDE_EN ,Slave DLL clk_out_dis is controlled by programming SLV_DLL_CLK_OUT_DIS/DLL controller" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " SLV_DLL_CLK_OUT_DIS ,Slave DLL clock out disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " MST_DLL_PWRDN_OVERRIDE_EN ,Master DLL can be kept in power down mode by programming MST_DLL_PWRDN field" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " MST_DLL_PWRDN ,Master DLL power down enable - active high control - used when MST_DLL_PWRDN_OVERRIDE_EN is set" "Power up,Power down"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 16.--22. 1. " TX_DLY_CODE_ADJ ,Delay code sent to TX slave DLL after applying offset"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " RX_DLY_CODE_ADJ ,Delay code sent to RX slave DLL after applying offset"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--6. 1. " DLY_CODE ,Holds delay code determined by calibration process which is sent to MST DLL during calibration"
|
|
endif
|
|
group.long 0x1C0++0x07
|
|
line.long 0x00 "VENDOR_TUNING_CNTRL0_0,Vendor Tuning Control 0 Register"
|
|
bitfld.long 0x00 30. " RD_DATA_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on read data CRC error" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " WR_DATA_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on write CRC error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " CMD_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on cmd CRC error" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RETUNING_REQ_EN_ON_CRC_ERR_DETECTION ,Generates re-tuning request" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TUNING_ERR_EN_ON_CRC_ERR_DETECTION ,Generates tuning error" "Not generated,Generated"
|
|
hexmask.long.byte 0x00 18.--25. 1. " START_TAP_VAL ,Start tap value to be used by tuning"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TAP_VAL_UPDATED_BY_HW ,Software can choose to update the tap value by itself" "Not updated,Updated"
|
|
bitfld.long 0x00 13.--15. " NUM_TUNING_ITERATIONS ,The number of tuning iterations to be used by tuning circuit" "TRIES_40,TRIES_64,TRIES_128,TRIES_192,TRIES_256,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 6.--12. 1. " MUL_M ,Implements a multiplier"
|
|
bitfld.long 0x00 3.--5. " DIV_N ,Implements a divider" "1,2,4,8,16,32,64,128"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TUNING_WORD_SEL ,Selects desired word from 256-bit tuning status bitmap status_word" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "VENDOR_TUNING_CNTRL1_0,Vendor Tuning Control 1 Register"
|
|
bitfld.long 0x04 4.--6. " STEP_SIZE_SDR104_HS200 ,TAP_VAL is incremented by step_size for every tuning iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " STEP_SIZE_SDR50 ,TAP_VAL is incremented by step_size for every tuning iteration" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1C8++0x07
|
|
line.long 0x00 "VENDOR_TUNING_STATUS0_0,Vendor Tuning Status 0 Register"
|
|
line.long 0x04 "VENDOR_TUNING_STATUS1_0,Vendor Tuning Status 1 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PASS_WINDOW_END_BEFORE_FINE_TUNING , End tap value of best PASS window found by scan FSM"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PASS_WINDOW_START_BEFORE_FINE_TUNING ,Start tap value of best PASS window found by scan FSM"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " PASS_WINDOW_END_AFTER_FINE_TUNING ,End tap value of best PASS window after fine tuning"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PASS_WINDOW_START_AFTER_FINE_TUNING ,Start tap value of best PASS window after fine tuning"
|
|
textline " "
|
|
endif
|
|
width 28.
|
|
group.long 0x1D0++0x0F
|
|
line.long 0x00 "VENDOR_CLK_GATE_HYST_CNT_0,Vendor Clock Gating Hysteresis Counter Initial Value"
|
|
bitfld.long 0x00 0.--5. " CLK_COUNT ,CLK count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "VENDOR_PRESET_VAL0_0,Vendor Preset Value Register 0"
|
|
hexmask.long.word 0x04 20.--29. 1. " SDCLK_FREQ_SEL_HIGH_SPEED ,10-bit divider value to generate an SD clock in default speed mode (<50 MHz)"
|
|
hexmask.long.word 0x04 10.--19. 1. " SDCLK_FREQ_SEL_DEFAULT ,10-bit divider value to generate an SD clock in default speed mode (<25 MHz)"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--9. 1. " SDCLK_FREQ_SEL_INIT ,10-bit divider value to generate the desired SD clock frequency during initialization"
|
|
line.long 0x08 "VENDOR_PRESET_VAL1_0,Vendor Preset Value Register 1"
|
|
hexmask.long.word 0x08 20.--29. 1. " SDCLK_FREQ_SEL_SDR50 ,10-bit divider value to generate the SD clock in SDR50 mode"
|
|
hexmask.long.word 0x08 10.--19. 1. " SDCLK_FREQ_SEL_SDR25 ,10-bit divider value to generate the SD clock in SDR25 mode"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--9. 1. " SDCLK_FREQ_SEL_SDR12 ,10-bit divider value to generate the SD clock in SDR12 mode"
|
|
line.long 0x0C "VENDOR_PRESET_VAL2_0,Vendor Preset Value Register 2"
|
|
hexmask.long.word 0x0C 10.--19. 1. " SDCLK_FREQ_SEL_DDR50 ,10-bit divider value to generate the SD clock in DDR50 mode"
|
|
hexmask.long.word 0x0C 0.--9. 1. " SDCLK_FREQ_SEL_SDR104 ,10-bit divider value to generate the SD clock in SDR104 mode"
|
|
sif cpuis("TEGRAX2")
|
|
if (((d.l(ad:0x700B0200+0x1E4))&0x20000000)==0x20000000)
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_E_PBIAS_BUF ,Enables internally generated bias levels for driver PMOS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Select different bias levels for driver PMOS when E_PBIAS_BUF=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_E_PBIAS_BUF ,Enables internally generated bias levels for driver PMOS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
hexmask.long.byte 0x00 20.--26. 1. " COMP_PAD_DRVUP_OVR ,Used to drive DRVUP input of COMP pad"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--18. 1. " COMP_PAD_DRVDN_OVR ,Used to drive DRVDN input of COMP pad"
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Select different bias levels for driver PMOS when E_PBIAS_BUF=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
elif cpuis("TEGRAX1")
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_REG_ON ,Turns ON regulator in comp pad" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 10. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Used to control vref_sel input of COMP pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if (((d.l(ad:0x700B0200+0x1E4))&0x20000000)==0x20000000)
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 29.--30. " PU_PAD_DRV_TYPE ,Pu pad drv type" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " PD_PAD_DRV_TYPE ,Pd pad drv type" "0,1,2,3"
|
|
bitfld.long 0x00 11. " PU_PAD_E_TEST_OUT ,Pu pad E test out" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PD_PAD_E_TEST_OUT ,Pd pad E test out" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " PU_PAD_TEST_SEL ,pu pad test sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PD_PAD_TEST_SEL ,Pd pad test sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,sdmmc2tmc cfg Sdmemcomp vref sel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 29.--30. " PU_PAD_DRV_TYPE ,PU PAD DRV TYPE" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " PD_PAD_DRV_TYPE ,PD PAD DRV TYPE" "0,1,2,3"
|
|
hexmask.long.byte 0x00 20.--26. 1. " CFG_SDMEMCOMP_DRVUP ,SDMMC pads drive up/down control"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--18. 1. " CFG_SDMEMCOMP_DRVDN ,SDMMC pads drive up/down control"
|
|
bitfld.long 0x00 11. " PU_PAD_E_TEST_OUT ,PU PAD E TEST OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PD_PAD_E_TEST_OUT ,PD_PAD_E_TEST_OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " PU_PAD_TEST_SEL ,PU PAD TEST SEL" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PD_PAD_TEST_SEL ,PD PAD TEST SEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,SDMMC2TMC CFG SDMEMCOMP VREF SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long 0x1E4++0x07
|
|
line.long 0x00 "AUTO_CAL_CFG_0,SDMEMCOMP Pad Auto-Calibration Settings"
|
|
bitfld.long 0x00 31. " AUTO_CAL_START ,Calibration state machine" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " AUTO_CAL_OVERRIDE ,AUTOCAL override" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 29. " AUTO_CAL_ENABLE ,AUTOCAL enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " AUTO_CAL_SLW_OVERRIDE ,AUTOCAL slew rate override" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " AUTO_CAL_STEP ,Calibration step interval" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PD_OFFSET ,2's complement offset for pull-down value"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PU_OFFSET ,2's complement offset for pull-up value"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
else
|
|
group.long 0x1E8++0x07
|
|
line.long 0x00 "AUTO_CAL_INTERVAL_0,SDMEMCOMP Pad Calibration Interval"
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "AUTO_CAL_STATUS_0,SDMEMCOMP Pad Calibration Status"
|
|
bitfld.long 0x00 31. " AUTO_CAL_ACTIVE ,Auto cal active" "Inactive,Active"
|
|
hexmask.long.byte 0x00 24.--30. 1. " AUTO_CAL_PULLDOWN_ADJ ,Pulldown code sent to pads"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " AUTO_CAL_PULLUP_ADJ ,Pullup code sent to pads"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PULLDOWN ,Pulldown code generated by auto-calibration"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PULLUP ,Pullup code generated by auto-calibration"
|
|
endif
|
|
sif cpuis("TEGRAX1")
|
|
group.long 0x1F0++0x07
|
|
line.long 0x00 "IO_SPARE_0,Memory Client Interface FIFO Control"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPARE_OUT ,PROD value"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPARE_IN ,PROD value"
|
|
endif
|
|
sif cpuis("TEGRAX2")
|
|
textline " "
|
|
group.long 0x1FC++0x0B
|
|
line.long 0x00 "CIF2AXI_CTRL_0,SD/MMC CIF2AXI Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MC_WRITE_REQ_STREAM_ID ,MC write transaction stream ID"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MC_READ_REQ_STREAM_ID ,MC read transaction stream ID"
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "TZ_DMA_CTRL_0,SD/MMC DMA Requests Security Attribute Control Register"
|
|
bitfld.long 0x00 1. " MC_WRITE_REQ_TZ_ACCESS_EN ,MC_WRITE_REQ_TZ_ACCESS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MC_READ_REQ_TZ_ACCESS_EN ,MC_READ_REQ_TZ_ACCESS enable" "Disabled,Enabled"
|
|
line.long 0x04 "VENDOR_MISC_CNTRL3_0,Misc Vendor Control Register 3"
|
|
bitfld.long 0x04 30. " STOP_TRIM_IN_CLK_DURING_TUNING ,Stops rx clk trimmer and rx FIFOs input clock during tuning" "Not stopped,Stopped"
|
|
bitfld.long 0x04 24.--29. " TUNING_TRIMMER_RECOVERY_TIME ,TUNING TRIMMER RECOVERY TIME" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " E_DIFF_DQ , Diff/Vref rx selection for DAT[7:0]"
|
|
bitfld.long 0x04 4. " E_DIFF_CMD ,Diff/Vref rx selection for CMD" "Stopped,Not stopped"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DAT_OE_POSTAMBLE_EN ,DAT pads output driver one cycle after disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " DAT_OE_PREAMBLE_EN ,DAT pads output driver one cycle before enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CMD_OE_POSTAMBLE_EN ,CMD pad output driver one cycle after disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CMD_OE_PREAMBLE_EN ,CMD pad output driver one cycle before enable" "Disabled,Enabled"
|
|
group.long 0x20C++0x07
|
|
line.long 0x00 "VENDOR_MISC_CNTRL4_0,Misc Vendor Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " SDMMC_SPARE3 ,Spare register bits with reset value of 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDMMC_SPARE2 ,Spare register bits with reset value of 0"
|
|
else
|
|
group.long 0x1F4++0x07
|
|
line.long 0x00 "SDMMC_MCCIF_FIFOCTRL_0,Memory Client Interface FIFO Control"
|
|
bitfld.long 0x00 20. " SDMMC_RCLK_OVR_MODE ,SDMMC RCLK OVR MODE" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SDMMC_WCLK_OVR_MODE ,SDMMC WCLK OVR MODE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SDMMC_CCLK_OVERRIDE ,SDMMC CCLK OVERRIDE" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SDMMC_RCLK_OVERRIDE ,SDMMC RCLK OVERRIDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SDMMC_WCLK_OVERRIDE ,SDMMC WCLK OVERRIDE" "Disabled,Enabled"
|
|
line.long 0x04 "TIMEOUT_WCOAL_SDMMC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SDMMCW_WCOAL_TMVAL ,SDMMCW WCOAL TMVAL"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "SDMMC-2B"
|
|
base ad:0x700B2200
|
|
tree.open "Standard Registers"
|
|
width 27.
|
|
sif !cpuis("TEGRAX1")&&!cpuis("TEGRAX2")
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "PSR,Present State Register"
|
|
bitfld.long 0x00 25.--28. " DAT_7_4_LINE_LEVEL ,This status reflects the DAT[7:4] lines state for debug" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif !cpuis("TEGRAX2")
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " BOOT_ACK_ERR ,Boot ack status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " BOOT_ACK_TIMEOUT_ERR ,Boot Ack is not received" "Not occurred,Occurred"
|
|
line.long 0x04 "ISTAER,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor Ack_Timeout and Ack error status" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
line.long 0x08 "ISIGR,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor specification error" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
else
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "INTERRUPT_STATUS_0,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " BOOT_ACK_ERR ,Boot ack status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " BOOT_ACK_TIMEOUT_ERR ,Boot Ack is not received" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BUFFER_READ_READY ,Buffer read ready" "NO_INT,GEN_INT"
|
|
line.long 0x04 "INTERRUPT_STATUS_ENABLE_0,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor Ack_Timeout and Ack error status" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BUFFER_READ_READY ,Buffer read ready" "Disabled,Enabled"
|
|
line.long 0x08 "INTERRUPT_SIGNAL_ENABLE_0,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor specification error" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
textline " "
|
|
bitfld.long 0x08 5. " BUFFER_READ_READY ,Buffer read ready" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("TEGRAX1")
|
|
group.long 0x3C++0x0B
|
|
line.long 0x00 "AUTO_CMD12_ERR_STATUS_0,Auto cmd12 err status 0"
|
|
bitfld.long 0x00 16.--18. " UHS_MODE_SEL ,UHS Mode Select" "LEGACY,HIGH,SDR50,SDR104,DDR50,HS400,?..."
|
|
endif
|
|
sif !cpuis("TEGRAX2")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FER,Force Event Register"
|
|
bitfld.long 0x00 30.--31. " VENDOR_SPECIFIC_ERR_STATUS ,Vendor specific error status" "No effect,ACK_TIMEOUT_ERR,ACK_ERR,Both"
|
|
endif
|
|
tree.end
|
|
tree.open "Vendor-Specific Registers"
|
|
width 27.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "VENDOR_CLOCK_CNTRL_0,Vendor Clock Control Register"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 29. " DIFF_CLK_SEL ,Selects differential CLK and DQS" "0,1"
|
|
bitfld.long 0x00 24.--28. " TRIM_VAL ,Tap value for output data path trimmer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " TAP_VAL ,Tap value for input data path trimmer"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BASE_CLK_FREQ ,SD/MMC clock frequency"
|
|
textline " "
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 6. " LEGACY_CLKEN_OVERRIDE ,Override for sdmmc_legacy_g_clk clken" "Normal,Override"
|
|
textline " "
|
|
endif
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 4. " UHS2_CAPABILITY_OVERRIDE ,Override the UHS-II capabilities bit" "Normal,Override"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " PADPIPE_CLKEN_OVERRIDE ,Override for padmacro and pipemacro clken" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SPI_MODE_CLKEN_OVERRIDE ,Override for CLKEN during SPI_MODE during sw_reset" "Normal,Override"
|
|
bitfld.long 0x00 1. " INPUT_IO_CLK ,Input I/O clock" "Feedback,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SDMMC_CLK ,Set when sdmmc_clk is supplied by the CAR module prior to sdmmc_clk switch OFF" "Disabled,Enabled"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
if (((d.l(ad:0x700B2200+0x104))&0x40000000)==0x40000000)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 31. " ENHANCED_STROBE_MODE ,Enables enhanced strobe mode in HS400/HS667 mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT ,Uses TMCLK data timeout counter for generating wr_crc_status data-timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " USE_NCRC_FOR_WR_CRC_STATUS_TIMEOUT_VAL ,Uses data timeout value as wr CRC/NCRC status timeout value" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " USE_TMCLK_FOR_DATA_TIMEOUT ,Uses TMCLK data timeout counter for generating legacy data timeout error" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,This register field is used to load wait_cycles counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,Busy should be sampled using clock instead DQS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 23. " ALLOW_CARD_CLK_STALLS_IN_WR ,Allows card clock stopping during transfer of data within a block in HIGH SPEED DDR/HS400 writes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EMMC_IOBRICK_CLK_DATA ,Used to drive AP_CLK and AN_CLK input of iobrick" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " QUALIFY_WITH_RD_DATA_VLD ,Async FIFOs in both cmd_in and dat_in paths in padmacro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,TUNING_SYS interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8.--11. " TUNING_ASYNC_FIFO_ADDNL_DELAY ,DATA/CMD IB path uses async FIFO which contributes additional delay to CMD/RESP and WDATA/CRC token round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,SD_BUS_POWER_ON_OFF interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,VOLT_SWITCH interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,TUNING_SYS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IO_TRIM_BYPASS ,Override bit for selecting between core trimmer and I/O trimmer in IB clock path" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 31. " ENHANCED_STROBE_MODE ,Enables enhanced strobe mode in HS400/HS667 mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT , Uses TMCLK data timeout counter for generating wr_crc_status data-timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " USE_TMCLK_FOR_DATA_TIMEOUT ,Uses TMCLK data timeout counter for generating legacy data timeout error" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,This register field is used to load wait_cycles counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,Busy should be sampled using clock instead DQS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 23. " ALLOW_CARD_CLK_STALLS_IN_WR ,allows card clock stopping during transfer of data within a block in HIGH SPEED DDR/HS400 writes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EMMC_IOBRICK_CLK_DATA ,Used to drive AP_CLK and AN_CLK input of iobrick" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " QUALIFY_WITH_RD_DATA_VLD ,Async FIFOs in both cmd_in and dat_in paths in padmacro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,TUNING_SYS interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8.--11. " TUNING_ASYNC_FIFO_ADDNL_DELAY ,DATA/CMD IB path uses async FIFO which contributes additional delay to CMD/RESP and WDATA/CRC token round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,SD_BUS_POWER_ON_OFF interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,VOLT_SWITCH interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,TUNING_SYS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IO_TRIM_BYPASS ,Override bit for selecting between core trimmer and I/O trimmer in IB clock path" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "VENDOR_ERR_INTR_STATUS_0,Legacy Interrupt Status Register"
|
|
bitfld.long 0x00 18. " SDMMC_LEGACY_CTLR_IDLE ,Indicates legacy SD interface controller is idle" "0,1"
|
|
bitfld.long 0x00 17. " READ_DATA_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " WRITE_CRC_STATUS_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
bitfld.long 0x00 15. " WRITE_BUSY_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RESP_BUSY_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
bitfld.long 0x00 13. " SPI_WRITE_BUSY_TIMEOUT ,SPI_WRITE_BUSY timeout" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SPI_RX_START_TOKEN_TIMEOUT ,SPI_RX_START_TOKEN timeout" "0,1"
|
|
bitfld.long 0x00 5.--8. " SPI_DAT_ERR_TOKEN ,Data Error Token while read from card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SPI_DAT_RESPONSE ,Data Response while write to card" ",,,,,DATA_ACCEPTED,,,,,,CRC_ERR,,WRITE_ERR,?..."
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER was changed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN was changed" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,CMD19 was issued while EXECUTE_TUNING was set" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10C++0x17
|
|
line.long 0x00 "VENDOR_CAP_OVERRIDES_0,Capabilities Override Bits"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
sif !cpuis("TEGRAX2")
|
|
bitfld.long 0x00 28. " CMD_QUEUING_MODE_EN ,Useful for eMMC5.x devices which support CMD queuing" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--13. " DQS_TRIM_VAL ,Tap value for incoming DQS path trimmer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DRV_LPBK_CLK_ON_CMD_LINE ,Loopback trimmed clock will be driven onto cmd line" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " VOLTAGE_3_3_V_SUPPORT_OVERRIDE ,Voltage support 3_3_V override" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " VOLTAGE_3_0_V_SUPPORT_OVERRIDE ,Voltage support 3_0_V override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VOLTAGE_1_8_V_SUPPORT_OVERRIDE ,Voltage support 1_8_V override" "Disabled,Enabled"
|
|
line.long 0x04 "VENDOR_BOOT_CNTRL_0,Vendor Boot Control Register"
|
|
bitfld.long 0x04 1. " BOOT_ACK ,Used to support Boot Option in MMC 4.3 version cards" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " BOOT ,Boot Option 1" "Disabled,Enabled"
|
|
line.long 0x08 "VENDOR_BOOT_ACK_TIMEOUT_0,Vendor Boot Acknowledgement Timeout Register"
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " VALUE ,Boot Acknowledgment timeout value"
|
|
line.long 0x0C "VENDOR_BOOT_DAT_TIMEOUT_0,Boot Data Timeout Register"
|
|
hexmask.long 0x0C 0.--24. 1. " VALUE ,Boot Data timeout value"
|
|
line.long 0x10 "VENDOR_DEBOUNCE_COUNT_0,Debounce Counter Value Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " VALUE ,The number of 32KHz clock cycles is programmed to meet the debounce period of the card slot"
|
|
line.long 0x14 "VENDOR_MISC_CNTRL_0,Miscellaneous Vendor Control Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " SDMMC_SPARE_1 ,Spare register bits with reset value of 1"
|
|
hexmask.long.word 0x14 1.--15. 1. " SDMMC_SPARE_0 ,Spare register bits with reset value of 0x40"
|
|
textline " "
|
|
bitfld.long 0x14 0. " ERASE_TIMEOUT_LIMIT ,Erase timeout value" "Finite,Infinite"
|
|
sif cpuis("TEGRAX2")
|
|
group.long 0x124++0x1F
|
|
line.long 0x00 "VENDOR_MISC_CNTRL1_0,Misc Vendor Control Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " OVERRIDE_FOR_1_8V ,Maximum override for 1.8V VDD1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OVERRIDE_FOR_3_0V ,Maximum override for 3.0V VDD1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OVERRIDE_FOR_3_3V ,Maximum override for 3.3V VDD1"
|
|
line.long 0x04 "VENDOR_MISC_CNTRL2_0,Misc Vendor Control Register 2"
|
|
bitfld.long 0x04 31. " VGPIO_MODE_EN ,VGPIO_MODE enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " SDMMC_CLK_OVR_ON ,Master clk en Override bit for all SLCGs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " SD_CARD_DETECT_STATUS_N ,SD card detect status n" "Detected,Not detected"
|
|
bitfld.long 0x04 28. " SD_CARD_WP_STATUS ,SD card wp status" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 27. " CMD_TFIFO_HOT_RESET ,CMD TFIFO hot reset" "No reset,Reset"
|
|
bitfld.long 0x04 26. " DAT_TFIFO_HOT_RESET ,DAT TFIFO hot reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ADMA3_CLKEN_OVERRIDE ,Override for sdmmc_adma3_g_clk clken" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x04 22. " ADMA3_DESC_PREFETCH_EN ,ADMA3 descriptors prefetch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " ADMA2_DESC_PREFETCH_EN ,ADMA2 descriptors prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--19. " DATA_TIMEOUT_VAL_MULTIPLIER ,Data timeout value multiplier" "No multiplier,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " DAT_TUNING_ASYNC_FIFO_ADDNL_DELAY ,Holds the additional delay in cycles which should be added to round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " ADDITIONAL_NCR_CYCLES ,Additional NCR wait time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " OVERRIDE_FOR_1_8V_VDD2 ,Maximum override for 1.8V VDD2"
|
|
textline " "
|
|
else
|
|
group.long 0x124++0x1F
|
|
line.long 0x00 "MAX_CURR_OVER_0,Maximum Current Override 0 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " OVERRIDE_FOR_1_8V ,Maximum override for 1.8V VDD1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OVERRIDE_FOR_3_0V ,Maximum override for 3.0V VDD1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OVERRIDE_FOR_3_3V ,Maximum override for 3.3V VDD1"
|
|
line.long 0x04 "MAX_CURR_OVER_HI_0,Maximum Current Override High 0 Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " OVERRIDE_FOR_1_8V_VDD2 ,Maximum override for 1.8V VDD2"
|
|
textline " "
|
|
endif
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "VENDOR_IO_TRIM_CNTRL_0,Vendor I/O Trimmer Control Register"
|
|
sif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 6.--7. " TRIM_SEL_ATEST ,Select analog test signals to send to comp pad" "No used,Input,Output before analog mux,Output after analog mux"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " TRIM_PWRSAVE ,Enables power saving mode by clock gating the unused taps in delay chain" "No,Yes"
|
|
bitfld.long 0x00 3.--4. " SEL_VREF_LEVEL ,Selects Vref voltage level" "VREF_875_MV,VREF_900_MV,VREF_925_MV,VREF_950_MV"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEL_VREG ,Select voltage supply for delay chain present in both Trimmer and DLLPROD value" "Regulated reference voltage,VAUXC"
|
|
bitfld.long 0x00 1. " SEL_VREF ,Select reference voltage for voltage regulator" "Bandgap Voltage Reference,Resistor divider voltage"
|
|
sif cpuis("TEGRAX2")
|
|
else
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "VENDOR_DLLCAL_CFG_0,Vendor DLL Calibration Configuration Register"
|
|
bitfld.long 0x00 31. " CALIBRATE ,Used to start a DLL calibration process" "Not started,Started"
|
|
bitfld.long 0x00 25.--29. " END_COUNT ,Determines the end condition of the calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 24. " USE_STATIC_CYCLES ,Calibration will be stopped when num static cycles reaches END_COUNT" "Not stopped,Stopped"
|
|
bitfld.long 0x00 23. " IGNORE_START_TRIM ,Used to ignore the START_TRM value" "Not ignored,Ignored"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " START_TRIM ,Specifies the starting trimmer value to calibrate the with"
|
|
bitfld.long 0x00 12.--15. " FILTER_BITS ,LSB of the counter to use for updating the trimmer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " SAMPLE_COUNT ,Number of times the phase detector is sampled before going onto the next set of trimmer values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAMPLE_DELAY ,Number of SDMMC host clks from changing the trimmer value"
|
|
line.long 0x04 "VENDOR_DLL_CTRL0_0,Vendor DLL Control Register 0"
|
|
bitfld.long 0x04 31. " MST_DLL_CLK_EN_OVERRIDE ,Master DLL CLK_IN enable override" "Normal,Override"
|
|
bitfld.long 0x04 30. " TX_SLV_DLL_PWRSAVE ,Active low signal" "No clock,Clock"
|
|
textline " "
|
|
bitfld.long 0x04 29. " RX_SLV_DLL_PWRSAVE ,Active low signal" "No clock,Clock"
|
|
hexmask.long.byte 0x04 22.--28. 1. " TX_SLV_DLL_DLY_CODE ,7-bit delay code to be applied to TX slave DLL"
|
|
textline " "
|
|
hexmask.long.byte 0x04 15.--21. 1. " RX_SLV_DLL_DLY_CODE ,7-bit delay code to be applied to RX slave DLL"
|
|
bitfld.long 0x04 14. " DLLCAL_BYPASS ,DLL calibration bypass enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x04 7.--13. 1. " TX_DLY_CODE_OFFSET ,Two-s complement offset will be added to delay code generated by calibration controller and sent to TX slv DLL"
|
|
hexmask.long.byte 0x04 0.--6. 1. " RX_DLY_CODE_OFFSET ,Two-s complement offset will be added to delay code generated by calibration controller and sent to RX slv DLL"
|
|
line.long 0x08 "VENDOR_DLL_CTRL1_0,Vendor DLL Control Register 1"
|
|
hexmask.long.byte 0x08 24.--30. 1. " REQD_DELAY_STEPS_TX ,Delay required in steps of 1/64 UI - 0 to 63 steps MST DLL is half cycle locked"
|
|
hexmask.long.byte 0x08 16.--22. 1. " REQD_DELAY_STEPS_RX ,Delay required in steps of 1/64 UI - 0 to 63 steps MST DLL is half cycle locked"
|
|
textline " "
|
|
bitfld.long 0x08 11.--15. " MST_DLL_RESET_TIME ,Master DLL CLK_IN enable override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 7.--10. " SLV_DLL_SETTLE_TIME ,Slave DLL requires 4 cycles settle time when dly code is changed for providing stable output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--6. 1. " MST_DLL_DLY_CODE ,7-bit delay code (128 taps) to be applied to master DLL"
|
|
line.long 0x0C "VENDOR_DLLCAL_CFG_STA_0,Vendor DLL Calibration Configuration Register"
|
|
bitfld.long 0x0C 31. " DLL_CAL_ACTIVE ,Calibration process status software has to wait for DONE once calibrate bit is cleared and before starting data transfers on eMMC interface" "Done,Running"
|
|
bitfld.long 0x0C 30. " DLL_PD ,Master DLL Phase detector output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " MST_DLL_RST_OVERRIDE_EN ,Master DLL reset is controlled by programming MST_DLL_RST/DLL controller" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " MST_DLL_RST ,Master DLL reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " SLV_DLL_CLK_OUT_DIS_OVERRIDE_EN ,Slave DLL clk_out_dis is controlled by programming SLV_DLL_CLK_OUT_DIS/DLL controller" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " SLV_DLL_CLK_OUT_DIS ,Slave DLL clock out disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " MST_DLL_PWRDN_OVERRIDE_EN ,Master DLL can be kept in power down mode by programming MST_DLL_PWRDN field" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " MST_DLL_PWRDN ,Master DLL power down enable - active high control - used when MST_DLL_PWRDN_OVERRIDE_EN is set" "Power up,Power down"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 16.--22. 1. " TX_DLY_CODE_ADJ ,Delay code sent to TX slave DLL after applying offset"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " RX_DLY_CODE_ADJ ,Delay code sent to RX slave DLL after applying offset"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--6. 1. " DLY_CODE ,Holds delay code determined by calibration process which is sent to MST DLL during calibration"
|
|
endif
|
|
group.long 0x1C0++0x07
|
|
line.long 0x00 "VENDOR_TUNING_CNTRL0_0,Vendor Tuning Control 0 Register"
|
|
bitfld.long 0x00 30. " RD_DATA_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on read data CRC error" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " WR_DATA_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on write CRC error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " CMD_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on cmd CRC error" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RETUNING_REQ_EN_ON_CRC_ERR_DETECTION ,Generates re-tuning request" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TUNING_ERR_EN_ON_CRC_ERR_DETECTION ,Generates tuning error" "Not generated,Generated"
|
|
hexmask.long.byte 0x00 18.--25. 1. " START_TAP_VAL ,Start tap value to be used by tuning"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TAP_VAL_UPDATED_BY_HW ,Software can choose to update the tap value by itself" "Not updated,Updated"
|
|
bitfld.long 0x00 13.--15. " NUM_TUNING_ITERATIONS ,The number of tuning iterations to be used by tuning circuit" "TRIES_40,TRIES_64,TRIES_128,TRIES_192,TRIES_256,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 6.--12. 1. " MUL_M ,Implements a multiplier"
|
|
bitfld.long 0x00 3.--5. " DIV_N ,Implements a divider" "1,2,4,8,16,32,64,128"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TUNING_WORD_SEL ,Selects desired word from 256-bit tuning status bitmap status_word" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "VENDOR_TUNING_CNTRL1_0,Vendor Tuning Control 1 Register"
|
|
bitfld.long 0x04 4.--6. " STEP_SIZE_SDR104_HS200 ,TAP_VAL is incremented by step_size for every tuning iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " STEP_SIZE_SDR50 ,TAP_VAL is incremented by step_size for every tuning iteration" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1C8++0x07
|
|
line.long 0x00 "VENDOR_TUNING_STATUS0_0,Vendor Tuning Status 0 Register"
|
|
line.long 0x04 "VENDOR_TUNING_STATUS1_0,Vendor Tuning Status 1 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PASS_WINDOW_END_BEFORE_FINE_TUNING , End tap value of best PASS window found by scan FSM"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PASS_WINDOW_START_BEFORE_FINE_TUNING ,Start tap value of best PASS window found by scan FSM"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " PASS_WINDOW_END_AFTER_FINE_TUNING ,End tap value of best PASS window after fine tuning"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PASS_WINDOW_START_AFTER_FINE_TUNING ,Start tap value of best PASS window after fine tuning"
|
|
textline " "
|
|
endif
|
|
width 28.
|
|
group.long 0x1D0++0x0F
|
|
line.long 0x00 "VENDOR_CLK_GATE_HYST_CNT_0,Vendor Clock Gating Hysteresis Counter Initial Value"
|
|
bitfld.long 0x00 0.--5. " CLK_COUNT ,CLK count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "VENDOR_PRESET_VAL0_0,Vendor Preset Value Register 0"
|
|
hexmask.long.word 0x04 20.--29. 1. " SDCLK_FREQ_SEL_HIGH_SPEED ,10-bit divider value to generate an SD clock in default speed mode (<50 MHz)"
|
|
hexmask.long.word 0x04 10.--19. 1. " SDCLK_FREQ_SEL_DEFAULT ,10-bit divider value to generate an SD clock in default speed mode (<25 MHz)"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--9. 1. " SDCLK_FREQ_SEL_INIT ,10-bit divider value to generate the desired SD clock frequency during initialization"
|
|
line.long 0x08 "VENDOR_PRESET_VAL1_0,Vendor Preset Value Register 1"
|
|
hexmask.long.word 0x08 20.--29. 1. " SDCLK_FREQ_SEL_SDR50 ,10-bit divider value to generate the SD clock in SDR50 mode"
|
|
hexmask.long.word 0x08 10.--19. 1. " SDCLK_FREQ_SEL_SDR25 ,10-bit divider value to generate the SD clock in SDR25 mode"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--9. 1. " SDCLK_FREQ_SEL_SDR12 ,10-bit divider value to generate the SD clock in SDR12 mode"
|
|
line.long 0x0C "VENDOR_PRESET_VAL2_0,Vendor Preset Value Register 2"
|
|
hexmask.long.word 0x0C 10.--19. 1. " SDCLK_FREQ_SEL_DDR50 ,10-bit divider value to generate the SD clock in DDR50 mode"
|
|
hexmask.long.word 0x0C 0.--9. 1. " SDCLK_FREQ_SEL_SDR104 ,10-bit divider value to generate the SD clock in SDR104 mode"
|
|
sif cpuis("TEGRAX2")
|
|
if (((d.l(ad:0x700B2200+0x1E4))&0x20000000)==0x20000000)
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_E_PBIAS_BUF ,Enables internally generated bias levels for driver PMOS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Select different bias levels for driver PMOS when E_PBIAS_BUF=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_E_PBIAS_BUF ,Enables internally generated bias levels for driver PMOS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
hexmask.long.byte 0x00 20.--26. 1. " COMP_PAD_DRVUP_OVR ,Used to drive DRVUP input of COMP pad"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--18. 1. " COMP_PAD_DRVDN_OVR ,Used to drive DRVDN input of COMP pad"
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Select different bias levels for driver PMOS when E_PBIAS_BUF=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
elif cpuis("TEGRAX1")
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_REG_ON ,Turns ON regulator in comp pad" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 10. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Used to control vref_sel input of COMP pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if (((d.l(ad:0x700B2200+0x1E4))&0x20000000)==0x20000000)
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 29.--30. " PU_PAD_DRV_TYPE ,Pu pad drv type" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " PD_PAD_DRV_TYPE ,Pd pad drv type" "0,1,2,3"
|
|
bitfld.long 0x00 11. " PU_PAD_E_TEST_OUT ,Pu pad E test out" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PD_PAD_E_TEST_OUT ,Pd pad E test out" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " PU_PAD_TEST_SEL ,pu pad test sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PD_PAD_TEST_SEL ,Pd pad test sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,sdmmc2tmc cfg Sdmemcomp vref sel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 29.--30. " PU_PAD_DRV_TYPE ,PU PAD DRV TYPE" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " PD_PAD_DRV_TYPE ,PD PAD DRV TYPE" "0,1,2,3"
|
|
hexmask.long.byte 0x00 20.--26. 1. " CFG_SDMEMCOMP_DRVUP ,SDMMC pads drive up/down control"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--18. 1. " CFG_SDMEMCOMP_DRVDN ,SDMMC pads drive up/down control"
|
|
bitfld.long 0x00 11. " PU_PAD_E_TEST_OUT ,PU PAD E TEST OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PD_PAD_E_TEST_OUT ,PD_PAD_E_TEST_OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " PU_PAD_TEST_SEL ,PU PAD TEST SEL" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PD_PAD_TEST_SEL ,PD PAD TEST SEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,SDMMC2TMC CFG SDMEMCOMP VREF SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long 0x1E4++0x07
|
|
line.long 0x00 "AUTO_CAL_CFG_0,SDMEMCOMP Pad Auto-Calibration Settings"
|
|
bitfld.long 0x00 31. " AUTO_CAL_START ,Calibration state machine" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " AUTO_CAL_OVERRIDE ,AUTOCAL override" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 29. " AUTO_CAL_ENABLE ,AUTOCAL enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " AUTO_CAL_SLW_OVERRIDE ,AUTOCAL slew rate override" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " AUTO_CAL_STEP ,Calibration step interval" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PD_OFFSET ,2's complement offset for pull-down value"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PU_OFFSET ,2's complement offset for pull-up value"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
else
|
|
group.long 0x1E8++0x07
|
|
line.long 0x00 "AUTO_CAL_INTERVAL_0,SDMEMCOMP Pad Calibration Interval"
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "AUTO_CAL_STATUS_0,SDMEMCOMP Pad Calibration Status"
|
|
bitfld.long 0x00 31. " AUTO_CAL_ACTIVE ,Auto cal active" "Inactive,Active"
|
|
hexmask.long.byte 0x00 24.--30. 1. " AUTO_CAL_PULLDOWN_ADJ ,Pulldown code sent to pads"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " AUTO_CAL_PULLUP_ADJ ,Pullup code sent to pads"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PULLDOWN ,Pulldown code generated by auto-calibration"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PULLUP ,Pullup code generated by auto-calibration"
|
|
endif
|
|
sif cpuis("TEGRAX1")
|
|
group.long 0x1F0++0x07
|
|
line.long 0x00 "IO_SPARE_0,Memory Client Interface FIFO Control"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPARE_OUT ,PROD value"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPARE_IN ,PROD value"
|
|
endif
|
|
sif cpuis("TEGRAX2")
|
|
textline " "
|
|
group.long 0x1FC++0x0B
|
|
line.long 0x00 "CIF2AXI_CTRL_0,SD/MMC CIF2AXI Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MC_WRITE_REQ_STREAM_ID ,MC write transaction stream ID"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MC_READ_REQ_STREAM_ID ,MC read transaction stream ID"
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "TZ_DMA_CTRL_0,SD/MMC DMA Requests Security Attribute Control Register"
|
|
bitfld.long 0x00 1. " MC_WRITE_REQ_TZ_ACCESS_EN ,MC_WRITE_REQ_TZ_ACCESS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MC_READ_REQ_TZ_ACCESS_EN ,MC_READ_REQ_TZ_ACCESS enable" "Disabled,Enabled"
|
|
line.long 0x04 "VENDOR_MISC_CNTRL3_0,Misc Vendor Control Register 3"
|
|
bitfld.long 0x04 30. " STOP_TRIM_IN_CLK_DURING_TUNING ,Stops rx clk trimmer and rx FIFOs input clock during tuning" "Not stopped,Stopped"
|
|
bitfld.long 0x04 24.--29. " TUNING_TRIMMER_RECOVERY_TIME ,TUNING TRIMMER RECOVERY TIME" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " E_DIFF_DQ , Diff/Vref rx selection for DAT[7:0]"
|
|
bitfld.long 0x04 4. " E_DIFF_CMD ,Diff/Vref rx selection for CMD" "Stopped,Not stopped"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DAT_OE_POSTAMBLE_EN ,DAT pads output driver one cycle after disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " DAT_OE_PREAMBLE_EN ,DAT pads output driver one cycle before enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CMD_OE_POSTAMBLE_EN ,CMD pad output driver one cycle after disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CMD_OE_PREAMBLE_EN ,CMD pad output driver one cycle before enable" "Disabled,Enabled"
|
|
group.long 0x20C++0x07
|
|
line.long 0x00 "VENDOR_MISC_CNTRL4_0,Misc Vendor Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " SDMMC_SPARE3 ,Spare register bits with reset value of 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDMMC_SPARE2 ,Spare register bits with reset value of 0"
|
|
else
|
|
group.long 0x1F4++0x07
|
|
line.long 0x00 "SDMMC_MCCIF_FIFOCTRL_0,Memory Client Interface FIFO Control"
|
|
bitfld.long 0x00 20. " SDMMC_RCLK_OVR_MODE ,SDMMC RCLK OVR MODE" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SDMMC_WCLK_OVR_MODE ,SDMMC WCLK OVR MODE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SDMMC_CCLK_OVERRIDE ,SDMMC CCLK OVERRIDE" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SDMMC_RCLK_OVERRIDE ,SDMMC RCLK OVERRIDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SDMMC_WCLK_OVERRIDE ,SDMMC WCLK OVERRIDE" "Disabled,Enabled"
|
|
line.long 0x04 "TIMEOUT_WCOAL_SDMMC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SDMMCW_WCOAL_TMVAL ,SDMMCW WCOAL TMVAL"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "SDMMC-3"
|
|
base ad:0x700B0400
|
|
tree.open "Standard Registers"
|
|
width 27.
|
|
sif !cpuis("TEGRAX1")&&!cpuis("TEGRAX2")
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "PSR,Present State Register"
|
|
bitfld.long 0x00 25.--28. " DAT_7_4_LINE_LEVEL ,This status reflects the DAT[7:4] lines state for debug" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif !cpuis("TEGRAX2")
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " BOOT_ACK_ERR ,Boot ack status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " BOOT_ACK_TIMEOUT_ERR ,Boot Ack is not received" "Not occurred,Occurred"
|
|
line.long 0x04 "ISTAER,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor Ack_Timeout and Ack error status" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
line.long 0x08 "ISIGR,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor specification error" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
else
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "INTERRUPT_STATUS_0,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " BOOT_ACK_ERR ,Boot ack status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " BOOT_ACK_TIMEOUT_ERR ,Boot Ack is not received" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BUFFER_READ_READY ,Buffer read ready" "NO_INT,GEN_INT"
|
|
line.long 0x04 "INTERRUPT_STATUS_ENABLE_0,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor Ack_Timeout and Ack error status" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BUFFER_READ_READY ,Buffer read ready" "Disabled,Enabled"
|
|
line.long 0x08 "INTERRUPT_SIGNAL_ENABLE_0,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor specification error" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
textline " "
|
|
bitfld.long 0x08 5. " BUFFER_READ_READY ,Buffer read ready" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("TEGRAX1")
|
|
group.long 0x3C++0x0B
|
|
line.long 0x00 "AUTO_CMD12_ERR_STATUS_0,Auto cmd12 err status 0"
|
|
bitfld.long 0x00 16.--18. " UHS_MODE_SEL ,UHS Mode Select" "LEGACY,HIGH,SDR50,SDR104,DDR50,HS400,?..."
|
|
endif
|
|
sif !cpuis("TEGRAX2")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FER,Force Event Register"
|
|
bitfld.long 0x00 30.--31. " VENDOR_SPECIFIC_ERR_STATUS ,Vendor specific error status" "No effect,ACK_TIMEOUT_ERR,ACK_ERR,Both"
|
|
endif
|
|
tree.end
|
|
tree.open "Vendor-Specific Registers"
|
|
width 27.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "VENDOR_CLOCK_CNTRL_0,Vendor Clock Control Register"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 29. " DIFF_CLK_SEL ,Selects differential CLK and DQS" "0,1"
|
|
bitfld.long 0x00 24.--28. " TRIM_VAL ,Tap value for output data path trimmer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " TAP_VAL ,Tap value for input data path trimmer"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BASE_CLK_FREQ ,SD/MMC clock frequency"
|
|
textline " "
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 6. " LEGACY_CLKEN_OVERRIDE ,Override for sdmmc_legacy_g_clk clken" "Normal,Override"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " SDR50_TUNING_OVERRIDE ,Override the SDR50_TUNING capabilities bit" "Normal,Override"
|
|
textline " "
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 4. " UHS2_CAPABILITY_OVERRIDE ,Override the UHS-II capabilities bit" "Normal,Override"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " PADPIPE_CLKEN_OVERRIDE ,Override for padmacro and pipemacro clken" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SPI_MODE_CLKEN_OVERRIDE ,Override for CLKEN during SPI_MODE during sw_reset" "Normal,Override"
|
|
bitfld.long 0x00 1. " INPUT_IO_CLK ,Input I/O clock" "Feedback,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SDMMC_CLK ,Set when sdmmc_clk is supplied by the CAR module prior to sdmmc_clk switch OFF" "Disabled,Enabled"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
if (((d.l(ad:0x700B0400+0x104))&0x40000000)==0x40000000)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 31. " ENHANCED_STROBE_MODE ,Enables enhanced strobe mode in HS400/HS667 mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT ,Uses TMCLK data timeout counter for generating wr_crc_status data-timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " USE_NCRC_FOR_WR_CRC_STATUS_TIMEOUT_VAL ,Uses data timeout value as wr CRC/NCRC status timeout value" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " USE_TMCLK_FOR_DATA_TIMEOUT ,Uses TMCLK data timeout counter for generating legacy data timeout error" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,This register field is used to load wait_cycles counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,Busy should be sampled using clock instead DQS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 23. " ALLOW_CARD_CLK_STALLS_IN_WR ,Allows card clock stopping during transfer of data within a block in HIGH SPEED DDR/HS400 writes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EMMC_IOBRICK_CLK_DATA ,Used to drive AP_CLK and AN_CLK input of iobrick" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " QUALIFY_WITH_RD_DATA_VLD ,Async FIFOs in both cmd_in and dat_in paths in padmacro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,TUNING_SYS interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8.--11. " TUNING_ASYNC_FIFO_ADDNL_DELAY ,DATA/CMD IB path uses async FIFO which contributes additional delay to CMD/RESP and WDATA/CRC token round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,SD_BUS_POWER_ON_OFF interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,VOLT_SWITCH interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,TUNING_SYS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IO_TRIM_BYPASS ,Override bit for selecting between core trimmer and I/O trimmer in IB clock path" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 31. " ENHANCED_STROBE_MODE ,Enables enhanced strobe mode in HS400/HS667 mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT , Uses TMCLK data timeout counter for generating wr_crc_status data-timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " USE_TMCLK_FOR_DATA_TIMEOUT ,Uses TMCLK data timeout counter for generating legacy data timeout error" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,This register field is used to load wait_cycles counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,Busy should be sampled using clock instead DQS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 23. " ALLOW_CARD_CLK_STALLS_IN_WR ,allows card clock stopping during transfer of data within a block in HIGH SPEED DDR/HS400 writes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EMMC_IOBRICK_CLK_DATA ,Used to drive AP_CLK and AN_CLK input of iobrick" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " QUALIFY_WITH_RD_DATA_VLD ,Async FIFOs in both cmd_in and dat_in paths in padmacro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,TUNING_SYS interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8.--11. " TUNING_ASYNC_FIFO_ADDNL_DELAY ,DATA/CMD IB path uses async FIFO which contributes additional delay to CMD/RESP and WDATA/CRC token round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,SD_BUS_POWER_ON_OFF interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,VOLT_SWITCH interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,TUNING_SYS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IO_TRIM_BYPASS ,Override bit for selecting between core trimmer and I/O trimmer in IB clock path" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "VENDOR_ERR_INTR_STATUS_0,Legacy Interrupt Status Register"
|
|
bitfld.long 0x00 18. " SDMMC_LEGACY_CTLR_IDLE ,Indicates legacy SD interface controller is idle" "0,1"
|
|
bitfld.long 0x00 17. " READ_DATA_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " WRITE_CRC_STATUS_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
bitfld.long 0x00 15. " WRITE_BUSY_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RESP_BUSY_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
bitfld.long 0x00 13. " SPI_WRITE_BUSY_TIMEOUT ,SPI_WRITE_BUSY timeout" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SPI_RX_START_TOKEN_TIMEOUT ,SPI_RX_START_TOKEN timeout" "0,1"
|
|
bitfld.long 0x00 5.--8. " SPI_DAT_ERR_TOKEN ,Data Error Token while read from card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SPI_DAT_RESPONSE ,Data Response while write to card" ",,,,,DATA_ACCEPTED,,,,,,CRC_ERR,,WRITE_ERR,?..."
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER was changed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN was changed" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,CMD19 was issued while EXECUTE_TUNING was set" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10C++0x17
|
|
line.long 0x00 "VENDOR_CAP_OVERRIDES_0,Capabilities Override Bits"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
sif !cpuis("TEGRAX2")
|
|
bitfld.long 0x00 28. " CMD_QUEUING_MODE_EN ,Useful for eMMC5.x devices which support CMD queuing" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--13. " DQS_TRIM_VAL ,Tap value for incoming DQS path trimmer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DRV_LPBK_CLK_ON_CMD_LINE ,Loopback trimmed clock will be driven onto cmd line" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " VOLTAGE_3_3_V_SUPPORT_OVERRIDE ,Voltage support 3_3_V override" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " VOLTAGE_3_0_V_SUPPORT_OVERRIDE ,Voltage support 3_0_V override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VOLTAGE_1_8_V_SUPPORT_OVERRIDE ,Voltage support 1_8_V override" "Disabled,Enabled"
|
|
line.long 0x04 "VENDOR_BOOT_CNTRL_0,Vendor Boot Control Register"
|
|
bitfld.long 0x04 1. " BOOT_ACK ,Used to support Boot Option in MMC 4.3 version cards" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " BOOT ,Boot Option 1" "Disabled,Enabled"
|
|
line.long 0x08 "VENDOR_BOOT_ACK_TIMEOUT_0,Vendor Boot Acknowledgement Timeout Register"
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " VALUE ,Boot Acknowledgment timeout value"
|
|
line.long 0x0C "VENDOR_BOOT_DAT_TIMEOUT_0,Boot Data Timeout Register"
|
|
hexmask.long 0x0C 0.--24. 1. " VALUE ,Boot Data timeout value"
|
|
line.long 0x10 "VENDOR_DEBOUNCE_COUNT_0,Debounce Counter Value Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " VALUE ,The number of 32KHz clock cycles is programmed to meet the debounce period of the card slot"
|
|
line.long 0x14 "VENDOR_MISC_CNTRL_0,Miscellaneous Vendor Control Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " SDMMC_SPARE_1 ,Spare register bits with reset value of 1"
|
|
hexmask.long.word 0x14 1.--15. 1. " SDMMC_SPARE_0 ,Spare register bits with reset value of 0x40"
|
|
textline " "
|
|
bitfld.long 0x14 0. " ERASE_TIMEOUT_LIMIT ,Erase timeout value" "Finite,Infinite"
|
|
sif cpuis("TEGRAX2")
|
|
group.long 0x124++0x1F
|
|
line.long 0x00 "VENDOR_MISC_CNTRL1_0,Misc Vendor Control Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " OVERRIDE_FOR_1_8V ,Maximum override for 1.8V VDD1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OVERRIDE_FOR_3_0V ,Maximum override for 3.0V VDD1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OVERRIDE_FOR_3_3V ,Maximum override for 3.3V VDD1"
|
|
line.long 0x04 "VENDOR_MISC_CNTRL2_0,Misc Vendor Control Register 2"
|
|
bitfld.long 0x04 31. " VGPIO_MODE_EN ,VGPIO_MODE enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " SDMMC_CLK_OVR_ON ,Master clk en Override bit for all SLCGs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " SD_CARD_DETECT_STATUS_N ,SD card detect status n" "Detected,Not detected"
|
|
bitfld.long 0x04 28. " SD_CARD_WP_STATUS ,SD card wp status" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 27. " CMD_TFIFO_HOT_RESET ,CMD TFIFO hot reset" "No reset,Reset"
|
|
bitfld.long 0x04 26. " DAT_TFIFO_HOT_RESET ,DAT TFIFO hot reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ADMA3_CLKEN_OVERRIDE ,Override for sdmmc_adma3_g_clk clken" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x04 22. " ADMA3_DESC_PREFETCH_EN ,ADMA3 descriptors prefetch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " ADMA2_DESC_PREFETCH_EN ,ADMA2 descriptors prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--19. " DATA_TIMEOUT_VAL_MULTIPLIER ,Data timeout value multiplier" "No multiplier,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " DAT_TUNING_ASYNC_FIFO_ADDNL_DELAY ,Holds the additional delay in cycles which should be added to round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " ADDITIONAL_NCR_CYCLES ,Additional NCR wait time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " OVERRIDE_FOR_1_8V_VDD2 ,Maximum override for 1.8V VDD2"
|
|
textline " "
|
|
else
|
|
group.long 0x124++0x1F
|
|
line.long 0x00 "MAX_CURR_OVER_0,Maximum Current Override 0 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " OVERRIDE_FOR_1_8V ,Maximum override for 1.8V VDD1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OVERRIDE_FOR_3_0V ,Maximum override for 3.0V VDD1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OVERRIDE_FOR_3_3V ,Maximum override for 3.3V VDD1"
|
|
line.long 0x04 "MAX_CURR_OVER_HI_0,Maximum Current Override High 0 Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " OVERRIDE_FOR_1_8V_VDD2 ,Maximum override for 1.8V VDD2"
|
|
textline " "
|
|
endif
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "VENDOR_IO_TRIM_CNTRL_0,Vendor I/O Trimmer Control Register"
|
|
sif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 6.--7. " TRIM_SEL_ATEST ,Select analog test signals to send to comp pad" "No used,Input,Output before analog mux,Output after analog mux"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " TRIM_PWRSAVE ,Enables power saving mode by clock gating the unused taps in delay chain" "No,Yes"
|
|
bitfld.long 0x00 3.--4. " SEL_VREF_LEVEL ,Selects Vref voltage level" "VREF_875_MV,VREF_900_MV,VREF_925_MV,VREF_950_MV"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEL_VREG ,Select voltage supply for delay chain present in both Trimmer and DLLPROD value" "Regulated reference voltage,VAUXC"
|
|
bitfld.long 0x00 1. " SEL_VREF ,Select reference voltage for voltage regulator" "Bandgap Voltage Reference,Resistor divider voltage"
|
|
sif cpuis("TEGRAX2")
|
|
else
|
|
endif
|
|
group.long 0x1C0++0x07
|
|
line.long 0x00 "VENDOR_TUNING_CNTRL0_0,Vendor Tuning Control 0 Register"
|
|
bitfld.long 0x00 30. " RD_DATA_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on read data CRC error" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " WR_DATA_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on write CRC error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " CMD_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on cmd CRC error" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RETUNING_REQ_EN_ON_CRC_ERR_DETECTION ,Generates re-tuning request" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TUNING_ERR_EN_ON_CRC_ERR_DETECTION ,Generates tuning error" "Not generated,Generated"
|
|
hexmask.long.byte 0x00 18.--25. 1. " START_TAP_VAL ,Start tap value to be used by tuning"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TAP_VAL_UPDATED_BY_HW ,Software can choose to update the tap value by itself" "Not updated,Updated"
|
|
bitfld.long 0x00 13.--15. " NUM_TUNING_ITERATIONS ,The number of tuning iterations to be used by tuning circuit" "TRIES_40,TRIES_64,TRIES_128,TRIES_192,TRIES_256,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 6.--12. 1. " MUL_M ,Implements a multiplier"
|
|
bitfld.long 0x00 3.--5. " DIV_N ,Implements a divider" "1,2,4,8,16,32,64,128"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TUNING_WORD_SEL ,Selects desired word from 256-bit tuning status bitmap status_word" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "VENDOR_TUNING_CNTRL1_0,Vendor Tuning Control 1 Register"
|
|
bitfld.long 0x04 4.--6. " STEP_SIZE_SDR104_HS200 ,TAP_VAL is incremented by step_size for every tuning iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " STEP_SIZE_SDR50 ,TAP_VAL is incremented by step_size for every tuning iteration" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1C8++0x07
|
|
line.long 0x00 "VENDOR_TUNING_STATUS0_0,Vendor Tuning Status 0 Register"
|
|
line.long 0x04 "VENDOR_TUNING_STATUS1_0,Vendor Tuning Status 1 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PASS_WINDOW_END_BEFORE_FINE_TUNING , End tap value of best PASS window found by scan FSM"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PASS_WINDOW_START_BEFORE_FINE_TUNING ,Start tap value of best PASS window found by scan FSM"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " PASS_WINDOW_END_AFTER_FINE_TUNING ,End tap value of best PASS window after fine tuning"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PASS_WINDOW_START_AFTER_FINE_TUNING ,Start tap value of best PASS window after fine tuning"
|
|
textline " "
|
|
endif
|
|
width 28.
|
|
group.long 0x1D0++0x0F
|
|
line.long 0x00 "VENDOR_CLK_GATE_HYST_CNT_0,Vendor Clock Gating Hysteresis Counter Initial Value"
|
|
bitfld.long 0x00 0.--5. " CLK_COUNT ,CLK count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "VENDOR_PRESET_VAL0_0,Vendor Preset Value Register 0"
|
|
hexmask.long.word 0x04 20.--29. 1. " SDCLK_FREQ_SEL_HIGH_SPEED ,10-bit divider value to generate an SD clock in default speed mode (<50 MHz)"
|
|
hexmask.long.word 0x04 10.--19. 1. " SDCLK_FREQ_SEL_DEFAULT ,10-bit divider value to generate an SD clock in default speed mode (<25 MHz)"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--9. 1. " SDCLK_FREQ_SEL_INIT ,10-bit divider value to generate the desired SD clock frequency during initialization"
|
|
line.long 0x08 "VENDOR_PRESET_VAL1_0,Vendor Preset Value Register 1"
|
|
hexmask.long.word 0x08 20.--29. 1. " SDCLK_FREQ_SEL_SDR50 ,10-bit divider value to generate the SD clock in SDR50 mode"
|
|
hexmask.long.word 0x08 10.--19. 1. " SDCLK_FREQ_SEL_SDR25 ,10-bit divider value to generate the SD clock in SDR25 mode"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--9. 1. " SDCLK_FREQ_SEL_SDR12 ,10-bit divider value to generate the SD clock in SDR12 mode"
|
|
line.long 0x0C "VENDOR_PRESET_VAL2_0,Vendor Preset Value Register 2"
|
|
hexmask.long.word 0x0C 10.--19. 1. " SDCLK_FREQ_SEL_DDR50 ,10-bit divider value to generate the SD clock in DDR50 mode"
|
|
hexmask.long.word 0x0C 0.--9. 1. " SDCLK_FREQ_SEL_SDR104 ,10-bit divider value to generate the SD clock in SDR104 mode"
|
|
sif cpuis("TEGRAX2")
|
|
if (((d.l(ad:0x700B0400+0x1E4))&0x20000000)==0x20000000)
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_E_PBIAS_BUF ,Enables internally generated bias levels for driver PMOS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Select different bias levels for driver PMOS when E_PBIAS_BUF=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_E_PBIAS_BUF ,Enables internally generated bias levels for driver PMOS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
hexmask.long.byte 0x00 20.--26. 1. " COMP_PAD_DRVUP_OVR ,Used to drive DRVUP input of COMP pad"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--18. 1. " COMP_PAD_DRVDN_OVR ,Used to drive DRVDN input of COMP pad"
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Select different bias levels for driver PMOS when E_PBIAS_BUF=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
elif cpuis("TEGRAX1")
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_REG_ON ,Turns ON regulator in comp pad" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 10. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Used to control vref_sel input of COMP pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if (((d.l(ad:0x700B0400+0x1E4))&0x20000000)==0x20000000)
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 29.--30. " PU_PAD_DRV_TYPE ,Pu pad drv type" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " PD_PAD_DRV_TYPE ,Pd pad drv type" "0,1,2,3"
|
|
bitfld.long 0x00 11. " PU_PAD_E_TEST_OUT ,Pu pad E test out" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PD_PAD_E_TEST_OUT ,Pd pad E test out" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " PU_PAD_TEST_SEL ,pu pad test sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PD_PAD_TEST_SEL ,Pd pad test sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,sdmmc2tmc cfg Sdmemcomp vref sel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 29.--30. " PU_PAD_DRV_TYPE ,PU PAD DRV TYPE" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " PD_PAD_DRV_TYPE ,PD PAD DRV TYPE" "0,1,2,3"
|
|
hexmask.long.byte 0x00 20.--26. 1. " CFG_SDMEMCOMP_DRVUP ,SDMMC pads drive up/down control"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--18. 1. " CFG_SDMEMCOMP_DRVDN ,SDMMC pads drive up/down control"
|
|
bitfld.long 0x00 11. " PU_PAD_E_TEST_OUT ,PU PAD E TEST OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PD_PAD_E_TEST_OUT ,PD_PAD_E_TEST_OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " PU_PAD_TEST_SEL ,PU PAD TEST SEL" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PD_PAD_TEST_SEL ,PD PAD TEST SEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,SDMMC2TMC CFG SDMEMCOMP VREF SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long 0x1E4++0x07
|
|
line.long 0x00 "AUTO_CAL_CFG_0,SDMEMCOMP Pad Auto-Calibration Settings"
|
|
bitfld.long 0x00 31. " AUTO_CAL_START ,Calibration state machine" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " AUTO_CAL_OVERRIDE ,AUTOCAL override" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 29. " AUTO_CAL_ENABLE ,AUTOCAL enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " AUTO_CAL_SLW_OVERRIDE ,AUTOCAL slew rate override" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " AUTO_CAL_STEP ,Calibration step interval" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PD_OFFSET ,2's complement offset for pull-down value"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PU_OFFSET ,2's complement offset for pull-up value"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
group.long 0x1E8++0x07
|
|
line.long 0x00 "AUTO_CAL_INTERVAL_0,SDMEMCOMP Pad Calibration Interval"
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "AUTO_CAL_STATUS_0,SDMEMCOMP Pad Calibration Status"
|
|
bitfld.long 0x00 31. " AUTO_CAL_ACTIVE ,Auto cal active" "Inactive,Active"
|
|
hexmask.long.byte 0x00 24.--30. 1. " AUTO_CAL_PULLDOWN_ADJ ,Pulldown code sent to pads"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " AUTO_CAL_PULLUP_ADJ ,Pullup code sent to pads"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PULLDOWN ,Pulldown code generated by auto-calibration"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PULLUP ,Pullup code generated by auto-calibration"
|
|
else
|
|
group.long 0x1E8++0x07
|
|
line.long 0x00 "AUTO_CAL_INTERVAL_0,SDMEMCOMP Pad Calibration Interval"
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "AUTO_CAL_STATUS_0,SDMEMCOMP Pad Calibration Status"
|
|
bitfld.long 0x00 31. " AUTO_CAL_ACTIVE ,Auto cal active" "Inactive,Active"
|
|
hexmask.long.byte 0x00 24.--30. 1. " AUTO_CAL_PULLDOWN_ADJ ,Pulldown code sent to pads"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " AUTO_CAL_PULLUP_ADJ ,Pullup code sent to pads"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PULLDOWN ,Pulldown code generated by auto-calibration"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PULLUP ,Pullup code generated by auto-calibration"
|
|
endif
|
|
sif cpuis("TEGRAX1")
|
|
group.long 0x1F0++0x07
|
|
line.long 0x00 "IO_SPARE_0,Memory Client Interface FIFO Control"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPARE_OUT ,PROD value"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPARE_IN ,PROD value"
|
|
endif
|
|
sif cpuis("TEGRAX2")
|
|
textline " "
|
|
group.long 0x1FC++0x0B
|
|
line.long 0x00 "CIF2AXI_CTRL_0,SD/MMC CIF2AXI Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MC_WRITE_REQ_STREAM_ID ,MC write transaction stream ID"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MC_READ_REQ_STREAM_ID ,MC read transaction stream ID"
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "TZ_DMA_CTRL_0,SD/MMC DMA Requests Security Attribute Control Register"
|
|
bitfld.long 0x00 1. " MC_WRITE_REQ_TZ_ACCESS_EN ,MC_WRITE_REQ_TZ_ACCESS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MC_READ_REQ_TZ_ACCESS_EN ,MC_READ_REQ_TZ_ACCESS enable" "Disabled,Enabled"
|
|
line.long 0x04 "VENDOR_MISC_CNTRL3_0,Misc Vendor Control Register 3"
|
|
bitfld.long 0x04 30. " STOP_TRIM_IN_CLK_DURING_TUNING ,Stops rx clk trimmer and rx FIFOs input clock during tuning" "Not stopped,Stopped"
|
|
bitfld.long 0x04 24.--29. " TUNING_TRIMMER_RECOVERY_TIME ,TUNING TRIMMER RECOVERY TIME" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " E_DIFF_DQ , Diff/Vref rx selection for DAT[7:0]"
|
|
bitfld.long 0x04 4. " E_DIFF_CMD ,Diff/Vref rx selection for CMD" "Stopped,Not stopped"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DAT_OE_POSTAMBLE_EN ,DAT pads output driver one cycle after disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " DAT_OE_PREAMBLE_EN ,DAT pads output driver one cycle before enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CMD_OE_POSTAMBLE_EN ,CMD pad output driver one cycle after disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CMD_OE_PREAMBLE_EN ,CMD pad output driver one cycle before enable" "Disabled,Enabled"
|
|
group.long 0x20C++0x07
|
|
line.long 0x00 "VENDOR_MISC_CNTRL4_0,Misc Vendor Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " SDMMC_SPARE3 ,Spare register bits with reset value of 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDMMC_SPARE2 ,Spare register bits with reset value of 0"
|
|
else
|
|
group.long 0x1F4++0x07
|
|
line.long 0x00 "SDMMC_MCCIF_FIFOCTRL_0,Memory Client Interface FIFO Control"
|
|
bitfld.long 0x00 20. " SDMMC_RCLK_OVR_MODE ,SDMMC RCLK OVR MODE" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SDMMC_WCLK_OVR_MODE ,SDMMC WCLK OVR MODE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SDMMC_CCLK_OVERRIDE ,SDMMC CCLK OVERRIDE" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SDMMC_RCLK_OVERRIDE ,SDMMC RCLK OVERRIDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SDMMC_WCLK_OVERRIDE ,SDMMC WCLK OVERRIDE" "Disabled,Enabled"
|
|
line.long 0x04 "TIMEOUT_WCOAL_SDMMC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SDMMCW_WCOAL_TMVAL ,SDMMCW WCOAL TMVAL"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "SDMMC-3B"
|
|
base ad:0x700B3400
|
|
tree.open "Standard Registers"
|
|
width 27.
|
|
sif !cpuis("TEGRAX1")&&!cpuis("TEGRAX2")
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "PSR,Present State Register"
|
|
bitfld.long 0x00 25.--28. " DAT_7_4_LINE_LEVEL ,This status reflects the DAT[7:4] lines state for debug" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif !cpuis("TEGRAX2")
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " BOOT_ACK_ERR ,Boot ack status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " BOOT_ACK_TIMEOUT_ERR ,Boot Ack is not received" "Not occurred,Occurred"
|
|
line.long 0x04 "ISTAER,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor Ack_Timeout and Ack error status" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
line.long 0x08 "ISIGR,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor specification error" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
else
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "INTERRUPT_STATUS_0,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " BOOT_ACK_ERR ,Boot ack status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " BOOT_ACK_TIMEOUT_ERR ,Boot Ack is not received" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BUFFER_READ_READY ,Buffer read ready" "NO_INT,GEN_INT"
|
|
line.long 0x04 "INTERRUPT_STATUS_ENABLE_0,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor Ack_Timeout and Ack error status" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BUFFER_READ_READY ,Buffer read ready" "Disabled,Enabled"
|
|
line.long 0x08 "INTERRUPT_SIGNAL_ENABLE_0,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor specification error" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
textline " "
|
|
bitfld.long 0x08 5. " BUFFER_READ_READY ,Buffer read ready" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("TEGRAX1")
|
|
group.long 0x3C++0x0B
|
|
line.long 0x00 "AUTO_CMD12_ERR_STATUS_0,Auto cmd12 err status 0"
|
|
bitfld.long 0x00 16.--18. " UHS_MODE_SEL ,UHS Mode Select" "LEGACY,HIGH,SDR50,SDR104,DDR50,HS400,?..."
|
|
endif
|
|
sif !cpuis("TEGRAX2")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FER,Force Event Register"
|
|
bitfld.long 0x00 30.--31. " VENDOR_SPECIFIC_ERR_STATUS ,Vendor specific error status" "No effect,ACK_TIMEOUT_ERR,ACK_ERR,Both"
|
|
endif
|
|
tree.end
|
|
tree.open "Vendor-Specific Registers"
|
|
width 27.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "VENDOR_CLOCK_CNTRL_0,Vendor Clock Control Register"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 29. " DIFF_CLK_SEL ,Selects differential CLK and DQS" "0,1"
|
|
bitfld.long 0x00 24.--28. " TRIM_VAL ,Tap value for output data path trimmer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " TAP_VAL ,Tap value for input data path trimmer"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BASE_CLK_FREQ ,SD/MMC clock frequency"
|
|
textline " "
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 6. " LEGACY_CLKEN_OVERRIDE ,Override for sdmmc_legacy_g_clk clken" "Normal,Override"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " SDR50_TUNING_OVERRIDE ,Override the SDR50_TUNING capabilities bit" "Normal,Override"
|
|
textline " "
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 4. " UHS2_CAPABILITY_OVERRIDE ,Override the UHS-II capabilities bit" "Normal,Override"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " PADPIPE_CLKEN_OVERRIDE ,Override for padmacro and pipemacro clken" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SPI_MODE_CLKEN_OVERRIDE ,Override for CLKEN during SPI_MODE during sw_reset" "Normal,Override"
|
|
bitfld.long 0x00 1. " INPUT_IO_CLK ,Input I/O clock" "Feedback,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SDMMC_CLK ,Set when sdmmc_clk is supplied by the CAR module prior to sdmmc_clk switch OFF" "Disabled,Enabled"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
if (((d.l(ad:0x700B3400+0x104))&0x40000000)==0x40000000)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 31. " ENHANCED_STROBE_MODE ,Enables enhanced strobe mode in HS400/HS667 mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT ,Uses TMCLK data timeout counter for generating wr_crc_status data-timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " USE_NCRC_FOR_WR_CRC_STATUS_TIMEOUT_VAL ,Uses data timeout value as wr CRC/NCRC status timeout value" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " USE_TMCLK_FOR_DATA_TIMEOUT ,Uses TMCLK data timeout counter for generating legacy data timeout error" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,This register field is used to load wait_cycles counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,Busy should be sampled using clock instead DQS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 23. " ALLOW_CARD_CLK_STALLS_IN_WR ,Allows card clock stopping during transfer of data within a block in HIGH SPEED DDR/HS400 writes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EMMC_IOBRICK_CLK_DATA ,Used to drive AP_CLK and AN_CLK input of iobrick" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " QUALIFY_WITH_RD_DATA_VLD ,Async FIFOs in both cmd_in and dat_in paths in padmacro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,TUNING_SYS interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8.--11. " TUNING_ASYNC_FIFO_ADDNL_DELAY ,DATA/CMD IB path uses async FIFO which contributes additional delay to CMD/RESP and WDATA/CRC token round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,SD_BUS_POWER_ON_OFF interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,VOLT_SWITCH interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,TUNING_SYS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IO_TRIM_BYPASS ,Override bit for selecting between core trimmer and I/O trimmer in IB clock path" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 31. " ENHANCED_STROBE_MODE ,Enables enhanced strobe mode in HS400/HS667 mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT , Uses TMCLK data timeout counter for generating wr_crc_status data-timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " USE_TMCLK_FOR_DATA_TIMEOUT ,Uses TMCLK data timeout counter for generating legacy data timeout error" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,This register field is used to load wait_cycles counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,Busy should be sampled using clock instead DQS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 23. " ALLOW_CARD_CLK_STALLS_IN_WR ,allows card clock stopping during transfer of data within a block in HIGH SPEED DDR/HS400 writes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EMMC_IOBRICK_CLK_DATA ,Used to drive AP_CLK and AN_CLK input of iobrick" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " QUALIFY_WITH_RD_DATA_VLD ,Async FIFOs in both cmd_in and dat_in paths in padmacro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,TUNING_SYS interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8.--11. " TUNING_ASYNC_FIFO_ADDNL_DELAY ,DATA/CMD IB path uses async FIFO which contributes additional delay to CMD/RESP and WDATA/CRC token round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,SD_BUS_POWER_ON_OFF interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,VOLT_SWITCH interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,TUNING_SYS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IO_TRIM_BYPASS ,Override bit for selecting between core trimmer and I/O trimmer in IB clock path" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "VENDOR_ERR_INTR_STATUS_0,Legacy Interrupt Status Register"
|
|
bitfld.long 0x00 18. " SDMMC_LEGACY_CTLR_IDLE ,Indicates legacy SD interface controller is idle" "0,1"
|
|
bitfld.long 0x00 17. " READ_DATA_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " WRITE_CRC_STATUS_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
bitfld.long 0x00 15. " WRITE_BUSY_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RESP_BUSY_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
bitfld.long 0x00 13. " SPI_WRITE_BUSY_TIMEOUT ,SPI_WRITE_BUSY timeout" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SPI_RX_START_TOKEN_TIMEOUT ,SPI_RX_START_TOKEN timeout" "0,1"
|
|
bitfld.long 0x00 5.--8. " SPI_DAT_ERR_TOKEN ,Data Error Token while read from card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SPI_DAT_RESPONSE ,Data Response while write to card" ",,,,,DATA_ACCEPTED,,,,,,CRC_ERR,,WRITE_ERR,?..."
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER was changed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN was changed" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,CMD19 was issued while EXECUTE_TUNING was set" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10C++0x17
|
|
line.long 0x00 "VENDOR_CAP_OVERRIDES_0,Capabilities Override Bits"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
sif !cpuis("TEGRAX2")
|
|
bitfld.long 0x00 28. " CMD_QUEUING_MODE_EN ,Useful for eMMC5.x devices which support CMD queuing" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--13. " DQS_TRIM_VAL ,Tap value for incoming DQS path trimmer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DRV_LPBK_CLK_ON_CMD_LINE ,Loopback trimmed clock will be driven onto cmd line" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " VOLTAGE_3_3_V_SUPPORT_OVERRIDE ,Voltage support 3_3_V override" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " VOLTAGE_3_0_V_SUPPORT_OVERRIDE ,Voltage support 3_0_V override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VOLTAGE_1_8_V_SUPPORT_OVERRIDE ,Voltage support 1_8_V override" "Disabled,Enabled"
|
|
line.long 0x04 "VENDOR_BOOT_CNTRL_0,Vendor Boot Control Register"
|
|
bitfld.long 0x04 1. " BOOT_ACK ,Used to support Boot Option in MMC 4.3 version cards" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " BOOT ,Boot Option 1" "Disabled,Enabled"
|
|
line.long 0x08 "VENDOR_BOOT_ACK_TIMEOUT_0,Vendor Boot Acknowledgement Timeout Register"
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " VALUE ,Boot Acknowledgment timeout value"
|
|
line.long 0x0C "VENDOR_BOOT_DAT_TIMEOUT_0,Boot Data Timeout Register"
|
|
hexmask.long 0x0C 0.--24. 1. " VALUE ,Boot Data timeout value"
|
|
line.long 0x10 "VENDOR_DEBOUNCE_COUNT_0,Debounce Counter Value Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " VALUE ,The number of 32KHz clock cycles is programmed to meet the debounce period of the card slot"
|
|
line.long 0x14 "VENDOR_MISC_CNTRL_0,Miscellaneous Vendor Control Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " SDMMC_SPARE_1 ,Spare register bits with reset value of 1"
|
|
hexmask.long.word 0x14 1.--15. 1. " SDMMC_SPARE_0 ,Spare register bits with reset value of 0x40"
|
|
textline " "
|
|
bitfld.long 0x14 0. " ERASE_TIMEOUT_LIMIT ,Erase timeout value" "Finite,Infinite"
|
|
sif cpuis("TEGRAX2")
|
|
group.long 0x124++0x1F
|
|
line.long 0x00 "VENDOR_MISC_CNTRL1_0,Misc Vendor Control Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " OVERRIDE_FOR_1_8V ,Maximum override for 1.8V VDD1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OVERRIDE_FOR_3_0V ,Maximum override for 3.0V VDD1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OVERRIDE_FOR_3_3V ,Maximum override for 3.3V VDD1"
|
|
line.long 0x04 "VENDOR_MISC_CNTRL2_0,Misc Vendor Control Register 2"
|
|
bitfld.long 0x04 31. " VGPIO_MODE_EN ,VGPIO_MODE enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " SDMMC_CLK_OVR_ON ,Master clk en Override bit for all SLCGs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " SD_CARD_DETECT_STATUS_N ,SD card detect status n" "Detected,Not detected"
|
|
bitfld.long 0x04 28. " SD_CARD_WP_STATUS ,SD card wp status" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 27. " CMD_TFIFO_HOT_RESET ,CMD TFIFO hot reset" "No reset,Reset"
|
|
bitfld.long 0x04 26. " DAT_TFIFO_HOT_RESET ,DAT TFIFO hot reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ADMA3_CLKEN_OVERRIDE ,Override for sdmmc_adma3_g_clk clken" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x04 22. " ADMA3_DESC_PREFETCH_EN ,ADMA3 descriptors prefetch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " ADMA2_DESC_PREFETCH_EN ,ADMA2 descriptors prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--19. " DATA_TIMEOUT_VAL_MULTIPLIER ,Data timeout value multiplier" "No multiplier,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " DAT_TUNING_ASYNC_FIFO_ADDNL_DELAY ,Holds the additional delay in cycles which should be added to round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " ADDITIONAL_NCR_CYCLES ,Additional NCR wait time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " OVERRIDE_FOR_1_8V_VDD2 ,Maximum override for 1.8V VDD2"
|
|
textline " "
|
|
else
|
|
group.long 0x124++0x1F
|
|
line.long 0x00 "MAX_CURR_OVER_0,Maximum Current Override 0 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " OVERRIDE_FOR_1_8V ,Maximum override for 1.8V VDD1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OVERRIDE_FOR_3_0V ,Maximum override for 3.0V VDD1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OVERRIDE_FOR_3_3V ,Maximum override for 3.3V VDD1"
|
|
line.long 0x04 "MAX_CURR_OVER_HI_0,Maximum Current Override High 0 Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " OVERRIDE_FOR_1_8V_VDD2 ,Maximum override for 1.8V VDD2"
|
|
textline " "
|
|
endif
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "VENDOR_IO_TRIM_CNTRL_0,Vendor I/O Trimmer Control Register"
|
|
sif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 6.--7. " TRIM_SEL_ATEST ,Select analog test signals to send to comp pad" "No used,Input,Output before analog mux,Output after analog mux"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " TRIM_PWRSAVE ,Enables power saving mode by clock gating the unused taps in delay chain" "No,Yes"
|
|
bitfld.long 0x00 3.--4. " SEL_VREF_LEVEL ,Selects Vref voltage level" "VREF_875_MV,VREF_900_MV,VREF_925_MV,VREF_950_MV"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEL_VREG ,Select voltage supply for delay chain present in both Trimmer and DLLPROD value" "Regulated reference voltage,VAUXC"
|
|
bitfld.long 0x00 1. " SEL_VREF ,Select reference voltage for voltage regulator" "Bandgap Voltage Reference,Resistor divider voltage"
|
|
sif cpuis("TEGRAX2")
|
|
else
|
|
endif
|
|
group.long 0x1C0++0x07
|
|
line.long 0x00 "VENDOR_TUNING_CNTRL0_0,Vendor Tuning Control 0 Register"
|
|
bitfld.long 0x00 30. " RD_DATA_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on read data CRC error" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " WR_DATA_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on write CRC error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " CMD_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on cmd CRC error" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RETUNING_REQ_EN_ON_CRC_ERR_DETECTION ,Generates re-tuning request" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TUNING_ERR_EN_ON_CRC_ERR_DETECTION ,Generates tuning error" "Not generated,Generated"
|
|
hexmask.long.byte 0x00 18.--25. 1. " START_TAP_VAL ,Start tap value to be used by tuning"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TAP_VAL_UPDATED_BY_HW ,Software can choose to update the tap value by itself" "Not updated,Updated"
|
|
bitfld.long 0x00 13.--15. " NUM_TUNING_ITERATIONS ,The number of tuning iterations to be used by tuning circuit" "TRIES_40,TRIES_64,TRIES_128,TRIES_192,TRIES_256,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 6.--12. 1. " MUL_M ,Implements a multiplier"
|
|
bitfld.long 0x00 3.--5. " DIV_N ,Implements a divider" "1,2,4,8,16,32,64,128"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TUNING_WORD_SEL ,Selects desired word from 256-bit tuning status bitmap status_word" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "VENDOR_TUNING_CNTRL1_0,Vendor Tuning Control 1 Register"
|
|
bitfld.long 0x04 4.--6. " STEP_SIZE_SDR104_HS200 ,TAP_VAL is incremented by step_size for every tuning iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " STEP_SIZE_SDR50 ,TAP_VAL is incremented by step_size for every tuning iteration" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1C8++0x07
|
|
line.long 0x00 "VENDOR_TUNING_STATUS0_0,Vendor Tuning Status 0 Register"
|
|
line.long 0x04 "VENDOR_TUNING_STATUS1_0,Vendor Tuning Status 1 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PASS_WINDOW_END_BEFORE_FINE_TUNING , End tap value of best PASS window found by scan FSM"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PASS_WINDOW_START_BEFORE_FINE_TUNING ,Start tap value of best PASS window found by scan FSM"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " PASS_WINDOW_END_AFTER_FINE_TUNING ,End tap value of best PASS window after fine tuning"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PASS_WINDOW_START_AFTER_FINE_TUNING ,Start tap value of best PASS window after fine tuning"
|
|
textline " "
|
|
endif
|
|
width 28.
|
|
group.long 0x1D0++0x0F
|
|
line.long 0x00 "VENDOR_CLK_GATE_HYST_CNT_0,Vendor Clock Gating Hysteresis Counter Initial Value"
|
|
bitfld.long 0x00 0.--5. " CLK_COUNT ,CLK count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "VENDOR_PRESET_VAL0_0,Vendor Preset Value Register 0"
|
|
hexmask.long.word 0x04 20.--29. 1. " SDCLK_FREQ_SEL_HIGH_SPEED ,10-bit divider value to generate an SD clock in default speed mode (<50 MHz)"
|
|
hexmask.long.word 0x04 10.--19. 1. " SDCLK_FREQ_SEL_DEFAULT ,10-bit divider value to generate an SD clock in default speed mode (<25 MHz)"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--9. 1. " SDCLK_FREQ_SEL_INIT ,10-bit divider value to generate the desired SD clock frequency during initialization"
|
|
line.long 0x08 "VENDOR_PRESET_VAL1_0,Vendor Preset Value Register 1"
|
|
hexmask.long.word 0x08 20.--29. 1. " SDCLK_FREQ_SEL_SDR50 ,10-bit divider value to generate the SD clock in SDR50 mode"
|
|
hexmask.long.word 0x08 10.--19. 1. " SDCLK_FREQ_SEL_SDR25 ,10-bit divider value to generate the SD clock in SDR25 mode"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--9. 1. " SDCLK_FREQ_SEL_SDR12 ,10-bit divider value to generate the SD clock in SDR12 mode"
|
|
line.long 0x0C "VENDOR_PRESET_VAL2_0,Vendor Preset Value Register 2"
|
|
hexmask.long.word 0x0C 10.--19. 1. " SDCLK_FREQ_SEL_DDR50 ,10-bit divider value to generate the SD clock in DDR50 mode"
|
|
hexmask.long.word 0x0C 0.--9. 1. " SDCLK_FREQ_SEL_SDR104 ,10-bit divider value to generate the SD clock in SDR104 mode"
|
|
sif cpuis("TEGRAX2")
|
|
if (((d.l(ad:0x700B3400+0x1E4))&0x20000000)==0x20000000)
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_E_PBIAS_BUF ,Enables internally generated bias levels for driver PMOS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Select different bias levels for driver PMOS when E_PBIAS_BUF=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_E_PBIAS_BUF ,Enables internally generated bias levels for driver PMOS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
hexmask.long.byte 0x00 20.--26. 1. " COMP_PAD_DRVUP_OVR ,Used to drive DRVUP input of COMP pad"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--18. 1. " COMP_PAD_DRVDN_OVR ,Used to drive DRVDN input of COMP pad"
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Select different bias levels for driver PMOS when E_PBIAS_BUF=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
elif cpuis("TEGRAX1")
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_REG_ON ,Turns ON regulator in comp pad" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 10. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Used to control vref_sel input of COMP pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if (((d.l(ad:0x700B3400+0x1E4))&0x20000000)==0x20000000)
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 29.--30. " PU_PAD_DRV_TYPE ,Pu pad drv type" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " PD_PAD_DRV_TYPE ,Pd pad drv type" "0,1,2,3"
|
|
bitfld.long 0x00 11. " PU_PAD_E_TEST_OUT ,Pu pad E test out" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PD_PAD_E_TEST_OUT ,Pd pad E test out" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " PU_PAD_TEST_SEL ,pu pad test sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PD_PAD_TEST_SEL ,Pd pad test sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,sdmmc2tmc cfg Sdmemcomp vref sel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 29.--30. " PU_PAD_DRV_TYPE ,PU PAD DRV TYPE" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " PD_PAD_DRV_TYPE ,PD PAD DRV TYPE" "0,1,2,3"
|
|
hexmask.long.byte 0x00 20.--26. 1. " CFG_SDMEMCOMP_DRVUP ,SDMMC pads drive up/down control"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--18. 1. " CFG_SDMEMCOMP_DRVDN ,SDMMC pads drive up/down control"
|
|
bitfld.long 0x00 11. " PU_PAD_E_TEST_OUT ,PU PAD E TEST OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PD_PAD_E_TEST_OUT ,PD_PAD_E_TEST_OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " PU_PAD_TEST_SEL ,PU PAD TEST SEL" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PD_PAD_TEST_SEL ,PD PAD TEST SEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,SDMMC2TMC CFG SDMEMCOMP VREF SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long 0x1E4++0x07
|
|
line.long 0x00 "AUTO_CAL_CFG_0,SDMEMCOMP Pad Auto-Calibration Settings"
|
|
bitfld.long 0x00 31. " AUTO_CAL_START ,Calibration state machine" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " AUTO_CAL_OVERRIDE ,AUTOCAL override" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 29. " AUTO_CAL_ENABLE ,AUTOCAL enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " AUTO_CAL_SLW_OVERRIDE ,AUTOCAL slew rate override" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " AUTO_CAL_STEP ,Calibration step interval" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PD_OFFSET ,2's complement offset for pull-down value"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PU_OFFSET ,2's complement offset for pull-up value"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
group.long 0x1E8++0x07
|
|
line.long 0x00 "AUTO_CAL_INTERVAL_0,SDMEMCOMP Pad Calibration Interval"
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "AUTO_CAL_STATUS_0,SDMEMCOMP Pad Calibration Status"
|
|
bitfld.long 0x00 31. " AUTO_CAL_ACTIVE ,Auto cal active" "Inactive,Active"
|
|
hexmask.long.byte 0x00 24.--30. 1. " AUTO_CAL_PULLDOWN_ADJ ,Pulldown code sent to pads"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " AUTO_CAL_PULLUP_ADJ ,Pullup code sent to pads"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PULLDOWN ,Pulldown code generated by auto-calibration"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PULLUP ,Pullup code generated by auto-calibration"
|
|
else
|
|
group.long 0x1E8++0x07
|
|
line.long 0x00 "AUTO_CAL_INTERVAL_0,SDMEMCOMP Pad Calibration Interval"
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "AUTO_CAL_STATUS_0,SDMEMCOMP Pad Calibration Status"
|
|
bitfld.long 0x00 31. " AUTO_CAL_ACTIVE ,Auto cal active" "Inactive,Active"
|
|
hexmask.long.byte 0x00 24.--30. 1. " AUTO_CAL_PULLDOWN_ADJ ,Pulldown code sent to pads"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " AUTO_CAL_PULLUP_ADJ ,Pullup code sent to pads"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PULLDOWN ,Pulldown code generated by auto-calibration"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PULLUP ,Pullup code generated by auto-calibration"
|
|
endif
|
|
sif cpuis("TEGRAX1")
|
|
group.long 0x1F0++0x07
|
|
line.long 0x00 "IO_SPARE_0,Memory Client Interface FIFO Control"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPARE_OUT ,PROD value"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPARE_IN ,PROD value"
|
|
endif
|
|
sif cpuis("TEGRAX2")
|
|
textline " "
|
|
group.long 0x1FC++0x0B
|
|
line.long 0x00 "CIF2AXI_CTRL_0,SD/MMC CIF2AXI Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MC_WRITE_REQ_STREAM_ID ,MC write transaction stream ID"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MC_READ_REQ_STREAM_ID ,MC read transaction stream ID"
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "TZ_DMA_CTRL_0,SD/MMC DMA Requests Security Attribute Control Register"
|
|
bitfld.long 0x00 1. " MC_WRITE_REQ_TZ_ACCESS_EN ,MC_WRITE_REQ_TZ_ACCESS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MC_READ_REQ_TZ_ACCESS_EN ,MC_READ_REQ_TZ_ACCESS enable" "Disabled,Enabled"
|
|
line.long 0x04 "VENDOR_MISC_CNTRL3_0,Misc Vendor Control Register 3"
|
|
bitfld.long 0x04 30. " STOP_TRIM_IN_CLK_DURING_TUNING ,Stops rx clk trimmer and rx FIFOs input clock during tuning" "Not stopped,Stopped"
|
|
bitfld.long 0x04 24.--29. " TUNING_TRIMMER_RECOVERY_TIME ,TUNING TRIMMER RECOVERY TIME" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " E_DIFF_DQ , Diff/Vref rx selection for DAT[7:0]"
|
|
bitfld.long 0x04 4. " E_DIFF_CMD ,Diff/Vref rx selection for CMD" "Stopped,Not stopped"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DAT_OE_POSTAMBLE_EN ,DAT pads output driver one cycle after disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " DAT_OE_PREAMBLE_EN ,DAT pads output driver one cycle before enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CMD_OE_POSTAMBLE_EN ,CMD pad output driver one cycle after disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CMD_OE_PREAMBLE_EN ,CMD pad output driver one cycle before enable" "Disabled,Enabled"
|
|
group.long 0x20C++0x07
|
|
line.long 0x00 "VENDOR_MISC_CNTRL4_0,Misc Vendor Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " SDMMC_SPARE3 ,Spare register bits with reset value of 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDMMC_SPARE2 ,Spare register bits with reset value of 0"
|
|
else
|
|
group.long 0x1F4++0x07
|
|
line.long 0x00 "SDMMC_MCCIF_FIFOCTRL_0,Memory Client Interface FIFO Control"
|
|
bitfld.long 0x00 20. " SDMMC_RCLK_OVR_MODE ,SDMMC RCLK OVR MODE" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SDMMC_WCLK_OVR_MODE ,SDMMC WCLK OVR MODE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SDMMC_CCLK_OVERRIDE ,SDMMC CCLK OVERRIDE" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SDMMC_RCLK_OVERRIDE ,SDMMC RCLK OVERRIDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SDMMC_WCLK_OVERRIDE ,SDMMC WCLK OVERRIDE" "Disabled,Enabled"
|
|
line.long 0x04 "TIMEOUT_WCOAL_SDMMC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SDMMCW_WCOAL_TMVAL ,SDMMCW WCOAL TMVAL"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "SDMMC-4"
|
|
base ad:0x700B0600
|
|
tree.open "Standard Registers"
|
|
width 27.
|
|
sif !cpuis("TEGRAX1")&&!cpuis("TEGRAX2")
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "PSR,Present State Register"
|
|
bitfld.long 0x00 25.--28. " DAT_7_4_LINE_LEVEL ,This status reflects the DAT[7:4] lines state for debug" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif !cpuis("TEGRAX2")
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " BOOT_ACK_ERR ,Boot ack status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " BOOT_ACK_TIMEOUT_ERR ,Boot Ack is not received" "Not occurred,Occurred"
|
|
line.long 0x04 "ISTAER,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor Ack_Timeout and Ack error status" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
line.long 0x08 "ISIGR,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor specification error" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
else
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "INTERRUPT_STATUS_0,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " BOOT_ACK_ERR ,Boot ack status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " BOOT_ACK_TIMEOUT_ERR ,Boot Ack is not received" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BUFFER_READ_READY ,Buffer read ready" "NO_INT,GEN_INT"
|
|
line.long 0x04 "INTERRUPT_STATUS_ENABLE_0,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor Ack_Timeout and Ack error status" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BUFFER_READ_READY ,Buffer read ready" "Disabled,Enabled"
|
|
line.long 0x08 "INTERRUPT_SIGNAL_ENABLE_0,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor specification error" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
textline " "
|
|
bitfld.long 0x08 5. " BUFFER_READ_READY ,Buffer read ready" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("TEGRAX1")
|
|
group.long 0x3C++0x0B
|
|
line.long 0x00 "AUTO_CMD12_ERR_STATUS_0,Auto cmd12 err status 0"
|
|
bitfld.long 0x00 16.--18. " UHS_MODE_SEL ,UHS Mode Select" "LEGACY,HIGH,SDR50,SDR104,DDR50,HS400,?..."
|
|
endif
|
|
sif !cpuis("TEGRAX2")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FER,Force Event Register"
|
|
bitfld.long 0x00 30.--31. " VENDOR_SPECIFIC_ERR_STATUS ,Vendor specific error status" "No effect,ACK_TIMEOUT_ERR,ACK_ERR,Both"
|
|
endif
|
|
tree.end
|
|
tree.open "Vendor-Specific Registers"
|
|
width 27.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "VENDOR_CLOCK_CNTRL_0,Vendor Clock Control Register"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 29. " DIFF_CLK_SEL ,Selects differential CLK and DQS" "0,1"
|
|
bitfld.long 0x00 24.--28. " TRIM_VAL ,Tap value for output data path trimmer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " TAP_VAL ,Tap value for input data path trimmer"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BASE_CLK_FREQ ,SD/MMC clock frequency"
|
|
textline " "
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 6. " LEGACY_CLKEN_OVERRIDE ,Override for sdmmc_legacy_g_clk clken" "Normal,Override"
|
|
textline " "
|
|
endif
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 4. " UHS2_CAPABILITY_OVERRIDE ,Override the UHS-II capabilities bit" "Normal,Override"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " PADPIPE_CLKEN_OVERRIDE ,Override for padmacro and pipemacro clken" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SPI_MODE_CLKEN_OVERRIDE ,Override for CLKEN during SPI_MODE during sw_reset" "Normal,Override"
|
|
bitfld.long 0x00 1. " INPUT_IO_CLK ,Input I/O clock" "Feedback,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SDMMC_CLK ,Set when sdmmc_clk is supplied by the CAR module prior to sdmmc_clk switch OFF" "Disabled,Enabled"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
if (((d.l(ad:0x700B0600+0x104))&0x40000000)==0x40000000)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 31. " ENHANCED_STROBE_MODE ,Enables enhanced strobe mode in HS400/HS667 mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT ,Uses TMCLK data timeout counter for generating wr_crc_status data-timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " USE_NCRC_FOR_WR_CRC_STATUS_TIMEOUT_VAL ,Uses data timeout value as wr CRC/NCRC status timeout value" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " USE_TMCLK_FOR_DATA_TIMEOUT ,Uses TMCLK data timeout counter for generating legacy data timeout error" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,This register field is used to load wait_cycles counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,Busy should be sampled using clock instead DQS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 23. " ALLOW_CARD_CLK_STALLS_IN_WR ,Allows card clock stopping during transfer of data within a block in HIGH SPEED DDR/HS400 writes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EMMC_IOBRICK_CLK_DATA ,Used to drive AP_CLK and AN_CLK input of iobrick" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " QUALIFY_WITH_RD_DATA_VLD ,Async FIFOs in both cmd_in and dat_in paths in padmacro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,TUNING_SYS interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8.--11. " TUNING_ASYNC_FIFO_ADDNL_DELAY ,DATA/CMD IB path uses async FIFO which contributes additional delay to CMD/RESP and WDATA/CRC token round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,SD_BUS_POWER_ON_OFF interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,VOLT_SWITCH interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,TUNING_SYS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IO_TRIM_BYPASS ,Override bit for selecting between core trimmer and I/O trimmer in IB clock path" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 31. " ENHANCED_STROBE_MODE ,Enables enhanced strobe mode in HS400/HS667 mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT , Uses TMCLK data timeout counter for generating wr_crc_status data-timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " USE_TMCLK_FOR_DATA_TIMEOUT ,Uses TMCLK data timeout counter for generating legacy data timeout error" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,This register field is used to load wait_cycles counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,Busy should be sampled using clock instead DQS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 23. " ALLOW_CARD_CLK_STALLS_IN_WR ,allows card clock stopping during transfer of data within a block in HIGH SPEED DDR/HS400 writes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EMMC_IOBRICK_CLK_DATA ,Used to drive AP_CLK and AN_CLK input of iobrick" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " QUALIFY_WITH_RD_DATA_VLD ,Async FIFOs in both cmd_in and dat_in paths in padmacro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,TUNING_SYS interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8.--11. " TUNING_ASYNC_FIFO_ADDNL_DELAY ,DATA/CMD IB path uses async FIFO which contributes additional delay to CMD/RESP and WDATA/CRC token round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,SD_BUS_POWER_ON_OFF interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,VOLT_SWITCH interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,TUNING_SYS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IO_TRIM_BYPASS ,Override bit for selecting between core trimmer and I/O trimmer in IB clock path" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "VENDOR_ERR_INTR_STATUS_0,Legacy Interrupt Status Register"
|
|
bitfld.long 0x00 18. " SDMMC_LEGACY_CTLR_IDLE ,Indicates legacy SD interface controller is idle" "0,1"
|
|
bitfld.long 0x00 17. " READ_DATA_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " WRITE_CRC_STATUS_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
bitfld.long 0x00 15. " WRITE_BUSY_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RESP_BUSY_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
bitfld.long 0x00 13. " SPI_WRITE_BUSY_TIMEOUT ,SPI_WRITE_BUSY timeout" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SPI_RX_START_TOKEN_TIMEOUT ,SPI_RX_START_TOKEN timeout" "0,1"
|
|
bitfld.long 0x00 5.--8. " SPI_DAT_ERR_TOKEN ,Data Error Token while read from card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SPI_DAT_RESPONSE ,Data Response while write to card" ",,,,,DATA_ACCEPTED,,,,,,CRC_ERR,,WRITE_ERR,?..."
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER was changed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN was changed" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,CMD19 was issued while EXECUTE_TUNING was set" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10C++0x17
|
|
line.long 0x00 "VENDOR_CAP_OVERRIDES_0,Capabilities Override Bits"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
sif !cpuis("TEGRAX2")
|
|
bitfld.long 0x00 28. " CMD_QUEUING_MODE_EN ,Useful for eMMC5.x devices which support CMD queuing" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--13. " DQS_TRIM_VAL ,Tap value for incoming DQS path trimmer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DRV_LPBK_CLK_ON_CMD_LINE ,Loopback trimmed clock will be driven onto cmd line" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " VOLTAGE_3_3_V_SUPPORT_OVERRIDE ,Voltage support 3_3_V override" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " VOLTAGE_3_0_V_SUPPORT_OVERRIDE ,Voltage support 3_0_V override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VOLTAGE_1_8_V_SUPPORT_OVERRIDE ,Voltage support 1_8_V override" "Disabled,Enabled"
|
|
line.long 0x04 "VENDOR_BOOT_CNTRL_0,Vendor Boot Control Register"
|
|
bitfld.long 0x04 1. " BOOT_ACK ,Used to support Boot Option in MMC 4.3 version cards" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " BOOT ,Boot Option 1" "Disabled,Enabled"
|
|
line.long 0x08 "VENDOR_BOOT_ACK_TIMEOUT_0,Vendor Boot Acknowledgement Timeout Register"
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " VALUE ,Boot Acknowledgment timeout value"
|
|
line.long 0x0C "VENDOR_BOOT_DAT_TIMEOUT_0,Boot Data Timeout Register"
|
|
hexmask.long 0x0C 0.--24. 1. " VALUE ,Boot Data timeout value"
|
|
line.long 0x10 "VENDOR_DEBOUNCE_COUNT_0,Debounce Counter Value Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " VALUE ,The number of 32KHz clock cycles is programmed to meet the debounce period of the card slot"
|
|
line.long 0x14 "VENDOR_MISC_CNTRL_0,Miscellaneous Vendor Control Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " SDMMC_SPARE_1 ,Spare register bits with reset value of 1"
|
|
hexmask.long.word 0x14 1.--15. 1. " SDMMC_SPARE_0 ,Spare register bits with reset value of 0x40"
|
|
textline " "
|
|
bitfld.long 0x14 0. " ERASE_TIMEOUT_LIMIT ,Erase timeout value" "Finite,Infinite"
|
|
sif cpuis("TEGRAX2")
|
|
group.long 0x124++0x1F
|
|
line.long 0x00 "VENDOR_MISC_CNTRL1_0,Misc Vendor Control Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " OVERRIDE_FOR_1_8V ,Maximum override for 1.8V VDD1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OVERRIDE_FOR_3_0V ,Maximum override for 3.0V VDD1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OVERRIDE_FOR_3_3V ,Maximum override for 3.3V VDD1"
|
|
line.long 0x04 "VENDOR_MISC_CNTRL2_0,Misc Vendor Control Register 2"
|
|
bitfld.long 0x04 31. " VGPIO_MODE_EN ,VGPIO_MODE enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " SDMMC_CLK_OVR_ON ,Master clk en Override bit for all SLCGs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " SD_CARD_DETECT_STATUS_N ,SD card detect status n" "Detected,Not detected"
|
|
bitfld.long 0x04 28. " SD_CARD_WP_STATUS ,SD card wp status" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 27. " CMD_TFIFO_HOT_RESET ,CMD TFIFO hot reset" "No reset,Reset"
|
|
bitfld.long 0x04 26. " DAT_TFIFO_HOT_RESET ,DAT TFIFO hot reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ADMA3_CLKEN_OVERRIDE ,Override for sdmmc_adma3_g_clk clken" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x04 24. " CQE_CLKEN_OVERRIDE ,Override for sdmmc_cqe_g_clk clken" "Normal,Override"
|
|
bitfld.long 0x04 23. " CQE_DESC_PREFETCH_EN ,Enables CQE task descriptors pre-fetch feature" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " ADMA3_DESC_PREFETCH_EN ,ADMA3 descriptors prefetch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " ADMA2_DESC_PREFETCH_EN ,ADMA2 descriptors prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--19. " DATA_TIMEOUT_VAL_MULTIPLIER ,Data timeout value multiplier" "No multiplier,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " DAT_TUNING_ASYNC_FIFO_ADDNL_DELAY ,Holds the additional delay in cycles which should be added to round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " ADDITIONAL_NCR_CYCLES ,Additional NCR wait time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " OVERRIDE_FOR_1_8V_VDD2 ,Maximum override for 1.8V VDD2"
|
|
textline " "
|
|
else
|
|
group.long 0x124++0x1F
|
|
line.long 0x00 "MAX_CURR_OVER_0,Maximum Current Override 0 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " OVERRIDE_FOR_1_8V ,Maximum override for 1.8V VDD1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OVERRIDE_FOR_3_0V ,Maximum override for 3.0V VDD1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OVERRIDE_FOR_3_3V ,Maximum override for 3.3V VDD1"
|
|
line.long 0x04 "MAX_CURR_OVER_HI_0,Maximum Current Override High 0 Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " OVERRIDE_FOR_1_8V_VDD2 ,Maximum override for 1.8V VDD2"
|
|
textline " "
|
|
endif
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "VENDOR_IO_TRIM_CNTRL_0,Vendor I/O Trimmer Control Register"
|
|
sif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 6.--7. " TRIM_SEL_ATEST ,Select analog test signals to send to comp pad" "No used,Input,Output before analog mux,Output after analog mux"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " TRIM_PWRSAVE ,Enables power saving mode by clock gating the unused taps in delay chain" "No,Yes"
|
|
bitfld.long 0x00 3.--4. " SEL_VREF_LEVEL ,Selects Vref voltage level" "VREF_875_MV,VREF_900_MV,VREF_925_MV,VREF_950_MV"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEL_VREG ,Select voltage supply for delay chain present in both Trimmer and DLLPROD value" "Regulated reference voltage,VAUXC"
|
|
bitfld.long 0x00 1. " SEL_VREF ,Select reference voltage for voltage regulator" "Bandgap Voltage Reference,Resistor divider voltage"
|
|
sif cpuis("TEGRAX2")
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "VENDOR_DLLCAL_CFG_0,Vendor DLL Calibration Configuration Register"
|
|
bitfld.long 0x00 31. " CALIBRATE ,Used to start a DLL calibration process" "Not started,Started"
|
|
bitfld.long 0x00 25.--29. " END_COUNT ,Determines the end condition of the calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 24. " USE_STATIC_CYCLES ,Calibration will be stopped when num static cycles reaches END_COUNT" "Not stopped,Stopped"
|
|
bitfld.long 0x00 23. " IGNORE_START_TRIM ,Used to ignore the START_TRM value" "Not ignored,Ignored"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " START_TRIM ,Specifies the starting trimmer value to calibrate the with"
|
|
bitfld.long 0x00 12.--15. " FILTER_BITS ,LSB of the counter to use for updating the trimmer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " SAMPLE_COUNT ,Number of times the phase detector is sampled before going onto the next set of trimmer values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAMPLE_DELAY ,Number of SDMMC host clks from changing the trimmer value"
|
|
line.long 0x04 "VENDOR_DLL_CTRL0_0,Vendor DLL Control Register 0"
|
|
bitfld.long 0x04 31. " MST_DLL_CLK_EN_OVERRIDE ,Master DLL CLK_IN enable override" "Normal,Override"
|
|
bitfld.long 0x04 30. " TX_SLV_DLL_PWRSAVE ,Active low signal" "No clock,Clock"
|
|
textline " "
|
|
bitfld.long 0x04 29. " RX_SLV_DLL_PWRSAVE ,Active low signal" "No clock,Clock"
|
|
hexmask.long.byte 0x04 22.--28. 1. " TX_SLV_DLL_DLY_CODE ,7-bit delay code to be applied to TX slave DLL"
|
|
textline " "
|
|
hexmask.long.byte 0x04 15.--21. 1. " RX_SLV_DLL_DLY_CODE ,7-bit delay code to be applied to RX slave DLL"
|
|
bitfld.long 0x04 14. " DLLCAL_BYPASS ,DLL calibration bypass enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x04 7.--13. 1. " TX_DLY_CODE_OFFSET ,Two-s complement offset will be added to delay code generated by calibration controller and sent to TX slv DLL"
|
|
hexmask.long.byte 0x04 0.--6. 1. " RX_DLY_CODE_OFFSET ,Two-s complement offset will be added to delay code generated by calibration controller and sent to RX slv DLL"
|
|
line.long 0x08 "VENDOR_DLL_CTRL1_0,Vendor DLL Control Register 1"
|
|
hexmask.long.byte 0x08 24.--30. 1. " REQD_DELAY_STEPS_TX ,Delay required in steps of 1/64 UI - 0 to 63 steps MST DLL is half cycle locked"
|
|
hexmask.long.byte 0x08 16.--22. 1. " REQD_DELAY_STEPS_RX ,Delay required in steps of 1/64 UI - 0 to 63 steps MST DLL is half cycle locked"
|
|
textline " "
|
|
bitfld.long 0x08 11.--15. " MST_DLL_RESET_TIME ,Master DLL reset duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 7.--10. " SLV_DLL_SETTLE_TIME ,Slave DLL requires 4 cycles settle time when delay code is changed for providing stable output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--6. 1. " MST_DLL_DLY_CODE ,7-bit delay code (128 taps) to be applied to master DLL"
|
|
line.long 0x0C "VENDOR_DLLCAL_CFG_STA_0,Vendor DLL Calibration Config and Status Register"
|
|
rbitfld.long 0x0C 31. " DLL_CAL_ACTIVE ,Calibration process status software has to wait for DONE once calibrate bit is cleared and before starting data transfers on eMMC interface" "Done,Running"
|
|
rbitfld.long 0x0C 30. " DLL_PD ,Master DLL Phase detector output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " MST_DLL_RST_OVERRIDE_EN ,MST_DLL_RST override enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " MST_DLL_RST ,Master DLL reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " SLV_DLL_CLK_OUT_DIS_OVERRIDE_EN ,SLV_DLL_CLK_OUT_DIS override enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " SLV_DLL_CLK_OUT_DIS ,Slave DLL clock out disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " MST_DLL_PWRDN_OVERRIDE_EN ,MST_DLL_PWRDN override enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " MST_DLL_PWRDN ,Master DLL power down enable - active high control - used when MST_DLL_PWRDN_OVERRIDE_EN is set" "Power up,Power down"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 16.--22. 1. " TX_DLY_CODE_ADJ ,Delay code sent to TX slave DLL after applying offset"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " RX_DLY_CODE_ADJ ,Delay code sent to RX slave DLL after applying offset"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--6. 1. " DLY_CODE ,Holds delay code determined by calibration process which is sent to MST DLL during calibration"
|
|
else
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "VENDOR_DLLCAL_CFG_0,Vendor DLL Calibration Configuration Register"
|
|
bitfld.long 0x00 31. " CALIBRATE ,Used to start a DLL calibration process" "Not started,Started"
|
|
bitfld.long 0x00 25.--29. " END_COUNT ,Determines the end condition of the calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 24. " USE_STATIC_CYCLES ,Calibration will be stopped when num static cycles reaches END_COUNT" "Not stopped,Stopped"
|
|
bitfld.long 0x00 23. " IGNORE_START_TRIM ,Used to ignore the START_TRM value" "Not ignored,Ignored"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " START_TRIM ,Specifies the starting trimmer value to calibrate the with"
|
|
bitfld.long 0x00 12.--15. " FILTER_BITS ,LSB of the counter to use for updating the trimmer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " SAMPLE_COUNT ,Number of times the phase detector is sampled before going onto the next set of trimmer values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAMPLE_DELAY ,Number of SDMMC host clks from changing the trimmer value"
|
|
line.long 0x04 "VENDOR_DLL_CTRL0_0,Vendor DLL Control Register 0"
|
|
bitfld.long 0x04 31. " MST_DLL_CLK_EN_OVERRIDE ,Master DLL CLK_IN enable override" "Normal,Override"
|
|
bitfld.long 0x04 30. " TX_SLV_DLL_PWRSAVE ,Active low signal" "No clock,Clock"
|
|
textline " "
|
|
bitfld.long 0x04 29. " RX_SLV_DLL_PWRSAVE ,Active low signal" "No clock,Clock"
|
|
hexmask.long.byte 0x04 22.--28. 1. " TX_SLV_DLL_DLY_CODE ,7-bit delay code to be applied to TX slave DLL"
|
|
textline " "
|
|
hexmask.long.byte 0x04 15.--21. 1. " RX_SLV_DLL_DLY_CODE ,7-bit delay code to be applied to RX slave DLL"
|
|
bitfld.long 0x04 14. " DLLCAL_BYPASS ,DLL calibration bypass enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x04 7.--13. 1. " TX_DLY_CODE_OFFSET ,Two-s complement offset will be added to delay code generated by calibration controller and sent to TX slv DLL"
|
|
hexmask.long.byte 0x04 0.--6. 1. " RX_DLY_CODE_OFFSET ,Two-s complement offset will be added to delay code generated by calibration controller and sent to RX slv DLL"
|
|
line.long 0x08 "VENDOR_DLL_CTRL1_0,Vendor DLL Control Register 1"
|
|
hexmask.long.byte 0x08 24.--30. 1. " REQD_DELAY_STEPS_TX ,Delay required in steps of 1/64 UI - 0 to 63 steps MST DLL is half cycle locked"
|
|
hexmask.long.byte 0x08 16.--22. 1. " REQD_DELAY_STEPS_RX ,Delay required in steps of 1/64 UI - 0 to 63 steps MST DLL is half cycle locked"
|
|
textline " "
|
|
bitfld.long 0x08 11.--15. " MST_DLL_RESET_TIME ,Master DLL CLK_IN enable override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 7.--10. " SLV_DLL_SETTLE_TIME ,Slave DLL requires 4 cycles settle time when dly code is changed for providing stable output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--6. 1. " MST_DLL_DLY_CODE ,7-bit delay code (128 taps) to be applied to master DLL"
|
|
line.long 0x0C "VENDOR_DLLCAL_CFG_STA_0,Vendor DLL Calibration Configuration Register"
|
|
bitfld.long 0x0C 31. " DLL_CAL_ACTIVE ,Calibration process status software has to wait for DONE once calibrate bit is cleared and before starting data transfers on eMMC interface" "Done,Running"
|
|
bitfld.long 0x0C 30. " DLL_PD ,Master DLL Phase detector output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " MST_DLL_RST_OVERRIDE_EN ,Master DLL reset is controlled by programming MST_DLL_RST/DLL controller" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " MST_DLL_RST ,Master DLL reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " SLV_DLL_CLK_OUT_DIS_OVERRIDE_EN ,Slave DLL clk_out_dis is controlled by programming SLV_DLL_CLK_OUT_DIS/DLL controller" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " SLV_DLL_CLK_OUT_DIS ,Slave DLL clock out disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " MST_DLL_PWRDN_OVERRIDE_EN ,Master DLL can be kept in power down mode by programming MST_DLL_PWRDN field" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " MST_DLL_PWRDN ,Master DLL power down enable - active high control - used when MST_DLL_PWRDN_OVERRIDE_EN is set" "Power up,Power down"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 16.--22. 1. " TX_DLY_CODE_ADJ ,Delay code sent to TX slave DLL after applying offset"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " RX_DLY_CODE_ADJ ,Delay code sent to RX slave DLL after applying offset"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--6. 1. " DLY_CODE ,Holds delay code determined by calibration process which is sent to MST DLL during calibration"
|
|
endif
|
|
group.long 0x1C0++0x07
|
|
line.long 0x00 "VENDOR_TUNING_CNTRL0_0,Vendor Tuning Control 0 Register"
|
|
bitfld.long 0x00 30. " RD_DATA_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on read data CRC error" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " WR_DATA_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on write CRC error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " CMD_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on cmd CRC error" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RETUNING_REQ_EN_ON_CRC_ERR_DETECTION ,Generates re-tuning request" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TUNING_ERR_EN_ON_CRC_ERR_DETECTION ,Generates tuning error" "Not generated,Generated"
|
|
hexmask.long.byte 0x00 18.--25. 1. " START_TAP_VAL ,Start tap value to be used by tuning"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TAP_VAL_UPDATED_BY_HW ,Software can choose to update the tap value by itself" "Not updated,Updated"
|
|
bitfld.long 0x00 13.--15. " NUM_TUNING_ITERATIONS ,The number of tuning iterations to be used by tuning circuit" "TRIES_40,TRIES_64,TRIES_128,TRIES_192,TRIES_256,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 6.--12. 1. " MUL_M ,Implements a multiplier"
|
|
bitfld.long 0x00 3.--5. " DIV_N ,Implements a divider" "1,2,4,8,16,32,64,128"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TUNING_WORD_SEL ,Selects desired word from 256-bit tuning status bitmap status_word" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "VENDOR_TUNING_CNTRL1_0,Vendor Tuning Control 1 Register"
|
|
bitfld.long 0x04 4.--6. " STEP_SIZE_SDR104_HS200 ,TAP_VAL is incremented by step_size for every tuning iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " STEP_SIZE_SDR50 ,TAP_VAL is incremented by step_size for every tuning iteration" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1C8++0x07
|
|
line.long 0x00 "VENDOR_TUNING_STATUS0_0,Vendor Tuning Status 0 Register"
|
|
line.long 0x04 "VENDOR_TUNING_STATUS1_0,Vendor Tuning Status 1 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PASS_WINDOW_END_BEFORE_FINE_TUNING , End tap value of best PASS window found by scan FSM"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PASS_WINDOW_START_BEFORE_FINE_TUNING ,Start tap value of best PASS window found by scan FSM"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " PASS_WINDOW_END_AFTER_FINE_TUNING ,End tap value of best PASS window after fine tuning"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PASS_WINDOW_START_AFTER_FINE_TUNING ,Start tap value of best PASS window after fine tuning"
|
|
textline " "
|
|
endif
|
|
width 28.
|
|
group.long 0x1D0++0x0F
|
|
line.long 0x00 "VENDOR_CLK_GATE_HYST_CNT_0,Vendor Clock Gating Hysteresis Counter Initial Value"
|
|
bitfld.long 0x00 0.--5. " CLK_COUNT ,CLK count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "VENDOR_PRESET_VAL0_0,Vendor Preset Value Register 0"
|
|
hexmask.long.word 0x04 20.--29. 1. " SDCLK_FREQ_SEL_HIGH_SPEED ,10-bit divider value to generate an SD clock in default speed mode (<50 MHz)"
|
|
hexmask.long.word 0x04 10.--19. 1. " SDCLK_FREQ_SEL_DEFAULT ,10-bit divider value to generate an SD clock in default speed mode (<25 MHz)"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--9. 1. " SDCLK_FREQ_SEL_INIT ,10-bit divider value to generate the desired SD clock frequency during initialization"
|
|
line.long 0x08 "VENDOR_PRESET_VAL1_0,Vendor Preset Value Register 1"
|
|
hexmask.long.word 0x08 20.--29. 1. " SDCLK_FREQ_SEL_SDR50 ,10-bit divider value to generate the SD clock in SDR50 mode"
|
|
hexmask.long.word 0x08 10.--19. 1. " SDCLK_FREQ_SEL_SDR25 ,10-bit divider value to generate the SD clock in SDR25 mode"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--9. 1. " SDCLK_FREQ_SEL_SDR12 ,10-bit divider value to generate the SD clock in SDR12 mode"
|
|
line.long 0x0C "VENDOR_PRESET_VAL2_0,Vendor Preset Value Register 2"
|
|
hexmask.long.word 0x0C 10.--19. 1. " SDCLK_FREQ_SEL_DDR50 ,10-bit divider value to generate the SD clock in DDR50 mode"
|
|
hexmask.long.word 0x0C 0.--9. 1. " SDCLK_FREQ_SEL_SDR104 ,10-bit divider value to generate the SD clock in SDR104 mode"
|
|
sif cpuis("TEGRAX2")
|
|
if (((d.l(ad:0x700B0600+0x1E4))&0x20000000)==0x20000000)
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_E_PBIAS_BUF ,Enables internally generated bias levels for driver PMOS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Select different bias levels for driver PMOS when E_PBIAS_BUF=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_E_PBIAS_BUF ,Enables internally generated bias levels for driver PMOS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
hexmask.long.byte 0x00 20.--26. 1. " COMP_PAD_DRVUP_OVR ,Used to drive DRVUP input of COMP pad"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--18. 1. " COMP_PAD_DRVDN_OVR ,Used to drive DRVDN input of COMP pad"
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Select different bias levels for driver PMOS when E_PBIAS_BUF=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
elif cpuis("TEGRAX1")
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_REG_ON ,Turns ON regulator in comp pad" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 10. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Used to control vref_sel input of COMP pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if (((d.l(ad:0x700B0600+0x1E4))&0x20000000)==0x20000000)
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 29.--30. " PU_PAD_DRV_TYPE ,Pu pad drv type" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " PD_PAD_DRV_TYPE ,Pd pad drv type" "0,1,2,3"
|
|
bitfld.long 0x00 11. " PU_PAD_E_TEST_OUT ,Pu pad E test out" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PD_PAD_E_TEST_OUT ,Pd pad E test out" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " PU_PAD_TEST_SEL ,pu pad test sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PD_PAD_TEST_SEL ,Pd pad test sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,sdmmc2tmc cfg Sdmemcomp vref sel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 29.--30. " PU_PAD_DRV_TYPE ,PU PAD DRV TYPE" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " PD_PAD_DRV_TYPE ,PD PAD DRV TYPE" "0,1,2,3"
|
|
hexmask.long.byte 0x00 20.--26. 1. " CFG_SDMEMCOMP_DRVUP ,SDMMC pads drive up/down control"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--18. 1. " CFG_SDMEMCOMP_DRVDN ,SDMMC pads drive up/down control"
|
|
bitfld.long 0x00 11. " PU_PAD_E_TEST_OUT ,PU PAD E TEST OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PD_PAD_E_TEST_OUT ,PD_PAD_E_TEST_OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " PU_PAD_TEST_SEL ,PU PAD TEST SEL" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PD_PAD_TEST_SEL ,PD PAD TEST SEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,SDMMC2TMC CFG SDMEMCOMP VREF SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long 0x1E4++0x07
|
|
line.long 0x00 "AUTO_CAL_CFG_0,SDMEMCOMP Pad Auto-Calibration Settings"
|
|
bitfld.long 0x00 31. " AUTO_CAL_START ,Calibration state machine" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " AUTO_CAL_OVERRIDE ,AUTOCAL override" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 29. " AUTO_CAL_ENABLE ,AUTOCAL enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " AUTO_CAL_SLW_OVERRIDE ,AUTOCAL slew rate override" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " AUTO_CAL_STEP ,Calibration step interval" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PD_OFFSET ,2's complement offset for pull-down value"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PU_OFFSET ,2's complement offset for pull-up value"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
else
|
|
group.long 0x1E8++0x07
|
|
line.long 0x00 "AUTO_CAL_INTERVAL_0,SDMEMCOMP Pad Calibration Interval"
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "AUTO_CAL_STATUS_0,SDMEMCOMP Pad Calibration Status"
|
|
bitfld.long 0x00 31. " AUTO_CAL_ACTIVE ,Auto cal active" "Inactive,Active"
|
|
hexmask.long.byte 0x00 24.--30. 1. " AUTO_CAL_PULLDOWN_ADJ ,Pulldown code sent to pads"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " AUTO_CAL_PULLUP_ADJ ,Pullup code sent to pads"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PULLDOWN ,Pulldown code generated by auto-calibration"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PULLUP ,Pullup code generated by auto-calibration"
|
|
endif
|
|
sif cpuis("TEGRAX1")
|
|
group.long 0x1F0++0x07
|
|
line.long 0x00 "IO_SPARE_0,Memory Client Interface FIFO Control"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPARE_OUT ,PROD value"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPARE_IN ,PROD value"
|
|
endif
|
|
sif cpuis("TEGRAX2")
|
|
textline " "
|
|
group.long 0x1FC++0x0B
|
|
line.long 0x00 "CIF2AXI_CTRL_0,SD/MMC CIF2AXI Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MC_WRITE_REQ_STREAM_ID ,MC write transaction stream ID"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MC_READ_REQ_STREAM_ID ,MC read transaction stream ID"
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "TZ_DMA_CTRL_0,SD/MMC DMA Requests Security Attribute Control Register"
|
|
bitfld.long 0x00 1. " MC_WRITE_REQ_TZ_ACCESS_EN ,MC_WRITE_REQ_TZ_ACCESS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MC_READ_REQ_TZ_ACCESS_EN ,MC_READ_REQ_TZ_ACCESS enable" "Disabled,Enabled"
|
|
line.long 0x04 "VENDOR_MISC_CNTRL3_0,Misc Vendor Control Register 3"
|
|
bitfld.long 0x04 30. " STOP_TRIM_IN_CLK_DURING_TUNING ,Stops rx clk trimmer and rx FIFOs input clock during tuning" "Not stopped,Stopped"
|
|
bitfld.long 0x04 24.--29. " TUNING_TRIMMER_RECOVERY_TIME ,TUNING TRIMMER RECOVERY TIME" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " E_DIFF_DQ , Diff/Vref rx selection for DAT[7:0]"
|
|
bitfld.long 0x04 4. " E_DIFF_CMD ,Diff/Vref rx selection for CMD" "Stopped,Not stopped"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DAT_OE_POSTAMBLE_EN ,DAT pads output driver one cycle after disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " DAT_OE_PREAMBLE_EN ,DAT pads output driver one cycle before enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CMD_OE_POSTAMBLE_EN ,CMD pad output driver one cycle after disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CMD_OE_PREAMBLE_EN ,CMD pad output driver one cycle before enable" "Disabled,Enabled"
|
|
group.long 0x20C++0x07
|
|
line.long 0x00 "VENDOR_MISC_CNTRL4_0,Misc Vendor Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " SDMMC_SPARE3 ,Spare register bits with reset value of 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDMMC_SPARE2 ,Spare register bits with reset value of 0"
|
|
else
|
|
group.long 0x1F4++0x07
|
|
line.long 0x00 "SDMMC_MCCIF_FIFOCTRL_0,Memory Client Interface FIFO Control"
|
|
bitfld.long 0x00 20. " SDMMC_RCLK_OVR_MODE ,SDMMC RCLK OVR MODE" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SDMMC_WCLK_OVR_MODE ,SDMMC WCLK OVR MODE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SDMMC_CCLK_OVERRIDE ,SDMMC CCLK OVERRIDE" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SDMMC_RCLK_OVERRIDE ,SDMMC RCLK OVERRIDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SDMMC_WCLK_OVERRIDE ,SDMMC WCLK OVERRIDE" "Disabled,Enabled"
|
|
line.long 0x04 "TIMEOUT_WCOAL_SDMMC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SDMMCW_WCOAL_TMVAL ,SDMMCW WCOAL TMVAL"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "SDMMC-4B"
|
|
base ad:0x700B4600
|
|
tree.open "Standard Registers"
|
|
width 27.
|
|
sif !cpuis("TEGRAX1")&&!cpuis("TEGRAX2")
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "PSR,Present State Register"
|
|
bitfld.long 0x00 25.--28. " DAT_7_4_LINE_LEVEL ,This status reflects the DAT[7:4] lines state for debug" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif !cpuis("TEGRAX2")
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " BOOT_ACK_ERR ,Boot ack status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " BOOT_ACK_TIMEOUT_ERR ,Boot Ack is not received" "Not occurred,Occurred"
|
|
line.long 0x04 "ISTAER,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor Ack_Timeout and Ack error status" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
line.long 0x08 "ISIGR,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor specification error" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
else
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "INTERRUPT_STATUS_0,Interrupt Status Register"
|
|
bitfld.long 0x00 31. " BOOT_ACK_ERR ,Boot ack status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " BOOT_ACK_TIMEOUT_ERR ,Boot Ack is not received" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BUFFER_READ_READY ,Buffer read ready" "NO_INT,GEN_INT"
|
|
line.long 0x04 "INTERRUPT_STATUS_ENABLE_0,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor Ack_Timeout and Ack error status" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BUFFER_READ_READY ,Buffer read ready" "Disabled,Enabled"
|
|
line.long 0x08 "INTERRUPT_SIGNAL_ENABLE_0,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 30.--31. " VENDOR_SPECIFIC_ERR ,Vendor specification error" "Neither,Ack_Timeout_Err,Ack_Err,Both"
|
|
textline " "
|
|
bitfld.long 0x08 5. " BUFFER_READ_READY ,Buffer read ready" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("TEGRAX1")
|
|
group.long 0x3C++0x0B
|
|
line.long 0x00 "AUTO_CMD12_ERR_STATUS_0,Auto cmd12 err status 0"
|
|
bitfld.long 0x00 16.--18. " UHS_MODE_SEL ,UHS Mode Select" "LEGACY,HIGH,SDR50,SDR104,DDR50,HS400,?..."
|
|
endif
|
|
sif !cpuis("TEGRAX2")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FER,Force Event Register"
|
|
bitfld.long 0x00 30.--31. " VENDOR_SPECIFIC_ERR_STATUS ,Vendor specific error status" "No effect,ACK_TIMEOUT_ERR,ACK_ERR,Both"
|
|
endif
|
|
tree.end
|
|
tree.open "Vendor-Specific Registers"
|
|
width 27.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "VENDOR_CLOCK_CNTRL_0,Vendor Clock Control Register"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 29. " DIFF_CLK_SEL ,Selects differential CLK and DQS" "0,1"
|
|
bitfld.long 0x00 24.--28. " TRIM_VAL ,Tap value for output data path trimmer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " TAP_VAL ,Tap value for input data path trimmer"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BASE_CLK_FREQ ,SD/MMC clock frequency"
|
|
textline " "
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 6. " LEGACY_CLKEN_OVERRIDE ,Override for sdmmc_legacy_g_clk clken" "Normal,Override"
|
|
textline " "
|
|
endif
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 4. " UHS2_CAPABILITY_OVERRIDE ,Override the UHS-II capabilities bit" "Normal,Override"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " PADPIPE_CLKEN_OVERRIDE ,Override for padmacro and pipemacro clken" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SPI_MODE_CLKEN_OVERRIDE ,Override for CLKEN during SPI_MODE during sw_reset" "Normal,Override"
|
|
bitfld.long 0x00 1. " INPUT_IO_CLK ,Input I/O clock" "Feedback,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SDMMC_CLK ,Set when sdmmc_clk is supplied by the CAR module prior to sdmmc_clk switch OFF" "Disabled,Enabled"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
if (((d.l(ad:0x700B4600+0x104))&0x40000000)==0x40000000)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 31. " ENHANCED_STROBE_MODE ,Enables enhanced strobe mode in HS400/HS667 mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT ,Uses TMCLK data timeout counter for generating wr_crc_status data-timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " USE_NCRC_FOR_WR_CRC_STATUS_TIMEOUT_VAL ,Uses data timeout value as wr CRC/NCRC status timeout value" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " USE_TMCLK_FOR_DATA_TIMEOUT ,Uses TMCLK data timeout counter for generating legacy data timeout error" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,This register field is used to load wait_cycles counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,Busy should be sampled using clock instead DQS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 23. " ALLOW_CARD_CLK_STALLS_IN_WR ,Allows card clock stopping during transfer of data within a block in HIGH SPEED DDR/HS400 writes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EMMC_IOBRICK_CLK_DATA ,Used to drive AP_CLK and AN_CLK input of iobrick" "Disabled,Enabled"
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|
bitfld.long 0x00 21. " QUALIFY_WITH_RD_DATA_VLD ,Async FIFOs in both cmd_in and dat_in paths in padmacro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,TUNING_SYS interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8.--11. " TUNING_ASYNC_FIFO_ADDNL_DELAY ,DATA/CMD IB path uses async FIFO which contributes additional delay to CMD/RESP and WDATA/CRC token round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,SD_BUS_POWER_ON_OFF interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,VOLT_SWITCH interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,TUNING_SYS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IO_TRIM_BYPASS ,Override bit for selecting between core trimmer and I/O trimmer in IB clock path" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 31. " ENHANCED_STROBE_MODE ,Enables enhanced strobe mode in HS400/HS667 mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " USE_TMCLK_FOR_WR_CRC_STATUS_TIMEOUT , Uses TMCLK data timeout counter for generating wr_crc_status data-timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " USE_TMCLK_FOR_DATA_TIMEOUT ,Uses TMCLK data timeout counter for generating legacy data timeout error" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,This register field is used to load wait_cycles counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 24.--27. " DEVICE_BUSY_WAIT_CYCLES ,Busy should be sampled using clock instead DQS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 23. " ALLOW_CARD_CLK_STALLS_IN_WR ,allows card clock stopping during transfer of data within a block in HIGH SPEED DDR/HS400 writes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EMMC_IOBRICK_CLK_DATA ,Used to drive AP_CLK and AN_CLK input of iobrick" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " QUALIFY_WITH_RD_DATA_VLD ,Async FIFOs in both cmd_in and dat_in paths in padmacro" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,TUNING_SYS interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8.--11. " TUNING_ASYNC_FIFO_ADDNL_DELAY ,DATA/CMD IB path uses async FIFO which contributes additional delay to CMD/RESP and WDATA/CRC token round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,SD_BUS_POWER_ON_OFF interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,VOLT_SWITCH interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,TUNING_SYS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IO_TRIM_BYPASS ,Override bit for selecting between core trimmer and I/O trimmer in IB clock path" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "VENDOR_ERR_INTR_STATUS_0,Legacy Interrupt Status Register"
|
|
bitfld.long 0x00 18. " SDMMC_LEGACY_CTLR_IDLE ,Indicates legacy SD interface controller is idle" "0,1"
|
|
bitfld.long 0x00 17. " READ_DATA_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " WRITE_CRC_STATUS_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
bitfld.long 0x00 15. " WRITE_BUSY_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RESP_BUSY_TIMEOUT ,Valid when a data timeout error occurs" "0,1"
|
|
bitfld.long 0x00 13. " SPI_WRITE_BUSY_TIMEOUT ,SPI_WRITE_BUSY timeout" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SPI_RX_START_TOKEN_TIMEOUT ,SPI_RX_START_TOKEN timeout" "0,1"
|
|
bitfld.long 0x00 5.--8. " SPI_DAT_ERR_TOKEN ,Data Error Token while read from card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SPI_DAT_RESPONSE ,Data Response while write to card" ",,,,,DATA_ACCEPTED,,,,,,CRC_ERR,,WRITE_ERR,?..."
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "VENDOR_SYS_SW_CNTRL_0,Vendor System SW Control Register"
|
|
bitfld.long 0x00 14. " SD_BUS_POWER_ON_OFF_INT_STATUS ,SD_BUS_POWER was changed" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " VOLT_SWITCH_INT_STATUS ,VOLT_18_EN was changed" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TUNING_SYS_INT_STATUS ,CMD19 was issued while EXECUTE_TUNING was set" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " SD_BUS_POWER_ON_OFF_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VOLT_SWITCH_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TUNING_SYS_INT_ENABLE ,Enables a separate system interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASSERT_BUFF_RD_RDY_INT ,Used by the system software that implements the tuning procedure to signal to the standard SD driver that the tuning process has completed" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INT_MASK_WHILE_TUNING ,Interrupt generation behavior is changed when a this bit is set" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPI_MODE ,SPI mode enable. Writing 1 will drive the CS low and writing 0 will deassert the CS signal" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10C++0x17
|
|
line.long 0x00 "VENDOR_CAP_OVERRIDES_0,Capabilities Override Bits"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
sif !cpuis("TEGRAX2")
|
|
bitfld.long 0x00 28. " CMD_QUEUING_MODE_EN ,Useful for eMMC5.x devices which support CMD queuing" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--13. " DQS_TRIM_VAL ,Tap value for incoming DQS path trimmer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DRV_LPBK_CLK_ON_CMD_LINE ,Loopback trimmed clock will be driven onto cmd line" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " VOLTAGE_3_3_V_SUPPORT_OVERRIDE ,Voltage support 3_3_V override" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " VOLTAGE_3_0_V_SUPPORT_OVERRIDE ,Voltage support 3_0_V override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VOLTAGE_1_8_V_SUPPORT_OVERRIDE ,Voltage support 1_8_V override" "Disabled,Enabled"
|
|
line.long 0x04 "VENDOR_BOOT_CNTRL_0,Vendor Boot Control Register"
|
|
bitfld.long 0x04 1. " BOOT_ACK ,Used to support Boot Option in MMC 4.3 version cards" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " BOOT ,Boot Option 1" "Disabled,Enabled"
|
|
line.long 0x08 "VENDOR_BOOT_ACK_TIMEOUT_0,Vendor Boot Acknowledgement Timeout Register"
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " VALUE ,Boot Acknowledgment timeout value"
|
|
line.long 0x0C "VENDOR_BOOT_DAT_TIMEOUT_0,Boot Data Timeout Register"
|
|
hexmask.long 0x0C 0.--24. 1. " VALUE ,Boot Data timeout value"
|
|
line.long 0x10 "VENDOR_DEBOUNCE_COUNT_0,Debounce Counter Value Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " VALUE ,The number of 32KHz clock cycles is programmed to meet the debounce period of the card slot"
|
|
line.long 0x14 "VENDOR_MISC_CNTRL_0,Miscellaneous Vendor Control Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " SDMMC_SPARE_1 ,Spare register bits with reset value of 1"
|
|
hexmask.long.word 0x14 1.--15. 1. " SDMMC_SPARE_0 ,Spare register bits with reset value of 0x40"
|
|
textline " "
|
|
bitfld.long 0x14 0. " ERASE_TIMEOUT_LIMIT ,Erase timeout value" "Finite,Infinite"
|
|
sif cpuis("TEGRAX2")
|
|
group.long 0x124++0x1F
|
|
line.long 0x00 "VENDOR_MISC_CNTRL1_0,Misc Vendor Control Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " OVERRIDE_FOR_1_8V ,Maximum override for 1.8V VDD1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OVERRIDE_FOR_3_0V ,Maximum override for 3.0V VDD1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OVERRIDE_FOR_3_3V ,Maximum override for 3.3V VDD1"
|
|
line.long 0x04 "VENDOR_MISC_CNTRL2_0,Misc Vendor Control Register 2"
|
|
bitfld.long 0x04 31. " VGPIO_MODE_EN ,VGPIO_MODE enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " SDMMC_CLK_OVR_ON ,Master clk en Override bit for all SLCGs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " SD_CARD_DETECT_STATUS_N ,SD card detect status n" "Detected,Not detected"
|
|
bitfld.long 0x04 28. " SD_CARD_WP_STATUS ,SD card wp status" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 27. " CMD_TFIFO_HOT_RESET ,CMD TFIFO hot reset" "No reset,Reset"
|
|
bitfld.long 0x04 26. " DAT_TFIFO_HOT_RESET ,DAT TFIFO hot reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ADMA3_CLKEN_OVERRIDE ,Override for sdmmc_adma3_g_clk clken" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x04 24. " CQE_CLKEN_OVERRIDE ,Override for sdmmc_cqe_g_clk clken" "Normal,Override"
|
|
bitfld.long 0x04 23. " CQE_DESC_PREFETCH_EN ,Enables CQE task descriptors pre-fetch feature" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " ADMA3_DESC_PREFETCH_EN ,ADMA3 descriptors prefetch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " ADMA2_DESC_PREFETCH_EN ,ADMA2 descriptors prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--19. " DATA_TIMEOUT_VAL_MULTIPLIER ,Data timeout value multiplier" "No multiplier,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " DAT_TUNING_ASYNC_FIFO_ADDNL_DELAY ,Holds the additional delay in cycles which should be added to round trip delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " ADDITIONAL_NCR_CYCLES ,Additional NCR wait time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " OVERRIDE_FOR_1_8V_VDD2 ,Maximum override for 1.8V VDD2"
|
|
textline " "
|
|
else
|
|
group.long 0x124++0x1F
|
|
line.long 0x00 "MAX_CURR_OVER_0,Maximum Current Override 0 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " OVERRIDE_FOR_1_8V ,Maximum override for 1.8V VDD1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " OVERRIDE_FOR_3_0V ,Maximum override for 3.0V VDD1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " OVERRIDE_FOR_3_3V ,Maximum override for 3.3V VDD1"
|
|
line.long 0x04 "MAX_CURR_OVER_HI_0,Maximum Current Override High 0 Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " OVERRIDE_FOR_1_8V_VDD2 ,Maximum override for 1.8V VDD2"
|
|
textline " "
|
|
endif
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "VENDOR_IO_TRIM_CNTRL_0,Vendor I/O Trimmer Control Register"
|
|
sif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 6.--7. " TRIM_SEL_ATEST ,Select analog test signals to send to comp pad" "No used,Input,Output before analog mux,Output after analog mux"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " TRIM_PWRSAVE ,Enables power saving mode by clock gating the unused taps in delay chain" "No,Yes"
|
|
bitfld.long 0x00 3.--4. " SEL_VREF_LEVEL ,Selects Vref voltage level" "VREF_875_MV,VREF_900_MV,VREF_925_MV,VREF_950_MV"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SEL_VREG ,Select voltage supply for delay chain present in both Trimmer and DLLPROD value" "Regulated reference voltage,VAUXC"
|
|
bitfld.long 0x00 1. " SEL_VREF ,Select reference voltage for voltage regulator" "Bandgap Voltage Reference,Resistor divider voltage"
|
|
sif cpuis("TEGRAX2")
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "VENDOR_DLLCAL_CFG_0,Vendor DLL Calibration Configuration Register"
|
|
bitfld.long 0x00 31. " CALIBRATE ,Used to start a DLL calibration process" "Not started,Started"
|
|
bitfld.long 0x00 25.--29. " END_COUNT ,Determines the end condition of the calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 24. " USE_STATIC_CYCLES ,Calibration will be stopped when num static cycles reaches END_COUNT" "Not stopped,Stopped"
|
|
bitfld.long 0x00 23. " IGNORE_START_TRIM ,Used to ignore the START_TRM value" "Not ignored,Ignored"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " START_TRIM ,Specifies the starting trimmer value to calibrate the with"
|
|
bitfld.long 0x00 12.--15. " FILTER_BITS ,LSB of the counter to use for updating the trimmer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " SAMPLE_COUNT ,Number of times the phase detector is sampled before going onto the next set of trimmer values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAMPLE_DELAY ,Number of SDMMC host clks from changing the trimmer value"
|
|
line.long 0x04 "VENDOR_DLL_CTRL0_0,Vendor DLL Control Register 0"
|
|
bitfld.long 0x04 31. " MST_DLL_CLK_EN_OVERRIDE ,Master DLL CLK_IN enable override" "Normal,Override"
|
|
bitfld.long 0x04 30. " TX_SLV_DLL_PWRSAVE ,Active low signal" "No clock,Clock"
|
|
textline " "
|
|
bitfld.long 0x04 29. " RX_SLV_DLL_PWRSAVE ,Active low signal" "No clock,Clock"
|
|
hexmask.long.byte 0x04 22.--28. 1. " TX_SLV_DLL_DLY_CODE ,7-bit delay code to be applied to TX slave DLL"
|
|
textline " "
|
|
hexmask.long.byte 0x04 15.--21. 1. " RX_SLV_DLL_DLY_CODE ,7-bit delay code to be applied to RX slave DLL"
|
|
bitfld.long 0x04 14. " DLLCAL_BYPASS ,DLL calibration bypass enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x04 7.--13. 1. " TX_DLY_CODE_OFFSET ,Two-s complement offset will be added to delay code generated by calibration controller and sent to TX slv DLL"
|
|
hexmask.long.byte 0x04 0.--6. 1. " RX_DLY_CODE_OFFSET ,Two-s complement offset will be added to delay code generated by calibration controller and sent to RX slv DLL"
|
|
line.long 0x08 "VENDOR_DLL_CTRL1_0,Vendor DLL Control Register 1"
|
|
hexmask.long.byte 0x08 24.--30. 1. " REQD_DELAY_STEPS_TX ,Delay required in steps of 1/64 UI - 0 to 63 steps MST DLL is half cycle locked"
|
|
hexmask.long.byte 0x08 16.--22. 1. " REQD_DELAY_STEPS_RX ,Delay required in steps of 1/64 UI - 0 to 63 steps MST DLL is half cycle locked"
|
|
textline " "
|
|
bitfld.long 0x08 11.--15. " MST_DLL_RESET_TIME ,Master DLL reset duration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 7.--10. " SLV_DLL_SETTLE_TIME ,Slave DLL requires 4 cycles settle time when delay code is changed for providing stable output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--6. 1. " MST_DLL_DLY_CODE ,7-bit delay code (128 taps) to be applied to master DLL"
|
|
line.long 0x0C "VENDOR_DLLCAL_CFG_STA_0,Vendor DLL Calibration Config and Status Register"
|
|
rbitfld.long 0x0C 31. " DLL_CAL_ACTIVE ,Calibration process status software has to wait for DONE once calibrate bit is cleared and before starting data transfers on eMMC interface" "Done,Running"
|
|
rbitfld.long 0x0C 30. " DLL_PD ,Master DLL Phase detector output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " MST_DLL_RST_OVERRIDE_EN ,MST_DLL_RST override enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " MST_DLL_RST ,Master DLL reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " SLV_DLL_CLK_OUT_DIS_OVERRIDE_EN ,SLV_DLL_CLK_OUT_DIS override enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " SLV_DLL_CLK_OUT_DIS ,Slave DLL clock out disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " MST_DLL_PWRDN_OVERRIDE_EN ,MST_DLL_PWRDN override enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " MST_DLL_PWRDN ,Master DLL power down enable - active high control - used when MST_DLL_PWRDN_OVERRIDE_EN is set" "Power up,Power down"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 16.--22. 1. " TX_DLY_CODE_ADJ ,Delay code sent to TX slave DLL after applying offset"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " RX_DLY_CODE_ADJ ,Delay code sent to RX slave DLL after applying offset"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--6. 1. " DLY_CODE ,Holds delay code determined by calibration process which is sent to MST DLL during calibration"
|
|
else
|
|
group.long 0x1B0++0x0F
|
|
line.long 0x00 "VENDOR_DLLCAL_CFG_0,Vendor DLL Calibration Configuration Register"
|
|
bitfld.long 0x00 31. " CALIBRATE ,Used to start a DLL calibration process" "Not started,Started"
|
|
bitfld.long 0x00 25.--29. " END_COUNT ,Determines the end condition of the calibration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 24. " USE_STATIC_CYCLES ,Calibration will be stopped when num static cycles reaches END_COUNT" "Not stopped,Stopped"
|
|
bitfld.long 0x00 23. " IGNORE_START_TRIM ,Used to ignore the START_TRM value" "Not ignored,Ignored"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " START_TRIM ,Specifies the starting trimmer value to calibrate the with"
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|
bitfld.long 0x00 12.--15. " FILTER_BITS ,LSB of the counter to use for updating the trimmer value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
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|
bitfld.long 0x00 8.--11. " SAMPLE_COUNT ,Number of times the phase detector is sampled before going onto the next set of trimmer values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
hexmask.long.byte 0x00 0.--7. 1. " SAMPLE_DELAY ,Number of SDMMC host clks from changing the trimmer value"
|
|
line.long 0x04 "VENDOR_DLL_CTRL0_0,Vendor DLL Control Register 0"
|
|
bitfld.long 0x04 31. " MST_DLL_CLK_EN_OVERRIDE ,Master DLL CLK_IN enable override" "Normal,Override"
|
|
bitfld.long 0x04 30. " TX_SLV_DLL_PWRSAVE ,Active low signal" "No clock,Clock"
|
|
textline " "
|
|
bitfld.long 0x04 29. " RX_SLV_DLL_PWRSAVE ,Active low signal" "No clock,Clock"
|
|
hexmask.long.byte 0x04 22.--28. 1. " TX_SLV_DLL_DLY_CODE ,7-bit delay code to be applied to TX slave DLL"
|
|
textline " "
|
|
hexmask.long.byte 0x04 15.--21. 1. " RX_SLV_DLL_DLY_CODE ,7-bit delay code to be applied to RX slave DLL"
|
|
bitfld.long 0x04 14. " DLLCAL_BYPASS ,DLL calibration bypass enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x04 7.--13. 1. " TX_DLY_CODE_OFFSET ,Two-s complement offset will be added to delay code generated by calibration controller and sent to TX slv DLL"
|
|
hexmask.long.byte 0x04 0.--6. 1. " RX_DLY_CODE_OFFSET ,Two-s complement offset will be added to delay code generated by calibration controller and sent to RX slv DLL"
|
|
line.long 0x08 "VENDOR_DLL_CTRL1_0,Vendor DLL Control Register 1"
|
|
hexmask.long.byte 0x08 24.--30. 1. " REQD_DELAY_STEPS_TX ,Delay required in steps of 1/64 UI - 0 to 63 steps MST DLL is half cycle locked"
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|
hexmask.long.byte 0x08 16.--22. 1. " REQD_DELAY_STEPS_RX ,Delay required in steps of 1/64 UI - 0 to 63 steps MST DLL is half cycle locked"
|
|
textline " "
|
|
bitfld.long 0x08 11.--15. " MST_DLL_RESET_TIME ,Master DLL CLK_IN enable override" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x08 7.--10. " SLV_DLL_SETTLE_TIME ,Slave DLL requires 4 cycles settle time when dly code is changed for providing stable output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
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|
hexmask.long.byte 0x08 0.--6. 1. " MST_DLL_DLY_CODE ,7-bit delay code (128 taps) to be applied to master DLL"
|
|
line.long 0x0C "VENDOR_DLLCAL_CFG_STA_0,Vendor DLL Calibration Configuration Register"
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|
bitfld.long 0x0C 31. " DLL_CAL_ACTIVE ,Calibration process status software has to wait for DONE once calibrate bit is cleared and before starting data transfers on eMMC interface" "Done,Running"
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|
bitfld.long 0x0C 30. " DLL_PD ,Master DLL Phase detector output" "0,1"
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|
textline " "
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|
bitfld.long 0x0C 29. " MST_DLL_RST_OVERRIDE_EN ,Master DLL reset is controlled by programming MST_DLL_RST/DLL controller" "Disabled,Enabled"
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|
bitfld.long 0x0C 28. " MST_DLL_RST ,Master DLL reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " SLV_DLL_CLK_OUT_DIS_OVERRIDE_EN ,Slave DLL clk_out_dis is controlled by programming SLV_DLL_CLK_OUT_DIS/DLL controller" "Disabled,Enabled"
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|
bitfld.long 0x0C 26. " SLV_DLL_CLK_OUT_DIS ,Slave DLL clock out disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " MST_DLL_PWRDN_OVERRIDE_EN ,Master DLL can be kept in power down mode by programming MST_DLL_PWRDN field" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " MST_DLL_PWRDN ,Master DLL power down enable - active high control - used when MST_DLL_PWRDN_OVERRIDE_EN is set" "Power up,Power down"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 16.--22. 1. " TX_DLY_CODE_ADJ ,Delay code sent to TX slave DLL after applying offset"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " RX_DLY_CODE_ADJ ,Delay code sent to RX slave DLL after applying offset"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--6. 1. " DLY_CODE ,Holds delay code determined by calibration process which is sent to MST DLL during calibration"
|
|
endif
|
|
group.long 0x1C0++0x07
|
|
line.long 0x00 "VENDOR_TUNING_CNTRL0_0,Vendor Tuning Control 0 Register"
|
|
bitfld.long 0x00 30. " RD_DATA_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on read data CRC error" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " WR_DATA_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on write CRC error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " CMD_CRC_ERR_EN ,Re-tuning request/tuning error is not generated on cmd CRC error" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RETUNING_REQ_EN_ON_CRC_ERR_DETECTION ,Generates re-tuning request" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 26. " TUNING_ERR_EN_ON_CRC_ERR_DETECTION ,Generates tuning error" "Not generated,Generated"
|
|
hexmask.long.byte 0x00 18.--25. 1. " START_TAP_VAL ,Start tap value to be used by tuning"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TAP_VAL_UPDATED_BY_HW ,Software can choose to update the tap value by itself" "Not updated,Updated"
|
|
bitfld.long 0x00 13.--15. " NUM_TUNING_ITERATIONS ,The number of tuning iterations to be used by tuning circuit" "TRIES_40,TRIES_64,TRIES_128,TRIES_192,TRIES_256,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 6.--12. 1. " MUL_M ,Implements a multiplier"
|
|
bitfld.long 0x00 3.--5. " DIV_N ,Implements a divider" "1,2,4,8,16,32,64,128"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " TUNING_WORD_SEL ,Selects desired word from 256-bit tuning status bitmap status_word" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "VENDOR_TUNING_CNTRL1_0,Vendor Tuning Control 1 Register"
|
|
bitfld.long 0x04 4.--6. " STEP_SIZE_SDR104_HS200 ,TAP_VAL is incremented by step_size for every tuning iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " STEP_SIZE_SDR50 ,TAP_VAL is incremented by step_size for every tuning iteration" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1C8++0x07
|
|
line.long 0x00 "VENDOR_TUNING_STATUS0_0,Vendor Tuning Status 0 Register"
|
|
line.long 0x04 "VENDOR_TUNING_STATUS1_0,Vendor Tuning Status 1 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PASS_WINDOW_END_BEFORE_FINE_TUNING , End tap value of best PASS window found by scan FSM"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PASS_WINDOW_START_BEFORE_FINE_TUNING ,Start tap value of best PASS window found by scan FSM"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " PASS_WINDOW_END_AFTER_FINE_TUNING ,End tap value of best PASS window after fine tuning"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PASS_WINDOW_START_AFTER_FINE_TUNING ,Start tap value of best PASS window after fine tuning"
|
|
textline " "
|
|
endif
|
|
width 28.
|
|
group.long 0x1D0++0x0F
|
|
line.long 0x00 "VENDOR_CLK_GATE_HYST_CNT_0,Vendor Clock Gating Hysteresis Counter Initial Value"
|
|
bitfld.long 0x00 0.--5. " CLK_COUNT ,CLK count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "VENDOR_PRESET_VAL0_0,Vendor Preset Value Register 0"
|
|
hexmask.long.word 0x04 20.--29. 1. " SDCLK_FREQ_SEL_HIGH_SPEED ,10-bit divider value to generate an SD clock in default speed mode (<50 MHz)"
|
|
hexmask.long.word 0x04 10.--19. 1. " SDCLK_FREQ_SEL_DEFAULT ,10-bit divider value to generate an SD clock in default speed mode (<25 MHz)"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--9. 1. " SDCLK_FREQ_SEL_INIT ,10-bit divider value to generate the desired SD clock frequency during initialization"
|
|
line.long 0x08 "VENDOR_PRESET_VAL1_0,Vendor Preset Value Register 1"
|
|
hexmask.long.word 0x08 20.--29. 1. " SDCLK_FREQ_SEL_SDR50 ,10-bit divider value to generate the SD clock in SDR50 mode"
|
|
hexmask.long.word 0x08 10.--19. 1. " SDCLK_FREQ_SEL_SDR25 ,10-bit divider value to generate the SD clock in SDR25 mode"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--9. 1. " SDCLK_FREQ_SEL_SDR12 ,10-bit divider value to generate the SD clock in SDR12 mode"
|
|
line.long 0x0C "VENDOR_PRESET_VAL2_0,Vendor Preset Value Register 2"
|
|
hexmask.long.word 0x0C 10.--19. 1. " SDCLK_FREQ_SEL_DDR50 ,10-bit divider value to generate the SD clock in DDR50 mode"
|
|
hexmask.long.word 0x0C 0.--9. 1. " SDCLK_FREQ_SEL_SDR104 ,10-bit divider value to generate the SD clock in SDR104 mode"
|
|
sif cpuis("TEGRAX2")
|
|
if (((d.l(ad:0x700B4600+0x1E4))&0x20000000)==0x20000000)
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_E_PBIAS_BUF ,Enables internally generated bias levels for driver PMOS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Select different bias levels for driver PMOS when E_PBIAS_BUF=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_E_PBIAS_BUF ,Enables internally generated bias levels for driver PMOS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
hexmask.long.byte 0x00 20.--26. 1. " COMP_PAD_DRVUP_OVR ,Used to drive DRVUP input of COMP pad"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--18. 1. " COMP_PAD_DRVDN_OVR ,Used to drive DRVDN input of COMP pad"
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Select different bias levels for driver PMOS when E_PBIAS_BUF=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
elif cpuis("TEGRAX1")
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " COMP_PAD_REG_ON ,Turns ON regulator in comp pad" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " COMP_PAD_DRV_TYPE ,Used to control drv_type input of BDSDMEMLVCOMP_C pad" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 10. " COMP_PAD_E_TEST_OUT ,Used to control e_test_out input of COMP pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP_PAD_TEST_SEL ,Used to control test_sel input of COMP pad" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,Used to control vref_sel input of COMP pad" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if (((d.l(ad:0x700B4600+0x1E4))&0x20000000)==0x20000000)
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 29.--30. " PU_PAD_DRV_TYPE ,Pu pad drv type" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " PD_PAD_DRV_TYPE ,Pd pad drv type" "0,1,2,3"
|
|
bitfld.long 0x00 11. " PU_PAD_E_TEST_OUT ,Pu pad E test out" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PD_PAD_E_TEST_OUT ,Pd pad E test out" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " PU_PAD_TEST_SEL ,pu pad test sel" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PD_PAD_TEST_SEL ,Pd pad test sel" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,sdmmc2tmc cfg Sdmemcomp vref sel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SDMEMCOMPPADCTRL_0,SDMEMCOMP Pad Control Register"
|
|
bitfld.long 0x00 31. " PAD_E_INPUT_OR_E_PWRD ,Used to control E_INPUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 29.--30. " PU_PAD_DRV_TYPE ,PU PAD DRV TYPE" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " PD_PAD_DRV_TYPE ,PD PAD DRV TYPE" "0,1,2,3"
|
|
hexmask.long.byte 0x00 20.--26. 1. " CFG_SDMEMCOMP_DRVUP ,SDMMC pads drive up/down control"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--18. 1. " CFG_SDMEMCOMP_DRVDN ,SDMMC pads drive up/down control"
|
|
bitfld.long 0x00 11. " PU_PAD_E_TEST_OUT ,PU PAD E TEST OUT" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PD_PAD_E_TEST_OUT ,PD_PAD_E_TEST_OUT" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " PU_PAD_TEST_SEL ,PU PAD TEST SEL" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PD_PAD_TEST_SEL ,PD PAD TEST SEL" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " SDMMC2TMC_CFG_SDMEMCOMP_VREF_SEL ,SDMMC2TMC CFG SDMEMCOMP VREF SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long 0x1E4++0x07
|
|
line.long 0x00 "AUTO_CAL_CFG_0,SDMEMCOMP Pad Auto-Calibration Settings"
|
|
bitfld.long 0x00 31. " AUTO_CAL_START ,Calibration state machine" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " AUTO_CAL_OVERRIDE ,AUTOCAL override" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 29. " AUTO_CAL_ENABLE ,AUTOCAL enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " AUTO_CAL_SLW_OVERRIDE ,AUTOCAL slew rate override" "Normal,Override"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " AUTO_CAL_STEP ,Calibration step interval" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PD_OFFSET ,2's complement offset for pull-down value"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PU_OFFSET ,2's complement offset for pull-up value"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
else
|
|
group.long 0x1E8++0x07
|
|
line.long 0x00 "AUTO_CAL_INTERVAL_0,SDMEMCOMP Pad Calibration Interval"
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "AUTO_CAL_STATUS_0,SDMEMCOMP Pad Calibration Status"
|
|
bitfld.long 0x00 31. " AUTO_CAL_ACTIVE ,Auto cal active" "Inactive,Active"
|
|
hexmask.long.byte 0x00 24.--30. 1. " AUTO_CAL_PULLDOWN_ADJ ,Pulldown code sent to pads"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--22. 1. " AUTO_CAL_PULLUP_ADJ ,Pullup code sent to pads"
|
|
hexmask.long.byte 0x00 8.--14. 1. " AUTO_CAL_PULLDOWN ,Pulldown code generated by auto-calibration"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " AUTO_CAL_PULLUP ,Pullup code generated by auto-calibration"
|
|
endif
|
|
sif cpuis("TEGRAX1")
|
|
group.long 0x1F0++0x07
|
|
line.long 0x00 "IO_SPARE_0,Memory Client Interface FIFO Control"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPARE_OUT ,PROD value"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPARE_IN ,PROD value"
|
|
endif
|
|
sif cpuis("TEGRAX2")
|
|
textline " "
|
|
group.long 0x1FC++0x0B
|
|
line.long 0x00 "CIF2AXI_CTRL_0,SD/MMC CIF2AXI Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MC_WRITE_REQ_STREAM_ID ,MC write transaction stream ID"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MC_READ_REQ_STREAM_ID ,MC read transaction stream ID"
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "TZ_DMA_CTRL_0,SD/MMC DMA Requests Security Attribute Control Register"
|
|
bitfld.long 0x00 1. " MC_WRITE_REQ_TZ_ACCESS_EN ,MC_WRITE_REQ_TZ_ACCESS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MC_READ_REQ_TZ_ACCESS_EN ,MC_READ_REQ_TZ_ACCESS enable" "Disabled,Enabled"
|
|
line.long 0x04 "VENDOR_MISC_CNTRL3_0,Misc Vendor Control Register 3"
|
|
bitfld.long 0x04 30. " STOP_TRIM_IN_CLK_DURING_TUNING ,Stops rx clk trimmer and rx FIFOs input clock during tuning" "Not stopped,Stopped"
|
|
bitfld.long 0x04 24.--29. " TUNING_TRIMMER_RECOVERY_TIME ,TUNING TRIMMER RECOVERY TIME" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " E_DIFF_DQ , Diff/Vref rx selection for DAT[7:0]"
|
|
bitfld.long 0x04 4. " E_DIFF_CMD ,Diff/Vref rx selection for CMD" "Stopped,Not stopped"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DAT_OE_POSTAMBLE_EN ,DAT pads output driver one cycle after disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " DAT_OE_PREAMBLE_EN ,DAT pads output driver one cycle before enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CMD_OE_POSTAMBLE_EN ,CMD pad output driver one cycle after disable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CMD_OE_PREAMBLE_EN ,CMD pad output driver one cycle before enable" "Disabled,Enabled"
|
|
group.long 0x20C++0x07
|
|
line.long 0x00 "VENDOR_MISC_CNTRL4_0,Misc Vendor Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " SDMMC_SPARE3 ,Spare register bits with reset value of 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDMMC_SPARE2 ,Spare register bits with reset value of 0"
|
|
else
|
|
group.long 0x1F4++0x07
|
|
line.long 0x00 "SDMMC_MCCIF_FIFOCTRL_0,Memory Client Interface FIFO Control"
|
|
bitfld.long 0x00 20. " SDMMC_RCLK_OVR_MODE ,SDMMC RCLK OVR MODE" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SDMMC_WCLK_OVR_MODE ,SDMMC WCLK OVR MODE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SDMMC_CCLK_OVERRIDE ,SDMMC CCLK OVERRIDE" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SDMMC_RCLK_OVERRIDE ,SDMMC RCLK OVERRIDE" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SDMMC_WCLK_OVERRIDE ,SDMMC WCLK OVERRIDE" "Disabled,Enabled"
|
|
line.long 0x04 "TIMEOUT_WCOAL_SDMMC_0,Write Coalescing Time-Out Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SDMMCW_WCOAL_TMVAL ,SDMMCW WCOAL TMVAL"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SATA Controller"
|
|
tree "IPFS registers"
|
|
base ad:0x70020000
|
|
width 19.
|
|
tree "Vectors"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "AXI_BAR0_SZ_0,The Size Of The Address Range Associated With BAR0"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR0_SIZE ,The size of the address range associated with BAR0 in 4K increments"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "AXI_BAR1_SZ_0,The Size Of The Address Range Associated With BAR1"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR1_SIZE ,The size of the address range associated with BAR1 in 4K increments"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "AXI_BAR2_SZ_0,The Size Of The Address Range Associated With BAR2"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR2_SIZE ,The size of the address range associated with BAR2 in 4K increments"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "AXI_BAR3_SZ_0,The Size Of The Address Range Associated With BAR3"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR3_SIZE ,The size of the address range associated with BAR3 in 4K increments"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "AXI_BAR4_SZ_0,The Size Of The Address Range Associated With BAR4"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR4_SIZE ,The size of the address range associated with BAR4 in 4K increments"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "AXI_BAR5_SZ_0,The Size Of The Address Range Associated With BAR5"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR5_SIZE ,The size of the address range associated with BAR5 in 4K increments"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "AXI_BAR6_SZ_0,The Size Of The Address Range Associated With BAR6"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR6_SIZE ,The size of the address range associated with BAR6 in 4K increments"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "AXI_BAR7_SZ_0,The Size Of The Address Range Associated With BAR7"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR7_SIZE ,The size of the address range associated with BAR7 in 4K increments"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "AXI_BAR0_START_0,The Start Of AXI Address Space For BAR0"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR0_START ,The start of the AXI address space for BAR0"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "AXI_BAR1_START_0,The Start Of AXI Address Space For BAR1"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR1_START ,The start of the AXI address space for BAR1"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "AXI_BAR2_START_0,The Start Of AXI Address Space For BAR2"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR2_START ,The start of the AXI address space for BAR2"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "AXI_BAR3_START_0,The Start Of AXI Address Space For BAR3"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR3_START ,The start of the AXI address space for BAR3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "AXI_BAR4_START_0,The Start Of AXI Address Space For BAR4"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR4_START ,The start of the AXI address space for BAR4"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "AXI_BAR5_START_0,The Start Of AXI Address Space For BAR5"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR5_START ,The start of the AXI address space for BAR5"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "AXI_BAR6_START_0,The Start Of AXI Address Space For BAR6"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR6_START ,The start of the AXI address space for BAR6"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "AXI_BAR7_START_0,The Start Of AXI Address Space For BAR7"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR7_START ,The start of the AXI address space for BAR7"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FPCI_BAR0_0,FPCI BAR0"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR0_START ,The start of FPCI address space mapped into the BAR0 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR0_ACCESS_TYPE ,Address region access type" "Memory-mapped,I/O or config"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FPCI_BAR1_0,FPCI BAR1"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR1_START ,The start of FPCI address space mapped into the BAR1 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR1_ACCESS_TYPE ,Address region access type" "Memory-mapped,I/O or config"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FPCI_BAR2_0,FPCI BAR2"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR2_START ,The start of FPCI address space mapped into the BAR2 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR2_ACCESS_TYPE ,Address region access type" "Memory-mapped,I/O or config"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "FPCI_BAR3_0,FPCI BAR3"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR3_START ,The start of FPCI address space mapped into the BAR3 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR3_ACCESS_TYPE ,Address region access type" "Memory-mapped,I/O or config"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "FPCI_BAR4_0,FPCI BAR4"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR4_START ,The start of FPCI address space mapped into the BAR4 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR4_ACCESS_TYPE ,Address region access type" "Memory-mapped,I/O or config"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "FPCI_BAR5_0,FPCI BAR5"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR5_START ,The start of FPCI address space mapped into the BAR5 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR5_ACCESS_TYPE ,Address region access type" "Memory-mapped,I/O or config"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "FPCI_BAR6_0,FPCI BAR6"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR6_START ,The start of FPCI address space mapped into the BAR6 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR6_ACCESS_TYPE ,Address region access type" "Memory-mapped,I/O or config"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "FPCI_BAR7_0,FPCI BAR7"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR7_START ,The start of FPCI address space mapped into the BAR7 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR7_ACCESS_TYPE ,Address region access type" "Memory-mapped,I/O or config"
|
|
group.long 0xC0++0x0B
|
|
line.long 0x00 "MSI_BAR_SZ_0,MSI BAR Size"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " MSI_BAR_SIZE ,The size of the address range associated with MSI BAR is in 4K increments"
|
|
line.long 0x04 "MSI_AXI_BAR_ST_0,MSI AXI BAR Start"
|
|
hexmask.long.tbyte 0x04 12.--31. 0x10 " MSI_AXI_BAR_START ,The start of the upstream AXI address space for MSI BAR"
|
|
line.long 0x08 "MSI_FPCI_BAR_ST_0,MSI FPCI BAR Start"
|
|
hexmask.long 0x08 4.--31. 0x10 " MSI_FPCI_BAR_START ,The start of the upstream FPCI address space for MSI BAR"
|
|
tree.end
|
|
width 12.
|
|
tree "MSI Vector registers"
|
|
width 12.
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "MSI_VEC0_0,SATA MSI Vector Register 0"
|
|
eventfld.long 0x00 31. " MSI_VECTOR[31] ,MSI vector 31" "No MSI,MSI sent"
|
|
eventfld.long 0x00 30. " [30] ,MSI vector 30" "No MSI,MSI sent"
|
|
eventfld.long 0x00 29. " [29] ,MSI vector 29" "No MSI,MSI sent"
|
|
eventfld.long 0x00 28. " [28] ,MSI vector 28" "No MSI,MSI sent"
|
|
eventfld.long 0x00 27. " [27] ,MSI vector 27" "No MSI,MSI sent"
|
|
eventfld.long 0x00 26. " [26] ,MSI vector 26" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x00 25. " [25] ,MSI vector 25" "No MSI,MSI sent"
|
|
eventfld.long 0x00 24. " [24] ,MSI vector 24" "No MSI,MSI sent"
|
|
eventfld.long 0x00 23. " [23] ,MSI vector 23" "No MSI,MSI sent"
|
|
eventfld.long 0x00 22. " [22] ,MSI vector 22" "No MSI,MSI sent"
|
|
eventfld.long 0x00 21. " [21] ,MSI vector 21" "No MSI,MSI sent"
|
|
eventfld.long 0x00 20. " [20] ,MSI vector 20" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x00 19. " [19] ,MSI vector 19" "No MSI,MSI sent"
|
|
eventfld.long 0x00 18. " [18] ,MSI vector 18" "No MSI,MSI sent"
|
|
eventfld.long 0x00 17. " [17] ,MSI vector 17" "No MSI,MSI sent"
|
|
eventfld.long 0x00 16. " [16] ,MSI vector 16" "No MSI,MSI sent"
|
|
eventfld.long 0x00 15. " [15] ,MSI vector 15" "No MSI,MSI sent"
|
|
eventfld.long 0x00 14. " [14] ,MSI vector 14" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x00 13. " [13] ,MSI vector 13" "No MSI,MSI sent"
|
|
eventfld.long 0x00 12. " [12] ,MSI vector 12" "No MSI,MSI sent"
|
|
eventfld.long 0x00 11. " [11] ,MSI vector 11" "No MSI,MSI sent"
|
|
eventfld.long 0x00 10. " [10] ,MSI vector 10" "No MSI,MSI sent"
|
|
eventfld.long 0x00 9. " [9] ,MSI vector 9" "No MSI,MSI sent"
|
|
eventfld.long 0x00 8. " [8] ,MSI vector 8" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x00 7. " [7] ,MSI vector 7" "No MSI,MSI sent"
|
|
eventfld.long 0x00 6. " [6] ,MSI vector 6" "No MSI,MSI sent"
|
|
eventfld.long 0x00 5. " [5] ,MSI vector 5" "No MSI,MSI sent"
|
|
eventfld.long 0x00 4. " [4] ,MSI vector 4" "No MSI,MSI sent"
|
|
eventfld.long 0x00 3. " [3] ,MSI vector 3" "No MSI,MSI sent"
|
|
eventfld.long 0x00 2. " [2] ,MSI vector 2" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x00 1. " [1] ,MSI vector 1" "No MSI,MSI sent"
|
|
eventfld.long 0x00 0. " [0] ,MSI vector 0" "No MSI,MSI sent"
|
|
line.long 0x04 "MSI_VEC1_0,SATA MSI Vector Register 1"
|
|
eventfld.long 0x04 31. " MSI_VECTOR[63] ,MSI vector 63" "No MSI,MSI sent"
|
|
eventfld.long 0x04 30. " [62] ,MSI vector 62" "No MSI,MSI sent"
|
|
eventfld.long 0x04 29. " [61] ,MSI vector 61" "No MSI,MSI sent"
|
|
eventfld.long 0x04 28. " [60] ,MSI vector 60" "No MSI,MSI sent"
|
|
eventfld.long 0x04 27. " [59] ,MSI vector 59" "No MSI,MSI sent"
|
|
eventfld.long 0x04 26. " [58] ,MSI vector 58" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x04 25. " [57] ,MSI vector 57" "No MSI,MSI sent"
|
|
eventfld.long 0x04 24. " [56] ,MSI vector 56" "No MSI,MSI sent"
|
|
eventfld.long 0x04 23. " [55] ,MSI vector 55" "No MSI,MSI sent"
|
|
eventfld.long 0x04 22. " [54] ,MSI vector 54" "No MSI,MSI sent"
|
|
eventfld.long 0x04 21. " [53] ,MSI vector 53" "No MSI,MSI sent"
|
|
eventfld.long 0x04 20. " [52] ,MSI vector 52" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x04 19. " [51] ,MSI vector 51" "No MSI,MSI sent"
|
|
eventfld.long 0x04 18. " [50] ,MSI vector 50" "No MSI,MSI sent"
|
|
eventfld.long 0x04 17. " [49] ,MSI vector 49" "No MSI,MSI sent"
|
|
eventfld.long 0x04 16. " [48] ,MSI vector 48" "No MSI,MSI sent"
|
|
eventfld.long 0x04 15. " [47] ,MSI vector 47" "No MSI,MSI sent"
|
|
eventfld.long 0x04 14. " [46] ,MSI vector 46" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x04 13. " [45] ,MSI vector 45" "No MSI,MSI sent"
|
|
eventfld.long 0x04 12. " [44] ,MSI vector 44" "No MSI,MSI sent"
|
|
eventfld.long 0x04 11. " [43] ,MSI vector 43" "No MSI,MSI sent"
|
|
eventfld.long 0x04 10. " [42] ,MSI vector 42" "No MSI,MSI sent"
|
|
eventfld.long 0x04 9. " [41] ,MSI vector 41" "No MSI,MSI sent"
|
|
eventfld.long 0x04 8. " [40] ,MSI vector 40" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x04 7. " [39] ,MSI vector 39" "No MSI,MSI sent"
|
|
eventfld.long 0x04 6. " [38] ,MSI vector 38" "No MSI,MSI sent"
|
|
eventfld.long 0x04 5. " [37] ,MSI vector 37" "No MSI,MSI sent"
|
|
eventfld.long 0x04 4. " [36] ,MSI vector 36" "No MSI,MSI sent"
|
|
eventfld.long 0x04 3. " [35] ,MSI vector 35" "No MSI,MSI sent"
|
|
eventfld.long 0x04 2. " [34] ,MSI vector 34" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x04 1. " [33] ,MSI vector 33" "No MSI,MSI sent"
|
|
eventfld.long 0x04 0. " [32] ,MSI vector 32" "No MSI,MSI sent"
|
|
line.long 0x08 "MSI_VEC2_0,SATA MSI Vector Register 2"
|
|
eventfld.long 0x08 31. " MSI_VECTOR[95] ,MSI vector 95" "No MSI,MSI sent"
|
|
eventfld.long 0x08 30. " [94] ,MSI vector 94" "No MSI,MSI sent"
|
|
eventfld.long 0x08 29. " [93] ,MSI vector 93" "No MSI,MSI sent"
|
|
eventfld.long 0x08 28. " [92] ,MSI vector 92" "No MSI,MSI sent"
|
|
eventfld.long 0x08 27. " [91] ,MSI vector 91" "No MSI,MSI sent"
|
|
eventfld.long 0x08 26. " [90] ,MSI vector 90" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x08 25. " [89] ,MSI vector 89" "No MSI,MSI sent"
|
|
eventfld.long 0x08 24. " [88] ,MSI vector 88" "No MSI,MSI sent"
|
|
eventfld.long 0x08 23. " [87] ,MSI vector 87" "No MSI,MSI sent"
|
|
eventfld.long 0x08 22. " [86] ,MSI vector 86" "No MSI,MSI sent"
|
|
eventfld.long 0x08 21. " [85] ,MSI vector 85" "No MSI,MSI sent"
|
|
eventfld.long 0x08 20. " [84] ,MSI vector 84" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x08 19. " [83] ,MSI vector 83" "No MSI,MSI sent"
|
|
eventfld.long 0x08 18. " [82] ,MSI vector 82" "No MSI,MSI sent"
|
|
eventfld.long 0x08 17. " [81] ,MSI vector 81" "No MSI,MSI sent"
|
|
eventfld.long 0x08 16. " [80] ,MSI vector 80" "No MSI,MSI sent"
|
|
eventfld.long 0x08 15. " [79] ,MSI vector 79" "No MSI,MSI sent"
|
|
eventfld.long 0x08 14. " [78] ,MSI vector 78" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x08 13. " [77] ,MSI vector 77" "No MSI,MSI sent"
|
|
eventfld.long 0x08 12. " [76] ,MSI vector 76" "No MSI,MSI sent"
|
|
eventfld.long 0x08 11. " [75] ,MSI vector 75" "No MSI,MSI sent"
|
|
eventfld.long 0x08 10. " [74] ,MSI vector 74" "No MSI,MSI sent"
|
|
eventfld.long 0x08 9. " [73] ,MSI vector 73" "No MSI,MSI sent"
|
|
eventfld.long 0x08 8. " [72] ,MSI vector 72" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x08 7. " [71] ,MSI vector 71" "No MSI,MSI sent"
|
|
eventfld.long 0x08 6. " [70] ,MSI vector 70" "No MSI,MSI sent"
|
|
eventfld.long 0x08 5. " [69] ,MSI vector 69" "No MSI,MSI sent"
|
|
eventfld.long 0x08 4. " [68] ,MSI vector 68" "No MSI,MSI sent"
|
|
eventfld.long 0x08 3. " [67] ,MSI vector 67" "No MSI,MSI sent"
|
|
eventfld.long 0x08 2. " [66] ,MSI vector 66" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x08 1. " [65] ,MSI vector 65" "No MSI,MSI sent"
|
|
eventfld.long 0x08 0. " [64] ,MSI vector 64" "No MSI,MSI sent"
|
|
line.long 0x0C "MSI_VEC3_0,SATA MSI Vector Register 3"
|
|
eventfld.long 0x0C 31. " MSI_VECTOR[127] ,MSI vector 127" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 30. " [126] ,MSI vector 126" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 29. " [125] ,MSI vector 125" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 28. " [124] ,MSI vector 124" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 27. " [123] ,MSI vector 123" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 26. " [122] ,MSI vector 122" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " [121] ,MSI vector 121" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 24. " [120] ,MSI vector 120" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 23. " [119] ,MSI vector 119" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 22. " [118] ,MSI vector 118" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 21. " [117] ,MSI vector 117" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 20. " [116] ,MSI vector 116" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " [115] ,MSI vector 115" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 18. " [114] ,MSI vector 114" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 17. " [113] ,MSI vector 113" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 16. " [112] ,MSI vector 112" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 15. " [111] ,MSI vector 111" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 14. " [110] ,MSI vector 110" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x0C 13. " [109] ,MSI vector 109" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 12. " [108] ,MSI vector 108" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 11. " [107] ,MSI vector 107" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 10. " [106] ,MSI vector 106" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 9. " [105] ,MSI vector 105" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 8. " [104] ,MSI vector 104" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " [103] ,MSI vector 103" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 6. " [102] ,MSI vector 102" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 5. " [101] ,MSI vector 101" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 4. " [100] ,MSI vector 100" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 3. " [99] ,MSI vector 99" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 2. " [98] ,MSI vector 98" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " [97] ,MSI vector 97" "No MSI,MSI sent"
|
|
eventfld.long 0x0C 0. " [96] ,MSI vector 96" "No MSI,MSI sent"
|
|
line.long 0x10 "MSI_VEC4_0,SATA MSI Vector Register 4"
|
|
eventfld.long 0x10 31. " MSI_VECTOR[159] ,MSI vector 159" "No MSI,MSI sent"
|
|
eventfld.long 0x10 30. " [158] ,MSI vector 158" "No MSI,MSI sent"
|
|
eventfld.long 0x10 29. " [157] ,MSI vector 157" "No MSI,MSI sent"
|
|
eventfld.long 0x10 28. " [156] ,MSI vector 156" "No MSI,MSI sent"
|
|
eventfld.long 0x10 27. " [155] ,MSI vector 155" "No MSI,MSI sent"
|
|
eventfld.long 0x10 26. " [154] ,MSI vector 154" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x10 25. " [153] ,MSI vector 153" "No MSI,MSI sent"
|
|
eventfld.long 0x10 24. " [152] ,MSI vector 152" "No MSI,MSI sent"
|
|
eventfld.long 0x10 23. " [151] ,MSI vector 151" "No MSI,MSI sent"
|
|
eventfld.long 0x10 22. " [150] ,MSI vector 150" "No MSI,MSI sent"
|
|
eventfld.long 0x10 21. " [149] ,MSI vector 149" "No MSI,MSI sent"
|
|
eventfld.long 0x10 20. " [148] ,MSI vector 148" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x10 19. " [147] ,MSI vector 147" "No MSI,MSI sent"
|
|
eventfld.long 0x10 18. " [146] ,MSI vector 146" "No MSI,MSI sent"
|
|
eventfld.long 0x10 17. " [145] ,MSI vector 145" "No MSI,MSI sent"
|
|
eventfld.long 0x10 16. " [144] ,MSI vector 144" "No MSI,MSI sent"
|
|
eventfld.long 0x10 15. " [143] ,MSI vector 143" "No MSI,MSI sent"
|
|
eventfld.long 0x10 14. " [142] ,MSI vector 142" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x10 13. " [141] ,MSI vector 141" "No MSI,MSI sent"
|
|
eventfld.long 0x10 12. " [140] ,MSI vector 140" "No MSI,MSI sent"
|
|
eventfld.long 0x10 11. " [139] ,MSI vector 139" "No MSI,MSI sent"
|
|
eventfld.long 0x10 10. " [138] ,MSI vector 138" "No MSI,MSI sent"
|
|
eventfld.long 0x10 9. " [137] ,MSI vector 137" "No MSI,MSI sent"
|
|
eventfld.long 0x10 8. " [136] ,MSI vector 136" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x10 7. " [135] ,MSI vector 135" "No MSI,MSI sent"
|
|
eventfld.long 0x10 6. " [134] ,MSI vector 134" "No MSI,MSI sent"
|
|
eventfld.long 0x10 5. " [133] ,MSI vector 133" "No MSI,MSI sent"
|
|
eventfld.long 0x10 4. " [132] ,MSI vector 132" "No MSI,MSI sent"
|
|
eventfld.long 0x10 3. " [131] ,MSI vector 131" "No MSI,MSI sent"
|
|
eventfld.long 0x10 2. " [130] ,MSI vector 130" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x10 1. " [129] ,MSI vector 129" "No MSI,MSI sent"
|
|
eventfld.long 0x10 0. " [128] ,MSI vector 128" "No MSI,MSI sent"
|
|
line.long 0x14 "MSI_VEC5_0,SATA MSI Vector Register 5"
|
|
eventfld.long 0x14 31. " MSI_VECTOR[191] ,MSI vector 191" "No MSI,MSI sent"
|
|
eventfld.long 0x14 30. " [190] ,MSI vector 190" "No MSI,MSI sent"
|
|
eventfld.long 0x14 29. " [189] ,MSI vector 189" "No MSI,MSI sent"
|
|
eventfld.long 0x14 28. " [188] ,MSI vector 188" "No MSI,MSI sent"
|
|
eventfld.long 0x14 27. " [187] ,MSI vector 187" "No MSI,MSI sent"
|
|
eventfld.long 0x14 26. " [186] ,MSI vector 186" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x14 25. " [185] ,MSI vector 185" "No MSI,MSI sent"
|
|
eventfld.long 0x14 24. " [184] ,MSI vector 184" "No MSI,MSI sent"
|
|
eventfld.long 0x14 23. " [183] ,MSI vector 183" "No MSI,MSI sent"
|
|
eventfld.long 0x14 22. " [182] ,MSI vector 182" "No MSI,MSI sent"
|
|
eventfld.long 0x14 21. " [181] ,MSI vector 181" "No MSI,MSI sent"
|
|
eventfld.long 0x14 20. " [180] ,MSI vector 180" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x14 19. " [179] ,MSI vector 179" "No MSI,MSI sent"
|
|
eventfld.long 0x14 18. " [178] ,MSI vector 178" "No MSI,MSI sent"
|
|
eventfld.long 0x14 17. " [177] ,MSI vector 177" "No MSI,MSI sent"
|
|
eventfld.long 0x14 16. " [176] ,MSI vector 176" "No MSI,MSI sent"
|
|
eventfld.long 0x14 15. " [175] ,MSI vector 175" "No MSI,MSI sent"
|
|
eventfld.long 0x14 14. " [174] ,MSI vector 174" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x14 13. " [173] ,MSI vector 173" "No MSI,MSI sent"
|
|
eventfld.long 0x14 12. " [172] ,MSI vector 172" "No MSI,MSI sent"
|
|
eventfld.long 0x14 11. " [171] ,MSI vector 171" "No MSI,MSI sent"
|
|
eventfld.long 0x14 10. " [170] ,MSI vector 170" "No MSI,MSI sent"
|
|
eventfld.long 0x14 9. " [169] ,MSI vector 169" "No MSI,MSI sent"
|
|
eventfld.long 0x14 8. " [168] ,MSI vector 168" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x14 7. " [167] ,MSI vector 167" "No MSI,MSI sent"
|
|
eventfld.long 0x14 6. " [166] ,MSI vector 166" "No MSI,MSI sent"
|
|
eventfld.long 0x14 5. " [165] ,MSI vector 165" "No MSI,MSI sent"
|
|
eventfld.long 0x14 4. " [164] ,MSI vector 164" "No MSI,MSI sent"
|
|
eventfld.long 0x14 3. " [163] ,MSI vector 163" "No MSI,MSI sent"
|
|
eventfld.long 0x14 2. " [162] ,MSI vector 162" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x14 1. " [161] ,MSI vector 161" "No MSI,MSI sent"
|
|
eventfld.long 0x14 0. " [160] ,MSI vector 160" "No MSI,MSI sent"
|
|
line.long 0x18 "MSI_VEC6_0,SATA MSI Vector Register 6"
|
|
eventfld.long 0x18 31. " MSI_VECTOR[223] ,MSI vector 223" "No MSI,MSI sent"
|
|
eventfld.long 0x18 30. " [222] ,MSI vector 222" "No MSI,MSI sent"
|
|
eventfld.long 0x18 29. " [221] ,MSI vector 221" "No MSI,MSI sent"
|
|
eventfld.long 0x18 28. " [220] ,MSI vector 220" "No MSI,MSI sent"
|
|
eventfld.long 0x18 27. " [219] ,MSI vector 219" "No MSI,MSI sent"
|
|
eventfld.long 0x18 26. " [218] ,MSI vector 218" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x18 25. " [217] ,MSI vector 217" "No MSI,MSI sent"
|
|
eventfld.long 0x18 24. " [216] ,MSI vector 216" "No MSI,MSI sent"
|
|
eventfld.long 0x18 23. " [215] ,MSI vector 215" "No MSI,MSI sent"
|
|
eventfld.long 0x18 22. " [214] ,MSI vector 214" "No MSI,MSI sent"
|
|
eventfld.long 0x18 21. " [213] ,MSI vector 213" "No MSI,MSI sent"
|
|
eventfld.long 0x18 20. " [212] ,MSI vector 212" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x18 19. " [211] ,MSI vector 211" "No MSI,MSI sent"
|
|
eventfld.long 0x18 18. " [210] ,MSI vector 210" "No MSI,MSI sent"
|
|
eventfld.long 0x18 17. " [209] ,MSI vector 209" "No MSI,MSI sent"
|
|
eventfld.long 0x18 16. " [208] ,MSI vector 208" "No MSI,MSI sent"
|
|
eventfld.long 0x18 15. " [207] ,MSI vector 207" "No MSI,MSI sent"
|
|
eventfld.long 0x18 14. " [206] ,MSI vector 206" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x18 13. " [205] ,MSI vector 205" "No MSI,MSI sent"
|
|
eventfld.long 0x18 12. " [204] ,MSI vector 204" "No MSI,MSI sent"
|
|
eventfld.long 0x18 11. " [203] ,MSI vector 203" "No MSI,MSI sent"
|
|
eventfld.long 0x18 10. " [202] ,MSI vector 202" "No MSI,MSI sent"
|
|
eventfld.long 0x18 9. " [201] ,MSI vector 201" "No MSI,MSI sent"
|
|
eventfld.long 0x18 8. " [200] ,MSI vector 200" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x18 7. " [199] ,MSI vector 199" "No MSI,MSI sent"
|
|
eventfld.long 0x18 6. " [198] ,MSI vector 198" "No MSI,MSI sent"
|
|
eventfld.long 0x18 5. " [197] ,MSI vector 197" "No MSI,MSI sent"
|
|
eventfld.long 0x18 4. " [196] ,MSI vector 196" "No MSI,MSI sent"
|
|
eventfld.long 0x18 3. " [195] ,MSI vector 195" "No MSI,MSI sent"
|
|
eventfld.long 0x18 2. " [194] ,MSI vector 194" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x18 1. " [193] ,MSI vector 193" "No MSI,MSI sent"
|
|
eventfld.long 0x18 0. " [192] ,MSI vector 192" "No MSI,MSI sent"
|
|
line.long 0x1C "MSI_VEC7_0,SATA MSI Vector Register 7"
|
|
eventfld.long 0x1C 31. " MSI_VECTOR[255] ,MSI vector 255" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 30. " [254] ,MSI vector 254" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 29. " [253] ,MSI vector 253" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 28. " [252] ,MSI vector 252" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 27. " [251] ,MSI vector 251" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 26. " [250] ,MSI vector 250" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x1C 25. " [249] ,MSI vector 249" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 24. " [248] ,MSI vector 248" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 23. " [247] ,MSI vector 247" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 22. " [246] ,MSI vector 246" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 21. " [245] ,MSI vector 245" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 20. " [244] ,MSI vector 244" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x1C 19. " [243] ,MSI vector 243" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 18. " [242] ,MSI vector 242" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 17. " [241] ,MSI vector 241" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 16. " [240] ,MSI vector 240" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 15. " [239] ,MSI vector 239" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 14. " [238] ,MSI vector 238" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x1C 13. " [237] ,MSI vector 237" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 12. " [236] ,MSI vector 236" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 11. " [235] ,MSI vector 235" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 10. " [234] ,MSI vector 234" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 9. " [233] ,MSI vector 233" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 8. " [232] ,MSI vector 232" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x1C 7. " [231] ,MSI vector 231" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 6. " [230] ,MSI vector 230" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 5. " [229] ,MSI vector 229" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 4. " [228] ,MSI vector 228" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 3. " [227] ,MSI vector 227" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 2. " [226] ,MSI vector 226" "No MSI,MSI sent"
|
|
textline " "
|
|
eventfld.long 0x1C 1. " [225] ,MSI vector 225" "No MSI,MSI sent"
|
|
eventfld.long 0x1C 0. " [224] ,MSI vector 224" "No MSI,MSI sent"
|
|
textline " "
|
|
width 15.
|
|
group.long 0x140++0x1F
|
|
line.long 0x00 "MSI_EN_VEC0_0,SATA MSI Vector Enable Register 0"
|
|
bitfld.long 0x00 31. " MSI_ENABLE_VECTOR[31] ,MSI vector enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,MSI vector enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,MSI vector enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,MSI vector enable 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,MSI vector enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,MSI vector enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [25] ,MSI vector enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,MSI vector enable 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,MSI vector enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,MSI vector enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,MSI vector enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,MSI vector enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,MSI vector enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,MSI vector enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,MSI vector enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,MSI vector enable 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,MSI vector enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,MSI vector enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,MSI vector enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,MSI vector enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,MSI vector enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,MSI vector enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,MSI vector enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,MSI vector enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,MSI vector enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,MSI vector enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,MSI vector enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,MSI vector enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,MSI vector enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,MSI vector enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,MSI vector enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,MSI vector enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "MSI_EN_VEC1_0,SATA MSI Vector Enable Register 1"
|
|
bitfld.long 0x04 31. " MSI_ENABLE_VECTOR[63] ,MSI vector enable 63" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,MSI vector enable 62" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,MSI vector enable 61" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,MSI vector enable 60" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " [59] ,MSI vector enable 59" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [58] ,MSI vector enable 58" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " [57] ,MSI vector enable 57" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,MSI vector enable 56" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " [55] ,MSI vector enable 55" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,MSI vector enable 54" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,MSI vector enable 53" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,MSI vector enable 52" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " [51] ,MSI vector enable 51" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,MSI vector enable 50" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,MSI vector enable 49" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,MSI vector enable 48" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " [47] ,MSI vector enable 47" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,MSI vector enable 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " [45] ,MSI vector enable 45" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,MSI vector enable 44" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " [43] ,MSI vector enable 43" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,MSI vector enable 42" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,MSI vector enable 41" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,MSI vector enable 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " [39] ,MSI vector enable 39" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,MSI vector enable 38" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,MSI vector enable 37" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,MSI vector enable 36" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " [35] ,MSI vector enable 35" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,MSI vector enable 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " [33] ,MSI vector enable 33" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,MSI vector enable 32" "Disabled,Enabled"
|
|
line.long 0x08 "MSI_EN_VEC2_0,SATA MSI Vector Enable Register 2"
|
|
bitfld.long 0x08 31. " MSI_ENABLE_VECTOR[95] ,MSI vector enable 95" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [94] ,MSI vector enable 94" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [93] ,MSI vector enable 93" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [92] ,MSI vector enable 92" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " [91] ,MSI vector enable 91" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [90] ,MSI vector enable 90" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " [89] ,MSI vector enable 89" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [88] ,MSI vector enable 88" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " [87] ,MSI vector enable 87" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,MSI vector enable 86" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,MSI vector enable 85" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,MSI vector enable 84" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " [83] ,MSI vector enable 83" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [82] ,MSI vector enable 82" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [81] ,MSI vector enable 81" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [80] ,MSI vector enable 80" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " [79] ,MSI vector enable 79" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,MSI vector enable 78" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " [77] ,MSI vector enable 77" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,MSI vector enable 76" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " [75] ,MSI vector enable 75" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,MSI vector enable 74" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,MSI vector enable 73" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [72] ,MSI vector enable 72" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " [71] ,MSI vector enable 71" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,MSI vector enable 70" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [69] ,MSI vector enable 69" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,MSI vector enable 68" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " [67] ,MSI vector enable 67" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,MSI vector enable 66" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " [65] ,MSI vector enable 65" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [64] ,MSI vector enable 64" "Disabled,Enabled"
|
|
line.long 0x0C "MSI_EN_VEC3_0,SATA MSI Vector Enable Register 3"
|
|
bitfld.long 0x0C 31. " MSI_ENABLE_VECTOR[127] ,MSI vector enable 127" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,MSI vector enable 126" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,MSI vector enable 125" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,MSI vector enable 124" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " [123] ,MSI vector enable 123" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [122] ,MSI vector enable 122" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " [121] ,MSI vector enable 121" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,MSI vector enable 120" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " [119] ,MSI vector enable 119" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,MSI vector enable 118" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,MSI vector enable 117" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,MSI vector enable 116" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " [115] ,MSI vector enable 115" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,MSI vector enable 114" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,MSI vector enable 113" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,MSI vector enable 112" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " [111] ,MSI vector enable 111" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [110] ,MSI vector enable 110" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " [109] ,MSI vector enable 109" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,MSI vector enable 108" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " [107] ,MSI vector enable 107" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,MSI vector enable 106" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [105] ,MSI vector enable 105" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,MSI vector enable 104" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " [103] ,MSI vector enable 103" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [102] ,MSI vector enable 102" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,MSI vector enable 101" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,MSI vector enable 100" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " [99] ,MSI vector enable 99" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [98] ,MSI vector enable 98" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " [97] ,MSI vector enable 97" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,MSI vector enable 96" "Disabled,Enabled"
|
|
line.long 0x10 "MSI_EN_VEC4_0,SATA MSI Vector Enable Register 4"
|
|
bitfld.long 0x10 31. " MSI_ENABLE_VECTOR[159] ,MSI vector enable 159" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " [158] ,MSI vector enable 158" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " [157] ,MSI vector enable 157" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " [156] ,MSI vector enable 156" "Disabled,Enabled"
|
|
bitfld.long 0x10 27. " [155] ,MSI vector enable 155" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " [154] ,MSI vector enable 154" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " [153] ,MSI vector enable 153" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " [152] ,MSI vector enable 152" "Disabled,Enabled"
|
|
bitfld.long 0x10 23. " [151] ,MSI vector enable 151" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " [150] ,MSI vector enable 150" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " [149] ,MSI vector enable 149" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " [148] ,MSI vector enable 148" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " [147] ,MSI vector enable 147" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " [146] ,MSI vector enable 146" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " [145] ,MSI vector enable 145" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " [144] ,MSI vector enable 144" "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " [143] ,MSI vector enable 143" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " [142] ,MSI vector enable 142" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " [141] ,MSI vector enable 141" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " [140] ,MSI vector enable 140" "Disabled,Enabled"
|
|
bitfld.long 0x10 11. " [139] ,MSI vector enable 139" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " [138] ,MSI vector enable 138" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " [137] ,MSI vector enable 137" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " [136] ,MSI vector enable 136" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " [135] ,MSI vector enable 135" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " [134] ,MSI vector enable 134" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " [133] ,MSI vector enable 133" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " [132] ,MSI vector enable 132" "Disabled,Enabled"
|
|
bitfld.long 0x10 3. " [131] ,MSI vector enable 131" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " [130] ,MSI vector enable 130" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " [129] ,MSI vector enable 129" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " [128] ,MSI vector enable 128" "Disabled,Enabled"
|
|
line.long 0x14 "MSI_EN_VEC5_0,SATA MSI Vector Enable Register 5"
|
|
bitfld.long 0x14 31. " MSI_ENABLE_VECTOR[191] ,MSI vector enable 191" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " [190] ,MSI vector enable 190" "Disabled,Enabled"
|
|
bitfld.long 0x14 29. " [189] ,MSI vector enable 189" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " [188] ,MSI vector enable 188" "Disabled,Enabled"
|
|
bitfld.long 0x14 27. " [187] ,MSI vector enable 187" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " [186] ,MSI vector enable 186" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " [185] ,MSI vector enable 185" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " [184] ,MSI vector enable 184" "Disabled,Enabled"
|
|
bitfld.long 0x14 23. " [183] ,MSI vector enable 183" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " [182] ,MSI vector enable 182" "Disabled,Enabled"
|
|
bitfld.long 0x14 21. " [181] ,MSI vector enable 181" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " [180] ,MSI vector enable 180" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " [179] ,MSI vector enable 179" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " [178] ,MSI vector enable 178" "Disabled,Enabled"
|
|
bitfld.long 0x14 17. " [177] ,MSI vector enable 177" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " [176] ,MSI vector enable 176" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " [175] ,MSI vector enable 175" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " [174] ,MSI vector enable 174" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " [173] ,MSI vector enable 173" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " [172] ,MSI vector enable 172" "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " [171] ,MSI vector enable 171" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " [170] ,MSI vector enable 170" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " [169] ,MSI vector enable 169" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " [168] ,MSI vector enable 168" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " [167] ,MSI vector enable 167" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " [166] ,MSI vector enable 166" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " [165] ,MSI vector enable 165" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " [164] ,MSI vector enable 164" "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " [163] ,MSI vector enable 163" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " [162] ,MSI vector enable 162" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " [161] ,MSI vector enable 161" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " [160] ,MSI vector enable 160" "Disabled,Enabled"
|
|
line.long 0x18 "MSI_EN_VEC6_0,SATA MSI Vector Enable Register 6"
|
|
bitfld.long 0x18 31. " MSI_ENABLE_VECTOR[223] ,MSI vector enable 223" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " [222] ,MSI vector enable 222" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " [221] ,MSI vector enable 221" "Disabled,Enabled"
|
|
bitfld.long 0x18 28. " [220] ,MSI vector enable 220" "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " [219] ,MSI vector enable 219" "Disabled,Enabled"
|
|
bitfld.long 0x18 26. " [218] ,MSI vector enable 218" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 25. " [217] ,MSI vector enable 217" "Disabled,Enabled"
|
|
bitfld.long 0x18 24. " [216] ,MSI vector enable 216" "Disabled,Enabled"
|
|
bitfld.long 0x18 23. " [215] ,MSI vector enable 215" "Disabled,Enabled"
|
|
bitfld.long 0x18 22. " [214] ,MSI vector enable 214" "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " [213] ,MSI vector enable 213" "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " [212] ,MSI vector enable 212" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 19. " [211] ,MSI vector enable 211" "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " [210] ,MSI vector enable 210" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " [209] ,MSI vector enable 209" "Disabled,Enabled"
|
|
bitfld.long 0x18 16. " [208] ,MSI vector enable 208" "Disabled,Enabled"
|
|
bitfld.long 0x18 15. " [207] ,MSI vector enable 207" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " [206] ,MSI vector enable 206" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 13. " [205] ,MSI vector enable 205" "Disabled,Enabled"
|
|
bitfld.long 0x18 12. " [204] ,MSI vector enable 204" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " [203] ,MSI vector enable 203" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " [202] ,MSI vector enable 202" "Disabled,Enabled"
|
|
bitfld.long 0x18 9. " [201] ,MSI vector enable 201" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " [200] ,MSI vector enable 200" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 7. " [199] ,MSI vector enable 199" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " [198] ,MSI vector enable 198" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " [197] ,MSI vector enable 197" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " [196] ,MSI vector enable 196" "Disabled,Enabled"
|
|
bitfld.long 0x18 3. " [195] ,MSI vector enable 195" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " [194] ,MSI vector enable 194" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " [193] ,MSI vector enable 193" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " [192] ,MSI vector enable 192" "Disabled,Enabled"
|
|
line.long 0x1C "MSI_EN_VEC7_0,SATA MSI Vector Enable Register 7"
|
|
bitfld.long 0x1C 31. " MSI_ENABLE_VECTOR[255] ,MSI vector enable 255" "Disabled,Enabled"
|
|
bitfld.long 0x1C 30. " [254] ,MSI vector enable 254" "Disabled,Enabled"
|
|
bitfld.long 0x1C 29. " [253] ,MSI vector enable 253" "Disabled,Enabled"
|
|
bitfld.long 0x1C 28. " [252] ,MSI vector enable 252" "Disabled,Enabled"
|
|
bitfld.long 0x1C 27. " [251] ,MSI vector enable 251" "Disabled,Enabled"
|
|
bitfld.long 0x1C 26. " [250] ,MSI vector enable 250" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 25. " [249] ,MSI vector enable 249" "Disabled,Enabled"
|
|
bitfld.long 0x1C 24. " [248] ,MSI vector enable 248" "Disabled,Enabled"
|
|
bitfld.long 0x1C 23. " [247] ,MSI vector enable 247" "Disabled,Enabled"
|
|
bitfld.long 0x1C 22. " [246] ,MSI vector enable 246" "Disabled,Enabled"
|
|
bitfld.long 0x1C 21. " [245] ,MSI vector enable 245" "Disabled,Enabled"
|
|
bitfld.long 0x1C 20. " [244] ,MSI vector enable 244" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " [243] ,MSI vector enable 243" "Disabled,Enabled"
|
|
bitfld.long 0x1C 18. " [242] ,MSI vector enable 242" "Disabled,Enabled"
|
|
bitfld.long 0x1C 17. " [241] ,MSI vector enable 241" "Disabled,Enabled"
|
|
bitfld.long 0x1C 16. " [240] ,MSI vector enable 240" "Disabled,Enabled"
|
|
bitfld.long 0x1C 15. " [239] ,MSI vector enable 239" "Disabled,Enabled"
|
|
bitfld.long 0x1C 14. " [238] ,MSI vector enable 238" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 13. " [237] ,MSI vector enable 237" "Disabled,Enabled"
|
|
bitfld.long 0x1C 12. " [236] ,MSI vector enable 236" "Disabled,Enabled"
|
|
bitfld.long 0x1C 11. " [235] ,MSI vector enable 235" "Disabled,Enabled"
|
|
bitfld.long 0x1C 10. " [234] ,MSI vector enable 234" "Disabled,Enabled"
|
|
bitfld.long 0x1C 9. " [233] ,MSI vector enable 233" "Disabled,Enabled"
|
|
bitfld.long 0x1C 8. " [232] ,MSI vector enable 232" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " [231] ,MSI vector enable 231" "Disabled,Enabled"
|
|
bitfld.long 0x1C 6. " [230] ,MSI vector enable 230" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " [229] ,MSI vector enable 229" "Disabled,Enabled"
|
|
bitfld.long 0x1C 4. " [228] ,MSI vector enable 228" "Disabled,Enabled"
|
|
bitfld.long 0x1C 3. " [227] ,MSI vector enable 227" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " [226] ,MSI vector enable 226" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " [225] ,MSI vector enable 225" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " [224] ,MSI vector enable 224" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
width 20.
|
|
tree "Configuration registers"
|
|
group.long 0x180++0x1F
|
|
line.long 0x00 "CONFIGURATION_0,Configuration"
|
|
bitfld.long 0x00 31. " CLKEN_OVERRIDE ,Override the clock enable in case of a malfunction" "Disabled,Enabled"
|
|
sif cpuis("TEGRAX1")
|
|
else
|
|
bitfld.long 0x00 19. " PW_NO_DEVSEL_ERR_CYA ,Disable detection of DECERR due to no DEVSEL" "No,Yes"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 18. " INITIATOR_READ_IDLE ,AFI upstream read status" "Busy,Idle"
|
|
rbitfld.long 0x00 17. " INITIATOR_WRITE_IDLE ,AFI upstream write status" "Busy,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WDATA_LEAD_CYA ,Enable the handling of write data ahead of requests on IPFS AXI" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WR_INTRLV_CYA ,Disable the handling of interleaved write requests on IPFS AXI" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " TARGET_READ_IDLE ,IPFS target read status" "Busy,Idle"
|
|
rbitfld.long 0x00 10. " TARGET_WRITE_IDLE ,IPFS target write status" "Busy,Idle"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " MSI_VEC_EMPTY ,MSI Vector registers status" "No empty,Empty"
|
|
bitfld.long 0x00 7. " UFPCI_MSIAW ,MSI After Write ordering rule" "Default behavior (MSIAW ordering),Interrupt whenever MSI is ready"
|
|
textline " "
|
|
bitfld.long 0x00 6. " UFPCI_PWPASSPW ,Send input to the upstream FPCI" "Whenever write is ready,Only when PW has retired"
|
|
bitfld.long 0x00 5. " UFPCI_PASSPW ,Allows the upstream FPCI reads to pass writes" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UFPCI_PWPASSNPW ,Allows the upstream FPCI PWs to pass NPW" "Not allowed,Allowed"
|
|
bitfld.long 0x00 3. " DFPCI_PWPASSNPW ,Allows the downstream FPCI PWs to pass NPW" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DFPCI_RSPPASSPW ,Allows the downstream FPCI responses to pass writes" "Not allowed,Allowed"
|
|
bitfld.long 0x00 1. " DFPCI_PASSPW ,Allow the downstream FPCI reads to pass writes" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN_FPCI ,Enable FPCI" "Disabled,Enabled"
|
|
line.long 0x04 "FPCI_ERROR_MASKS_0,SATAFPCI Error Masks"
|
|
bitfld.long 0x04 2. " MASK_FPCI_MASTER_ABORT ,Allows an FPCI error response indicates a Master Abort" "Return AXI OK,Forward error"
|
|
bitfld.long 0x04 1. " MASK_FPCI_DATA_ERROR ,Allows an FPCI error response indicates a Data Error" "Return AXI OK,Forward error"
|
|
bitfld.long 0x04 0. " MASK_FPCI_TARGET_ABORT ,Allows an FPCI error response indicates a Target Abort" "Return AXI OK,Forward error"
|
|
line.long 0x08 "INTR_MASK_0,Interrupt Masks"
|
|
bitfld.long 0x08 16. " IP_INT_MASK ,IP interrupt to the CPU complex gated by the mask" "0,1"
|
|
bitfld.long 0x08 8. " MSI_MASK ,MSI to the CPU complex gated by the mask" "0,1"
|
|
bitfld.long 0x08 0. " INT_MASK ,Interrupt to the CPU complex gated by the mask" "0,1"
|
|
line.long 0x0C "INTR_CODE_0,Interrupt Control"
|
|
bitfld.long 0x0C 0.--4. " INT_CODE ,Eight interrupt codes" "CLEAR,INI_SLVERR,INI_DECERR,TGT_SLVERR,TGT_DECERR,TGT_WRERR,,DFPCI_DECERR,AXI_DECERR,TIMEOUT,,,,,,SM_FATAL_ERROR,SM_NON_FATAL_ERROR,?..."
|
|
line.long 0x10 "INTR_SIGNATURE_0,Interrupt Signature"
|
|
hexmask.long 0x10 2.--31. 0x4 " INT_INFO ,Interrupt info (Address bits for interrupt codes)"
|
|
bitfld.long 0x10 0. " DIR ,Direction of the AXI/FPCI transaction" "Write,Read"
|
|
line.long 0x14 "UPPER_FPCI_ADDR_0,Upper FPCI Address"
|
|
hexmask.long.byte 0x14 0.--7. 0x01 " INT_INFO_UPPER ,Upper byte of the captured FPCI address (for interrupt code: 3, 4 or 7)"
|
|
line.long 0x18 "IPFS_INTR_ENABLE_0,IPFS Interrupt Enable"
|
|
bitfld.long 0x18 13. " EN_SM_NON_FATAL_ERROR ,Enable bit for interrupt code 15" "Disabled,Enabled"
|
|
bitfld.long 0x18 12. " EN_SM_FATAL_ERROR ,Enable bit for interrupt code 14" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " EN_FPCI_TIMEOUT ,Enable bit for interrupt code 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 6. " EN_AXI_DECERR ,Enable bit for interrupt code 8" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EN_DFPCI_DECERR ,Enable bit for interrupt code 7" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " EN_TGT_WRERR ,Enable bit for interrupt code 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 3. " EN_TGT_DECERR ,Enable bit for interrupt code 4" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " EN_TGT_SLVERR ,Enable bit for interrupt code 3" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " EN_INI_DECERR ,Enable bit for interrupt code 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0. " EN_INI_SLVERR ,Enable bit for interrupt code 1" "Disabled,Enabled"
|
|
line.long 0x1C "UFPCI_CONFIG_0,Upstream FPCI Configuration"
|
|
bitfld.long 0x1C 0.--4. " UNITID_T0C0 ,Upstream FPCI Unit ID for controller 0. HyperTransport (Upstream FPCI request)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x1A0++0x0B
|
|
line.long 0x00 "CFG_REVID_0,CFG_REVID Register"
|
|
rbitfld.long 0x00 19. " DEV2SM_NONISO_REQUEST_PEND ,There is a non-ISO request pending" "Not pending,Pending"
|
|
rbitfld.long 0x00 18. " DEV2SM_ISO_REQUEST_PEND ,There is an ISO request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12.--13. " STRAP_CPU_MODE ,MCP: Mode to send MSI" "NB_INTEL,NB_AMD,AMD,TMTA"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CFG_REVID_WRITE_ENABLE ,Enable to override the rev ID" "Clear,Set"
|
|
bitfld.long 0x00 10. " CFG_REVID_OVERRIDE ,Provides a way to override the current revision ID" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " DEV2LEG_NONCOH_REQUEST_PEND ,Tells the leg block that a non-coherent request is pending" "Not pending,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " DEV2LEG_COH_REQUEST_PEND ,Tells the leg block that a coherent request is pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " SM2DEV_FPCI_TIMEOUT_EN ,FPCI timeout enable bit for Controller" "Disabled,Enabled"
|
|
line.long 0x04 "FPCI_TIMEOUT_0,FPCI_TIMEOUT Register"
|
|
hexmask.long.tbyte 0x04 0.--19. 1. " SM2ALL_FPCI_TIMEOUT_THRESH ,Timeout threshold value for the FPCI bus"
|
|
line.long 0x08 "TOM_0,Top Of Memory Limit"
|
|
hexmask.long.word 0x08 16.--29. 1. " LEG2ALL_TOM2 ,Top of Memory Limit 2"
|
|
hexmask.long.word 0x08 0.--11. 1. " LEG2ALL_TOM1 ,Top of Memory Limit 1"
|
|
textline " "
|
|
width 33.
|
|
rgroup.long 0x1AC++0x0B
|
|
line.long 0x00 "INITIATOR_ISO_PW_RESP_PENDING_0,Initiator ISO PW Response Pending"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NUM_INITIATOR_ISO_PW_RESP_PEND ,Number of pending initiator ISO PW responses"
|
|
line.long 0x04 "INITIATOR_NISO_PW_RESP_PENDING_0,Initiator Non-ISO PW Response Pending"
|
|
hexmask.long.byte 0x04 0.--7. 1. " NUM_INITIATOR_NISO_PW_RESP_PEND ,Number of pending initiator NISO PW responses"
|
|
line.long 0x08 "INTR_STATUS_0,IPFS Interrupt Status"
|
|
bitfld.long 0x08 2. " IP_INTR_STATUS ,Status of IP interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 1. " MSI_INTR_STATUS ,Status of MSI interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " IPFS_INTR_STATUS ,Status of IPFS interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
width 22.
|
|
group.long 0x1B8++0x07
|
|
line.long 0x00 "DFPCI_BEN_0,Downstream FPCI Byte Enables"
|
|
bitfld.long 0x00 31. " EN_DFPCI_BEN ,Enable bit for BEN" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DFPCI_BYTE_ENABLE_N ,Active low byte enables" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CLKGATE_HYSTERESIS_0,CLKGATE HYSTERESIS 0"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CLK_DISABLE_CNT ,Number of IPFS clock cycles to wait after clock gating criteria is met to disable IPFS/FPCI clocks"
|
|
sif !cpuis("TEGRAX2")
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "MCCIF_FIFOCTRL_0,Memory Client Interface FIFO Control Register"
|
|
bitfld.long 0x00 20. " RCLK_OVR_MODE ,RCLK OVR MODE" "Legacy,On"
|
|
bitfld.long 0x00 19. " WCLK_OVR_MODE ,RCLK OVR MODE" "Legacy,On"
|
|
bitfld.long 0x00 18. " CCLK_OVERRIDE ,CCLK OVERRIDE" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x00 17. " RCLK_OVERRIDE ,RCLK OVERRIDE" "No override,Override"
|
|
bitfld.long 0x00 16. " WCLK_OVERRIDE ,WCLK OVERRIDE" "No override,Override"
|
|
bitfld.long 0x00 3. " MCCIF_RDCL_RDFAST ,MCCIF RDCL RDFAST" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MCCIF_WRMC_CLLE2X ,MCCIF WRMC CLLE2X" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MCCIF_RDMC_RDFAST ,MCCIF RDMC RDFAST" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MCCIF_WRCL_MCLE2X ,MCCIF WRCL MCLE2X" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
width 18.
|
|
group.long 0x1E0++0x0B
|
|
line.long 0x00 "ORDERING_RULES_0,ORDERING RULES"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 3. " UPSTREAM_MSIAW ,Modified Upstream MSIAW ordering" "Tegra X1,Tegra 3"
|
|
bitfld.long 0x00 2. " UPSTREAM_RESPAW ,Modified RespAW ordering." "Tegra X1,Tegra 3"
|
|
bitfld.long 0x00 1. " UPSTREAM_RAW ,Modified RAW ordering" "Tegra X1,Tegra 3"
|
|
elif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 3. " UPSTREAM_MSIAW ,Modified Upstream MSIAW ordering" "Parker,Parker 3"
|
|
bitfld.long 0x00 2. " UPSTREAM_RESPAW ,Modified RespAW ordering." "Parker,Parker 3"
|
|
bitfld.long 0x00 1. " UPSTREAM_RAW ,Modified RAW ordering" "Parker,Parker 3"
|
|
else
|
|
bitfld.long 0x00 3. " UPSTREAM_MSIAW ,Modified Upstream MSIAW ordering" "Tegra K1,Tegra 3"
|
|
bitfld.long 0x00 2. " UPSTREAM_RESPAW ,Modified RespAW ordering." "Tegra K1,Tegra 3"
|
|
bitfld.long 0x00 1. " UPSTREAM_RAW ,Modified RAW ordering" "Tegra K1,Tegra 3"
|
|
endif
|
|
line.long 0x04 "A2F_UFPCI_CFG0_0,A2F UFPCI CFG0"
|
|
hexmask.long.byte 0x04 24.--31. 1. " STATIC_WAIT_IDLE_CNTR ,Static wait idle control"
|
|
bitfld.long 0x04 16.--18. " STATIC_UFPCI_UFA_STARVE_CNTR_PRI1 ,Static UFPCI UFA starve Control PRI1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 12.--15. " STATIC_UFPCI_UFA_STARVE_CNTR_PRI0 ,Static UFPCI UFA starve control PRI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " STATIC_UFPCI_RR_BURST_SZ_PRI1 ,Static UFPCI RR burst SZ PRI1" "0,1,2,3"
|
|
bitfld.long 0x04 8.--9. " STATIC_UFPCI_RR_BURST_SZ_PRI0 ,Static UFPCI RR burst SZ PRI0" "0,1,2,3"
|
|
bitfld.long 0x04 7. " STATIC_WAIT_CLAMP_EN ,Static wait clamp enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " STATIC_UFPCI_UFA_DYN_BLOCK_EN ,Static UFPCI UFA DYN block enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " STATIC_UFPCI_UFA_BLK_COHERENT ,Static UFPCI UFA BLK coherent" "No coherent,Coherent"
|
|
bitfld.long 0x04 2.--4. " STATIC_UFPCI_BLOCK_CMD_THRESHOLD ,Static UFPCI block CMD threshold" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 1. " STATIC_CYA_UFA_ARB ,Static CYA UFA ARB" "0,1"
|
|
bitfld.long 0x04 0. " STATIC_CYA_BACK2BACK_UPSTREAM_BLOCK ,Static CYA back to back upstream block" "0,1"
|
|
line.long 0x08 "A2F_UFPCI_CFG1_0,A2F UFPCI CFG1"
|
|
hexmask.long.byte 0x08 0.--7. 1. " STATIC_WAIT_UNCLAMP_CNTR ,Static wait unclamp control"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "AHCI registers"
|
|
base ad:0x70027000
|
|
width 11.
|
|
tree "Host Bus Adaptor Registers (HBA)"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CAP_0,Host Bus Adaptor Capabilities"
|
|
bitfld.long 0x00 31. " S64A ,CAP_S64A" "FALSE,TRUE"
|
|
bitfld.long 0x00 30. " SNCQ ,CAP_SNCQ" "FALSE,TRUE"
|
|
bitfld.long 0x00 29. " SSNTF ,CAP_SSNTF" "FALSE,TRUE"
|
|
bitfld.long 0x00 28. " SMPS ,Supports Mechanical Presence Switch" "FALSE,TRUE"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SSS ,Supports Staggered Spin-up" "FALSE,TRUE"
|
|
bitfld.long 0x00 26. " SALP ,Supports Aggressive Link Power Management" "FALSE,TRUE"
|
|
bitfld.long 0x00 25. " SAL ,Supports Activity LED" "FALSE,TRUE"
|
|
bitfld.long 0x00 24. " SCLO ,Supports Command List Override" "FALSE,TRUE"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ISS ,Interface Speed Supported" ",GEN1,GEN1_2,?..."
|
|
bitfld.long 0x00 19. " SNZO ,Supports Non-Zero DMA Offsets" "FALSE,TRUE"
|
|
bitfld.long 0x00 18. " SAM ,Supports AHCI mode only" "FALSE,TRUE"
|
|
bitfld.long 0x00 17. " SPM ,Supports Port Multiplier" "FALSE,TRUE"
|
|
textline " "
|
|
bitfld.long 0x00 16. " FBSS ,FIS Based Switching Supported" "FALSE,TRUE"
|
|
bitfld.long 0x00 15. " PMD ,PIO Multiple DRQ Block" "FALSE,TRUE"
|
|
bitfld.long 0x00 14. " SSC ,Supports Slumber State" "FALSE,TRUE"
|
|
bitfld.long 0x00 13. " PSC ,Supports Partial State" "FALSE,TRUE"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " NCS ,Number of Command Slots" "1,,,,,,,8,,,,,,,,16,,,,,,,,,,,,,,,,32"
|
|
bitfld.long 0x00 7. " CCCS ,Command Completion Coalescing Support" "FALSE,TRUE"
|
|
bitfld.long 0x00 6. " EMS ,Enclosure Management Support" "FALSE,TRUE"
|
|
bitfld.long 0x00 5. " SXS ,Supports External SATA" "FALSE,TRUE"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NP ,Number of ports" "1,2,3,4,?..."
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "GHC,Host Bus Adaptor Global Host Control"
|
|
bitfld.long 0x00 31. " AE ,Indicates that communication to the HBA shall be via AHCI" "NO,YES"
|
|
bitfld.long 0x00 2. " MRSM ,Indicates that HBA requested more than one MSI vector but reverted to using the first vector only" "NO,YES"
|
|
bitfld.long 0x00 1. " IE ,Enables interrupts from the HBA" "FALSE,TRUE"
|
|
bitfld.long 0x00 0. " HR ,Causes an internal reset of the HBA" "No reset,Reset"
|
|
line.long 0x04 "IS,Host Bus Adaptor Interrupt Status"
|
|
eventfld.long 0x04 3. " PORT3_INTR ,IS_PORT3_INTR" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " PORT2_INTR ,IS_PORT2_INTR" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 1. " PORT1_INTR ,IS_PORT1_INTR" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 0. " PORT0_INTR ,IS_PORT0_INTR" "No interrupt,Interrupt"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "PI,Host Bus Adaptor Ports Implemented"
|
|
bitfld.long 0x00 3. " PI_FOURTH ,Port 4 available for software to use" "Not available,Available"
|
|
bitfld.long 0x00 2. " PI_THIRD ,Port 3 available for software to use" "Not available,Available"
|
|
bitfld.long 0x00 1. " PI_SECOND ,Port 2 available for software to use" "Not available,Available"
|
|
bitfld.long 0x00 0. " PI_FIRST ,Port 1 available for software to use" "Not available,Available"
|
|
line.long 0x04 "VS,VS AHCI Revision"
|
|
hexmask.long.word 0x04 16.--31. 1. " MAJOR_REV ,Indicates the major version"
|
|
hexmask.long.word 0x04 0.--15. 1. " MINOR_REV ,Indicates the minor version"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "CCC_CTL,Command Completion Coalescing Control"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIMEOUT_VAL ,Timeout value"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CTL_CC ,Number of command completions necessary to cause CCC interrupt"
|
|
rbitfld.long 0x00 3.--7. " CTL_INT ,Interrupt used by the CCC feature" "ZERO,,,,FIVE,,SEVEN,,,,,,,,,,,,,,,,,,,,,,,,,INIT"
|
|
bitfld.long 0x00 0. " CTL_EN ,Command completion coalescing enable" "Disabled,Enabled"
|
|
line.long 0x04 "CCC_PORTS,Command Completion Coalescing Ports"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "EM_LOC,Enclosure Management Location"
|
|
hexmask.long.word 0x00 16.--31. 1. " OFST ,The offset of the message buffer in Dwords from the beginning of the ABAR"
|
|
hexmask.long.word 0x00 0.--15. 1. " SZ ,Specifies the size of the transmit message buffer area in Dwords"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "EM_CTL,Enclosure Management Control"
|
|
rbitfld.long 0x00 27. " ATTR_PM ,HBA enclosure management messages support" "FALSE,TRUE"
|
|
rbitfld.long 0x00 26. " ATTR_ALHD ,HBA hardware based activity signal drive" "FALSE,TRUE"
|
|
rbitfld.long 0x00 25. " ATTR_XMT ,HBA transmitting messages support without receive support" "FALSE,TRUE"
|
|
rbitfld.long 0x00 24. " ATTR_SMB ,Single message buffer support" "FALSE,TRUE"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " SUPP_SGPIO ,SGPIO register interface message type support" "FALSE,TRUE"
|
|
rbitfld.long 0x00 18. " SUPP_SES2 ,SES-2 message type support" "FALSE,TRUE"
|
|
rbitfld.long 0x00 17. " SUPP_SAFTE ,SAF-TE message type support" "FALSE,TRUE"
|
|
rbitfld.long 0x00 16. " SUPP_LED ,LED message support" "FALSE,TRUE"
|
|
textline " "
|
|
eventfld.long 0x00 9. " RST ,Software reset request" "No effect,Reset"
|
|
eventfld.long 0x00 8. " TM ,Software transmit message request" "No effect,Transmit"
|
|
eventfld.long 0x00 0. " STS_MR ,Message received" "Not received,Received"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CAP2,HBA Capabilities Extended"
|
|
bitfld.long 0x00 5. " DESO ,DEVSLP assertion only when interface is in Slumber" "FALSE,TRUE"
|
|
bitfld.long 0x00 4. " SADM ,DEVSLP assertion after the idle timeout expiration" "FALSE,TRUE"
|
|
bitfld.long 0x00 3. " SDS , Device Sleep feature support" "FALSE,TRUE"
|
|
bitfld.long 0x00 2. " APST ,Automatic Partial to Slumber Transitions support" "FALSE,TRUE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BOH ,BIOS/OS handoff mechanism support" "FALSE,TRUE"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "BOHC,BIOS/OS Handoff Control and Status"
|
|
bitfld.long 0x00 4. " BB ,BIOS Busy" "FALSE,TRUE"
|
|
eventfld.long 0x00 3. " OOC ,OS Ownership Change" "FALSE,TRUE"
|
|
bitfld.long 0x00 2. " SOOE ,SMI on OS Ownership Change Enable" "FALSE,TRUE"
|
|
bitfld.long 0x00 1. " OOS ,OS Owned Semaphore" "FALSE,TRUE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BOS ,BIOS Owned Semaphore" "FALSE,TRUE"
|
|
textline " "
|
|
group.long 0xA0++0x07
|
|
line.long 0x00 "CAP_BKDR,Capability Back-door Writes"
|
|
bitfld.long 0x00 31. " S64A ,CAP_BKDR_S64A" "FALSE,TRUE"
|
|
bitfld.long 0x00 30. " SNCQ ,CAP_BKDR_SNCQ" "FALSE,TRUE"
|
|
bitfld.long 0x00 29. " SSNTF ,CAP_BKDR_SSNTF" "FALSE,TRUE"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SMPS ,Back-door field to Mechanical Presence Switch Support" "FALSE,TRUE"
|
|
bitfld.long 0x00 27. " SUPP_STG_SPUP ,Back-door field to advertise staggered spin up" "CLEARED,SET"
|
|
bitfld.long 0x00 26. " SALP ,Back-door field to Aggressive Link Power Management support" "FALSE,TRUE"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SAL ,Back-door field to Activity LED Support" "FALSE,TRUE"
|
|
bitfld.long 0x00 24. " SUPP_CLO ,Back-door field to Command List Override Support" "FALSE,TRUE"
|
|
bitfld.long 0x00 20.--23. " INTF_SPD_SUPP ,Back-door field to Interface Suppported Speed: CAP.ISS can be written using this" ",GEN1,GEN1_2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19. " SUPP_NONZERO_OFFSET ,Back-door field to Non-Zero DMA Offsets support" "FALSE,TRUE"
|
|
bitfld.long 0x00 18. " SUPP_AHCI_ONLY ,Back-door field to AHCI mode only support" "FALSE,TRUE"
|
|
bitfld.long 0x00 17. " SUPP_PM ,Back-door field to Port Multiplier support" "FALSE,TRUE"
|
|
textline " "
|
|
bitfld.long 0x00 16. " FIS_SWITCHING ,Back-door field to FIS Based Switching Support" "FALSE,TRUE"
|
|
bitfld.long 0x00 15. " PIO_MULT_DRQ_BLK ,Back-door field to PIO Multiple DRQ Block" "NOT_SUPP,SUPP"
|
|
bitfld.long 0x00 14. " SLUMBER_ST_CAP ,Back-door field to Slumber state capability" "FALSE,TRUE"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PARTIAL_ST_CAP ,Back-door field to Partial state capability" "FALSE,TRUE"
|
|
bitfld.long 0x00 8.--12. " NUM_CMD_SLOTS ,Back-door field to Number of Command Slots" "1,,,,,,,8,,,,,,,,16,,,,,,,,,,,,,,,,32"
|
|
bitfld.long 0x00 7. " CMD_CMPL_COALESING ,Back-door field to Command Completion Coalescing Support" "FALSE,TRUE"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ENCL_MGMT_SUPP ,Back-door field to Enclosure Management Support" "FALSE,TRUE"
|
|
bitfld.long 0x00 5. " EXT_SATA ,Back-door access for enabling external SATA" "NOT SUPPORTED,SUPPORTED"
|
|
bitfld.long 0x00 0.--4. " NUM_PORTS ,Back-door field to Number of ports" "1,2,3,4,?..."
|
|
line.long 0x04 "SPARE,Spare register with cold reset"
|
|
textline " "
|
|
width 16.
|
|
group.long 0xA8++0x07
|
|
line.long 0x00 "PLL_CTRL,PLL_CTRL"
|
|
bitfld.long 0x00 24. " CLAMP_TXCLK_ON_DEVSLP ,PLL_CTRL_CLAMP_TXCLK_ON_DEVSLP" "NO,YES"
|
|
bitfld.long 0x00 23. " CLAMP_DEVCLK_ON_DEVSLP ,PLL_CTRL_CLAMP_DEVCLK_ON_DEVSLP" "NO,YES"
|
|
bitfld.long 0x00 22. " SHUTDOWN_TXCLK_ON_DEVSLP ,PLL_CTRL_SHUTDOWN_TXCLK_ON_DEVSLP" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DIS_TXRXCLK_SHUTDOWN ,PLL_CTRL_DIS_TXRXCLK_SHUTDOWN" "NO,YES"
|
|
bitfld.long 0x00 20. " DIS_TXRXCLK_CLAMPING ,PLL_CTRL_DIS_TXRXCLK_CLAMPING" "NO,YES"
|
|
bitfld.long 0x00 19. " DIS_DEVCLK_CLAMPING ,PLL_CTRL_DIS_DEVCLK_CLAMPING" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CLAMP_DEVCLK_IN_AWAIT_COMINIT ,PLL_CTRL_CLAMP_DEVCLK_IN_AWAIT" "NO,YES"
|
|
bitfld.long 0x00 17. " CLAMP_TXRXCLK_IN_AWAIT_COMINIT ,PLL_CTRL_CLAMP_TXRXCLK_IN_AWAIT" "NO,YES"
|
|
bitfld.long 0x00 16. " UNCLAMP_DEVCLK_ONLY_THRU_SW ,PLL_CTRL_UNCLAMP_DEVCLK_ONLY_THRU_SW" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x00 15. " UNCLAMP_TXRXCLK_ONLY_THRU_SW ,PLL_CTRL_UNCLAMP_TXRXCLK_ONLY_THRU_SW" "NO,YES"
|
|
bitfld.long 0x00 14. " WAKEUP_ONLY_THRU_SW ,PLL_CTRL_WAKEUP_ONLY_THRU_SW" "NO,YES"
|
|
bitfld.long 0x00 13. " CLAMP_TXCLK_ON_SLUMBER ,Indicates that txclk and rxclk clamping is enabled when PHY is in SLUMBER" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CLAMP_TXCLK_ON_PHYRDY_LOW ,Indicates txclk and rxclk clamping is enabled when PHY_RDY goes low" "NO,YES"
|
|
bitfld.long 0x00 11. " CLAMP_TXCLK_ON_PARTIAL ,Indicates that txclk and rxclk clamping is enabled when PHY is in PARTIAL" "NO,YES"
|
|
bitfld.long 0x00 10. " CLAMP_DEVCLK_ON_SLUMBER ,PLL_CTRL_CLAMP_DEVCLK_ON_SLUMBER" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLAMP_DEVCLK_ON_PHYRDY_LOW ,PLL_CTRL_CLAMP_DEVCLK_ON_PHYRDY_LOW" "NO,YES"
|
|
bitfld.long 0x00 8. " CLAMP_DEVCLK_ON_PARTIAL ,PLL_CTRL_CLAMP_DEVCLK_ON_PARTIAL" "NO,YES"
|
|
bitfld.long 0x00 7. " SHUTDOWN_TXCLK_ON_PHYRDY_LOW ,Shutdown signal assertion when PHY_RDY ports go low" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x00 6. " HUTDOWN_TXCLK_ON_SLUMBER ,Shutdown signal assertion when all the ports are in SLUMBER and SHUTDOWN_TXCLK_ON_PHYRDY_LOW == 0" "NO,YES"
|
|
bitfld.long 0x00 5. " SHUTDOWN_DEVCLK_ON_PHYRDY_LOW ,PLL_CTRL_SHUTDOWN_DEVCLK_ON_PHYRDY_LOW" "NO,YES"
|
|
bitfld.long 0x00 4. " SHUTDOWN_DEVCLK_ON_SLUMBER ,PLL_CTRL_SHUTDOWN_DEVCLK_ON_SLUMBER" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NO_CLAMP_SHUTDOWN ,Disables clamping of clocks and shutdown of PLL" "NO,YES"
|
|
bitfld.long 0x00 2. " TXRXCLK_WAKEUP ,Deasserts the above signal to wakeup the TXRXCLK PLL" "NO,YES"
|
|
bitfld.long 0x00 1. " TXRXCLK_SHUTDOWN ,Sets a signal to clocks block to shut down the TXRXCLK PLL" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DEVCLK_SHUTDOWN ,Sets a signal to clocks block to shut down the DEVCLK PLL" "NO,YES"
|
|
line.long 0x04 "SHUTDOWN_TIMER,HBA Shut-down Timer"
|
|
hexmask.long.word 0x04 14.--27. 1. " DEV_CLK ,SHUTDOWN_TIMER_DEV_CLK"
|
|
hexmask.long.word 0x04 14.--27. 1. " TXRX_CLK ,Specifies how many 100us to wait before shutting down the PLL"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "SPARE_3,HBA Spare register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " SPARE_3[31:16] ,SPARE_3_RSVD_31_16 (Cold reset)"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPARE_3[15:0] ,SPARE_3_RSVD_15_0"
|
|
tree.end
|
|
width 10.
|
|
tree "Port Registers (PORT)"
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "PXCLB,Port Command List Base Address"
|
|
hexmask.long.tbyte 0x00 10.--31. 0x400 " CLB ,32-bit base physical address for the command list for this port"
|
|
line.long 0x04 "PXCLBU,Port Command List Base Address Upper"
|
|
line.long 0x08 "PXFB,Port FIS Base Address"
|
|
hexmask.long.tbyte 0x08 8.--31. 0x100 " FB ,32-bit base physical address for received FISes"
|
|
line.long 0x0C "PXFBU,Port FIS Base Address Upper"
|
|
line.long 0x10 "PXIS,Port Interrupt Status"
|
|
eventfld.long 0x10 31. " CPDS ,CPD Port Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 30. " TFES ,TFE Port Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 29. " HBFS ,HBF Port Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 28. " HBDS ,HBD Port Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x10 27. " IFS ,IF Port Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 26. " INFS ,INF Port Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 24. " OFS ,OF Port Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 23. " IPMS ,IPM Port Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x10 22. " PRCS ,PRC Port Interrupt Status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x10 7. " DMPS ,DMP Port Interrupt Status" "No interrupt,Interrupt"
|
|
rbitfld.long 0x10 6. " PCS ,PC Port Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 5. " DPS ,DP Port Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x10 4. " UFS ,UF Port Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 3. " SDBS ,SDB Port Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 2. " DSS ,DS Port Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x10 1. " PSS ,PS Port Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x10 0. " DHRS ,DHR Port Interrupt Status" "No interrupt,Interrupt"
|
|
line.long 0x14 "PXIE,Port Interrupt Enable"
|
|
rbitfld.long 0x14 31. " CPDE ,CPD Port Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " TFEE ,TFE Port Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 29. " HBFE ,HBF Port Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " HBDE ,HBD Port Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " IFE ,IF Port Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " INFE ,INF Port Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " OFE ,OF Port Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 23. " IPME ,IPM Port Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 22. " PRCE ,PRC Port Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x14 7. " DMPE ,DMP Port Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " PCE ,PC Port Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " DPE ,DP Port Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " UFE ,UF Port Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " SDBE ,SDB Port Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " DSE ,DS Port Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " PSE ,PS Port Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " DHRE ,DHR Port Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x18 "PXCMD,Port Command and Status"
|
|
bitfld.long 0x18 28.--31. " ICC ,PXCMD_ICC" "NO_OP,ACTIVE,PARTIAL,,,,SLUMBER,,DEVSLEEP,?..."
|
|
bitfld.long 0x18 27. " ASP ,PXCMD_ASP" "Disabled,Enabled"
|
|
bitfld.long 0x18 26. " ALPE ,PXCMD_ALPE" "FALSE,TRUE"
|
|
bitfld.long 0x18 25. " DLAE ,PXCMD_DLAE" "CMDS,ALWYS"
|
|
textline " "
|
|
bitfld.long 0x18 24. " ATAPI ,PXCMD_ATAPI" "NOTPRSNT,PRSNT"
|
|
bitfld.long 0x18 23. " APSTE ,PXCMD_APSTE" "FALSE,TRUE"
|
|
bitfld.long 0x18 22. " FBSCP ,PXCMD_FBSCP" "FALSE,TRUE"
|
|
bitfld.long 0x18 21. " ESP ,PXCMD_ESP" "NOTSUPPORTED,SUPPORTED"
|
|
textline " "
|
|
bitfld.long 0x18 20. " CPD ,PXCMD_CPD" "NOTSUPPORTED,SUPPORTED"
|
|
bitfld.long 0x18 19. " MPSP ,PXCMD_MPSP" "FALSE,TRUE"
|
|
bitfld.long 0x18 18. " HPCP ,PXCMD_HPCP" "FALSE,TRUE"
|
|
bitfld.long 0x18 17. " PMA ,PXCMD_PMA" "FALSE,TRUE"
|
|
textline " "
|
|
bitfld.long 0x18 16. " CPS ,PXCMD_CPS" "NOTDETECTED,DETECTED"
|
|
bitfld.long 0x18 15. " CR ,PXCMD_CR" "NOTRCVD,RCVD"
|
|
bitfld.long 0x18 14. " FR ,PXCMD_FR" "NOTRCVD,RCVD"
|
|
bitfld.long 0x18 13. " MPSS ,PXCMD_MPSS" "CLOSED,OPEN"
|
|
textline " "
|
|
bitfld.long 0x18 8.--12. " CCS ,PXCMD_CCS" "00,,,,,,,,,,,,,,,16,,,,,,,,,,,,,,,,32"
|
|
bitfld.long 0x18 4. " FRE ,PXCMD_FRE" "CLEARED,SET"
|
|
bitfld.long 0x18 3. " CLO ,PXCMD_CLO" "DISABLED,ENABLED"
|
|
rbitfld.long 0x18 2. " POD ,PXCMD_POD" "CLEARED,SET"
|
|
textline " "
|
|
bitfld.long 0x18 1. " SUD ,PXCMD_SUD" "CLEARED,SET"
|
|
bitfld.long 0x18 0. " ST ,PXCMD_ST" "CLEARED,SET"
|
|
rgroup.long 0x120++0x0B
|
|
line.long 0x00 "PXTFD,Port Task File Data"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ERR ,PXTFD_ERR"
|
|
bitfld.long 0x00 7. " BSY ,PXTFD_STS_BSY" "CREARED,SET"
|
|
bitfld.long 0x00 6. " DRDY ,PXTFD_STS_DRDY" "CREARED,SET"
|
|
bitfld.long 0x00 5. " DF ,PXTFD_STS_DF" "CREARED,SET"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CS ,PXTFD_STS_CS" "CREARED,SET"
|
|
bitfld.long 0x00 3. " DRQ ,PXTFD_STS_DRQ" "CREARED,SET"
|
|
bitfld.long 0x00 1.--2. " STS_2_1 ,PXTFD_STS_2_1" "0,1,2,3"
|
|
bitfld.long 0x00 0. " ERR ,PXTFD_STS_ERR" "CREARED,SET"
|
|
line.long 0x04 "PXSIG,Port Signature"
|
|
hexmask.long.byte 0x04 24.--31. 1. " LBA_HIGH ,PXSIG_LBA_HIGH"
|
|
hexmask.long.byte 0x04 16.--23. 1. " LBA_MID ,PXSIG_LBA_MID"
|
|
hexmask.long.byte 0x04 8.--15. 1. " LBA_LOW ,PXSIG_LBA_LOW"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SECTOR_CNT ,PXSIG_SECTOR_CNT"
|
|
textline " "
|
|
line.long 0x08 "PXSSTS,PXSSTS"
|
|
bitfld.long 0x08 8.--11. " IPM ,PXSSTS_IPM" "NO_DEV,ACT_ST,PARTIAL_ST,,,SLUMBER_ST,,DEVSLEEP_ST,?..."
|
|
bitfld.long 0x08 4.--7. " SPD ,PXSSTS_SPD" "NO_DEV,GEN1,GEN2,?..."
|
|
bitfld.long 0x08 0.--3. " DET ,PXSSTS_DET" "NO_DEV,DEV_PRSNT_NO_PHY_COMM,,DEV_PRSNT_PHY_COMM,BIST_LPBK,?..."
|
|
group.long 0x12C++0x2B
|
|
line.long 0x00 "PXSCTL,Port Serial ATA Control"
|
|
rbitfld.long 0x00 16.--19. " PMP ,PXSCTL_PMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. " SPM ,PXSCTL_SPM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " IPM ,PXSCTL_IPM" "NO_RSTCT,PARTIAL_ST_DISABLED,SLUMBER_ST_DISABLED,PART_SLUM_ST_DISABLED,DEVSLEEP_ST_DISABLED,PART_DEVSLP_ST_DISABLED,SLUM_DEVSLP_ST_DISABLED,PART_SLUM_DEVSLP_ST_DISABLED,?..."
|
|
bitfld.long 0x00 4.--7. " SPD ,PXSCTL_SPD" "00,GEN1,GEN2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DET ,PXSCTL_DET" "NO_DEV_RQD,INTF_INIT,,,PHY_OFFLINE,?..."
|
|
textline ""
|
|
line.long 0x04 "PXSERR,Port Serial ATA Error"
|
|
eventfld.long 0x04 26. " DIAG_X ,PXSERR_DIAG_X" "FALSE,TRUE"
|
|
eventfld.long 0x04 25. " DIAG_F ,PXSERR_DIAG_F" "FALSE,TRUE"
|
|
eventfld.long 0x04 24. " DIAG_T ,PXSERR_DIAG_T" "FALSE,TRUE"
|
|
eventfld.long 0x04 23. " DIAG_S ,PXSERR_DIAG_S" "FALSE,TRUE"
|
|
textline " "
|
|
eventfld.long 0x04 22. " DIAG_H ,PXSERR_DIAG_H" "FALSE,TRUE"
|
|
eventfld.long 0x04 21. " DIAG_C ,PXSERR_DIAG_C" "FALSE,TRUE"
|
|
eventfld.long 0x04 20. " DIAG_D ,PXSERR_DIAG_D" "FALSE,TRUE"
|
|
eventfld.long 0x04 19. " DIAG_B ,PXSERR_DIAG_B" "FALSE,TRUE"
|
|
textline " "
|
|
eventfld.long 0x04 18. " DIAG_W ,PXSERR_DIAG_W" "FALSE,TRUE"
|
|
eventfld.long 0x04 17. " DIAG_I ,PXSERR_DIAG_I" "FALSE,TRUE"
|
|
eventfld.long 0x04 16. " DIAG_N ,PXSERR_DIAG_N" "FALSE,TRUE"
|
|
eventfld.long 0x04 11. " ERR_E ,PXSERR_ERR_E" "FALSE,TRUE"
|
|
textline " "
|
|
eventfld.long 0x04 10. " ERR_P ,PXSERR_ERR_P" "FALSE,TRUE"
|
|
eventfld.long 0x04 9. " ERR_C ,PXSERR_ERR_C" "FALSE,TRUE"
|
|
eventfld.long 0x04 8. " ERR_T ,PXSERR_ERR_T" "FALSE,TRUE"
|
|
eventfld.long 0x04 1. " ERR_M ,PXSERR_ERR_M" "FALSE,TRUE"
|
|
textline " "
|
|
eventfld.long 0x04 0. " ERR_I ,PXSERR_ERR_I" "FALSE,TRUE"
|
|
line.long 0x08 "PXSACT,Port Serial ATA Active"
|
|
bitfld.long 0x08 31. " DS31 ,PXSACT_DS31" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 30. " DS30 ,PXSACT_DS30" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 29. " DS29 ,PXSACT_DS29" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 28. " DS28 ,PXSACT_DS28" "NOT_PRSNT,PRSNT"
|
|
textline " "
|
|
bitfld.long 0x08 27. " DS27 ,PXSACT_DS27" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 26. " DS26 ,PXSACT_DS26" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 25. " DS25 ,PXSACT_DS25" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 24. " DS24 ,PXSACT_DS24" "NOT_PRSNT,PRSNT"
|
|
textline " "
|
|
bitfld.long 0x08 23. " DS23 ,PXSACT_DS23" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 22. " DS22 ,PXSACT_DS22" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 21. " DS21 ,PXSACT_DS21" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 20. " DS20 ,PXSACT_DS20" "NOT_PRSNT,PRSNT"
|
|
textline " "
|
|
bitfld.long 0x08 19. " DS19 ,PXSACT_DS19" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 18. " DS18 ,PXSACT_DS18" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 17. " DS17 ,PXSACT_DS17" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 16. " DS16 ,PXSACT_DS16" "NOT_PRSNT,PRSNT"
|
|
textline " "
|
|
bitfld.long 0x08 15. " DS15 ,PXSACT_DS15" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 14. " DS14 ,PXSACT_DS14" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 13. " DS13 ,PXSACT_DS13" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 12. " DS12 ,PXSACT_DS12" "NOT_PRSNT,PRSNT"
|
|
textline " "
|
|
bitfld.long 0x08 11. " DS11 ,PXSACT_DS11" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 10. " DS10 ,PXSACT_DS10" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 9. " DS9 ,PXSACT_DS9" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 8. " DS8 ,PXSACT_DS8" "NOT_PRSNT,PRSNT"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DS7 ,PXSACT_DS7" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 6. " DS6 ,PXSACT_DS6" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 5. " DS5 ,PXSACT_DS5" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 4. " DS4 ,PXSACT_DS4" "NOT_PRSNT,PRSNT"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DS3 ,PXSACT_DS3" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 2. " DS2 ,PXSACT_DS2" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x08 1. " DS1 ,PXSACT_DS1" "NOT_PRSNT,PRSNT"
|
|
line.long 0x0C "PXCI,Port Command Issue"
|
|
bitfld.long 0x0C 31. " PXCI31 ,PXCI_CI31" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 30. " PXCI30 ,PXCI_CI30" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 29. " PXCI29 ,PXCI_CI29" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 28. " PXCI28 ,PXCI_CI28" "NOT_PRSNT,PRSNT"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " PXCI27 ,PXCI_CI27" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 26. " PXCI26 ,PXCI_CI26" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 25. " PXCI25 ,PXCI_CI25" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 24. " PXCI24 ,PXCI_CI24" "NOT_PRSNT,PRSNT"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " PXCI23 ,PXCI_CI23" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 22. " PXCI22 ,PXCI_CI22" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 21. " PXCI21 ,PXCI_CI21" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 20. " PXCI20 ,PXCI_CI20" "NOT_PRSNT,PRSNT"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " PXCI19 ,PXCI_CI19" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 18. " PXCI18 ,PXCI_CI18" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 17. " PXCI17 ,PXCI_CI17" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 16. " PXCI16 ,PXCI_CI16" "NOT_PRSNT,PRSNT"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " PXCI15 ,PXCI_CI15" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 14. " PXCI14 ,PXCI_CI14" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 13. " PXCI13 ,PXCI_CI13" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 12. " PXCI12 ,PXCI_CI12" "NOT_PRSNT,PRSNT"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " PXCI11 ,PXCI_CI11" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 10. " PXCI10 ,PXCI_CI10" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 9. " PXCI9 ,PXCI_CI9" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 8. " PXCI8 ,PXCI_CI8" "NOT_PRSNT,PRSNT"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " PXCI7 ,PXCI_CI7" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 6. " PXCI6 ,PXCI_CI6" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 5. " PXCI5 ,PXCI_CI5" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 4. " PXCI4 ,PXCI_CI4" "NOT_PRSNT,PRSNT"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " PXCI3 ,PXCI_CI3" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 2. " PXCI2 ,PXCI_CI2" "NOT_PRSNT,PRSNT"
|
|
bitfld.long 0x0C 1. " PXCI1 ,PXCI_CI1" "NOT_PRSNT,PRSNT"
|
|
line.long 0x10 "PXSNTF,Port S Notification"
|
|
eventfld.long 0x10 15. " PMN_PORT15 ,PXSNTF_PMN_PORT15" "NOT_SET,SET"
|
|
eventfld.long 0x10 14. " PMN_PORT14 ,PXSNTF_PMN_PORT14" "NOT_SET,SET"
|
|
eventfld.long 0x10 13. " PMN_PORT13 ,PXSNTF_PMN_PORT13" "NOT_SET,SET"
|
|
eventfld.long 0x10 12. " PMN_PORT12 ,PXSNTF_PMN_PORT12" "NOT_SET,SET"
|
|
textline " "
|
|
eventfld.long 0x10 11. " PMN_PORT11 ,PXSNTF_PMN_PORT11" "NOT_SET,SET"
|
|
eventfld.long 0x10 10. " PMN_PORT10 ,PXSNTF_PMN_PORT10" "NOT_SET,SET"
|
|
eventfld.long 0x10 9. " PMN_PORT9 ,PXSNTF_PMN_PORT9" "NOT_SET,SET"
|
|
eventfld.long 0x10 8. " PMN_PORT8 ,PXSNTF_PMN_PORT8" "NOT_SET,SET"
|
|
textline " "
|
|
eventfld.long 0x10 7. " PMN_PORT7 ,PXSNTF_PMN_PORT7" "NOT_SET,SET"
|
|
eventfld.long 0x10 6. " PMN_PORT6 ,PXSNTF_PMN_PORT6" "NOT_SET,SET"
|
|
eventfld.long 0x10 5. " PMN_PORT5 ,PXSNTF_PMN_PORT5" "NOT_SET,SET"
|
|
eventfld.long 0x10 4. " PMN_PORT4 ,PXSNTF_PMN_PORT4" "NOT_SET,SET"
|
|
textline " "
|
|
eventfld.long 0x10 3. " PMN_PORT3 ,PXSNTF_PMN_PORT3" "NOT_SET,SET"
|
|
eventfld.long 0x10 2. " PMN_PORT2 ,PXSNTF_PMN_PORT2" "NOT_SET,SET"
|
|
eventfld.long 0x10 1. " PMN_PORT1 ,PXSNTF_PMN_PORT1" "NOT_SET,SET"
|
|
eventfld.long 0x10 0. " PMN_PORT0 ,PXSNTF_PMN_PORT0" "NOT_SET,SET"
|
|
line.long 0x14 "PXFBS,Reserved for FIS Based Switching"
|
|
rbitfld.long 0x14 16.--19. " DWE ,PXFBS_DWE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x14 12.--15. " ADO ,PXFBS_ADO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 8.--11. " DEV ,PXFBS_DEV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
rbitfld.long 0x14 2. " SDE ,PXFBS_SDE" "SDE_DEFAULT,?..."
|
|
rbitfld.long 0x14 1. " DEC ,PXFBS_DEC" "NOT,TRUE"
|
|
rbitfld.long 0x14 0. " EN ,PXFBS_EN" "EN_FALSE,?..."
|
|
line.long 0x18 "PXDEVSLP,Port Device Sleep"
|
|
rbitfld.long 0x18 25.--28. " DM ,Port Device Sleep" "DM_DEFAULT,?..."
|
|
hexmask.long.word 0x18 15.--24. 1. " DITO ,PXDEVSLP_DITO"
|
|
bitfld.long 0x18 10.--14. " MDAT ,PXDEVSLP_MDAT" ",,,,,,,,,MDAT_DEFAULT,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x18 2.--9. 1. " DETO ,PXDEVSLP_DETO"
|
|
bitfld.long 0x18 1. " DSP ,PXDEVSLP_DSP" "FALSE,TRUE"
|
|
bitfld.long 0x18 0. " ADSE ,PXDEVSLP_ADSE" "FALSE,TRUE"
|
|
group.long 0x170++0xF
|
|
line.long 0x00 "BKDR,Port Vendor Specific Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DETO_OVERRIDE_VAL ,BKDR_PXDEVSLP_DETO_ OVERRIDE_VAL"
|
|
bitfld.long 0x00 16.--20. " MDAT_OVERRIDE_VAL ,BKDR_PXDEVSLP_MDAT_OVERRIDE_VAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " DETO_OVERRIDE ,BKDR_PXDEVSLP_DETO_OVERRIDE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " MDAT_OVERRIDE ,BKDR_PXDEVSLP_MDAT_OVERRIDE" "0,1"
|
|
bitfld.long 0x00 10.--13. " DM ,BKDR_PXDEVSLP_DM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 9. " UNCONNECTED ,BKDR_UNCONNECTED: Written by the BIOS during the initial boot-up when it finds a port unconnected" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLAMP_THIS_CH ,BKDR_CLK_CLAMP_CTRL_CLAMP_THIS_CH: Enable/Disable Clamping capability for individual channel(both devclk and txclk)" "NO,YES"
|
|
bitfld.long 0x00 7. " TXRXCLK_UNCLAMP ,BKDR_CLK_CLAMP_CTRL_TXRXCLK_UNCLAMP" "NO,YES"
|
|
bitfld.long 0x00 6. " TXRXCLK_CLAMP ,BKDR_CLK_CLAMP_CTRL_TXRXCLK_CLAMP" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DEVCLK_UNCLAMP ,BKDR_CLK_CLAMP_CTRL_DEVCLK_UNCLAMP" "NO,YES"
|
|
bitfld.long 0x00 4. " DEVCLK_CLAMP ,BKDR_CLK_CLAMP_CTRL_DEVCLK_CLAMP" "NOT_SUPP,SUPP"
|
|
bitfld.long 0x00 3. " HOTPLUG_CAP ,BKDR_HOTPLUG_CAP" "NOT_SUPP,SUPP"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MECH_SWITCH ,BKDR_MECH_SWITCH" "NOT_SUPP,SUPP"
|
|
bitfld.long 0x00 1. " COLD_PRSN_DET ,BKDR_COLD_PRSN_DET" "NOT_SUPP,SUPP"
|
|
bitfld.long 0x00 0. " EXT_SATA_SUPP ,BKDR_EXT_SATA_SUPP" "NOT_SUPP,SUPP"
|
|
line.long 0x04 "INTR,Port Interrupt Source"
|
|
bitfld.long 0x04 31. " NCQ_MIX ,EN_IFS_NCQ_NON_NCQ_MIX" "CLEARED,SET"
|
|
bitfld.long 0x04 30. " TAG_ERROR ,INTR_EN_IFS_FPDMA_TAG_ERROR" "CLEARED,SET"
|
|
bitfld.long 0x04 29. " CRC_ERROR ,INTR_EN_INFS_NONDATA_FIS_CRC_ERROR" "CLEARED,SET"
|
|
textline " "
|
|
bitfld.long 0x04 28. " PMP_MISMATCH ,INTR_EN_INFS_PMP_MISMATCH" "CLEARED,SET"
|
|
bitfld.long 0x04 27. " NONDATA_FIS_SIZE ,INTR_EN_INFS_NONDATA_FIS_SIZE" "CLEARED,SET"
|
|
bitfld.long 0x04 26. " UFIS_SIZE ,INTR_EN_INFS_UFIS_SIZE" "CLEARED,SET"
|
|
textline " "
|
|
bitfld.long 0x04 25. " DMA_CNT_ERROR ,INTR_EN_IFS_DMA_CNT_ERROR" "CLEARED,SET"
|
|
bitfld.long 0x04 24. " FIFO_OVERWRITTEN ,INTR_EN_IFS_FIFO_OVERWRITTEN" "CLEARED,SET"
|
|
bitfld.long 0x04 23. " SYNC_ESCAPE_RECV ,INTR_EN_IFS_SYNC_ESCAPE_RECV" "CLEARED,SET"
|
|
textline " "
|
|
bitfld.long 0x04 22. " NONNCQ_TX_RX_UNDERFLOW ,INTR_EN_IFS_NONNCQ_TX_RX_UNDERFLOW" "CLEARED,SET"
|
|
bitfld.long 0x04 21. " DATA_FIS_RECV ,INTR_EN_IFS_DATA_FIS_RECV" "CLEARED,SET"
|
|
bitfld.long 0x04 20. " DATA_FIS_XMIT ,INTR_EN_IFS_DATA_FIS_XMIT" "CLEARED,SET"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ATAPI_CMD_XMIT ,INTR_EN_IFS_ATAPI_CMD_XMIT" "CLEARED,SET"
|
|
bitfld.long 0x04 18. " NCQ_TX_RX_UNDERFLOW ,INTR_EN_IFS_NCQ_TX_RX_UNDERFLOW" "CLEARED,SET"
|
|
bitfld.long 0x04 17. " OFS_TX ,INTR_EN_OFS_TX" "CLEARED,SET"
|
|
textline " "
|
|
bitfld.long 0x04 16. " OFS_RX ,INTR_EN_OFS_RX" "CLEARED,SET"
|
|
rbitfld.long 0x04 15. " NON_NCQ_MIX ,INTR_IFS_NCQ_NON_NCQ_MIX" "INIT,SET"
|
|
rbitfld.long 0x04 14. " TAG_ERROR ,INTR_IFS_FPDMA_TAG_ERROR" "CLEARED,SET"
|
|
textline " "
|
|
rbitfld.long 0x04 13. " CRC_ERROR ,INTR_INFS_NONDATA_FIS_CRC_ERROR" "CLEARED,SET"
|
|
rbitfld.long 0x04 12. " PMP_MISMATCH ,INTR_INFS_PMP_MISMATCH" "CLEARED,SET"
|
|
rbitfld.long 0x04 11. " NONDATA_FIS_SIZE ,INTR_INFS_NONDATA_FIS_SIZE" "CLEARED,SET"
|
|
textline " "
|
|
rbitfld.long 0x04 10. " UFIS_SIZE ,INTR_INFS_UFIS_SIZE" "CLEARED,SET"
|
|
rbitfld.long 0x04 9. " DMA_CNT_ERROR ,INTR_IFS_DMA_CNT_ERROR" "CLEARED,SET"
|
|
rbitfld.long 0x04 8. " FIFO_OVERWRITTEN ,INTR_IFS_FIFO_OVERWRITTEN" "CLEARED,SET"
|
|
textline " "
|
|
rbitfld.long 0x04 7. " SYNC_ESCAPE_RECV ,INTR_IFS_SYNC_ESCAPE_RECV" "CLEARED,SET"
|
|
rbitfld.long 0x04 6. " NONNCQ_TX_RX ,INTR_IFS_NONNCQ_TX_RX" "CLEARED,SET"
|
|
rbitfld.long 0x04 5. " DATA_FIS_RECV ,INTR_IFS_DATA_FIS_RECV" "CLEARED,SET"
|
|
textline " "
|
|
rbitfld.long 0x04 4. " DATA_FIS_XMIT ,INTR_IFS_DATA_FIS_XMIT" "CLEARED,SET"
|
|
rbitfld.long 0x04 3. " ATAPI_CMD_XMIT ,INTR_IFS_ATAPI_CMD_XMIT" "CLEARED,SET"
|
|
rbitfld.long 0x04 2. " NCQ_TX_RX ,INTR_IFS_NCQ_TX_RX" "CLEARED,SET"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " OFS_TX ,INTR_OFS_TX" "CLEARED,SET"
|
|
rbitfld.long 0x04 0. " OFS_RX ,INTR_OFS_RX" "CLEARED,SET"
|
|
textline ""
|
|
width 20.
|
|
line.long 0x08 "FBS_RX_PMP_REG_FIS,PMP status of register FIS reception"
|
|
hexmask.long.word 0x08 16.--31. 1. " SPARE ,FBS_RX_PMP_REG_FIS_SPARE_31_16"
|
|
textline " "
|
|
eventfld.long 0x08 15. " PMP15 ,FBS_RX_PMP_REG_FIS_PMP15" "INIT,CLR"
|
|
eventfld.long 0x08 14. " PMP14 ,FBS_RX_PMP_REG_FIS_PMP14" "INIT,CLR"
|
|
eventfld.long 0x08 13. " PMP13 ,FBS_RX_PMP_REG_FIS_PMP13" "INIT,CLR"
|
|
eventfld.long 0x08 12. " PMP12 ,FBS_RX_PMP_REG_FIS_PMP12" "INIT,CLR"
|
|
textline " "
|
|
eventfld.long 0x08 11. " PMP11 ,FBS_RX_PMP_REG_FIS_PMP11" "INIT,CLR"
|
|
eventfld.long 0x08 10. " PMP10 ,FBS_RX_PMP_REG_FIS_PMP10" "INIT,CLR"
|
|
eventfld.long 0x08 9. " PMP9 ,FBS_RX_PMP_REG_FIS_PMP9" "INIT,CLR"
|
|
eventfld.long 0x08 8. " PMP8 ,FBS_RX_PMP_REG_FIS_PMP8" "INIT,CLR"
|
|
textline " "
|
|
eventfld.long 0x08 7. " PMP7 ,FBS_RX_PMP_REG_FIS_PMP7" "INIT,CLR"
|
|
eventfld.long 0x08 6. " PMP6 ,FBS_RX_PMP_REG_FIS_PMP6" "INIT,CLR"
|
|
eventfld.long 0x08 5. " PMP5 ,FBS_RX_PMP_REG_FIS_PMP5" "INIT,CLR"
|
|
eventfld.long 0x08 4. " PMP4 ,FBS_RX_PMP_REG_FIS_PMP4" "INIT,CLR"
|
|
textline " "
|
|
eventfld.long 0x08 3. " PMP3 ,FBS_RX_PMP_REG_FIS_PMP3" "INIT,CLR"
|
|
eventfld.long 0x08 2. " PMP2 ,FBS_RX_PMP_REG_FIS_PMP2" "INIT,CLR"
|
|
eventfld.long 0x08 1. " PMP1 ,FBS_RX_PMP_REG_FIS_PMP1" "INIT,CLR"
|
|
eventfld.long 0x08 0. " PMP0 ,FBS_RX_PMP_REG_FIS_PMP0" "INIT,CLR"
|
|
textline ""
|
|
width 4.
|
|
line.long 0x0C "MP,Motion Protection"
|
|
bitfld.long 0x0C 10. " USE_EOF_DETECTION ,MP_USE_EOF_DETECTION" "RESET,SET"
|
|
bitfld.long 0x0C 9. " COMRESET_ON_TIMEOUT ,MP_COMRESET_ON_TIMEOUT" "RESET,SET"
|
|
bitfld.long 0x0C 8. " UNLOAD_WITH_COMRESET ,MP_UNLOAD_WITH_COMRESET" "RESET,SET"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " MPA ,MP_MPA" "CLEARED,SET"
|
|
eventfld.long 0x0C 5. " MPIS , MP_MPIS" "CLEARED,SET"
|
|
bitfld.long 0x0C 4. " MPES ,MP_MPES" "CLEARED,SET"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " MPSIE ,MP_MPSIE" "CLEARED,SET"
|
|
bitfld.long 0x0C 1. " MPGBE ,MP_MPGBE" "CLEARED,SET"
|
|
bitfld.long 0x0C 0. " MPE ,MP_MPE" "CLEARED,SET"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
; tree "SATA0 Configuration space"
|
|
; base ad:0x70021000
|
|
; %include tegrak1/sataconf.ph ad:0x70021000 SATA0
|
|
; tree.end
|
|
tree "SATA Configuration space"
|
|
base ad:0x70021000
|
|
tree "PCI Configuration Registers"
|
|
width 8.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CFG_0,PCI Vendor and Device ID Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DEVICE_ID_UNIT ,Identify the particular device"
|
|
hexmask.long.word 0x00 0.--15. 1. " VENDOR_ID ,Identify the manufacturer of the device"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CFG_1,PCI Device Control Register"
|
|
rbitfld.long 0x00 31. " DETECTED_PERR ,Indicates that the device has detected a parity error" "Not active,Active"
|
|
eventfld.long 0x00 30. " SIGNALED_SERR ,Indicates that the device has asserted SERR#" "Not active,Active"
|
|
eventfld.long 0x00 29. " RECEIVED_MASTER ,Indicates that a master device's transaction (except for Special Cycle) was terminated with a master-abort" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.long 0x00 28. " RECEIVED_TARGET ,Indicates that a master device's transaction was terminated with a target-abort" "Not aborted,Aborted"
|
|
rbitfld.long 0x00 27. " SIGNALED_TARGET ,Indicates that the device has terminated a transaction with target-abort" "Not aborted,Aborted"
|
|
rbitfld.long 0x00 25.--26. " DEVSEL_TIMING ,The timing of DEVSEL#" "Fast,Medium,Slow,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 24. " CFG_1_MASTER_DATA_PERR ,MASTER_DATA_PERR" "NOT_ACTIVE,?..."
|
|
rbitfld.long 0x00 23. " FAST_BACK2BACK ,Back-to-back transfers handling capability" "Not supported,Supported"
|
|
rbitfld.long 0x00 21. " 66MHZ ,66 MHz PCI Bus operation capability" "Not supported,Supported"
|
|
textline " "
|
|
rbitfld.long 0x00 20. " CAPLIST ,Capabilities list presence" "Not present,Present"
|
|
rbitfld.long 0x00 19. " INTR_STATUS ,State of the interrupt in the device/function" "0,1"
|
|
bitfld.long 0x00 10. " INTR_DISABLE ,Disables the assertion of INTx# signal" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " BACK2BACK ,BACK2BACK Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SERR ,SERR Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " STEP ,STEP Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " PERR ,PERR Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " PALETTE_SNOOP ,Special palette snooping behaviour enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " WRITE_AND_INVAL ,Memory Write and Invalidate command usage enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " SPECIAL_CYCLE ,SPECIAL_CYCLE Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BUS_MASTER ,Bus master behaviour Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MEMORY_SPACE ,Memory space addresses Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IO_SPACE ,IO Space addresses Enable" "Disabled,Enabled"
|
|
rgroup.long 0x08++0x07
|
|
line.long 0x00 "CFG_2,PCI Revision ID and Class Code Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CLASS_CODE ,Identifies generic function of the device"
|
|
bitfld.long 0x00 15. " BUS_MASTER ,Bus mastering capability" ",YES"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SEC_OP_MODE ,Secondary Operating Mode" "COMP,NTV"
|
|
bitfld.long 0x00 8. " PRI_OP_MODE ,Primary Operating Mode" "COMP,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " REVISION_ID ,Device specific revision identifier"
|
|
line.long 0x04 "CFG_3,PCI Configuration Register"
|
|
bitfld.long 0x04 23. " HEADER_TYPE_FUNC ,CFG_3_HEADER_TYPE_FUNC" "Single,Multi"
|
|
hexmask.long.byte 0x04 16.--22. 1. " HEADER_TYPE_DEVICE ,Layout of the bytes [3F:10] in configuration space and single/multiple function capability identification"
|
|
bitfld.long 0x04 11.--15. " LATENCY_TIMER ,Latency Timer value" "0_CLOCKS,8_CLOCKS,16_CLOCKS,24_CLOCKS,32_CLOCKS,40_CLOCKS,48_CLOCKS,56_CLOCKS,64_CLOCKS,72_CLOCKS,80_CLOCKS,88_CLOCKS,96_CLOCKS,104_CLOCKS,112_CLOCKS,120_CLOCKS,128_CLOCKS,136_CLOCKS,144_CLOCKS,152_CLOCKS,160_CLOCKS,168_CLOCKS,176_CLOCKS,184_CLOCKS,192_CLOCKS,200_CLOCKS,208_CLOCKS,216_CLOCKS,224_CLOCKS,232_CLOCKS,240_CLOCKS,248_CLOCKS"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " CACHE_LINE_SIZE ,CFG_3_CACHE_LINE_SIZE"
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "CFG_4,PCI Configuration Register"
|
|
hexmask.long 0x00 3.--31. 0x08 " BASE_ADDRESS ,Base Address"
|
|
line.long 0x04 "CFG_5,PCI Configuration Register"
|
|
hexmask.long 0x04 3.--31. 0x08 " BASE_ADDRESS ,Base Address"
|
|
line.long 0x08 "CFG_6,PCI Configuration Register"
|
|
hexmask.long 0x08 3.--31. 0x08 " BASE_ADDRESS ,Base Address"
|
|
line.long 0x0C "CFG_7,PCI Configuration Register"
|
|
hexmask.long 0x0C 3.--31. 0x08 " BASE_ADDRESS ,Base Address"
|
|
line.long 0x10 "CFG_8,PCI Configuration Register"
|
|
hexmask.long 0x10 3.--31. 0x08 " BASE_ADDRESS ,Base Address"
|
|
rbitfld.long 0x10 0. " SPACE_TYPE ,Space Type" "Memory,IO"
|
|
line.long 0x14 "CFG_9,PCI Memory BAR for AHCI Register"
|
|
hexmask.long 0x14 3.--31. 0x08 " BASE_ADDRESS ,Base Address"
|
|
rbitfld.long 0x14 0. " SPACE_TYPE ,Space Type" "Memory,IO"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "CFG_11,PCI Subsystem Vendor ID and Subsystem ID Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SUBSYSTEM_ID ,SUBSYSTEM ID"
|
|
hexmask.long.word 0x00 0.--15. 1. " VENDOR_ID ,VENDOR ID"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "CFG_13,PCI Capability Pointer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAP_PTR ,Offset into configuration space where the capabilities list begins"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CFG_15,PCI Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MAX_LAT ,Maximum time required to gain access to the PCI"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MIN_GNT ,Burst period assuming 33MHz CLK rate"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTR_LINE ,Interrupt routing information"
|
|
tree.end
|
|
tree "Device Specific Configuration Registers"
|
|
width 15.
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CFG_16,Write Subsystem Vendor ID and Subsystem ID Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SUBSYSTEM_ID ,Subsystem ID"
|
|
hexmask.long.word 0x00 0.--15. 1. " VENDOR_ID ,Vendor ID"
|
|
sif !CPUIS("TEGRAX2")
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CFG_17,PCI Power Management Capabilities Register"
|
|
bitfld.long 0x00 31. " PME_SUPPORT_D3C ,PME_SUPPORT_D3C" "NO,YES"
|
|
bitfld.long 0x00 30. " PME_SUPPORT_D3H ,PME_SUPPORT_D3H" "NO,YES"
|
|
bitfld.long 0x00 29. " PME_SUPPORT_D2 ,PME_SUPPORT_D2" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PME_SUPPORT_D1 ,PME_SUPPORT_D1" "NO,YES"
|
|
bitfld.long 0x00 27. " PME_SUPPORT_D0 ,PME_SUPPORT_D0" "NO,YES"
|
|
bitfld.long 0x00 26. " D2_SUPPORT ,D2_SUPPORT" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x00 25. " D1_SUPPORT ,D1_SUPPORT" "NO,YES"
|
|
bitfld.long 0x00 22.--24. " AUX_CURRENT ,AUX_CURRENT" "0,55MA,100MA,160MA,220MA,270MA,320MA,375MA"
|
|
bitfld.long 0x00 21. " DEV_SPEC_INIT ,DEV_SPEC_INIT" "NOT_NEEDED,NEEDED"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PME_CLOCK ,PME_CLOCK" "NOT_NEEDED,NEEDED"
|
|
bitfld.long 0x00 16.--18. " PCIPM_REV ,PCIPM_REV" ",,11,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " NEXT_PTR ,NEXT_PTR"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAP_ID ,CAP_ID"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CFG_18,PCI Power Management Control/Status Register"
|
|
rbitfld.long 0x00 15. " PME_STATUS ,PME Status" "NOT_ACTIVE,?..."
|
|
rbitfld.long 0x00 8. " PME ,PME Enable" "Disabled,?..."
|
|
bitfld.long 0x00 0.--1. " PM_STATE ,Current power state" "D0,D1,D2,D3hot"
|
|
endif
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "FPCI_SW,FPCI_SW"
|
|
bitfld.long 0x00 8. " WAKEUP_PLL ,WAKEUP_PLL" "0,1"
|
|
bitfld.long 0x00 0. " IDDQ_PG ,IDDQ_PG" "0,1"
|
|
sif !CPUIS("TEGRAX2")
|
|
rgroup.long 0x8C++0x07
|
|
line.long 0x00 "ATACAP0,Serial ATA Capability Register 0"
|
|
bitfld.long 0x00 20.--23. " MAJREV ,MAJREV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " MINREV ,MINREV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CID ,CID_SATA"
|
|
line.long 0x04 "ATACAP1,Serial ATA Capability Register 1"
|
|
hexmask.long.word 0x04 4.--15. 1. " BAROFST ,BAROFST"
|
|
bitfld.long 0x04 0.--3. " BARLOC ,BARLOC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CFG_35,Serial ATA IDP Index"
|
|
hexmask.long.word 0x00 2.--12. 1. " IDP_INDEX ,IDP_INDEX"
|
|
group.long 0xB0++0x0F
|
|
line.long 0x00 "MSI_CTRL,MSI Message Control and Capability Register"
|
|
rbitfld.long 0x00 24. " VECTOR_MASK_CAP ,MSI-per-vector masking support" "DIS,EN"
|
|
rbitfld.long 0x00 23. " 64_ADDR_CAP ,64-bit message address generation capability" "DIS,EN"
|
|
bitfld.long 0x00 20.--22. " MULT_MSG_ENABLE ,Number of allocated vectors" "1,2,3,4,16,32,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 17.--19. " MULT_MSG_CAP ,Number of requested vectors" "1,2,4,8,16,32,?..."
|
|
bitfld.long 0x00 16. " MSI_ENABLE ,MSI capability enable" "OFF,ON"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NEXT_PTR ,Identifies the next item in the capabilities list"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAP_ID ,MSI capability block"
|
|
line.long 0x04 "MSI_ADDR1,MSI Message Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " MSG_ADDR ,System-specified message address"
|
|
line.long 0x08 "MSI_ADDR2,MSI Message Upper Address Register"
|
|
line.long 0x0C "MSI_DATA,MSI Message Data Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " MSG_DATA ,System-specified message"
|
|
endif
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "MSI_QUEUE,MSI Message Queue Configuration Register"
|
|
bitfld.long 0x00 3. " MSI_QUEUE3 ,MSI message to VC queue 3 send enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MSI_QUEUE2 ,MSI message to VC queue 2 send enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MSI_QUEUE1 ,MSI message to VC queue 1 send enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSI_QUEUE0 ,MSI message to VC queue 0 send enable" "Disabled,Enabled"
|
|
sif !CPUIS("TEGRAX2")
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "MSI_MAP,MSI Mapping Capability Register"
|
|
rbitfld.long 0x00 27.--31. " CAP_TYPE , MSI Mapping Capability" ",,,,,,,,,,,,,,,Default,?..."
|
|
rbitfld.long 0x00 17. " FIXD ,Indicates that the next 2 dwords for programmable address are present in the capability" "OFF,ON"
|
|
bitfld.long 0x00 16. " EN ,Mapping activity" "OFF,ON"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " NEXT_PTR ,NEXT_PTR field points to the next item in the capabilities list"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAP_ID ,HT capability list item identification"
|
|
endif
|
|
group.long 0xF0++0x0F
|
|
line.long 0x00 "INDIRECT_IDP0,IDP pair to access 257-4K address space - Address register"
|
|
hexmask.long.word 0x00 2.--11. 1. " IDP_INDEX ,IDP_INDEX"
|
|
line.long 0x04 "INDIRECT_IDP1,IDP pair to access 257-4K address space - DATA register"
|
|
line.long 0x08 "FPCICFG,FPCI Debug register"
|
|
bitfld.long 0x08 28.--31. " DEVID_OVERRIDE_ID ,DEVID_OVERRIDE_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 27. " DEVID_OVERRIDE_ENABLE ,DEVID_OVERRIDE_ENABLE: Indicates a Linux system when set" "OFF,ON"
|
|
bitfld.long 0x08 26. " DROP_ON_TA_ERR_ENABLE ,DROP_ON_TA_ERR_ENABLE" "OFF,ON"
|
|
textline " "
|
|
bitfld.long 0x08 25. " DROP_ON_MA_ERR_ENABLE ,DROP_ON_MA_ERR_ENABLE" "OFF,ON"
|
|
bitfld.long 0x08 24. " DROP_ON_ERR_ENABLE ,DROP_ON_ERR_ENABLE" "OFF,ON"
|
|
bitfld.long 0x08 23. " FIX_DEADLOCK_ENABLE ,FIX_DEADLOCK_ENABLE" "OFF,ON"
|
|
textline " "
|
|
bitfld.long 0x08 22. " PASSIVE_UID_CLMP_ENABLE ,PASSIVE_UID_CLMP_ENABLE" "OFF,ON"
|
|
rbitfld.long 0x08 21. " PASSIVE_UID_CLMP ,PASSIVE_UID_CLMP" "NOT_SUPP,SUPP"
|
|
bitfld.long 0x08 16.--20. " NONISO_READ_CREDITS ,NONISO_READ_CREDITS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 15. " ERR_SEVERITY , ERR_SEVERITY" "NONFATAL,FATAL"
|
|
bitfld.long 0x08 14. " TGTDONE_PASSPW ,TGTDONE_PASSPW" "CLR,SET"
|
|
bitfld.long 0x08 8. " CREDIT_SYS_ENABLE ,Read credit system enable" "OFF,ON"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " COHCMD ,COHCMD" "TOY,COH,NONCOH,?..."
|
|
bitfld.long 0x08 4.--5. " RSPPASSPW ,Issue of non-posted commands" "TOY,PASS,NOPASS,?..."
|
|
bitfld.long 0x08 2.--3. " PASSPW ,Issue of non-broadcast commands" "TOY,PASS,NOPASS,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " ISOCMD ,Issue of ISO/NONISO-counterparts influenced commands issue" "TOY,ISO,NONISO,?..."
|
|
line.long 0x0C "SCRATCH_1,General purpose scratch register used for communication between the storage SW and the SBIOS"
|
|
textline " "
|
|
width 16.
|
|
group.long 0x114++0x0F
|
|
line.long 0x00 "NVOOB,Serial ATA internal PHY control register used in nvoob"
|
|
bitfld.long 0x00 31. " RETIMED_FAREND_LOOPBACK_EN ,SATA controller farend retimed loopback mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--30. " COMMA_CNT ,The number of comma characters seen for the phy_rdy to go high after going through OOB signalling" "0,16,32,48,64,80,96,112"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SQUELCH_FILTER_LENGTH ,Amount of glitch duration that are filtered out" "6.66ns,13.32ns,19.98ns,26.64ns"
|
|
bitfld.long 0x00 24.--25. " SQUELCH_FILTER_MODE ,Squelch signal filtering mode selection" "NONE,LOW,HIGH,?..."
|
|
line.long 0x04 "CROSS_BAR,SATA CROSS BAR: contains the phy_select"
|
|
line.long 0x08 "PMUCTL,SATA PHY Control Register"
|
|
rbitfld.long 0x08 24.--27. " CORE_STS ,Current core_act_sts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DEV_STS_HOLD ,Number of txclk cycles to hold the dev_act_tog and dev_act_sts"
|
|
textline " "
|
|
bitfld.long 0x08 8. " HOLD_SEND_ALIGN_DIS ,HOLD_SEND_ALIGN_DIS" "NO,YES"
|
|
bitfld.long 0x08 2. " FORCE_CORE_CLAMP ,Core clock clamp enable" "DIS,EN"
|
|
line.long 0x0C "CFG_PHY_0,CFG_PHY_0"
|
|
bitfld.long 0x0C 6. " PLL_IDDQ_OVERRIDE_VAL ,PLL_IDDQ_OVERRIDE_VAL" "NO,YES"
|
|
bitfld.long 0x0C 5. " PLL_IDDQ_OVERRIDE ,PLL_IDDQ_OVERRIDE" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--4. " RBC_RESET_DELAY ,Number of tx_clk ticks (300MHz) between the deassertion of sata2phy_ch{1,2}_cdr_reset and the release of ch{1,2}_rbc_reset_" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x12C++0x0F
|
|
line.long 0x00 "CFG_PHY_1,CFG_PHY_1"
|
|
bitfld.long 0x00 26. " DONT_CHK_PHY_RESET ,DONT_CHK_PHY_RESET" "0,1"
|
|
bitfld.long 0x00 25. " COMWAKE_GLOBAL ,COMWAKE_GLOBAL" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PLL_PD_NO_CMDS ,PLL_PD_NO_CMDS" "0,1"
|
|
bitfld.long 0x00 23. " PADS_IDDQ_EN ,PADS_IDDQ_EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PAD_PLL_IDDQ_EN ,PAD_PLL_IDDQ_EN" "0,1"
|
|
bitfld.long 0x00 21. " SEND_OOB_DATA_IN_LOW_POWER ,SEND_OOB_DATA_IN_LOW_POWER" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " NO_OVERRIDE_STAT_IDLE_PHYRDY ,NO_OVERRIDE_STAT_IDLE_PHYRDY" "0,1"
|
|
bitfld.long 0x00 16.--19. " NUMBER_OF_COMMA_WINDOWS ,NUMBER_OF_COMMA_WINDOWS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 4.--15. 1. " COUNT_FOR_COMMA_WAIT ,COUNT_FOR_COMMA_WAIT"
|
|
bitfld.long 0x00 3. " DONT_USE_COMMA_FOR_PHYRDY_LOW ,DONT_USE_COMMA_FOR_PHYRDY_LOW" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EN_ASYNC_REC_ARC_IN_HRRDY ,EN_ASYNC_REC_ARC_IN_HRRDY" "0,1"
|
|
bitfld.long 0x00 1. " HOLD_RBC_RESET_IN_BIST ,HOLD_RBC_RESET_IN_BIST" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ASSERT_PHYRDY_FOR_ALL_BIST ,ASSERT_PHYRDY_FOR_ALL_BIST" "0,1"
|
|
line.long 0x04 "CFG2NVOOB_1,CFG2NVOOB_1"
|
|
hexmask.long.word 0x04 18.--26. 1. " COMINIT_IDLE_CNT_HIGH ,COMINIT_IDLE_CNT_HIGH"
|
|
hexmask.long.word 0x04 9.--17. 1. " ACTIVE_CNT_LOW ,ACTIVE_CNT_LOW"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--8. 1. " ACTIVE_CNT_HIGH ,ACTIVE_CNT_HIGH"
|
|
line.long 0x08 "CFG2NVOOB_2,CFG2NVOOB_2"
|
|
hexmask.long.word 0x08 18.--26. 1. " COMINIT_IDLE_CNT_LOW ,COMINIT_IDLE_CNT_LOW"
|
|
hexmask.long.word 0x08 9.--17. 1. " ACTIVE_CNT_HIGH ,ACTIVE_CNT_HIGH"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--8. 1. " ACTIVE_CNT_LOW ,ACTIVE_CNT_LOW"
|
|
line.long 0x0C "CFG_PHY_ACTIVE,CFG_PHY_ACTIVE"
|
|
hexmask.long.tbyte 0x0C 10.--31. 1. " FROM_SLUMBER ,Time to be in SLUMEBR state after we receive a COMWAKE from the device or the Link Layer lowers the slumber flag"
|
|
hexmask.long.word 0x0C 0.--9. 1. " FROM_PARTIAL ,Time to be in PARTIAL state after we receive a COMWAKE from the device or the Link Layer lowers the partial flag"
|
|
group.long 0x170++0x13
|
|
line.long 0x00 "FIFO,FIFO"
|
|
bitfld.long 0x00 16.--19. " P2L_FIFO_DEPTH ,Effective depth of p2l FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " L2P_FIFO_DEPTH ,Effective depth of l2p FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CFG_LINK_0,CFG_LINK_0"
|
|
bitfld.long 0x04 7. " GOTO_SEND_SYNC_P ,Sending Link SM to L_SEND_SYNC_P in BIST" "NO,YES"
|
|
bitfld.long 0x04 6. " AUTO_REPEAT_PRIMS ,AUTO_REPEAT_PRIMS" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x04 5. " DEBOUNCE_PHYRDY_PERIOD ,Hysteresis period" "SHORT,LONG"
|
|
bitfld.long 0x04 4. " DEBOUNCE_PHYRDY ,Phyrdy debounce behaviour" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DELAY_HOTPLUG_INTR ,Generation of hotplug interrupts when we get PHYRDY" "NO,YES"
|
|
bitfld.long 0x04 2. " SET_BSY_BIT_MTHD ,SET_BSY_BIT_MTHD" "COMINIT,PHYRDY"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " LED_MIN_ON_TIME ,LED blinking" "OFF,20MS,40MS,80MS"
|
|
line.long 0x08 "CFG_LINK_1,CFG_LINK_1"
|
|
hexmask.long.word 0x08 16.--31. 1. " GEN3_DWRD_WAIT_CNT ,Number of generation3 ALIGN dwords the controller sends to drive while waiting for gen3 align from drive"
|
|
hexmask.long.word 0x08 0.--15. 1. " GEN2_DWRD_WAIT_CNT ,Number of generation2 ALIGN dwords the controller sends to drive while waiting for gen2 align from drive"
|
|
line.long 0x0C "CFG_LINK_2,CFG_LINK_2"
|
|
bitfld.long 0x0C 12.--15. " PHYRDY_USE_ITH_BIT ,PHYRDY_USE_ITH_BIT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 11. " USE_BIT_FOR_DEBOUNCE ,USE_BIT_FOR_DEBOUNCE" "0,1"
|
|
textline " "
|
|
hexmask.long.word 0x0C 0.--10. 1. " PHYRDY_DBNC_MUX ,Debounced version of PHYRDY which has two options: 10 ms and 10 us"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "CFG_TRANS_0,CFG_TRANS_0"
|
|
bitfld.long 0x00 1. " USE_RISE_EDGE_STATUS_RESET ,USE_RISE_EDGE_STATUS_RESET" "0,1"
|
|
bitfld.long 0x00 0. " F2I_FIFO_FLUSH_FIX ,F2I_FIFO_FLUSH_FIX" "0,1"
|
|
textline " "
|
|
width 19.
|
|
width 16.
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "CFG,Config"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CTRL_TICKS_FOR_MASTER_TO ,Control ticks used in Master-slave emulation"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "IDE1,OLD IDE TIMING"
|
|
rgroup.long 0x498++0x03
|
|
line.long 0x00 "FEATURE,Feature Register"
|
|
bitfld.long 0x00 18.--23. " FEATURE_AHCI_ESATA_DIS ,FEATURE_AHCI_ESATA_DIS" "NO,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,YES"
|
|
bitfld.long 0x00 10.--12. " RAID_FUNCTION_DIS ,RAID_FUNCTION_DIS" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PORTS_2_3_DIS ,PORTS_2_3_DIS" "NO,YES"
|
|
bitfld.long 0x00 8. " PORTS_0_1_DIS ,PORTS_0_1_DIS" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AHCI_POWER_DIS ,AHCI_POWER_DIS" "NO,YES"
|
|
bitfld.long 0x00 3. " FBS_DIS ,FBS_DIS" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x00 2. " GEN3_EN ,GEN3_EN" "NO,YES"
|
|
bitfld.long 0x00 1. " GEN2_EN ,GEN2_EN" "NO,YES"
|
|
group.long 0x4A0++0x0B
|
|
line.long 0x00 "CTL1,Miscellaneous CTL1"
|
|
bitfld.long 0x00 9. " BLK_NONPIO_IDP ,NONPIO read in the case of IDP read suppression (second read block)" "Not blocked,Blocked"
|
|
bitfld.long 0x00 0. " SATA_ADNVCD_SPD_NEGO ,Advanced way of detecting SATA speeds" "NO,YES"
|
|
line.long 0x04 "BKDOOR_CC,Backdoor update of the programming interface field and class code of the CFG2[15:8] register"
|
|
hexmask.long.word 0x04 16.--31. 1. " CLASS_CODE ,CLASS_CODE"
|
|
hexmask.long.byte 0x04 8.--15. 1. " PROG_IF ,PROG_IF"
|
|
line.long 0x08 "CFG_CTRL_1,CFG_CTRL_1"
|
|
bitfld.long 0x08 1. " SATA_CAP ,SATA capability enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " 48BIT_ADDRESS_DISABLE ,48-bit addressing mode disable" "Not disabled,Disabled"
|
|
textline " "
|
|
width 18.
|
|
group.long 0x4F0++0x07
|
|
line.long 0x00 "PERF0,SATA implementation options"
|
|
bitfld.long 0x00 28. " DONT_DELAY_ROK ,Optimization feature on DMA reads" "FALSE,TRUE"
|
|
bitfld.long 0x00 25.--26. " SATA_PLL_POWERDOWN ,SATA_PLL_POWERDOWN" "NO,YES,?..."
|
|
bitfld.long 0x00 7.--11. " MIN_FPCI_CLK_FREQ ,Minimum frequency at which the fpci_clk should run in increments of 1/16th" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "PERF1,SATA implementation options"
|
|
hexmask.long.byte 0x04 24.--31. 1. " MAX_WATER_MARK ,Maximum occupancy of the two i2f_fifos"
|
|
hexmask.long.byte 0x04 8.--15. 1. " HIGH_WATER_MARK_PIO ,PIO reads high water mark"
|
|
hexmask.long.byte 0x04 0.--7. 1. " HIGH_WATER_MARK ,Configures the read FIFO limit at which point the host starts sending HOLD primitives to back-off the data transfer from device"
|
|
group.long 0x530++0x07
|
|
line.long 0x00 "CHXCFG1,CHXCFG1"
|
|
bitfld.long 0x00 12.--15. " PHY_CHX_RX_CTL ,PHY_CHX_RX_CTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " PHY_CHX_TX_CTL ,PHY_CHX_TX_CTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " CHX_NEAR_LOOP_BACK ,CHX_NEAR_LOOP_BACK" "INACTIVE,ACTIVE"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHX_RESET ,CHX_RESET" "INACTIVE,ACTIVE"
|
|
line.long 0x04 "PHY_CTRL,PHY_CTRL"
|
|
bitfld.long 0x04 3.--4. " PLL_SLEEP ,Power setting of SATA2 internal PHY" "ACTIVE,3G_DISABLED,ALL_CLKS_DISABLED,PLL_DISABLED"
|
|
bitfld.long 0x04 0. " SLUMBER_DURING_D3 ,Slumber During D3 Enable" "Disabled,Enabled"
|
|
group.long 0x53C++0x07
|
|
line.long 0x00 "LDT,LDT Unit ID Register"
|
|
bitfld.long 0x00 8.--12. " NON_ISO_UNIT_ID ,Non-ISO Unit ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " ISO_UNIT_ID ,ISO Unit ID. Hard-wired to 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "CTRL,CTRL"
|
|
bitfld.long 0x04 30. " ENABLE_CH2_CH4_INTR ,ENABLE_CH2_CH4_INTR" "NO,YES"
|
|
bitfld.long 0x04 29. " ENABLE_CH1_CH3_INTR ,ENABLE_CH1_CH3_INTR" "NO,YES"
|
|
bitfld.long 0x04 27. " NP_RSP_ERROR_INTR ,NP_RSP_ERROR_INTR" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x04 26. " PW_CMD_ERROR_INTR ,PW_CMD_ERROR_INTR" "NO,YES"
|
|
bitfld.long 0x04 25. " NP_RSP_ERROR_INTR_EN ,NP_RSP_ERROR_INTR_EN" "NO,YES"
|
|
bitfld.long 0x04 24. " PW_CMD_ERROR_INTR_EN ,PW_CMD_ERROR_INTR_EN" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x04 21. " CH4_EN ,CH4_EN" "NO,YES"
|
|
bitfld.long 0x04 20. " CH3_EN ,CH3_EN" "NO,YES"
|
|
bitfld.long 0x04 3. " INTF_ERR_HANDLING_EN ,SATA interface errors advanced error handling feature enable" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x04 2. " BAR5_SPACE_EN ,BAR5 space usage enable" "NO,YES"
|
|
bitfld.long 0x04 1. " PRI_CHANNEL_EN ,Primary SATA channel enable" "NO,YES"
|
|
bitfld.long 0x04 0. " SEC_CHANNEL_EN ,Secondary SATA channel enable" "NO,YES"
|
|
group.long 0x54C++0x0F
|
|
line.long 0x00 "CFG_SATA,CFG_SATA"
|
|
bitfld.long 0x00 16. " FORCE_NATIVE ,FORCE_NATIVE Enable" "DISABLED,ENABLED"
|
|
bitfld.long 0x00 15. " CTRL_ALT_UID_SCHEME ,CTRL_ALT_UID_SCHEME" "0,1"
|
|
rbitfld.long 0x00 14. " CTRL_SATA_GEN3_CAPABLE ,CTRL_SATA_GEN3_CAPABLE" "NO,YES"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " CTRL_SATA_GEN2_CAPABLE ,CTRL_SATA_GEN2_CAPABLE" "NO,YES"
|
|
bitfld.long 0x00 12. " BACKDOOR_PROG_IF_EN ,BACKDOOR_PROG_IF_EN" "NO,YES"
|
|
bitfld.long 0x00 7.--11. " PORT2UNITID_MAPPING ,PORT2UNITID_MAPPING" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 6. " MSI_CAP_DISABLE , MSI_CAP_DISABLE" "NO,YES"
|
|
bitfld.long 0x00 5. " MSIX_CAP_DISABLE ,MSIX_CAP_DISABLE" "NO,YES"
|
|
bitfld.long 0x00 4. " USE_40B_ADDR ,NVIDIA style 40b addressing while DMAing data" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERROR_HANDLING ,ERROR_HANDLING" "NO,YES"
|
|
bitfld.long 0x00 2. " CTRL_RAID_MODE_CTRL ,RAID Controller mode" "OEM,CHANNEL"
|
|
bitfld.long 0x00 1. " CTRL_STORAGE_FEATURE ,General purpose bit that SW can use to distinguish between Advanced and Basic storage controller modes" "ADVANCED,BASIC"
|
|
line.long 0x04 "CFG_MISC,CFG_MISC"
|
|
bitfld.long 0x04 10. " PHY_RESET_USAGE_MODE2 ,LOCKDET or CFG bit select for pi_reset" "0,1"
|
|
bitfld.long 0x04 9. " PHY_RESET_USAGE_MODE1 ,ATA status register quick update during PIO writes enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PHY_RESET_USAGE_MODE0 ,LOCKDET use as PHY reset" "0,1"
|
|
bitfld.long 0x04 7. " CFG_MISC_LINK_SM_MODE3 ,L_IDLE features" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CFG_MISC_LINK_SM_MODE2 ,L_IDLE features" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CFG_MISC_LINK_SM_MODE0 ,Hold a bypass enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PHY_OOB_SEQ_MODE1 ,COMRESET behavior control" "Send 1 on scontrol_det[0] write,Send while scontrol_det active"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PHY_OOB_SEQ_MODE0 ,COMWAKE send back off on COMWAKE received from drive" "0,1"
|
|
line.long 0x08 "LOWPOWER_COUNT ,LOWPOWER_COUNT"
|
|
bitfld.long 0x08 4.--7. " LOWPOWER_COUNT_SLUMBER ,LOWPOWER_COUNT_SLUMBER" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. " LOWPOWER_COUNT_PARTIAL ,LOWPOWER_COUNT_PARTIAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "DEVSLP_CTRL0,DEVSLP_CTRL0"
|
|
rbitfld.long 0x0C 0. " PARTIAL_OR_SLUMBER ,PORT0_INTFC_IN_PARTIAL_OR_SLUMBER" "0,1"
|
|
group.long 0x680++0x07
|
|
line.long 0x00 "INDEX,Index Mask Register"
|
|
bitfld.long 0x00 3. " CH04 ,CH04" "UNSELECTED,SELECTED"
|
|
bitfld.long 0x00 2. " CH03 ,CH03" "UNSELECTED,SELECTED"
|
|
bitfld.long 0x00 1. " CH02 ,CH02" "UNSELECTED,SELECTED"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CH01 ,CH01" "UNSELECTED,SELECTED"
|
|
line.long 0x04 "CHX_MISC ,SATA Miscellaneous Control Register"
|
|
bitfld.long 0x04 0. " LED_DISABLE ,LED_DISABLE" "0,1"
|
|
textline " "
|
|
width 20.
|
|
group.long 0x690++0x0F
|
|
line.long 0x00 "CHX_PHY_CTRL1_GEN1,SATA PHY Control Register (GEN1)"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 26.--29. " TX_DRV_CNTL ,TX_DRV_CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--25. " TX_PEAK_PRE ,TX_PEAK_PRE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 24.--27. " TX_DRV_CNTL ,TX_DRV_CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " TX_PEAK_PRE ,TX_PEAK_PRE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
bitfld.long 0x00 16.--19. " TX_CMADJ ,TX_CMADJ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " TX_PEAK ,PEAK values for GEN1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TX_AMP ,AMP values for GEN1"
|
|
line.long 0x04 "CHX_PHY_CTRL1_GEN2,SATA PHY Control Register (GEN2)"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x04 26.--29. " TX_DRV_CNTL ,TX_DRV_CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--25. " TX_PEAK_PRE ,TX_PEAK_PRE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x04 24.--27. " TX_DRV_CNTL ,TX_DRV_CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--23. " TX_PEAK_PRE ,TX_PEAK_PRE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
hexmask.long.byte 0x04 12.--19. 1. " TX_PEAK ,PEAK values for GEN2"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " TX_CMADJ ,TX_CMADJ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TX_AMP ,AMP values for GEN2"
|
|
line.long 0x08 "CHX_PHY_CTRL1_GEN3,SATA PHY Control Register (GEN3)"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x08 26.--29. " TX_DRV_CNTL ,TX_DRV_CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 20.--25. " TX_PEAK_PRE ,TX_PEAK_PRE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x08 24.--27. " TX_DRV_CNTL ,TX_DRV_CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 20.--23. " TX_PEAK_PRE ,TX_PEAK_PRE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
hexmask.long.byte 0x08 12.--19. 1. " TX_PEAK ,PEAK values for GEN3"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " TX_CMADJ ,TX_CMADJ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TX_AMP ,AMP values for GEN3"
|
|
line.long 0x0C "CHX_PHY_CTRL2,SATA PHY Control Register"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
hexmask.long.word 0x0C 16.--31. 1. " CDR_CNTL_GEN2 ,CDR_CNTL_GEN2"
|
|
hexmask.long.word 0x0C 0.--15. 1. " CDR_CNTL_GEN1 ,CDR_CNTL_GEN1"
|
|
else
|
|
hexmask.long.byte 0x0C 16.--23. 1. " CDR_CNTL_GEN3 ,CDR_CNTL_GEN3"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " CDR_CNTL_GEN2 ,CDR_CNTL_GEN2"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CDR_CNTL_GEN1 ,CDR_CNTL_GEN1"
|
|
endif
|
|
textline " "
|
|
width 18.
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
group.long 0x6A0++0x0B
|
|
line.long 0x00 "CHX_PHY_CTRL24,SATA PHY Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDR_CNTL_GEN3 ,CDR_CNTL_GEN3"
|
|
line.long 0x04 "CHX_PHY_CTRL25,SATA PHY Control Register"
|
|
line.long 0x08 "CHX_PHY_CTRL25,SATA PHY Control Register"
|
|
endif
|
|
group.long 0x6B0++0x2F
|
|
line.long 0x00 "CHX_PHY_CTRL3,SATA PHY Control Register"
|
|
rbitfld.long 0x00 29. " STATUS_RX_STAT_IDLE ,STATUS_RX_STAT_IDLE" "0,1"
|
|
rbitfld.long 0x00 28. " STATUS_TX_STAT_PRESENT ,STATUS_TX_STAT_PRESENT" "0,1"
|
|
rbitfld.long 0x00 26.--27. " STATUS_RX_RATE ,STATUS_RX_RATE" "GEN1,GEN2,GEN3,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 24.--25. " STATUS_TX_RATE ,STATUS_TX_RATE" "GEN1,GEN2,GEN3,?..."
|
|
bitfld.long 0x00 23. " RX_RATE_OVERRIDE ,RX_RATE_OVERRIDE" "DISABLED,ENABLED"
|
|
bitfld.long 0x00 20.--21. " RX_RATE ,RX_RATE" "GEN1,GEN2,GEN3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19. " TX_RATE_OVERRIDE ,TX_RATE_OVERRIDE" "DISABLED,ENABLED"
|
|
bitfld.long 0x00 16.--17. " TX_RATE ,TX_RATE" "GEN1,GEN2,GEN3,?..."
|
|
bitfld.long 0x00 15. " RX_DATA_READY ,RX_DATA_READY" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RX_DATA_EN ,RX_DATA_EN" "0,1"
|
|
bitfld.long 0x00 13. " TX_DATA_EN_OVERRIDE ,TX_DATA_EN_OVERRIDE" "NO,YES"
|
|
bitfld.long 0x00 12. " TX_DATA_EN ,TX_DATA Enable (manually)" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RX_SLEEP_OVERRIDE ,RX_SLEEP_OVERRIDE" "NO,YES"
|
|
bitfld.long 0x00 10. " TX_DATA_READY ,TX_DATA_READY" "NO,YES"
|
|
bitfld.long 0x00 8.--9. " RX_SLEEP ,Sleep mode on the SATA port selection (used for debug of the sleep modes)" "Active,Partial,Slumber,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TX_SLEEP_OVERRIDE ,Enable a forced sleep mode on the SATA port" "NO,YES"
|
|
bitfld.long 0x00 4.--5. " TX_SLEEP ,Sleep mode on the SATA port selection (used for debug of the sleep modes)" "Active,Partial,Slumber,Disabled"
|
|
bitfld.long 0x00 3. " CKBUFPD_OVRD ,CKBUFPD_OVRD" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CKBUFPD ,CKBUFPD" "0,1"
|
|
bitfld.long 0x00 0. " IDDQ ,IDDQ" "0,1"
|
|
line.long 0x04 "CHX_PHY_CTRL4,SATA PHY Control Register"
|
|
bitfld.long 0x04 30.--31. " SPARE_OUT ,SPARE_OUT" "0,1,2,3"
|
|
bitfld.long 0x04 28.--29. " SPARE_IN ,SPARE_IN" "0,1,2,3"
|
|
bitfld.long 0x04 27. " PRBS_CHK_EN ,PRBS_CHK_EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 26. " TEST_EN ,TEST_EN" "0,1"
|
|
bitfld.long 0x04 24. " RATE_MODE ,RATE_MODE" "0,1"
|
|
bitfld.long 0x04 20.--21. " RX_DIV ,RX_DIV" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 16.--17. " TX_DIV ,TX_DIV" "0,1,2,3"
|
|
bitfld.long 0x04 13. " RX_CDR_RESET ,RX_CDR_RESET" "0,1"
|
|
bitfld.long 0x04 12. " TX_SYNC ,TX_SYNC" "IDLE,NOW"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FED_LOOP ,FED_LOOP" "0,1"
|
|
bitfld.long 0x04 8.--10. " TX_DATA_MODE ,TX_DATA_MODE" "NORMAL,PRBS_2_7,0101010101,1100110011,0000011111,0101111100,?..."
|
|
bitfld.long 0x04 7. " FEA_LOOP ,FEA_LOOP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " FEA_MODE ,FEA_MODE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 3. " NEA_LOOP ,NEA_LOOP" "0,1"
|
|
bitfld.long 0x04 2. " NED_LOOP ,NED_LOOP" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " NED_MODE ,NED_MODE" "0,1,2,3"
|
|
line.long 0x08 "CHX_PHY_CTRL5,SATA PHY Control Register"
|
|
bitfld.long 0x08 24.--27. " CDR_MODE ,CDR_MODE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 19. " TX_RDET ,TX_RDET" "IDLE,START"
|
|
bitfld.long 0x08 18. " RX_IDLE_MODE ,RX_IDLE_MODE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 17. " RX_IDLE_BYP ,RX_IDLE_BYP" "DISABLED,ENABLED"
|
|
bitfld.long 0x08 16. " TX_RDET_BYP ,TX_RDET_BYP" "DISABLED,ENABLED"
|
|
bitfld.long 0x08 14.--15. " RX_IDLE_T ,RX_IDLE_T" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " TX_RDET_T ,TX_RDET_T" "0,1,2,3"
|
|
bitfld.long 0x08 8.--11. " TX_SEL_LOAD ,TX_SEL_LOAD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. " MISC_CNTL ,MISC_CNTL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "CHX_PHY_CTRL6,SATA PHY Control Register"
|
|
sif cpuis("TEGAX1")||cpuis("TEGRAX2")
|
|
rbitfld.long 0x0C 27.--28. " RX_BYP_DATA ,RX_BYP_DATA" "0,1,2,3"
|
|
bitfld.long 0x0C 26. " RX_TERM_MODE ,RX_TERM_MODE" "FALSE,TRUE"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " RX_TERM_EN ,RX_TERM_EN" "FALSE,TRUE"
|
|
bitfld.long 0x0C 24. " TX_TERM_MODE ,TX_TERM_MODE" "FALSE,TRUE"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x0C 16.--23. 1. " MISC_OUT ,MISC_OUT"
|
|
rbitfld.long 0x0C 14. " RX_BYP_IN ,RX_BYP_IN" "0,1"
|
|
rbitfld.long 0x0C 12. " TX_BYP_IN ,TX_BYP_IN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " RX_BYP_MODE ,RX_BYP_MODE" "FALSE,TRUE"
|
|
bitfld.long 0x0C 7. " RX_BYP_EN ,RX_BYP_EN" "FALSE,TRUE"
|
|
bitfld.long 0x0C 6. " RX_BYP_DIR ,RX_BYP_DIR" "FALSE,TRUE"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " RX_BYP_OUT ,RX_BYP_OUT" "FALSE,TRUE"
|
|
bitfld.long 0x0C 3. " TX_BYP_EN ,TX_BYP_EN" "FALSE,TRUE"
|
|
bitfld.long 0x0C 2. " TX_BYP_DIR ,TX_BYP_DIR" "FALSE,TRUE"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " TX_BYP_OUT ,TX_BYP_OUT" "FALSE,TRUE"
|
|
line.long 0x10 "CHX_PHY_CTRL7,SATA PHY Control Register"
|
|
bitfld.long 0x10 20.--23. " RX_WANDER_GEN3 ,RX_WANDER_GEN3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 18.--19. " RX_TERM_CNTL_GEN3 ,RX_TERM_CNTL_GEN3" "0,1,2,3"
|
|
bitfld.long 0x10 16.--17. " TX_TERM_CNTL_GEN3 ,TX_TERM_CNTL_GEN3" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x10 12.--15. " RX_WANDER_GEN2 ,RX_WANDER_GEN2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 10.--11. " RX_TERM_CNTL_GEN2 ,RX_TERM_CNTL_GEN2" "0,1,2,3"
|
|
bitfld.long 0x10 8.--9. " TX_TERM_CNTL_GEN2 ,TX_TERM_CNTL_GEN2" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x10 4.--7. " RX_WANDER_GEN1 ,RX_WANDER_GEN1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 2.--3. " RX_TERM_CNTL_GEN1 ,RX_TERM_CNTL_GEN1" "0,1,2,3"
|
|
bitfld.long 0x10 0.--1. " TX_TERM_CNTL_GEN1 ,TX_TERM_CNTL_GEN1" "0,1,2,3"
|
|
line.long 0x14 "CHX_PHY_CTRL8,SATA PHY Control Register"
|
|
rbitfld.long 0x14 16.--21. " RX_QEYE_OUT ,RX_QEYE_OUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x14 8. " RX_QEYE_EN_GEN3 ,RX_QEYE_EN_GEN3" "0,1"
|
|
bitfld.long 0x14 4. " RX_QEYE_EN_GEN2 ,RX_QEYE_EN_GEN2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 0. " RX_QEYE_EN_GEN1 ,RX_QEYE_EN_GEN1" "0,1"
|
|
line.long 0x18 "CHX_PHY_CTRL9,SATA PHY Control Register"
|
|
hexmask.long.word 0x18 16.--31. 1. " MISC_TEST ,MISC_TEST"
|
|
hexmask.long.byte 0x18 8.--15. 1. " MISC_OUT_SEL ,MISC_OUT_SEL"
|
|
bitfld.long 0x18 2. " DFE_RESET ,DFE_RESET" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x18 1. " DFE_TRAIN_DONE ,DFE_TRAIN_DONE" "0,1"
|
|
bitfld.long 0x18 0. " DFE_TRAIN_EN ,DFE_TRAIN_EN" "0,1"
|
|
line.long 0x1C "CHX_PHY_CTRL10,SATA PHY Control Register"
|
|
hexmask.long.word 0x1C 16.--31. 1. " EOM_CNTL ,EOM_CNTL"
|
|
bitfld.long 0x1C 2. " EOM_EN ,EOM_EN" "0,1"
|
|
rbitfld.long 0x1C 1. " EOM_TRAIN_DONE ,EOM_TRAIN_DONE" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " EOM_TRAIN_EN ,EOM_TRAIN_EN" "0,1"
|
|
line.long 0x20 "CHX_PHY_CTRL11,SATA PHY Control Register"
|
|
hexmask.long.word 0x20 16.--31. 1. " GEN2_RX_EQ ,GEN2_RX_EQ"
|
|
hexmask.long.word 0x20 0.--15. 1. " GEN1_RX_EQ ,GEN1_RX_EQ"
|
|
line.long 0x24 "CHX_PHY_CTRL12,SATA PHY Control Register"
|
|
hexmask.long.word 0x24 0.--15. 1. " GEN3_RX_EQ ,GEN3_RX_EQ"
|
|
line.long 0x28 "CHX_PHY_CTRL13,SATA PHY Control Register"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x28 20.--23. " RX_IQ_CTRL_GEN3 ,RX_IQ_CTRL_GEN3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x28 16.--19. " RX_IQ_CTRL_GEN2 ,RX_IQ_CTRL_GEN2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x28 12.--15. " RX_IQ_CTRL_GEN1 ,RX_IQ_CTRL_GEN1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x28 0.--11. 1. " CDR_TEST ,CDR_TEST"
|
|
line.long 0x2C "CHX_PHY_CTRL14,SATA PHY Control Register"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
group.long 0x700++0x1F
|
|
line.long 0x00 "CHX_PHY_CTRL15,SATA PHY Control Register"
|
|
bitfld.long 0x00 20.--23. " RX_FELS_GEN3 ,RX_FELS_GEN3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " RX_FELS_GEN2 ,RX_FELS_GEN2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " RX_FELS_GEN1 ,RX_FELS_GEN1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " DRV_SLEW_GEN3 ,DRV_SLEW_GEN3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DRV_SLEW_GEN2 ,DRV_SLEW_GEN2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DRV_SLEW_GEN1 ,DRV_SLEW_GEN1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CHX_PHY_CTRL16,SATA PHY Control Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " RX_PI_CTRL_GEN3 ,RX_PI_CTRL_GEN3"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RX_PI_CTRL_GEN2 ,RX_PI_CTRL_GEN2"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RX_PI_CTRL_GEN1 ,RX_PI_CTRL_GEN1"
|
|
line.long 0x08 "CHX_PHY_CTRL17,SATA PHY Control Register"
|
|
line.long 0x0C "CHX_PHY_CTRL18,SATA PHY Control Register"
|
|
line.long 0x10 "CHX_PHY_CTRL19,SATA PHY Control Register"
|
|
line.long 0x14 "CHX_PHY_CTRL20,SATA PHY Control Register"
|
|
line.long 0x18 "CHX_PHY_CTRL21,SATA PHY Control Register"
|
|
line.long 0x1C "CHX_PHY_CTRL22,SATA PHY Control Register"
|
|
endif
|
|
group.long 0x700++0x07
|
|
line.long 0x00 "CHXCFG3,Serial ATA Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CHX_PRBS_ERROR_CNT ,CHX_PRBS_ERROR_CNT"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHX_BIST_CODE ,CHX_BIST_CODE"
|
|
rbitfld.long 0x00 1. " CHX_BIST_STAT ,CHX_BIST_STAT" "NOT_BUSY,BUSY"
|
|
textline " "
|
|
eventfld.long 0x00 0. " CHX_BIST_SEND ,CHX_BIST_SEND" "INIT,NOW"
|
|
line.long 0x04 "CHXCFG4_CHX,CHXCFG4_CHX"
|
|
bitfld.long 0x04 12. " CHX_SW_COMWAKE_PI ,CHX_SW_COMWAKE_PI" "0,1"
|
|
bitfld.long 0x04 8.--11. " CHX_PHY_ALIGN_NUM_CNT ,Number of ALIGN primitive pairs that are inserted by the PHY interface block into the output stream" "1 pair,2 pairs,3 pairs,4 pairs,5 pairs,6 pairs,7 pairs,8 pairs,9 pairs,10 pairs,11 pairs,12 pairs,13 pairs,14 pairs,15 pairs,16 pairs"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CHX_PHY_ALIGN_DWORD_CNT ,Number of DWORDs sent before the required align pairs"
|
|
group.long 0x714++0x03
|
|
line.long 0x00 "PRBS_CHX,Control bits for the IOBIST PRBS generator and checker"
|
|
hexmask.long.word 0x00 16.--31. 1. " ERROR_COUNT ,ERROR_COUNT"
|
|
rbitfld.long 0x00 15. " LOCKED ,LOCKED" "0,1"
|
|
rbitfld.long 0x00 14. " ERROR ,ERROR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " HOT_RESET ,HOT_RESET" "0,1"
|
|
bitfld.long 0x00 10. " PI_LOOPBACK ,PI_LOOPBACK" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. " SEED ,SEED"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX1")
|
|
group.long 0x718++0x03
|
|
line.long 0x00 "CHX_PHY_CTRL23,SATA PHY Control Register"
|
|
bitfld.long 0x00 16. " RX_EOM_DONE ,RX_EOM_DONE" "0,1"
|
|
hexmask.long.word 0x00 0.--15. 1. " RX_EOM_STATUS ,RX_EOM_STATUS"
|
|
endif
|
|
group.long 0x750++0x03
|
|
line.long 0x00 "CHX_LINK0,CHX_LINK0"
|
|
bitfld.long 0x00 2. " IDDQ_ON_OFFLINE ,IDDQ_ON_OFFLINE" "NO,YES"
|
|
bitfld.long 0x00 1. " CONT_DISABLE ,CONT primitive in the SATA TX: Disable" "NO,YES"
|
|
bitfld.long 0x00 0. " SCRAM_DIS ,Data scrambling in the SATA Link layer: Disable" "NO,YES"
|
|
textline " "
|
|
width 27.
|
|
group.long 0x790++0x0B
|
|
line.long 0x00 "CHX_AHCI_PORT_PXTFD_BKDR,Backdoor register for PXTFD of the PSM registers"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ERR ,ERR"
|
|
bitfld.long 0x00 7. " STS_BSY ,STS_BSY" "CLEARED,SET"
|
|
bitfld.long 0x00 6. " STS_DRDY ,STS_DRDY" "CLEARED,SET"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STS_DF ,STS_DF" "CLEARED,SET"
|
|
bitfld.long 0x00 4. " STS_CS ,STS_CS" "CLEARED,SET"
|
|
bitfld.long 0x00 3. " STS_DRQ ,STS_DRQ" "CLEARED,SET"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " STS_2_1 ,STS_2_1" "0,1,2,3"
|
|
bitfld.long 0x00 0. " STS_ERR ,STS_ERR" "CLEARED,SET"
|
|
line.long 0x04 "CHX_AHCI_PORT_PXSIG_BKDR,Backdoor register for PXSIG of the PSM registers"
|
|
hexmask.long.byte 0x04 24.--31. 1. " LBA_HIGH ,LBA_HIGH"
|
|
hexmask.long.byte 0x04 16.--23. 1. " LBA_MID ,LBA_MID"
|
|
hexmask.long.byte 0x04 8.--15. 1. " LBA_LOW ,LBA_LOW"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " SECTOR_CNT ,SECTOR_CNT"
|
|
line.long 0x08 "CHX_AHCI_PORT_PXSSTS_BKDR,Backdoor register for PXSSTS_SPD of the PSM registers"
|
|
bitfld.long 0x08 8.--11. " IPM ,IPM" "NO_DEV,,,,,,SLUMBER,,DEVSLEEP,?..."
|
|
bitfld.long 0x08 4.--7. " SPD ,SPD" "NO_DEV,GEN1,GEN2,GEN3,?..."
|
|
bitfld.long 0x08 0.--3. " DET ,DET" "NO_DEV,?..."
|
|
group.long 0x7F0++0x03
|
|
line.long 0x00 "CHX_GLUE,CHX_GLUE"
|
|
bitfld.long 0x00 0. " ATAPI_BLINK_EN ,LED_ACTIVE signal qualifier" "0,1"
|
|
rgroup.long 0xAC0++0x03
|
|
line.long 0x00 "INTR,Serial ATA Reserved Register"
|
|
bitfld.long 0x00 31. " SEC_INTR ,Secondary Interrupt pending status" "NOT_PENDING,PENDING"
|
|
bitfld.long 0x00 30. " PRI_INTR ,Primary Interrupt pending status" "NOT_PENDING,PENDING"
|
|
group.long 0xC00++0x07
|
|
line.long 0x00 "EMU1,Serial ATA Control Register"
|
|
bitfld.long 0x00 28.--31. " PHY_UART_TIMEOUT ,PHY_UART_TIMEOUT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 26. " PHY_USE_RBC1 ,PHY_USE_RBC1" "NO,YES"
|
|
bitfld.long 0x00 25. " PHY_ABSORB_ALIGN_PRIM ,PHY_ABSORB_ALIGN_PRIM" "NO,YES"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PHY_BYPASS_EN ,PHY_BYPASS_EN" "NO,YES"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PHY_UART_SAMPLE ,PHY_UART_SAMPLE"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PHY_UART_DIV ,PHY_UART_DIV"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PHY_PM_EN ,PHY_PM_EN" "NO,YES"
|
|
bitfld.long 0x00 5. " PHY_TXCLK_EARLY ,PHY_TXCLK_EARLY" "NO,YES"
|
|
bitfld.long 0x00 4. " PHY_DATA_EARLY ,PHY_DATA_EARLY" "NO,YES"
|
|
textline " "
|
|
rbitfld.long 0x00 1.--3. " PHY_SEL ,PHY_SEL" "NOTHING,MARVELL,SI,NVDA_EXT,NVDA_INT,?..."
|
|
bitfld.long 0x00 0. " RESET_ON_COMRESET ,RESET_ON_COMRESET" "NO,YES"
|
|
line.long 0x04 "EMU2,Serial ATA Backdoor Class Code Register"
|
|
bitfld.long 0x04 31. " RETRY_CTL_FIS_SRST ,RETRY_CTL_FIS_SRST" "0,1"
|
|
bitfld.long 0x04 24.--26. " AHCI_DEBUG_PORT_SEL ,AHCI_DEBUG_PORT_SEL" "ZERO,ONE,TWO,THREE,?..."
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
; tree "DMA Control Registers"
|
|
; base ad:0x70006C00
|
|
; %include tegrak1/sataDma.ph
|
|
; tree.end
|
|
tree "AUX Registers"
|
|
base ad:0x70001100
|
|
width 17.
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "MISC_CNTL_1,Misc Control 1 Register"
|
|
bitfld.long 0x00 19. " AUX_RX_IDLE_STATUS_MASK ,AUX Rx idle status input mask" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " AUX_OR_CORE_IDLE_STATUS_SEL ,Interrupt generation Rx idle status source select" "AUX,CORE"
|
|
sif !cpuis("TEGRAX1")
|
|
textline " "
|
|
bitfld.long 0x00 17. " DEVSLP_OVERRIDE ,SATA core DEVSLP output override enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DSP_SUPPORT ,Device sleep support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DESO_SUPPORT ,Capability to enter DEVSLP from state" "Any,Slumber"
|
|
bitfld.long 0x00 14. " SADM_SUPPORT ,SATA core capability to support hardware assertion of the DEVSLP" "Not supported,Supported"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 13. " SDS_SUPPORT ,SATA core device sleep support" "Not supported,Supported"
|
|
bitfld.long 0x00 12. " RX_STAT_IDLE_MASK ,Mask the Rx stat idle input to the SATA core" "Not masked,Masked"
|
|
sif !cpuis("TEGRAX1")
|
|
textline " "
|
|
rbitfld.long 0x00 11. " SATA2IPSM_DEVSLP ,SATA link DEVSLP state" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 9.--10. " SATA2IPSM_ST ,SATA link partial/slumber modes indication" "0,1,2,3"
|
|
bitfld.long 0x00 8. " NVA2SATA_OOB_ON_SCONTROL_SPD_WR ,OOB and through speed negotiation on SCONTROL SPD write" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " NVA2SATA_OOB_ON_POR ,Automatic OOB sequence on coming out of reset" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5.--6. " L0_RX_IDLE_T_SAX ,L0 Rx idle T value from the SATA controller" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " L0_RX_IDLE_T_NPG ,L0 Rx idle T value for the SATA PHY from APB misc" "0,1,2,3"
|
|
bitfld.long 0x00 2. " L0_RX_IDLE_T_MUX ,Select L0 Rx idle T driving source for SATA PHY" "SATA controller,APB misc"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PMU2SATA_ACCLMTR_TRIG ,External accelerometer trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DEVICE_DIS_SATA0 ,Serial ATA interface 0 disable" "No,Yes"
|
|
line.long 0x04 "RX_STAT_INT,Rx Stat Int Register"
|
|
sif cpuis("TEGRAX2")
|
|
bitfld.long 0x04 11. " SATA_AUX_RX_STAT_INT_DISABLE ,SATA AUX Rx stat interrupt disable" "No,Yes"
|
|
rbitfld.long 0x04 10. " SATA_L0_AUX_RX_STAT_IDLE ,SATA PAD L0 AUX Rx idle status status" "Active,Idle"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x08 3. 0x0C 3. " SATA_AUX_RX_STAT_INT_STATUS_SET/CLR ,SATA Rx stat interrupt status from SATA PAD VAUX portion" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("TEGRAX1")
|
|
bitfld.long 0x04 8. " SATA_DEVSLP_INT_DISABLE ,SATA DEVSLP interrupt disable" "No,Yes"
|
|
rbitfld.long 0x04 7. " SATA_DEVSLP ,SATA DEVSLP state interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x04 6. 0x08 2. 0x0C 2. " SATA_DEVSLP_INT_STATUS_SET/CLR ,SATA DEVSLP state interrupt status" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 5. " SATA_DEV_ATTEN_INT_DISABLE ,SATA device attention interrupt disable" "No,Yes"
|
|
rbitfld.long 0x04 4. " SATA_DEVICE_ATTENTION ,SATA device attention status" "Cleared,Asserted"
|
|
setclrfld.long 0x04 3. 0x08 1. 0x0C 1. " SATA_DEV_ATTEN_INT_STATUS_SET/CLR ,SATA device attention interrupt status from GPIO" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif !cpuis("TEGRAX2")
|
|
bitfld.long 0x04 2. " SATA_RX_STAT_INT_DISABLE ,SATA Rx stat interrupt disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SATA_L0_RX_STAT_IDLE ,SATA PAD L0 Rx stat idle status" "Idle,Active"
|
|
endif
|
|
setclrfld.long 0x04 0. 0x08 0. 0x0C 0. " SATA_RX_STAT_INT_STATUS_SET/CLR ,SATA Rx stat interrupt status from the SATA PAD" "No interrupt,Interrupt"
|
|
group.long 0x18++0x1B
|
|
line.long 0x00 "SPARE_CFG0,Spare CFG0 Register"
|
|
bitfld.long 0x00 14. " MDAT_TIMER_AFTER_PG_VALID ,MDAT timer value valid" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--13. " MDAT_TIMER_AFTER_PG ,MDAT timer value to be updated by the SW before power-ungating SATA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. " MDAT_TIMER_BEFORE_PG ,MDAT timer value to be updated by the SW before power-gating SATA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SPARE_CFG1,Spare CFG1 Register"
|
|
line.long 0x08 "PAD_PLL_CTRL,SATA PAD PLL Control Register"
|
|
bitfld.long 0x08 28.--29. " PLL1_REFCLK_NDIV ,Select feedback divider for PLL" "0,1,2,3"
|
|
rbitfld.long 0x08 27. " PLL1_LOCKDET ,PLL1 locked" "Not locked,Locked"
|
|
bitfld.long 0x08 24. " PLL1_MODE ,PLL1 mode" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 20.--21. " PLL0_REFCLK_NDIV ,Select feedback divider for PLL" "0,1,2,3"
|
|
rbitfld.long 0x08 19. " PLL0_LOCKDET ,PLL0 locked" "Not locked,Locked"
|
|
bitfld.long 0x08 16. " PLL0_MODE ,PLL0 mode" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " REFCLK_SEL ,Reference clock select" "Internal CML,Internal CMOS,External,External,?..."
|
|
bitfld.long 0x08 11. " REFCLK_TERM100 ,REFCLK TERM100" "0,1"
|
|
bitfld.long 0x08 9. " PLL_CKBUFPD_OVRD ,PLL CKBUFPD override" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x08 8. " PLL_CKBUFPD_M ,PLL CKBUFPD M" "0,1"
|
|
bitfld.long 0x08 7. " PLL_CKBUFPD_BL ,PLL CKBUFPD BL" "0,1"
|
|
bitfld.long 0x08 6. " PLL_CKBUFPD_BR ,PLL CKBUFPD BR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 5. " PLL_CKBUFPD_TL ,PLL CKBUFPD TL" "0,1"
|
|
bitfld.long 0x08 4. " PLL_CKBUFPD_TR ,PLL CKBUFPD TR" "0,1"
|
|
bitfld.long 0x08 2. " PLL_EMULATION_RSTN ,Digital reset for clock divider during emulation mode" "Reset,No reset"
|
|
line.long 0x0C "PAD_PLL_CTRL_1,PAD PLL Control 1 Register"
|
|
bitfld.long 0x0C 20.--23. " PLL1_CP_CNTL ,Charge-pump current control for PLL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 16.--19. " PLL0_CP_CNTL ,Charge-pump current control for PLL0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 15. " PLL_BYPASS_EN ,Bypass PLL serial output clocks with input reference clock" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " PLL_EMULATION_ON ,Enable clock bypass for emulation mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " TCLKOUT_EN ,Enable test clock output PADs TSTCLKP/N" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8.--11. " TCLKOUT_SEL ,Select internal clock source to bring out through the TSTCLKP/N PADs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " XDIGCLK4P5_EN ,Enable XDIGCLK4P5 clock output to core" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " REFCLKBUF_EN ,Enable REFCLKBUF clock output to core" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " TXCLKREF_EN ,Enable TXCLKREF clock to core" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " TXCLKREF_SEL ,Select the post divider for TXCLKREF clock" "0,1"
|
|
bitfld.long 0x0C 3. " XDIGCLK_EN ,Enable XDIGCLK output clock" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--2. " XDIGCLK_SEL ,Select the output frequency of XDIGCLK" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "PAD_PLL_CTRL_2,PAD PLL Control 2 Register"
|
|
bitfld.long 0x10 28.--31. " PLL_TEMP_CNTL ,PLL TEMP control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 18.--23. " PLL_BW_CNTL ,PLL BW control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x10 16.--17. " PLL_BGAP_CNTL ,PLL BGAP control" "0,1,2,3"
|
|
textline " "
|
|
rbitfld.long 0x10 15. " RCAL_DONE ,Status signal to indicate calibration status" "Not done,Done"
|
|
bitfld.long 0x10 14. " RCAL_RESET ,Reset the resistor calibration logic" "No reset,Reset"
|
|
rbitfld.long 0x10 8.--12. " RCAL_VAL ,Setting of current active resistor calibration code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x10 7. " RCAL_BYPASS ,Bypass resistor calibration logic" "Not bypassed,Bypassed"
|
|
bitfld.long 0x10 0.--4. " RCAL_CODE ,Sets resistor calibration code when logic is bypassed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "PAD_PLL_CTRL_3,PAD PLL Control 3 Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " PLL_MISC_CNTL ,PLL MISC control"
|
|
line.long 0x18 "PAD_L0_AUX_CTRL,PAD L0 AUX Control Register"
|
|
rbitfld.long 0x18 9. " AUX_RX_IDLE_STATUS ,AUX Rx idle status" "0,1"
|
|
rbitfld.long 0x18 8. " AUX_TX_RDET_STATUS ,AUX Tx RDET status" "0,1"
|
|
bitfld.long 0x18 5. " AUX_HOLD_EN ,AUX hold enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " AUX_RX_IDLE_MODE ,AUX Rx idle mode" "0,1"
|
|
bitfld.long 0x18 3. " AUX_RX_IDLE_EN ,AUX Rx idle enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " AUX_RX_TERM_EN ,AUX Rx term enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " AUX_TX_RDET_EN ,AUX Tx RDET enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " AUX_TX_TERM_EN ,AUX Tx term enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "PCI-Express Controller (PCI-E)"
|
|
tree "PCIe Controller 0"
|
|
base ad:0x01000000
|
|
width 11.
|
|
tree "PCI Compatible Configuration Registers"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DEV_ID,Device ID And Vendor ID Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DEVICE_ID ,Identify the particular device"
|
|
hexmask.long.word 0x00 0.--15. 1. " VENDOR_ID ,Identify manufacturer of the device"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DEV_CTRL,Command And Status Register"
|
|
eventfld.long 0x00 31. " DETECTED_PERR ,Primary side device receives a poisoned TLP" "Not active,Active"
|
|
eventfld.long 0x00 30. " SIGNALED_SERR ,ERR_FATAL or ERR_NONFATAL message from primary side device" "Not active,Active"
|
|
eventfld.long 0x00 29. " RECEIVED_MASTER ,Primary side requestor receives a completion with unsupported request completion status" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.long 0x00 28. " RECEIVED_TARGET ,Primary side requestor receives a completion with completer abort completion status" "Not aborted,Aborted"
|
|
eventfld.long 0x00 27. " SIGNALED_TARGET ,Primary side device completes a request using completer abort completion status" "Not aborted,Aborted"
|
|
eventfld.long 0x00 24. " MASTER_DATA_PERR ,Master data parity error bit" "Not active,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 20. " CAPLIST ,Device configuration space includes a capabilities list" "Not present,Present"
|
|
rbitfld.long 0x00 19. " INTR_STATUS ,INTx interrupt message is pending internally to the device" "Not active,Active"
|
|
bitfld.long 0x00 10. " INTR_DISABLE ,Ability of the device to generate INTx interrupt messages" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SERR ,SERR enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PERR ,Parity Error Response bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BUS_MASTER ,Ability of the root complex to issue memory and I/O read/write requests" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MEMORY_SPACE ,Respond to memory space accesses on the primary interface" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IO_SPACE ,Respond to I/O space accesses on the primary interface" "Disabled,Enabled"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "REV_CC,Revision ID And Class Code Registers"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " CLASS_CODE ,Generic function of the device"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REVISION_ID ,Device specific revision identifier"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MISC_1,MISC 1 Register"
|
|
rbitfld.long 0x00 23. " HEADER_TYPE1 ,Identifies a multi-function device" "Single function,Multi function"
|
|
hexmask.long.byte 0x00 16.--22. 1. " HEADER_TYPE0 ,Specifies the layout of bytes 10h through 3Fh"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CACHE_LINE_SIZE ,Cache line size"
|
|
group.long 0x18++0x1B
|
|
line.long 0x00 "BN_LT,Bus Number And Latency Timer Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SUB_BUS_NUMBER ,Subordinate bus number"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SEC_BUS_NUMBER ,The secondary bus number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_BUS_NUMBER ,The primary bus number"
|
|
line.long 0x04 "IO_BL_SS,I/O Base/Limit And Secondary Status Register"
|
|
eventfld.long 0x04 31. " DETECTED_PERR ,Secondary side device receives a poisoned TLP" "Not active,Active"
|
|
eventfld.long 0x04 30. " RECEIVED_SERR ,Secondary side device receives an ERR_FATAL or ERR_NONFATAL message" "Not active,Active"
|
|
eventfld.long 0x04 29. " RECEIVED_MASTER ,Secondary side device receives a completion with unsupported request completion status" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.long 0x04 28. " RECEIVED_TARGET ,Secondary side device receives a completion with completer abort completion status" "Not aborted,Aborted"
|
|
eventfld.long 0x04 27. " SIGNALED_TARGET ,Secondary side device completes a request using completer abort completion status" "Not aborted,Aborted"
|
|
eventfld.long 0x04 24. " MASTER_DATA_PERR ,Master data parity error bit" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " IO_LIMIT ,Corresponds to address bits AD[15:12] of the I/O limit" "0,256,512,,,,,,,,,,,,,64k"
|
|
rbitfld.long 0x04 8.--11. " IO_LIMIT_SUPPORT ,Identifies the I/O addressing support" "16,32,?..."
|
|
bitfld.long 0x04 4.--7. " IO_BASE ,Corresponds to address bits AD[15:12] of the I/O base address" "0,256,512,,,,,,,,,,,,,64k"
|
|
textline " "
|
|
rbitfld.long 0x04 0.--3. " IO_BASE_SUPPORT ,Identifies the I/O addressing support" "16,32,?..."
|
|
line.long 0x08 "MEM_BL,Memory Base And Memory Limit Register"
|
|
hexmask.long.word 0x08 20.--31. 0x10 " MEM_LIMIT ,Corresponds to address bits AD[31:20] of the memory-mapped I/O limit"
|
|
hexmask.long.word 0x08 4.--15. 0x10 " MEM_BASE ,Corresponds to address bits AD[31:20] of the memory-mapped I/O base address"
|
|
line.long 0x0C "PRE_BL,Prefetchable Memory Base/Limit Register"
|
|
hexmask.long.word 0x0C 20.--31. 0x10 " PREFETCH_MEM_LIMIT ,Corresponds to address bits AD[31:20] of the prefetchable memory limit"
|
|
rbitfld.long 0x0C 16.--19. " L64BIT ,Identifies the prefetchable memory addressing support" "Not supported,Supported,?..."
|
|
hexmask.long.word 0x0C 4.--15. 0x10 " PREFETCH_MEM_BASE ,corresponds to address bits AD[31:20] of the prefetchable memory base address"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " B64BIT ,Identifies the prefetchable memory addressing support" "Not supported,Supported,?..."
|
|
line.long 0x10 "PRE_BU32,Prefetchable Memory Base Upper 32 Bits Register"
|
|
line.long 0x14 "PRE_LU32,Prefetchable Memory Limit Upper 32 Bits Register"
|
|
line.long 0x18 "IO_BL_U16,I/O Base/Limit Upper 16 Bits Register"
|
|
hexmask.long.word 0x18 16.--31. 1. " LIMIT_UPPER_BITS ,specifies the upper 16 bits,corresponding to AD[31:16],of the 32-bit I/O limit"
|
|
hexmask.long.word 0x18 0.--15. 1. " BASE_UPPER_BITS ,specifies the upper 16 bits,corresponding to AD[31:16],of the 32-bit I/O base address"
|
|
rgroup.long 0x34++0x07
|
|
line.long 0x00 "CAP_PTR,Capabilities Pointer"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " CAP_PTR_CAP_PTR ,Offset into configuration space where the capabilities list begins"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "INTR_BCR,Interrupt Bridge Control Registers"
|
|
bitfld.long 0x00 22. " SB_RESET ,Triggers a hot reset on the corresponding PCI express port" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " VGA_16BITIO ,Full 16-bit decode of IO address range for VGA" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " VGA_ADDRESS ,P2P bridge will claim all of the legacy VGA addresses" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " ISA_ADDRESS ,Modifies the response by the bridge to ISA I/O addresses" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SERR_FORWARD ,Forwarding of ERR_COR/ERR_NONFATAL and ERR_FATAL from secondary to primary" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PERR_RESP ,Response to poisoned TLPs" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTR_PIN ,Contains the interrupt pin the device (or device function) uses"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTR_LINE ,Contains the interrupt routing information"
|
|
tree.end
|
|
tree "PCI Subsystem ID And Subsystem Vendor ID Capability Registers"
|
|
width 6.
|
|
rgroup.long 0x40++0x07
|
|
line.long 0x00 "SS_0,Subsystem ID/Vendor ID Capability Register 0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NEXT_PTR ,Points to the next capabilities list item"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAP_ID ,Detect the presence of the SSID/SSVID registers in a PCI-to-PCI bridge"
|
|
line.long 0x04 "SS_1,Subsystem ID/Vendor ID Capability Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " SSID ,Identifies the particular add-in card or subsystem"
|
|
hexmask.long.word 0x04 0.--15. 1. " SSVID ,Identifies the manufacturer of the add-in card or subsystem"
|
|
tree.end
|
|
tree "PCI Power Management Capability Structure Registers"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "PM_0,Power Management Register 0"
|
|
bitfld.long 0x00 31. " D3_COLD_SUPPORT ,Power states in which the function may assert PME?..." "Not supported,Supported"
|
|
bitfld.long 0x00 30. " D3_HOT_SUPPORT ,Power states in which the function may assert PME?..." "Not supported,Supported"
|
|
bitfld.long 0x00 29. " D2_SUPPORT ,Power states in which the function may assert PME?..." "Not supported,Supported"
|
|
bitfld.long 0x00 28. " D1_SUPPORT ,Power states in which the function may assert PME?..." "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 27. " D0_SUPPORT ,Power states in which the function may assert PME?..." "Not supported,Supported"
|
|
bitfld.long 0x00 26. " D2_SUPPORT ,D2 power management state support" "Not supported,Supported"
|
|
bitfld.long 0x00 25. " D1_SUPPORT ,D1 power management state support" "Not supported,Supported"
|
|
bitfld.long 0x00 22.--24. " AUX_CURRENT ,3.3Vaux auxiliary current requirements for the PCI function" "0,55 mA,100 mA,160 mA,220 mA,270 mA,320 mA,375 mA"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DEV_SPEC_INIT ,Device specific initialization bit" "Not needed,Needed"
|
|
bitfld.long 0x00 16.--18. " PCIPM_REV ,Revision of the PCI power management interface specification" ",,Rev 1.1,Rev 1.2,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " NEXT_PTR ,Points to the next capabilities list item"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAP_ID ,Detect the presence of the power management capability registers in a PCI to PCI bridge"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PM_1,Power Management Register 1"
|
|
eventfld.long 0x00 15. " PME_STATUS ,Assert the PME# signal independent of the state of the PME_En bit" "Not active,Active"
|
|
bitfld.long 0x00 8. " PME ,Assert PME?..." "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " PWR_STATE ,Determine the current power state of a function and to set the function into a new power state" "D0,D1,D2,D3hot"
|
|
tree.end
|
|
tree "PCI MSI Capability Structure Registers"
|
|
width 16.
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "MSI_CTRL,MSI Control Registers"
|
|
rbitfld.long 0x00 23. " 64BIT_CAP ,Capability of generating a 64-bit message address" "Not capable,Capable"
|
|
bitfld.long 0x00 20.--22. " MULT_EN ,Number of allocated messages" "0,2,4,8,?..."
|
|
rbitfld.long 0x00 17.--19. " MULT_CAP ,Number of requested messages" "0,2,?..."
|
|
bitfld.long 0x00 16. " CTRL_MSI ,Permission to use message signaled interrupt to request service" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NEXT_PTR ,Points to the next item in the capabilities list"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAP_ID ,Detect the presence of the Message Signaled Interrupt Capability registers in a PCI-to-PCI bridge"
|
|
line.long 0x04 "MSI_LOW_ADDR,MSI Message Lower Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " DWORD ,Bits 31:2 of the address"
|
|
line.long 0x08 "MSI_UPPER_ADDR,MSI Message Upper Address Register"
|
|
line.long 0x0C "MSI_DATA,MSI Message Data Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " DATA ,MSI message data"
|
|
tree.end
|
|
sif (cpuis("TEGRAX2"))
|
|
tree "PCI MSI Map Register"
|
|
group.long 0x60++0x0B
|
|
line.long 0x00 "MSI_MAP_0,MSI MAP Capability Register"
|
|
rbitfld.long 0x00 27.--31. " CAP_TYPE ,Capability type for MSI Mapping Capability block" ",,,,,,,,,,,,,,,,,,,,,CAP_TYPE_MSI,?..."
|
|
bitfld.long 0x00 16. " XLATE_ENABLE ,Global enable for MSI translation" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " CAP_PTR ,Pointer to the next capability in the list"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAP_ID ,Capability ID for HyperTransport technology devices"
|
|
line.long 0x04 "MSI_MAP_1,MSI MAP Lower Address Register"
|
|
hexmask.long.word 0x04 20.--31. 0x10 " ADDRESS_LOWER ,Lower [31:0] bit address field"
|
|
line.long 0x08 "MSI_MAP_2,MSI MAP Upper Address Register"
|
|
tree.end
|
|
endif
|
|
tree "PCI Express Capability Structure Registers"
|
|
width 26.
|
|
rgroup.long 0x80++0x07
|
|
line.long 0x00 "PCI_EXPRESS_CAPABILITY,PCI Express Capability List Register"
|
|
bitfld.long 0x00 25.--29. " INTERRUPT_MESSAGE_NUMBER ,PCI express capability interrupt message number " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SLOT_IMPLEMENTED ,PCI express capability slot implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " DEVICE_PORT_TYPE ,PCI express capability device port type" "PCI express endpoint device,Legacy PCI express endpoint device,,,Root port of PCI express root complex,Upstream port of PCI express switch,Downstream port of PCI express switch,PCI express to PCI/PCI-X bridge,PCI/PCI-X to PCI express bridge,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " VERSION ,PCI express capability version number" ",Version 1,Version 2,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " LIST_NEXT_CAPABILITY_PTR ,The offset to the next PCI capability structure"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " LIST_CAPABILITY_ID ,Indicates PCI express capability structure"
|
|
line.long 0x04 "DEVICE_CAPABILITY,Device Capabilities Register"
|
|
bitfld.long 0x04 26.--27. " CAPTURED_SLOT_POWER_LIMIT_SCALE ,Scale used for the slot power limit value" "1.0x,0.1x,0.01x,0.001x"
|
|
textline " "
|
|
hexmask.long.byte 0x04 18.--25. 1. " CAPTURED_SLOT_POWER_LIMIT_VALUE ,Specifies the upper limit on power supplied by slot"
|
|
textline " "
|
|
bitfld.long 0x04 15. " ROLE_BASED_ERR_REPORTING ,Device implements the functionality originally defined in the error reporting ECN" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x04 14. " POWER_INDICATOR_PRESENT ,Power indicator" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ATTENTION_INDICATOR_PRESENT ,Attention indicator" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x04 12. " ATTENTION_BUTTON_PRESENT ,Attention button" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x04 9.--11. " ENDPOINT_L1_ACCEPTABLE_LATENCY ,Acceptable latency due to the transition from L1 state to the L0 state" "<1 us,1 us - 2 us,2 us -4 us,4 us - 8 us,8 us - 16 us,16 us - 32 us,32 us-64 us,> 64 us"
|
|
textline " "
|
|
bitfld.long 0x04 6.--8. " ENDPOINT_L0S_ACCEPTABLE_LATENCY ,Acceptable total latency due to the transition from L1 state to the L0 state" "< 64 ns,64 ns - 128 ns,128 ns - 256 ns,256 ns - 512 ns,512 ns - 1. us,1 us - 2 us,2 us-4us,> 4 us"
|
|
textline " "
|
|
bitfld.long 0x04 5. " EXTENDED_TAG_FIELD_SIZE ,Maximum supported size of the tag field" "5-bit tag field,8-bit tag field"
|
|
textline " "
|
|
bitfld.long 0x04 3.--4. " PHANTOM_FUNCTIONS_SUPPORTED ,Phantom functions support" "No bits used,First MSB used,First two MSB used,Three bits"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " MAX_PAYLOAD_SIZE ,Maximum payload size" "128B,256B,512B,1024B,2048B,4096B,?..."
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "DEVICE_CONTROL_STATUS,Device Control/Status Registers"
|
|
rbitfld.long 0x00 21. " TRANSACTIONS_PENDING ,Transactions pending" "Completed,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 20. " AUX_POWER_DETECTED ,AUX power detected" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " UNSUPP_REQUEST_DETECTED ,Unsupported request" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 18. " FATAL_ERROR_DETECTED ,Fatal error" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 17. " NON_FATAL_ERROR_DETECTED ,Non-fatal error" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CORR_ERROR_DETECTED ,Correctable errors" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " MAX_READ_REQUEST_SIZE ,Maximum read request size" "128B,256B,512B,1024B,2048B,4096B,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENABLE_NO_SNOOP ,No snoop bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " AUXILLARY_POWER_PM_ENABLE ,AUX power PM enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " PHANTOM_FUNCTIONS_ENABLE ,Phantom functions" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EXTENDED_TAG_FIELD_ENABLE ,8-bit tag field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " MAX_PAYLOAD_SIZE ,Maximum TLP payload size" "128B,256B,512B,1024B,2048B,4096B,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENABLE_RELAXED_ORDERING ,Relaxed ordering bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " UNSUPP_REQ_REPORTING_ENABLE ,Reporting of unsupported requests" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FATAL_ERROR_REPORTING_ENABLE ,Reporting of fatal errors" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NON_FATAL_ERROR_REPORTING_ENABLE ,Reporting of non-fatal errors" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CORR_ERROR_REPORTING_ENABLE ,Reporting of correctable errors" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "LINK_CAPABILITIES,Link Capabilities Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PORT_NUMBER ,PCI express port number"
|
|
textline " "
|
|
bitfld.long 0x00 21. " BW_NOTIFY ,Bandwidth notify" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " LINKACTV_REPORTING ,Link active reporting" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SURPRISE_DOWN_ERPT_CAP ,Detecting and reporting a surprise down error condition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CLOCK_PM ,Component tolerates the removal of any reference clock" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " L1_EXIT_LATENCY ,L1 exit latency" "< 1 us,1 us - 2 us,2 us - 4 us,4 us - 8 us,8 us - 16 us,16 us - 32 us,32 us - 64 us,> 64 us"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " L0S_EXIT_LATENCY ,L0s exit latency" "< 64 ns,64 ns - 128 ns,128 ns - 256 ns,256 ns - 512 ns,512 ns - 1 us,1 us - 2 us,2 us - 4us,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " ACTIVE_STATE_LINK_PM_SUPPORT ,Level of active state power management supported" ",L0s Entry,,L0s and L1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--9. " MAX_LINK_WIDTH ,Maximum width" ",x1,x2,,x4,,,,x8,,,,x12,,,,x16,,,,,,,,,,,,,,,,x32,?..."
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 0.--3. " MAX_LINK_SPEED ,Maximum Link speed" ",2.5 Gb/s Link,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " MAX_LINK_SPEED ,Maximum Link speed" ",2.5 Gb/s Link,5.0 Gb/s Link,?..."
|
|
endif
|
|
textline " "
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "LINK_CONTROL_STATUS,Link Control/Status Register"
|
|
eventfld.long 0x00 31. " AUTO_BANDWIDTH ,Auto bandwidth" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 30. " BW_MANAGEMENT ,Bandwidth management" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 29. " DL_LINK_ACTIVE ,Data link control and management state machine" "Not active,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 28. " SLOT_CLOCK_CONFIG ,Component uses platform reference clock" "Platform clock,Independent"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " LINK_TRAINING ,Link training" "Completed,In progress"
|
|
textline " "
|
|
rbitfld.long 0x00 20.--25. " NEG_LINK_WIDTH ,Negotiated width" ",x1,x2,,x4,,,,x8,,,,x12,,,,x16,,,,,,,,,,,,,,,,x32,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16.--19. " LINK_SPEED ,Negotiated Link Speed" ",2.5 Gb/s,5.0 Gb/s,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " AUTO_BANDWIDTH_INT_EN ,Auto bandwidth interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BW_MANAGEMENT_INT_EN ,Bandwidth management interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HW_AUTO_WIDTH_DISABLE ,Hardware auto width disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " CLOCK_PM ,Clock PM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EXTENDED_SYNCH ,Forces extended transmission" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COMMON_CLOCK_CONFIGURATION ,Common clock configuration" "Common reference clock,Asynchrous reference clock"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " RETRAIN_LINK ,Link retraining" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LINK_DISABLE ,Disabling the Link" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " READ_COMPLETION_BOUNDARY ,RCB support capabilities" "64 byte,128 byte"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ACTIVE_STATE_LINK_PM_CONTROL ,Level of active state PM supported" ",L0s Entry,,L0s and L1"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "SLOT_CAPABILITIES,Slot Capabilities Register"
|
|
hexmask.long.word 0x00 19.--31. 0x08 " PHYSICAL_SLOT_NUMBER ,Physical slot number attached to this port"
|
|
textline " "
|
|
bitfld.long 0x00 18. " NO_CMD_COMPLETED_SUPPORT ,Notification when an issued command is completed by the hot plug controller" "Supported,Not supported"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ELECTROMECHANICAL_INTERLOCK_PRESENT ,Electro mechanical interlock mechanism" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 15.--16. " SLOT_POWER_LIMIT_SCALE ,Scale used for the slot power limit value" "1.0x,0.1x,0.01x,0.001x"
|
|
textline " "
|
|
hexmask.long.byte 0x00 7.--14. 1. " SLOT_POWER_LIMIT_VALUE ,Upper limit on power supplied by slot"
|
|
textline " "
|
|
bitfld.long 0x00 6. " HOT_PLUG_CAPABLE ,Supporting Hot-plug operations" "Not capable,Capable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HOT_PLUG_SURPRISE ,Hot-plug surprise" "Not capable,Capable"
|
|
textline " "
|
|
bitfld.long 0x00 4. " POWER_INDICATOR_PRESENT ,Power indicator" "Not Implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ATTENTION_INDICATOR_PRESENT ,Attention indicator" "Not Implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MRL_SENSOR_PRESENT ,MRL sensor" "Not Implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 1. " POWER_CONTROLLER_PRESENT ,Power controller" "Not Implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ATTENTION_BUTTON_PRESENT ,Attention button" "Not Implemented,Implemented"
|
|
group.long 0x98++0x0B
|
|
line.long 0x00 "SLOT_CONTROL_STATUS,Slot Control/Status Register"
|
|
eventfld.long 0x00 24. " DL_LAYER_STATE_CHANGED ,Notification when Data Link Layer Active field is changed" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 23. " ELECTROMECHANICAL_INTERLOCK_STATE ,Electromechanical interlock" "Disengaged,Engaged"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " PRESENCE_DETECT_STATE ,Presence of a card in the slot" "Slot empty,Card present"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MRL_SENSOR_STATE ,MRL sensor status" "MRL Closed,MRL Open"
|
|
textline " "
|
|
eventfld.long 0x00 20. " COMMAND_COMPLETED ,Hot-plug controller completed an issued command" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 19. " PRESENCE_DETECT_CHANGED ,Presence Detect change" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 18. " MRL_SENSOR_CHANGED ,MRL Sensor state change" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 17. " POWER_FAULT_DETECTED ,Power fault" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ATTN_BUTTON_PRESSED ,Attention button" "Not pressed,Pressed"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DL_LAYER_STATE_CHANGED_ENABLE ,Data Link Layer Link Active field" "Not changed,Changed"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ELECTROMECHANICAL_INTERLOCK_CONTROL ,Electromechanical interlock mechanism" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 10. " POWER_CONTROLLER_CONTROL ,Power state of the slot" "Power on,Power off"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " POWER_INDICATOR_CONTROL ,Current state of the Power Indicator" ",On,Blink,Off"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " ATTN_INDICATOR_CONTROL ,Current state of the Attention Indicator" ",On,Blink,Off"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HOT_PLUG_INTERRUPT_ENABLE ,Generation of hot plug interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " COMMAND_COMPLETED_INTERRUPT_ENABLE ,Generation of hot plug interrupt when a command is completed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PRESENCE_DETECT_CHANGED_ENABLE ,Presence detect changed event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " STATUS_MRL_SENSOR_CHANGED_ENABLE ,MRL sensor changed event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " POWER_FAULT_DETECTED_ENABLE ,Power fault event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ATTN_BUTTON_PRESSED_ENABLE ,Attention button pressed event interrupt" "Disabled,Enabled"
|
|
line.long 0x04 "RCR,Root Control Register"
|
|
bitfld.long 0x04 3. " PME_INT ,PME interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SERR_FAT ,Generating system error if a fatal error is reported" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SERR_NONFAT ,Generating system error if a non-fatal error is reported" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SERR_COR ,System error if a correctable error is reported" "Disabled,Enabled"
|
|
line.long 0x08 "RSR,Root Status Register"
|
|
rbitfld.long 0x08 17. " PMEPEND ,Another PME is pending when the PMESTAT bit is set" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 16. " PMESTAT ,PME was asserted by the requester ID" "Not active,Active"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--15. 1. " REQID ,PCI requester ID of the last PME requester"
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "DEVICE_CAPABILITIES_2,Root Capabilities Register 2"
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 11. " LTR_MECH_SUP ,LTR Capability support" "Unsupported,Supported"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " CPL_TO_DIS_SUP ,Support disabling the completion timeout mechanism" "Unsupported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPL_TO_RANGES_SUP ,Completion timeout ranges supported by the root port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "DEVICE_CONTROL_STATUS_2,Device Control/Status Register 2"
|
|
bitfld.long 0x00 4. " CPL_TO_DISABLE ,Disables completion timeout" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPL_TO_VALUE ,Completion timeout ranges supported by the root port" "Default,Range A LO,Range A HI,,,Range B LO,Range B HI,?..."
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "LINK_CONTROL_STATUS_2,Link Control Status Register"
|
|
rbitfld.long 0x00 16. " CURRENT_DEEMPHASIS_LEVEL ,Current deemphasis level" "6,3.5"
|
|
textline " "
|
|
bitfld.long 0x00 12. " COMPLIANCE_DEEMPHASIS ,Compliance deemphasis" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMPLIANCE_SOS ,Compliance SOS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ENTER_MODIFIED_COMPLIANCE ,Transmission of the modified compliance pattern" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7.--9. " TRANSMIT_MARGIN ,Value of the non-deemphasized voltage level (Full-swing/Half swing)" "800-1200mV/400-600mV,600-800mV/300-400mV,400-600mV/200-300mV,200-400mV/100-200mV,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 6. " SELECTABLE_DEEMPHASIS ,Level of de-emphasis" "-6dB,-3.5dB"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " HW_AUTO_SPEED_DISABLE ,Link speed change disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENTER_COMPLIANCE ,Forces link to enter compliance mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TARGET_LINK_SPEED ,Upper limit on the link operational speed" ",2.5Gb/s,5Gb/s,?..."
|
|
tree.end
|
|
tree "Error Reporting Capability Registers"
|
|
width 20.
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "ERPTCAP,Advanced Error Reporting Enhanced Capability Header Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " NEXT_PTR ,Next PTR"
|
|
bitfld.long 0x00 16.--19. " VERSION ,Version" "Version 0,Version 1,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " ID ,ID"
|
|
else
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "ERPTCAP,Advanced Error Reporting Enhanced Capability Header Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " ID ,ID"
|
|
bitfld.long 0x00 16.--19. " VERSION ,Version" "Version 0,Version 1,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " NEXT_PTR ,Next PTR"
|
|
endif
|
|
group.long 0x104++0x0B
|
|
line.long 0x00 "ERPTCAP_UCERR,Uncorrectable Error Status Register"
|
|
eventfld.long 0x00 20. " UNSUP_REQ_ERR ,Unsupported request error status" "No error,Error"
|
|
eventfld.long 0x00 19. " ECRC_ERR ,ECRC error status" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 18. " MF_TLP ,Malformed TLP status" "False,True"
|
|
eventfld.long 0x00 17. " RCV_OVFL ,Receiver overflow status" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 16. " UNEXP_COMP ,Unexpected completion status" "False,True"
|
|
eventfld.long 0x00 15. " COMP_ABORT ,Completion abort status" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.long 0x00 14. " COMP_TO ,Completion timeout status" "No timeout,Timeout"
|
|
eventfld.long 0x00 13. " FC_PROTO_ERR ,Flow control protocol error status" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 12. " POS_TLP ,Poisoned TLP status" "False,True"
|
|
eventfld.long 0x00 4. " DLINK_PROTO_ERR ,Data link protocol error status" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " TRAINING_ERR ,Training error status" "No error,Error"
|
|
line.long 0x04 "ERPTCAP_UCERR_MK,Uncorrectable Error Mask Register"
|
|
bitfld.long 0x04 20. " UNSUP_REQ_ERR ,Unsupported request error mask" "Not masked,Masked"
|
|
bitfld.long 0x04 19. " ECRC_ERR ,ECRC error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " MF_TLP ,Malformed TLP mask" "Not masked,Masked"
|
|
bitfld.long 0x04 17. " RCV_OVFL ,Receiver overflow mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " UNEXP_COMP ,Unexpected completion mask" "Not masked,Masked"
|
|
bitfld.long 0x04 15. " COMP_ABORT ,Completion abort mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " COMP_TO ,Completion timeout mask" "Not masked,Masked"
|
|
bitfld.long 0x04 13. " PROTO_ERR ,Flow control protocol error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " POS_TLP ,Poisoned TLP mask" "Not masked,Masked"
|
|
bitfld.long 0x04 4. " DLINK_PROTO_ERR ,Data link protocol error mask" "Not masked,Masked"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " TRAINING_ERR ,Training error mask" "Not masked,Masked"
|
|
line.long 0x08 "ERPTCAP_UCERR_SEVR,Correctable Error Severity Register"
|
|
bitfld.long 0x08 20. " UNSUP_REQ_ERR ,Unsupported request error" "Non-fatal,Fatal"
|
|
bitfld.long 0x08 19. " ECRC_ERR ,ECRC error" "Non-fatal,Fatal"
|
|
textline " "
|
|
bitfld.long 0x08 18. " MF_TLP ,Malformed TLP" "Non-fatal,Fatal"
|
|
bitfld.long 0x08 17. " RCV_OVFL ,Receiver overflow" "Non-fatal,Fatal"
|
|
textline " "
|
|
bitfld.long 0x08 16. " UNEXP_COMP ,Unexpected completion" "Non-fatal,Fatal"
|
|
bitfld.long 0x08 15. " COMP_ABORT ,Completion abort" "Non-fatal,Fatal"
|
|
textline " "
|
|
bitfld.long 0x08 14. " COMP_TO ,Completion timeout" "Non-fatal,Fatal"
|
|
bitfld.long 0x08 13. " PROTO_ERR ,Flow control protocol error" "Non-fatal,Fatal"
|
|
textline " "
|
|
bitfld.long 0x08 12. " POS_TLP ,Poisoned TLP" "Non-fatal,Fatal"
|
|
bitfld.long 0x08 4. " DLINK_PROTO_ERR ,Data link protocol error" "Non-fatal,Fatal"
|
|
textline " "
|
|
rbitfld.long 0x08 0. " TRAINING_ERR ,Training error" "Non-fatal,Fatal"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "ERPTCAP_CERR,Correctable Error Status Register"
|
|
eventfld.long 0x00 13. " ADVISORY_NF ,ADVISORY NF status" "Not masked,Masked"
|
|
eventfld.long 0x00 12. " RPLY_TO ,Replay timer timeout status" "Not masked,Masked"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RPLY_RLOV ,Replay NUM rollover status" "Not masked,Masked"
|
|
eventfld.long 0x00 7. " BAD_DLLP ,Bad DLLP status" "Not masked,Masked"
|
|
textline " "
|
|
eventfld.long 0x00 6. " BAD_TLP ,Bad TLP status" "Not masked,Masked"
|
|
eventfld.long 0x00 0. " RCV_ERR ,Receiver error status" "Not masked,Masked"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "ERPTCAP_CERR_MK,Correctable Error Mask Register"
|
|
bitfld.long 0x00 13. " ADVISORY_NF ,ADVISORY NF mask" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " RPLY_TO ,Replay timer timeout mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPLY_RLOV ,Replay NUM rollover mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " BAD_DLLP ,Bad DLLP mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BAD_TLP ,Bad TLP mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " RCV_ERR ,Receiver error mask" "Not masked,Masked"
|
|
textline " "
|
|
width 26.
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "ERPTCAP_ADV_ERR_CAP_CNTL,Advanced Error Capabilities And Control Register"
|
|
bitfld.long 0x00 8. " ECRC_CHK_EN ,ECRC CHK EN" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " ECRC_CHK_CAP ,ECRC CHK CAP" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ECRC_GEN_EN ,ECRC GEN EN" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " ECRC_GEN_CAP ,ECRC GEN CAP" "False,True"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--4. " ERR_PTR ,ERR PTR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x11C++0xF
|
|
line.long 0x00 "ERPTCAP_HDR_LOG_DW0,Header Log Dword 0 Register"
|
|
line.long 0x04 "ERPTCAP_HDR_LOG_DW1,Header Log Dword 1 Register"
|
|
line.long 0x08 "ERPTCAP_HDR_LOG_DW2,Header Log Dword 2 Register"
|
|
line.long 0x0C "ERPTCAP_HDR_LOG_DW3,Header Log Dword 3 Register"
|
|
textline " "
|
|
width 20.
|
|
group.long 0x12C++0x0B
|
|
line.long 0x00 "ERPTCAP_ERR_CMD,Root Error Command Register"
|
|
bitfld.long 0x00 2. " FATAL_ERR_RPT_EN ,Fatal error RPT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NONFATAL_ERR_RPT_EN ,Non fatal error RPT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " COR_ERR_RPT_EN ,Correctable error RPT enable" "Disabled,Enabled"
|
|
line.long 0x04 "ERPTCAP_ERR_STS,Root Error Status Register"
|
|
rbitfld.long 0x04 27.--31. " ADV_ERR_INTR_MSG_NUM ,Base and MSI message data offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x04 6. " FATAL_RCVD ,Fatal uncorrectable error messages" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x04 5. " NONFATAL_RCVD ,Non-fatal uncorrectable error messages" "Not received,Received"
|
|
eventfld.long 0x04 4. " FIRST_FATAL_RCVD ,First uncorrectable error message" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x04 3. " MULT_UNCOR_RCVD ,Error is received and UNCOR_RCVD is already set" "False,True"
|
|
eventfld.long 0x04 2. " STS_UNCOR_RCVD ,Error message" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x04 1. " MULT_COR_RCVD ,Correctable error message is received and COR_RCVD is already set" "False,True"
|
|
eventfld.long 0x04 0. " COR_RCVD ,Correctable error" "Not received,Received"
|
|
line.long 0x08 "ERPTCAP_ERR_ID,Error Source Identification Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " ERR_COR ,Requestor ID of first correctable error in root error status register "
|
|
hexmask.long.word 0x08 0.--15. 1. " ERR_UNCOR ,Requestor ID of first uncorrectable error in root error status register "
|
|
textline " "
|
|
tree.end
|
|
width 20.
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
tree "PCI L1 PM Substate Capability Registers"
|
|
rgroup.long 0x140++0x07
|
|
line.long 0x00 "EXT_CAP,Extended Capability Header Register"
|
|
hexmask.long.word 0x00 20.--31. 0x10 " EXT_CAP_NEXT_CAP ,Offset to the next PCI express capability structure"
|
|
bitfld.long 0x00 16.--19. " EXT_CAP_VERSION ,PCI-SIG defined version number that indicates the version of the capability structure present" ",L1_SUBSTATES,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " EXT_CAP_ID ,PCI-SIG defined ID number that indicates the nature and format of the extended capability"
|
|
line.long 0x04 "CAP,Capability Register"
|
|
bitfld.long 0x04 19.--23. " CAP_T_PWRON_VALUE ,Time (in us) that this Port requires the port on the opposite side of the link to wait" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 16.--17. " CAP_T_PWRON_SCALE ,Specifies the scale used for this port" "2 us,10 us,100 us,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " CAP_CM_RESTORE_TIME ,Time (in us) required for this port to re-establish common mode"
|
|
bitfld.long 0x04 4. " CAP_L1_PM_SUBSTATES_SUPPORTED ,L1 PM Substates is supported" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CAP_ASPM_L1_1_SUPPORTED ,ASPM L1.1 is supported" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CAP_ASPM_L1_2_SUPPORTED ,ASPM L1.2 is is supported" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CAP_PCI_PM_L1_1_SUPPORTED ,PCI-PM L1.1 is supported" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CAP_PCI_PM_L1_2_SUPPORTED ,PCI-PM L1.2 is supported" "Disabled,Enabled"
|
|
group.long 0x148++0x07
|
|
line.long 0x00 "CTRL1,Control 1 Register"
|
|
bitfld.long 0x00 29.--31. " LTR_L1_2_THRES_SCALE ,Scale for value contained within the LTR_L1.2_THRESHOLD_Value" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 16.--25. 1. " LTR1_2_THRESH_VAL ,Threshold value"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CM_RESTORE_TIME ,Restore time"
|
|
bitfld.long 0x00 3. " ASPM_L1_1_EN ,ASPM L1.1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ASPM_L1_2_EN ,ASPM L1.2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PCIPM_L1_1_EN ,PCIPM L1.1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PCIPM_L1_2_EN ,PCIPM L1.2 enable" "Disabled,Enabled"
|
|
line.long 0x04 "CTRL2,Control 2 Register"
|
|
bitfld.long 0x04 3.--7. " T_PWRON_VALUE ,Minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--1. " T_PWRON_SCALE ,Scale used for the port T_POWER_ON Valuse field in the L1 PM Substates Capabilities register" "2 us,10 us,100 us,?..."
|
|
tree.end
|
|
endif
|
|
tree "NVIDIA Private Registers"
|
|
width 20.
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "PRIV_XP_DL_0,Various Configurable Registers In The Data Link layer"
|
|
hexmask.long.word 0x00 19.--29. 1. " GEN2_REPLAY_TIMER_LIMIT ,Replay timer limit"
|
|
hexmask.long.word 0x00 10.--18. 1. " GEN2_ACK_TIMER_LIMIT ,ACK timer limit"
|
|
textline " "
|
|
hexmask.long.word 0x00 1.--9. 1. " GEN2_UPDATE_FC_THRESHOLD ,Update FC frequency"
|
|
bitfld.long 0x00 0. " GEN2_DL_TIMERS_DISABLE ,Enables the Gen2 DL timer settings" "No,Yes"
|
|
textline " "
|
|
width 34.
|
|
sif (cpuis("TEGRAX1"))
|
|
rgroup.long 0xC10++0x0F
|
|
line.long 0x00 "T_PCIE2_RP_LTR_REP_VAL,T_PCIE2_RP_LTR_REP_VAL"
|
|
hexmask.long.word 0x00 16.--31. 1. " T_PCIE2_RP_LTR_REP_VAL_NO_SNOOP ,T_PCIE2_RP_LTR_REP_VAL_NO_SNOOP"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " T_PCIE2_RP_LTR_REP_VAL_SNOOP ,T_PCIE2_RP_LTR_REP_VAL_SNOOP"
|
|
line.long 0x04 "T_PCIE2_RP_L1_1_ENTRY_COUNT,T_PCIE2_RP_L1_1_ENTRY_COUNT"
|
|
bitfld.long 0x04 31. " T_PCIE2_RP_L1_1_ENTRY_COUNT_RESET ,T_PCIE2_RP_L1_1_ENTRY_COUNT_RESET" "Done,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 30. " T_PCIE2_RP_L1_1_ENTRY_COUNT_FREEZE ,T_PCIE2_RP_L1_1_ENTRY_COUNT_FREEZE" "Done,Pending"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " T_PCIE2_RP_L1_1_ENTRY_COUNT_VALUE ,T_PCIE2_RP_L1_1_ENTRY_COUNT_VALUE"
|
|
line.long 0x08 "T_PCIE2_RP_L1_2_ENTRY_COUNT,T_PCIE2_RP_L1_2_ENTRY_COUNT"
|
|
bitfld.long 0x08 31. " T_PCIE2_RP_L1_2_ENTRY_COUNT_RESET ,T_PCIE2_RP_L1_2_ENTRY_COUNT_RESET" "Done,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 30. " T_PCIE2_RP_L1_2_ENTRY_COUNT_FREEZE ,T_PCIE2_RP_L1_2_ENTRY_COUNT_FREEZE" "Done,Pending"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--15. 1. " T_PCIE2_RP_L1_2_ENTRY_COUNT_VALUE ,T_PCIE2_RP_L1_2_ENTRY_COUNT_VALUE"
|
|
line.long 0x0C "T_PCIE2_RP_L1_2_ABORT_COUNT,T_PCIE2_RP_L1_2_ABORT_COUNT"
|
|
bitfld.long 0x0C 31. " T_PCIE2_RP_L1_2_ABORT_COUNT_RESET ,T_PCIE2_RP_L1_2_ABORT_COUNT_RESET" "Done,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 30. " T_PCIE2_RP_L1_2_ABORT_COUNT_FREEZE ,T_PCIE2_RP_L1_2_ABORT_COUNT_FREEZE" "Done,Pending"
|
|
textline " "
|
|
hexmask.long.word 0x0C 0.--15. 1. " T_PCIE2_RP_L1_2_ABORT_COUNT_VALUE ,0 T_PCIE2_RP_L1_2_ABORT_COUNT_VALUE"
|
|
textline " "
|
|
elif cpuis("TEGRAX2")
|
|
width 27.
|
|
group.long 0xC00++0x0F
|
|
line.long 0x00 "L1_PM_SUBSTATES_CYA,L1 PM Substates CYA Register"
|
|
bitfld.long 0x00 26. " REFCLK_ON_WITH_PAD_PLL_LOCK ,Refclk on with pad PLL lock" "Not locked,Locked"
|
|
bitfld.long 0x00 25. " REFCLK_ON_WITH_PLLE_LOCK ,Refclk on with PLLE lock" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24. " HIDE_CAP ,Hide capability of L1 PM substates" "Not hidden,Hidden"
|
|
bitfld.long 0x00 19.--23. " T_PWRON_VALUE ,Time (in us) that this port requires the port on the opposite side of link to wait in L1.2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " T_PWRON_SCALE ,Specifies the scale used for the port T_POWER_ON value field in the L1 PM substates capabilities register" "2 us,10 us,100 us,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " CM_RESTORE_TIME ,Time (in us) required for this port to re-establish common mode as described in table in the L1 PM substates ECN"
|
|
textline " "
|
|
bitfld.long 0x00 4. " L1_PM_SUBSTATES ,L1 PM Substates support enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASPM_L1_1 ,ASPM L1.1 support enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ASPM_L1_2 ,ASPM L1.2 support enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PCI_PM_L1_1 ,PCI-PM L1.1 support enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PCI_PM_L1_2 ,PCI-PM L1.2 support enable" "Disabled,Enabled"
|
|
line.long 0x04 "L1_PM_SUBSTATES_1_CYA,L1 PM Substates 1 CYA Register"
|
|
bitfld.long 0x04 22. " RX_TERM_EN_IN_L1_2 ,Receiver PAD termination when in L1.2 enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 13.--21. 1. " CHK_CLKREQ_ASSERTED_DLY ,Amount of time the DUT waits in L1.2"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--12. 1. " T_PWR_OFF_DLY ,T POWER ON DELY diagnostic amount of time the DUT waits in L1.2_entry before it enters L1.2_idle"
|
|
line.long 0x08 "L1_PM_SUBSTATES_2_CYA,L1 PM Substates 2 CYA Register"
|
|
bitfld.long 0x08 21.--24. " MICROSECOND_COMP ,Compensation value of the crystal oscillator frequency in microsecond tick generator used for REFCLK_ON time and common-mode turn ON time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x08 13.--20. 1. " MICROSECOND ,Microsecond diagnostic bit number of clocks in a microsecond in clk25m"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--12. 1. " T_L1_2_DLY ,T L1.2 delay diagnostic"
|
|
line.long 0x0C "L1_PM_SUBSTATES_3_CYA,L1 PM Substates 3 CYA Register"
|
|
hexmask.long.word 0x0C 18.--30. 1. " L11_T_REFCLK_ON ,Number of microseconds the port must wait in L1.1 to enable refclk after clkreq# has been asserted"
|
|
bitfld.long 0x0C 17. " L11_T_REFCLK_ON_ENABLE ,Refclk clock timer logic when in L1.1 after seeing deassertion of clkreq# enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x0C 4.--16. 1. " L12_T_REFCLK_ON ,Number of microseconds the port must wait to enable refclk after clkreq# has been asserted"
|
|
bitfld.long 0x0C 3. " PCIPM_L1_2 ,PCIMPM L1.2 functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " ASPM_L1_2 ,ASPM L1.2 functionality enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " PCIPM_L1_1 ,PCIPM L1.1 functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " ASPM_L1_1 ,ASPM L1.1 functionality enable" "Disabled,Enabled"
|
|
rgroup.long 0xC10++0x03
|
|
line.long 0x00 "LTR_REP_VAL,LTR Reported Value Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " NO_SNOOP ,Value for no snoop"
|
|
hexmask.long.word 0x00 0.--15. 1. " SNOOP ,Value for snoop"
|
|
group.long 0xC14++0x17
|
|
line.long 0x00 "L1_1_ENTRY_COUNT,L1.1 Entry Count Register"
|
|
bitfld.long 0x00 31. " RESET ,VALUE reset" "No reset,Reset"
|
|
bitfld.long 0x00 30. " FREEZE ,Freeze" "No freeze,Freeze"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Number of times the link entered the L1.1 state"
|
|
line.long 0x04 "L1_2_ENTRY_COUNT,L1.2 Entry Count Register"
|
|
bitfld.long 0x04 31. " RESET ,VALUE reset" "No reset,Reset"
|
|
bitfld.long 0x04 30. " FREEZE ,Freeze" "No freeze,Freeze"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " VALUE ,Number of times the link entered L1.2 ENTRY state"
|
|
line.long 0x08 "L1_2_ABORT_COUNT,L1.2 Abort Count Register"
|
|
bitfld.long 0x08 31. " RESET ,VALUE reset" "No reset,Reset"
|
|
bitfld.long 0x08 30. " FREEZE ,Freeze" "No freeze,Freeze"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--15. 1. " VALUE ,Number of times the link entered the L1.2 ENTRY state"
|
|
line.long 0x0C "LTR_OVERRIDE,LTR Override Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " NO_SNOOP ,LTR override no snoop value"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SNOOP ,LTR override snoop value"
|
|
line.long 0x10 "L1SS_SPARE,L1SS Spare Register"
|
|
hexmask.long.word 0x10 18.--31. 1. " SPARE2 ,Spare 2"
|
|
eventfld.long 0x10 17. " LTR_MSG_RCV_STS ,LTR MSG RCV STS" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 16. " LTR_MSG_INT_EN ,LTR MSG INT enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x10 2.--15. 1. " SPARE1 ,Spare 1"
|
|
textline " "
|
|
bitfld.long 0x10 1. " LTR_OVERRIDE_NO_SNOOP_EN ,LTR override no snoop enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " LTR_OVERRIDE_SNOOP_EN ,LTR override snoop enable" "Disabled,Enabled"
|
|
line.long 0x14 "SLCG_OVERRIDE_DIS_SLCG,SLCG Override Disable SLCG Register"
|
|
bitfld.long 0x14 22. " PRI_CLK ,PRI CLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 21. " TMS0_UFPCI_CLK ,TMS0 UFPCI CLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " TMS0_DFPCI_CLK ,TMS0 DFPCI CLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 19. " TMS0C2_XTXCLK1X ,TMS0C2 XTXCLK1X enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 18. " TMS0C2_XCLK ,TMS0C2 XCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 17. " TMS0C1_XTXCLK1X ,TMS0C1 XTXCLK1X enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " TMS0C1_XCLK ,TMS0C1 XCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " TMS0C0_XTXCLK1X ,TMS0C0 XTXCLK1X enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 14. " TMS0C0_XCLK ,TMS0C0 XCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 13. " TMSC0_XCLK ,TMSC0 XCLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 12. " T0C2_PCA_XCLK ,T0C2 PCA XCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " T0C2_PCA_UFPCI_CLK ,T0C2 PCA UFPCI CLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 10. " T0C1_PCA_XCLK ,T0C1 PCA XCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " T0C1_PCA_UFPCI_CLK ,T0C1 PCA UFPCI CLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 8. " T0C0_PCA_XCLK ,T0C0 PCA XCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 7. " T0C0_PCA_UFPCI_CLK ,T0C0 PCA UFPCI CLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 6. " GRP2_XTXCLK1X ,GRP2 XTXCLK1X enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " GRP2_XCLK ,GRP2 XCLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " GRP1_XTXCLK1X ,GRP1 XTXCLK1X enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " GRP1_XCLK ,GRP1 XCLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " GRP0_XTXCLK1X ,GRP0 XTXCLK1X enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " GRP0_XCLK ,GRP0 XCLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " CLK25M ,CLK25M enable" "Disabled,Enabled"
|
|
group.long 0xD00++0x1B
|
|
line.long 0x00 "DBG0,Debug 0"
|
|
line.long 0x04 "DBG1,Debug 1"
|
|
line.long 0x08 "DBG2,Debug 2"
|
|
line.long 0x0C "DBG3,Debug 3"
|
|
line.long 0x10 "DBG4,Debug 4"
|
|
line.long 0x14 "DBG5,Debug 5"
|
|
line.long 0x18 "DBG6,Debug 6"
|
|
bitfld.long 0x18 31. " LOW_POWER_MODE ,Low power mode" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " CG_EN ,CG enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x18 0.--29. 1. " CTL ,Control"
|
|
rgroup.long 0xD1C++0x03
|
|
line.long 0x00 "DBG_RD_BACK_LO,Debug RD Back LO"
|
|
group.long 0xD20++0x1B
|
|
line.long 0x00 "DBG_RD_BACK_HI,Debug RD Back HI"
|
|
line.long 0x04 "LANE_DBG0,Lane Debug 0"
|
|
line.long 0x08 "LANE_DBG1,Lane Debug 1"
|
|
line.long 0x0C "LANE_DBG2,Lane Debug 2"
|
|
line.long 0x10 "LANE_DBG3,Lane Debug 3"
|
|
line.long 0x14 "LANE_DBG4,Lane Debug 4"
|
|
line.long 0x18 "LANE_DBG5,Lane Debug 5"
|
|
bitfld.long 0x18 31. " LOW_POWER_MODE ,Low power mode" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " CG_EN ,CG enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x18 0.--29. 1. " CTL ,Control"
|
|
rgroup.long 0xD3C++0x07
|
|
line.long 0x00 "LANE_DBG_RD_BACK_LO_VALUE,Lane Debug RD Back LO Value"
|
|
line.long 0x04 "LANE_DBG_RD_BACK_HI_VALUE,Lane Debug RD Back HI Value"
|
|
group.long 0xD44++0x0B
|
|
line.long 0x00 "LINK_DBG0,Link Debug 0"
|
|
line.long 0x04 "LINK_DBG1,Link Debug 1"
|
|
line.long 0x08 "LINK_DBG2,Link Debug 2"
|
|
bitfld.long 0x08 31. " LOW_POWER_MODE ,Low power mode" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " CG_EN ,CG enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " CTL ,Control" "0,1"
|
|
rgroup.long 0xD50++0x07
|
|
line.long 0x00 "LINK_DBG_RD_BACK_LO_VALUE,Link Debug RD Back LO Value"
|
|
line.long 0x04 "LINK_DBG_RD_BACK_HI_VALUE,Link Debug RD Back HI Value"
|
|
endif
|
|
width 27.
|
|
group.long 0xD5C++0x03
|
|
line.long 0x00 "PIPE_CTL,Controls (enabling /disabling) the pipelines added to meet timing on various interfaces"
|
|
bitfld.long 0x00 8. " UFA2WRR_PWTOP ,UFA2WRR PWTOP enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " UBFI2DFI_P2P ,UBFI2DFI P2P enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TXBA2DFI_WR ,TXBA2DFI WR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CMDQ2UFARB ,CMDQ2UFARB enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UBFI2DFI_NTT ,UBFI2DFI NTT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PCA ,PCA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DFIREQ ,DFIREQ enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DFIRSP ,DFIRSP enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DFI2UBFI ,DFI2UBFI enable" "Disabled,Enabled"
|
|
sif (cpuis("TEGRAX2"))
|
|
group.long 0xD60++0x07
|
|
line.long 0x00 "XP_BUST_TRIG1,XP Bust Trigger 1"
|
|
bitfld.long 0x00 25. " L02RCVRY_L0S_FTS_TO ,Allows bus tracer trigger when getting FTS timeout in L0.0s" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " L02RCVRY_TS_DET ,Allows bus tracer trigger when receiving TS in L0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " L02RCVRY_SURPRISE_EIDLE ,Allows bus tracer trigger when seeing surprise eidle in L0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 22. " L02RCVRY_8B10B_ERR ,Allows bus tracer trigger when receiving 8b10b error in L0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 21. " L02RCVRY_ADVERTISEDRATECHANGE ,Allows bus tracer trigger at advertised rate change in L0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 20. " L02RCVRY_DL_RETRAIN ,Allows bus tracer trigger at dl retrain in L0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " L02RCVRY_LPBK ,Allows bus tracer trigger at dl retrain in L0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " L02RCVRY_SPEEDCHANGE ,Allows bus tracer trigger at speed change in L0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L02RCVRY_WIDTHCHANGE ,Allows bus tracer trigger at width change in L0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 16. " L02RCVRY_LINK_RETRAIN ,Allows bus tracer trigger at link retraining in L0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. " CUST_TRANSITION_TO_MINOR_ST ,Mirror TO state of custom transition [Detect/Polling/Config/Recovery/L0/L1/L2/LoopBack/HotReset/Disabled/TXCHAR]" "Quiet/Active/Link start/RCVRLOCK/Normal/Entry/Entry/Entry/TS1/TS1/Active,Active/Config/Link accept/RCVRCFG/Entry/WAITRX/WAITRX/Active/Up check DN hold/Down wait/Compliance,Retry/Idle/Lane accept/Speed/Idle/Idle/Transmitwake/Idle/-/Entry/Eidle entry,Wait/-/Lane wait/Idle/Wait/Wait/Idle/Exit/-/Down/Eidle idle,Entry/Compliance/Idle/-/FTS/PWRUP/-/Speed/-/-/Eidle exit,-/CSpeed/PWRUP/-/PWRUP/Beacon entry/-/-/-/-/-,-/-/Complete/-/-/Beacon exit/-/Pre speed/-/-/-,-/-/-/Finish PKT/-/-/-/-/-/-/-"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " CUST_TRANSITION_FROM_MINOR_ST ,Mirror FROM state of custom transition [Detect/Polling/Config/Recovery/L0/L1/L2/LoopBack/HotReset/Disabled/TXCHAR]" "Quiet/Active/Link start/RCVRLOCK/Normal/Entry/Entry/Entry/TS1/TS1/Active,Active/Config/Link accept/RCVRCFG/Entry/WAITRX/WAITRX/Active/Up check DN hold/Down wait/Compliance,Retry/Idle/Lane accept/Speed/Idle/Idle/Transmitwake/Idle/-/Entry/Eidle entry,Wait/-/Lane wait/Idle/Wait/Wait/Idle/Exit/-/Down/Eidle idle,Entry/Compliance/Idle/-/FTS/PWRUP/-/Speed/-/-/Eidle exit,-/CSpeed/PWRUP/-/PWRUP/Beacon entry/-/-/-/-/-,-/-/Complete/-/-/Beacon exit/-/Pre speed/-/-/-,-/-/-/Finish PKT/-/-/-/-/-/-/-"
|
|
textline " "
|
|
bitfld.long 0x00 6.--9. " CUST_TRANSITION_TO_MAJOR_ST ,Major TO state of the custom transition" "DETECT,POLLING,CONFIG,,L0,L1,L2,RECOVERY,LOOPBACK,HOTRESET,DISABLED,TXCHAR,?..."
|
|
bitfld.long 0x00 2.--5. " CUST_TRANSITION_FROM_MAJOR_ST ,Major FROM state of the custom transition" "DETECT,POLLING,CONFIG,,L0,L1,L2,RECOVERY,LOOPBACK,HOTRESET,DISABLED,TXCHAR,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_EN ,Bus tracer trigger receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TX_EN ,Bus tracer trigger receive enable" "Disabled,Enabled"
|
|
line.long 0x04 "XP_BUST_TRIG2,XP BUST Trigger 2"
|
|
bitfld.long 0x04 31. " REPLAY_TIMER_EXPIRED_ERR ,REPLA timer expired error" "No error,Error"
|
|
bitfld.long 0x04 30. " SA_ERR ,SA error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 29. " DESKEW_ERR ,DESKEW error" "No error,Error"
|
|
bitfld.long 0x04 28. " TRAINING_ERR ,Training error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 27. " DPLLP_CRC_ERR ,DPLLP CRC error" "No error,Error"
|
|
bitfld.long 0x04 26. " 8B10B_ERR ,8B10B error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 25. " REPLAY_STARTED_ERR ,REPLAY started error" "No error,Error"
|
|
bitfld.long 0x04 24. " ROLLOVER_ERR ,ROLLOVER error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 23. " PWH_UPDATE_FC_ERR ,PWH update FC error" "No error,Error"
|
|
bitfld.long 0x04 22. " PWH_TOO_MANY_CREDITS_ERR ,PWH too many credits error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 21. " PWD_UPDATE_FC_ERR ,PWD update FC error" "No error,Error"
|
|
bitfld.long 0x04 20. " PWD_TOO_MANY_CREDITS_ERR ,PWD too many credits error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 19. " NPH_UPDATE_FC_ERR ,NPH update FC error" "No error,Error"
|
|
bitfld.long 0x04 18. " NPH_TOO_MANY_CREDITS_ERR ,NPH too many credits error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 17. " NPD_UPDATE_FC_ERR ,NPD update FC error" "No error,Error"
|
|
bitfld.long 0x04 16. " NPD_TOO_MANY_CREDITS_ERR ,NPD too many credits error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 15. " CH_UPDATE_FC_ERR ,CH update FC error" "No error,Error"
|
|
bitfld.long 0x04 14. " CH_TOO_MANY_CREDITS_ERR ,CH too many credits error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 13. " CD_UPDATE_FC_ERR ,CD update FC error" "No error,Error"
|
|
bitfld.long 0x04 12. " CD_TOO_MANY_CREDITS_ERR ,CD too many credits error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 11. " REC_OVFL_ISOPW_DATA_ERR ,REC overflow ISOPW data error" "No error,Error"
|
|
bitfld.long 0x04 10. " REC_OVFL_ISOPW_HDR_ERR ,REC overflow ISOPW HDR error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 9. " REC_OVFL_ISONP_HDR_ERR ,REC overflow ISONP HDR error" "No error,Error"
|
|
bitfld.long 0x04 8. " REC_OVFL_CPL_DATA_ERR ,REC overflow CPL data error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 7. " REC_OVFL_PW_DATA_ERR ,REC overflow PW data error" "No error,Error"
|
|
bitfld.long 0x04 6. " REC_OVFL_NP_DATA_ERR ,REC overflow NP data error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 5. " REC_OVFL_CPL_HDR_ERR ,REC overflow CPL HDR error" "No error,Error"
|
|
bitfld.long 0x04 4. " REC_OVFL_PW_HDR_ERR ,REC overflow PW HDR error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 3. " REC_OVFL_NP_HDR_ERR ,REC_OVFL_NP_HDR_ERR error" "No error,Error"
|
|
bitfld.long 0x04 2. " FRAMING_ERR ,Framing error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SEQ_ERR ,SEQ error" "No error,Error"
|
|
bitfld.long 0x04 0. " LCRC_ERR ,LCRC error" "No error,Error"
|
|
rgroup.long 0xD68++0x03
|
|
line.long 0x00 "XP_DEBUG,XP Debug"
|
|
bitfld.long 0x00 0.--1. " RX_CAL_STATUS ,Receiver CAL status" "Idle,Pending,Done,Disabled"
|
|
endif
|
|
tree.end
|
|
tree "Vendor-Defined Registers"
|
|
width 20.
|
|
group.long 0xE00++0x2B
|
|
line.long 0x00 "RX_HDR_LIMIT,RX HDR Limit"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPL ,Completion header buffer size"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PW ,Posted write header buffer size"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NP ,Non-posted header buffer size"
|
|
line.long 0x04 "RX_DATA_LIMIT,RX Data Limit"
|
|
hexmask.long.byte 0x04 20.--27. 1. " CPL ,Completion data buffer size"
|
|
hexmask.long.word 0x04 8.--19. 1. " PW ,Posted write data buffer size"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " NP ,Non-posted write header buffer size"
|
|
line.long 0x08 "TX_HDR_LIMIT,TX HDR Limit"
|
|
sif (cpuis("TEGRAX2"))
|
|
hexmask.long.byte 0x08 24.--31. 1. " NPT ,TX HDR limit NPT"
|
|
textline " "
|
|
hexmask.long.byte 0x08 16.--23. 1. " CPL ,Size of the downstream completions header buffer"
|
|
else
|
|
hexmask.long.byte 0x08 16.--23. 1. " NP ,Size of the downstream non posted header buffer"
|
|
endif
|
|
hexmask.long.byte 0x08 8.--15. 1. " PW ,Size of the downstream posted writes header buffer"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " NP ,Size of the downstream non posted header buffer"
|
|
line.long 0x0C "TX_DATA_LIMIT,TX Data Limit"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " PW ,Size of the downstream Posted Writes Data Buffer"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " NP ,Size of the downstream Non Posted Data Buffer"
|
|
line.long 0x10 "UFPCI,Upstream FPCI Control Register"
|
|
bitfld.long 0x10 23.--27. " ISO_WEIGHT ,ISO weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 22. " ISO_CONTROL_ENABLE ,ISO control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " ISOPW2HPISO ,Convert posted writes" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " ISONP2HPISO ,Convert non-posted reads" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x10 12.--19. 1. " REQ_PEND_PERIOD ,Timers are reset when they hit the value"
|
|
bitfld.long 0x10 10.--11. " WRR_GRANT_BURST ,Time for arbitration within a TMS" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x10 5.--9. " PW_PRI_OVR_COUNT ,Number of grants" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 0.--4. " PW_STARV_COUNT ,Number of grants" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "MISC0,Miscellaneous Register 0"
|
|
bitfld.long 0x14 31. " SHORT_RXL_TIMER ,Completion timeout feature in RXL test" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " P2P_SMALL_ISA_HOLE ,P2P settings control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " P2P_F ,Transactions (64'hF_XXXX)" "0,1"
|
|
bitfld.long 0x14 28. " P2P_E ,Transactions (64'hE_XXXX)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 27. " P2P_D ,Transactions (64'hD_XXXX)" "0,1"
|
|
bitfld.long 0x14 26. " P2P_C ,Transactions (64'hC_XXXX)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 25. " P2P_B ,Transactions (64'hB_XXXX)" "0,1"
|
|
bitfld.long 0x14 24. " P2P_A ,Transactions (64'hA_XXXX)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 23. " NISONC2HPISO ,Upgrade to HPISO Read" "Disabled,Enabled"
|
|
bitfld.long 0x14 21. " AUTO_XCLK_FREQ_EN ,XCLK frequency dynamic switch" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " RXL_CLEAR_DROP ,Receiver DROP ALL status clear" "Disabled,Enabled"
|
|
sif (cpuis("TEGRAX2"))
|
|
hexmask.long.word 0x14 4.--19. 1. " ISO_PW_ENABLE[1] ,Enables ISO PW [1] transactions for packets with TC >= TC2ISOMAP"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 3. " ISO_PW_ENABLE ,Enables ISO PW transactions for packets with TC >= TC2ISOMAP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " ISO_NP_ENABLE ,Enables ISO NP transactions for packets with TC >= TC2ISOMAP" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " NATIVE_P2P_ENABLE ,Enables native peer2peer transactions" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " ENABLE_CLUMPING ,Enables unitid clumping" "Disabled,Enabled"
|
|
line.long 0x18 "TXBA0,TXBA0 Register"
|
|
hexmask.long.word 0x18 16.--31. 1. " REPLAY_TIMER_EXPIRY ,Replay timer expiry"
|
|
bitfld.long 0x18 12. " USE_REPLAY_TIMER_OFFSET ,Use replay timer offset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 11. " CMPL_MERGE_UPTO_64DW ,Merge completions upto 64DW payloads" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " CMPL_MERGE_UPTO_32DW ,Merge completions upto 32DW payloads" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " CMPL_MERGE_DISABLE ,Disables completion merging" "No,Yes"
|
|
hexmask.long.word 0x18 0.--8. 1. " REPLAY_BUF_LIMIT ,Replay buffer limit"
|
|
line.long 0x1C "TXBA1,TXBA1 Register"
|
|
sif (cpuis("TEGRAX2"))
|
|
hexmask.long.word 0x1C 8.--16. 1. " MERGE_THRESHOLD ,Merge threshold"
|
|
else
|
|
hexmask.long.byte 0x1C 8.--15. 1. " MERGE_THRESHOLD ,Merge threshold"
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x1C 4.--7. " CM_OVER_PW_BURST ,Inputs into the downstream arbiter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
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bitfld.long 0x1C 0.--3. " PW_OVER_CM_BURST ,Inputs into the downstream arbiter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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else
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rbitfld.long 0x1C 0.--3. " PW_OVER_CM_BURST ,Inputs into the downstream arbiter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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endif
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line.long 0x20 "FORCEFC,FC Priority Flip Threshold Register"
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hexmask.long.byte 0x20 24.--31. 1. " NPD_UNRET_THRESH ,NPD UNRET THRESH"
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hexmask.long.byte 0x20 16.--23. 1. " NPH_UNRET_THRESH ,NPH UNRET THRESH"
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textline " "
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hexmask.long.byte 0x20 8.--15. 1. " PWD_UNRET_THRESH ,PWD UNRET THRESH"
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hexmask.long.byte 0x20 0.--7. 1. " PWH_UNRET_THRESH ,PWH UNRET THRESH"
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line.long 0x24 "TIMEOUT0,LINK LTSSM Timeout 0 Register"
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hexmask.long.byte 0x24 24.--31. 1. " PAD_SPDCHNG_GEN2 ,Time to wait for pads to change speed from Gen1 to Gen2"
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hexmask.long.word 0x24 8.--23. 1. " PAD_PWRUP_CM ,Time to power up pads (no common-mode voltage during power down)"
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textline " "
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hexmask.long.byte 0x24 0.--7. 1. " PAD_PWRUP ,Time to power up pads (common-mode voltage during power down)"
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line.long 0x28 "TIMEOUT1,LINK LTSSM Timeout 1. Register"
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hexmask.long.byte 0x28 24.--31. 1. " RCVRY_SPD_UNSUCCESS_EIDLE ,Wait time in E-Idle after unsuccessful speed change"
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hexmask.long.byte 0x28 16.--23. 1. " RCVRY_SPD_SUCCESS_EIDLE ,Wait time in E-Idle after unsuccessful speed change"
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textline " "
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hexmask.long.word 0x28 0.--15. 1. " PAD_SPDCHNG_GEN1 ,Wait time for pads to change speed from Gen2 to Gen1"
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rgroup.long 0xE34++0x03
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line.long 0x00 "PRBS,PRBS Results Register"
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hexmask.long.word 0x00 16.--31. 1. " LOCKED ,Locks lanes onto the incoming PRBS pattern"
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hexmask.long.word 0x00 0.--15. 1. " ERR_COUNT_OVERFLOW ,Number of bit mismatches during PRBS run"
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group.long 0xE38++0x03
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line.long 0x00 "PRBS_ERR,PRBS Results Register"
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hexmask.long.word 0x00 16.--31. 1. " COUNT ,Number of bit errors detected in the incoming PRBS stream"
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bitfld.long 0x00 0.--3. " SELECT ,Selects which lane number's Error Count shows up in the ERR_COUNT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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width 22.
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group.long 0xE3C++0x27
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line.long 0x00 "EIDLE_INFER_TO_0,EIDLE Inference Timeout Register 0"
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hexmask.long.word 0x00 16.--31. 1. " RCVRCFG_SUC_SPEED ,Infer E-Idle after this amount of time while in recovery"
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hexmask.long.word 0x00 0.--15. 1. " L0_LPBK ,Infer E-Idle after this amount of time while in L0 or loopback"
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line.long 0x04 "EIDLE_INFER_TO_1,EIDLE Inference Timeout Register 1"
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hexmask.long.word 0x04 16.--31. 1. " UNSUC_SPEED_GEN2 ,Infer E-Idle after this amount of time while in recovery"
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hexmask.long.word 0x04 0.--15. 1. " UNSUC_SPEED_GEN1 ,Infer E-Idle after this amount of time while in recovery"
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line.long 0x08 "LTSSM_DBGREG,LTSSM Debug Register"
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eventfld.long 0x08 31. " LINKFSM[31] ,LINKFSM31" "Init,Clear"
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eventfld.long 0x08 30. " [30] ,LINKFSM30" "Init,Clear"
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textline " "
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eventfld.long 0x08 29. " [29] ,LINKFSM29" "Init,Clear"
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eventfld.long 0x08 28. " [28] ,LINKFSM28" "Init,Clear"
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textline " "
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eventfld.long 0x08 27. " [27] ,LINKFSM27" "Init,Clear"
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eventfld.long 0x08 26. " [26] ,LINKFSM26" "Init,Clear"
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textline " "
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eventfld.long 0x08 25. " [25] ,LINKFSM25" "Init,Clear"
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eventfld.long 0x08 24. " [24] ,LINKFSM24" "Init,Clear"
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textline " "
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eventfld.long 0x08 23. " [23] ,LINKFSM23" "Init,Clear"
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eventfld.long 0x08 22. " [22] ,LINKFSM22" "Init,Clear"
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textline " "
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eventfld.long 0x08 21. " [21] ,LINKFSM21" "Init,Clear"
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eventfld.long 0x08 20. " [20] ,LINKFSM20" "Init,Clear"
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textline " "
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eventfld.long 0x08 19. " [19] ,LINKFSM19" "Init,Clear"
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eventfld.long 0x08 18. " [18] ,LINKFSM18" "Init,Clear"
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textline " "
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eventfld.long 0x08 17. " [17] ,LINKFSM17" "Init,Clear"
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eventfld.long 0x08 16. " [16] ,LINKFSM16" "Init,Clear"
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textline " "
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eventfld.long 0x08 15. " [15] ,LINKFSM15" "Init,Clear"
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eventfld.long 0x08 14. " [14] ,LINKFSM14" "Init,Clear"
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textline " "
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eventfld.long 0x08 13. " [13] ,LINKFSM13" "Init,Clear"
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eventfld.long 0x08 12. " [12] ,LINKFSM12" "Init,Clear"
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textline " "
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eventfld.long 0x08 11. " [11] ,LINKFSM11" "Init,Clear"
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eventfld.long 0x08 10. " [10] ,LINKFSM10" "Init,Clear"
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|
textline " "
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eventfld.long 0x08 9. " [9] ,LINKFSM9" "Init,Clear"
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eventfld.long 0x08 8. " [8] ,LINKFSM8" "Init,Clear"
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|
textline " "
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|
eventfld.long 0x08 7. " [7] ,LINKFSM7" "Init,Clear"
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|
eventfld.long 0x08 6. " [6] ,LINKFSM6" "Init,Clear"
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|
textline " "
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eventfld.long 0x08 5. " [5] ,LINKFSM5" "Init,Clear"
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|
eventfld.long 0x08 4. " [4] ,LINKFSM4" "Init,Clear"
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|
textline " "
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|
eventfld.long 0x08 3. " [3] ,LINKFSM3" "Init,Clear"
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|
eventfld.long 0x08 2. " [2] ,LINKFSM2" "Init,Clear"
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|
textline " "
|
|
eventfld.long 0x08 1. " [1] ,LINKFSM1" "Init,Clear"
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|
eventfld.long 0x08 0. " [0] ,LINKFSM0" "Init,Clear"
|
|
line.long 0x0C "PRIV_ERRSTS,Detailed Private Error Status Register"
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|
eventfld.long 0x0C 31. " REPLAY_TIMER_EXPIRED_ERR ,Replay timer expired error" "No error,Error"
|
|
eventfld.long 0x0C 30. " SA_ERR ,SA error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 29. " DESKEW_ERR ,DESKEW error" "No error,Error"
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|
eventfld.long 0x0C 28. " TRAINING_ERR ,Training error" "No error,Error"
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|
textline " "
|
|
eventfld.long 0x0C 27. " DLLP_CRC_ERR ,DLLP CRC error" "No error,Error"
|
|
eventfld.long 0x0C 26. " 8B10B_ERR ,8B10B error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " REPLAY_STARTED_ERR ,Replay started error" "No error,Error"
|
|
eventfld.long 0x0C 24. " REPLAY_ROLLOVER_ERR ,Replay rollover error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 23. " PWH_UPDATE_FC_ERR ,PWH update FC error" "No error,Error"
|
|
eventfld.long 0x0C 22. " PWH_TOO_MANY_CREDITS_ERR ,PWH too many credits error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 21. " PWD_UPDATE_FC_ERR ,PWD update FC error" "No error,Error"
|
|
eventfld.long 0x0C 20. " PWD_TOO_MANY_CREDITS_ERR ,PWD too many credits error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " NPH_UPDATE_FC_ERR ,NPH update FC error" "No error,Error"
|
|
eventfld.long 0x0C 18. " NPH_TOO_MANY_CREDITS_ERR ,NPH too many credits error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 17. " NPD_UPDATE_FC_ERR ,NPD update FC error" "No error,Error"
|
|
eventfld.long 0x0C 16. " NPD_TOO_MANY_CREDITS_ERR ,NPD too many credits error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 15. " CH_UPDATE_FC_ERR ,CH update FC error" "No error,Error"
|
|
eventfld.long 0x0C 14. " CH_TOO_MANY_CREDITS_ERR ,CH too many credits error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 13. " CD_UPDATE_FC_ERR ,CD update FC error" "No error,Error"
|
|
eventfld.long 0x0C 12. " CD_TOO_MANY_CREDITS_ERR ,CD too many credits error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 11. " REC_OVFL_ISOPW_DATA_ERR ,REC overflow ISOPW data error" "No error,Error"
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|
eventfld.long 0x0C 10. " REC_OVFL_ISOPW_HDR_ERR ,REC overflow ISOPW HDR error" "No error,Error"
|
|
textline " "
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|
eventfld.long 0x0C 9. " REC_OVFL_ISONP_HDR_ERR ,REC overflow ISONP HDR error" "No error,Error"
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|
eventfld.long 0x0C 8. " REC_OVFL_CPL_DATA_ERR ,REC overflow CPL data error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " REC_OVFL_PW_DATA_ERR ,REC overflow PW data error" "No error,Error"
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|
eventfld.long 0x0C 6. " REC_OVFL_NP_DATA_ERR ,REC overflow NP data error" "No error,Error"
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|
textline " "
|
|
eventfld.long 0x0C 5. " REC_OVFL_CPL_HDR_ERR ,REC overflow CPL HDR error" "No error,Error"
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eventfld.long 0x0C 4. " REC_OVFL_PW_HDR_ERR ,REC overflow PW HDR error" "No error,Error"
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|
textline " "
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eventfld.long 0x0C 3. " REC_OVFL_NP_HDR_ERR ,REC overflow NP HDR error" "No error,Error"
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eventfld.long 0x0C 2. " FRAMING_ERR ,Framing error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " SEQ_ERR ,SEQ error" "No error,Error"
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|
eventfld.long 0x0C 0. " LCRC_ERR ,LCRC error" "No error,Error"
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line.long 0x10 "PRIV_ERRMSK,Detailed Private Error Mask Register"
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bitfld.long 0x10 31. " REPLAY_TIMER_EXPIRED_ERR_EN ,Replay timer expired error enable" "Disabled,Enabled"
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bitfld.long 0x10 30. " SA_ERR_EN ,SA error enable" "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x10 27. " DLLP_CRC_ERR_EN ,DLLP CRC error enable" "Disabled,Enabled"
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|
bitfld.long 0x10 26. " 8B10B_ERR_EN ,8B10B error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " REPLAY_ROLLOVER_ERR_EN ,Replay rollover error enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 23. " PWH_UPDATE_FC_ERR_EN ,PWH update FC error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 22. " PWD_TOO_MANY_CREDITS_ERR_EN ,PWD too many credits error enable" "Disabled,Enabled"
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|
bitfld.long 0x10 21. " PWD_UPDATE_FC_ERR_EN ,PWD update FC error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PWD_TOO_MANY_CREDITS_ERR_EN ,PWD too many credits error enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 19. " NPH_UPDATE_FC_ERR_EN ,NPH update FC error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 18. " NPH_TOO_MANY_CREDITS_ERR_EN ,NPH too many credits error enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " NPD_UPDATE_FC_ERR_EN ,NPD update FC error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " NPD_TOO_MANY_CREDITS_ERR_EN ,NPD too many credits error enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " CH_UPDATE_FC_ERR_EN ,CH update FC error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 14. " CH_TOO_MANY_CREDITS_ERR_EN ,CH too many credits error enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " CD_UPDATE_FC_ERR_EN ,CD update FC error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 12. " CD_TOO_MANY_CREDITS_ERR_EN ,CD too many credits error enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 11. " DLL_PROTOCOL_ERR_EN ,DLL protocol error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " FRAMING_ERR_EN ,Framing error enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " SEQ_ERR_EN ,SEQ error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " LCRC_ERR_EN ,LCRC error enable" "Disabled,Enabled"
|
|
line.long 0x14 "LTSSM_TRACE_CONTROL,LTSSM Trace Control Register"
|
|
bitfld.long 0x14 11.--13. " TRIG_PRX_LTSSM_MINOR ,Trigger PRX LTSSM minor" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 8.--10. " TRIG_PTX_LTSSM_MINOR ,Trigger PTX LTSSM minor" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " TRIG_LTSSM_MAJOR ,Trigger LTSSM major" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 3. " TRIG_ON_EVENT ,Trigger on event" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x14 2. " CLEAR_RAM ,Clear RAM" "Not cleared,Cleared"
|
|
bitfld.long 0x14 1. " WRAP_EN ,Wrap enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " STORE_EN ,Store enable" "Disabled,Enabled"
|
|
line.long 0x18 "LTSSM_TRACE_STATUS,LTSSM Trace Status Register"
|
|
rbitfld.long 0x18 19.--21. " PRX_LTSSM_MINOR ,PRX LTSSM minor" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x18 16.--18. " PTX_LTSSM_MINOR ,PTX LTSSM minor" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
rbitfld.long 0x18 12.--15. " LTSSM_MAJOR ,LTSSM major" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x18 11. " READ_DATA_VALID ,Read data valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x18 6.--10. " READ_ADDR ,Read address to LTSSM trace RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x18 1.--5. " WRITE_PTR ,Current location of write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
rbitfld.long 0x18 0. " RAM_FULL ,All entries in RAM has been written" "Not full,Full"
|
|
line.long 0x1C "PG,PCIe Power Gate Register"
|
|
bitfld.long 0x1C 2. " RCVD_PME_TO_ACK_INTR_EN ,Generation of interrupt on reception of PME TO ACK TLP" "Disabled,Enabled"
|
|
eventfld.long 0x1C 1. " RCVD_PME_TO_ACK ,Root port received a PME TO ACK TLP" "Init,Clear"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " SEND_PME_TO_MSG ,Send a PME TO message downstream" "Idle,Send now"
|
|
line.long 0x20 "VAR_RANGE0,PCIe Legacy I/O Decode Range Control Register 0"
|
|
hexmask.long.word 0x20 18.--31. 0x04 " LIMIT ,Top address for the variable range positive decode addresses"
|
|
hexmask.long.word 0x20 2.--15. 0x04 " BASE ,Base address for the variable range positive decode addresses"
|
|
textline " "
|
|
bitfld.long 0x20 0. " ENABLE ,Enable" "Disabled,Enabled"
|
|
line.long 0x24 "VAR_RANGE1,PCIe Legacy I/O Decode Range Control Register 1"
|
|
hexmask.long.word 0x24 18.--31. 0x04 " LIMIT ,Top address for the variable range positive decode addresses"
|
|
textline " "
|
|
hexmask.long.word 0x24 2.--15. 0x04 " BASE ,Base address for the variable range positive decode addresses"
|
|
bitfld.long 0x24 0. " ENABLE ,Enable" "Disabled,Enabled"
|
|
sif (cpuis("TEGRAX1"))
|
|
group.long 0xE80++0x1F
|
|
line.long 0x00 "T_PCIE2_RP_ECTL_1_R1,T_PCIE2_RP_ECTL_1_R1"
|
|
bitfld.long 0x00 24.--27. " T_PCIE2_RP_ECTL_1_R1_RX_FELS_1C ,T_PCIE2_RP_ECTL_1_R1_RX_FELS_1C" "DEFAULT,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 18.--19. " T_PCIE2_RP_ECTL_1_R1_RX_TERM_CTRL_1C ,T_PCIE2_RP_ECTL_1_R1_RX_TERM_CTRL_1C" "DEFAULT,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " T_PCIE2_RP_ECTL_1_R1_TX_TERM_CTRL_1C ,T_PCIE2_RP_ECTL_1_R1_TX_TERM_CTRL_1C" "DEFAULT,1,2,3"
|
|
bitfld.long 0x00 12.--15. " T_PCIE2_RP_ECTL_1_R1_TX_DRV_CTRL_1C ,T_PCIE2_RP_ECTL_1_R1_TX_DRV_CTRL_1C" "DEFAULT,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " T_PCIE2_RP_ECTL_1_R1_TX_DRV_SLEW_1C ,T_PCIE2_RP_ECTL_1_R1_TX_DRV_SLEW_1C" "DEFAULT,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--5. " T_PCIE2_RP_ECTL_1_R1_TX_DRV_AMP_1C ,T_PCIE2_RP_ECTL_1_R1_TX_DRV_AMP_1C" "DEFAULT,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "T_PCIE2_RP_ECTL_2_R1,T_PCIE2_RP_ECTL_1_R2"
|
|
bitfld.long 0x04 18.--19. " T_PCIE2_RP_ECTL_2_R1_RX_IQ_CTRL_1C ,T_PCIE2_RP_ECTL_2_R1_RX_IQ_CTRL_1C" "DEFAULT,1,2,3"
|
|
hexmask.long.word 0x04 0.--15. 1. " T_PCIE2_RP_ECTL_2_R1_RX_CTLE_1C ,T_PCIE2_RP_ECTL_2_R1_RX_CTLE_1C"
|
|
line.long 0x08 "T_PCIE2_RP_ECTL_3_R1,T_PCIE2_RP_ECTL_3_R1"
|
|
line.long 0x0C "T_PCIE2_RP_ECTL_4_R1,T_PCIE2_RP_ECTL_4_R1"
|
|
hexmask.long.word 0x0C 16.--31. 1. " T_PCIE2_RP_ECTL_4_R1_RX_CDR_CTRL_1C ,T_PCIE2_RP_ECTL_4_R1_RX_CDR_CTRL_1C"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " T_PCIE2_RP_ECTL_4_R1_RX_PI_CTRL_1C ,T_PCIE2_RP_ECTL_4_R1_RX_PI_CTRL_1C"
|
|
line.long 0x10 "T_PCIE2_RP_ECTL_5_R1,T_PCIE2_RP_ECTL_5_R1"
|
|
line.long 0x14 "T_PCIE2_RP_ECTL_6_R1,T_PCIE2_RP_ECTL_6_R1"
|
|
line.long 0x18 "T_PCIE2_RP_ECTL_7_R1,T_PCIE2_RP_ECTL_7_R1"
|
|
bitfld.long 0x18 8.--13. " T_PCIE2_RP_ECTL_7_R1_TX_DRV_PRE_1C ,T_PCIE2_RP_ECTL_7_R1_TX_DRV_PRE_1C" "DEFAULT,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x18 0.--5. " T_PCIE2_RP_ECTL_7_R1_TX_DRV_POST_1C ,T_PCIE2_RP_ECTL_7_R1_TX_DRV_POST_1C" "DEFAULT,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xEA0++0x1B
|
|
line.long 0x00 "T_PCIE2_RP_ECTL_1_R2,T_PCIE2_RP_ECTL_1_R2"
|
|
bitfld.long 0x00 24.--27. " T_PCIE2_RP_ECTL_1_R2_RX_FELS_1C ,T_PCIE2_RP_ECTL_1_R2_RX_FELS_1C" "DEFAULT,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "T_PCIE2_RP_ECTL_2_R2,T_PCIE2_RP_ECTL_2_R2"
|
|
hexmask.long.word 0x04 16.--31. 1. " T_PCIE2_RP_ECTL_2_R2_RX_DFE_1C ,T_PCIE2_RP_ECTL_2_R2_RX_DFE_1C"
|
|
hexmask.long.word 0x04 0.--15. 1. " T_PCIE2_RP_ECTL_2_R2_CDR_CNTL_1C ,T_PCIE2_RP_ECTL_2_R2_CDR_CNTL_1C"
|
|
line.long 0x08 "T_PCIE2_RP_ECTL_3_R2,T_PCIE2_RP_ECTL_3_R2"
|
|
line.long 0x0C "T_PCIE2_RP_ECTL_4_R2,T_PCIE2_RP_ECTL_4_R2"
|
|
hexmask.long.word 0x0C 16.--31. 1. " T_PCIE2_RP_ECTL_4_R2_RX_CDR_CTRL_1C ,T_PCIE2_RP_ECTL_4_R2_RX_CDR_CTRL_1C"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " T_PCIE2_RP_ECTL_4_R2_RX_PI_CTRL_1C ,T_PCIE2_RP_ECTL_4_R2_RX_PI_CTRL_1C"
|
|
line.long 0x10 "T_PCIE2_RP_ECTL_5_R2,T_PCIE2_RP_ECTL_5_R2"
|
|
line.long 0x14 "T_PCIE2_RP_ECTL_6_R2,T_PCIE2_RP_ECTL_6_R2"
|
|
line.long 0x18 "T_PCIE2_RP_ECTL_7_R1,T_PCIE2_RP_ECTL_7_R1"
|
|
bitfld.long 0x18 8.--13. " T_PCIE2_RP_ECTL_7_R2_TX_DRV_PRE_SEL0_1C ,T_PCIE2_RP_ECTL_7_R2_TX_DRV_PRE_SEL0_1C" "Default,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x18 0.--5. " T_PCIE2_RP_ECTL_7_R2_TX_DRV_POST_SEL0_1C ,T_PCIE2_RP_ECTL_7_R2_TX_DRV_POST_SEL0_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Default,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xF00++0x0B
|
|
line.long 0x00 "VEND_XP,Vendor XP Register (NVIDIA's Implementation)"
|
|
bitfld.long 0x00 31. " FORCE_COMPLIANCE ,Force compliance" "Disabled,Enabled"
|
|
rbitfld.long 0x00 30. " DL_UP ,Status of data link layer in XP" "Down,Up"
|
|
textline " "
|
|
bitfld.long 0x00 29. " INTERLEAVE_DLLPS ,Interleave DLLPS" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " OPPORTUNISTIC_UPDATEFC ,DL will send any pending UpdateFC packet" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " OPPORTUNISTIC_ACK ,DL will send pending Acks" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TRAIN_ERR_ENABLE ,Enables reporting of training errors" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 18.--25. 1. " UPDATE_FC_THRESHOLD ,Override for the UpdateFC frequency"
|
|
hexmask.long.word 0x00 2.--17. 1. " PRBS_STAT ,Results of loopback mode testing"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PRBS_EN ,Enables the root port as loopback master" "Disabled,Enabled"
|
|
sif (!cpuis("TEGRAX1")&&!cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " EMULATION ,Enables emulation mode operation" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "VEND_XP1,Vendor XP Register 1 (NVIDIA's Implementation)"
|
|
bitfld.long 0x04 29.--31. " L1_EXIT_LATENCY ,L1 exit latency for the given PCI express link" "< 1us,1us - 2us,2us - 4us,4us - 8us,8us - 16us,16us -32us,32us-64us,> 64us"
|
|
bitfld.long 0x04 28. " FORCE_DOWNSTREAM_NO_SNOOP ,Force downstream no snoop" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FORCE_UPSTREAM_NONCOH ,Force upstream non-coherent" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " NP_REQ_TIMEOUT ,Disable downstream NP request timeout" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 23. " IGNORE_L0S ,Ignore L0S" "No,Yes"
|
|
bitfld.long 0x04 22. " DONT_MERGE_PMASNAK ,Don't merge PMASNAK" "Merged,Not merged"
|
|
textline " "
|
|
bitfld.long 0x04 21. " L1_ASPM_SUPPORT ,Link capability register L1 ASPM support" "Not supported,Supported"
|
|
bitfld.long 0x04 20. " L23_READY_NO_D3 ,L23 ready no D3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACK_L1_NO_WAIT ,ACK L1 no wait" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 10.--18. 1. " ACK_TIMER_LIMIT ,Overrides the Ack timer limit for this root port"
|
|
textline " "
|
|
bitfld.long 0x04 8. " RNCTRL_GEN2_WAIT_FOR_FIRST_EIES ,RNCTRL GEN2 wait for first EIES" "Disabled,Enabled"
|
|
rbitfld.long 0x04 7. " RNCTRL_EN ,Dynamic link width re-negotiation procedure in XP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " GEN2_LINK_UPGRADE ,Selects the 2.0-compliant link width upgrade protocol" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--5. " RNCTRL_MAXWIDTH ,Maximum link width required at the end of dynamic link width renegotiation process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "VEND_XP2,Vendor XP Register 2 (NVIDIA's Implementation)"
|
|
hexmask.long.byte 0x08 24.--31. 1. " L0S_UPDATE_WAKE ,L0S update wake"
|
|
hexmask.long.word 0x08 8.--17. 1. " L0S_THRESHOLD ,Controls the idle time required for TxL0s entry from L0"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " L0S_ACK_WAKE ,L0S ACK wake"
|
|
sif (cpuis("TEGRAX1"))
|
|
group.long 0xF0C++0x03
|
|
line.long 0x00 "VEND_XV_TIMEOUT,Fields unique to NVIDIA's implementation of PCI Express devices"
|
|
hexmask.long.word 0x00 20.--31. 1. " N100MS_DFPCI ,N100MS_DFPCI"
|
|
hexmask.long.word 0x00 0.--9. 1. " MICROSECOND ,MICROSECOND"
|
|
elif (cpuis("TEGRAX2"))
|
|
group.long 0xF0C++0x03
|
|
line.long 0x00 "VEND_XV_TIMEOUT,Vendor XV Timeout Register (NVIDIA's Implementation)"
|
|
hexmask.long.word 0x00 20.--31. 1. " 100MS_DFPCI ,Number of Dfpci_clk clocks in a given 100ms interval"
|
|
hexmask.long.word 0x00 0.--9. 1. " MICROSECOND ,Various timers required by PCI-express specification"
|
|
group.long 0xF14++0x07
|
|
line.long 0x00 "VEND_XV_CMN,Vendor XV CMN Register (NVIDIA's Implementation)"
|
|
bitfld.long 0x00 29.--31. " ISO2TC_MAP ,TC to be used for FPCI ISO transactions" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "VEND_THERM_MGMT,Vendor THERM MGMT"
|
|
hexmask.long.word 0x04 4.--15. 1. " PERIOD ,Defines period (in microseconds) for the purpose of throttling"
|
|
bitfld.long 0x04 1.--3. " DUTY_CYCLE ,Defines fraction of PERIOD throttling is applied" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Enables throttling of PCIe traffic" "Disabled,Enabled"
|
|
else
|
|
group.long 0xF0C++0x03
|
|
line.long 0x00 "VEND_XV_TIMEOUT,Fields unique to NVIDIA's implementation of PCI Express devices"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " VEND_XV_TIMEOUT ,VEND_XV_TIMEOUT"
|
|
endif
|
|
group.long 0xF20++0x03
|
|
line.long 0x00 "VEND_SLOT_STRAP,Vendor Slot Capabilities Register"
|
|
sif (cpuis("TEGRAX2"))
|
|
hexmask.long.word 0x00 19.--31. 1. " PHYSICAL_SLOT_NUMBER ,Physical slot number"
|
|
bitfld.long 0x00 18. " NO_CMD_COMPLETED_SUPPORT ,No CMD completed support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ELECTROMECH_INTERLOCK_PRESENT ,Electromechanical interlock present" "Not present,Present"
|
|
bitfld.long 0x00 15.--16. " SLOT_POWER_LIMIT_SCALE ,Slot power limit scale" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 7.--14. 1. " SLOT_POWER_LIMIT_VALUE ,Slot power limit value"
|
|
bitfld.long 0x00 6. " HOT_PLUG_CAPABLE ,Supporting hot-plug operations" "Not capable,Capable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HOT_PLUG_SURPRISE ,Hot-plug surprise" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " POWER_INDICATOR_PRESENT ,Power indicator" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ATTENTION_INDICATOR_PRESENT ,Attention Indicator" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. " MRL_SENSOR_PRESENT ,MRL Sensor" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 1. " POWER_CONTROLLER_PRESENT ,Power Controller" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " ATTENTION_BUTTON_PRESENT ,Attention Button" "Not implemented,Implemented"
|
|
else
|
|
hexmask.long.word 0x00 19.--31. 1. " PHYSICAL_SLOT_NUMBER ,Physical slot number"
|
|
bitfld.long 0x00 15.--16. " SLOT_POWER_LIMIT_SCALE ,Slot power limit scale" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 7.--14. 1. " SLOT_POWER_LIMIT_VALUE ,Slot power limit value"
|
|
endif
|
|
sif (cpuis("TEGRAX1"))
|
|
group.long 0xF30++0x03
|
|
line.long 0x00 "RP_XP_REF,This register contains diagnostic bits used in XP"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " CPL_TO_CUSTOM_VALUE ,User-specified value to use for completion timeout"
|
|
bitfld.long 0x00 13. " CPL_TO_OVERRIDE ,Enables the user override mode for completion timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ADVANCE_BY_2_CYA ,ADVANCE_BY_2_CYA" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " NAK_SCHEDULE_CYA ,NAK_SCHEDULE_CYA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RXL2LINK_NPT_EMPTY_CYA ,RXL2LINK_NPT_EMPTY_CYA" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " L2_READ_FIX_EN ,L2_READ_FIX_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MICROSECOND_ENABLE ,MICROSECOND_ENABLE" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MICROSECOND_LIMIT ,MICROSECOND_LIMIT"
|
|
elif (cpuis("TEGRAX2"))
|
|
group.long 0xF30++0x03
|
|
line.long 0x00 "RP_XP_REF,RP XP Reference Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " CPL_TO_CUSTOM_VALUE ,User-specified value to use for completion timeout"
|
|
bitfld.long 0x00 13. " CPL_TO_OVERRIDE ,Enables the user override mode for completion timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ADVANCE_BY_2_CYA ,Advanced by 2 CYA" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " NAK_SCHEDULE_CYA ,NAK schedule CYA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RXL2LINK_NPT_EMPTY_CYA ,RXL2LINK NPT empty CYA" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " L2_READ_FIX_EN ,L2 read fix enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MICROSECOND_ENABLE ,Microsecond enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MICROSECOND_LIMIT ,Counter value to be used to reset the one microsecond counter used for update FC scheduling"
|
|
group.long 0xF44++0x03
|
|
line.long 0x00 "VEND_CYA0,Vendor CYA0 Register"
|
|
bitfld.long 0x00 30. " FORCE_RETRY_POSSIBLE ,Force retry possible" "No,Yes"
|
|
bitfld.long 0x00 29. " UP_NC2C ,Forces all upstream non-coherent traffic to coherent" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DROP_VDM_TYPE1 ,VDM messages with vendor ID other than NVIDIA drop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " DROP_NV_VDM_TYPE1 ,VDM messages with vendor ID NVIDIA(0x10DE) drop enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " REL_CRDT_4PKT_DRP_RXL ,Credits for the VDM packet dropped release enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " LTR_EN ,Hide LTR capability enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ALLOW_ALL_DS_RO ,Allow all DS RO" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NATIVE_P2P_STARVE_COUNT ,Native P2P starve count"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DSK_RESET_PULSE_WIDTH ,Number of symbol times Deskewer should hold RX fifos in hot_reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. " FINISH_PKT_ON_RCVRY_EN ,Finish packet on recovery enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " UR_PW_DROP_ALL_MODE ,UR PW drop all mode" "No,Yes"
|
|
bitfld.long 0x00 9. " DROP_ALL_MODE ,Drop all mode" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " MAX_PAYLOAD_SIZE ,Max payload size" "INIT,,,,,4KB,,Auto"
|
|
bitfld.long 0x00 5. " ADR64 ,64-bit addressing mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IGNORE_BME ,Ignores BMS and accepts upstream PCIe transactions" "Not ignored,Ignored"
|
|
bitfld.long 0x00 3. " UFPCI_BLOCK_B2B_NP ,UFPCI block back-to-back NP" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " GPU_NISONC2HPISO ,GPU NISONC2HPISO" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PASSPW_RO ,PASSPW RO" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " REL_CREDIT_UR_PW ,Credits for the ur_pw received release" "No,Yes"
|
|
else
|
|
group.long 0xF34++0x0F
|
|
line.long 0x00 "ECTL_2_R1,ECTL_2_R1"
|
|
hexmask.long.word 0x00 16.--31. 1. " RX_DFE_1C ,RX_DFE_1C"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RX_EQ_1C ,RX_EQ_1C"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CDR_CNTL_1C ,CDR_CNTL_1C"
|
|
line.long 0x04 "ECTL_3_R1,ECTL_3_R1"
|
|
bitfld.long 0x04 8.--11. " TX_PEAK_PRE_1C ,TX_PEAK_PRE_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--4. " TX_PEAK_1C ,TX_PEAK_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "ECTL_2_R2,ECTL_2_R2"
|
|
hexmask.long.word 0x08 16.--31. 1. " RX_DFE_1C ,RX_DFE_1C"
|
|
hexmask.long.word 0x08 0.--15. 1. " RX_EQ_1C ,RX_EQ_1C"
|
|
line.long 0x0C "ECTL_3_R2,ECTL_3_R2"
|
|
bitfld.long 0x0C 24.--27. " PRE_SEL1_1C ,PRE_SEL1_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 16.--20. " SEL1_1C ,SEL1_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--11. " PRE_SEL0_1C ,PRE_SEL0_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--4. " SEL0_1C ,SEL0_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.long 0xF48++0x07
|
|
line.long 0x00 "VEND_CTL1,Vendor Control Register 1 (NVIDIA's Implementation)"
|
|
bitfld.long 0x00 21. " POLLING_RESET_FIX_EN ,Polling reset fix enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " HOTPLUG_IN_TRAFFIC_EN ,Hotplug in traffic enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NISO2ISO ,All upstream non-ISO-PW and non-ISO-NP will be upgraded to ISO" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ALLOW_UPSTREAM_CMPL_OVERTAKE_PW ,UBFI allows CPL bypass PW regardless of RO bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPLIT_ARB_BLOCK_COH ,Split ARB block coherent" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " HIDE_MSIMAP ,Hide MSIMAP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LINKACTV_REPORTING ,Setting the data link layer link active reporting capable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P2P_ISO2NIS ,Forces upstream peer-to-peer ISO requests to be peer-to-peer NONISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERPT ,ERPT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " HIDE_MSI_CAP ,Hides the entire MSI capability structure from the capabilities list" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ACCEPT_MSGD1 ,Allows acceptance of NVIDIA specific vendor type message with data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--3. " TC2ISO_MAP ,TC2ISO MAP" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P2P_BLOCK_P2P_ONLY ,P2P block P2P only" "Disabled,Enabled"
|
|
line.long 0x04 "VEND_XP_BIST,IOBIST And Characterization Control Register (NVIDIA's Implementation)"
|
|
bitfld.long 0x04 30. " GOTO_DETECT_ON_SURPRISE_EIDLE ,Goto detect on surprise EIDLE" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " ENABLE_SERR_REPORTING ,Enable SERR reporting" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " GOTO_L1_L2_AFTER_DLLP_DONE ,Goto L1 L2 after DLLP done" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " CTRL_IGNORE_LPBK_EXIT ,Control ignore LPBK exit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 26. " CTRL_RELAX_LPBK_ENTRY ,Control relax LPBK entry" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " CTRL_FORCE_PRBS_RST ,Control force PRBS reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24. " FORCE_DEEMPHASIS_ADVERTISED_EN ,Force Deemphasis advertised enable" "Disabled,Enabled"
|
|
sif (cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x04 23. " POWER_UP_BYPASS ,Power up bypass" "No bypass,Bypass"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 22. " FORCE_RECEIVER_COMPLIANCE_EN ,Force reciver compliance enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " FORCE_COMPLIANCE_GEN2_SPEED_EN ,Force compliance GEN2 speed enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " FORCE_COMPLIANCE_AND_ADVERTISE_MODE ,Force compliance and advertise mode" "Disabled,Enabled"
|
|
sif (cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x04 19. " PRESERVE_TX_PACKET_DURING_SPEED_CHANGE ,Preserve TX packet during speed change" "Not preserved,Preserved"
|
|
bitfld.long 0x04 18. " GEN2_EXIT_USE_STAT_IDLE ,GEN2 exit use status idle" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GEN2_LOOPBACK ,GEN2 loopback" "0,1"
|
|
bitfld.long 0x04 16. " SA_EXTRA_RESET_EN_RANGE ,SA extra reset enable range" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 6.--15. 1. " CTRL_TX_PTRN_RANGE ,Control TX PTRN range"
|
|
bitfld.long 0x04 4.--5. " TEST_MODE_RANGE ,Test mode range" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 3. " NOSCRAMBLE_RANGE ,No scramble range" "0,1"
|
|
bitfld.long 0x04 2. " EIDLE_DATA_RANGE ,EIDLE data range" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 1. " EIDLE_OVERRIDE_RANGE ,EIDLE override range" "0,1"
|
|
bitfld.long 0x04 0. " RDET_BYPASS_RANGE ,RDET bypass range" "0,1"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
width 22.
|
|
group.long 0xF50++0x03
|
|
line.long 0x00 "VEND_XP_PAD_PWRDN,Vendor XP PAD Powerdown (NVIDIA's Implementation)"
|
|
bitfld.long 0x00 31. " IDLE_MODE_L1_CLKREQ ,Idle mode L1 clock request" "0,1"
|
|
bitfld.long 0x00 30. " IDLE_MODE_DYNAMIC ,Idle mode dynamic" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " IDLE_MODE_L1 ,Idle mode L1" "0,1"
|
|
bitfld.long 0x00 28. " XVR_USE_DFPCI_DATA_UNINTR ,XVR use DFPCI data UNINTR" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 18.--27. 1. " MICROSECOND ,Various timers required by PCI-express specification"
|
|
bitfld.long 0x00 16.--17. " SLEEP_MODE_L1_CLKREQ ,Defines the 2-bit sleep-mode coding when clkreq is deasserted in L1" "L0,L1,L1P,L1PP"
|
|
textline " "
|
|
bitfld.long 0x00 15. " L1_CLKREQ ,Power down to SLEEP_MODE_L1_REQ enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " MINIMUM ,Minimum number of Gen1 xclks(4ns) that analog pads must remain powered down (or up) before the LTSSM attempts to power them back up/down again"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " SLEEP_MODE_DYNAMIC ,2-bit sleep-mode coding in the pad when the lane shut down due to dynamic link downsizing" "L0,L1,L1P,L1PP"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SLEEP_MODE_L1 ,2-bit sleep-mode coding in the pad when LTSSM is in the L1 state or DISABLED state" "L0,L1,L1P,L1PP"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DISABLED ,Enable analog pads to power down in the DISABLED_DOWN state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DYNAMIC ,Enable unused analog pads to power down after dynamic link width re-negotiation takes place" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " L1 ,Enable analog pads to power down when in L1 state" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
width 22.
|
|
group.long 0xF54++0x07
|
|
line.long 0x00 "VEND_XP_FTS,Vendor XP FTS (NVIDIA's Implementation)"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TS_DETECT_START ,TS detect start"
|
|
hexmask.long.byte 0x00 16.--23. 1. " FTS_DETECT_START ,Number of symbol times we wait before the root port begins looking at FTS ordered sets when exiting L0s"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " N_FTS_REMOTE ,N_FTS value advertised by the remote device"
|
|
hexmask.long.byte 0x00 0.--7. 1. " N_FTS ,N_FTS value that we advertise to the device on the other side of the link"
|
|
line.long 0x04 "VEND_XP_STATS0,Vendor XP States Register 0"
|
|
bitfld.long 0x04 28. " FAILED_L0S_EXITS_INF ,Failed L0s exit counter accumulates indefinitely" "No,Yes"
|
|
eventfld.long 0x04 24. " FAILED_L0S_EXITS_LC ,Failed L0S exits LC" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 20. " NAKS_RCVD_INF ,NAKs received counter accumulates indefinitely" "No,Yes"
|
|
eventfld.long 0x04 16. " NAKS_RCVD_LC ,NAKS received LC" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 12. " CRC_ERRORS_INF ,CRC error counter accumulates indefinitely" "No,Yes"
|
|
eventfld.long 0x04 8. " CRC_ERRORS_LC ,Current value from the CRC error counter" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 4. " 8B10B_ERRORS_INF ,8b/10b error counter accumulates indefinitely" "No,Yes"
|
|
eventfld.long 0x04 0. " 8B10B_ERRORS_LC ,Current value from the 8b/10b error counter" "No effect,Clear"
|
|
rgroup.long 0xF5C++0x07
|
|
line.long 0x00 "VEND_XP_STATS1,Vendor XP States Register 1"
|
|
sif (cpuis("TEGRAX2"))
|
|
hexmask.long.byte 0x00 24.--31. 1. " FAILED_L0S_EXITS ,Counts the number of times the RX side of the XP went into Recovery in one millisecond"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NAKS_RCVD ,Counts the number of NAKs received from the endpoint in 64 microseconds"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CRC_ERRORS ,Counts the number of CRC errors detected in 64 microseconds"
|
|
hexmask.long.byte 0x00 0.--7. 1. " 8B10B_ERRORS ,Counts the number of 8b/10b errors detected in one microsecond"
|
|
else
|
|
hexmask.long.byte 0x00 24.--31. 1. " 8B10B_ERRORS ,Counts the number of 8b/10b errors detected in one microsecond"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CRC_ERRORS ,Counts the number of CRC errors detected in 64 microseconds"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " NAKS_RCVD ,Counts the number of NAKs received from the endpoint in 64 microseconds"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FAILED_L0S_EXITS ,Counts the number of times the RX side of the XP went into Recovery in one millisecond"
|
|
endif
|
|
line.long 0x04 "VEND_ERROR_COUNT,Vendor Error Count Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " REPLAY ,Counts number of times TXBA replays"
|
|
hexmask.long.byte 0x04 8.--15. 1. " BAD_TLP ,Counts bad tlps reported by RXL"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " LCRC_ERR ,Counts LCRCL Errors reported by RXL"
|
|
textline " "
|
|
width 28.
|
|
group.long 0xF64++0x0B
|
|
line.long 0x00 "CFG_MISC,Config Miscellaneous Register (NVIDIA's Implementation)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MUTE_IDLE ,Mute idle"
|
|
line.long 0x04 "PRIV_XP_INIT_RECOVERY,Private XP Initialize Recovery Register (NVIDIA's Implementation)"
|
|
bitfld.long 0x04 31. " 8B10B_ERROR_ENABLE ,8B10B feature enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 20.--30. 1. " 8B10B_ERROR_WINDOW ,CPrograms the time frame in multiples of 1 microsecond"
|
|
textline " "
|
|
hexmask.long.tbyte 0x04 0.--19. 1. " 8B10B_ERROR_THRESHOLD ,Programs the 8b10b error threshold"
|
|
line.long 0x08 "PRIV_XP_LCTRL_2,Private XP LCTRL (NVIDIA's Implementation)"
|
|
rbitfld.long 0x08 31. " UPCONFIGURE_CAPABLE ,Gen2 link width up-configure capability" "Not capable,Capable"
|
|
bitfld.long 0x08 30. " REV2P0_COMPLIANCE_DIS ,Disable advertising rev2.0 support and link width up-configure capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " EIDLE_INFERENCE_EN ,Disable electrical idle inference" "No,Yes"
|
|
bitfld.long 0x08 28. " SURPRISE_IDLE_USE_STAT_IDLE ,Surprise idle use status idle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " ALLOW_SPEED_CHANGE_FROM_L1 ,Allow speed change to be initiated from the L1 or Rx_L0s link states" "Disabled,Enabled"
|
|
bitfld.long 0x08 24.--26. " RECOVERY_SPEED_TIMEOUT_ADJ ,Adjust minimum length of time the transmitter stays in idle in the Recover Sped state" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 20.--23. " N_EIE_SYMBOLS ,Number of K28.7 symbols" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 19. " DEEMPHASIS_STRAP ,DEEMPHASIS_STRAP" "-6db,-3.5db"
|
|
textline " "
|
|
bitfld.long 0x08 18. " ENFORCE_DEEMPHASIS ,Forces root port to use de-emphasis value" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " POLLING_PREDETERMINED_LANES ,Polling predetermined lanes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " AUTONOMOUS_CHANGE ,Autonomous change" "No,Yes"
|
|
rbitfld.long 0x08 12.--15. " DATA_RATE_SUPPORTED_REMOTE ,Gen2 data rate supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " DATA_RATE_SUPPORTED ,Supported link speed reported in the link capabilities" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 4.--7. " TARGET_LINK_SPEED ,Specifies the link rate to change to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 3. " TX_MARGIN_OVERRIDE ,TX_MARGIN_OVERRIDE" "Disabled,Enabled"
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x08 2. " CYA_DEEMPHASIS_OVERRIDE ,CYA deemphasis override" "No override,Override"
|
|
endif
|
|
bitfld.long 0x08 1. " ADVERTISED_RATE_CHANGE ,ADVERTISED_RATE_CHANGE" "No effect,Change"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SPEED_CHANGE ,Link speed negotiation procedure" "No effect,Change"
|
|
group.long 0xF74++0x03
|
|
line.long 0x00 "PRIV_XP_PAD_PWRUP,Private XP PAD_Powerup"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PMRX_PWRUP_THRESHOLD ,Time to hold CDR at reset in Recovery"
|
|
sif (cpuis("TEGRAX2"))
|
|
group.long 0xF78++0x03
|
|
line.long 0x00 "PRIV_XP_PAD_GEN2_PAD_PWRDN,Private XP PAD GEN2 PAD Powerdown"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MICROSECOND ,Number of xclks in 1 microsecond when running at gen2 speed"
|
|
endif
|
|
group.long 0xF84++0x03
|
|
line.long 0x00 "PRIV_XP_RECOVERY_REASONS,Register Records The Reasons We Went Into Recovery"
|
|
textline " "
|
|
width 30.
|
|
sif (cpuis("TEGRAX2"))
|
|
rgroup.long 0xF88++0x07
|
|
line.long 0x00 "PRIV_XP_RECOVERY_COUNT,Number Of RECOVERY STATE Entries In XP By The XVR"
|
|
line.long 0x04 "PRIV_XP_L0S_ENTRY_COUNT,Number Of Entries From L0 To L0s At ltssm Side"
|
|
rgroup.long 0xF94++0x0B
|
|
line.long 0x00 "PRIV_XP_L1_ENTRY_COUNT,Number Of Entries From L0 To L1 It Is Reset Whenever It Is Read"
|
|
line.long 0x04 "PRIV_XP_L1_TO_RECOVERY_COUNT,Number Of Entries From L1 To Recovery"
|
|
line.long 0x08 "PRIV_XP_L0_TO_RECOVERY_COUNT,Number Of Entries From L0 To Recovery"
|
|
bitfld.long 0x08 8. " REASON ,Reason" "All,Error"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " VALUE ,Value"
|
|
else
|
|
rgroup.long 0xF88++0x13
|
|
line.long 0x00 "PRIV_XP_RECOVERY_COUNT,Number of RECOVERY STATE entries in XP by the XVR"
|
|
line.long 0x04 "PRIV_XP_RX_L0S_ENTRY_COUNT,Number of entries from L0 to L0s at ltssm RX side"
|
|
line.long 0x08 "PRIV_XP_TX_L0S_ENTRY_COUNT,Number of entries from L0 to L0s at ltssm TX side"
|
|
line.long 0x0C "PRIV_XP_L1_ENTRY_COUNT,Number of entries from L0 to L1 It is reset whenever it is read"
|
|
line.long 0x10 "PRIV_XP_L1_TO_RECOVERY_COUNT,Number of entries from L1 to Recovery"
|
|
group.long 0xF9C++0x03
|
|
line.long 0x00 "PRIV_XP_L0_TO_RECOVERY_COUNT,Number of entries from L0 to Recovery"
|
|
bitfld.long 0x00 8. " REASON ,REASON" "All,Error"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,VALUE"
|
|
endif
|
|
rgroup.long 0xFA0++0x07
|
|
line.long 0x00 "PRIV_XP_L1P_ENTRY_COUNT,Number Of Entries From L0 To Deep L1"
|
|
line.long 0x04 "PRIV_XP_ASLM_COUNT,Number Of Switching Between X1 And X16 for Gen2 Only"
|
|
group.long 0xFA8++0x07
|
|
line.long 0x00 "VEND_CTL2,Vendor Control Register (Miscellaneous)"
|
|
bitfld.long 0x00 24. " COMPLIANCE_X8_DELAY ,CTL for compliance delay pattern" "Wrap on n-1,Wrap on 8/16 mod 8"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IGNORE_ATTENTION_BUTTON_MSG ,Ignore upstream attention button" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 22. " UNBLOCK_UP_TRANSACTIONS ,Unblock up transaction" "Blocked,Unblocked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " BLOCK_UP_TRANSACTIONS_ON_ERR ,Block all upstream transaction after an error" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " HW_AUTO_WIDTH_DISABLE_DIS ,HW auto width disable disable" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 19. " BW_MANAGEMENT_INT_EN_DIS ,BW management INT enable disable" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 18. " AUTO_BANDWIDTH_INT_EN_DIS ,Auto bandwidth INT enable disable" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 17. " AUTO_BANDWIDTH_DIS ,Auto bandwidth disable" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BW_MANAGEMENT_DIS ,BW management disable" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SHADOW_LINK_BW_NOTIFY_CAP ,Shadow link BW notify capable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 12. " GEN2_PROTOCOL_DISABLE ,GEN2 protocol disable" "No,Yes"
|
|
else
|
|
rbitfld.long 0x00 12. " GEN2_PROTOCOL_DISABLE ,GEN2 protocol disable" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " SLOT_IMPLEMENTED ,Slot implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
eventfld.long 0x00 9. " ERR_STS_HOTPLUG_PME ,Error STS hotplug PME" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " ERR_STS_HOTPLUG_NMI ,Error STS hotplug NMI" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PCA_ENABLE ,Enable/disable the PCA in any TMS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GEN2_SPEED_DISABLE ,Gen 2 protocol speed disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GEN2_PROTOCOL_DISABLE ,Disable gen2 protocol and will force the use of Gen 1.1 protocol" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DEV_CAP_EXTENDED_TAG_FIELD_SIZE ,DEV capable extended tag field size" "5bit,8bit"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIS_MA_TA_EP_MERGE ,Disables the logic which takes care of merging of EP/MA/TA" "No,Yes"
|
|
line.long 0x04 "PRIV_XP_CONFIG,Private XP Config"
|
|
bitfld.long 0x04 0.--1. " LOW_PWR_DURATION ,information logging for the health and performance counters" "TX_L0S,RX_L0S,L1,Idle"
|
|
textline " "
|
|
width 35.
|
|
rgroup.long 0xFB0++0x03
|
|
line.long 0x00 "PRIV_XP_DURATION_IN_LOW_PWR_100NS,Counts The Duration In Multiples Of 100ns For The Type Of Low Power Information"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
rgroup.long 0xFB4++0x03
|
|
line.long 0x00 "PRIV_XP_SKP_TIMEOUT,Counts The Duration In Multiples Of 100ns For The Type Of Low Power Information"
|
|
hexmask.long.word 0x00 13.--25. 1. " THRESHOLD_GEN2 ,Threshold GEN2"
|
|
hexmask.long.word 0x00 0.--12. 1. " THRESHOLD ,Threshold"
|
|
else
|
|
group.long 0xFB4++0x03
|
|
line.long 0x00 "PRIV_XP_SKP_TIMEOUT,Counts The Duration In Multiples Of 100ns For The Type Of Low Power Information"
|
|
hexmask.long.word 0x00 13.--25. 1. " THRESHOLD_GEN2 ,Threshold GEN2"
|
|
hexmask.long.word 0x00 0.--12. 1. " THRESHOLD ,Threshold"
|
|
endif
|
|
textline " "
|
|
group.long 0xFB8++0x03
|
|
line.long 0x00 "PRIV_XP_EIDLE_INFERENCE_TIMEOUT,Counts The Duration In Multiples Of 100ns For The Type Of Low Power Information"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIMEOUT_B ,UI window for electrical idle exit not detected in the Recover"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMEOUT_A ,UI window for COM not detected in the Recovery"
|
|
textline " "
|
|
width 25.
|
|
sif (cpuis("TEGRAX2"))
|
|
group.long 0xFBC++0x03
|
|
line.long 0x00 "SLOT_CONTROL_STATUS_HPC,Slot Control Status HPC Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " COMMAND ,Command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " STATE ,State"
|
|
textline " "
|
|
eventfld.long 0x00 7. " STATE_CHANGE7 ,State change 7" "Not changed,Changed"
|
|
eventfld.long 0x00 6. " STATE_CHANGE6 ,State change 6" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 5. " STATE_CHANGE5 ,State change 5" "Not changed,Changed"
|
|
eventfld.long 0x00 4. " STATE_CHANGE4 ,State change 4" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STATE_CHANGE3 ,State change 3" "Not changed,Changed"
|
|
eventfld.long 0x00 2. " STATE_CHANGE2 ,State change 2" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 1. " STATE_CHANGE1 ,State change 1" "Not changed,Changed"
|
|
eventfld.long 0x00 0. " STATE_CHANGE0 ,State change 0" "Not changed,Changed"
|
|
group.long 0xFC4++0x07
|
|
line.long 0x00 "VEND_XP_LANEMAP1,Vendor XP Lane MAP 1"
|
|
bitfld.long 0x00 28.--31. " LANE_15 ,Lane 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " LANE_14 ,Lane 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " LANE_13 ,Lane 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " LANE_12 ,Lane 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " LANE_11 ,Lane 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " LANE_10 ,Lane 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " LANE_9 ,Lane 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " LANE_8 ,Lane 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "VEND_SS_1,Shadow Register Of SS 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " SSID ,SSID"
|
|
hexmask.long.word 0x04 0.--15. 1. " SSVID ,SSVID"
|
|
endif
|
|
sif (!cpuis("TEGRAX2"))
|
|
group.long 0xFC8++0x0B
|
|
line.long 0x00 "VEND_SHADOW,Shadow register of SS_1"
|
|
hexmask.long.word 0x00 16.--31. 1. " SS_1_SSID ,SS_1_SSID"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " SS_1_SSVID ,SS_1_SSVID"
|
|
line.long 0x04 "TX_MARGIN_MAP0_TX_AMP,Mapping of the Transmit Margin field in the Link Control 2 register"
|
|
bitfld.long 0x04 30.--31. " CTL ,CTL" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 24.--29. " CODE3 ,CODE3" "Init,,,,,,,,Mobile,,,,,,,,,,,,Desktop,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--21. " CODE2 ,CODE2" "Init,,,,,,,,,,Mobile,,,,,,,,,,,,,,Desktop,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--13. " CODE1 ,CODE1" "Init,,,,,,,,,,,,Mobile,,,,,,,,,,,,,,,,Desktop,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--5. " CODE0 ,CODE0" "Init,,,,,,,,,,,,Mobile,,,,,,,,,,,,,,,,,,,,Desktop,?..."
|
|
line.long 0x08 "TX_MARGIN_MAP1_TX_AMP,Mapping of the Transmit Margin field in the Link Control 2 register"
|
|
bitfld.long 0x08 30.--31. " CTL ,CTL" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 24.--29. " CODE7 ,CODE7" "Mobile,,,,Desktop,?..."
|
|
textline " "
|
|
bitfld.long 0x08 16.--21. " CODE6 ,CODE6" "Init,,Mobile,,,,,,Desktop,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--13. " CODE5 ,CODE5" "Init,,,,Mobile,,,,,,,,Desktop,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--5. " CODE4 ,CODE4" "Init,,,,,,Mobile,,,,,,,,,,Desktop,?..."
|
|
endif
|
|
textline " "
|
|
sif (cpuis("TEGRAK1"))
|
|
group.long 0xFD4++0x03
|
|
line.long 0x00 "ECTL_1_R1,ECTL_1_R1"
|
|
bitfld.long 0x00 28.--31. " TX_DRV_CNTL_1C ,TX_DRV_CNTL_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RX_QEYE_EN_1C ,RX_ QEYE_EN_1C" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " RX_WANDER_1C ,RX_WANDER_1C" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_TERM_CNTL_1C ,_RX_TERM_CNTL_1C" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_TERM_CNTL_1C ,TX_TERM_CNTL_1C" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TX_CMADJ_1C ,TX_CMADJ_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " TX_AMP_1C ,TX_AMP_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xFD8++0x03
|
|
line.long 0x00 "ECTL_1_R2,ECTL_1_R2"
|
|
bitfld.long 0x00 28.--31. " TX_DRV_CNTL_1C ,TX_DRV_CNTL_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RX_QEYE_EN_1C ,RX_ QEYE_EN_1C" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " RX_WANDER_1C ,RX_WANDER_1C" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_TERM_CNTL_1C ,_RX_TERM_CNTL_1C" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_TERM_CNTL_1C ,TX_TERM_CNTL_1C" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TX_CMADJ_1C ,TX_CMADJ_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " TX_AMP_1C ,TX_AMP_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xFDC++0x07
|
|
line.long 0x00 "TIMEOUT2,Timeout 2 Register"
|
|
bitfld.long 0x00 0.--4. " MIN_L1_L2_IDLE_TIME ,Sets minimum amount of time we stay in L1/L2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "PRIV_MISC,Private Miscellaneous Register"
|
|
bitfld.long 0x04 31. " TMS_CLK_CLAMP_ENABLE ,Enables per-TMS XCLK/XTXCLK clamping" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x04 24.--30. 1. " CLK_CLAMP_THRESHOLD ,Number of contiguous nbref_clks (25MHz) after clamping"
|
|
textline " "
|
|
bitfld.long 0x04 23. " CTLR_CLK_CLAMP_ENABLE ,Enables per-controller XCLK/XTXCLK clamping" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--22. 1. " CTLR_CLK_CLAMP_THRESHOLD ,Number of contiguous nbref_clks (12MHz) after clamping"
|
|
sif (cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x04 4. " USE_EXT_CLKREQ ,Use EXT CLKREQ" "Not used,Used"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " PRSNT_MAP ,PRSNT MAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpuis("TEGRAX2"))
|
|
group.long 0xFE4++0x03
|
|
line.long 0x00 "BIST_CTRL_2,BIST Control 2 Register"
|
|
bitfld.long 0x00 31. " OVERRIDE_JTAG ,Internal JTAG register override" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TX_CHAR_SPEED ,Speed of TXCHAR output" ",2.5Gbps,5.0Gbps,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " TXCHAR_MIN_EIDLE ,Force LTSSM to spend minimum time in E-idle" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TXCHAR_EIDLE_EXIT ,Transition from E-idle to compliance pattern" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXCHAR_EIDLE_ENTRY ,Transition from compliance pattern to E-idle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SHORT_LINK_TIMERS ,Shortened timers in LINK" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xFE8++0x03
|
|
line.long 0x00 "VEND_XP3,Symbol Alignment Error Handling Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SA_ERROR_LIMIT ,Specifies number of misaligned COM symbols"
|
|
group.long 0xFEC++0x03
|
|
line.long 0x00 "XP_CTL_1,Control Registers Used In XP"
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 31. " CYA_RP_INITIATED_WAKE_ON_TLP ,Initiated wake one TLP" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("TEGRAX1"))
|
|
bitfld.long 0x00 29.--30. " SPARE ,SPARE" "0,1,2,3"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 28.--30. " SPARE ,Spare" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " EXIT_L1_AT_CLKREQ_ASSERTION ,When set,ltssm will exit L1 when clkreq assertion happens" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " NEW_IOBIST_CTRL ,Enable control signals from iobist" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OLD_IOBIST_EN ,When set will enable old iobist,else it will enable new iobist" "New,Old"
|
|
textline " "
|
|
bitfld.long 0x00 19.--24. " EIOS_DEBOUNCE_TIMER ,Number of xclk for which rx_data_en signals need to be deasserted before asserting it again" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DISABLE_RX_LANE_AFTER_EIOS ,Disable rx_lane_en after EIOS is seen in any of the enabled lane during recovery" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ENABLE_DESKEW_FOR_SPDCH_NEGOTIATION ,LTSSM enable deskew in recovery" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BYPASS_CONFIG_PWRUP ,Bypass config powerup" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RESET_TS_CTRL_ON_ERROR ,Reset TS control on error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RX_EIDLE_EXIT_TIMER_IN_CONFIG ,RX EIDLE exit timer in config" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FORCE_RESET_IN_CONFIG ,Force reset in config" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LINK_RESIZE_PWRDN_CTL ,Link resize powerdown control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ALLOW_SPEED_CHANGE_FROM_L0S ,When set,LTSSM will initiate link speed/width/advertised rate change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PRESERVE_TX_PACKET_ON_DL_RETRAIN ,When set,LTSSM will wait for framer to be idle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PRESERVE_TX_PACKET_ON_RECOVERY ,Preserve TX packet on recovery" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PRESERVE_TX_PACKET_ON_WIDTH_CHANGE ,When set,LTSSM will wait for framer to be idle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PRESERVE_TX_PACKET_ON_SPEED_CHANGE ,When set,LTSSM will wait for framer to be idle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RESET_LANE_ENABLE_ORIG_IN_DETECT ,allow lane_enable_original to be reset in Detect state" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " IDLE_TO_L0_DELAY ,Number of clocks that the LTSSM will delay the transition from Recovery" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LWLO_HUNT_ON_BAD_TS1 ,LWLO HUNT on bad TS1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FORCE_SA_IN_CONFIG ,Enables symbol alignment" "Disabled,Enabled"
|
|
group.long 0xFF0++0x0F
|
|
line.long 0x00 "PRIV_XP_L1BEACON,Private XP L1 Beacon"
|
|
hexmask.long.byte 0x00 2.--9. 1. " N_EIE_SYMBOLS ,Number of EIE symbols sent in L1 Beacon Entry/Exist state"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX_BYP_CTRL ,TX bypass control" "Only L0,All Lanes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
line.long 0x04 "TIMEOUT3,Timeout 3 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " RX_L0S_IDLE_TIME_GEN2 ,Controls the amount of time LTSSM delays"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--23. 1. " RX_L0S_IDLE_TIME_GEN1 ,Controls the amount of time LTSSM delays"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " TX_L0S_IDLE_TIME ,Controls the minimum amount of time LTSSM stays in TX_L0S_IDLE state"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " RX_EIDLE_EXIT_DELAY ,Controls the amount of time the LTSSM delays" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " TX_EIDLE_EXIT_DELAY ,Controls the amount of time the LTSSM delays" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "RP_XP_CTL_2,XP Control 2 Register"
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
sif cpuis("TEGRAX2")
|
|
bitfld.long 0x08 24. " LOOPBACK_RATE_DEEMPH_CHECK_DIS ,Loopback rate deemph check disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 23. " RX_CAL_EN ,Hardware RX calibration in UPHY enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 22. " AUX_RX_IDLE_EN ,RX idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " OVERRIDE_AUX_RX_IDLE_EN ,Override for bit for AUX_RX_IDLE_EN enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " WAIT_FOR_LOCKDET_DURING_L1_EXIT ,Wait for lockdet during L1 exit" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x08 12.--19. 1. " ECO351987_HOLDOFF_CNTR_LIMIT ,Holdoff counter limit for counter that was added in ECO 351987"
|
|
textline " "
|
|
bitfld.long 0x08 11. " USE_QUALIFIED_TS_CTL_BITS ,Qualifies the training control bits in the transmitted TS1s/TS2s with the LTSSM state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " RELAXED_UNEXP_CPL_CHECK ,Relaxed unexpected completion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " LOOPBACK_FORCE_NOSCRAMBLE ,Loopback force nonscramble enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 8. " CONFIG_LINKSTART_REQUIRE_PAD_LANE_NUM ,Config link start require PAD lane num" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPBACK_EXIT_THRESHOLD ,Maximum amount of time spent in loopback"
|
|
line.long 0x0C "VEND_XP_STATS2,Vendor XP States (NVIDIAs Implementation)"
|
|
hexmask.long.word 0x0C 0.--15. 1. " 8B10B_ERR_LANEMASK ,Each bit represent the corresponding logical lane"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "PCIe Controller 1"
|
|
base ad:0x01001000
|
|
width 11.
|
|
tree "PCI Compatible Configuration Registers"
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DEV_ID,Device ID And Vendor ID Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DEVICE_ID ,Identify the particular device"
|
|
hexmask.long.word 0x00 0.--15. 1. " VENDOR_ID ,Identify manufacturer of the device"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DEV_CTRL,Command And Status Register"
|
|
eventfld.long 0x00 31. " DETECTED_PERR ,Primary side device receives a poisoned TLP" "Not active,Active"
|
|
eventfld.long 0x00 30. " SIGNALED_SERR ,ERR_FATAL or ERR_NONFATAL message from primary side device" "Not active,Active"
|
|
eventfld.long 0x00 29. " RECEIVED_MASTER ,Primary side requestor receives a completion with unsupported request completion status" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.long 0x00 28. " RECEIVED_TARGET ,Primary side requestor receives a completion with completer abort completion status" "Not aborted,Aborted"
|
|
eventfld.long 0x00 27. " SIGNALED_TARGET ,Primary side device completes a request using completer abort completion status" "Not aborted,Aborted"
|
|
eventfld.long 0x00 24. " MASTER_DATA_PERR ,Master data parity error bit" "Not active,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 20. " CAPLIST ,Device configuration space includes a capabilities list" "Not present,Present"
|
|
rbitfld.long 0x00 19. " INTR_STATUS ,INTx interrupt message is pending internally to the device" "Not active,Active"
|
|
bitfld.long 0x00 10. " INTR_DISABLE ,Ability of the device to generate INTx interrupt messages" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SERR ,SERR enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PERR ,Parity Error Response bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BUS_MASTER ,Ability of the root complex to issue memory and I/O read/write requests" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MEMORY_SPACE ,Respond to memory space accesses on the primary interface" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IO_SPACE ,Respond to I/O space accesses on the primary interface" "Disabled,Enabled"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "REV_CC,Revision ID And Class Code Registers"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " CLASS_CODE ,Generic function of the device"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REVISION_ID ,Device specific revision identifier"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MISC_1,MISC 1 Register"
|
|
rbitfld.long 0x00 23. " HEADER_TYPE1 ,Identifies a multi-function device" "Single function,Multi function"
|
|
hexmask.long.byte 0x00 16.--22. 1. " HEADER_TYPE0 ,Specifies the layout of bytes 10h through 3Fh"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CACHE_LINE_SIZE ,Cache line size"
|
|
group.long 0x18++0x1B
|
|
line.long 0x00 "BN_LT,Bus Number And Latency Timer Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SUB_BUS_NUMBER ,Subordinate bus number"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SEC_BUS_NUMBER ,The secondary bus number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRI_BUS_NUMBER ,The primary bus number"
|
|
line.long 0x04 "IO_BL_SS,I/O Base/Limit And Secondary Status Register"
|
|
eventfld.long 0x04 31. " DETECTED_PERR ,Secondary side device receives a poisoned TLP" "Not active,Active"
|
|
eventfld.long 0x04 30. " RECEIVED_SERR ,Secondary side device receives an ERR_FATAL or ERR_NONFATAL message" "Not active,Active"
|
|
eventfld.long 0x04 29. " RECEIVED_MASTER ,Secondary side device receives a completion with unsupported request completion status" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.long 0x04 28. " RECEIVED_TARGET ,Secondary side device receives a completion with completer abort completion status" "Not aborted,Aborted"
|
|
eventfld.long 0x04 27. " SIGNALED_TARGET ,Secondary side device completes a request using completer abort completion status" "Not aborted,Aborted"
|
|
eventfld.long 0x04 24. " MASTER_DATA_PERR ,Master data parity error bit" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " IO_LIMIT ,Corresponds to address bits AD[15:12] of the I/O limit" "0,256,512,,,,,,,,,,,,,64k"
|
|
rbitfld.long 0x04 8.--11. " IO_LIMIT_SUPPORT ,Identifies the I/O addressing support" "16,32,?..."
|
|
bitfld.long 0x04 4.--7. " IO_BASE ,Corresponds to address bits AD[15:12] of the I/O base address" "0,256,512,,,,,,,,,,,,,64k"
|
|
textline " "
|
|
rbitfld.long 0x04 0.--3. " IO_BASE_SUPPORT ,Identifies the I/O addressing support" "16,32,?..."
|
|
line.long 0x08 "MEM_BL,Memory Base And Memory Limit Register"
|
|
hexmask.long.word 0x08 20.--31. 0x10 " MEM_LIMIT ,Corresponds to address bits AD[31:20] of the memory-mapped I/O limit"
|
|
hexmask.long.word 0x08 4.--15. 0x10 " MEM_BASE ,Corresponds to address bits AD[31:20] of the memory-mapped I/O base address"
|
|
line.long 0x0C "PRE_BL,Prefetchable Memory Base/Limit Register"
|
|
hexmask.long.word 0x0C 20.--31. 0x10 " PREFETCH_MEM_LIMIT ,Corresponds to address bits AD[31:20] of the prefetchable memory limit"
|
|
rbitfld.long 0x0C 16.--19. " L64BIT ,Identifies the prefetchable memory addressing support" "Not supported,Supported,?..."
|
|
hexmask.long.word 0x0C 4.--15. 0x10 " PREFETCH_MEM_BASE ,corresponds to address bits AD[31:20] of the prefetchable memory base address"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " B64BIT ,Identifies the prefetchable memory addressing support" "Not supported,Supported,?..."
|
|
line.long 0x10 "PRE_BU32,Prefetchable Memory Base Upper 32 Bits Register"
|
|
line.long 0x14 "PRE_LU32,Prefetchable Memory Limit Upper 32 Bits Register"
|
|
line.long 0x18 "IO_BL_U16,I/O Base/Limit Upper 16 Bits Register"
|
|
hexmask.long.word 0x18 16.--31. 1. " LIMIT_UPPER_BITS ,specifies the upper 16 bits,corresponding to AD[31:16],of the 32-bit I/O limit"
|
|
hexmask.long.word 0x18 0.--15. 1. " BASE_UPPER_BITS ,specifies the upper 16 bits,corresponding to AD[31:16],of the 32-bit I/O base address"
|
|
rgroup.long 0x34++0x07
|
|
line.long 0x00 "CAP_PTR,Capabilities Pointer"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " CAP_PTR_CAP_PTR ,Offset into configuration space where the capabilities list begins"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "INTR_BCR,Interrupt Bridge Control Registers"
|
|
bitfld.long 0x00 22. " SB_RESET ,Triggers a hot reset on the corresponding PCI express port" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " VGA_16BITIO ,Full 16-bit decode of IO address range for VGA" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " VGA_ADDRESS ,P2P bridge will claim all of the legacy VGA addresses" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " ISA_ADDRESS ,Modifies the response by the bridge to ISA I/O addresses" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SERR_FORWARD ,Forwarding of ERR_COR/ERR_NONFATAL and ERR_FATAL from secondary to primary" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PERR_RESP ,Response to poisoned TLPs" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTR_PIN ,Contains the interrupt pin the device (or device function) uses"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTR_LINE ,Contains the interrupt routing information"
|
|
tree.end
|
|
tree "PCI Subsystem ID And Subsystem Vendor ID Capability Registers"
|
|
width 6.
|
|
rgroup.long 0x40++0x07
|
|
line.long 0x00 "SS_0,Subsystem ID/Vendor ID Capability Register 0"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NEXT_PTR ,Points to the next capabilities list item"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAP_ID ,Detect the presence of the SSID/SSVID registers in a PCI-to-PCI bridge"
|
|
line.long 0x04 "SS_1,Subsystem ID/Vendor ID Capability Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " SSID ,Identifies the particular add-in card or subsystem"
|
|
hexmask.long.word 0x04 0.--15. 1. " SSVID ,Identifies the manufacturer of the add-in card or subsystem"
|
|
tree.end
|
|
tree "PCI Power Management Capability Structure Registers"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "PM_0,Power Management Register 0"
|
|
bitfld.long 0x00 31. " D3_COLD_SUPPORT ,Power states in which the function may assert PME?..." "Not supported,Supported"
|
|
bitfld.long 0x00 30. " D3_HOT_SUPPORT ,Power states in which the function may assert PME?..." "Not supported,Supported"
|
|
bitfld.long 0x00 29. " D2_SUPPORT ,Power states in which the function may assert PME?..." "Not supported,Supported"
|
|
bitfld.long 0x00 28. " D1_SUPPORT ,Power states in which the function may assert PME?..." "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 27. " D0_SUPPORT ,Power states in which the function may assert PME?..." "Not supported,Supported"
|
|
bitfld.long 0x00 26. " D2_SUPPORT ,D2 power management state support" "Not supported,Supported"
|
|
bitfld.long 0x00 25. " D1_SUPPORT ,D1 power management state support" "Not supported,Supported"
|
|
bitfld.long 0x00 22.--24. " AUX_CURRENT ,3.3Vaux auxiliary current requirements for the PCI function" "0,55 mA,100 mA,160 mA,220 mA,270 mA,320 mA,375 mA"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DEV_SPEC_INIT ,Device specific initialization bit" "Not needed,Needed"
|
|
bitfld.long 0x00 16.--18. " PCIPM_REV ,Revision of the PCI power management interface specification" ",,Rev 1.1,Rev 1.2,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " NEXT_PTR ,Points to the next capabilities list item"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAP_ID ,Detect the presence of the power management capability registers in a PCI to PCI bridge"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PM_1,Power Management Register 1"
|
|
eventfld.long 0x00 15. " PME_STATUS ,Assert the PME# signal independent of the state of the PME_En bit" "Not active,Active"
|
|
bitfld.long 0x00 8. " PME ,Assert PME?..." "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " PWR_STATE ,Determine the current power state of a function and to set the function into a new power state" "D0,D1,D2,D3hot"
|
|
tree.end
|
|
tree "PCI MSI Capability Structure Registers"
|
|
width 16.
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "MSI_CTRL,MSI Control Registers"
|
|
rbitfld.long 0x00 23. " 64BIT_CAP ,Capability of generating a 64-bit message address" "Not capable,Capable"
|
|
bitfld.long 0x00 20.--22. " MULT_EN ,Number of allocated messages" "0,2,4,8,?..."
|
|
rbitfld.long 0x00 17.--19. " MULT_CAP ,Number of requested messages" "0,2,?..."
|
|
bitfld.long 0x00 16. " CTRL_MSI ,Permission to use message signaled interrupt to request service" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " NEXT_PTR ,Points to the next item in the capabilities list"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAP_ID ,Detect the presence of the Message Signaled Interrupt Capability registers in a PCI-to-PCI bridge"
|
|
line.long 0x04 "MSI_LOW_ADDR,MSI Message Lower Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " DWORD ,Bits 31:2 of the address"
|
|
line.long 0x08 "MSI_UPPER_ADDR,MSI Message Upper Address Register"
|
|
line.long 0x0C "MSI_DATA,MSI Message Data Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " DATA ,MSI message data"
|
|
tree.end
|
|
sif (cpuis("TEGRAX2"))
|
|
tree "PCI MSI Map Register"
|
|
group.long 0x60++0x0B
|
|
line.long 0x00 "MSI_MAP_0,MSI MAP Capability Register"
|
|
rbitfld.long 0x00 27.--31. " CAP_TYPE ,Capability type for MSI Mapping Capability block" ",,,,,,,,,,,,,,,,,,,,,CAP_TYPE_MSI,?..."
|
|
bitfld.long 0x00 16. " XLATE_ENABLE ,Global enable for MSI translation" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " CAP_PTR ,Pointer to the next capability in the list"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAP_ID ,Capability ID for HyperTransport technology devices"
|
|
line.long 0x04 "MSI_MAP_1,MSI MAP Lower Address Register"
|
|
hexmask.long.word 0x04 20.--31. 0x10 " ADDRESS_LOWER ,Lower [31:0] bit address field"
|
|
line.long 0x08 "MSI_MAP_2,MSI MAP Upper Address Register"
|
|
tree.end
|
|
endif
|
|
tree "PCI Express Capability Structure Registers"
|
|
width 26.
|
|
rgroup.long 0x80++0x07
|
|
line.long 0x00 "PCI_EXPRESS_CAPABILITY,PCI Express Capability List Register"
|
|
bitfld.long 0x00 25.--29. " INTERRUPT_MESSAGE_NUMBER ,PCI express capability interrupt message number " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SLOT_IMPLEMENTED ,PCI express capability slot implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " DEVICE_PORT_TYPE ,PCI express capability device port type" "PCI express endpoint device,Legacy PCI express endpoint device,,,Root port of PCI express root complex,Upstream port of PCI express switch,Downstream port of PCI express switch,PCI express to PCI/PCI-X bridge,PCI/PCI-X to PCI express bridge,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " VERSION ,PCI express capability version number" ",Version 1,Version 2,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " LIST_NEXT_CAPABILITY_PTR ,The offset to the next PCI capability structure"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " LIST_CAPABILITY_ID ,Indicates PCI express capability structure"
|
|
line.long 0x04 "DEVICE_CAPABILITY,Device Capabilities Register"
|
|
bitfld.long 0x04 26.--27. " CAPTURED_SLOT_POWER_LIMIT_SCALE ,Scale used for the slot power limit value" "1.0x,0.1x,0.01x,0.001x"
|
|
textline " "
|
|
hexmask.long.byte 0x04 18.--25. 1. " CAPTURED_SLOT_POWER_LIMIT_VALUE ,Specifies the upper limit on power supplied by slot"
|
|
textline " "
|
|
bitfld.long 0x04 15. " ROLE_BASED_ERR_REPORTING ,Device implements the functionality originally defined in the error reporting ECN" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x04 14. " POWER_INDICATOR_PRESENT ,Power indicator" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ATTENTION_INDICATOR_PRESENT ,Attention indicator" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x04 12. " ATTENTION_BUTTON_PRESENT ,Attention button" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x04 9.--11. " ENDPOINT_L1_ACCEPTABLE_LATENCY ,Acceptable latency due to the transition from L1 state to the L0 state" "<1 us,1 us - 2 us,2 us -4 us,4 us - 8 us,8 us - 16 us,16 us - 32 us,32 us-64 us,> 64 us"
|
|
textline " "
|
|
bitfld.long 0x04 6.--8. " ENDPOINT_L0S_ACCEPTABLE_LATENCY ,Acceptable total latency due to the transition from L1 state to the L0 state" "< 64 ns,64 ns - 128 ns,128 ns - 256 ns,256 ns - 512 ns,512 ns - 1. us,1 us - 2 us,2 us-4us,> 4 us"
|
|
textline " "
|
|
bitfld.long 0x04 5. " EXTENDED_TAG_FIELD_SIZE ,Maximum supported size of the tag field" "5-bit tag field,8-bit tag field"
|
|
textline " "
|
|
bitfld.long 0x04 3.--4. " PHANTOM_FUNCTIONS_SUPPORTED ,Phantom functions support" "No bits used,First MSB used,First two MSB used,Three bits"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " MAX_PAYLOAD_SIZE ,Maximum payload size" "128B,256B,512B,1024B,2048B,4096B,?..."
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "DEVICE_CONTROL_STATUS,Device Control/Status Registers"
|
|
rbitfld.long 0x00 21. " TRANSACTIONS_PENDING ,Transactions pending" "Completed,Pending"
|
|
textline " "
|
|
rbitfld.long 0x00 20. " AUX_POWER_DETECTED ,AUX power detected" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 19. " UNSUPP_REQUEST_DETECTED ,Unsupported request" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 18. " FATAL_ERROR_DETECTED ,Fatal error" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 17. " NON_FATAL_ERROR_DETECTED ,Non-fatal error" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CORR_ERROR_DETECTED ,Correctable errors" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " MAX_READ_REQUEST_SIZE ,Maximum read request size" "128B,256B,512B,1024B,2048B,4096B,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENABLE_NO_SNOOP ,No snoop bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " AUXILLARY_POWER_PM_ENABLE ,AUX power PM enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " PHANTOM_FUNCTIONS_ENABLE ,Phantom functions" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EXTENDED_TAG_FIELD_ENABLE ,8-bit tag field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " MAX_PAYLOAD_SIZE ,Maximum TLP payload size" "128B,256B,512B,1024B,2048B,4096B,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENABLE_RELAXED_ORDERING ,Relaxed ordering bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " UNSUPP_REQ_REPORTING_ENABLE ,Reporting of unsupported requests" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FATAL_ERROR_REPORTING_ENABLE ,Reporting of fatal errors" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NON_FATAL_ERROR_REPORTING_ENABLE ,Reporting of non-fatal errors" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CORR_ERROR_REPORTING_ENABLE ,Reporting of correctable errors" "Disabled,Enabled"
|
|
textline " "
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "LINK_CAPABILITIES,Link Capabilities Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PORT_NUMBER ,PCI express port number"
|
|
textline " "
|
|
bitfld.long 0x00 21. " BW_NOTIFY ,Bandwidth notify" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " LINKACTV_REPORTING ,Link active reporting" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SURPRISE_DOWN_ERPT_CAP ,Detecting and reporting a surprise down error condition" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CLOCK_PM ,Component tolerates the removal of any reference clock" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " L1_EXIT_LATENCY ,L1 exit latency" "< 1 us,1 us - 2 us,2 us - 4 us,4 us - 8 us,8 us - 16 us,16 us - 32 us,32 us - 64 us,> 64 us"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " L0S_EXIT_LATENCY ,L0s exit latency" "< 64 ns,64 ns - 128 ns,128 ns - 256 ns,256 ns - 512 ns,512 ns - 1 us,1 us - 2 us,2 us - 4us,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " ACTIVE_STATE_LINK_PM_SUPPORT ,Level of active state power management supported" ",L0s Entry,,L0s and L1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--9. " MAX_LINK_WIDTH ,Maximum width" ",x1,x2,,x4,,,,x8,,,,x12,,,,x16,,,,,,,,,,,,,,,,x32,?..."
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 0.--3. " MAX_LINK_SPEED ,Maximum Link speed" ",2.5 Gb/s Link,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " MAX_LINK_SPEED ,Maximum Link speed" ",2.5 Gb/s Link,5.0 Gb/s Link,?..."
|
|
endif
|
|
textline " "
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "LINK_CONTROL_STATUS,Link Control/Status Register"
|
|
eventfld.long 0x00 31. " AUTO_BANDWIDTH ,Auto bandwidth" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 30. " BW_MANAGEMENT ,Bandwidth management" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 29. " DL_LINK_ACTIVE ,Data link control and management state machine" "Not active,Active"
|
|
textline " "
|
|
rbitfld.long 0x00 28. " SLOT_CLOCK_CONFIG ,Component uses platform reference clock" "Platform clock,Independent"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " LINK_TRAINING ,Link training" "Completed,In progress"
|
|
textline " "
|
|
rbitfld.long 0x00 20.--25. " NEG_LINK_WIDTH ,Negotiated width" ",x1,x2,,x4,,,,x8,,,,x12,,,,x16,,,,,,,,,,,,,,,,x32,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16.--19. " LINK_SPEED ,Negotiated Link Speed" ",2.5 Gb/s,5.0 Gb/s,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " AUTO_BANDWIDTH_INT_EN ,Auto bandwidth interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BW_MANAGEMENT_INT_EN ,Bandwidth management interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HW_AUTO_WIDTH_DISABLE ,Hardware auto width disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " CLOCK_PM ,Clock PM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EXTENDED_SYNCH ,Forces extended transmission" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " COMMON_CLOCK_CONFIGURATION ,Common clock configuration" "Common reference clock,Asynchrous reference clock"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " RETRAIN_LINK ,Link retraining" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LINK_DISABLE ,Disabling the Link" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " READ_COMPLETION_BOUNDARY ,RCB support capabilities" "64 byte,128 byte"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ACTIVE_STATE_LINK_PM_CONTROL ,Level of active state PM supported" ",L0s Entry,,L0s and L1"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "SLOT_CAPABILITIES,Slot Capabilities Register"
|
|
hexmask.long.word 0x00 19.--31. 0x08 " PHYSICAL_SLOT_NUMBER ,Physical slot number attached to this port"
|
|
textline " "
|
|
bitfld.long 0x00 18. " NO_CMD_COMPLETED_SUPPORT ,Notification when an issued command is completed by the hot plug controller" "Supported,Not supported"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ELECTROMECHANICAL_INTERLOCK_PRESENT ,Electro mechanical interlock mechanism" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 15.--16. " SLOT_POWER_LIMIT_SCALE ,Scale used for the slot power limit value" "1.0x,0.1x,0.01x,0.001x"
|
|
textline " "
|
|
hexmask.long.byte 0x00 7.--14. 1. " SLOT_POWER_LIMIT_VALUE ,Upper limit on power supplied by slot"
|
|
textline " "
|
|
bitfld.long 0x00 6. " HOT_PLUG_CAPABLE ,Supporting Hot-plug operations" "Not capable,Capable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HOT_PLUG_SURPRISE ,Hot-plug surprise" "Not capable,Capable"
|
|
textline " "
|
|
bitfld.long 0x00 4. " POWER_INDICATOR_PRESENT ,Power indicator" "Not Implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ATTENTION_INDICATOR_PRESENT ,Attention indicator" "Not Implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MRL_SENSOR_PRESENT ,MRL sensor" "Not Implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 1. " POWER_CONTROLLER_PRESENT ,Power controller" "Not Implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ATTENTION_BUTTON_PRESENT ,Attention button" "Not Implemented,Implemented"
|
|
group.long 0x98++0x0B
|
|
line.long 0x00 "SLOT_CONTROL_STATUS,Slot Control/Status Register"
|
|
eventfld.long 0x00 24. " DL_LAYER_STATE_CHANGED ,Notification when Data Link Layer Active field is changed" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 23. " ELECTROMECHANICAL_INTERLOCK_STATE ,Electromechanical interlock" "Disengaged,Engaged"
|
|
textline " "
|
|
rbitfld.long 0x00 22. " PRESENCE_DETECT_STATE ,Presence of a card in the slot" "Slot empty,Card present"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " MRL_SENSOR_STATE ,MRL sensor status" "MRL Closed,MRL Open"
|
|
textline " "
|
|
eventfld.long 0x00 20. " COMMAND_COMPLETED ,Hot-plug controller completed an issued command" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 19. " PRESENCE_DETECT_CHANGED ,Presence Detect change" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 18. " MRL_SENSOR_CHANGED ,MRL Sensor state change" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 17. " POWER_FAULT_DETECTED ,Power fault" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ATTN_BUTTON_PRESSED ,Attention button" "Not pressed,Pressed"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DL_LAYER_STATE_CHANGED_ENABLE ,Data Link Layer Link Active field" "Not changed,Changed"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ELECTROMECHANICAL_INTERLOCK_CONTROL ,Electromechanical interlock mechanism" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 10. " POWER_CONTROLLER_CONTROL ,Power state of the slot" "Power on,Power off"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " POWER_INDICATOR_CONTROL ,Current state of the Power Indicator" ",On,Blink,Off"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " ATTN_INDICATOR_CONTROL ,Current state of the Attention Indicator" ",On,Blink,Off"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HOT_PLUG_INTERRUPT_ENABLE ,Generation of hot plug interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " COMMAND_COMPLETED_INTERRUPT_ENABLE ,Generation of hot plug interrupt when a command is completed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PRESENCE_DETECT_CHANGED_ENABLE ,Presence detect changed event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " STATUS_MRL_SENSOR_CHANGED_ENABLE ,MRL sensor changed event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " POWER_FAULT_DETECTED_ENABLE ,Power fault event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ATTN_BUTTON_PRESSED_ENABLE ,Attention button pressed event interrupt" "Disabled,Enabled"
|
|
line.long 0x04 "RCR,Root Control Register"
|
|
bitfld.long 0x04 3. " PME_INT ,PME interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SERR_FAT ,Generating system error if a fatal error is reported" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SERR_NONFAT ,Generating system error if a non-fatal error is reported" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SERR_COR ,System error if a correctable error is reported" "Disabled,Enabled"
|
|
line.long 0x08 "RSR,Root Status Register"
|
|
rbitfld.long 0x08 17. " PMEPEND ,Another PME is pending when the PMESTAT bit is set" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x08 16. " PMESTAT ,PME was asserted by the requester ID" "Not active,Active"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--15. 1. " REQID ,PCI requester ID of the last PME requester"
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "DEVICE_CAPABILITIES_2,Root Capabilities Register 2"
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 11. " LTR_MECH_SUP ,LTR Capability support" "Unsupported,Supported"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " CPL_TO_DIS_SUP ,Support disabling the completion timeout mechanism" "Unsupported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPL_TO_RANGES_SUP ,Completion timeout ranges supported by the root port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "DEVICE_CONTROL_STATUS_2,Device Control/Status Register 2"
|
|
bitfld.long 0x00 4. " CPL_TO_DISABLE ,Disables completion timeout" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CPL_TO_VALUE ,Completion timeout ranges supported by the root port" "Default,Range A LO,Range A HI,,,Range B LO,Range B HI,?..."
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "LINK_CONTROL_STATUS_2,Link Control Status Register"
|
|
rbitfld.long 0x00 16. " CURRENT_DEEMPHASIS_LEVEL ,Current deemphasis level" "6,3.5"
|
|
textline " "
|
|
bitfld.long 0x00 12. " COMPLIANCE_DEEMPHASIS ,Compliance deemphasis" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMPLIANCE_SOS ,Compliance SOS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ENTER_MODIFIED_COMPLIANCE ,Transmission of the modified compliance pattern" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7.--9. " TRANSMIT_MARGIN ,Value of the non-deemphasized voltage level (Full-swing/Half swing)" "800-1200mV/400-600mV,600-800mV/300-400mV,400-600mV/200-300mV,200-400mV/100-200mV,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 6. " SELECTABLE_DEEMPHASIS ,Level of de-emphasis" "-6dB,-3.5dB"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " HW_AUTO_SPEED_DISABLE ,Link speed change disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ENTER_COMPLIANCE ,Forces link to enter compliance mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TARGET_LINK_SPEED ,Upper limit on the link operational speed" ",2.5Gb/s,5Gb/s,?..."
|
|
tree.end
|
|
tree "Error Reporting Capability Registers"
|
|
width 20.
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "ERPTCAP,Advanced Error Reporting Enhanced Capability Header Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " NEXT_PTR ,Next PTR"
|
|
bitfld.long 0x00 16.--19. " VERSION ,Version" "Version 0,Version 1,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " ID ,ID"
|
|
else
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "ERPTCAP,Advanced Error Reporting Enhanced Capability Header Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " ID ,ID"
|
|
bitfld.long 0x00 16.--19. " VERSION ,Version" "Version 0,Version 1,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " NEXT_PTR ,Next PTR"
|
|
endif
|
|
group.long 0x104++0x0B
|
|
line.long 0x00 "ERPTCAP_UCERR,Uncorrectable Error Status Register"
|
|
eventfld.long 0x00 20. " UNSUP_REQ_ERR ,Unsupported request error status" "No error,Error"
|
|
eventfld.long 0x00 19. " ECRC_ERR ,ECRC error status" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 18. " MF_TLP ,Malformed TLP status" "False,True"
|
|
eventfld.long 0x00 17. " RCV_OVFL ,Receiver overflow status" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 16. " UNEXP_COMP ,Unexpected completion status" "False,True"
|
|
eventfld.long 0x00 15. " COMP_ABORT ,Completion abort status" "Not aborted,Aborted"
|
|
textline " "
|
|
eventfld.long 0x00 14. " COMP_TO ,Completion timeout status" "No timeout,Timeout"
|
|
eventfld.long 0x00 13. " FC_PROTO_ERR ,Flow control protocol error status" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 12. " POS_TLP ,Poisoned TLP status" "False,True"
|
|
eventfld.long 0x00 4. " DLINK_PROTO_ERR ,Data link protocol error status" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " TRAINING_ERR ,Training error status" "No error,Error"
|
|
line.long 0x04 "ERPTCAP_UCERR_MK,Uncorrectable Error Mask Register"
|
|
bitfld.long 0x04 20. " UNSUP_REQ_ERR ,Unsupported request error mask" "Not masked,Masked"
|
|
bitfld.long 0x04 19. " ECRC_ERR ,ECRC error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " MF_TLP ,Malformed TLP mask" "Not masked,Masked"
|
|
bitfld.long 0x04 17. " RCV_OVFL ,Receiver overflow mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " UNEXP_COMP ,Unexpected completion mask" "Not masked,Masked"
|
|
bitfld.long 0x04 15. " COMP_ABORT ,Completion abort mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " COMP_TO ,Completion timeout mask" "Not masked,Masked"
|
|
bitfld.long 0x04 13. " PROTO_ERR ,Flow control protocol error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " POS_TLP ,Poisoned TLP mask" "Not masked,Masked"
|
|
bitfld.long 0x04 4. " DLINK_PROTO_ERR ,Data link protocol error mask" "Not masked,Masked"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " TRAINING_ERR ,Training error mask" "Not masked,Masked"
|
|
line.long 0x08 "ERPTCAP_UCERR_SEVR,Correctable Error Severity Register"
|
|
bitfld.long 0x08 20. " UNSUP_REQ_ERR ,Unsupported request error" "Non-fatal,Fatal"
|
|
bitfld.long 0x08 19. " ECRC_ERR ,ECRC error" "Non-fatal,Fatal"
|
|
textline " "
|
|
bitfld.long 0x08 18. " MF_TLP ,Malformed TLP" "Non-fatal,Fatal"
|
|
bitfld.long 0x08 17. " RCV_OVFL ,Receiver overflow" "Non-fatal,Fatal"
|
|
textline " "
|
|
bitfld.long 0x08 16. " UNEXP_COMP ,Unexpected completion" "Non-fatal,Fatal"
|
|
bitfld.long 0x08 15. " COMP_ABORT ,Completion abort" "Non-fatal,Fatal"
|
|
textline " "
|
|
bitfld.long 0x08 14. " COMP_TO ,Completion timeout" "Non-fatal,Fatal"
|
|
bitfld.long 0x08 13. " PROTO_ERR ,Flow control protocol error" "Non-fatal,Fatal"
|
|
textline " "
|
|
bitfld.long 0x08 12. " POS_TLP ,Poisoned TLP" "Non-fatal,Fatal"
|
|
bitfld.long 0x08 4. " DLINK_PROTO_ERR ,Data link protocol error" "Non-fatal,Fatal"
|
|
textline " "
|
|
rbitfld.long 0x08 0. " TRAINING_ERR ,Training error" "Non-fatal,Fatal"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "ERPTCAP_CERR,Correctable Error Status Register"
|
|
eventfld.long 0x00 13. " ADVISORY_NF ,ADVISORY NF status" "Not masked,Masked"
|
|
eventfld.long 0x00 12. " RPLY_TO ,Replay timer timeout status" "Not masked,Masked"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RPLY_RLOV ,Replay NUM rollover status" "Not masked,Masked"
|
|
eventfld.long 0x00 7. " BAD_DLLP ,Bad DLLP status" "Not masked,Masked"
|
|
textline " "
|
|
eventfld.long 0x00 6. " BAD_TLP ,Bad TLP status" "Not masked,Masked"
|
|
eventfld.long 0x00 0. " RCV_ERR ,Receiver error status" "Not masked,Masked"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "ERPTCAP_CERR_MK,Correctable Error Mask Register"
|
|
bitfld.long 0x00 13. " ADVISORY_NF ,ADVISORY NF mask" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " RPLY_TO ,Replay timer timeout mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RPLY_RLOV ,Replay NUM rollover mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " BAD_DLLP ,Bad DLLP mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BAD_TLP ,Bad TLP mask" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " RCV_ERR ,Receiver error mask" "Not masked,Masked"
|
|
textline " "
|
|
width 26.
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "ERPTCAP_ADV_ERR_CAP_CNTL,Advanced Error Capabilities And Control Register"
|
|
bitfld.long 0x00 8. " ECRC_CHK_EN ,ECRC CHK EN" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " ECRC_CHK_CAP ,ECRC CHK CAP" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ECRC_GEN_EN ,ECRC GEN EN" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " ECRC_GEN_CAP ,ECRC GEN CAP" "False,True"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--4. " ERR_PTR ,ERR PTR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x11C++0xF
|
|
line.long 0x00 "ERPTCAP_HDR_LOG_DW0,Header Log Dword 0 Register"
|
|
line.long 0x04 "ERPTCAP_HDR_LOG_DW1,Header Log Dword 1 Register"
|
|
line.long 0x08 "ERPTCAP_HDR_LOG_DW2,Header Log Dword 2 Register"
|
|
line.long 0x0C "ERPTCAP_HDR_LOG_DW3,Header Log Dword 3 Register"
|
|
textline " "
|
|
width 20.
|
|
group.long 0x12C++0x0B
|
|
line.long 0x00 "ERPTCAP_ERR_CMD,Root Error Command Register"
|
|
bitfld.long 0x00 2. " FATAL_ERR_RPT_EN ,Fatal error RPT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NONFATAL_ERR_RPT_EN ,Non fatal error RPT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " COR_ERR_RPT_EN ,Correctable error RPT enable" "Disabled,Enabled"
|
|
line.long 0x04 "ERPTCAP_ERR_STS,Root Error Status Register"
|
|
rbitfld.long 0x04 27.--31. " ADV_ERR_INTR_MSG_NUM ,Base and MSI message data offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
eventfld.long 0x04 6. " FATAL_RCVD ,Fatal uncorrectable error messages" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x04 5. " NONFATAL_RCVD ,Non-fatal uncorrectable error messages" "Not received,Received"
|
|
eventfld.long 0x04 4. " FIRST_FATAL_RCVD ,First uncorrectable error message" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x04 3. " MULT_UNCOR_RCVD ,Error is received and UNCOR_RCVD is already set" "False,True"
|
|
eventfld.long 0x04 2. " STS_UNCOR_RCVD ,Error message" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x04 1. " MULT_COR_RCVD ,Correctable error message is received and COR_RCVD is already set" "False,True"
|
|
eventfld.long 0x04 0. " COR_RCVD ,Correctable error" "Not received,Received"
|
|
line.long 0x08 "ERPTCAP_ERR_ID,Error Source Identification Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " ERR_COR ,Requestor ID of first correctable error in root error status register "
|
|
hexmask.long.word 0x08 0.--15. 1. " ERR_UNCOR ,Requestor ID of first uncorrectable error in root error status register "
|
|
textline " "
|
|
tree.end
|
|
width 20.
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
tree "PCI L1 PM Substate Capability Registers"
|
|
rgroup.long 0x140++0x07
|
|
line.long 0x00 "EXT_CAP,Extended Capability Header Register"
|
|
hexmask.long.word 0x00 20.--31. 0x10 " EXT_CAP_NEXT_CAP ,Offset to the next PCI express capability structure"
|
|
bitfld.long 0x00 16.--19. " EXT_CAP_VERSION ,PCI-SIG defined version number that indicates the version of the capability structure present" ",L1_SUBSTATES,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " EXT_CAP_ID ,PCI-SIG defined ID number that indicates the nature and format of the extended capability"
|
|
line.long 0x04 "CAP,Capability Register"
|
|
bitfld.long 0x04 19.--23. " CAP_T_PWRON_VALUE ,Time (in us) that this Port requires the port on the opposite side of the link to wait" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 16.--17. " CAP_T_PWRON_SCALE ,Specifies the scale used for this port" "2 us,10 us,100 us,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " CAP_CM_RESTORE_TIME ,Time (in us) required for this port to re-establish common mode"
|
|
bitfld.long 0x04 4. " CAP_L1_PM_SUBSTATES_SUPPORTED ,L1 PM Substates is supported" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CAP_ASPM_L1_1_SUPPORTED ,ASPM L1.1 is supported" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CAP_ASPM_L1_2_SUPPORTED ,ASPM L1.2 is is supported" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CAP_PCI_PM_L1_1_SUPPORTED ,PCI-PM L1.1 is supported" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CAP_PCI_PM_L1_2_SUPPORTED ,PCI-PM L1.2 is supported" "Disabled,Enabled"
|
|
group.long 0x148++0x07
|
|
line.long 0x00 "CTRL1,Control 1 Register"
|
|
bitfld.long 0x00 29.--31. " LTR_L1_2_THRES_SCALE ,Scale for value contained within the LTR_L1.2_THRESHOLD_Value" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 16.--25. 1. " LTR1_2_THRESH_VAL ,Threshold value"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CM_RESTORE_TIME ,Restore time"
|
|
bitfld.long 0x00 3. " ASPM_L1_1_EN ,ASPM L1.1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ASPM_L1_2_EN ,ASPM L1.2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PCIPM_L1_1_EN ,PCIPM L1.1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PCIPM_L1_2_EN ,PCIPM L1.2 enable" "Disabled,Enabled"
|
|
line.long 0x04 "CTRL2,Control 2 Register"
|
|
bitfld.long 0x04 3.--7. " T_PWRON_VALUE ,Minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--1. " T_PWRON_SCALE ,Scale used for the port T_POWER_ON Valuse field in the L1 PM Substates Capabilities register" "2 us,10 us,100 us,?..."
|
|
tree.end
|
|
endif
|
|
tree "NVIDIA Private Registers"
|
|
width 20.
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "PRIV_XP_DL_0,Various Configurable Registers In The Data Link layer"
|
|
hexmask.long.word 0x00 19.--29. 1. " GEN2_REPLAY_TIMER_LIMIT ,Replay timer limit"
|
|
hexmask.long.word 0x00 10.--18. 1. " GEN2_ACK_TIMER_LIMIT ,ACK timer limit"
|
|
textline " "
|
|
hexmask.long.word 0x00 1.--9. 1. " GEN2_UPDATE_FC_THRESHOLD ,Update FC frequency"
|
|
bitfld.long 0x00 0. " GEN2_DL_TIMERS_DISABLE ,Enables the Gen2 DL timer settings" "No,Yes"
|
|
textline " "
|
|
width 34.
|
|
sif (cpuis("TEGRAX1"))
|
|
rgroup.long 0xC10++0x0F
|
|
line.long 0x00 "T_PCIE2_RP_LTR_REP_VAL,T_PCIE2_RP_LTR_REP_VAL"
|
|
hexmask.long.word 0x00 16.--31. 1. " T_PCIE2_RP_LTR_REP_VAL_NO_SNOOP ,T_PCIE2_RP_LTR_REP_VAL_NO_SNOOP"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " T_PCIE2_RP_LTR_REP_VAL_SNOOP ,T_PCIE2_RP_LTR_REP_VAL_SNOOP"
|
|
line.long 0x04 "T_PCIE2_RP_L1_1_ENTRY_COUNT,T_PCIE2_RP_L1_1_ENTRY_COUNT"
|
|
bitfld.long 0x04 31. " T_PCIE2_RP_L1_1_ENTRY_COUNT_RESET ,T_PCIE2_RP_L1_1_ENTRY_COUNT_RESET" "Done,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 30. " T_PCIE2_RP_L1_1_ENTRY_COUNT_FREEZE ,T_PCIE2_RP_L1_1_ENTRY_COUNT_FREEZE" "Done,Pending"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " T_PCIE2_RP_L1_1_ENTRY_COUNT_VALUE ,T_PCIE2_RP_L1_1_ENTRY_COUNT_VALUE"
|
|
line.long 0x08 "T_PCIE2_RP_L1_2_ENTRY_COUNT,T_PCIE2_RP_L1_2_ENTRY_COUNT"
|
|
bitfld.long 0x08 31. " T_PCIE2_RP_L1_2_ENTRY_COUNT_RESET ,T_PCIE2_RP_L1_2_ENTRY_COUNT_RESET" "Done,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 30. " T_PCIE2_RP_L1_2_ENTRY_COUNT_FREEZE ,T_PCIE2_RP_L1_2_ENTRY_COUNT_FREEZE" "Done,Pending"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--15. 1. " T_PCIE2_RP_L1_2_ENTRY_COUNT_VALUE ,T_PCIE2_RP_L1_2_ENTRY_COUNT_VALUE"
|
|
line.long 0x0C "T_PCIE2_RP_L1_2_ABORT_COUNT,T_PCIE2_RP_L1_2_ABORT_COUNT"
|
|
bitfld.long 0x0C 31. " T_PCIE2_RP_L1_2_ABORT_COUNT_RESET ,T_PCIE2_RP_L1_2_ABORT_COUNT_RESET" "Done,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 30. " T_PCIE2_RP_L1_2_ABORT_COUNT_FREEZE ,T_PCIE2_RP_L1_2_ABORT_COUNT_FREEZE" "Done,Pending"
|
|
textline " "
|
|
hexmask.long.word 0x0C 0.--15. 1. " T_PCIE2_RP_L1_2_ABORT_COUNT_VALUE ,0 T_PCIE2_RP_L1_2_ABORT_COUNT_VALUE"
|
|
textline " "
|
|
elif cpuis("TEGRAX2")
|
|
width 27.
|
|
group.long 0xC00++0x0F
|
|
line.long 0x00 "L1_PM_SUBSTATES_CYA,L1 PM Substates CYA Register"
|
|
bitfld.long 0x00 26. " REFCLK_ON_WITH_PAD_PLL_LOCK ,Refclk on with pad PLL lock" "Not locked,Locked"
|
|
bitfld.long 0x00 25. " REFCLK_ON_WITH_PLLE_LOCK ,Refclk on with PLLE lock" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 24. " HIDE_CAP ,Hide capability of L1 PM substates" "Not hidden,Hidden"
|
|
bitfld.long 0x00 19.--23. " T_PWRON_VALUE ,Time (in us) that this port requires the port on the opposite side of link to wait in L1.2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " T_PWRON_SCALE ,Specifies the scale used for the port T_POWER_ON value field in the L1 PM substates capabilities register" "2 us,10 us,100 us,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " CM_RESTORE_TIME ,Time (in us) required for this port to re-establish common mode as described in table in the L1 PM substates ECN"
|
|
textline " "
|
|
bitfld.long 0x00 4. " L1_PM_SUBSTATES ,L1 PM Substates support enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ASPM_L1_1 ,ASPM L1.1 support enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ASPM_L1_2 ,ASPM L1.2 support enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PCI_PM_L1_1 ,PCI-PM L1.1 support enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PCI_PM_L1_2 ,PCI-PM L1.2 support enable" "Disabled,Enabled"
|
|
line.long 0x04 "L1_PM_SUBSTATES_1_CYA,L1 PM Substates 1 CYA Register"
|
|
bitfld.long 0x04 22. " RX_TERM_EN_IN_L1_2 ,Receiver PAD termination when in L1.2 enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 13.--21. 1. " CHK_CLKREQ_ASSERTED_DLY ,Amount of time the DUT waits in L1.2"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--12. 1. " T_PWR_OFF_DLY ,T POWER ON DELY diagnostic amount of time the DUT waits in L1.2_entry before it enters L1.2_idle"
|
|
line.long 0x08 "L1_PM_SUBSTATES_2_CYA,L1 PM Substates 2 CYA Register"
|
|
bitfld.long 0x08 21.--24. " MICROSECOND_COMP ,Compensation value of the crystal oscillator frequency in microsecond tick generator used for REFCLK_ON time and common-mode turn ON time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x08 13.--20. 1. " MICROSECOND ,Microsecond diagnostic bit number of clocks in a microsecond in clk25m"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--12. 1. " T_L1_2_DLY ,T L1.2 delay diagnostic"
|
|
line.long 0x0C "L1_PM_SUBSTATES_3_CYA,L1 PM Substates 3 CYA Register"
|
|
hexmask.long.word 0x0C 18.--30. 1. " L11_T_REFCLK_ON ,Number of microseconds the port must wait in L1.1 to enable refclk after clkreq# has been asserted"
|
|
bitfld.long 0x0C 17. " L11_T_REFCLK_ON_ENABLE ,Refclk clock timer logic when in L1.1 after seeing deassertion of clkreq# enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x0C 4.--16. 1. " L12_T_REFCLK_ON ,Number of microseconds the port must wait to enable refclk after clkreq# has been asserted"
|
|
bitfld.long 0x0C 3. " PCIPM_L1_2 ,PCIMPM L1.2 functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " ASPM_L1_2 ,ASPM L1.2 functionality enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " PCIPM_L1_1 ,PCIPM L1.1 functionality enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " ASPM_L1_1 ,ASPM L1.1 functionality enable" "Disabled,Enabled"
|
|
rgroup.long 0xC10++0x03
|
|
line.long 0x00 "LTR_REP_VAL,LTR Reported Value Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " NO_SNOOP ,Value for no snoop"
|
|
hexmask.long.word 0x00 0.--15. 1. " SNOOP ,Value for snoop"
|
|
group.long 0xC14++0x17
|
|
line.long 0x00 "L1_1_ENTRY_COUNT,L1.1 Entry Count Register"
|
|
bitfld.long 0x00 31. " RESET ,VALUE reset" "No reset,Reset"
|
|
bitfld.long 0x00 30. " FREEZE ,Freeze" "No freeze,Freeze"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Number of times the link entered the L1.1 state"
|
|
line.long 0x04 "L1_2_ENTRY_COUNT,L1.2 Entry Count Register"
|
|
bitfld.long 0x04 31. " RESET ,VALUE reset" "No reset,Reset"
|
|
bitfld.long 0x04 30. " FREEZE ,Freeze" "No freeze,Freeze"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " VALUE ,Number of times the link entered L1.2 ENTRY state"
|
|
line.long 0x08 "L1_2_ABORT_COUNT,L1.2 Abort Count Register"
|
|
bitfld.long 0x08 31. " RESET ,VALUE reset" "No reset,Reset"
|
|
bitfld.long 0x08 30. " FREEZE ,Freeze" "No freeze,Freeze"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--15. 1. " VALUE ,Number of times the link entered the L1.2 ENTRY state"
|
|
line.long 0x0C "LTR_OVERRIDE,LTR Override Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " NO_SNOOP ,LTR override no snoop value"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SNOOP ,LTR override snoop value"
|
|
line.long 0x10 "L1SS_SPARE,L1SS Spare Register"
|
|
hexmask.long.word 0x10 18.--31. 1. " SPARE2 ,Spare 2"
|
|
eventfld.long 0x10 17. " LTR_MSG_RCV_STS ,LTR MSG RCV STS" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 16. " LTR_MSG_INT_EN ,LTR MSG INT enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x10 2.--15. 1. " SPARE1 ,Spare 1"
|
|
textline " "
|
|
bitfld.long 0x10 1. " LTR_OVERRIDE_NO_SNOOP_EN ,LTR override no snoop enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " LTR_OVERRIDE_SNOOP_EN ,LTR override snoop enable" "Disabled,Enabled"
|
|
line.long 0x14 "SLCG_OVERRIDE_DIS_SLCG,SLCG Override Disable SLCG Register"
|
|
bitfld.long 0x14 22. " PRI_CLK ,PRI CLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 21. " TMS0_UFPCI_CLK ,TMS0 UFPCI CLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " TMS0_DFPCI_CLK ,TMS0 DFPCI CLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 19. " TMS0C2_XTXCLK1X ,TMS0C2 XTXCLK1X enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 18. " TMS0C2_XCLK ,TMS0C2 XCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 17. " TMS0C1_XTXCLK1X ,TMS0C1 XTXCLK1X enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " TMS0C1_XCLK ,TMS0C1 XCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " TMS0C0_XTXCLK1X ,TMS0C0 XTXCLK1X enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 14. " TMS0C0_XCLK ,TMS0C0 XCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 13. " TMSC0_XCLK ,TMSC0 XCLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 12. " T0C2_PCA_XCLK ,T0C2 PCA XCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " T0C2_PCA_UFPCI_CLK ,T0C2 PCA UFPCI CLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 10. " T0C1_PCA_XCLK ,T0C1 PCA XCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " T0C1_PCA_UFPCI_CLK ,T0C1 PCA UFPCI CLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 8. " T0C0_PCA_XCLK ,T0C0 PCA XCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 7. " T0C0_PCA_UFPCI_CLK ,T0C0 PCA UFPCI CLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 6. " GRP2_XTXCLK1X ,GRP2 XTXCLK1X enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " GRP2_XCLK ,GRP2 XCLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " GRP1_XTXCLK1X ,GRP1 XTXCLK1X enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " GRP1_XCLK ,GRP1 XCLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " GRP0_XTXCLK1X ,GRP0 XTXCLK1X enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " GRP0_XCLK ,GRP0 XCLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " CLK25M ,CLK25M enable" "Disabled,Enabled"
|
|
group.long 0xD00++0x1B
|
|
line.long 0x00 "DBG0,Debug 0"
|
|
line.long 0x04 "DBG1,Debug 1"
|
|
line.long 0x08 "DBG2,Debug 2"
|
|
line.long 0x0C "DBG3,Debug 3"
|
|
line.long 0x10 "DBG4,Debug 4"
|
|
line.long 0x14 "DBG5,Debug 5"
|
|
line.long 0x18 "DBG6,Debug 6"
|
|
bitfld.long 0x18 31. " LOW_POWER_MODE ,Low power mode" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " CG_EN ,CG enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x18 0.--29. 1. " CTL ,Control"
|
|
rgroup.long 0xD1C++0x03
|
|
line.long 0x00 "DBG_RD_BACK_LO,Debug RD Back LO"
|
|
group.long 0xD20++0x1B
|
|
line.long 0x00 "DBG_RD_BACK_HI,Debug RD Back HI"
|
|
line.long 0x04 "LANE_DBG0,Lane Debug 0"
|
|
line.long 0x08 "LANE_DBG1,Lane Debug 1"
|
|
line.long 0x0C "LANE_DBG2,Lane Debug 2"
|
|
line.long 0x10 "LANE_DBG3,Lane Debug 3"
|
|
line.long 0x14 "LANE_DBG4,Lane Debug 4"
|
|
line.long 0x18 "LANE_DBG5,Lane Debug 5"
|
|
bitfld.long 0x18 31. " LOW_POWER_MODE ,Low power mode" "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " CG_EN ,CG enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long 0x18 0.--29. 1. " CTL ,Control"
|
|
rgroup.long 0xD3C++0x07
|
|
line.long 0x00 "LANE_DBG_RD_BACK_LO_VALUE,Lane Debug RD Back LO Value"
|
|
line.long 0x04 "LANE_DBG_RD_BACK_HI_VALUE,Lane Debug RD Back HI Value"
|
|
group.long 0xD44++0x0B
|
|
line.long 0x00 "LINK_DBG0,Link Debug 0"
|
|
line.long 0x04 "LINK_DBG1,Link Debug 1"
|
|
line.long 0x08 "LINK_DBG2,Link Debug 2"
|
|
bitfld.long 0x08 31. " LOW_POWER_MODE ,Low power mode" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " CG_EN ,CG enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " CTL ,Control" "0,1"
|
|
rgroup.long 0xD50++0x07
|
|
line.long 0x00 "LINK_DBG_RD_BACK_LO_VALUE,Link Debug RD Back LO Value"
|
|
line.long 0x04 "LINK_DBG_RD_BACK_HI_VALUE,Link Debug RD Back HI Value"
|
|
endif
|
|
width 27.
|
|
group.long 0xD5C++0x03
|
|
line.long 0x00 "PIPE_CTL,Controls (enabling /disabling) the pipelines added to meet timing on various interfaces"
|
|
bitfld.long 0x00 8. " UFA2WRR_PWTOP ,UFA2WRR PWTOP enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " UBFI2DFI_P2P ,UBFI2DFI P2P enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TXBA2DFI_WR ,TXBA2DFI WR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CMDQ2UFARB ,CMDQ2UFARB enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " UBFI2DFI_NTT ,UBFI2DFI NTT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PCA ,PCA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DFIREQ ,DFIREQ enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DFIRSP ,DFIRSP enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DFI2UBFI ,DFI2UBFI enable" "Disabled,Enabled"
|
|
sif (cpuis("TEGRAX2"))
|
|
group.long 0xD60++0x07
|
|
line.long 0x00 "XP_BUST_TRIG1,XP Bust Trigger 1"
|
|
bitfld.long 0x00 25. " L02RCVRY_L0S_FTS_TO ,Allows bus tracer trigger when getting FTS timeout in L0.0s" "Not allowed,Allowed"
|
|
bitfld.long 0x00 24. " L02RCVRY_TS_DET ,Allows bus tracer trigger when receiving TS in L0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " L02RCVRY_SURPRISE_EIDLE ,Allows bus tracer trigger when seeing surprise eidle in L0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 22. " L02RCVRY_8B10B_ERR ,Allows bus tracer trigger when receiving 8b10b error in L0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 21. " L02RCVRY_ADVERTISEDRATECHANGE ,Allows bus tracer trigger at advertised rate change in L0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 20. " L02RCVRY_DL_RETRAIN ,Allows bus tracer trigger at dl retrain in L0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " L02RCVRY_LPBK ,Allows bus tracer trigger at dl retrain in L0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 18. " L02RCVRY_SPEEDCHANGE ,Allows bus tracer trigger at speed change in L0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L02RCVRY_WIDTHCHANGE ,Allows bus tracer trigger at width change in L0" "Not allowed,Allowed"
|
|
bitfld.long 0x00 16. " L02RCVRY_LINK_RETRAIN ,Allows bus tracer trigger at link retraining in L0" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 13.--15. " CUST_TRANSITION_TO_MINOR_ST ,Mirror TO state of custom transition [Detect/Polling/Config/Recovery/L0/L1/L2/LoopBack/HotReset/Disabled/TXCHAR]" "Quiet/Active/Link start/RCVRLOCK/Normal/Entry/Entry/Entry/TS1/TS1/Active,Active/Config/Link accept/RCVRCFG/Entry/WAITRX/WAITRX/Active/Up check DN hold/Down wait/Compliance,Retry/Idle/Lane accept/Speed/Idle/Idle/Transmitwake/Idle/-/Entry/Eidle entry,Wait/-/Lane wait/Idle/Wait/Wait/Idle/Exit/-/Down/Eidle idle,Entry/Compliance/Idle/-/FTS/PWRUP/-/Speed/-/-/Eidle exit,-/CSpeed/PWRUP/-/PWRUP/Beacon entry/-/-/-/-/-,-/-/Complete/-/-/Beacon exit/-/Pre speed/-/-/-,-/-/-/Finish PKT/-/-/-/-/-/-/-"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " CUST_TRANSITION_FROM_MINOR_ST ,Mirror FROM state of custom transition [Detect/Polling/Config/Recovery/L0/L1/L2/LoopBack/HotReset/Disabled/TXCHAR]" "Quiet/Active/Link start/RCVRLOCK/Normal/Entry/Entry/Entry/TS1/TS1/Active,Active/Config/Link accept/RCVRCFG/Entry/WAITRX/WAITRX/Active/Up check DN hold/Down wait/Compliance,Retry/Idle/Lane accept/Speed/Idle/Idle/Transmitwake/Idle/-/Entry/Eidle entry,Wait/-/Lane wait/Idle/Wait/Wait/Idle/Exit/-/Down/Eidle idle,Entry/Compliance/Idle/-/FTS/PWRUP/-/Speed/-/-/Eidle exit,-/CSpeed/PWRUP/-/PWRUP/Beacon entry/-/-/-/-/-,-/-/Complete/-/-/Beacon exit/-/Pre speed/-/-/-,-/-/-/Finish PKT/-/-/-/-/-/-/-"
|
|
textline " "
|
|
bitfld.long 0x00 6.--9. " CUST_TRANSITION_TO_MAJOR_ST ,Major TO state of the custom transition" "DETECT,POLLING,CONFIG,,L0,L1,L2,RECOVERY,LOOPBACK,HOTRESET,DISABLED,TXCHAR,?..."
|
|
bitfld.long 0x00 2.--5. " CUST_TRANSITION_FROM_MAJOR_ST ,Major FROM state of the custom transition" "DETECT,POLLING,CONFIG,,L0,L1,L2,RECOVERY,LOOPBACK,HOTRESET,DISABLED,TXCHAR,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_EN ,Bus tracer trigger receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TX_EN ,Bus tracer trigger receive enable" "Disabled,Enabled"
|
|
line.long 0x04 "XP_BUST_TRIG2,XP BUST Trigger 2"
|
|
bitfld.long 0x04 31. " REPLAY_TIMER_EXPIRED_ERR ,REPLA timer expired error" "No error,Error"
|
|
bitfld.long 0x04 30. " SA_ERR ,SA error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 29. " DESKEW_ERR ,DESKEW error" "No error,Error"
|
|
bitfld.long 0x04 28. " TRAINING_ERR ,Training error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 27. " DPLLP_CRC_ERR ,DPLLP CRC error" "No error,Error"
|
|
bitfld.long 0x04 26. " 8B10B_ERR ,8B10B error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 25. " REPLAY_STARTED_ERR ,REPLAY started error" "No error,Error"
|
|
bitfld.long 0x04 24. " ROLLOVER_ERR ,ROLLOVER error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 23. " PWH_UPDATE_FC_ERR ,PWH update FC error" "No error,Error"
|
|
bitfld.long 0x04 22. " PWH_TOO_MANY_CREDITS_ERR ,PWH too many credits error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 21. " PWD_UPDATE_FC_ERR ,PWD update FC error" "No error,Error"
|
|
bitfld.long 0x04 20. " PWD_TOO_MANY_CREDITS_ERR ,PWD too many credits error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 19. " NPH_UPDATE_FC_ERR ,NPH update FC error" "No error,Error"
|
|
bitfld.long 0x04 18. " NPH_TOO_MANY_CREDITS_ERR ,NPH too many credits error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 17. " NPD_UPDATE_FC_ERR ,NPD update FC error" "No error,Error"
|
|
bitfld.long 0x04 16. " NPD_TOO_MANY_CREDITS_ERR ,NPD too many credits error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 15. " CH_UPDATE_FC_ERR ,CH update FC error" "No error,Error"
|
|
bitfld.long 0x04 14. " CH_TOO_MANY_CREDITS_ERR ,CH too many credits error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 13. " CD_UPDATE_FC_ERR ,CD update FC error" "No error,Error"
|
|
bitfld.long 0x04 12. " CD_TOO_MANY_CREDITS_ERR ,CD too many credits error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 11. " REC_OVFL_ISOPW_DATA_ERR ,REC overflow ISOPW data error" "No error,Error"
|
|
bitfld.long 0x04 10. " REC_OVFL_ISOPW_HDR_ERR ,REC overflow ISOPW HDR error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 9. " REC_OVFL_ISONP_HDR_ERR ,REC overflow ISONP HDR error" "No error,Error"
|
|
bitfld.long 0x04 8. " REC_OVFL_CPL_DATA_ERR ,REC overflow CPL data error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 7. " REC_OVFL_PW_DATA_ERR ,REC overflow PW data error" "No error,Error"
|
|
bitfld.long 0x04 6. " REC_OVFL_NP_DATA_ERR ,REC overflow NP data error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 5. " REC_OVFL_CPL_HDR_ERR ,REC overflow CPL HDR error" "No error,Error"
|
|
bitfld.long 0x04 4. " REC_OVFL_PW_HDR_ERR ,REC overflow PW HDR error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 3. " REC_OVFL_NP_HDR_ERR ,REC_OVFL_NP_HDR_ERR error" "No error,Error"
|
|
bitfld.long 0x04 2. " FRAMING_ERR ,Framing error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SEQ_ERR ,SEQ error" "No error,Error"
|
|
bitfld.long 0x04 0. " LCRC_ERR ,LCRC error" "No error,Error"
|
|
rgroup.long 0xD68++0x03
|
|
line.long 0x00 "XP_DEBUG,XP Debug"
|
|
bitfld.long 0x00 0.--1. " RX_CAL_STATUS ,Receiver CAL status" "Idle,Pending,Done,Disabled"
|
|
endif
|
|
tree.end
|
|
tree "Vendor-Defined Registers"
|
|
width 20.
|
|
group.long 0xE00++0x2B
|
|
line.long 0x00 "RX_HDR_LIMIT,RX HDR Limit"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPL ,Completion header buffer size"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PW ,Posted write header buffer size"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " NP ,Non-posted header buffer size"
|
|
line.long 0x04 "RX_DATA_LIMIT,RX Data Limit"
|
|
hexmask.long.byte 0x04 20.--27. 1. " CPL ,Completion data buffer size"
|
|
hexmask.long.word 0x04 8.--19. 1. " PW ,Posted write data buffer size"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " NP ,Non-posted write header buffer size"
|
|
line.long 0x08 "TX_HDR_LIMIT,TX HDR Limit"
|
|
sif (cpuis("TEGRAX2"))
|
|
hexmask.long.byte 0x08 24.--31. 1. " NPT ,TX HDR limit NPT"
|
|
textline " "
|
|
hexmask.long.byte 0x08 16.--23. 1. " CPL ,Size of the downstream completions header buffer"
|
|
else
|
|
hexmask.long.byte 0x08 16.--23. 1. " NP ,Size of the downstream non posted header buffer"
|
|
endif
|
|
hexmask.long.byte 0x08 8.--15. 1. " PW ,Size of the downstream posted writes header buffer"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " NP ,Size of the downstream non posted header buffer"
|
|
line.long 0x0C "TX_DATA_LIMIT,TX Data Limit"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " PW ,Size of the downstream Posted Writes Data Buffer"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " NP ,Size of the downstream Non Posted Data Buffer"
|
|
line.long 0x10 "UFPCI,Upstream FPCI Control Register"
|
|
bitfld.long 0x10 23.--27. " ISO_WEIGHT ,ISO weight" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 22. " ISO_CONTROL_ENABLE ,ISO control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " ISOPW2HPISO ,Convert posted writes" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " ISONP2HPISO ,Convert non-posted reads" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x10 12.--19. 1. " REQ_PEND_PERIOD ,Timers are reset when they hit the value"
|
|
bitfld.long 0x10 10.--11. " WRR_GRANT_BURST ,Time for arbitration within a TMS" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x10 5.--9. " PW_PRI_OVR_COUNT ,Number of grants" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 0.--4. " PW_STARV_COUNT ,Number of grants" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "MISC0,Miscellaneous Register 0"
|
|
bitfld.long 0x14 31. " SHORT_RXL_TIMER ,Completion timeout feature in RXL test" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " P2P_SMALL_ISA_HOLE ,P2P settings control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " P2P_F ,Transactions (64'hF_XXXX)" "0,1"
|
|
bitfld.long 0x14 28. " P2P_E ,Transactions (64'hE_XXXX)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 27. " P2P_D ,Transactions (64'hD_XXXX)" "0,1"
|
|
bitfld.long 0x14 26. " P2P_C ,Transactions (64'hC_XXXX)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 25. " P2P_B ,Transactions (64'hB_XXXX)" "0,1"
|
|
bitfld.long 0x14 24. " P2P_A ,Transactions (64'hA_XXXX)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 23. " NISONC2HPISO ,Upgrade to HPISO Read" "Disabled,Enabled"
|
|
bitfld.long 0x14 21. " AUTO_XCLK_FREQ_EN ,XCLK frequency dynamic switch" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " RXL_CLEAR_DROP ,Receiver DROP ALL status clear" "Disabled,Enabled"
|
|
sif (cpuis("TEGRAX2"))
|
|
hexmask.long.word 0x14 4.--19. 1. " ISO_PW_ENABLE[1] ,Enables ISO PW [1] transactions for packets with TC >= TC2ISOMAP"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x14 3. " ISO_PW_ENABLE ,Enables ISO PW transactions for packets with TC >= TC2ISOMAP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " ISO_NP_ENABLE ,Enables ISO NP transactions for packets with TC >= TC2ISOMAP" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " NATIVE_P2P_ENABLE ,Enables native peer2peer transactions" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " ENABLE_CLUMPING ,Enables unitid clumping" "Disabled,Enabled"
|
|
line.long 0x18 "TXBA0,TXBA0 Register"
|
|
hexmask.long.word 0x18 16.--31. 1. " REPLAY_TIMER_EXPIRY ,Replay timer expiry"
|
|
bitfld.long 0x18 12. " USE_REPLAY_TIMER_OFFSET ,Use replay timer offset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 11. " CMPL_MERGE_UPTO_64DW ,Merge completions upto 64DW payloads" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " CMPL_MERGE_UPTO_32DW ,Merge completions upto 32DW payloads" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " CMPL_MERGE_DISABLE ,Disables completion merging" "No,Yes"
|
|
hexmask.long.word 0x18 0.--8. 1. " REPLAY_BUF_LIMIT ,Replay buffer limit"
|
|
line.long 0x1C "TXBA1,TXBA1 Register"
|
|
sif (cpuis("TEGRAX2"))
|
|
hexmask.long.word 0x1C 8.--16. 1. " MERGE_THRESHOLD ,Merge threshold"
|
|
else
|
|
hexmask.long.byte 0x1C 8.--15. 1. " MERGE_THRESHOLD ,Merge threshold"
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x1C 4.--7. " CM_OVER_PW_BURST ,Inputs into the downstream arbiter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x1C 0.--3. " PW_OVER_CM_BURST ,Inputs into the downstream arbiter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rbitfld.long 0x1C 0.--3. " PW_OVER_CM_BURST ,Inputs into the downstream arbiter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x20 "FORCEFC,FC Priority Flip Threshold Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " NPD_UNRET_THRESH ,NPD UNRET THRESH"
|
|
hexmask.long.byte 0x20 16.--23. 1. " NPH_UNRET_THRESH ,NPH UNRET THRESH"
|
|
textline " "
|
|
hexmask.long.byte 0x20 8.--15. 1. " PWD_UNRET_THRESH ,PWD UNRET THRESH"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PWH_UNRET_THRESH ,PWH UNRET THRESH"
|
|
line.long 0x24 "TIMEOUT0,LINK LTSSM Timeout 0 Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PAD_SPDCHNG_GEN2 ,Time to wait for pads to change speed from Gen1 to Gen2"
|
|
hexmask.long.word 0x24 8.--23. 1. " PAD_PWRUP_CM ,Time to power up pads (no common-mode voltage during power down)"
|
|
textline " "
|
|
hexmask.long.byte 0x24 0.--7. 1. " PAD_PWRUP ,Time to power up pads (common-mode voltage during power down)"
|
|
line.long 0x28 "TIMEOUT1,LINK LTSSM Timeout 1. Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " RCVRY_SPD_UNSUCCESS_EIDLE ,Wait time in E-Idle after unsuccessful speed change"
|
|
hexmask.long.byte 0x28 16.--23. 1. " RCVRY_SPD_SUCCESS_EIDLE ,Wait time in E-Idle after unsuccessful speed change"
|
|
textline " "
|
|
hexmask.long.word 0x28 0.--15. 1. " PAD_SPDCHNG_GEN1 ,Wait time for pads to change speed from Gen2 to Gen1"
|
|
rgroup.long 0xE34++0x03
|
|
line.long 0x00 "PRBS,PRBS Results Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " LOCKED ,Locks lanes onto the incoming PRBS pattern"
|
|
hexmask.long.word 0x00 0.--15. 1. " ERR_COUNT_OVERFLOW ,Number of bit mismatches during PRBS run"
|
|
group.long 0xE38++0x03
|
|
line.long 0x00 "PRBS_ERR,PRBS Results Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " COUNT ,Number of bit errors detected in the incoming PRBS stream"
|
|
bitfld.long 0x00 0.--3. " SELECT ,Selects which lane number's Error Count shows up in the ERR_COUNT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
width 22.
|
|
group.long 0xE3C++0x27
|
|
line.long 0x00 "EIDLE_INFER_TO_0,EIDLE Inference Timeout Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " RCVRCFG_SUC_SPEED ,Infer E-Idle after this amount of time while in recovery"
|
|
hexmask.long.word 0x00 0.--15. 1. " L0_LPBK ,Infer E-Idle after this amount of time while in L0 or loopback"
|
|
line.long 0x04 "EIDLE_INFER_TO_1,EIDLE Inference Timeout Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " UNSUC_SPEED_GEN2 ,Infer E-Idle after this amount of time while in recovery"
|
|
hexmask.long.word 0x04 0.--15. 1. " UNSUC_SPEED_GEN1 ,Infer E-Idle after this amount of time while in recovery"
|
|
line.long 0x08 "LTSSM_DBGREG,LTSSM Debug Register"
|
|
eventfld.long 0x08 31. " LINKFSM[31] ,LINKFSM31" "Init,Clear"
|
|
eventfld.long 0x08 30. " [30] ,LINKFSM30" "Init,Clear"
|
|
textline " "
|
|
eventfld.long 0x08 29. " [29] ,LINKFSM29" "Init,Clear"
|
|
eventfld.long 0x08 28. " [28] ,LINKFSM28" "Init,Clear"
|
|
textline " "
|
|
eventfld.long 0x08 27. " [27] ,LINKFSM27" "Init,Clear"
|
|
eventfld.long 0x08 26. " [26] ,LINKFSM26" "Init,Clear"
|
|
textline " "
|
|
eventfld.long 0x08 25. " [25] ,LINKFSM25" "Init,Clear"
|
|
eventfld.long 0x08 24. " [24] ,LINKFSM24" "Init,Clear"
|
|
textline " "
|
|
eventfld.long 0x08 23. " [23] ,LINKFSM23" "Init,Clear"
|
|
eventfld.long 0x08 22. " [22] ,LINKFSM22" "Init,Clear"
|
|
textline " "
|
|
eventfld.long 0x08 21. " [21] ,LINKFSM21" "Init,Clear"
|
|
eventfld.long 0x08 20. " [20] ,LINKFSM20" "Init,Clear"
|
|
textline " "
|
|
eventfld.long 0x08 19. " [19] ,LINKFSM19" "Init,Clear"
|
|
eventfld.long 0x08 18. " [18] ,LINKFSM18" "Init,Clear"
|
|
textline " "
|
|
eventfld.long 0x08 17. " [17] ,LINKFSM17" "Init,Clear"
|
|
eventfld.long 0x08 16. " [16] ,LINKFSM16" "Init,Clear"
|
|
textline " "
|
|
eventfld.long 0x08 15. " [15] ,LINKFSM15" "Init,Clear"
|
|
eventfld.long 0x08 14. " [14] ,LINKFSM14" "Init,Clear"
|
|
textline " "
|
|
eventfld.long 0x08 13. " [13] ,LINKFSM13" "Init,Clear"
|
|
eventfld.long 0x08 12. " [12] ,LINKFSM12" "Init,Clear"
|
|
textline " "
|
|
eventfld.long 0x08 11. " [11] ,LINKFSM11" "Init,Clear"
|
|
eventfld.long 0x08 10. " [10] ,LINKFSM10" "Init,Clear"
|
|
textline " "
|
|
eventfld.long 0x08 9. " [9] ,LINKFSM9" "Init,Clear"
|
|
eventfld.long 0x08 8. " [8] ,LINKFSM8" "Init,Clear"
|
|
textline " "
|
|
eventfld.long 0x08 7. " [7] ,LINKFSM7" "Init,Clear"
|
|
eventfld.long 0x08 6. " [6] ,LINKFSM6" "Init,Clear"
|
|
textline " "
|
|
eventfld.long 0x08 5. " [5] ,LINKFSM5" "Init,Clear"
|
|
eventfld.long 0x08 4. " [4] ,LINKFSM4" "Init,Clear"
|
|
textline " "
|
|
eventfld.long 0x08 3. " [3] ,LINKFSM3" "Init,Clear"
|
|
eventfld.long 0x08 2. " [2] ,LINKFSM2" "Init,Clear"
|
|
textline " "
|
|
eventfld.long 0x08 1. " [1] ,LINKFSM1" "Init,Clear"
|
|
eventfld.long 0x08 0. " [0] ,LINKFSM0" "Init,Clear"
|
|
line.long 0x0C "PRIV_ERRSTS,Detailed Private Error Status Register"
|
|
eventfld.long 0x0C 31. " REPLAY_TIMER_EXPIRED_ERR ,Replay timer expired error" "No error,Error"
|
|
eventfld.long 0x0C 30. " SA_ERR ,SA error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 29. " DESKEW_ERR ,DESKEW error" "No error,Error"
|
|
eventfld.long 0x0C 28. " TRAINING_ERR ,Training error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 27. " DLLP_CRC_ERR ,DLLP CRC error" "No error,Error"
|
|
eventfld.long 0x0C 26. " 8B10B_ERR ,8B10B error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " REPLAY_STARTED_ERR ,Replay started error" "No error,Error"
|
|
eventfld.long 0x0C 24. " REPLAY_ROLLOVER_ERR ,Replay rollover error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 23. " PWH_UPDATE_FC_ERR ,PWH update FC error" "No error,Error"
|
|
eventfld.long 0x0C 22. " PWH_TOO_MANY_CREDITS_ERR ,PWH too many credits error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 21. " PWD_UPDATE_FC_ERR ,PWD update FC error" "No error,Error"
|
|
eventfld.long 0x0C 20. " PWD_TOO_MANY_CREDITS_ERR ,PWD too many credits error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " NPH_UPDATE_FC_ERR ,NPH update FC error" "No error,Error"
|
|
eventfld.long 0x0C 18. " NPH_TOO_MANY_CREDITS_ERR ,NPH too many credits error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 17. " NPD_UPDATE_FC_ERR ,NPD update FC error" "No error,Error"
|
|
eventfld.long 0x0C 16. " NPD_TOO_MANY_CREDITS_ERR ,NPD too many credits error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 15. " CH_UPDATE_FC_ERR ,CH update FC error" "No error,Error"
|
|
eventfld.long 0x0C 14. " CH_TOO_MANY_CREDITS_ERR ,CH too many credits error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 13. " CD_UPDATE_FC_ERR ,CD update FC error" "No error,Error"
|
|
eventfld.long 0x0C 12. " CD_TOO_MANY_CREDITS_ERR ,CD too many credits error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 11. " REC_OVFL_ISOPW_DATA_ERR ,REC overflow ISOPW data error" "No error,Error"
|
|
eventfld.long 0x0C 10. " REC_OVFL_ISOPW_HDR_ERR ,REC overflow ISOPW HDR error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 9. " REC_OVFL_ISONP_HDR_ERR ,REC overflow ISONP HDR error" "No error,Error"
|
|
eventfld.long 0x0C 8. " REC_OVFL_CPL_DATA_ERR ,REC overflow CPL data error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " REC_OVFL_PW_DATA_ERR ,REC overflow PW data error" "No error,Error"
|
|
eventfld.long 0x0C 6. " REC_OVFL_NP_DATA_ERR ,REC overflow NP data error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 5. " REC_OVFL_CPL_HDR_ERR ,REC overflow CPL HDR error" "No error,Error"
|
|
eventfld.long 0x0C 4. " REC_OVFL_PW_HDR_ERR ,REC overflow PW HDR error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 3. " REC_OVFL_NP_HDR_ERR ,REC overflow NP HDR error" "No error,Error"
|
|
eventfld.long 0x0C 2. " FRAMING_ERR ,Framing error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " SEQ_ERR ,SEQ error" "No error,Error"
|
|
eventfld.long 0x0C 0. " LCRC_ERR ,LCRC error" "No error,Error"
|
|
line.long 0x10 "PRIV_ERRMSK,Detailed Private Error Mask Register"
|
|
bitfld.long 0x10 31. " REPLAY_TIMER_EXPIRED_ERR_EN ,Replay timer expired error enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " SA_ERR_EN ,SA error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " DLLP_CRC_ERR_EN ,DLLP CRC error enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " 8B10B_ERR_EN ,8B10B error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " REPLAY_ROLLOVER_ERR_EN ,Replay rollover error enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 23. " PWH_UPDATE_FC_ERR_EN ,PWH update FC error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 22. " PWD_TOO_MANY_CREDITS_ERR_EN ,PWD too many credits error enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " PWD_UPDATE_FC_ERR_EN ,PWD update FC error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PWD_TOO_MANY_CREDITS_ERR_EN ,PWD too many credits error enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 19. " NPH_UPDATE_FC_ERR_EN ,NPH update FC error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 18. " NPH_TOO_MANY_CREDITS_ERR_EN ,NPH too many credits error enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " NPD_UPDATE_FC_ERR_EN ,NPD update FC error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " NPD_TOO_MANY_CREDITS_ERR_EN ,NPD too many credits error enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " CH_UPDATE_FC_ERR_EN ,CH update FC error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 14. " CH_TOO_MANY_CREDITS_ERR_EN ,CH too many credits error enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " CD_UPDATE_FC_ERR_EN ,CD update FC error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 12. " CD_TOO_MANY_CREDITS_ERR_EN ,CD too many credits error enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 11. " DLL_PROTOCOL_ERR_EN ,DLL protocol error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " FRAMING_ERR_EN ,Framing error enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " SEQ_ERR_EN ,SEQ error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " LCRC_ERR_EN ,LCRC error enable" "Disabled,Enabled"
|
|
line.long 0x14 "LTSSM_TRACE_CONTROL,LTSSM Trace Control Register"
|
|
bitfld.long 0x14 11.--13. " TRIG_PRX_LTSSM_MINOR ,Trigger PRX LTSSM minor" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 8.--10. " TRIG_PTX_LTSSM_MINOR ,Trigger PTX LTSSM minor" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " TRIG_LTSSM_MAJOR ,Trigger LTSSM major" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 3. " TRIG_ON_EVENT ,Trigger on event" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x14 2. " CLEAR_RAM ,Clear RAM" "Not cleared,Cleared"
|
|
bitfld.long 0x14 1. " WRAP_EN ,Wrap enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " STORE_EN ,Store enable" "Disabled,Enabled"
|
|
line.long 0x18 "LTSSM_TRACE_STATUS,LTSSM Trace Status Register"
|
|
rbitfld.long 0x18 19.--21. " PRX_LTSSM_MINOR ,PRX LTSSM minor" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x18 16.--18. " PTX_LTSSM_MINOR ,PTX LTSSM minor" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
rbitfld.long 0x18 12.--15. " LTSSM_MAJOR ,LTSSM major" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x18 11. " READ_DATA_VALID ,Read data valid" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x18 6.--10. " READ_ADDR ,Read address to LTSSM trace RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x18 1.--5. " WRITE_PTR ,Current location of write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
rbitfld.long 0x18 0. " RAM_FULL ,All entries in RAM has been written" "Not full,Full"
|
|
line.long 0x1C "PG,PCIe Power Gate Register"
|
|
bitfld.long 0x1C 2. " RCVD_PME_TO_ACK_INTR_EN ,Generation of interrupt on reception of PME TO ACK TLP" "Disabled,Enabled"
|
|
eventfld.long 0x1C 1. " RCVD_PME_TO_ACK ,Root port received a PME TO ACK TLP" "Init,Clear"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " SEND_PME_TO_MSG ,Send a PME TO message downstream" "Idle,Send now"
|
|
line.long 0x20 "VAR_RANGE0,PCIe Legacy I/O Decode Range Control Register 0"
|
|
hexmask.long.word 0x20 18.--31. 0x04 " LIMIT ,Top address for the variable range positive decode addresses"
|
|
hexmask.long.word 0x20 2.--15. 0x04 " BASE ,Base address for the variable range positive decode addresses"
|
|
textline " "
|
|
bitfld.long 0x20 0. " ENABLE ,Enable" "Disabled,Enabled"
|
|
line.long 0x24 "VAR_RANGE1,PCIe Legacy I/O Decode Range Control Register 1"
|
|
hexmask.long.word 0x24 18.--31. 0x04 " LIMIT ,Top address for the variable range positive decode addresses"
|
|
textline " "
|
|
hexmask.long.word 0x24 2.--15. 0x04 " BASE ,Base address for the variable range positive decode addresses"
|
|
bitfld.long 0x24 0. " ENABLE ,Enable" "Disabled,Enabled"
|
|
sif (cpuis("TEGRAX1"))
|
|
group.long 0xE80++0x1F
|
|
line.long 0x00 "T_PCIE2_RP_ECTL_1_R1,T_PCIE2_RP_ECTL_1_R1"
|
|
bitfld.long 0x00 24.--27. " T_PCIE2_RP_ECTL_1_R1_RX_FELS_1C ,T_PCIE2_RP_ECTL_1_R1_RX_FELS_1C" "DEFAULT,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 18.--19. " T_PCIE2_RP_ECTL_1_R1_RX_TERM_CTRL_1C ,T_PCIE2_RP_ECTL_1_R1_RX_TERM_CTRL_1C" "DEFAULT,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " T_PCIE2_RP_ECTL_1_R1_TX_TERM_CTRL_1C ,T_PCIE2_RP_ECTL_1_R1_TX_TERM_CTRL_1C" "DEFAULT,1,2,3"
|
|
bitfld.long 0x00 12.--15. " T_PCIE2_RP_ECTL_1_R1_TX_DRV_CTRL_1C ,T_PCIE2_RP_ECTL_1_R1_TX_DRV_CTRL_1C" "DEFAULT,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " T_PCIE2_RP_ECTL_1_R1_TX_DRV_SLEW_1C ,T_PCIE2_RP_ECTL_1_R1_TX_DRV_SLEW_1C" "DEFAULT,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--5. " T_PCIE2_RP_ECTL_1_R1_TX_DRV_AMP_1C ,T_PCIE2_RP_ECTL_1_R1_TX_DRV_AMP_1C" "DEFAULT,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "T_PCIE2_RP_ECTL_2_R1,T_PCIE2_RP_ECTL_1_R2"
|
|
bitfld.long 0x04 18.--19. " T_PCIE2_RP_ECTL_2_R1_RX_IQ_CTRL_1C ,T_PCIE2_RP_ECTL_2_R1_RX_IQ_CTRL_1C" "DEFAULT,1,2,3"
|
|
hexmask.long.word 0x04 0.--15. 1. " T_PCIE2_RP_ECTL_2_R1_RX_CTLE_1C ,T_PCIE2_RP_ECTL_2_R1_RX_CTLE_1C"
|
|
line.long 0x08 "T_PCIE2_RP_ECTL_3_R1,T_PCIE2_RP_ECTL_3_R1"
|
|
line.long 0x0C "T_PCIE2_RP_ECTL_4_R1,T_PCIE2_RP_ECTL_4_R1"
|
|
hexmask.long.word 0x0C 16.--31. 1. " T_PCIE2_RP_ECTL_4_R1_RX_CDR_CTRL_1C ,T_PCIE2_RP_ECTL_4_R1_RX_CDR_CTRL_1C"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " T_PCIE2_RP_ECTL_4_R1_RX_PI_CTRL_1C ,T_PCIE2_RP_ECTL_4_R1_RX_PI_CTRL_1C"
|
|
line.long 0x10 "T_PCIE2_RP_ECTL_5_R1,T_PCIE2_RP_ECTL_5_R1"
|
|
line.long 0x14 "T_PCIE2_RP_ECTL_6_R1,T_PCIE2_RP_ECTL_6_R1"
|
|
line.long 0x18 "T_PCIE2_RP_ECTL_7_R1,T_PCIE2_RP_ECTL_7_R1"
|
|
bitfld.long 0x18 8.--13. " T_PCIE2_RP_ECTL_7_R1_TX_DRV_PRE_1C ,T_PCIE2_RP_ECTL_7_R1_TX_DRV_PRE_1C" "DEFAULT,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x18 0.--5. " T_PCIE2_RP_ECTL_7_R1_TX_DRV_POST_1C ,T_PCIE2_RP_ECTL_7_R1_TX_DRV_POST_1C" "DEFAULT,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xEA0++0x1B
|
|
line.long 0x00 "T_PCIE2_RP_ECTL_1_R2,T_PCIE2_RP_ECTL_1_R2"
|
|
bitfld.long 0x00 24.--27. " T_PCIE2_RP_ECTL_1_R2_RX_FELS_1C ,T_PCIE2_RP_ECTL_1_R2_RX_FELS_1C" "DEFAULT,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "T_PCIE2_RP_ECTL_2_R2,T_PCIE2_RP_ECTL_2_R2"
|
|
hexmask.long.word 0x04 16.--31. 1. " T_PCIE2_RP_ECTL_2_R2_RX_DFE_1C ,T_PCIE2_RP_ECTL_2_R2_RX_DFE_1C"
|
|
hexmask.long.word 0x04 0.--15. 1. " T_PCIE2_RP_ECTL_2_R2_CDR_CNTL_1C ,T_PCIE2_RP_ECTL_2_R2_CDR_CNTL_1C"
|
|
line.long 0x08 "T_PCIE2_RP_ECTL_3_R2,T_PCIE2_RP_ECTL_3_R2"
|
|
line.long 0x0C "T_PCIE2_RP_ECTL_4_R2,T_PCIE2_RP_ECTL_4_R2"
|
|
hexmask.long.word 0x0C 16.--31. 1. " T_PCIE2_RP_ECTL_4_R2_RX_CDR_CTRL_1C ,T_PCIE2_RP_ECTL_4_R2_RX_CDR_CTRL_1C"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " T_PCIE2_RP_ECTL_4_R2_RX_PI_CTRL_1C ,T_PCIE2_RP_ECTL_4_R2_RX_PI_CTRL_1C"
|
|
line.long 0x10 "T_PCIE2_RP_ECTL_5_R2,T_PCIE2_RP_ECTL_5_R2"
|
|
line.long 0x14 "T_PCIE2_RP_ECTL_6_R2,T_PCIE2_RP_ECTL_6_R2"
|
|
line.long 0x18 "T_PCIE2_RP_ECTL_7_R1,T_PCIE2_RP_ECTL_7_R1"
|
|
bitfld.long 0x18 8.--13. " T_PCIE2_RP_ECTL_7_R2_TX_DRV_PRE_SEL0_1C ,T_PCIE2_RP_ECTL_7_R2_TX_DRV_PRE_SEL0_1C" "Default,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x18 0.--5. " T_PCIE2_RP_ECTL_7_R2_TX_DRV_POST_SEL0_1C ,T_PCIE2_RP_ECTL_7_R2_TX_DRV_POST_SEL0_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Default,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xF00++0x0B
|
|
line.long 0x00 "VEND_XP,Vendor XP Register (NVIDIA's Implementation)"
|
|
bitfld.long 0x00 31. " FORCE_COMPLIANCE ,Force compliance" "Disabled,Enabled"
|
|
rbitfld.long 0x00 30. " DL_UP ,Status of data link layer in XP" "Down,Up"
|
|
textline " "
|
|
bitfld.long 0x00 29. " INTERLEAVE_DLLPS ,Interleave DLLPS" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " OPPORTUNISTIC_UPDATEFC ,DL will send any pending UpdateFC packet" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " OPPORTUNISTIC_ACK ,DL will send pending Acks" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TRAIN_ERR_ENABLE ,Enables reporting of training errors" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 18.--25. 1. " UPDATE_FC_THRESHOLD ,Override for the UpdateFC frequency"
|
|
hexmask.long.word 0x00 2.--17. 1. " PRBS_STAT ,Results of loopback mode testing"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PRBS_EN ,Enables the root port as loopback master" "Disabled,Enabled"
|
|
sif (!cpuis("TEGRAX1")&&!cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " EMULATION ,Enables emulation mode operation" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "VEND_XP1,Vendor XP Register 1 (NVIDIA's Implementation)"
|
|
bitfld.long 0x04 29.--31. " L1_EXIT_LATENCY ,L1 exit latency for the given PCI express link" "< 1us,1us - 2us,2us - 4us,4us - 8us,8us - 16us,16us -32us,32us-64us,> 64us"
|
|
bitfld.long 0x04 28. " FORCE_DOWNSTREAM_NO_SNOOP ,Force downstream no snoop" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FORCE_UPSTREAM_NONCOH ,Force upstream non-coherent" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " NP_REQ_TIMEOUT ,Disable downstream NP request timeout" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 23. " IGNORE_L0S ,Ignore L0S" "No,Yes"
|
|
bitfld.long 0x04 22. " DONT_MERGE_PMASNAK ,Don't merge PMASNAK" "Merged,Not merged"
|
|
textline " "
|
|
bitfld.long 0x04 21. " L1_ASPM_SUPPORT ,Link capability register L1 ASPM support" "Not supported,Supported"
|
|
bitfld.long 0x04 20. " L23_READY_NO_D3 ,L23 ready no D3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACK_L1_NO_WAIT ,ACK L1 no wait" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 10.--18. 1. " ACK_TIMER_LIMIT ,Overrides the Ack timer limit for this root port"
|
|
textline " "
|
|
bitfld.long 0x04 8. " RNCTRL_GEN2_WAIT_FOR_FIRST_EIES ,RNCTRL GEN2 wait for first EIES" "Disabled,Enabled"
|
|
rbitfld.long 0x04 7. " RNCTRL_EN ,Dynamic link width re-negotiation procedure in XP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " GEN2_LINK_UPGRADE ,Selects the 2.0-compliant link width upgrade protocol" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--5. " RNCTRL_MAXWIDTH ,Maximum link width required at the end of dynamic link width renegotiation process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "VEND_XP2,Vendor XP Register 2 (NVIDIA's Implementation)"
|
|
hexmask.long.byte 0x08 24.--31. 1. " L0S_UPDATE_WAKE ,L0S update wake"
|
|
hexmask.long.word 0x08 8.--17. 1. " L0S_THRESHOLD ,Controls the idle time required for TxL0s entry from L0"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " L0S_ACK_WAKE ,L0S ACK wake"
|
|
sif (cpuis("TEGRAX1"))
|
|
group.long 0xF0C++0x03
|
|
line.long 0x00 "VEND_XV_TIMEOUT,Fields unique to NVIDIA's implementation of PCI Express devices"
|
|
hexmask.long.word 0x00 20.--31. 1. " N100MS_DFPCI ,N100MS_DFPCI"
|
|
hexmask.long.word 0x00 0.--9. 1. " MICROSECOND ,MICROSECOND"
|
|
elif (cpuis("TEGRAX2"))
|
|
group.long 0xF0C++0x03
|
|
line.long 0x00 "VEND_XV_TIMEOUT,Vendor XV Timeout Register (NVIDIA's Implementation)"
|
|
hexmask.long.word 0x00 20.--31. 1. " 100MS_DFPCI ,Number of Dfpci_clk clocks in a given 100ms interval"
|
|
hexmask.long.word 0x00 0.--9. 1. " MICROSECOND ,Various timers required by PCI-express specification"
|
|
group.long 0xF14++0x07
|
|
line.long 0x00 "VEND_XV_CMN,Vendor XV CMN Register (NVIDIA's Implementation)"
|
|
bitfld.long 0x00 29.--31. " ISO2TC_MAP ,TC to be used for FPCI ISO transactions" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "VEND_THERM_MGMT,Vendor THERM MGMT"
|
|
hexmask.long.word 0x04 4.--15. 1. " PERIOD ,Defines period (in microseconds) for the purpose of throttling"
|
|
bitfld.long 0x04 1.--3. " DUTY_CYCLE ,Defines fraction of PERIOD throttling is applied" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ENABLE ,Enables throttling of PCIe traffic" "Disabled,Enabled"
|
|
else
|
|
group.long 0xF0C++0x03
|
|
line.long 0x00 "VEND_XV_TIMEOUT,Fields unique to NVIDIA's implementation of PCI Express devices"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " VEND_XV_TIMEOUT ,VEND_XV_TIMEOUT"
|
|
endif
|
|
group.long 0xF20++0x03
|
|
line.long 0x00 "VEND_SLOT_STRAP,Vendor Slot Capabilities Register"
|
|
sif (cpuis("TEGRAX2"))
|
|
hexmask.long.word 0x00 19.--31. 1. " PHYSICAL_SLOT_NUMBER ,Physical slot number"
|
|
bitfld.long 0x00 18. " NO_CMD_COMPLETED_SUPPORT ,No CMD completed support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ELECTROMECH_INTERLOCK_PRESENT ,Electromechanical interlock present" "Not present,Present"
|
|
bitfld.long 0x00 15.--16. " SLOT_POWER_LIMIT_SCALE ,Slot power limit scale" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 7.--14. 1. " SLOT_POWER_LIMIT_VALUE ,Slot power limit value"
|
|
bitfld.long 0x00 6. " HOT_PLUG_CAPABLE ,Supporting hot-plug operations" "Not capable,Capable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HOT_PLUG_SURPRISE ,Hot-plug surprise" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " POWER_INDICATOR_PRESENT ,Power indicator" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ATTENTION_INDICATOR_PRESENT ,Attention Indicator" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. " MRL_SENSOR_PRESENT ,MRL Sensor" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 1. " POWER_CONTROLLER_PRESENT ,Power Controller" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " ATTENTION_BUTTON_PRESENT ,Attention Button" "Not implemented,Implemented"
|
|
else
|
|
hexmask.long.word 0x00 19.--31. 1. " PHYSICAL_SLOT_NUMBER ,Physical slot number"
|
|
bitfld.long 0x00 15.--16. " SLOT_POWER_LIMIT_SCALE ,Slot power limit scale" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 7.--14. 1. " SLOT_POWER_LIMIT_VALUE ,Slot power limit value"
|
|
endif
|
|
sif (cpuis("TEGRAX1"))
|
|
group.long 0xF30++0x03
|
|
line.long 0x00 "RP_XP_REF,This register contains diagnostic bits used in XP"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " CPL_TO_CUSTOM_VALUE ,User-specified value to use for completion timeout"
|
|
bitfld.long 0x00 13. " CPL_TO_OVERRIDE ,Enables the user override mode for completion timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ADVANCE_BY_2_CYA ,ADVANCE_BY_2_CYA" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " NAK_SCHEDULE_CYA ,NAK_SCHEDULE_CYA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RXL2LINK_NPT_EMPTY_CYA ,RXL2LINK_NPT_EMPTY_CYA" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " L2_READ_FIX_EN ,L2_READ_FIX_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MICROSECOND_ENABLE ,MICROSECOND_ENABLE" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MICROSECOND_LIMIT ,MICROSECOND_LIMIT"
|
|
elif (cpuis("TEGRAX2"))
|
|
group.long 0xF30++0x03
|
|
line.long 0x00 "RP_XP_REF,RP XP Reference Register"
|
|
hexmask.long.tbyte 0x00 14.--31. 1. " CPL_TO_CUSTOM_VALUE ,User-specified value to use for completion timeout"
|
|
bitfld.long 0x00 13. " CPL_TO_OVERRIDE ,Enables the user override mode for completion timeout" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ADVANCE_BY_2_CYA ,Advanced by 2 CYA" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " NAK_SCHEDULE_CYA ,NAK schedule CYA" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RXL2LINK_NPT_EMPTY_CYA ,RXL2LINK NPT empty CYA" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " L2_READ_FIX_EN ,L2 read fix enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MICROSECOND_ENABLE ,Microsecond enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MICROSECOND_LIMIT ,Counter value to be used to reset the one microsecond counter used for update FC scheduling"
|
|
group.long 0xF44++0x03
|
|
line.long 0x00 "VEND_CYA0,Vendor CYA0 Register"
|
|
bitfld.long 0x00 30. " FORCE_RETRY_POSSIBLE ,Force retry possible" "No,Yes"
|
|
bitfld.long 0x00 29. " UP_NC2C ,Forces all upstream non-coherent traffic to coherent" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DROP_VDM_TYPE1 ,VDM messages with vendor ID other than NVIDIA drop enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " DROP_NV_VDM_TYPE1 ,VDM messages with vendor ID NVIDIA(0x10DE) drop enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " REL_CRDT_4PKT_DRP_RXL ,Credits for the VDM packet dropped release enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " LTR_EN ,Hide LTR capability enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ALLOW_ALL_DS_RO ,Allow all DS RO" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NATIVE_P2P_STARVE_COUNT ,Native P2P starve count"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DSK_RESET_PULSE_WIDTH ,Number of symbol times Deskewer should hold RX fifos in hot_reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. " FINISH_PKT_ON_RCVRY_EN ,Finish packet on recovery enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " UR_PW_DROP_ALL_MODE ,UR PW drop all mode" "No,Yes"
|
|
bitfld.long 0x00 9. " DROP_ALL_MODE ,Drop all mode" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " MAX_PAYLOAD_SIZE ,Max payload size" "INIT,,,,,4KB,,Auto"
|
|
bitfld.long 0x00 5. " ADR64 ,64-bit addressing mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IGNORE_BME ,Ignores BMS and accepts upstream PCIe transactions" "Not ignored,Ignored"
|
|
bitfld.long 0x00 3. " UFPCI_BLOCK_B2B_NP ,UFPCI block back-to-back NP" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " GPU_NISONC2HPISO ,GPU NISONC2HPISO" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PASSPW_RO ,PASSPW RO" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " REL_CREDIT_UR_PW ,Credits for the ur_pw received release" "No,Yes"
|
|
else
|
|
group.long 0xF34++0x0F
|
|
line.long 0x00 "ECTL_2_R1,ECTL_2_R1"
|
|
hexmask.long.word 0x00 16.--31. 1. " RX_DFE_1C ,RX_DFE_1C"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RX_EQ_1C ,RX_EQ_1C"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CDR_CNTL_1C ,CDR_CNTL_1C"
|
|
line.long 0x04 "ECTL_3_R1,ECTL_3_R1"
|
|
bitfld.long 0x04 8.--11. " TX_PEAK_PRE_1C ,TX_PEAK_PRE_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--4. " TX_PEAK_1C ,TX_PEAK_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "ECTL_2_R2,ECTL_2_R2"
|
|
hexmask.long.word 0x08 16.--31. 1. " RX_DFE_1C ,RX_DFE_1C"
|
|
hexmask.long.word 0x08 0.--15. 1. " RX_EQ_1C ,RX_EQ_1C"
|
|
line.long 0x0C "ECTL_3_R2,ECTL_3_R2"
|
|
bitfld.long 0x0C 24.--27. " PRE_SEL1_1C ,PRE_SEL1_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 16.--20. " SEL1_1C ,SEL1_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--11. " PRE_SEL0_1C ,PRE_SEL0_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--4. " SEL0_1C ,SEL0_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.long 0xF48++0x07
|
|
line.long 0x00 "VEND_CTL1,Vendor Control Register 1 (NVIDIA's Implementation)"
|
|
bitfld.long 0x00 21. " POLLING_RESET_FIX_EN ,Polling reset fix enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " HOTPLUG_IN_TRAFFIC_EN ,Hotplug in traffic enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NISO2ISO ,All upstream non-ISO-PW and non-ISO-NP will be upgraded to ISO" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ALLOW_UPSTREAM_CMPL_OVERTAKE_PW ,UBFI allows CPL bypass PW regardless of RO bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPLIT_ARB_BLOCK_COH ,Split ARB block coherent" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " HIDE_MSIMAP ,Hide MSIMAP" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LINKACTV_REPORTING ,Setting the data link layer link active reporting capable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " P2P_ISO2NIS ,Forces upstream peer-to-peer ISO requests to be peer-to-peer NONISO" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ERPT ,ERPT" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " HIDE_MSI_CAP ,Hides the entire MSI capability structure from the capabilities list" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ACCEPT_MSGD1 ,Allows acceptance of NVIDIA specific vendor type message with data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--3. " TC2ISO_MAP ,TC2ISO MAP" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P2P_BLOCK_P2P_ONLY ,P2P block P2P only" "Disabled,Enabled"
|
|
line.long 0x04 "VEND_XP_BIST,IOBIST And Characterization Control Register (NVIDIA's Implementation)"
|
|
bitfld.long 0x04 30. " GOTO_DETECT_ON_SURPRISE_EIDLE ,Goto detect on surprise EIDLE" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " ENABLE_SERR_REPORTING ,Enable SERR reporting" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " GOTO_L1_L2_AFTER_DLLP_DONE ,Goto L1 L2 after DLLP done" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " CTRL_IGNORE_LPBK_EXIT ,Control ignore LPBK exit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 26. " CTRL_RELAX_LPBK_ENTRY ,Control relax LPBK entry" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " CTRL_FORCE_PRBS_RST ,Control force PRBS reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24. " FORCE_DEEMPHASIS_ADVERTISED_EN ,Force Deemphasis advertised enable" "Disabled,Enabled"
|
|
sif (cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x04 23. " POWER_UP_BYPASS ,Power up bypass" "No bypass,Bypass"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 22. " FORCE_RECEIVER_COMPLIANCE_EN ,Force reciver compliance enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " FORCE_COMPLIANCE_GEN2_SPEED_EN ,Force compliance GEN2 speed enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " FORCE_COMPLIANCE_AND_ADVERTISE_MODE ,Force compliance and advertise mode" "Disabled,Enabled"
|
|
sif (cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x04 19. " PRESERVE_TX_PACKET_DURING_SPEED_CHANGE ,Preserve TX packet during speed change" "Not preserved,Preserved"
|
|
bitfld.long 0x04 18. " GEN2_EXIT_USE_STAT_IDLE ,GEN2 exit use status idle" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GEN2_LOOPBACK ,GEN2 loopback" "0,1"
|
|
bitfld.long 0x04 16. " SA_EXTRA_RESET_EN_RANGE ,SA extra reset enable range" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 6.--15. 1. " CTRL_TX_PTRN_RANGE ,Control TX PTRN range"
|
|
bitfld.long 0x04 4.--5. " TEST_MODE_RANGE ,Test mode range" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 3. " NOSCRAMBLE_RANGE ,No scramble range" "0,1"
|
|
bitfld.long 0x04 2. " EIDLE_DATA_RANGE ,EIDLE data range" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 1. " EIDLE_OVERRIDE_RANGE ,EIDLE override range" "0,1"
|
|
bitfld.long 0x04 0. " RDET_BYPASS_RANGE ,RDET bypass range" "0,1"
|
|
endif
|
|
textline " "
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
width 22.
|
|
group.long 0xF50++0x03
|
|
line.long 0x00 "VEND_XP_PAD_PWRDN,Vendor XP PAD Powerdown (NVIDIA's Implementation)"
|
|
bitfld.long 0x00 31. " IDLE_MODE_L1_CLKREQ ,Idle mode L1 clock request" "0,1"
|
|
bitfld.long 0x00 30. " IDLE_MODE_DYNAMIC ,Idle mode dynamic" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " IDLE_MODE_L1 ,Idle mode L1" "0,1"
|
|
bitfld.long 0x00 28. " XVR_USE_DFPCI_DATA_UNINTR ,XVR use DFPCI data UNINTR" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 18.--27. 1. " MICROSECOND ,Various timers required by PCI-express specification"
|
|
bitfld.long 0x00 16.--17. " SLEEP_MODE_L1_CLKREQ ,Defines the 2-bit sleep-mode coding when clkreq is deasserted in L1" "L0,L1,L1P,L1PP"
|
|
textline " "
|
|
bitfld.long 0x00 15. " L1_CLKREQ ,Power down to SLEEP_MODE_L1_REQ enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " MINIMUM ,Minimum number of Gen1 xclks(4ns) that analog pads must remain powered down (or up) before the LTSSM attempts to power them back up/down again"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " SLEEP_MODE_DYNAMIC ,2-bit sleep-mode coding in the pad when the lane shut down due to dynamic link downsizing" "L0,L1,L1P,L1PP"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SLEEP_MODE_L1 ,2-bit sleep-mode coding in the pad when LTSSM is in the L1 state or DISABLED state" "L0,L1,L1P,L1PP"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DISABLED ,Enable analog pads to power down in the DISABLED_DOWN state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DYNAMIC ,Enable unused analog pads to power down after dynamic link width re-negotiation takes place" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " L1 ,Enable analog pads to power down when in L1 state" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
width 22.
|
|
group.long 0xF54++0x07
|
|
line.long 0x00 "VEND_XP_FTS,Vendor XP FTS (NVIDIA's Implementation)"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TS_DETECT_START ,TS detect start"
|
|
hexmask.long.byte 0x00 16.--23. 1. " FTS_DETECT_START ,Number of symbol times we wait before the root port begins looking at FTS ordered sets when exiting L0s"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " N_FTS_REMOTE ,N_FTS value advertised by the remote device"
|
|
hexmask.long.byte 0x00 0.--7. 1. " N_FTS ,N_FTS value that we advertise to the device on the other side of the link"
|
|
line.long 0x04 "VEND_XP_STATS0,Vendor XP States Register 0"
|
|
bitfld.long 0x04 28. " FAILED_L0S_EXITS_INF ,Failed L0s exit counter accumulates indefinitely" "No,Yes"
|
|
eventfld.long 0x04 24. " FAILED_L0S_EXITS_LC ,Failed L0S exits LC" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 20. " NAKS_RCVD_INF ,NAKs received counter accumulates indefinitely" "No,Yes"
|
|
eventfld.long 0x04 16. " NAKS_RCVD_LC ,NAKS received LC" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 12. " CRC_ERRORS_INF ,CRC error counter accumulates indefinitely" "No,Yes"
|
|
eventfld.long 0x04 8. " CRC_ERRORS_LC ,Current value from the CRC error counter" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 4. " 8B10B_ERRORS_INF ,8b/10b error counter accumulates indefinitely" "No,Yes"
|
|
eventfld.long 0x04 0. " 8B10B_ERRORS_LC ,Current value from the 8b/10b error counter" "No effect,Clear"
|
|
rgroup.long 0xF5C++0x07
|
|
line.long 0x00 "VEND_XP_STATS1,Vendor XP States Register 1"
|
|
sif (cpuis("TEGRAX2"))
|
|
hexmask.long.byte 0x00 24.--31. 1. " FAILED_L0S_EXITS ,Counts the number of times the RX side of the XP went into Recovery in one millisecond"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NAKS_RCVD ,Counts the number of NAKs received from the endpoint in 64 microseconds"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CRC_ERRORS ,Counts the number of CRC errors detected in 64 microseconds"
|
|
hexmask.long.byte 0x00 0.--7. 1. " 8B10B_ERRORS ,Counts the number of 8b/10b errors detected in one microsecond"
|
|
else
|
|
hexmask.long.byte 0x00 24.--31. 1. " 8B10B_ERRORS ,Counts the number of 8b/10b errors detected in one microsecond"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CRC_ERRORS ,Counts the number of CRC errors detected in 64 microseconds"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " NAKS_RCVD ,Counts the number of NAKs received from the endpoint in 64 microseconds"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FAILED_L0S_EXITS ,Counts the number of times the RX side of the XP went into Recovery in one millisecond"
|
|
endif
|
|
line.long 0x04 "VEND_ERROR_COUNT,Vendor Error Count Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " REPLAY ,Counts number of times TXBA replays"
|
|
hexmask.long.byte 0x04 8.--15. 1. " BAD_TLP ,Counts bad tlps reported by RXL"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " LCRC_ERR ,Counts LCRCL Errors reported by RXL"
|
|
textline " "
|
|
width 28.
|
|
group.long 0xF64++0x0B
|
|
line.long 0x00 "CFG_MISC,Config Miscellaneous Register (NVIDIA's Implementation)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MUTE_IDLE ,Mute idle"
|
|
line.long 0x04 "PRIV_XP_INIT_RECOVERY,Private XP Initialize Recovery Register (NVIDIA's Implementation)"
|
|
bitfld.long 0x04 31. " 8B10B_ERROR_ENABLE ,8B10B feature enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 20.--30. 1. " 8B10B_ERROR_WINDOW ,CPrograms the time frame in multiples of 1 microsecond"
|
|
textline " "
|
|
hexmask.long.tbyte 0x04 0.--19. 1. " 8B10B_ERROR_THRESHOLD ,Programs the 8b10b error threshold"
|
|
line.long 0x08 "PRIV_XP_LCTRL_2,Private XP LCTRL (NVIDIA's Implementation)"
|
|
rbitfld.long 0x08 31. " UPCONFIGURE_CAPABLE ,Gen2 link width up-configure capability" "Not capable,Capable"
|
|
bitfld.long 0x08 30. " REV2P0_COMPLIANCE_DIS ,Disable advertising rev2.0 support and link width up-configure capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " EIDLE_INFERENCE_EN ,Disable electrical idle inference" "No,Yes"
|
|
bitfld.long 0x08 28. " SURPRISE_IDLE_USE_STAT_IDLE ,Surprise idle use status idle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " ALLOW_SPEED_CHANGE_FROM_L1 ,Allow speed change to be initiated from the L1 or Rx_L0s link states" "Disabled,Enabled"
|
|
bitfld.long 0x08 24.--26. " RECOVERY_SPEED_TIMEOUT_ADJ ,Adjust minimum length of time the transmitter stays in idle in the Recover Sped state" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 20.--23. " N_EIE_SYMBOLS ,Number of K28.7 symbols" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 19. " DEEMPHASIS_STRAP ,DEEMPHASIS_STRAP" "-6db,-3.5db"
|
|
textline " "
|
|
bitfld.long 0x08 18. " ENFORCE_DEEMPHASIS ,Forces root port to use de-emphasis value" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " POLLING_PREDETERMINED_LANES ,Polling predetermined lanes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " AUTONOMOUS_CHANGE ,Autonomous change" "No,Yes"
|
|
rbitfld.long 0x08 12.--15. " DATA_RATE_SUPPORTED_REMOTE ,Gen2 data rate supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " DATA_RATE_SUPPORTED ,Supported link speed reported in the link capabilities" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 4.--7. " TARGET_LINK_SPEED ,Specifies the link rate to change to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 3. " TX_MARGIN_OVERRIDE ,TX_MARGIN_OVERRIDE" "Disabled,Enabled"
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x08 2. " CYA_DEEMPHASIS_OVERRIDE ,CYA deemphasis override" "No override,Override"
|
|
endif
|
|
bitfld.long 0x08 1. " ADVERTISED_RATE_CHANGE ,ADVERTISED_RATE_CHANGE" "No effect,Change"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SPEED_CHANGE ,Link speed negotiation procedure" "No effect,Change"
|
|
group.long 0xF74++0x03
|
|
line.long 0x00 "PRIV_XP_PAD_PWRUP,Private XP PAD_Powerup"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PMRX_PWRUP_THRESHOLD ,Time to hold CDR at reset in Recovery"
|
|
sif (cpuis("TEGRAX2"))
|
|
group.long 0xF78++0x03
|
|
line.long 0x00 "PRIV_XP_PAD_GEN2_PAD_PWRDN,Private XP PAD GEN2 PAD Powerdown"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MICROSECOND ,Number of xclks in 1 microsecond when running at gen2 speed"
|
|
endif
|
|
group.long 0xF84++0x03
|
|
line.long 0x00 "PRIV_XP_RECOVERY_REASONS,Register Records The Reasons We Went Into Recovery"
|
|
textline " "
|
|
width 30.
|
|
sif (cpuis("TEGRAX2"))
|
|
rgroup.long 0xF88++0x07
|
|
line.long 0x00 "PRIV_XP_RECOVERY_COUNT,Number Of RECOVERY STATE Entries In XP By The XVR"
|
|
line.long 0x04 "PRIV_XP_L0S_ENTRY_COUNT,Number Of Entries From L0 To L0s At ltssm Side"
|
|
rgroup.long 0xF94++0x0B
|
|
line.long 0x00 "PRIV_XP_L1_ENTRY_COUNT,Number Of Entries From L0 To L1 It Is Reset Whenever It Is Read"
|
|
line.long 0x04 "PRIV_XP_L1_TO_RECOVERY_COUNT,Number Of Entries From L1 To Recovery"
|
|
line.long 0x08 "PRIV_XP_L0_TO_RECOVERY_COUNT,Number Of Entries From L0 To Recovery"
|
|
bitfld.long 0x08 8. " REASON ,Reason" "All,Error"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " VALUE ,Value"
|
|
else
|
|
rgroup.long 0xF88++0x13
|
|
line.long 0x00 "PRIV_XP_RECOVERY_COUNT,Number of RECOVERY STATE entries in XP by the XVR"
|
|
line.long 0x04 "PRIV_XP_RX_L0S_ENTRY_COUNT,Number of entries from L0 to L0s at ltssm RX side"
|
|
line.long 0x08 "PRIV_XP_TX_L0S_ENTRY_COUNT,Number of entries from L0 to L0s at ltssm TX side"
|
|
line.long 0x0C "PRIV_XP_L1_ENTRY_COUNT,Number of entries from L0 to L1 It is reset whenever it is read"
|
|
line.long 0x10 "PRIV_XP_L1_TO_RECOVERY_COUNT,Number of entries from L1 to Recovery"
|
|
group.long 0xF9C++0x03
|
|
line.long 0x00 "PRIV_XP_L0_TO_RECOVERY_COUNT,Number of entries from L0 to Recovery"
|
|
bitfld.long 0x00 8. " REASON ,REASON" "All,Error"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " VALUE ,VALUE"
|
|
endif
|
|
rgroup.long 0xFA0++0x07
|
|
line.long 0x00 "PRIV_XP_L1P_ENTRY_COUNT,Number Of Entries From L0 To Deep L1"
|
|
line.long 0x04 "PRIV_XP_ASLM_COUNT,Number Of Switching Between X1 And X16 for Gen2 Only"
|
|
group.long 0xFA8++0x07
|
|
line.long 0x00 "VEND_CTL2,Vendor Control Register (Miscellaneous)"
|
|
bitfld.long 0x00 24. " COMPLIANCE_X8_DELAY ,CTL for compliance delay pattern" "Wrap on n-1,Wrap on 8/16 mod 8"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IGNORE_ATTENTION_BUTTON_MSG ,Ignore upstream attention button" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 22. " UNBLOCK_UP_TRANSACTIONS ,Unblock up transaction" "Blocked,Unblocked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " BLOCK_UP_TRANSACTIONS_ON_ERR ,Block all upstream transaction after an error" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " HW_AUTO_WIDTH_DISABLE_DIS ,HW auto width disable disable" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 19. " BW_MANAGEMENT_INT_EN_DIS ,BW management INT enable disable" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 18. " AUTO_BANDWIDTH_INT_EN_DIS ,Auto bandwidth INT enable disable" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 17. " AUTO_BANDWIDTH_DIS ,Auto bandwidth disable" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BW_MANAGEMENT_DIS ,BW management disable" "False,True"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SHADOW_LINK_BW_NOTIFY_CAP ,Shadow link BW notify capable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 12. " GEN2_PROTOCOL_DISABLE ,GEN2 protocol disable" "No,Yes"
|
|
else
|
|
rbitfld.long 0x00 12. " GEN2_PROTOCOL_DISABLE ,GEN2 protocol disable" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " SLOT_IMPLEMENTED ,Slot implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
eventfld.long 0x00 9. " ERR_STS_HOTPLUG_PME ,Error STS hotplug PME" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " ERR_STS_HOTPLUG_NMI ,Error STS hotplug NMI" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PCA_ENABLE ,Enable/disable the PCA in any TMS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GEN2_SPEED_DISABLE ,Gen 2 protocol speed disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GEN2_PROTOCOL_DISABLE ,Disable gen2 protocol and will force the use of Gen 1.1 protocol" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DEV_CAP_EXTENDED_TAG_FIELD_SIZE ,DEV capable extended tag field size" "5bit,8bit"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DIS_MA_TA_EP_MERGE ,Disables the logic which takes care of merging of EP/MA/TA" "No,Yes"
|
|
line.long 0x04 "PRIV_XP_CONFIG,Private XP Config"
|
|
bitfld.long 0x04 0.--1. " LOW_PWR_DURATION ,information logging for the health and performance counters" "TX_L0S,RX_L0S,L1,Idle"
|
|
textline " "
|
|
width 35.
|
|
rgroup.long 0xFB0++0x03
|
|
line.long 0x00 "PRIV_XP_DURATION_IN_LOW_PWR_100NS,Counts The Duration In Multiples Of 100ns For The Type Of Low Power Information"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
rgroup.long 0xFB4++0x03
|
|
line.long 0x00 "PRIV_XP_SKP_TIMEOUT,Counts The Duration In Multiples Of 100ns For The Type Of Low Power Information"
|
|
hexmask.long.word 0x00 13.--25. 1. " THRESHOLD_GEN2 ,Threshold GEN2"
|
|
hexmask.long.word 0x00 0.--12. 1. " THRESHOLD ,Threshold"
|
|
else
|
|
group.long 0xFB4++0x03
|
|
line.long 0x00 "PRIV_XP_SKP_TIMEOUT,Counts The Duration In Multiples Of 100ns For The Type Of Low Power Information"
|
|
hexmask.long.word 0x00 13.--25. 1. " THRESHOLD_GEN2 ,Threshold GEN2"
|
|
hexmask.long.word 0x00 0.--12. 1. " THRESHOLD ,Threshold"
|
|
endif
|
|
textline " "
|
|
group.long 0xFB8++0x03
|
|
line.long 0x00 "PRIV_XP_EIDLE_INFERENCE_TIMEOUT,Counts The Duration In Multiples Of 100ns For The Type Of Low Power Information"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIMEOUT_B ,UI window for electrical idle exit not detected in the Recover"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMEOUT_A ,UI window for COM not detected in the Recovery"
|
|
textline " "
|
|
width 25.
|
|
sif (cpuis("TEGRAX2"))
|
|
group.long 0xFBC++0x03
|
|
line.long 0x00 "SLOT_CONTROL_STATUS_HPC,Slot Control Status HPC Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " COMMAND ,Command"
|
|
hexmask.long.byte 0x00 8.--15. 1. " STATE ,State"
|
|
textline " "
|
|
eventfld.long 0x00 7. " STATE_CHANGE7 ,State change 7" "Not changed,Changed"
|
|
eventfld.long 0x00 6. " STATE_CHANGE6 ,State change 6" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 5. " STATE_CHANGE5 ,State change 5" "Not changed,Changed"
|
|
eventfld.long 0x00 4. " STATE_CHANGE4 ,State change 4" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 3. " STATE_CHANGE3 ,State change 3" "Not changed,Changed"
|
|
eventfld.long 0x00 2. " STATE_CHANGE2 ,State change 2" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 1. " STATE_CHANGE1 ,State change 1" "Not changed,Changed"
|
|
eventfld.long 0x00 0. " STATE_CHANGE0 ,State change 0" "Not changed,Changed"
|
|
group.long 0xFC4++0x07
|
|
line.long 0x00 "VEND_XP_LANEMAP1,Vendor XP Lane MAP 1"
|
|
bitfld.long 0x00 28.--31. " LANE_15 ,Lane 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " LANE_14 ,Lane 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " LANE_13 ,Lane 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " LANE_12 ,Lane 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " LANE_11 ,Lane 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " LANE_10 ,Lane 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " LANE_9 ,Lane 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " LANE_8 ,Lane 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "VEND_SS_1,Shadow Register Of SS 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " SSID ,SSID"
|
|
hexmask.long.word 0x04 0.--15. 1. " SSVID ,SSVID"
|
|
endif
|
|
sif (!cpuis("TEGRAX2"))
|
|
group.long 0xFC8++0x0B
|
|
line.long 0x00 "VEND_SHADOW,Shadow register of SS_1"
|
|
hexmask.long.word 0x00 16.--31. 1. " SS_1_SSID ,SS_1_SSID"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " SS_1_SSVID ,SS_1_SSVID"
|
|
line.long 0x04 "TX_MARGIN_MAP0_TX_AMP,Mapping of the Transmit Margin field in the Link Control 2 register"
|
|
bitfld.long 0x04 30.--31. " CTL ,CTL" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 24.--29. " CODE3 ,CODE3" "Init,,,,,,,,Mobile,,,,,,,,,,,,Desktop,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--21. " CODE2 ,CODE2" "Init,,,,,,,,,,Mobile,,,,,,,,,,,,,,Desktop,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--13. " CODE1 ,CODE1" "Init,,,,,,,,,,,,Mobile,,,,,,,,,,,,,,,,Desktop,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--5. " CODE0 ,CODE0" "Init,,,,,,,,,,,,Mobile,,,,,,,,,,,,,,,,,,,,Desktop,?..."
|
|
line.long 0x08 "TX_MARGIN_MAP1_TX_AMP,Mapping of the Transmit Margin field in the Link Control 2 register"
|
|
bitfld.long 0x08 30.--31. " CTL ,CTL" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 24.--29. " CODE7 ,CODE7" "Mobile,,,,Desktop,?..."
|
|
textline " "
|
|
bitfld.long 0x08 16.--21. " CODE6 ,CODE6" "Init,,Mobile,,,,,,Desktop,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8.--13. " CODE5 ,CODE5" "Init,,,,Mobile,,,,,,,,Desktop,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--5. " CODE4 ,CODE4" "Init,,,,,,Mobile,,,,,,,,,,Desktop,?..."
|
|
endif
|
|
textline " "
|
|
sif (cpuis("TEGRAK1"))
|
|
group.long 0xFD4++0x03
|
|
line.long 0x00 "ECTL_1_R1,ECTL_1_R1"
|
|
bitfld.long 0x00 28.--31. " TX_DRV_CNTL_1C ,TX_DRV_CNTL_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RX_QEYE_EN_1C ,RX_ QEYE_EN_1C" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " RX_WANDER_1C ,RX_WANDER_1C" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_TERM_CNTL_1C ,_RX_TERM_CNTL_1C" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_TERM_CNTL_1C ,TX_TERM_CNTL_1C" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TX_CMADJ_1C ,TX_CMADJ_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " TX_AMP_1C ,TX_AMP_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xFD8++0x03
|
|
line.long 0x00 "ECTL_1_R2,ECTL_1_R2"
|
|
bitfld.long 0x00 28.--31. " TX_DRV_CNTL_1C ,TX_DRV_CNTL_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20. " RX_QEYE_EN_1C ,RX_ QEYE_EN_1C" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " RX_WANDER_1C ,RX_WANDER_1C" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " RX_TERM_CNTL_1C ,_RX_TERM_CNTL_1C" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " TX_TERM_CNTL_1C ,TX_TERM_CNTL_1C" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TX_CMADJ_1C ,TX_CMADJ_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " TX_AMP_1C ,TX_AMP_1C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xFDC++0x07
|
|
line.long 0x00 "TIMEOUT2,Timeout 2 Register"
|
|
bitfld.long 0x00 0.--4. " MIN_L1_L2_IDLE_TIME ,Sets minimum amount of time we stay in L1/L2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "PRIV_MISC,Private Miscellaneous Register"
|
|
bitfld.long 0x04 31. " TMS_CLK_CLAMP_ENABLE ,Enables per-TMS XCLK/XTXCLK clamping" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x04 24.--30. 1. " CLK_CLAMP_THRESHOLD ,Number of contiguous nbref_clks (25MHz) after clamping"
|
|
textline " "
|
|
bitfld.long 0x04 23. " CTLR_CLK_CLAMP_ENABLE ,Enables per-controller XCLK/XTXCLK clamping" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--22. 1. " CTLR_CLK_CLAMP_THRESHOLD ,Number of contiguous nbref_clks (12MHz) after clamping"
|
|
sif (cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x04 4. " USE_EXT_CLKREQ ,Use EXT CLKREQ" "Not used,Used"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " PRSNT_MAP ,PRSNT MAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpuis("TEGRAX2"))
|
|
group.long 0xFE4++0x03
|
|
line.long 0x00 "BIST_CTRL_2,BIST Control 2 Register"
|
|
bitfld.long 0x00 31. " OVERRIDE_JTAG ,Internal JTAG register override" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " TX_CHAR_SPEED ,Speed of TXCHAR output" ",2.5Gbps,5.0Gbps,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " TXCHAR_MIN_EIDLE ,Force LTSSM to spend minimum time in E-idle" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TXCHAR_EIDLE_EXIT ,Transition from E-idle to compliance pattern" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXCHAR_EIDLE_ENTRY ,Transition from compliance pattern to E-idle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SHORT_LINK_TIMERS ,Shortened timers in LINK" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xFE8++0x03
|
|
line.long 0x00 "VEND_XP3,Symbol Alignment Error Handling Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SA_ERROR_LIMIT ,Specifies number of misaligned COM symbols"
|
|
group.long 0xFEC++0x03
|
|
line.long 0x00 "XP_CTL_1,Control Registers Used In XP"
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 31. " CYA_RP_INITIATED_WAKE_ON_TLP ,Initiated wake one TLP" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("TEGRAX1"))
|
|
bitfld.long 0x00 29.--30. " SPARE ,SPARE" "0,1,2,3"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 28.--30. " SPARE ,Spare" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " EXIT_L1_AT_CLKREQ_ASSERTION ,When set,ltssm will exit L1 when clkreq assertion happens" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " NEW_IOBIST_CTRL ,Enable control signals from iobist" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OLD_IOBIST_EN ,When set will enable old iobist,else it will enable new iobist" "New,Old"
|
|
textline " "
|
|
bitfld.long 0x00 19.--24. " EIOS_DEBOUNCE_TIMER ,Number of xclk for which rx_data_en signals need to be deasserted before asserting it again" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DISABLE_RX_LANE_AFTER_EIOS ,Disable rx_lane_en after EIOS is seen in any of the enabled lane during recovery" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ENABLE_DESKEW_FOR_SPDCH_NEGOTIATION ,LTSSM enable deskew in recovery" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BYPASS_CONFIG_PWRUP ,Bypass config powerup" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RESET_TS_CTRL_ON_ERROR ,Reset TS control on error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RX_EIDLE_EXIT_TIMER_IN_CONFIG ,RX EIDLE exit timer in config" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FORCE_RESET_IN_CONFIG ,Force reset in config" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LINK_RESIZE_PWRDN_CTL ,Link resize powerdown control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ALLOW_SPEED_CHANGE_FROM_L0S ,When set,LTSSM will initiate link speed/width/advertised rate change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PRESERVE_TX_PACKET_ON_DL_RETRAIN ,When set,LTSSM will wait for framer to be idle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PRESERVE_TX_PACKET_ON_RECOVERY ,Preserve TX packet on recovery" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PRESERVE_TX_PACKET_ON_WIDTH_CHANGE ,When set,LTSSM will wait for framer to be idle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PRESERVE_TX_PACKET_ON_SPEED_CHANGE ,When set,LTSSM will wait for framer to be idle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RESET_LANE_ENABLE_ORIG_IN_DETECT ,allow lane_enable_original to be reset in Detect state" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " IDLE_TO_L0_DELAY ,Number of clocks that the LTSSM will delay the transition from Recovery" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LWLO_HUNT_ON_BAD_TS1 ,LWLO HUNT on bad TS1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FORCE_SA_IN_CONFIG ,Enables symbol alignment" "Disabled,Enabled"
|
|
group.long 0xFF0++0x0F
|
|
line.long 0x00 "PRIV_XP_L1BEACON,Private XP L1 Beacon"
|
|
hexmask.long.byte 0x00 2.--9. 1. " N_EIE_SYMBOLS ,Number of EIE symbols sent in L1 Beacon Entry/Exist state"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX_BYP_CTRL ,TX bypass control" "Only L0,All Lanes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
line.long 0x04 "TIMEOUT3,Timeout 3 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " RX_L0S_IDLE_TIME_GEN2 ,Controls the amount of time LTSSM delays"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--23. 1. " RX_L0S_IDLE_TIME_GEN1 ,Controls the amount of time LTSSM delays"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " TX_L0S_IDLE_TIME ,Controls the minimum amount of time LTSSM stays in TX_L0S_IDLE state"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " RX_EIDLE_EXIT_DELAY ,Controls the amount of time the LTSSM delays" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " TX_EIDLE_EXIT_DELAY ,Controls the amount of time the LTSSM delays" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "RP_XP_CTL_2,XP Control 2 Register"
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
sif cpuis("TEGRAX2")
|
|
bitfld.long 0x08 24. " LOOPBACK_RATE_DEEMPH_CHECK_DIS ,Loopback rate deemph check disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 23. " RX_CAL_EN ,Hardware RX calibration in UPHY enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 22. " AUX_RX_IDLE_EN ,RX idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " OVERRIDE_AUX_RX_IDLE_EN ,Override for bit for AUX_RX_IDLE_EN enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " WAIT_FOR_LOCKDET_DURING_L1_EXIT ,Wait for lockdet during L1 exit" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x08 12.--19. 1. " ECO351987_HOLDOFF_CNTR_LIMIT ,Holdoff counter limit for counter that was added in ECO 351987"
|
|
textline " "
|
|
bitfld.long 0x08 11. " USE_QUALIFIED_TS_CTL_BITS ,Qualifies the training control bits in the transmitted TS1s/TS2s with the LTSSM state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " RELAXED_UNEXP_CPL_CHECK ,Relaxed unexpected completion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " LOOPBACK_FORCE_NOSCRAMBLE ,Loopback force nonscramble enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 8. " CONFIG_LINKSTART_REQUIRE_PAD_LANE_NUM ,Config link start require PAD lane num" "0,1"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " LOOPBACK_EXIT_THRESHOLD ,Maximum amount of time spent in loopback"
|
|
line.long 0x0C "VEND_XP_STATS2,Vendor XP States (NVIDIAs Implementation)"
|
|
hexmask.long.word 0x0C 0.--15. 1. " 8B10B_ERR_LANEMASK ,Each bit represent the corresponding logical lane"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "AFI"
|
|
base ad:0x01003800
|
|
width 18.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "AXI_BAR0_SZ_0,AXI BAR SIZE Register 0"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR0_SIZE ,The size of the address range associated with BAR0"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "AXI_BAR1_SZ_0,AXI BAR SIZE Register 1"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR1_SIZE ,The size of the address range associated with BAR1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "AXI_BAR2_SZ_0,AXI BAR SIZE Register 2"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR2_SIZE ,The size of the address range associated with BAR2"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "AXI_BAR3_SZ_0,AXI BAR SIZE Register 3"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR3_SIZE ,The size of the address range associated with BAR3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "AXI_BAR4_SZ_0,AXI BAR SIZE Register 4"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR4_SIZE ,The size of the address range associated with BAR4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "AXI_BAR5_SZ_0,AXI BAR SIZE Register 5"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR5_SIZE ,The size of the address range associated with BAR5"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "AXI_BAR6_SZ_0,AXI BAR SIZE Register 6"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR6_SIZE ,The size of the address range associated with BAR6"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "AXI_BAR7_SZ_0,AXI BAR SIZE Register 7"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR7_SIZE ,The size of the address range associated with BAR7"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "AXI_BAR8_SZ_0,AXI BAR SIZE Register 8"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " AXI_BAR8_SIZE ,The size of the address range associated with BAR8"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "AXI_BAR0_START_0,AXI BAR START Registers, 0"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR0_START ,The start of AXI address space for BAR0"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "AXI_BAR1_START_0,AXI BAR START Registers, 1"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR1_START ,The start of AXI address space for BAR1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "AXI_BAR2_START_0,AXI BAR START Registers, 2"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR2_START ,The start of AXI address space for BAR2"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "AXI_BAR3_START_0,AXI BAR START Registers, 3"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR3_START ,The start of AXI address space for BAR3"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "AXI_BAR4_START_0,AXI BAR START Registers, 4"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR4_START ,The start of AXI address space for BAR4"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "AXI_BAR5_START_0,AXI BAR START Registers, 5"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR5_START ,The start of AXI address space for BAR5"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "AXI_BAR6_START_0,AXI BAR START Registers, 6"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR6_START ,The start of AXI address space for BAR6"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "AXI_BAR7_START_0,AXI BAR START Registers, 7"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR7_START ,The start of AXI address space for BAR7"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "AXI_BAR8_START_0,AXI BAR START Registers, 8"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " AXI_BAR8_START ,The start of AXI address space for BAR8"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "FPCI_BAR0_0,FPCI BAR Register 0"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR0_START ,The start of FPCI address space mapped into the BAR0 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR0_ACCESS_TYPE ,Indicates if the address region is memory mapped versus configuration or I/O space" "IO/config,Memory mapped"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "FPCI_BAR1_0,FPCI BAR Register 1"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR1_START ,The start of FPCI address space mapped into the BAR1 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR1_ACCESS_TYPE ,Indicates if the address region is memory mapped versus configuration or I/O space" "IO/config,Memory mapped"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "FPCI_BAR2_0,FPCI BAR Register 2"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR2_START ,The start of FPCI address space mapped into the BAR2 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR2_ACCESS_TYPE ,Indicates if the address region is memory mapped versus configuration or I/O space" "IO/config,Memory mapped"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "FPCI_BAR3_0,FPCI BAR Register 3"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR3_START ,The start of FPCI address space mapped into the BAR3 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR3_ACCESS_TYPE ,Indicates if the address region is memory mapped versus configuration or I/O space" "IO/config,Memory mapped"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FPCI_BAR4_0,FPCI BAR Register 4"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR4_START ,The start of FPCI address space mapped into the BAR4 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR4_ACCESS_TYPE ,Indicates if the address region is memory mapped versus configuration or I/O space" "IO/config,Memory mapped"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "FPCI_BAR5_0,FPCI BAR Register 5"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR5_START ,The start of FPCI address space mapped into the BAR5 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR5_ACCESS_TYPE ,Indicates if the address region is memory mapped versus configuration or I/O space" "IO/config,Memory mapped"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "FPCI_BAR6_0,FPCI BAR Register 6"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR6_START ,The start of FPCI address space mapped into the BAR6 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR6_ACCESS_TYPE ,Indicates if the address region is memory mapped versus configuration or I/O space" "IO/config,Memory mapped"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "FPCI_BAR7_0,FPCI BAR Register 7"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR7_START ,The start of FPCI address space mapped into the BAR7 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR7_ACCESS_TYPE ,Indicates if the address region is memory mapped versus configuration or I/O space" "IO/config,Memory mapped"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "FPCI_BAR8_0,FPCI BAR Register 8"
|
|
hexmask.long 0x00 4.--31. 0x10 " FPCI_BAR8_START ,The start of FPCI address space mapped into the BAR8 range of PCI memory space"
|
|
bitfld.long 0x00 0. " FPCI_BAR8_ACCESS_TYPE ,Indicates if the address region is memory mapped versus configuration or I/O space" "IO/config,Memory mapped"
|
|
textline " "
|
|
width 19.
|
|
sif cpuis("TEGRAX2")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "AFI_MSI_BAR_SZ_0,AFI MSI BAR SZ 0"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " MSI_BAR_SIZE ,The size of the address range associated with MSI BAR is in 4K increments"
|
|
endif
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "MSI_FPCI_BAR_ST_0,MSI FPCI BAR Start"
|
|
hexmask.long 0x00 4.--31. 1. " MSI_FPCI_BAR_START ,The start of upstream FPCI address space for MSI BAR"
|
|
line.long 0x04 "MSI_AXI_BAR_ST_0,MSI AXI BAR Start"
|
|
hexmask.long.tbyte 0x04 12.--31. 1. " MSI_AXI_BAR_START ,The start of upstream AXI address space for MSI BAR"
|
|
textline " "
|
|
width 16.
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "MSI_VEC0_0,MSI Vector Register 0"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "MSI_VEC1_0,MSI Vector Register 1"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "MSI_VEC2_0,MSI Vector Register 2"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "MSI_VEC3_0,MSI Vector Register 3"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "MSI_VEC4_0,MSI Vector Register 4"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "MSI_VEC5_0,MSI Vector Register 5"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "MSI_VEC6_0,MSI Vector Register 6"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "MSI_VEC7_0,MSI Vector Register 7"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "MSI_EN_VEC0_0,MSI Enable Vector Register 0"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "MSI_EN_VEC1_0,MSI Enable Vector Register 1"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "MSI_EN_VEC2_0,MSI Enable Vector Register 2"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "MSI_EN_VEC3_0,MSI Enable Vector Register 3"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "MSI_EN_VEC4_0,MSI Enable Vector Register 4"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "MSI_EN_VEC5_0,MSI Enable Vector Register 5"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "MSI_EN_VEC6_0,MSI Enable Vector Register 6"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "MSI_EN_VEC7_0,MSI Enable Vector Register 7"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CONFIGURATION_0,AFI Configuration"
|
|
bitfld.long 0x00 31. " CLKEN_OVERRIDE ,Override the clock enable in case of malfunction" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 23. " SPARSE_WSTRB ,Diagnostic bit for enabling sparse WSTRB" "0,1"
|
|
bitfld.long 0x00 22. " UNALIGNED_BYTE_ACCESS ,Diagnostic bit for unaligned byte access" "0,1"
|
|
bitfld.long 0x00 21. " UPSTREAM_RAW_RESPAW_MSIAW ,Diagnostic bit for upstream RAW, RESPAW, MSIAW issue" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " PW_NO_DEVSEL_ERR_CYA ,Disable detection of DECERR due to no devsel" "No,Yes"
|
|
rbitfld.long 0x00 18. " INITIATOR_READ_IDLE ,Status reads on AFI upstream" "Busy,Idle"
|
|
rbitfld.long 0x00 17. " INITIATOR_WRITE_IDLE ,Status write on AFI upstream" "Busy,Idle"
|
|
textline " "
|
|
sif cpuis("TEGRAX2")
|
|
rbitfld.long 0x00 16. " PE2_PRSNT_L_IN ,Card is present in PCIe slot 2" "Present,Not present"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " WDATA_LEAD_CYA ,Enable handling of write data ahead of requests on mselect" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WR_INTRLV_CYA ,Enable handling of interleaved write requests on mselect" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " PE1_PRSNT_L_IN ,PCIe card present in slot 0" "Present,Not present"
|
|
rbitfld.long 0x00 12. " PE0_PRSNT_L_IN ,PCIe card present in slot 1" "Present,Not present"
|
|
rbitfld.long 0x00 11. " TARGET_READ_IDLE ,Status reads to AFI target" "Busy,Idle"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " TARGET_WRITE_IDLE ,Status write to AFI target" "Busy,Idle"
|
|
rbitfld.long 0x00 9. " MSI_VEC_EMPTY ,Provides status on MSI Vector registers" "No valid,Valid"
|
|
bitfld.long 0x00 7. " UFPCI_MSIAW ,MSI After Write ordering rule" "Default,MSI Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " UFPCI_PWPASSPW ,Input to upstream FPCI" "Not send,Send"
|
|
bitfld.long 0x00 5. " UFPCI_PASSPW ,Allow upstream FPCI reads to pass writes" "No Allowed,Allowed"
|
|
bitfld.long 0x00 4. " UFPCI_PWPASSNPW ,Allow upstream FPCI PWs to pass NPWs" "Not Allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DFPCI_PWPASSNPW ,Allow downstream FPCI PWs to pass NPWs" "Not Allowed,Allowed"
|
|
bitfld.long 0x00 2. " DFPCI_RSPPASSPW ,Allow downstream FPCI responses to pass writes" "Not allowed,Allowed"
|
|
bitfld.long 0x00 1. " DFPCI_PASSPW ,Allow downstream FPCI reads to pass writes" "Not Allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN_FPCI ,FPCI device block Enable" "Disabled,Enabled"
|
|
textline " "
|
|
width 20.
|
|
group.long 0xb0++0x1B
|
|
line.long 0x00 "FPCI_ERROR_MASKS_0,FPCI Error Masks"
|
|
bitfld.long 0x00 2. " MASK_FPCI_MASTER_ABORT ,Allow FPCI error to be forwarded to AXI response on Master Abort error" "Return AXI OKAY,Forward error"
|
|
bitfld.long 0x00 1. " MASK_FPCI_DATA_ERROR ,Allow FPCI error to be forwarded to AXI response on Data Error" "Return AXI OKAY,Forward error"
|
|
bitfld.long 0x00 0. " MASK_FPCI_TARGET_ABORT ,Allows an FPCI error to be forwarded to AXI response on Target Abort error" "Return AXI OKAY,Forward error"
|
|
line.long 0x04 "INTR_MASK_0,Interrupt Masks"
|
|
bitfld.long 0x04 8. " MSI_MASK ,MSI to MPCORE gated by mask" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " INT_MASK ,Interrupt to MPCORE gated by mask" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "INTR_CODE_0,Interrupt Code"
|
|
bitfld.long 0x08 0.--4. " INT_CODE ,Interrupt Code" "Clear,AXI Slave error,AXI Decode error,PCIe target abort/data error,PCIe master abort,Write to NPW address region,PCIe 2.0 Sideband message,FPCI Decode error,AXI Decode error,FPCI Timeout,Slot Present Pin Change,Slot Clock Request Change,TMS Clock Clamp Change,TMS Ready for power down,Peer-to-peer error,?..."
|
|
line.long 0x0C "INTR_SIGNATURE_0,Interrupt Signature"
|
|
hexmask.long 0x0C 2.--31. 0x04 " INT_INFO ,Interrupt info - For interrupt codes FPCI memory space or AXI space"
|
|
bitfld.long 0x0C 0. " DIR ,Indicates the direction of the AXI/FPCI transaction" "Write,Read"
|
|
line.long 0x10 "UPPER_FPCI_ADDR_0,Upper FPCI Address"
|
|
bitfld.long 0x10 16.--17. " P2P_ERR_RESP ,This bits are for the captured endpoint device error response" "0,1,2,3"
|
|
hexmask.long.byte 0x10 0.--7. 0x01 " INT_INFO_UPPER ,Upper byte of captured FPCI address"
|
|
line.long 0x14 "SM_INTR_ENABLE_0,Sideband Message Interrupt Enable"
|
|
sif cpuis("TEGRAX2")
|
|
bitfld.long 0x14 15. " ENABLE_MESSAGE[15] ,Interrupt message enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 14. " [14] ,Interrupt(Root Port Interrupt Deassertion) message enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x14 14. " ENABLE_MESSAGE[14] ,Interrupt(Root Port Interrupt Deassertion) message enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x14 13. " [13] ,Interrupt(Root Port Interrupt Assertion) message enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " [12] ,Hotplug SCI assertion message enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " [11] ,PME assertion message enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 10. " [10] ,Error(Uncorrectable Fatal Error) message enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " [9] ,Error(Uncorrectable Non-Fatal Error) message enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " [8] ,Interrupt(INTB Deassertion) message enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 7. " [7] ,Error(Correctable Error) message enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 6. " [6] ,Interrupt(INTD Deassertion) message enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " [5] ,Interrupt(INTC Deassertion) message enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " [4] ,Interrupt(INTA Deassertion) message enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " [3] ,Interrupt(INTD Assertion) message enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " [2] ,Interrupt(INTC Assertion) message enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " [1] ,Interrupt(INTB Assertion) message enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " [0] ,Interrupt(INTA Assertion) message enable" "Disabled,Enabled"
|
|
textline " "
|
|
line.long 0x18 "AFI_INTR_ENABLE_0,AFI Interrupt Enable"
|
|
sif cpuis("TEGRAX2")
|
|
bitfld.long 0x18 13. " EN_FATAL_ERR ,Enable bit for fatal interrupt reporting to SCE master" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 12. " EN_P2P_ERR ,Enable bit for interrupt code 14" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " EN_RDY4PD_SENSE ,Enable bit for interrupt code 13" "Disabled,Enabled"
|
|
bitfld.long 0x18 10. " EN_CLKCLAMP_SENSE ,Enable bit for interrupt code 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " EN_PE_CLKREQ_SENSE ,Enable bit for interrupt code 11" "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " EN_PE_PRSNT_SENSE ,Enable bit for interrupt code 10" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " EN_FPCI_TIMEOUT ,Enable bit for interrupt code 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 6. " EN_AXI_DECERR ,Enable bit for interrupt code 8" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " EN_DFPCI_DECERR ,Enable bit for interrupt code 7" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " EN_TGT_WRERR ,Enable bit for interrupt code 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 3. " EN_TGT_DECERR ,Enable bit for interrupt code 4" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " EN_TGT_SLVERR ,Enable bit for interrupt code 3" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " EN_INI_DECERR ,Enable bit for interrupt code 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0. " EN_INI_SLVERR ,Enable bit for interrupt code 1" "Disabled,Enabled"
|
|
group.long 0xEC++0x07
|
|
line.long 0x00 "PCIE_THROTTLE_0,PCIe Throttle"
|
|
bitfld.long 0x00 31. " SM2PCIE_THROT_EN ,Override THERM MGMT" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 4.--15. 1. " SM2PCIE_THROT_PERIOD ,Override THERM MGMT period"
|
|
bitfld.long 0x00 0.--2. " SM2PCIE_THROT_DUTY_CYCLE ,Override THERM MGMT duty cycle" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "PME_0,PCIe PME"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
rbitfld.long 0x04 15. " TMS0C22SM_PRESENCE_STATE ,PCIe Link Presence State" "No,Yes"
|
|
rbitfld.long 0x04 14. " TMS0C22SM_PME_ACK ,:PCIe Endpoint PME Ack" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x04 13. " TMS0C22SM_PME ,PCIe Endpoint PME message" "No,Yes"
|
|
bitfld.long 0x04 12. " SM2TMS0C2_PME_TO ,SM to PCIe PME Turn Off" "No,Yes"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x04 11. " TMS0C12SM_PRESENCE_STATE ,PCIe Link Presence State" "No,Yes"
|
|
rbitfld.long 0x04 10. " TMS0C12SM_PME_ACK ,PCIe Endpoint PME Ack" "No,Yes"
|
|
rbitfld.long 0x04 9. " TMS0C12SM_PME ,PCIe Endpoint PME message" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 8. " SM2TMS0C1_PME_TO ,SM to PCIe PME Turn Off" "No,Yes"
|
|
rbitfld.long 0x04 6. " TMS0C02SM_PRESENCE_STATE ,PCIe Link Presence State" "No,Yes"
|
|
rbitfld.long 0x04 5. " TMS0C02SM_PME_ACK ,PCIe Endpoint PME Ack" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x04 4. " TMS0C02SM_PME ,PCIe Endpoint PME message" "No,Yes"
|
|
bitfld.long 0x04 0. " SM2TMS0C0_PME_TO ,SM to PCIe PME Turn Off" "No,Yes"
|
|
rgroup.long 0xf4++0x03
|
|
line.long 0x00 "REQ_PENDING_0,Request Pending"
|
|
sif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 11. " TMS0C22SM_NONISO_PENDING ,Non-ISO request is pending from PCIe to FPCI" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " TMS0C22SM_ISO_PENDING ,ISO request is pending from PCIE to FPCI" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TMS0C22SM_NONCOH_REQUEST_PEND ,Non-coherent request is pending from PCIe to FPCI" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " TMS0C22SM_COH_REQUEST_PEND ,Coherent request is pending from PCIe to FPCI" "Not pending,Pending"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " TMS0C12SM_NONISO_PENDING ,Non-ISO request is pending from PCIe to FPCI" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " TMS0C12SM_ISO_PENDING ,ISO request is pending from PCIE to FPCI" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " TMS0C12SM_NONCOH_REQUEST_PEND ,Non-coherent request is pending from PCIe to FPCI" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TMS0C12SM_COH_REQUEST_PEND ,Coherent request is pending from PCIe to FPCI" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " TMS0C02SM_NONISO_PENDING ,Non-ISO request is pending from PCIe to FPCI" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " TMS0C02SM_ISO_PENDING ,ISO request is pending from PCIe to FPCI" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TMS0C02SM_NONCOH_REQUEST_PEND ,Non-coherent request is pending from PCIe to FPCI" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " TMS0C02SM_COH_REQUEST_PEND ,Coherent request is pending from PCIe to FPCI" "Not pending,Pending"
|
|
group.long 0xF8++0x13
|
|
line.long 0x00 "PCIE_CONFIG_0,PCIe Config"
|
|
sif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 31. " PCIEC2_CLKREQ_GPIO ,Whether CLKREQ is GPIO or not" "0,1"
|
|
bitfld.long 0x00 30. " PCIEC1_CLKREQ_GPIO ,Whether CLKREQ is GPIO or not" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PCIEC0_CLKREQ_GPIO ,Whether CLKREQ is GPIO or not" "0,1"
|
|
bitfld.long 0x00 24.--28. " UNITID_T0C2 ,T0C2 Upstream FPCI Unit ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " SM2TMS0_XBAR_CONFIG ,SM configuration of PCIe crossbar" "x4_x1 configuration,x2_x1 configuration,x1_x1 configuration,?..."
|
|
else
|
|
bitfld.long 0x00 20.--23. " SM2TMS0_XBAR_CONFIG ,SM configuration of PCIe crossbar" "x2_x1 configuration,x4_x1 configuration,?..."
|
|
endif
|
|
bitfld.long 0x00 12.--16. " UNITID_T0C1 ,T0C1 Upstream FPCI Unit ID HyperTransport, upstream FPCI request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--8. " UNITID_T0C0 ,T0C0 Upstream FPCI Unit ID HyperTransport, upstream FPCI request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
sif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 3. " PCIEC2_DISABLE_DEVICE ,Disable PCIe Controller 2" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " PCIEC1_DISABLE_DEVICE ,Disable PCIe Controller 1" "No,Yes"
|
|
bitfld.long 0x00 1. " PCIEC0_DISABLE_DEVICE ,Disable PCIe Controller 0" "No,Yes"
|
|
bitfld.long 0x00 0. " SM2TGIO_SLOT_EMPTY_PD_CYA ,Indicates PCIe slot empty" "Not empty,Empty"
|
|
line.long 0x04 "REV_ID_0,Revision ID"
|
|
bitfld.long 0x04 1. " CFG_REVID_WRITE_ENABLE ,Write Enable for PCI backdoor rev ID override value" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CFG_REVID_OVERRIDE ,Override for PCI config revision ID read-only register" "No override,Override"
|
|
line.long 0x08 "TOM_0,Top of Memory Limit"
|
|
hexmask.long.word 0x08 16.--29. 1. " DLDT2ALL_TOM2 ,Top of Memory Limit 2"
|
|
hexmask.long.word 0x08 0.--11. 1. " DLDT2ALL_TOM1 ,Top of Memory Limit 1"
|
|
line.long 0x0C "FUSE_0,PCIe Fuse"
|
|
sif cpuis("TEGRAX2")
|
|
bitfld.long 0x0C 12.--14. " FUSE_PCIE_WIDTH_T0C2 ,Configure PCIe 2" "x1,x2,x4,x8,x16,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 8.--10. " FUSE_PCIE_WIDTH_T0C1 ,Configure PCIe 1" "x1,x2,x4,x8,x16,?..."
|
|
bitfld.long 0x0C 4.--6. " FUSE_PCIE_WIDTH_T0C0 ,Configure PCIe 0" "x1,x2,x4,x8,x16,?..."
|
|
bitfld.long 0x0C 2. " FUSE_PCIE_T0_GEN2_DIS ,Disable Gen 2 capability of PCIe" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " FUSE_PCIE_SLI_DIS ,Disable SLI capability for the GPU" "No,Yes"
|
|
textline " "
|
|
line.long 0x10 "PMU_0,PMU Interface"
|
|
rbitfld.long 0x10 24. " CTLR_T0_C1_2PMU_TOG ,PMU toggle response from PCIe" "Not toggled,Toggled"
|
|
rbitfld.long 0x10 20.--23. " CTLR_T0_C1_2PMU_STATUS ,PMU Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x10 16. " CTLR_T0_C0_2PMU_TOG ,PMU toggle response from PCIe" "Not toggled,Toggled"
|
|
textline " "
|
|
rbitfld.long 0x10 12.--15. " CTLR_T0_C0_2PMU_STATUS ,PMU Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8.--11. " PMU2CTLR_T0_C1_LOAD_INDICATOR_SCALE ,PMU Load Indicator Scale for T0C1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 4.--7. " PMU2CTLR_T0_C0_LOAD_INDICATOR_SCALE ,PMU Load Indicator Scale for T0C0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 0. " PMU2ALL_LI_UPDATE_FAST_TOG ,PMU Load Indicator Enable" "Disabled,Enabled"
|
|
textline " "
|
|
width 34.
|
|
group.long 0x10C++0x07
|
|
line.long 0x00 "PCIE_CLK_CONFIG_STATUS_0,PCIE2 CLK Config/Status"
|
|
rbitfld.long 0x00 24.--27. " PCIE2CLK_TMS0GRP2_PAD_MACRO_CLK_SEL ,Clock select to pad macro" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
rbitfld.long 0x00 20.--23. " PCIE2CLK_TMS0GRP1_PAD_MACRO_CLK_SEL ,Clock select to pad macro" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 16.--19. " PCIE2CLK_TMS0GRP0_PAD_MACRO_CLK_SEL ,Clock select to pad macro" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("TEGRAX2")
|
|
rbitfld.long 0x00 15. " PCIE2CLK_TMS0C2_SEL_XTXCLK1X_GEN2 ,Request to select Gen2 speed clock for T0C2 XTXCLK1X" "No requested,Requested"
|
|
rbitfld.long 0x00 14. " PCIE2CLK_TMS0C2_DIS_XTXCLK1X ,Request to gate T0C2 XTXCLK1X" "No requested,Requested"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 13. " PCIE2CLK_TMS0C1_DIS_XTXCLK1X ,Request to gate T0C1 XTXCLK1X" "No requested,Requested"
|
|
rbitfld.long 0x00 12. " PCIE2CLK_TMS0C0_DIS_XTXCLK1X ,Request to gate T0C0 XTXCLK1X" "No requested,Requested"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " PCIE2CLK_TMS0_CLAMP_CLK_L1 ,Request to gate TMS/FPCI clocks" "No requested,Requested"
|
|
rbitfld.long 0x00 10. " PCIE2CLK_TMS0C1_SEL_XTXCLK1X_GEN2 ,Request to select Gen2 speed clock for T0C1 XTXCLK1X" "No requested,Requested"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " PCIE2CLK_TMS0C0_SEL_XTXCLK1X_GEN2 ,Request to select Gen2 speed clock for T0C0 XTXCLK1X" "No requested,Requested"
|
|
rbitfld.long 0x00 8. " PCIE2CLK_TMS0_SEL_XCLK_GEN2 ,Request to select Gen2 speed clock for XCLK" "No requested,Requested"
|
|
textline " "
|
|
sif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 6. " CLK2PCIE_TMS0C2_OFF_XTXCLK1X ,Acknowledge to disable T0C1 XTXCLK1X request" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 5. " CLK2PCIE_TMS0C2_RDY_XTXCLK1X_GEN2 ,Acknowledge to select T0C1 XTXCLK1X Gen2 request" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " CLK2PCIE_TMS0C1_OFF_XTXCLK1X ,Acknowledge to disable T0C1 XTXCLK1X request" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLK2PCIE_TMS0C1_RDY_XTXCLK1X_GEN2 ,Acknowledge to select T0C1 XTXCLK1X Gen2 request" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 2. " CLK2PCIE_TMS0C0_OFF_XTXCLK1X ,Acknowledge to disable T0C0 XTXCLK1X" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLK2PCIE_TMS0C0_RDY_XTXCLK1X_GEN2 ,Acknowledge to select T0C0 XTXCLK1X Gen2 request" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 0. " CLK2PCIE_TMS0_RDY_XCLK_GEN2 ,Acknowledge to select XCLK Gen2 request" "Not acknowledged,Acknowledged"
|
|
line.long 0x04 "PEX0_CTRL_0,PCIe PHY And Sideband Signal Interface"
|
|
bitfld.long 0x04 4. " PEX0_REFCLK_OVERRIDE_EN ,PEX0 enable to override refclk to be enabled always when PEX0_REFCLK_EN is set" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " PEX0_REFCLK_EN ,PEX0 enable to clkout pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PEX0_CLKREQ_EN ,PEX0 enable clkreq to control clkout pad" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PEX0_REFCLK_EN ,PEX0 external pe0_rst_l register" "No reset,Reset"
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "PEX0_STATUS_0,PCIe PHY Status"
|
|
bitfld.long 0x00 0. " PEX0_CLKREQ_L ,Status of the PEX0 pe0_clkreq_l input" "0,1"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "PEX1_CTRL_0,PCIe PHY And Sideband Signal Interface"
|
|
bitfld.long 0x00 4. " PEX1_REFCLK_OVERRIDE_EN ,PEX1 enable to override refclk to be enabled always when PEX1_REFCLK_EN is set" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PEX1_REFCLK_EN ,PEX1 enable to clkout pad" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PEX1_CLKREQ_EN ,PEX1 enable clkreq to control clkout pad" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PEX1_RST_L ,PEX1 external pe1_rst_l register" "Disabled,Enabled"
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "PEX0_STATUS_0,PCIe PHY Status"
|
|
bitfld.long 0x00 0. " PEX1_CLKREQ_L ,Status of the PEX1 pe1_clkreq_l input" "0,1"
|
|
textline " "
|
|
rgroup.long 0x158++0x07
|
|
line.long 0x00 "INITIATOR_ISO_PW_RESP_PENDING_0,Initiator ISO PW Response Pending"
|
|
sif cpuis("TEGRAX2")
|
|
hexmask.long.byte 0x00 16.--23. 1. " NUM_INITIATOR_ISO_PW_RESP_PEND_T0C2 ,Number of pending initiator ISO PW responses for controller 2"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 8.--15. 1. " NUM_INITIATOR_ISO_PW_RESP_PEND_T0C1 ,Number of pending initiator ISO PW responses for controller 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NUM_INITIATOR_ISO_PW_RESP_PEND_T0C0 ,Number of pending initiator ISO PW responses for controller 0"
|
|
line.long 0x04 "INITIATOR_NISO_PW_RESP_PENDING_0,Initiator Non-ISO PW Response Pending"
|
|
sif cpuis("TEGRAX2")
|
|
hexmask.long.byte 0x04 16.--23. 1. " NUM_INITIATOR_NISO_PW_RESP_PEND_T0C2 ,Number of pending initiator ISO PW responses for controller 2"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x04 8.--15. 1. " NUM_INITIATOR_NISO_PW_RESP_PEND_T0C1 ,Number of pending initiator NISO PW responses for controller 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " NUM_INITIATOR_NISO_PW_RESP_PEND_T0C0 ,Number of pending initiator NISO PW responses for controller 0"
|
|
textline " "
|
|
width 22.
|
|
group.long 0x160++0x17
|
|
line.long 0x00 "PLLE_CONTROL_0,PLLE Controls"
|
|
bitfld.long 0x00 9. " BYPASS_PADS2PLLE_CONTROL ,Overrides PCIe PADS CLKREQ control of the PLLE" "No override,Override"
|
|
bitfld.long 0x00 8. " BYPASS_PCIE2PLLE_CONTROL ,Overrides PCIe2 CLOCK CLAMP control of the PLLE" "No override,Override"
|
|
bitfld.long 0x00 1. " PADS2PLLE_CONTROL_EN ,PADS2PLLE Control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PCIE2PLLE_CONTROL_EN ,PCIE2PLLE Control enable" "Disabled,Enabled"
|
|
line.long 0x04 "BUST_CONTROL_0,Bus Trace Module Controls"
|
|
rbitfld.long 0x04 21. " PCIE_RXL_BUST_TRIG_OUT0_T0 ,Bus trigger from bus trace module in PCIE2" "No trigger,Trigger"
|
|
bitfld.long 0x04 20. " TRACE_EXTERNAL_START ,Start signal to bus trace module in PCIE2" "No trigger,Trigger"
|
|
bitfld.long 0x04 16.--17. " PCIE_RXL_BUST_BUS_TRACE_MUX_SEL_T0 ,MUX select to bus trace module in PCIE2" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " CHIP_ID ,Chip ID to bus trace module in PCIE2"
|
|
line.long 0x08 "PEXBIAS_CTRL_0,PEXBIAS_CTRL_0"
|
|
bitfld.long 0x08 0. " PEX_BIAS_PWRD ,PEX clock bias pad power down" "0,1"
|
|
line.long 0x0C "P2PBOM_CTRL_0,P2PBOM_CTRL_0"
|
|
hexmask.long.tbyte 0x0C 0.--19. 1. " P2P_BASE ,Peer-to-peer Bottom of Memory"
|
|
line.long 0x10 "P2PTOM_CTRL_0,P2PTOM_CTRL_0"
|
|
hexmask.long.tbyte 0x10 0.--19. 1. " P2P_LIMIT ,Peer-to-peer Top of Memory"
|
|
line.long 0x14 "CLKGATE_HYSTERESIS_0,Clock Gate Hysteresis"
|
|
hexmask.long.byte 0x14 0.--7. 1. " CLK_DISABLE_CNT ,Number of AFI clock cycles to wait after clock gating criteria is met to disable the AFI/FPCI clocks"
|
|
group.long 0x180++0x0B
|
|
line.long 0x00 "SPARE_REG0_0,Spare Register"
|
|
line.long 0x04 "A2F_UFPCI_CFG0_0,UFPCI Configuration Register 0"
|
|
hexmask.long.byte 0x04 24.--31. 1. " STATIC_WAIT_IDLE_CNTR ,Static wait idle control"
|
|
bitfld.long 0x04 16.--18. " STATIC_UFPCI_UFA_STARVE_CNTR_PRI1 ,Static UFPCI UFA starve control PRI1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 12.--15. " STATIC_UFPCI_UFA_STARVE_CNTR_PRI0 ,Static UFPCI UFA starve control PRI0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " STATIC_UFPCI_RR_BURST_SZ_PRI1 ,Static_UFPCI RR burst SZ PRI1" "0,1,2,3"
|
|
bitfld.long 0x04 8.--9. " STATIC_UFPCI_RR_BURST_SZ_PRI0 ,Static UFPCI RR burst SZ PRI0" "0,1,2,3"
|
|
bitfld.long 0x04 7. " STATIC_WAIT_CLAMP_EN ,Static wait clamp enable" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 6. " STATIC_UFPCI_UFA_DYN_BLOCK_EN ,Static UFPCI UFA DYN block enable" "0,1"
|
|
bitfld.long 0x04 5. " STATIC_UFPCI_UFA_BLK_COHERENT ,Static UFPCI UFA BLK coherent" "0,1"
|
|
bitfld.long 0x04 2.--4. " STATIC_UFPCI_BLOCK_CMD_THRESHOLD ,Static UFPCI block CMD threshold" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 1. " STATIC_CYA_UFA_ARB ,Static CYA UFA ARB" "0,1"
|
|
bitfld.long 0x04 0. " STATIC_CYA_BACK2BACK_UPSTREAM_BLOCK ,Static CYA back to back upstream block" "0,1"
|
|
line.long 0x08 "A2F_UFPCI_CFG1_0,UFPCI Configuration Register 1"
|
|
hexmask.long.byte 0x08 0.--7. 1. " STATIC_WAIT_UNCLAMP_CNTR ,Static wait unclamp control"
|
|
textline " "
|
|
group.long 0x7CC++0x03
|
|
line.long 0x00 "AFI_MCCIF_FIFOCTRL_0,Memory Client Interface FIFO Control And Clock Gating Control Register"
|
|
bitfld.long 0x00 20. " AFI_RCLK_OVR_MODE ,RCLK override mode" "Legacy,ON"
|
|
bitfld.long 0x00 19. " AFI_WCLK_OVR_MODE ,WCLK override mode" "Legacy,ON"
|
|
bitfld.long 0x00 18. " AFI_CCLK_OVERRIDE ,Clock override" "Not override,Override"
|
|
textline " "
|
|
bitfld.long 0x00 17. " AFI_RCLK_OVERRIDE ,Clock override" "Not override,Override"
|
|
bitfld.long 0x00 16. " AFI_WCLK_OVERRIDE ,Clock override" "Not override,Override"
|
|
bitfld.long 0x00 3. " AFI_MCCIF_RDCL_RDFAST ,AFI_MCCIF_RDCL_RDFAST" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AFI_MCCIF_WRMC_CLLE2X ,AFI_MCCIF_WRMC_CLLE2X" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AFI_MCCIF_RDMC_RDFAST ,AFI_MCCIF_RDMC_RDFAST" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AFI_MCCIF_WRCL_MCLE2X ,AFI_MCCIF_WRCL_MCLE2X" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "I2C Controller"
|
|
tree "I2C-1"
|
|
base ad:0x7000C000
|
|
width 20.
|
|
if (((per.l(ad:0x7000C000))&0x10)==0x10)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CNFG_0,IC Controller Configuration Register"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Single,Multi"
|
|
bitfld.long 0x00 16. " HS_RND_TRIP_DLY_EFFECT ,Diagnostic bit to disable round trip delay effect on data rate in HS mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " MSTR_CLR_BUS_ON_TIMEOUT ,I2C master force clock low on timeout" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " DEBOUNCE_CNT ,De-bounce period for SDA and SCL lines" "No Debounce,2T,4T,6T,8T,10T,12T,14T"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NEW_MASTER_FSM ,Maintained for compatibility sake" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PACKET_MODE_EN ,Initiate transfer in packet mode" "NOP,GO"
|
|
bitfld.long 0x00 9. " SEND ,Master initiates the transaction in normal mode" "NOP,GO"
|
|
textline " "
|
|
bitfld.long 0x00 8. " NOACK ,No ACK mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CMD2 ,Read/Write Command for Slave 2" "Write,Read"
|
|
bitfld.long 0x00 6. " CMD1 ,Read/Write Command for Slave 1" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 5. " START ,Send Start byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SLV2 ,Enables a two slave transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--3. " LENGTH ,Number of bytes to be transmitted per transaction" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " A_MOD ,7-bit or a 10-bit slave address" "7-bit address,10-bit address"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CNFG_0,IC Controller Configuration Register"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Single,Multi"
|
|
bitfld.long 0x00 16. " HS_RND_TRIP_DLY_EFFECT ,Diagnostic bit to disable round trip delay effect on data rate in HS mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " MSTR_CLR_BUS_ON_TIMEOUT ,I2C master force clock low on timeout" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " DEBOUNCE_CNT ,De-bounce period for SDA and SCL lines" "No Debounce,2T,4T,6T,8T,10T,12T,14T"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NEW_MASTER_FSM ,Maintained for compatibility sake" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PACKET_MODE_EN ,Initiate transfer in packet mode" "NOP,GO"
|
|
bitfld.long 0x00 9. " SEND ,Master initiates the transaction in normal mode" "NOP,GO"
|
|
textline " "
|
|
bitfld.long 0x00 8. " NOACK ,No ACK mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CMD1 ,Read/Write Command for Slave 1" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 5. " START ,Send Start byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SLV2 ,Enables a two slave transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--3. " LENGTH ,Number of bytes to be transmitted per transaction" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " A_MOD ,7-bit or a 10-bit slave address" "7-bit address,10-bit address"
|
|
endif
|
|
if (((per.l(ad:0x7000C000))&0x01)==0x01)
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "CMD_ADDR0_0,I2C Slave-1 Address"
|
|
hexmask.long.word 0x00 0.--9. 1. " ADDR0 ,I2C Slave-1 Address"
|
|
line.long 0x04 "CMD_ADDR1_0,I2C Slave-2 Address"
|
|
hexmask.long.word 0x04 0.--9. 1. " ADDR1 ,I2C Slave-2 Address"
|
|
else
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "CMD_ADDR0_0,I2C Slave-1 Address"
|
|
hexmask.long.byte 0x00 1.--7. 1. " ADDR0 ,I2C Slave-1 Address"
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMD_ADDR0[0] ,Indicates read/write transaction" "Write,Read"
|
|
endif
|
|
line.long 0x04 "CMD_ADDR1_0,I2C Slave-2 Address"
|
|
hexmask.long.byte 0x04 1.--7. 1. " ADDR1 ,I2C Slave-2 Address"
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x04 0. " CMD_ADDR1[0] ,Indicates read/write transaction" "Write,Read"
|
|
endif
|
|
endif
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "CMD_DATA1_0,I2C Controller Data 1 Transmit/Receive"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA4 ,Fourth data byte to be sent/received"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA3 ,Third data byte to be sent/received"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA2 ,Second data byte to be sent/received"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA1 ,First data byte to be sent/received"
|
|
line.long 0x04 "CMD_DATA2_0,I2C Controller Data 2 Transmit/Receive"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA8 ,Eighth data byte to be sent/received"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA7 ,Seventh data byte to be sent/received"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA6 ,Sixth data byte to be sent/received"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA5 ,Fifth data byte to be sent/received"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "STATUS_0,I2C Controller Master Status"
|
|
bitfld.long 0x00 8. " BUSY ,Master busy" "Not busy,Busy"
|
|
bitfld.long 0x00 4.--7. " CMD2_STAT ,Transaction for Slave 2" "Successful,NOACK for byte 1,NOACK for byte 2,NOACK for byte 3,NOACK for byte 4,NOACK for byte 5,NOACK for byte 6,NOACK for byte 7,NOACK for byte 8,NOACK for byte 9,NOACK for byte 10,?..."
|
|
bitfld.long 0x00 0.--3. " CMD1_STAT ,Transaction for Slave 1" "Successful,NOACK for byte 1,NOACK for byte 2,NOACK for byte 3,NOACK for byte 4,NOACK for byte 5,NOACK for byte 6,NOACK for byte 7,NOACK for byte 8,NOACK for byte 9,NOACK for byte 10,?..."
|
|
sif (cpuis("TEGRAX2"))
|
|
if (((per.l(ad:0x7000C000+0x20))&0x100000)==0x100000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SL_CNFG_0,I2C Controller Slave Configuration"
|
|
bitfld.long 0x00 21. " SLV_XFER_ERR_CLK_STRETCH_EN ,Enables the slave stretch I2C SCL line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FIFO_XFER_EN ,FIFO transfer enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 8.--19. 1. " BUFFER_SIZE ,Payload size in bytes"
|
|
bitfld.long 0x00 7. " ACK_LAST_BYTE_VALID ,ACK the last byte valid (write-only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACK_LAST_BYTE ,ACK the last byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACK_WITHHOLD_EN ,Ack withhold feature enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PKT_MODE_EN ,Packet mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_SL ,Enable slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NEWSL ,Use new slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,Disable Slave acknowledge -The slave will not acknowledge reception of address or data byte" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESP ,Slave response to general call address" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SL_CNFG_0,I2C Controller Slave Configuration"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FIFO_XFER_EN ,FIFO transfer enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 8.--19. 1. " BUFFER_SIZE ,Payload size in bytes"
|
|
bitfld.long 0x00 7. " ACK_LAST_BYTE_VALID ,ACK the last byte valid (write-only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACK_LAST_BYTE ,ACK the last byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACK_WITHHOLD_EN ,Ack withhold feature enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PKT_MODE_EN ,Packet mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_SL ,Enable slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NEWSL ,Use new slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,Disable Slave acknowledge -The slave will not acknowledge reception of address or data byte" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESP ,Slave response to general call address" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SL_CNFG_0,I2C Controller Slave Configuration"
|
|
bitfld.long 0x00 20. " FIFO_XFER_EN ,FIFO transfer enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 8.--19. 1. " BUFFER_SIZE ,Payload size in bytes"
|
|
bitfld.long 0x00 7. " ACK_LAST_BYTE_VALID ,ACK the last byte valid(Write-Only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACK_LAST_BYTE ,ACK the last byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACK_WITHHOLD_EN ,Ack withhold feature enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PKT_MODE_EN ,Packet mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_SL ,Enable slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NEWSL ,Use new slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,Disable Slave acknowledge -The slave will not acknowledge reception of address or data byte" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESP ,Slave response to general call address" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SL_RCVD_0,I2C Controller Slave Receive/Transmit Data"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SL_DATA ,Slave received data"
|
|
if (((per.l(ad:0x7000C000+0x28))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SL_STATUS_0,I2C Controller Slave Status"
|
|
hexmask.long.byte 0x00 8.--14. 1. " HW_MSTR_ADR ,Hardware master address received via general call addressing"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,Interrupt generated by the slave when hardware master address is received" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " REPROG_SL ,Interrupt generated by the slave after the General Call Address is 0x04" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RST_SL ,Interrupt generated by the slave after the General Call Address is 0x06" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,Slave Transaction complete" "Completed,In progress"
|
|
bitfld.long 0x00 3. " SL_IRQ ,Interrupt generated by slave" "Not interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RCVD ,New transaction received status" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " RNW ,Slave transaction status" "Write,Read"
|
|
bitfld.long 0x00 0. " ZA ,Zero address status" "No response,Response"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SL_STATUS_0,I2C Controller Slave Status"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,Interrupt generated by the slave when hardware master address is received" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " REPROG_SL ,Interrupt generated by the slave after the General Call Address is 0x04" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RST_SL ,Interrupt generated by the slave after the General Call Address is 0x06" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,Slave Transaction complete" "Completed,In progress"
|
|
bitfld.long 0x00 3. " SL_IRQ ,Interrupt generated by slave" "Not interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RCVD ,New transaction received status" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " RNW ,Slave transaction status" "Write,Read"
|
|
bitfld.long 0x00 0. " ZA ,Zero address status" "No response,Response"
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SL_ADDR1_0,I2C Controller Slave Address 1 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SL_ADDR1 ,Slave address 1 (for a 10-bit slave address: least significant 8 bits)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SL_ADDR0 ,Slave address 0 (for a 10-bit slave address: least significant 8 bits)"
|
|
if (((per.l(ad:0x7000C000+0x30))&0x01)==0x00)&&(((per.l(ad:0x7000C000+0x30))&0x100)==0x00)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
elif (((per.l(ad:0x7000C000+0x30))&0x01)==0x00)&&(((per.l(ad:0x7000C000+0x30))&0x100)==0x100)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
bitfld.long 0x00 1.--2. " SL_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
elif (((per.l(ad:0x7000C000+0x30))&0x01)==0x01)&&(((per.l(ad:0x7000C000+0x30))&0x100)==0x00)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
bitfld.long 0x00 9.--10. " SL1_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
else
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
bitfld.long 0x00 9.--10. " SL1_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
bitfld.long 0x00 1.--2. " SL_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
endif
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "TLOW_SEXT_0,I2C Controller SMBUS Timeout Thresholds"
|
|
bitfld.long 0x00 27. " RST_SL_ON_TIMEOUT ,Reset Slave state machine on time-out" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TLOW_MEXT_EN ,Enable TLOW_MEXT counter" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " TLOW_SEXT_EN ,Enable TLOW_SEXT counter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TIMEOUT_EN ,Enable TIMEOUT counter" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOW_MEXT ,Cumulative clock low extend time (transfer period)"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOW_SEXT ,Cumulative clock low extend time (complete transfer)"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " TIMEOUT ,Clock low timeout period in milliseconds"
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "SL_DELAY_COUNT_0,I2C Slave Controller Delay Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " SL_DELAY_COUNT ,Timing between address-data cycles or data-data cycles"
|
|
line.long 0x04 "SL_INT_MASK_0,I2C Controller Slave Mask"
|
|
bitfld.long 0x04 7. " HW_MSTR_INT ,HW_MSTR_INT (Hardware master address is received) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " REPROG_SL ,REPROG_SL (General Call Address is 0x04) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " RST_SL ,RST_SL (General Call Address is 0x06) Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " END_TRANS ,END_TRANS (Transaction complete) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " SL_IRQ ,SL_IRQ (Interrupt generated) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCVD ,RCVD (Transaction received) Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ZA ,ZA (Zero address) Mask" "Disabled,Enabled"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SL_INT_SOURCE_0,I2C Controller Slave Interrupt Source"
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,HW_MSTR_INT (Hardware master address is received) Source" "Unset,Set"
|
|
bitfld.long 0x00 6. " REPROG_SL ,REPROG_SL (General Call Address is 0x04) Source" "Unset,Set"
|
|
bitfld.long 0x00 5. " RST_SL ,RST_SL (General Call Address is 0x06) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,END_TRANS (Transaction complete) Source" "Unset,Set"
|
|
bitfld.long 0x00 3. " SL_IRQ ,SL_IRQ (Interrupt generated) Source" "Unset,Set"
|
|
bitfld.long 0x00 2. " RCVD ,RCVD (Transaction received) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ZA ,ZA (Zero address) Source" "Unset,Set"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SL_INT_SET_0,I2C Controller Slave Interrupt Set"
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,HW_MSTR_INT (Hardware master address is received) Source" "Unset,Set"
|
|
bitfld.long 0x00 6. " REPROG_SL ,REPROG_SL (General Call Address is 0x04) Source" "Unset,Set"
|
|
bitfld.long 0x00 5. " RST_SL ,RST_SL (General Call Address is 0x06) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,END_TRANS (Transaction complete) Source" "Unset,Set"
|
|
bitfld.long 0x00 3. " SL_IRQ ,SL_IRQ (Interrupt generated) Source" "Unset,Set"
|
|
bitfld.long 0x00 2. " RCVD ,RCVD (Transaction received) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ZA ,ZA (Zero address) Source" "Unset,Set"
|
|
tree "Packet Mode"
|
|
width 29.
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "TX_PACKET_FIFO_0,TX Packet FIFO"
|
|
rgroup.long 0x54++0x07
|
|
line.long 0x00 "RX_FIFO_0,Header or I2C Specific Header or Data"
|
|
line.long 0x04 "PACKET_TRANSFER_STATUS_0,I2C Packet Transfer Status"
|
|
bitfld.long 0x04 24. " TRANSFER_COMPLETE ,The packet transfer for which last packet is set has been completed" "Unset,Set"
|
|
hexmask.long.byte 0x04 16.--23. 1. " TRANSFER_PKT_ID ,The current packet ID for which the transaction is happening on the bus"
|
|
textline " "
|
|
hexmask.long.word 0x04 4.--15. 1. " TRANSFER_BYTENUM ,The number of bytes transferred in the current packet"
|
|
bitfld.long 0x04 3. " NOACK_FOR_ADDR ,No ACK received for the address byte" "ACK,No ACK"
|
|
textline " "
|
|
bitfld.long 0x04 2. " NOACK_FOR_DATA ,No ACK received for the data byte" "ACK,No ACK"
|
|
bitfld.long 0x04 1. " ARB_LOST ,Arbitration lost for the current byte" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CONTROLLER_BUSY ,Controller is busy" "Not busy,Busy"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "FIFO_CONTROL_0,I2C FIFO Control Register"
|
|
bitfld.long 0x00 13.--15. " SLV_TX_FIFO_TRIG ,Slave Transmit FIFO trigger" "1 word,2 words,?..."
|
|
bitfld.long 0x00 10.--12. " SLV_RX_FIFO_TRIG ,Slave Receive FIFO trigger" "1 word,2 words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SLV_TX_FIFO_FLUSH ,Flush the TX FIFO" "No effect,Flush"
|
|
bitfld.long 0x00 8. " SLV_RX_FIFO_FLUSH ,Flush the RX FIFO" "No effect,Flush"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " TX_FIFO_TRIG ,Transmit FIFO trigger level" "1 word,2 words,?..."
|
|
bitfld.long 0x00 2.--4. " RX_FIFO_TRIG ,Receive FIFO trigger level" "1 word,2 words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX_FIFO_FLUSH ,Flush the TX FIFO" "No effect,Flush"
|
|
bitfld.long 0x00 0. " RX_FIFO_FLUSH ,Flush the RX FIFO" "No effect,Flush"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "FIFO_STATUS_0,I2C FIFO Status Register"
|
|
bitfld.long 0x00 25. " SLV_XFER_ERR_REASON ,Nature of the packet transfer error" "Terminated before end,Not terminated"
|
|
bitfld.long 0x00 20.--23. " SLV_TX_FIFO_EMPTY_CNT ,The number of slots that can be written to the slave TX" "TX FIFO Full,1 slot empty,2 slots empty,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SLV_RX_FIFO_FULL_CNT ,The number of slots to be read from the Slave RX" "RX FIFO empty,1 slot full,2 slots full,?..."
|
|
bitfld.long 0x00 4.--7. " TX_FIFO_EMPTY_CNT ,The number of slots that can be written to the TX FIFO" "TX FIFO Full,1 slot empty,2 slots empty,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " RX_FIFO_FULL_CNT ,The number of slots to be read from the RX FIFO" "RX FIFO empty,1 slot full,2 slots full,?..."
|
|
textline " "
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "INTERRUPT_MASK_REGISTER_0,I2C Interrupt Mask Register"
|
|
bitfld.long 0x00 28. " SLV_ACK_WITHHELD_INT_EN ,SLV_ACK_WITHHELD (Withheld - waiting for sw explicit info about ACK) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SLV_RD2WR_INT_EN ,SLV_RD2WR (Transaction switching from rd to wr) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SLV_WR2RD_INT_EN ,SLV_WR2RD (Transaction switching from wr to rd) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " SLV_PKT_XFER_ERR_INT_EN ,SLV_PKT_XFER_ERR (Request error) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ_INT_EN ,SLV_TX_BUFFER_REQ (Slave TX buffer is empty) Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ_INT_EN ,SLV_TX_BUFFER_REQ (Slave TX buffer is full) Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 23. " SLV_RX_BUFFER_FILLED_INT_EN ,SLV_RX_BUFFER_FILLED (Slave Rx buffer is full) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE_INT_EN ,SLV_PACKET_XFER_COMPLETE (Slave packet transfer complete) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SLV_TFIFO_OVF_REQ_INT_EN ,SLV_TFIFO_OVF_REQ (Slave TX FIFO overflow) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SLV_RFIFO_UNF_REQ_INT_EN ,SLV_RFIFO_UNF_REQ (Slave Rx FIFO underflow) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SLV_TFIFO_DATA_REQ_INT_EN ,SLV_TFIFO_DATA_REQ (Slave TX FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SLV_RFIFO_DATA_REQ_INT_EN ,SLV_RFIFO_DATA_REQ (Slave Rx FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " BUS_CLEAR_DONE_INT_EN ,BUS_CLEAR_DONE (Bus clear done status) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TLOW_MEXT_TIMEOUT_EN ,TLOW_MEXT_TIMEOUT_EN (SMBUS mext time-out) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TLOW_SEXT_TIMEOUT_EN ,TLOW_SEXT_TIMEOUT_EN (SMBUS sext time-out) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMEOUT_INT_EN ,TIMEOUT (SMBUS time-out) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PACKET_XFER_COMPLETE_INT_EN ,PACKET_XFER_COMPLETE (Packet has been transferred successfully) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE_INT_EN ,ALL_PACKETS_XFER_COMPLETE (All the packets transferred successfully) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TFIFO_OVF_INT_EN ,TFIFO_OVF (TX FIFO overflow) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFIFO_UNF_INT_EN ,RFIFO_UNF (Rx FIFO underflow) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NOACK_INT_EN ,NOACK (No ACK from slave) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ARB_LOST_INT_EN ,ARB_LOST (Arbitration lost) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TFIFO_DATA_REQ_INT_EN ,TFIFO_DATA_REQ (TX FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RFIFO_DATA_REQ_INT_EN ,RFIFO_DATA_REQ (RX FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "INTERRUPT_STATUS_REGISTER_0,I2C Interrupt Status Register"
|
|
eventfld.long 0x00 28. " SLV_ACK_WITHHELD ,Withheld - Waiting for sw explicit info about ACK" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 27. " SLV_RD2WR ,Transaction switching from rd to wr" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 26. " SLV_WR2RD ,Transaction switching from wr to rd" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " SLV_PKT_XFER_ERR ,Request error" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
eventfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is empty" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is full" "No interrupt,Interrupt"
|
|
endif
|
|
eventfld.long 0x00 23. " SLV_RX_BUFFER_FILLED ,Slave RX buffer is full" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE ,Slave packet transfer complete" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " SLV_TFIFO_OVF ,Slave TX FIFO overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 20. " SLV_RFIFO_UN ,Slave RX FIFO underflow" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 17. " SLV_TFIFO_DATA_REQ ,Slave TX FIFO data request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " SLV_RFIFO_DATA_REQ ,Slave Rx FIFO data request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " BUS_CLEAR_DONE ,Bus clear done status" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
eventfld.long 0x00 10. " TLOW_MEXT_TIMEOUT ,SMBUS mext time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " TLOW_SEXT_TIMEOUT ,SMBUS sext time-out" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 10. " TLOW_MEXT_TIMEOUT_EN ,SMBUS mext time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " TLOW_SEXT_TIMEOUT_EN ,SMBUS sext time-out" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 8. " TIMEOUT ,SMBUS time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " PACKET_XFER_COMPLETE ,Packet has been transferred successfully" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE ,All the packets transferred successfully" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " TFIFO_OVF ,TX FIFO overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RFIFO_UNF ,RX FIFO underflow" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " NOACK ,No ACK from slave" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ARB_LOST ,Arbitration lost" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 1. " TFIFO_DATA_REQ ,TX FIFO data request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " RFIFO_DATA_REQ ,RX FIFO data request" "No interrupt,Interrupt"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CLK_DIVISOR_REGISTER_0,I2C Clock Divisor Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " I2C_CLK_DIVISOR_STD_FAST_MODE ,Divisor - fast mode"
|
|
hexmask.long.word 0x00 0.--15. 1. " I2C_CLK_DIVISOR_HSMODE ,Divisor - high speed mode"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "INTERRUPT_SOURCE_REGISTER_0,I2C Interrupt Source Register"
|
|
bitfld.long 0x00 28. " SLV_ACK_WITHHELD ,Waiting for sw explicit info about ack - source" "Unset,Set"
|
|
bitfld.long 0x00 27. " SLV_RD2WR ,Transaction switching from rd to wr - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SLV_WR2RD ,Transaction switching from wr to rd - source" "Unset,Set"
|
|
bitfld.long 0x00 25. " SLV_PKT_XFER_ERR ,Error occurred during slave xfer - source" "Unset,Set"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is empty - source" "Unset,Set"
|
|
else
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is full - source" "Unset,Set"
|
|
endif
|
|
bitfld.long 0x00 23. " SLV_RX_BUFFER_FILLED ,Slave RX buffer is full - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE ,Slave packet transfer complete - source" "Unset,Set"
|
|
bitfld.long 0x00 21. " SLV_TFIFO_OVF ,Slave TX FIFO overflow - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SLV_RFIFO_UNF ,Slave RX FIFO underflow - source" "Unset,Set"
|
|
bitfld.long 0x00 17. " SLV_TFIFO_DATA_REQ ,Slave TX FIFO data request - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SLV_RFIFO_DATA_REQ ,Slave RX FIFO data request - source" "Unset,Set"
|
|
bitfld.long 0x00 11. " BUS_CLEAR_DONE ,Bus clear done - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TLOW_MEXT_TIMEOUT ,SMBUS mext time-out - source" "Unset,Set"
|
|
bitfld.long 0x00 9. " TLOW_SEXT_TIMEOUT ,SMBUS sext time-out - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMEOUT ,SMBUS time-out - source" "Unset,Set"
|
|
bitfld.long 0x00 7. " PACKET_XFER_COMPLETE ,Packet has been transferred successfully - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE ,All the packets transferred successfully - source" "Unset,Set"
|
|
bitfld.long 0x00 5. " TFIFO_OVF ,TX FIFO overflow - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFIFO_UNF ,RX FIFO underflow - source" "Unset,Set"
|
|
bitfld.long 0x00 3. " NOACK ,No ACK from slave - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ARB_LOST ,Arbitration lost - source" "Unset,Set"
|
|
bitfld.long 0x00 1. " TFIFO_DATA_REQ ,TX FIFO data request - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RFIFO_DATA_REQ ,RX FIFO data request - source" "Unset,Set"
|
|
group.long 0x74++0x07
|
|
line.long 0x00 "INTERRUPT_SET_REGISTER_0,I2C Interrupt Source register"
|
|
bitfld.long 0x00 28. " SLV_ACK_WITHHELD ,Waiting for sw explicit info about ack - source - source" "No effect,Set"
|
|
bitfld.long 0x00 27. " SLV_RD2WR ,Transaction switching from rd to wr - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SLV_WR2RD ,Transaction switching from wr to rd - source" "No effect,Set"
|
|
bitfld.long 0x00 25. " SLV_PKT_XFER_ERR ,Error occurred during slave XFER - source" "No effect,Set"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is empty - source" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is full - source" "No effect,Set"
|
|
endif
|
|
bitfld.long 0x00 23. " SLV_RX_BUFFER_FILLED ,Slave RX buffer is full - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE ,Slave packet transfer complete - source" "No effect,Set"
|
|
bitfld.long 0x00 21. " SLV_TFIFO_OVF ,Slave TX FIFO overflow - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SLV_RFIFO_UNF ,Slave RX FIFO underflow - source" "No effect,Set"
|
|
bitfld.long 0x00 11. " BUS_CLEAR_DONE ,Bus clear done - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TLOW_MEXT_TIMEOUT ,SMBUS mext time-out - source" "No effect,Set"
|
|
bitfld.long 0x00 9. " TLOW_SEXT_TIMEOUT ,SMBUS sext time-out - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMEOUT ,SMBUS time-out - source" "No effect,Set"
|
|
bitfld.long 0x00 7. " PACKET_XFER_COMPLETE ,Packet has been transferred successfully - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE ,All the packets transferred successfully - source" "No effect,Set"
|
|
bitfld.long 0x00 5. " TFIFO_OVF ,TX FIFO overflow - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFIFO_UNF ,RX FIFO underflow - source" "No effect,Set"
|
|
bitfld.long 0x00 3. " NOACK ,No ACK from slave - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ARB_LOST ,Arbitration lost - source" "No effect,Set"
|
|
line.long 0x04 "SLV_TX_PACKET_FIFO_0,I2C Slave TX Packet FIFO"
|
|
rgroup.long 0x7C++0x07
|
|
line.long 0x00 "SLV_RX_FIFO_0,I2C Slave RX FIFO"
|
|
line.long 0x04 "SLV_PACKET_STATUS_0,I2C Slave Packet Status"
|
|
bitfld.long 0x04 25. " ACK_WITHHELD ,ACK is withheld for last byte and slave is waiting for host" "Bus is released,ACK is withheld"
|
|
bitfld.long 0x04 24. " TRANSFER_COMPLETE ,All the packets have been transferred successfully" "Not completed,Completed"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--23. 1. " TRANSFER_PKT_ID ,Current packet ID for which the transaction is happening"
|
|
hexmask.long.word 0x04 4.--15. 1. " TRANSFER_BYTENUM ,Number of bytes transferred in the current packet"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "BUS_CLEAR_CONFIG_0,I2C Bus Clear Configure"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BC_SCLK_THRESHOLD ,Send the clock pulses until this threshold is met"
|
|
bitfld.long 0x00 2. " BC_STOP_COND ,Bus clear operation" "No stopped,Stopped"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 1. " BC_TERMINATE ,Terminate the bus clear operation" "THRESHOLD,IMMEDIATE"
|
|
else
|
|
bitfld.long 0x00 1. " BC_TERMINATE ,Terminate the bus clear operation" "IMMEDIATE,THRESHOLD"
|
|
endif
|
|
bitfld.long 0x00 0. " BC_ENABLE ,Starts bus clear operation" "Disabled,Enabled"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "BUS_CLEAR_STATUS_0,Bus Clear Status"
|
|
bitfld.long 0x00 0. " BC_STATUS ,Bus clear" "Not cleared,Cleared"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CONFIG_LOAD_0,Spare Register"
|
|
bitfld.long 0x00 2. " TIMEOUT_CONFIG_LOAD ,Loads the timeout configuration" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SLV_CONFIG_LOAD ,Loads the slave configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR_CONFIG_LOAD ,Loads the master configuration" "Disabled,Enabled"
|
|
sif (cpuis("TEGRAX2"))
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CLKEN_OVERRIDE_0,I2C Clock Enable Override 0"
|
|
bitfld.long 0x00 4. " I2C_BUS_CLEAR_CLKEN_OVR ,Override for 2nd level clock enable for I2C bus clear logic" "Gated,Always on"
|
|
bitfld.long 0x00 3. " I2C_SLV_HIF_CLKEN_OVR ,Override for 2nd level clock enable for I2C slave to host interface logic" "Gated,Always on"
|
|
textline " "
|
|
bitfld.long 0x00 2. " I2C_SLV_CORE_CLKEN_OVR ,Override for 2nd level clock enable for I2C slave core logic" "Gated,Always on"
|
|
bitfld.long 0x00 0. " I2C_MST_CORE_CLKEN_OVR ,Override for 2nd level clock enable for I2C master core logic" "Gated,Always on"
|
|
endif
|
|
group.long 0x94++0x0F
|
|
line.long 0x00 "INTERFACE_TIMING_0_0,Interface Timing Register 0"
|
|
bitfld.long 0x00 8.--13. " THIGH ,High period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " TLOW ,Low period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "INTERFACE_TIMING_1_0,Interface Timing Register 1"
|
|
bitfld.long 0x04 24.--29. " TBUF ,Bus free time between STOP and START conditions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 16.--21. " TSU_STO ,Setup time for STOP condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x04 8.--13. " THD_STA ,Hold time for a START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 0.--5. " TSU_STA ,Setup time for a Repeated START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "HS_INTERFACE_TIMING_0_0,HS Interface Timing Register 0"
|
|
bitfld.long 0x08 8.--13. " HS_THIGH ,High period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 0.--5. " HS_TLOW ,Low period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "HS_INTERFACE_TIMING_1_0,HS Interface Timing Register 1"
|
|
bitfld.long 0x0C 16.--21. " HS_TSU_STO ,Setup time for STOP condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0C 8.--13. " HS_THD_STA ,Hold time for a START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--5. " HS_TSU_STA ,Setup time for a Repeated START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif !cpuis("TEGRAX1")
|
|
group.long 0xA8++0x07
|
|
line.long 0x00 "MASTER_RESET_CNTRL_0,I2C Master Reset Control Register"
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset" "Cleared,Asserted"
|
|
line.long 0x04 "SLV_RESET_CNTRL_0,I2C Slave Reset Control Register"
|
|
bitfld.long 0x04 0. " SOFT_RESET ,Soft reset" "Cleared,Asserted"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C-2"
|
|
base ad:0x7000C400
|
|
width 20.
|
|
if (((per.l(ad:0x7000C400))&0x10)==0x10)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CNFG_0,IC Controller Configuration Register"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Single,Multi"
|
|
bitfld.long 0x00 16. " HS_RND_TRIP_DLY_EFFECT ,Diagnostic bit to disable round trip delay effect on data rate in HS mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " MSTR_CLR_BUS_ON_TIMEOUT ,I2C master force clock low on timeout" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " DEBOUNCE_CNT ,De-bounce period for SDA and SCL lines" "No Debounce,2T,4T,6T,8T,10T,12T,14T"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NEW_MASTER_FSM ,Maintained for compatibility sake" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PACKET_MODE_EN ,Initiate transfer in packet mode" "NOP,GO"
|
|
bitfld.long 0x00 9. " SEND ,Master initiates the transaction in normal mode" "NOP,GO"
|
|
textline " "
|
|
bitfld.long 0x00 8. " NOACK ,No ACK mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CMD2 ,Read/Write Command for Slave 2" "Write,Read"
|
|
bitfld.long 0x00 6. " CMD1 ,Read/Write Command for Slave 1" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 5. " START ,Send Start byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SLV2 ,Enables a two slave transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--3. " LENGTH ,Number of bytes to be transmitted per transaction" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " A_MOD ,7-bit or a 10-bit slave address" "7-bit address,10-bit address"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CNFG_0,IC Controller Configuration Register"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Single,Multi"
|
|
bitfld.long 0x00 16. " HS_RND_TRIP_DLY_EFFECT ,Diagnostic bit to disable round trip delay effect on data rate in HS mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " MSTR_CLR_BUS_ON_TIMEOUT ,I2C master force clock low on timeout" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " DEBOUNCE_CNT ,De-bounce period for SDA and SCL lines" "No Debounce,2T,4T,6T,8T,10T,12T,14T"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NEW_MASTER_FSM ,Maintained for compatibility sake" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PACKET_MODE_EN ,Initiate transfer in packet mode" "NOP,GO"
|
|
bitfld.long 0x00 9. " SEND ,Master initiates the transaction in normal mode" "NOP,GO"
|
|
textline " "
|
|
bitfld.long 0x00 8. " NOACK ,No ACK mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CMD1 ,Read/Write Command for Slave 1" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 5. " START ,Send Start byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SLV2 ,Enables a two slave transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--3. " LENGTH ,Number of bytes to be transmitted per transaction" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " A_MOD ,7-bit or a 10-bit slave address" "7-bit address,10-bit address"
|
|
endif
|
|
if (((per.l(ad:0x7000C400))&0x01)==0x01)
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "CMD_ADDR0_0,I2C Slave-1 Address"
|
|
hexmask.long.word 0x00 0.--9. 1. " ADDR0 ,I2C Slave-1 Address"
|
|
line.long 0x04 "CMD_ADDR1_0,I2C Slave-2 Address"
|
|
hexmask.long.word 0x04 0.--9. 1. " ADDR1 ,I2C Slave-2 Address"
|
|
else
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "CMD_ADDR0_0,I2C Slave-1 Address"
|
|
hexmask.long.byte 0x00 1.--7. 1. " ADDR0 ,I2C Slave-1 Address"
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMD_ADDR0[0] ,Indicates read/write transaction" "Write,Read"
|
|
endif
|
|
line.long 0x04 "CMD_ADDR1_0,I2C Slave-2 Address"
|
|
hexmask.long.byte 0x04 1.--7. 1. " ADDR1 ,I2C Slave-2 Address"
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x04 0. " CMD_ADDR1[0] ,Indicates read/write transaction" "Write,Read"
|
|
endif
|
|
endif
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "CMD_DATA1_0,I2C Controller Data 1 Transmit/Receive"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA4 ,Fourth data byte to be sent/received"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA3 ,Third data byte to be sent/received"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA2 ,Second data byte to be sent/received"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA1 ,First data byte to be sent/received"
|
|
line.long 0x04 "CMD_DATA2_0,I2C Controller Data 2 Transmit/Receive"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA8 ,Eighth data byte to be sent/received"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA7 ,Seventh data byte to be sent/received"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA6 ,Sixth data byte to be sent/received"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA5 ,Fifth data byte to be sent/received"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "STATUS_0,I2C Controller Master Status"
|
|
bitfld.long 0x00 8. " BUSY ,Master busy" "Not busy,Busy"
|
|
bitfld.long 0x00 4.--7. " CMD2_STAT ,Transaction for Slave 2" "Successful,NOACK for byte 1,NOACK for byte 2,NOACK for byte 3,NOACK for byte 4,NOACK for byte 5,NOACK for byte 6,NOACK for byte 7,NOACK for byte 8,NOACK for byte 9,NOACK for byte 10,?..."
|
|
bitfld.long 0x00 0.--3. " CMD1_STAT ,Transaction for Slave 1" "Successful,NOACK for byte 1,NOACK for byte 2,NOACK for byte 3,NOACK for byte 4,NOACK for byte 5,NOACK for byte 6,NOACK for byte 7,NOACK for byte 8,NOACK for byte 9,NOACK for byte 10,?..."
|
|
sif (cpuis("TEGRAX2"))
|
|
if (((per.l(ad:0x7000C400+0x20))&0x100000)==0x100000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SL_CNFG_0,I2C Controller Slave Configuration"
|
|
bitfld.long 0x00 21. " SLV_XFER_ERR_CLK_STRETCH_EN ,Enables the slave stretch I2C SCL line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FIFO_XFER_EN ,FIFO transfer enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 8.--19. 1. " BUFFER_SIZE ,Payload size in bytes"
|
|
bitfld.long 0x00 7. " ACK_LAST_BYTE_VALID ,ACK the last byte valid (write-only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACK_LAST_BYTE ,ACK the last byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACK_WITHHOLD_EN ,Ack withhold feature enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PKT_MODE_EN ,Packet mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_SL ,Enable slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NEWSL ,Use new slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,Disable Slave acknowledge -The slave will not acknowledge reception of address or data byte" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESP ,Slave response to general call address" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SL_CNFG_0,I2C Controller Slave Configuration"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FIFO_XFER_EN ,FIFO transfer enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 8.--19. 1. " BUFFER_SIZE ,Payload size in bytes"
|
|
bitfld.long 0x00 7. " ACK_LAST_BYTE_VALID ,ACK the last byte valid (write-only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACK_LAST_BYTE ,ACK the last byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACK_WITHHOLD_EN ,Ack withhold feature enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PKT_MODE_EN ,Packet mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_SL ,Enable slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NEWSL ,Use new slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,Disable Slave acknowledge -The slave will not acknowledge reception of address or data byte" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESP ,Slave response to general call address" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SL_CNFG_0,I2C Controller Slave Configuration"
|
|
bitfld.long 0x00 20. " FIFO_XFER_EN ,FIFO transfer enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 8.--19. 1. " BUFFER_SIZE ,Payload size in bytes"
|
|
bitfld.long 0x00 7. " ACK_LAST_BYTE_VALID ,ACK the last byte valid(Write-Only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACK_LAST_BYTE ,ACK the last byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACK_WITHHOLD_EN ,Ack withhold feature enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PKT_MODE_EN ,Packet mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_SL ,Enable slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NEWSL ,Use new slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,Disable Slave acknowledge -The slave will not acknowledge reception of address or data byte" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESP ,Slave response to general call address" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SL_RCVD_0,I2C Controller Slave Receive/Transmit Data"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SL_DATA ,Slave received data"
|
|
if (((per.l(ad:0x7000C400+0x28))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SL_STATUS_0,I2C Controller Slave Status"
|
|
hexmask.long.byte 0x00 8.--14. 1. " HW_MSTR_ADR ,Hardware master address received via general call addressing"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,Interrupt generated by the slave when hardware master address is received" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " REPROG_SL ,Interrupt generated by the slave after the General Call Address is 0x04" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RST_SL ,Interrupt generated by the slave after the General Call Address is 0x06" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,Slave Transaction complete" "Completed,In progress"
|
|
bitfld.long 0x00 3. " SL_IRQ ,Interrupt generated by slave" "Not interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RCVD ,New transaction received status" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " RNW ,Slave transaction status" "Write,Read"
|
|
bitfld.long 0x00 0. " ZA ,Zero address status" "No response,Response"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SL_STATUS_0,I2C Controller Slave Status"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,Interrupt generated by the slave when hardware master address is received" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " REPROG_SL ,Interrupt generated by the slave after the General Call Address is 0x04" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RST_SL ,Interrupt generated by the slave after the General Call Address is 0x06" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,Slave Transaction complete" "Completed,In progress"
|
|
bitfld.long 0x00 3. " SL_IRQ ,Interrupt generated by slave" "Not interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RCVD ,New transaction received status" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " RNW ,Slave transaction status" "Write,Read"
|
|
bitfld.long 0x00 0. " ZA ,Zero address status" "No response,Response"
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SL_ADDR1_0,I2C Controller Slave Address 1 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SL_ADDR1 ,Slave address 1 (for a 10-bit slave address: least significant 8 bits)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SL_ADDR0 ,Slave address 0 (for a 10-bit slave address: least significant 8 bits)"
|
|
if (((per.l(ad:0x7000C400+0x30))&0x01)==0x00)&&(((per.l(ad:0x7000C400+0x30))&0x100)==0x00)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
elif (((per.l(ad:0x7000C400+0x30))&0x01)==0x00)&&(((per.l(ad:0x7000C400+0x30))&0x100)==0x100)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
bitfld.long 0x00 1.--2. " SL_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
elif (((per.l(ad:0x7000C400+0x30))&0x01)==0x01)&&(((per.l(ad:0x7000C400+0x30))&0x100)==0x00)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
bitfld.long 0x00 9.--10. " SL1_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
else
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
bitfld.long 0x00 9.--10. " SL1_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
bitfld.long 0x00 1.--2. " SL_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
endif
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "TLOW_SEXT_0,I2C Controller SMBUS Timeout Thresholds"
|
|
bitfld.long 0x00 27. " RST_SL_ON_TIMEOUT ,Reset Slave state machine on time-out" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TLOW_MEXT_EN ,Enable TLOW_MEXT counter" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " TLOW_SEXT_EN ,Enable TLOW_SEXT counter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TIMEOUT_EN ,Enable TIMEOUT counter" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOW_MEXT ,Cumulative clock low extend time (transfer period)"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOW_SEXT ,Cumulative clock low extend time (complete transfer)"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " TIMEOUT ,Clock low timeout period in milliseconds"
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "SL_DELAY_COUNT_0,I2C Slave Controller Delay Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " SL_DELAY_COUNT ,Timing between address-data cycles or data-data cycles"
|
|
line.long 0x04 "SL_INT_MASK_0,I2C Controller Slave Mask"
|
|
bitfld.long 0x04 7. " HW_MSTR_INT ,HW_MSTR_INT (Hardware master address is received) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " REPROG_SL ,REPROG_SL (General Call Address is 0x04) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " RST_SL ,RST_SL (General Call Address is 0x06) Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " END_TRANS ,END_TRANS (Transaction complete) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " SL_IRQ ,SL_IRQ (Interrupt generated) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCVD ,RCVD (Transaction received) Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ZA ,ZA (Zero address) Mask" "Disabled,Enabled"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SL_INT_SOURCE_0,I2C Controller Slave Interrupt Source"
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,HW_MSTR_INT (Hardware master address is received) Source" "Unset,Set"
|
|
bitfld.long 0x00 6. " REPROG_SL ,REPROG_SL (General Call Address is 0x04) Source" "Unset,Set"
|
|
bitfld.long 0x00 5. " RST_SL ,RST_SL (General Call Address is 0x06) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,END_TRANS (Transaction complete) Source" "Unset,Set"
|
|
bitfld.long 0x00 3. " SL_IRQ ,SL_IRQ (Interrupt generated) Source" "Unset,Set"
|
|
bitfld.long 0x00 2. " RCVD ,RCVD (Transaction received) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ZA ,ZA (Zero address) Source" "Unset,Set"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SL_INT_SET_0,I2C Controller Slave Interrupt Set"
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,HW_MSTR_INT (Hardware master address is received) Source" "Unset,Set"
|
|
bitfld.long 0x00 6. " REPROG_SL ,REPROG_SL (General Call Address is 0x04) Source" "Unset,Set"
|
|
bitfld.long 0x00 5. " RST_SL ,RST_SL (General Call Address is 0x06) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,END_TRANS (Transaction complete) Source" "Unset,Set"
|
|
bitfld.long 0x00 3. " SL_IRQ ,SL_IRQ (Interrupt generated) Source" "Unset,Set"
|
|
bitfld.long 0x00 2. " RCVD ,RCVD (Transaction received) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ZA ,ZA (Zero address) Source" "Unset,Set"
|
|
tree "Packet Mode"
|
|
width 29.
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "TX_PACKET_FIFO_0,TX Packet FIFO"
|
|
rgroup.long 0x54++0x07
|
|
line.long 0x00 "RX_FIFO_0,Header or I2C Specific Header or Data"
|
|
line.long 0x04 "PACKET_TRANSFER_STATUS_0,I2C Packet Transfer Status"
|
|
bitfld.long 0x04 24. " TRANSFER_COMPLETE ,The packet transfer for which last packet is set has been completed" "Unset,Set"
|
|
hexmask.long.byte 0x04 16.--23. 1. " TRANSFER_PKT_ID ,The current packet ID for which the transaction is happening on the bus"
|
|
textline " "
|
|
hexmask.long.word 0x04 4.--15. 1. " TRANSFER_BYTENUM ,The number of bytes transferred in the current packet"
|
|
bitfld.long 0x04 3. " NOACK_FOR_ADDR ,No ACK received for the address byte" "ACK,No ACK"
|
|
textline " "
|
|
bitfld.long 0x04 2. " NOACK_FOR_DATA ,No ACK received for the data byte" "ACK,No ACK"
|
|
bitfld.long 0x04 1. " ARB_LOST ,Arbitration lost for the current byte" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CONTROLLER_BUSY ,Controller is busy" "Not busy,Busy"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "FIFO_CONTROL_0,I2C FIFO Control Register"
|
|
bitfld.long 0x00 13.--15. " SLV_TX_FIFO_TRIG ,Slave Transmit FIFO trigger" "1 word,2 words,?..."
|
|
bitfld.long 0x00 10.--12. " SLV_RX_FIFO_TRIG ,Slave Receive FIFO trigger" "1 word,2 words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SLV_TX_FIFO_FLUSH ,Flush the TX FIFO" "No effect,Flush"
|
|
bitfld.long 0x00 8. " SLV_RX_FIFO_FLUSH ,Flush the RX FIFO" "No effect,Flush"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " TX_FIFO_TRIG ,Transmit FIFO trigger level" "1 word,2 words,?..."
|
|
bitfld.long 0x00 2.--4. " RX_FIFO_TRIG ,Receive FIFO trigger level" "1 word,2 words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX_FIFO_FLUSH ,Flush the TX FIFO" "No effect,Flush"
|
|
bitfld.long 0x00 0. " RX_FIFO_FLUSH ,Flush the RX FIFO" "No effect,Flush"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "FIFO_STATUS_0,I2C FIFO Status Register"
|
|
bitfld.long 0x00 25. " SLV_XFER_ERR_REASON ,Nature of the packet transfer error" "Terminated before end,Not terminated"
|
|
bitfld.long 0x00 20.--23. " SLV_TX_FIFO_EMPTY_CNT ,The number of slots that can be written to the slave TX" "TX FIFO Full,1 slot empty,2 slots empty,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SLV_RX_FIFO_FULL_CNT ,The number of slots to be read from the Slave RX" "RX FIFO empty,1 slot full,2 slots full,?..."
|
|
bitfld.long 0x00 4.--7. " TX_FIFO_EMPTY_CNT ,The number of slots that can be written to the TX FIFO" "TX FIFO Full,1 slot empty,2 slots empty,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " RX_FIFO_FULL_CNT ,The number of slots to be read from the RX FIFO" "RX FIFO empty,1 slot full,2 slots full,?..."
|
|
textline " "
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "INTERRUPT_MASK_REGISTER_0,I2C Interrupt Mask Register"
|
|
bitfld.long 0x00 28. " SLV_ACK_WITHHELD_INT_EN ,SLV_ACK_WITHHELD (Withheld - waiting for sw explicit info about ACK) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SLV_RD2WR_INT_EN ,SLV_RD2WR (Transaction switching from rd to wr) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SLV_WR2RD_INT_EN ,SLV_WR2RD (Transaction switching from wr to rd) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " SLV_PKT_XFER_ERR_INT_EN ,SLV_PKT_XFER_ERR (Request error) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ_INT_EN ,SLV_TX_BUFFER_REQ (Slave TX buffer is empty) Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ_INT_EN ,SLV_TX_BUFFER_REQ (Slave TX buffer is full) Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 23. " SLV_RX_BUFFER_FILLED_INT_EN ,SLV_RX_BUFFER_FILLED (Slave Rx buffer is full) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE_INT_EN ,SLV_PACKET_XFER_COMPLETE (Slave packet transfer complete) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SLV_TFIFO_OVF_REQ_INT_EN ,SLV_TFIFO_OVF_REQ (Slave TX FIFO overflow) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SLV_RFIFO_UNF_REQ_INT_EN ,SLV_RFIFO_UNF_REQ (Slave Rx FIFO underflow) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SLV_TFIFO_DATA_REQ_INT_EN ,SLV_TFIFO_DATA_REQ (Slave TX FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SLV_RFIFO_DATA_REQ_INT_EN ,SLV_RFIFO_DATA_REQ (Slave Rx FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " BUS_CLEAR_DONE_INT_EN ,BUS_CLEAR_DONE (Bus clear done status) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TLOW_MEXT_TIMEOUT_EN ,TLOW_MEXT_TIMEOUT_EN (SMBUS mext time-out) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TLOW_SEXT_TIMEOUT_EN ,TLOW_SEXT_TIMEOUT_EN (SMBUS sext time-out) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMEOUT_INT_EN ,TIMEOUT (SMBUS time-out) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PACKET_XFER_COMPLETE_INT_EN ,PACKET_XFER_COMPLETE (Packet has been transferred successfully) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE_INT_EN ,ALL_PACKETS_XFER_COMPLETE (All the packets transferred successfully) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TFIFO_OVF_INT_EN ,TFIFO_OVF (TX FIFO overflow) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFIFO_UNF_INT_EN ,RFIFO_UNF (Rx FIFO underflow) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NOACK_INT_EN ,NOACK (No ACK from slave) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ARB_LOST_INT_EN ,ARB_LOST (Arbitration lost) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TFIFO_DATA_REQ_INT_EN ,TFIFO_DATA_REQ (TX FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RFIFO_DATA_REQ_INT_EN ,RFIFO_DATA_REQ (RX FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "INTERRUPT_STATUS_REGISTER_0,I2C Interrupt Status Register"
|
|
eventfld.long 0x00 28. " SLV_ACK_WITHHELD ,Withheld - Waiting for sw explicit info about ACK" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 27. " SLV_RD2WR ,Transaction switching from rd to wr" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 26. " SLV_WR2RD ,Transaction switching from wr to rd" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " SLV_PKT_XFER_ERR ,Request error" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
eventfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is empty" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is full" "No interrupt,Interrupt"
|
|
endif
|
|
eventfld.long 0x00 23. " SLV_RX_BUFFER_FILLED ,Slave RX buffer is full" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE ,Slave packet transfer complete" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " SLV_TFIFO_OVF ,Slave TX FIFO overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 20. " SLV_RFIFO_UN ,Slave RX FIFO underflow" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 17. " SLV_TFIFO_DATA_REQ ,Slave TX FIFO data request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " SLV_RFIFO_DATA_REQ ,Slave Rx FIFO data request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " BUS_CLEAR_DONE ,Bus clear done status" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
eventfld.long 0x00 10. " TLOW_MEXT_TIMEOUT ,SMBUS mext time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " TLOW_SEXT_TIMEOUT ,SMBUS sext time-out" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 10. " TLOW_MEXT_TIMEOUT_EN ,SMBUS mext time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " TLOW_SEXT_TIMEOUT_EN ,SMBUS sext time-out" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 8. " TIMEOUT ,SMBUS time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " PACKET_XFER_COMPLETE ,Packet has been transferred successfully" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE ,All the packets transferred successfully" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " TFIFO_OVF ,TX FIFO overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RFIFO_UNF ,RX FIFO underflow" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " NOACK ,No ACK from slave" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ARB_LOST ,Arbitration lost" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 1. " TFIFO_DATA_REQ ,TX FIFO data request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " RFIFO_DATA_REQ ,RX FIFO data request" "No interrupt,Interrupt"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CLK_DIVISOR_REGISTER_0,I2C Clock Divisor Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " I2C_CLK_DIVISOR_STD_FAST_MODE ,Divisor - fast mode"
|
|
hexmask.long.word 0x00 0.--15. 1. " I2C_CLK_DIVISOR_HSMODE ,Divisor - high speed mode"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "INTERRUPT_SOURCE_REGISTER_0,I2C Interrupt Source Register"
|
|
bitfld.long 0x00 28. " SLV_ACK_WITHHELD ,Waiting for sw explicit info about ack - source" "Unset,Set"
|
|
bitfld.long 0x00 27. " SLV_RD2WR ,Transaction switching from rd to wr - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SLV_WR2RD ,Transaction switching from wr to rd - source" "Unset,Set"
|
|
bitfld.long 0x00 25. " SLV_PKT_XFER_ERR ,Error occurred during slave xfer - source" "Unset,Set"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is empty - source" "Unset,Set"
|
|
else
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is full - source" "Unset,Set"
|
|
endif
|
|
bitfld.long 0x00 23. " SLV_RX_BUFFER_FILLED ,Slave RX buffer is full - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE ,Slave packet transfer complete - source" "Unset,Set"
|
|
bitfld.long 0x00 21. " SLV_TFIFO_OVF ,Slave TX FIFO overflow - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SLV_RFIFO_UNF ,Slave RX FIFO underflow - source" "Unset,Set"
|
|
bitfld.long 0x00 17. " SLV_TFIFO_DATA_REQ ,Slave TX FIFO data request - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SLV_RFIFO_DATA_REQ ,Slave RX FIFO data request - source" "Unset,Set"
|
|
bitfld.long 0x00 11. " BUS_CLEAR_DONE ,Bus clear done - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TLOW_MEXT_TIMEOUT ,SMBUS mext time-out - source" "Unset,Set"
|
|
bitfld.long 0x00 9. " TLOW_SEXT_TIMEOUT ,SMBUS sext time-out - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMEOUT ,SMBUS time-out - source" "Unset,Set"
|
|
bitfld.long 0x00 7. " PACKET_XFER_COMPLETE ,Packet has been transferred successfully - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE ,All the packets transferred successfully - source" "Unset,Set"
|
|
bitfld.long 0x00 5. " TFIFO_OVF ,TX FIFO overflow - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFIFO_UNF ,RX FIFO underflow - source" "Unset,Set"
|
|
bitfld.long 0x00 3. " NOACK ,No ACK from slave - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ARB_LOST ,Arbitration lost - source" "Unset,Set"
|
|
bitfld.long 0x00 1. " TFIFO_DATA_REQ ,TX FIFO data request - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RFIFO_DATA_REQ ,RX FIFO data request - source" "Unset,Set"
|
|
group.long 0x74++0x07
|
|
line.long 0x00 "INTERRUPT_SET_REGISTER_0,I2C Interrupt Source register"
|
|
bitfld.long 0x00 28. " SLV_ACK_WITHHELD ,Waiting for sw explicit info about ack - source - source" "No effect,Set"
|
|
bitfld.long 0x00 27. " SLV_RD2WR ,Transaction switching from rd to wr - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SLV_WR2RD ,Transaction switching from wr to rd - source" "No effect,Set"
|
|
bitfld.long 0x00 25. " SLV_PKT_XFER_ERR ,Error occurred during slave XFER - source" "No effect,Set"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is empty - source" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is full - source" "No effect,Set"
|
|
endif
|
|
bitfld.long 0x00 23. " SLV_RX_BUFFER_FILLED ,Slave RX buffer is full - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE ,Slave packet transfer complete - source" "No effect,Set"
|
|
bitfld.long 0x00 21. " SLV_TFIFO_OVF ,Slave TX FIFO overflow - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SLV_RFIFO_UNF ,Slave RX FIFO underflow - source" "No effect,Set"
|
|
bitfld.long 0x00 11. " BUS_CLEAR_DONE ,Bus clear done - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TLOW_MEXT_TIMEOUT ,SMBUS mext time-out - source" "No effect,Set"
|
|
bitfld.long 0x00 9. " TLOW_SEXT_TIMEOUT ,SMBUS sext time-out - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMEOUT ,SMBUS time-out - source" "No effect,Set"
|
|
bitfld.long 0x00 7. " PACKET_XFER_COMPLETE ,Packet has been transferred successfully - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE ,All the packets transferred successfully - source" "No effect,Set"
|
|
bitfld.long 0x00 5. " TFIFO_OVF ,TX FIFO overflow - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFIFO_UNF ,RX FIFO underflow - source" "No effect,Set"
|
|
bitfld.long 0x00 3. " NOACK ,No ACK from slave - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ARB_LOST ,Arbitration lost - source" "No effect,Set"
|
|
line.long 0x04 "SLV_TX_PACKET_FIFO_0,I2C Slave TX Packet FIFO"
|
|
rgroup.long 0x7C++0x07
|
|
line.long 0x00 "SLV_RX_FIFO_0,I2C Slave RX FIFO"
|
|
line.long 0x04 "SLV_PACKET_STATUS_0,I2C Slave Packet Status"
|
|
bitfld.long 0x04 25. " ACK_WITHHELD ,ACK is withheld for last byte and slave is waiting for host" "Bus is released,ACK is withheld"
|
|
bitfld.long 0x04 24. " TRANSFER_COMPLETE ,All the packets have been transferred successfully" "Not completed,Completed"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--23. 1. " TRANSFER_PKT_ID ,Current packet ID for which the transaction is happening"
|
|
hexmask.long.word 0x04 4.--15. 1. " TRANSFER_BYTENUM ,Number of bytes transferred in the current packet"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "BUS_CLEAR_CONFIG_0,I2C Bus Clear Configure"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BC_SCLK_THRESHOLD ,Send the clock pulses until this threshold is met"
|
|
bitfld.long 0x00 2. " BC_STOP_COND ,Bus clear operation" "No stopped,Stopped"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 1. " BC_TERMINATE ,Terminate the bus clear operation" "THRESHOLD,IMMEDIATE"
|
|
else
|
|
bitfld.long 0x00 1. " BC_TERMINATE ,Terminate the bus clear operation" "IMMEDIATE,THRESHOLD"
|
|
endif
|
|
bitfld.long 0x00 0. " BC_ENABLE ,Starts bus clear operation" "Disabled,Enabled"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "BUS_CLEAR_STATUS_0,Bus Clear Status"
|
|
bitfld.long 0x00 0. " BC_STATUS ,Bus clear" "Not cleared,Cleared"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CONFIG_LOAD_0,Spare Register"
|
|
bitfld.long 0x00 2. " TIMEOUT_CONFIG_LOAD ,Loads the timeout configuration" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SLV_CONFIG_LOAD ,Loads the slave configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR_CONFIG_LOAD ,Loads the master configuration" "Disabled,Enabled"
|
|
sif (cpuis("TEGRAX2"))
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CLKEN_OVERRIDE_0,I2C Clock Enable Override 0"
|
|
bitfld.long 0x00 4. " I2C_BUS_CLEAR_CLKEN_OVR ,Override for 2nd level clock enable for I2C bus clear logic" "Gated,Always on"
|
|
bitfld.long 0x00 3. " I2C_SLV_HIF_CLKEN_OVR ,Override for 2nd level clock enable for I2C slave to host interface logic" "Gated,Always on"
|
|
textline " "
|
|
bitfld.long 0x00 2. " I2C_SLV_CORE_CLKEN_OVR ,Override for 2nd level clock enable for I2C slave core logic" "Gated,Always on"
|
|
bitfld.long 0x00 0. " I2C_MST_CORE_CLKEN_OVR ,Override for 2nd level clock enable for I2C master core logic" "Gated,Always on"
|
|
endif
|
|
group.long 0x94++0x0F
|
|
line.long 0x00 "INTERFACE_TIMING_0_0,Interface Timing Register 0"
|
|
bitfld.long 0x00 8.--13. " THIGH ,High period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " TLOW ,Low period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "INTERFACE_TIMING_1_0,Interface Timing Register 1"
|
|
bitfld.long 0x04 24.--29. " TBUF ,Bus free time between STOP and START conditions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 16.--21. " TSU_STO ,Setup time for STOP condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x04 8.--13. " THD_STA ,Hold time for a START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 0.--5. " TSU_STA ,Setup time for a Repeated START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "HS_INTERFACE_TIMING_0_0,HS Interface Timing Register 0"
|
|
bitfld.long 0x08 8.--13. " HS_THIGH ,High period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 0.--5. " HS_TLOW ,Low period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "HS_INTERFACE_TIMING_1_0,HS Interface Timing Register 1"
|
|
bitfld.long 0x0C 16.--21. " HS_TSU_STO ,Setup time for STOP condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0C 8.--13. " HS_THD_STA ,Hold time for a START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--5. " HS_TSU_STA ,Setup time for a Repeated START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif !cpuis("TEGRAX1")
|
|
group.long 0xA8++0x07
|
|
line.long 0x00 "MASTER_RESET_CNTRL_0,I2C Master Reset Control Register"
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset" "Cleared,Asserted"
|
|
line.long 0x04 "SLV_RESET_CNTRL_0,I2C Slave Reset Control Register"
|
|
bitfld.long 0x04 0. " SOFT_RESET ,Soft reset" "Cleared,Asserted"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C-3"
|
|
base ad:0x7000C500
|
|
width 20.
|
|
if (((per.l(ad:0x7000C500))&0x10)==0x10)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CNFG_0,IC Controller Configuration Register"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Single,Multi"
|
|
bitfld.long 0x00 16. " HS_RND_TRIP_DLY_EFFECT ,Diagnostic bit to disable round trip delay effect on data rate in HS mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " MSTR_CLR_BUS_ON_TIMEOUT ,I2C master force clock low on timeout" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " DEBOUNCE_CNT ,De-bounce period for SDA and SCL lines" "No Debounce,2T,4T,6T,8T,10T,12T,14T"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NEW_MASTER_FSM ,Maintained for compatibility sake" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PACKET_MODE_EN ,Initiate transfer in packet mode" "NOP,GO"
|
|
bitfld.long 0x00 9. " SEND ,Master initiates the transaction in normal mode" "NOP,GO"
|
|
textline " "
|
|
bitfld.long 0x00 8. " NOACK ,No ACK mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CMD2 ,Read/Write Command for Slave 2" "Write,Read"
|
|
bitfld.long 0x00 6. " CMD1 ,Read/Write Command for Slave 1" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 5. " START ,Send Start byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SLV2 ,Enables a two slave transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--3. " LENGTH ,Number of bytes to be transmitted per transaction" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " A_MOD ,7-bit or a 10-bit slave address" "7-bit address,10-bit address"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CNFG_0,IC Controller Configuration Register"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Single,Multi"
|
|
bitfld.long 0x00 16. " HS_RND_TRIP_DLY_EFFECT ,Diagnostic bit to disable round trip delay effect on data rate in HS mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " MSTR_CLR_BUS_ON_TIMEOUT ,I2C master force clock low on timeout" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " DEBOUNCE_CNT ,De-bounce period for SDA and SCL lines" "No Debounce,2T,4T,6T,8T,10T,12T,14T"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NEW_MASTER_FSM ,Maintained for compatibility sake" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PACKET_MODE_EN ,Initiate transfer in packet mode" "NOP,GO"
|
|
bitfld.long 0x00 9. " SEND ,Master initiates the transaction in normal mode" "NOP,GO"
|
|
textline " "
|
|
bitfld.long 0x00 8. " NOACK ,No ACK mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CMD1 ,Read/Write Command for Slave 1" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 5. " START ,Send Start byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SLV2 ,Enables a two slave transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--3. " LENGTH ,Number of bytes to be transmitted per transaction" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " A_MOD ,7-bit or a 10-bit slave address" "7-bit address,10-bit address"
|
|
endif
|
|
if (((per.l(ad:0x7000C500))&0x01)==0x01)
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "CMD_ADDR0_0,I2C Slave-1 Address"
|
|
hexmask.long.word 0x00 0.--9. 1. " ADDR0 ,I2C Slave-1 Address"
|
|
line.long 0x04 "CMD_ADDR1_0,I2C Slave-2 Address"
|
|
hexmask.long.word 0x04 0.--9. 1. " ADDR1 ,I2C Slave-2 Address"
|
|
else
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "CMD_ADDR0_0,I2C Slave-1 Address"
|
|
hexmask.long.byte 0x00 1.--7. 1. " ADDR0 ,I2C Slave-1 Address"
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMD_ADDR0[0] ,Indicates read/write transaction" "Write,Read"
|
|
endif
|
|
line.long 0x04 "CMD_ADDR1_0,I2C Slave-2 Address"
|
|
hexmask.long.byte 0x04 1.--7. 1. " ADDR1 ,I2C Slave-2 Address"
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x04 0. " CMD_ADDR1[0] ,Indicates read/write transaction" "Write,Read"
|
|
endif
|
|
endif
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "CMD_DATA1_0,I2C Controller Data 1 Transmit/Receive"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA4 ,Fourth data byte to be sent/received"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA3 ,Third data byte to be sent/received"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA2 ,Second data byte to be sent/received"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA1 ,First data byte to be sent/received"
|
|
line.long 0x04 "CMD_DATA2_0,I2C Controller Data 2 Transmit/Receive"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA8 ,Eighth data byte to be sent/received"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA7 ,Seventh data byte to be sent/received"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA6 ,Sixth data byte to be sent/received"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA5 ,Fifth data byte to be sent/received"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "STATUS_0,I2C Controller Master Status"
|
|
bitfld.long 0x00 8. " BUSY ,Master busy" "Not busy,Busy"
|
|
bitfld.long 0x00 4.--7. " CMD2_STAT ,Transaction for Slave 2" "Successful,NOACK for byte 1,NOACK for byte 2,NOACK for byte 3,NOACK for byte 4,NOACK for byte 5,NOACK for byte 6,NOACK for byte 7,NOACK for byte 8,NOACK for byte 9,NOACK for byte 10,?..."
|
|
bitfld.long 0x00 0.--3. " CMD1_STAT ,Transaction for Slave 1" "Successful,NOACK for byte 1,NOACK for byte 2,NOACK for byte 3,NOACK for byte 4,NOACK for byte 5,NOACK for byte 6,NOACK for byte 7,NOACK for byte 8,NOACK for byte 9,NOACK for byte 10,?..."
|
|
sif (cpuis("TEGRAX2"))
|
|
if (((per.l(ad:0x7000C500+0x20))&0x100000)==0x100000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SL_CNFG_0,I2C Controller Slave Configuration"
|
|
bitfld.long 0x00 21. " SLV_XFER_ERR_CLK_STRETCH_EN ,Enables the slave stretch I2C SCL line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FIFO_XFER_EN ,FIFO transfer enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 8.--19. 1. " BUFFER_SIZE ,Payload size in bytes"
|
|
bitfld.long 0x00 7. " ACK_LAST_BYTE_VALID ,ACK the last byte valid (write-only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACK_LAST_BYTE ,ACK the last byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACK_WITHHOLD_EN ,Ack withhold feature enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PKT_MODE_EN ,Packet mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_SL ,Enable slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NEWSL ,Use new slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,Disable Slave acknowledge -The slave will not acknowledge reception of address or data byte" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESP ,Slave response to general call address" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SL_CNFG_0,I2C Controller Slave Configuration"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FIFO_XFER_EN ,FIFO transfer enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 8.--19. 1. " BUFFER_SIZE ,Payload size in bytes"
|
|
bitfld.long 0x00 7. " ACK_LAST_BYTE_VALID ,ACK the last byte valid (write-only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACK_LAST_BYTE ,ACK the last byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACK_WITHHOLD_EN ,Ack withhold feature enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PKT_MODE_EN ,Packet mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_SL ,Enable slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NEWSL ,Use new slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,Disable Slave acknowledge -The slave will not acknowledge reception of address or data byte" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESP ,Slave response to general call address" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SL_CNFG_0,I2C Controller Slave Configuration"
|
|
bitfld.long 0x00 20. " FIFO_XFER_EN ,FIFO transfer enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 8.--19. 1. " BUFFER_SIZE ,Payload size in bytes"
|
|
bitfld.long 0x00 7. " ACK_LAST_BYTE_VALID ,ACK the last byte valid(Write-Only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACK_LAST_BYTE ,ACK the last byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACK_WITHHOLD_EN ,Ack withhold feature enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PKT_MODE_EN ,Packet mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_SL ,Enable slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NEWSL ,Use new slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,Disable Slave acknowledge -The slave will not acknowledge reception of address or data byte" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESP ,Slave response to general call address" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SL_RCVD_0,I2C Controller Slave Receive/Transmit Data"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SL_DATA ,Slave received data"
|
|
if (((per.l(ad:0x7000C500+0x28))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SL_STATUS_0,I2C Controller Slave Status"
|
|
hexmask.long.byte 0x00 8.--14. 1. " HW_MSTR_ADR ,Hardware master address received via general call addressing"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,Interrupt generated by the slave when hardware master address is received" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " REPROG_SL ,Interrupt generated by the slave after the General Call Address is 0x04" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RST_SL ,Interrupt generated by the slave after the General Call Address is 0x06" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,Slave Transaction complete" "Completed,In progress"
|
|
bitfld.long 0x00 3. " SL_IRQ ,Interrupt generated by slave" "Not interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RCVD ,New transaction received status" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " RNW ,Slave transaction status" "Write,Read"
|
|
bitfld.long 0x00 0. " ZA ,Zero address status" "No response,Response"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SL_STATUS_0,I2C Controller Slave Status"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,Interrupt generated by the slave when hardware master address is received" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " REPROG_SL ,Interrupt generated by the slave after the General Call Address is 0x04" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RST_SL ,Interrupt generated by the slave after the General Call Address is 0x06" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,Slave Transaction complete" "Completed,In progress"
|
|
bitfld.long 0x00 3. " SL_IRQ ,Interrupt generated by slave" "Not interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RCVD ,New transaction received status" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " RNW ,Slave transaction status" "Write,Read"
|
|
bitfld.long 0x00 0. " ZA ,Zero address status" "No response,Response"
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SL_ADDR1_0,I2C Controller Slave Address 1 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SL_ADDR1 ,Slave address 1 (for a 10-bit slave address: least significant 8 bits)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SL_ADDR0 ,Slave address 0 (for a 10-bit slave address: least significant 8 bits)"
|
|
if (((per.l(ad:0x7000C500+0x30))&0x01)==0x00)&&(((per.l(ad:0x7000C500+0x30))&0x100)==0x00)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
elif (((per.l(ad:0x7000C500+0x30))&0x01)==0x00)&&(((per.l(ad:0x7000C500+0x30))&0x100)==0x100)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
bitfld.long 0x00 1.--2. " SL_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
elif (((per.l(ad:0x7000C500+0x30))&0x01)==0x01)&&(((per.l(ad:0x7000C500+0x30))&0x100)==0x00)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
bitfld.long 0x00 9.--10. " SL1_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
else
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
bitfld.long 0x00 9.--10. " SL1_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
bitfld.long 0x00 1.--2. " SL_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
endif
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "TLOW_SEXT_0,I2C Controller SMBUS Timeout Thresholds"
|
|
bitfld.long 0x00 27. " RST_SL_ON_TIMEOUT ,Reset Slave state machine on time-out" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TLOW_MEXT_EN ,Enable TLOW_MEXT counter" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " TLOW_SEXT_EN ,Enable TLOW_SEXT counter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TIMEOUT_EN ,Enable TIMEOUT counter" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOW_MEXT ,Cumulative clock low extend time (transfer period)"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOW_SEXT ,Cumulative clock low extend time (complete transfer)"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " TIMEOUT ,Clock low timeout period in milliseconds"
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "SL_DELAY_COUNT_0,I2C Slave Controller Delay Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " SL_DELAY_COUNT ,Timing between address-data cycles or data-data cycles"
|
|
line.long 0x04 "SL_INT_MASK_0,I2C Controller Slave Mask"
|
|
bitfld.long 0x04 7. " HW_MSTR_INT ,HW_MSTR_INT (Hardware master address is received) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " REPROG_SL ,REPROG_SL (General Call Address is 0x04) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " RST_SL ,RST_SL (General Call Address is 0x06) Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " END_TRANS ,END_TRANS (Transaction complete) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " SL_IRQ ,SL_IRQ (Interrupt generated) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCVD ,RCVD (Transaction received) Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ZA ,ZA (Zero address) Mask" "Disabled,Enabled"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SL_INT_SOURCE_0,I2C Controller Slave Interrupt Source"
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,HW_MSTR_INT (Hardware master address is received) Source" "Unset,Set"
|
|
bitfld.long 0x00 6. " REPROG_SL ,REPROG_SL (General Call Address is 0x04) Source" "Unset,Set"
|
|
bitfld.long 0x00 5. " RST_SL ,RST_SL (General Call Address is 0x06) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,END_TRANS (Transaction complete) Source" "Unset,Set"
|
|
bitfld.long 0x00 3. " SL_IRQ ,SL_IRQ (Interrupt generated) Source" "Unset,Set"
|
|
bitfld.long 0x00 2. " RCVD ,RCVD (Transaction received) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ZA ,ZA (Zero address) Source" "Unset,Set"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SL_INT_SET_0,I2C Controller Slave Interrupt Set"
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,HW_MSTR_INT (Hardware master address is received) Source" "Unset,Set"
|
|
bitfld.long 0x00 6. " REPROG_SL ,REPROG_SL (General Call Address is 0x04) Source" "Unset,Set"
|
|
bitfld.long 0x00 5. " RST_SL ,RST_SL (General Call Address is 0x06) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,END_TRANS (Transaction complete) Source" "Unset,Set"
|
|
bitfld.long 0x00 3. " SL_IRQ ,SL_IRQ (Interrupt generated) Source" "Unset,Set"
|
|
bitfld.long 0x00 2. " RCVD ,RCVD (Transaction received) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ZA ,ZA (Zero address) Source" "Unset,Set"
|
|
tree "Packet Mode"
|
|
width 29.
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "TX_PACKET_FIFO_0,TX Packet FIFO"
|
|
rgroup.long 0x54++0x07
|
|
line.long 0x00 "RX_FIFO_0,Header or I2C Specific Header or Data"
|
|
line.long 0x04 "PACKET_TRANSFER_STATUS_0,I2C Packet Transfer Status"
|
|
bitfld.long 0x04 24. " TRANSFER_COMPLETE ,The packet transfer for which last packet is set has been completed" "Unset,Set"
|
|
hexmask.long.byte 0x04 16.--23. 1. " TRANSFER_PKT_ID ,The current packet ID for which the transaction is happening on the bus"
|
|
textline " "
|
|
hexmask.long.word 0x04 4.--15. 1. " TRANSFER_BYTENUM ,The number of bytes transferred in the current packet"
|
|
bitfld.long 0x04 3. " NOACK_FOR_ADDR ,No ACK received for the address byte" "ACK,No ACK"
|
|
textline " "
|
|
bitfld.long 0x04 2. " NOACK_FOR_DATA ,No ACK received for the data byte" "ACK,No ACK"
|
|
bitfld.long 0x04 1. " ARB_LOST ,Arbitration lost for the current byte" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CONTROLLER_BUSY ,Controller is busy" "Not busy,Busy"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "FIFO_CONTROL_0,I2C FIFO Control Register"
|
|
bitfld.long 0x00 13.--15. " SLV_TX_FIFO_TRIG ,Slave Transmit FIFO trigger" "1 word,2 words,?..."
|
|
bitfld.long 0x00 10.--12. " SLV_RX_FIFO_TRIG ,Slave Receive FIFO trigger" "1 word,2 words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SLV_TX_FIFO_FLUSH ,Flush the TX FIFO" "No effect,Flush"
|
|
bitfld.long 0x00 8. " SLV_RX_FIFO_FLUSH ,Flush the RX FIFO" "No effect,Flush"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " TX_FIFO_TRIG ,Transmit FIFO trigger level" "1 word,2 words,?..."
|
|
bitfld.long 0x00 2.--4. " RX_FIFO_TRIG ,Receive FIFO trigger level" "1 word,2 words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX_FIFO_FLUSH ,Flush the TX FIFO" "No effect,Flush"
|
|
bitfld.long 0x00 0. " RX_FIFO_FLUSH ,Flush the RX FIFO" "No effect,Flush"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "FIFO_STATUS_0,I2C FIFO Status Register"
|
|
bitfld.long 0x00 25. " SLV_XFER_ERR_REASON ,Nature of the packet transfer error" "Terminated before end,Not terminated"
|
|
bitfld.long 0x00 20.--23. " SLV_TX_FIFO_EMPTY_CNT ,The number of slots that can be written to the slave TX" "TX FIFO Full,1 slot empty,2 slots empty,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SLV_RX_FIFO_FULL_CNT ,The number of slots to be read from the Slave RX" "RX FIFO empty,1 slot full,2 slots full,?..."
|
|
bitfld.long 0x00 4.--7. " TX_FIFO_EMPTY_CNT ,The number of slots that can be written to the TX FIFO" "TX FIFO Full,1 slot empty,2 slots empty,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " RX_FIFO_FULL_CNT ,The number of slots to be read from the RX FIFO" "RX FIFO empty,1 slot full,2 slots full,?..."
|
|
textline " "
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "INTERRUPT_MASK_REGISTER_0,I2C Interrupt Mask Register"
|
|
bitfld.long 0x00 28. " SLV_ACK_WITHHELD_INT_EN ,SLV_ACK_WITHHELD (Withheld - waiting for sw explicit info about ACK) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SLV_RD2WR_INT_EN ,SLV_RD2WR (Transaction switching from rd to wr) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SLV_WR2RD_INT_EN ,SLV_WR2RD (Transaction switching from wr to rd) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " SLV_PKT_XFER_ERR_INT_EN ,SLV_PKT_XFER_ERR (Request error) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ_INT_EN ,SLV_TX_BUFFER_REQ (Slave TX buffer is empty) Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ_INT_EN ,SLV_TX_BUFFER_REQ (Slave TX buffer is full) Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 23. " SLV_RX_BUFFER_FILLED_INT_EN ,SLV_RX_BUFFER_FILLED (Slave Rx buffer is full) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE_INT_EN ,SLV_PACKET_XFER_COMPLETE (Slave packet transfer complete) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SLV_TFIFO_OVF_REQ_INT_EN ,SLV_TFIFO_OVF_REQ (Slave TX FIFO overflow) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SLV_RFIFO_UNF_REQ_INT_EN ,SLV_RFIFO_UNF_REQ (Slave Rx FIFO underflow) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SLV_TFIFO_DATA_REQ_INT_EN ,SLV_TFIFO_DATA_REQ (Slave TX FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SLV_RFIFO_DATA_REQ_INT_EN ,SLV_RFIFO_DATA_REQ (Slave Rx FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " BUS_CLEAR_DONE_INT_EN ,BUS_CLEAR_DONE (Bus clear done status) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TLOW_MEXT_TIMEOUT_EN ,TLOW_MEXT_TIMEOUT_EN (SMBUS mext time-out) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TLOW_SEXT_TIMEOUT_EN ,TLOW_SEXT_TIMEOUT_EN (SMBUS sext time-out) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMEOUT_INT_EN ,TIMEOUT (SMBUS time-out) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PACKET_XFER_COMPLETE_INT_EN ,PACKET_XFER_COMPLETE (Packet has been transferred successfully) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE_INT_EN ,ALL_PACKETS_XFER_COMPLETE (All the packets transferred successfully) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TFIFO_OVF_INT_EN ,TFIFO_OVF (TX FIFO overflow) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFIFO_UNF_INT_EN ,RFIFO_UNF (Rx FIFO underflow) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NOACK_INT_EN ,NOACK (No ACK from slave) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ARB_LOST_INT_EN ,ARB_LOST (Arbitration lost) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TFIFO_DATA_REQ_INT_EN ,TFIFO_DATA_REQ (TX FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RFIFO_DATA_REQ_INT_EN ,RFIFO_DATA_REQ (RX FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "INTERRUPT_STATUS_REGISTER_0,I2C Interrupt Status Register"
|
|
eventfld.long 0x00 28. " SLV_ACK_WITHHELD ,Withheld - Waiting for sw explicit info about ACK" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 27. " SLV_RD2WR ,Transaction switching from rd to wr" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 26. " SLV_WR2RD ,Transaction switching from wr to rd" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " SLV_PKT_XFER_ERR ,Request error" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
eventfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is empty" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is full" "No interrupt,Interrupt"
|
|
endif
|
|
eventfld.long 0x00 23. " SLV_RX_BUFFER_FILLED ,Slave RX buffer is full" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE ,Slave packet transfer complete" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " SLV_TFIFO_OVF ,Slave TX FIFO overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 20. " SLV_RFIFO_UN ,Slave RX FIFO underflow" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 17. " SLV_TFIFO_DATA_REQ ,Slave TX FIFO data request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " SLV_RFIFO_DATA_REQ ,Slave Rx FIFO data request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " BUS_CLEAR_DONE ,Bus clear done status" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
eventfld.long 0x00 10. " TLOW_MEXT_TIMEOUT ,SMBUS mext time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " TLOW_SEXT_TIMEOUT ,SMBUS sext time-out" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 10. " TLOW_MEXT_TIMEOUT_EN ,SMBUS mext time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " TLOW_SEXT_TIMEOUT_EN ,SMBUS sext time-out" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 8. " TIMEOUT ,SMBUS time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " PACKET_XFER_COMPLETE ,Packet has been transferred successfully" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE ,All the packets transferred successfully" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " TFIFO_OVF ,TX FIFO overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RFIFO_UNF ,RX FIFO underflow" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " NOACK ,No ACK from slave" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ARB_LOST ,Arbitration lost" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 1. " TFIFO_DATA_REQ ,TX FIFO data request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " RFIFO_DATA_REQ ,RX FIFO data request" "No interrupt,Interrupt"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CLK_DIVISOR_REGISTER_0,I2C Clock Divisor Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " I2C_CLK_DIVISOR_STD_FAST_MODE ,Divisor - fast mode"
|
|
hexmask.long.word 0x00 0.--15. 1. " I2C_CLK_DIVISOR_HSMODE ,Divisor - high speed mode"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "INTERRUPT_SOURCE_REGISTER_0,I2C Interrupt Source Register"
|
|
bitfld.long 0x00 28. " SLV_ACK_WITHHELD ,Waiting for sw explicit info about ack - source" "Unset,Set"
|
|
bitfld.long 0x00 27. " SLV_RD2WR ,Transaction switching from rd to wr - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SLV_WR2RD ,Transaction switching from wr to rd - source" "Unset,Set"
|
|
bitfld.long 0x00 25. " SLV_PKT_XFER_ERR ,Error occurred during slave xfer - source" "Unset,Set"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is empty - source" "Unset,Set"
|
|
else
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is full - source" "Unset,Set"
|
|
endif
|
|
bitfld.long 0x00 23. " SLV_RX_BUFFER_FILLED ,Slave RX buffer is full - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE ,Slave packet transfer complete - source" "Unset,Set"
|
|
bitfld.long 0x00 21. " SLV_TFIFO_OVF ,Slave TX FIFO overflow - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SLV_RFIFO_UNF ,Slave RX FIFO underflow - source" "Unset,Set"
|
|
bitfld.long 0x00 17. " SLV_TFIFO_DATA_REQ ,Slave TX FIFO data request - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SLV_RFIFO_DATA_REQ ,Slave RX FIFO data request - source" "Unset,Set"
|
|
bitfld.long 0x00 11. " BUS_CLEAR_DONE ,Bus clear done - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TLOW_MEXT_TIMEOUT ,SMBUS mext time-out - source" "Unset,Set"
|
|
bitfld.long 0x00 9. " TLOW_SEXT_TIMEOUT ,SMBUS sext time-out - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMEOUT ,SMBUS time-out - source" "Unset,Set"
|
|
bitfld.long 0x00 7. " PACKET_XFER_COMPLETE ,Packet has been transferred successfully - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE ,All the packets transferred successfully - source" "Unset,Set"
|
|
bitfld.long 0x00 5. " TFIFO_OVF ,TX FIFO overflow - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFIFO_UNF ,RX FIFO underflow - source" "Unset,Set"
|
|
bitfld.long 0x00 3. " NOACK ,No ACK from slave - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ARB_LOST ,Arbitration lost - source" "Unset,Set"
|
|
bitfld.long 0x00 1. " TFIFO_DATA_REQ ,TX FIFO data request - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RFIFO_DATA_REQ ,RX FIFO data request - source" "Unset,Set"
|
|
group.long 0x74++0x07
|
|
line.long 0x00 "INTERRUPT_SET_REGISTER_0,I2C Interrupt Source register"
|
|
bitfld.long 0x00 28. " SLV_ACK_WITHHELD ,Waiting for sw explicit info about ack - source - source" "No effect,Set"
|
|
bitfld.long 0x00 27. " SLV_RD2WR ,Transaction switching from rd to wr - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SLV_WR2RD ,Transaction switching from wr to rd - source" "No effect,Set"
|
|
bitfld.long 0x00 25. " SLV_PKT_XFER_ERR ,Error occurred during slave XFER - source" "No effect,Set"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is empty - source" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is full - source" "No effect,Set"
|
|
endif
|
|
bitfld.long 0x00 23. " SLV_RX_BUFFER_FILLED ,Slave RX buffer is full - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE ,Slave packet transfer complete - source" "No effect,Set"
|
|
bitfld.long 0x00 21. " SLV_TFIFO_OVF ,Slave TX FIFO overflow - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SLV_RFIFO_UNF ,Slave RX FIFO underflow - source" "No effect,Set"
|
|
bitfld.long 0x00 11. " BUS_CLEAR_DONE ,Bus clear done - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TLOW_MEXT_TIMEOUT ,SMBUS mext time-out - source" "No effect,Set"
|
|
bitfld.long 0x00 9. " TLOW_SEXT_TIMEOUT ,SMBUS sext time-out - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMEOUT ,SMBUS time-out - source" "No effect,Set"
|
|
bitfld.long 0x00 7. " PACKET_XFER_COMPLETE ,Packet has been transferred successfully - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE ,All the packets transferred successfully - source" "No effect,Set"
|
|
bitfld.long 0x00 5. " TFIFO_OVF ,TX FIFO overflow - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFIFO_UNF ,RX FIFO underflow - source" "No effect,Set"
|
|
bitfld.long 0x00 3. " NOACK ,No ACK from slave - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ARB_LOST ,Arbitration lost - source" "No effect,Set"
|
|
line.long 0x04 "SLV_TX_PACKET_FIFO_0,I2C Slave TX Packet FIFO"
|
|
rgroup.long 0x7C++0x07
|
|
line.long 0x00 "SLV_RX_FIFO_0,I2C Slave RX FIFO"
|
|
line.long 0x04 "SLV_PACKET_STATUS_0,I2C Slave Packet Status"
|
|
bitfld.long 0x04 25. " ACK_WITHHELD ,ACK is withheld for last byte and slave is waiting for host" "Bus is released,ACK is withheld"
|
|
bitfld.long 0x04 24. " TRANSFER_COMPLETE ,All the packets have been transferred successfully" "Not completed,Completed"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--23. 1. " TRANSFER_PKT_ID ,Current packet ID for which the transaction is happening"
|
|
hexmask.long.word 0x04 4.--15. 1. " TRANSFER_BYTENUM ,Number of bytes transferred in the current packet"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "BUS_CLEAR_CONFIG_0,I2C Bus Clear Configure"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BC_SCLK_THRESHOLD ,Send the clock pulses until this threshold is met"
|
|
bitfld.long 0x00 2. " BC_STOP_COND ,Bus clear operation" "No stopped,Stopped"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 1. " BC_TERMINATE ,Terminate the bus clear operation" "THRESHOLD,IMMEDIATE"
|
|
else
|
|
bitfld.long 0x00 1. " BC_TERMINATE ,Terminate the bus clear operation" "IMMEDIATE,THRESHOLD"
|
|
endif
|
|
bitfld.long 0x00 0. " BC_ENABLE ,Starts bus clear operation" "Disabled,Enabled"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "BUS_CLEAR_STATUS_0,Bus Clear Status"
|
|
bitfld.long 0x00 0. " BC_STATUS ,Bus clear" "Not cleared,Cleared"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CONFIG_LOAD_0,Spare Register"
|
|
bitfld.long 0x00 2. " TIMEOUT_CONFIG_LOAD ,Loads the timeout configuration" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SLV_CONFIG_LOAD ,Loads the slave configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR_CONFIG_LOAD ,Loads the master configuration" "Disabled,Enabled"
|
|
sif (cpuis("TEGRAX2"))
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CLKEN_OVERRIDE_0,I2C Clock Enable Override 0"
|
|
bitfld.long 0x00 4. " I2C_BUS_CLEAR_CLKEN_OVR ,Override for 2nd level clock enable for I2C bus clear logic" "Gated,Always on"
|
|
bitfld.long 0x00 3. " I2C_SLV_HIF_CLKEN_OVR ,Override for 2nd level clock enable for I2C slave to host interface logic" "Gated,Always on"
|
|
textline " "
|
|
bitfld.long 0x00 2. " I2C_SLV_CORE_CLKEN_OVR ,Override for 2nd level clock enable for I2C slave core logic" "Gated,Always on"
|
|
bitfld.long 0x00 0. " I2C_MST_CORE_CLKEN_OVR ,Override for 2nd level clock enable for I2C master core logic" "Gated,Always on"
|
|
endif
|
|
group.long 0x94++0x0F
|
|
line.long 0x00 "INTERFACE_TIMING_0_0,Interface Timing Register 0"
|
|
bitfld.long 0x00 8.--13. " THIGH ,High period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " TLOW ,Low period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "INTERFACE_TIMING_1_0,Interface Timing Register 1"
|
|
bitfld.long 0x04 24.--29. " TBUF ,Bus free time between STOP and START conditions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 16.--21. " TSU_STO ,Setup time for STOP condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x04 8.--13. " THD_STA ,Hold time for a START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 0.--5. " TSU_STA ,Setup time for a Repeated START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "HS_INTERFACE_TIMING_0_0,HS Interface Timing Register 0"
|
|
bitfld.long 0x08 8.--13. " HS_THIGH ,High period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 0.--5. " HS_TLOW ,Low period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "HS_INTERFACE_TIMING_1_0,HS Interface Timing Register 1"
|
|
bitfld.long 0x0C 16.--21. " HS_TSU_STO ,Setup time for STOP condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0C 8.--13. " HS_THD_STA ,Hold time for a START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--5. " HS_TSU_STA ,Setup time for a Repeated START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif !cpuis("TEGRAX1")
|
|
group.long 0xA8++0x07
|
|
line.long 0x00 "MASTER_RESET_CNTRL_0,I2C Master Reset Control Register"
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset" "Cleared,Asserted"
|
|
line.long 0x04 "SLV_RESET_CNTRL_0,I2C Slave Reset Control Register"
|
|
bitfld.long 0x04 0. " SOFT_RESET ,Soft reset" "Cleared,Asserted"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C-4"
|
|
base ad:0x7000C700
|
|
width 20.
|
|
if (((per.l(ad:0x7000C700))&0x10)==0x10)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CNFG_0,IC Controller Configuration Register"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Single,Multi"
|
|
bitfld.long 0x00 16. " HS_RND_TRIP_DLY_EFFECT ,Diagnostic bit to disable round trip delay effect on data rate in HS mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " MSTR_CLR_BUS_ON_TIMEOUT ,I2C master force clock low on timeout" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " DEBOUNCE_CNT ,De-bounce period for SDA and SCL lines" "No Debounce,2T,4T,6T,8T,10T,12T,14T"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NEW_MASTER_FSM ,Maintained for compatibility sake" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PACKET_MODE_EN ,Initiate transfer in packet mode" "NOP,GO"
|
|
bitfld.long 0x00 9. " SEND ,Master initiates the transaction in normal mode" "NOP,GO"
|
|
textline " "
|
|
bitfld.long 0x00 8. " NOACK ,No ACK mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CMD2 ,Read/Write Command for Slave 2" "Write,Read"
|
|
bitfld.long 0x00 6. " CMD1 ,Read/Write Command for Slave 1" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 5. " START ,Send Start byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SLV2 ,Enables a two slave transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--3. " LENGTH ,Number of bytes to be transmitted per transaction" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " A_MOD ,7-bit or a 10-bit slave address" "7-bit address,10-bit address"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CNFG_0,IC Controller Configuration Register"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Single,Multi"
|
|
bitfld.long 0x00 16. " HS_RND_TRIP_DLY_EFFECT ,Diagnostic bit to disable round trip delay effect on data rate in HS mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " MSTR_CLR_BUS_ON_TIMEOUT ,I2C master force clock low on timeout" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " DEBOUNCE_CNT ,De-bounce period for SDA and SCL lines" "No Debounce,2T,4T,6T,8T,10T,12T,14T"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NEW_MASTER_FSM ,Maintained for compatibility sake" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PACKET_MODE_EN ,Initiate transfer in packet mode" "NOP,GO"
|
|
bitfld.long 0x00 9. " SEND ,Master initiates the transaction in normal mode" "NOP,GO"
|
|
textline " "
|
|
bitfld.long 0x00 8. " NOACK ,No ACK mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CMD1 ,Read/Write Command for Slave 1" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 5. " START ,Send Start byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SLV2 ,Enables a two slave transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--3. " LENGTH ,Number of bytes to be transmitted per transaction" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " A_MOD ,7-bit or a 10-bit slave address" "7-bit address,10-bit address"
|
|
endif
|
|
if (((per.l(ad:0x7000C700))&0x01)==0x01)
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "CMD_ADDR0_0,I2C Slave-1 Address"
|
|
hexmask.long.word 0x00 0.--9. 1. " ADDR0 ,I2C Slave-1 Address"
|
|
line.long 0x04 "CMD_ADDR1_0,I2C Slave-2 Address"
|
|
hexmask.long.word 0x04 0.--9. 1. " ADDR1 ,I2C Slave-2 Address"
|
|
else
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "CMD_ADDR0_0,I2C Slave-1 Address"
|
|
hexmask.long.byte 0x00 1.--7. 1. " ADDR0 ,I2C Slave-1 Address"
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMD_ADDR0[0] ,Indicates read/write transaction" "Write,Read"
|
|
endif
|
|
line.long 0x04 "CMD_ADDR1_0,I2C Slave-2 Address"
|
|
hexmask.long.byte 0x04 1.--7. 1. " ADDR1 ,I2C Slave-2 Address"
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x04 0. " CMD_ADDR1[0] ,Indicates read/write transaction" "Write,Read"
|
|
endif
|
|
endif
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "CMD_DATA1_0,I2C Controller Data 1 Transmit/Receive"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA4 ,Fourth data byte to be sent/received"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA3 ,Third data byte to be sent/received"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA2 ,Second data byte to be sent/received"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA1 ,First data byte to be sent/received"
|
|
line.long 0x04 "CMD_DATA2_0,I2C Controller Data 2 Transmit/Receive"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA8 ,Eighth data byte to be sent/received"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA7 ,Seventh data byte to be sent/received"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA6 ,Sixth data byte to be sent/received"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA5 ,Fifth data byte to be sent/received"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "STATUS_0,I2C Controller Master Status"
|
|
bitfld.long 0x00 8. " BUSY ,Master busy" "Not busy,Busy"
|
|
bitfld.long 0x00 4.--7. " CMD2_STAT ,Transaction for Slave 2" "Successful,NOACK for byte 1,NOACK for byte 2,NOACK for byte 3,NOACK for byte 4,NOACK for byte 5,NOACK for byte 6,NOACK for byte 7,NOACK for byte 8,NOACK for byte 9,NOACK for byte 10,?..."
|
|
bitfld.long 0x00 0.--3. " CMD1_STAT ,Transaction for Slave 1" "Successful,NOACK for byte 1,NOACK for byte 2,NOACK for byte 3,NOACK for byte 4,NOACK for byte 5,NOACK for byte 6,NOACK for byte 7,NOACK for byte 8,NOACK for byte 9,NOACK for byte 10,?..."
|
|
sif (cpuis("TEGRAX2"))
|
|
if (((per.l(ad:0x7000C700+0x20))&0x100000)==0x100000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SL_CNFG_0,I2C Controller Slave Configuration"
|
|
bitfld.long 0x00 21. " SLV_XFER_ERR_CLK_STRETCH_EN ,Enables the slave stretch I2C SCL line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FIFO_XFER_EN ,FIFO transfer enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 8.--19. 1. " BUFFER_SIZE ,Payload size in bytes"
|
|
bitfld.long 0x00 7. " ACK_LAST_BYTE_VALID ,ACK the last byte valid (write-only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACK_LAST_BYTE ,ACK the last byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACK_WITHHOLD_EN ,Ack withhold feature enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PKT_MODE_EN ,Packet mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_SL ,Enable slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NEWSL ,Use new slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,Disable Slave acknowledge -The slave will not acknowledge reception of address or data byte" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESP ,Slave response to general call address" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SL_CNFG_0,I2C Controller Slave Configuration"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FIFO_XFER_EN ,FIFO transfer enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 8.--19. 1. " BUFFER_SIZE ,Payload size in bytes"
|
|
bitfld.long 0x00 7. " ACK_LAST_BYTE_VALID ,ACK the last byte valid (write-only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACK_LAST_BYTE ,ACK the last byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACK_WITHHOLD_EN ,Ack withhold feature enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PKT_MODE_EN ,Packet mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_SL ,Enable slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NEWSL ,Use new slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,Disable Slave acknowledge -The slave will not acknowledge reception of address or data byte" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESP ,Slave response to general call address" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SL_CNFG_0,I2C Controller Slave Configuration"
|
|
bitfld.long 0x00 20. " FIFO_XFER_EN ,FIFO transfer enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 8.--19. 1. " BUFFER_SIZE ,Payload size in bytes"
|
|
bitfld.long 0x00 7. " ACK_LAST_BYTE_VALID ,ACK the last byte valid(Write-Only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACK_LAST_BYTE ,ACK the last byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACK_WITHHOLD_EN ,Ack withhold feature enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PKT_MODE_EN ,Packet mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_SL ,Enable slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NEWSL ,Use new slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,Disable Slave acknowledge -The slave will not acknowledge reception of address or data byte" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESP ,Slave response to general call address" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SL_RCVD_0,I2C Controller Slave Receive/Transmit Data"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SL_DATA ,Slave received data"
|
|
if (((per.l(ad:0x7000C700+0x28))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SL_STATUS_0,I2C Controller Slave Status"
|
|
hexmask.long.byte 0x00 8.--14. 1. " HW_MSTR_ADR ,Hardware master address received via general call addressing"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,Interrupt generated by the slave when hardware master address is received" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " REPROG_SL ,Interrupt generated by the slave after the General Call Address is 0x04" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RST_SL ,Interrupt generated by the slave after the General Call Address is 0x06" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,Slave Transaction complete" "Completed,In progress"
|
|
bitfld.long 0x00 3. " SL_IRQ ,Interrupt generated by slave" "Not interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RCVD ,New transaction received status" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " RNW ,Slave transaction status" "Write,Read"
|
|
bitfld.long 0x00 0. " ZA ,Zero address status" "No response,Response"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SL_STATUS_0,I2C Controller Slave Status"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,Interrupt generated by the slave when hardware master address is received" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " REPROG_SL ,Interrupt generated by the slave after the General Call Address is 0x04" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RST_SL ,Interrupt generated by the slave after the General Call Address is 0x06" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,Slave Transaction complete" "Completed,In progress"
|
|
bitfld.long 0x00 3. " SL_IRQ ,Interrupt generated by slave" "Not interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RCVD ,New transaction received status" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " RNW ,Slave transaction status" "Write,Read"
|
|
bitfld.long 0x00 0. " ZA ,Zero address status" "No response,Response"
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SL_ADDR1_0,I2C Controller Slave Address 1 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SL_ADDR1 ,Slave address 1 (for a 10-bit slave address: least significant 8 bits)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SL_ADDR0 ,Slave address 0 (for a 10-bit slave address: least significant 8 bits)"
|
|
if (((per.l(ad:0x7000C700+0x30))&0x01)==0x00)&&(((per.l(ad:0x7000C700+0x30))&0x100)==0x00)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
elif (((per.l(ad:0x7000C700+0x30))&0x01)==0x00)&&(((per.l(ad:0x7000C700+0x30))&0x100)==0x100)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
bitfld.long 0x00 1.--2. " SL_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
elif (((per.l(ad:0x7000C700+0x30))&0x01)==0x01)&&(((per.l(ad:0x7000C700+0x30))&0x100)==0x00)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
bitfld.long 0x00 9.--10. " SL1_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
else
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
bitfld.long 0x00 9.--10. " SL1_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
bitfld.long 0x00 1.--2. " SL_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
endif
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "TLOW_SEXT_0,I2C Controller SMBUS Timeout Thresholds"
|
|
bitfld.long 0x00 27. " RST_SL_ON_TIMEOUT ,Reset Slave state machine on time-out" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TLOW_MEXT_EN ,Enable TLOW_MEXT counter" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " TLOW_SEXT_EN ,Enable TLOW_SEXT counter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TIMEOUT_EN ,Enable TIMEOUT counter" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOW_MEXT ,Cumulative clock low extend time (transfer period)"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOW_SEXT ,Cumulative clock low extend time (complete transfer)"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " TIMEOUT ,Clock low timeout period in milliseconds"
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "SL_DELAY_COUNT_0,I2C Slave Controller Delay Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " SL_DELAY_COUNT ,Timing between address-data cycles or data-data cycles"
|
|
line.long 0x04 "SL_INT_MASK_0,I2C Controller Slave Mask"
|
|
bitfld.long 0x04 7. " HW_MSTR_INT ,HW_MSTR_INT (Hardware master address is received) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " REPROG_SL ,REPROG_SL (General Call Address is 0x04) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " RST_SL ,RST_SL (General Call Address is 0x06) Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " END_TRANS ,END_TRANS (Transaction complete) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " SL_IRQ ,SL_IRQ (Interrupt generated) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCVD ,RCVD (Transaction received) Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ZA ,ZA (Zero address) Mask" "Disabled,Enabled"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SL_INT_SOURCE_0,I2C Controller Slave Interrupt Source"
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,HW_MSTR_INT (Hardware master address is received) Source" "Unset,Set"
|
|
bitfld.long 0x00 6. " REPROG_SL ,REPROG_SL (General Call Address is 0x04) Source" "Unset,Set"
|
|
bitfld.long 0x00 5. " RST_SL ,RST_SL (General Call Address is 0x06) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,END_TRANS (Transaction complete) Source" "Unset,Set"
|
|
bitfld.long 0x00 3. " SL_IRQ ,SL_IRQ (Interrupt generated) Source" "Unset,Set"
|
|
bitfld.long 0x00 2. " RCVD ,RCVD (Transaction received) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ZA ,ZA (Zero address) Source" "Unset,Set"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SL_INT_SET_0,I2C Controller Slave Interrupt Set"
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,HW_MSTR_INT (Hardware master address is received) Source" "Unset,Set"
|
|
bitfld.long 0x00 6. " REPROG_SL ,REPROG_SL (General Call Address is 0x04) Source" "Unset,Set"
|
|
bitfld.long 0x00 5. " RST_SL ,RST_SL (General Call Address is 0x06) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,END_TRANS (Transaction complete) Source" "Unset,Set"
|
|
bitfld.long 0x00 3. " SL_IRQ ,SL_IRQ (Interrupt generated) Source" "Unset,Set"
|
|
bitfld.long 0x00 2. " RCVD ,RCVD (Transaction received) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ZA ,ZA (Zero address) Source" "Unset,Set"
|
|
tree "Packet Mode"
|
|
width 29.
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "TX_PACKET_FIFO_0,TX Packet FIFO"
|
|
rgroup.long 0x54++0x07
|
|
line.long 0x00 "RX_FIFO_0,Header or I2C Specific Header or Data"
|
|
line.long 0x04 "PACKET_TRANSFER_STATUS_0,I2C Packet Transfer Status"
|
|
bitfld.long 0x04 24. " TRANSFER_COMPLETE ,The packet transfer for which last packet is set has been completed" "Unset,Set"
|
|
hexmask.long.byte 0x04 16.--23. 1. " TRANSFER_PKT_ID ,The current packet ID for which the transaction is happening on the bus"
|
|
textline " "
|
|
hexmask.long.word 0x04 4.--15. 1. " TRANSFER_BYTENUM ,The number of bytes transferred in the current packet"
|
|
bitfld.long 0x04 3. " NOACK_FOR_ADDR ,No ACK received for the address byte" "ACK,No ACK"
|
|
textline " "
|
|
bitfld.long 0x04 2. " NOACK_FOR_DATA ,No ACK received for the data byte" "ACK,No ACK"
|
|
bitfld.long 0x04 1. " ARB_LOST ,Arbitration lost for the current byte" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CONTROLLER_BUSY ,Controller is busy" "Not busy,Busy"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "FIFO_CONTROL_0,I2C FIFO Control Register"
|
|
bitfld.long 0x00 13.--15. " SLV_TX_FIFO_TRIG ,Slave Transmit FIFO trigger" "1 word,2 words,?..."
|
|
bitfld.long 0x00 10.--12. " SLV_RX_FIFO_TRIG ,Slave Receive FIFO trigger" "1 word,2 words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SLV_TX_FIFO_FLUSH ,Flush the TX FIFO" "No effect,Flush"
|
|
bitfld.long 0x00 8. " SLV_RX_FIFO_FLUSH ,Flush the RX FIFO" "No effect,Flush"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " TX_FIFO_TRIG ,Transmit FIFO trigger level" "1 word,2 words,?..."
|
|
bitfld.long 0x00 2.--4. " RX_FIFO_TRIG ,Receive FIFO trigger level" "1 word,2 words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX_FIFO_FLUSH ,Flush the TX FIFO" "No effect,Flush"
|
|
bitfld.long 0x00 0. " RX_FIFO_FLUSH ,Flush the RX FIFO" "No effect,Flush"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "FIFO_STATUS_0,I2C FIFO Status Register"
|
|
bitfld.long 0x00 25. " SLV_XFER_ERR_REASON ,Nature of the packet transfer error" "Terminated before end,Not terminated"
|
|
bitfld.long 0x00 20.--23. " SLV_TX_FIFO_EMPTY_CNT ,The number of slots that can be written to the slave TX" "TX FIFO Full,1 slot empty,2 slots empty,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SLV_RX_FIFO_FULL_CNT ,The number of slots to be read from the Slave RX" "RX FIFO empty,1 slot full,2 slots full,?..."
|
|
bitfld.long 0x00 4.--7. " TX_FIFO_EMPTY_CNT ,The number of slots that can be written to the TX FIFO" "TX FIFO Full,1 slot empty,2 slots empty,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " RX_FIFO_FULL_CNT ,The number of slots to be read from the RX FIFO" "RX FIFO empty,1 slot full,2 slots full,?..."
|
|
textline " "
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "INTERRUPT_MASK_REGISTER_0,I2C Interrupt Mask Register"
|
|
bitfld.long 0x00 28. " SLV_ACK_WITHHELD_INT_EN ,SLV_ACK_WITHHELD (Withheld - waiting for sw explicit info about ACK) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SLV_RD2WR_INT_EN ,SLV_RD2WR (Transaction switching from rd to wr) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SLV_WR2RD_INT_EN ,SLV_WR2RD (Transaction switching from wr to rd) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " SLV_PKT_XFER_ERR_INT_EN ,SLV_PKT_XFER_ERR (Request error) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ_INT_EN ,SLV_TX_BUFFER_REQ (Slave TX buffer is empty) Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ_INT_EN ,SLV_TX_BUFFER_REQ (Slave TX buffer is full) Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 23. " SLV_RX_BUFFER_FILLED_INT_EN ,SLV_RX_BUFFER_FILLED (Slave Rx buffer is full) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE_INT_EN ,SLV_PACKET_XFER_COMPLETE (Slave packet transfer complete) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SLV_TFIFO_OVF_REQ_INT_EN ,SLV_TFIFO_OVF_REQ (Slave TX FIFO overflow) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SLV_RFIFO_UNF_REQ_INT_EN ,SLV_RFIFO_UNF_REQ (Slave Rx FIFO underflow) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SLV_TFIFO_DATA_REQ_INT_EN ,SLV_TFIFO_DATA_REQ (Slave TX FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SLV_RFIFO_DATA_REQ_INT_EN ,SLV_RFIFO_DATA_REQ (Slave Rx FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " BUS_CLEAR_DONE_INT_EN ,BUS_CLEAR_DONE (Bus clear done status) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TLOW_MEXT_TIMEOUT_EN ,TLOW_MEXT_TIMEOUT_EN (SMBUS mext time-out) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TLOW_SEXT_TIMEOUT_EN ,TLOW_SEXT_TIMEOUT_EN (SMBUS sext time-out) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMEOUT_INT_EN ,TIMEOUT (SMBUS time-out) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PACKET_XFER_COMPLETE_INT_EN ,PACKET_XFER_COMPLETE (Packet has been transferred successfully) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE_INT_EN ,ALL_PACKETS_XFER_COMPLETE (All the packets transferred successfully) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TFIFO_OVF_INT_EN ,TFIFO_OVF (TX FIFO overflow) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFIFO_UNF_INT_EN ,RFIFO_UNF (Rx FIFO underflow) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NOACK_INT_EN ,NOACK (No ACK from slave) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ARB_LOST_INT_EN ,ARB_LOST (Arbitration lost) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TFIFO_DATA_REQ_INT_EN ,TFIFO_DATA_REQ (TX FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RFIFO_DATA_REQ_INT_EN ,RFIFO_DATA_REQ (RX FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "INTERRUPT_STATUS_REGISTER_0,I2C Interrupt Status Register"
|
|
eventfld.long 0x00 28. " SLV_ACK_WITHHELD ,Withheld - Waiting for sw explicit info about ACK" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 27. " SLV_RD2WR ,Transaction switching from rd to wr" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 26. " SLV_WR2RD ,Transaction switching from wr to rd" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " SLV_PKT_XFER_ERR ,Request error" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
eventfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is empty" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is full" "No interrupt,Interrupt"
|
|
endif
|
|
eventfld.long 0x00 23. " SLV_RX_BUFFER_FILLED ,Slave RX buffer is full" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE ,Slave packet transfer complete" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " SLV_TFIFO_OVF ,Slave TX FIFO overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 20. " SLV_RFIFO_UN ,Slave RX FIFO underflow" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 17. " SLV_TFIFO_DATA_REQ ,Slave TX FIFO data request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " SLV_RFIFO_DATA_REQ ,Slave Rx FIFO data request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " BUS_CLEAR_DONE ,Bus clear done status" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
eventfld.long 0x00 10. " TLOW_MEXT_TIMEOUT ,SMBUS mext time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " TLOW_SEXT_TIMEOUT ,SMBUS sext time-out" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 10. " TLOW_MEXT_TIMEOUT_EN ,SMBUS mext time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " TLOW_SEXT_TIMEOUT_EN ,SMBUS sext time-out" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 8. " TIMEOUT ,SMBUS time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " PACKET_XFER_COMPLETE ,Packet has been transferred successfully" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE ,All the packets transferred successfully" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " TFIFO_OVF ,TX FIFO overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RFIFO_UNF ,RX FIFO underflow" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " NOACK ,No ACK from slave" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ARB_LOST ,Arbitration lost" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 1. " TFIFO_DATA_REQ ,TX FIFO data request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " RFIFO_DATA_REQ ,RX FIFO data request" "No interrupt,Interrupt"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CLK_DIVISOR_REGISTER_0,I2C Clock Divisor Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " I2C_CLK_DIVISOR_STD_FAST_MODE ,Divisor - fast mode"
|
|
hexmask.long.word 0x00 0.--15. 1. " I2C_CLK_DIVISOR_HSMODE ,Divisor - high speed mode"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "INTERRUPT_SOURCE_REGISTER_0,I2C Interrupt Source Register"
|
|
bitfld.long 0x00 28. " SLV_ACK_WITHHELD ,Waiting for sw explicit info about ack - source" "Unset,Set"
|
|
bitfld.long 0x00 27. " SLV_RD2WR ,Transaction switching from rd to wr - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SLV_WR2RD ,Transaction switching from wr to rd - source" "Unset,Set"
|
|
bitfld.long 0x00 25. " SLV_PKT_XFER_ERR ,Error occurred during slave xfer - source" "Unset,Set"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is empty - source" "Unset,Set"
|
|
else
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is full - source" "Unset,Set"
|
|
endif
|
|
bitfld.long 0x00 23. " SLV_RX_BUFFER_FILLED ,Slave RX buffer is full - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE ,Slave packet transfer complete - source" "Unset,Set"
|
|
bitfld.long 0x00 21. " SLV_TFIFO_OVF ,Slave TX FIFO overflow - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SLV_RFIFO_UNF ,Slave RX FIFO underflow - source" "Unset,Set"
|
|
bitfld.long 0x00 17. " SLV_TFIFO_DATA_REQ ,Slave TX FIFO data request - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SLV_RFIFO_DATA_REQ ,Slave RX FIFO data request - source" "Unset,Set"
|
|
bitfld.long 0x00 11. " BUS_CLEAR_DONE ,Bus clear done - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TLOW_MEXT_TIMEOUT ,SMBUS mext time-out - source" "Unset,Set"
|
|
bitfld.long 0x00 9. " TLOW_SEXT_TIMEOUT ,SMBUS sext time-out - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMEOUT ,SMBUS time-out - source" "Unset,Set"
|
|
bitfld.long 0x00 7. " PACKET_XFER_COMPLETE ,Packet has been transferred successfully - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE ,All the packets transferred successfully - source" "Unset,Set"
|
|
bitfld.long 0x00 5. " TFIFO_OVF ,TX FIFO overflow - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFIFO_UNF ,RX FIFO underflow - source" "Unset,Set"
|
|
bitfld.long 0x00 3. " NOACK ,No ACK from slave - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ARB_LOST ,Arbitration lost - source" "Unset,Set"
|
|
bitfld.long 0x00 1. " TFIFO_DATA_REQ ,TX FIFO data request - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RFIFO_DATA_REQ ,RX FIFO data request - source" "Unset,Set"
|
|
group.long 0x74++0x07
|
|
line.long 0x00 "INTERRUPT_SET_REGISTER_0,I2C Interrupt Source register"
|
|
bitfld.long 0x00 28. " SLV_ACK_WITHHELD ,Waiting for sw explicit info about ack - source - source" "No effect,Set"
|
|
bitfld.long 0x00 27. " SLV_RD2WR ,Transaction switching from rd to wr - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SLV_WR2RD ,Transaction switching from wr to rd - source" "No effect,Set"
|
|
bitfld.long 0x00 25. " SLV_PKT_XFER_ERR ,Error occurred during slave XFER - source" "No effect,Set"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is empty - source" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is full - source" "No effect,Set"
|
|
endif
|
|
bitfld.long 0x00 23. " SLV_RX_BUFFER_FILLED ,Slave RX buffer is full - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE ,Slave packet transfer complete - source" "No effect,Set"
|
|
bitfld.long 0x00 21. " SLV_TFIFO_OVF ,Slave TX FIFO overflow - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SLV_RFIFO_UNF ,Slave RX FIFO underflow - source" "No effect,Set"
|
|
bitfld.long 0x00 11. " BUS_CLEAR_DONE ,Bus clear done - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TLOW_MEXT_TIMEOUT ,SMBUS mext time-out - source" "No effect,Set"
|
|
bitfld.long 0x00 9. " TLOW_SEXT_TIMEOUT ,SMBUS sext time-out - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMEOUT ,SMBUS time-out - source" "No effect,Set"
|
|
bitfld.long 0x00 7. " PACKET_XFER_COMPLETE ,Packet has been transferred successfully - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE ,All the packets transferred successfully - source" "No effect,Set"
|
|
bitfld.long 0x00 5. " TFIFO_OVF ,TX FIFO overflow - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFIFO_UNF ,RX FIFO underflow - source" "No effect,Set"
|
|
bitfld.long 0x00 3. " NOACK ,No ACK from slave - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ARB_LOST ,Arbitration lost - source" "No effect,Set"
|
|
line.long 0x04 "SLV_TX_PACKET_FIFO_0,I2C Slave TX Packet FIFO"
|
|
rgroup.long 0x7C++0x07
|
|
line.long 0x00 "SLV_RX_FIFO_0,I2C Slave RX FIFO"
|
|
line.long 0x04 "SLV_PACKET_STATUS_0,I2C Slave Packet Status"
|
|
bitfld.long 0x04 25. " ACK_WITHHELD ,ACK is withheld for last byte and slave is waiting for host" "Bus is released,ACK is withheld"
|
|
bitfld.long 0x04 24. " TRANSFER_COMPLETE ,All the packets have been transferred successfully" "Not completed,Completed"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--23. 1. " TRANSFER_PKT_ID ,Current packet ID for which the transaction is happening"
|
|
hexmask.long.word 0x04 4.--15. 1. " TRANSFER_BYTENUM ,Number of bytes transferred in the current packet"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "BUS_CLEAR_CONFIG_0,I2C Bus Clear Configure"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BC_SCLK_THRESHOLD ,Send the clock pulses until this threshold is met"
|
|
bitfld.long 0x00 2. " BC_STOP_COND ,Bus clear operation" "No stopped,Stopped"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 1. " BC_TERMINATE ,Terminate the bus clear operation" "THRESHOLD,IMMEDIATE"
|
|
else
|
|
bitfld.long 0x00 1. " BC_TERMINATE ,Terminate the bus clear operation" "IMMEDIATE,THRESHOLD"
|
|
endif
|
|
bitfld.long 0x00 0. " BC_ENABLE ,Starts bus clear operation" "Disabled,Enabled"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "BUS_CLEAR_STATUS_0,Bus Clear Status"
|
|
bitfld.long 0x00 0. " BC_STATUS ,Bus clear" "Not cleared,Cleared"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CONFIG_LOAD_0,Spare Register"
|
|
bitfld.long 0x00 2. " TIMEOUT_CONFIG_LOAD ,Loads the timeout configuration" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SLV_CONFIG_LOAD ,Loads the slave configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR_CONFIG_LOAD ,Loads the master configuration" "Disabled,Enabled"
|
|
sif (cpuis("TEGRAX2"))
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CLKEN_OVERRIDE_0,I2C Clock Enable Override 0"
|
|
bitfld.long 0x00 4. " I2C_BUS_CLEAR_CLKEN_OVR ,Override for 2nd level clock enable for I2C bus clear logic" "Gated,Always on"
|
|
bitfld.long 0x00 3. " I2C_SLV_HIF_CLKEN_OVR ,Override for 2nd level clock enable for I2C slave to host interface logic" "Gated,Always on"
|
|
textline " "
|
|
bitfld.long 0x00 2. " I2C_SLV_CORE_CLKEN_OVR ,Override for 2nd level clock enable for I2C slave core logic" "Gated,Always on"
|
|
bitfld.long 0x00 0. " I2C_MST_CORE_CLKEN_OVR ,Override for 2nd level clock enable for I2C master core logic" "Gated,Always on"
|
|
endif
|
|
group.long 0x94++0x0F
|
|
line.long 0x00 "INTERFACE_TIMING_0_0,Interface Timing Register 0"
|
|
bitfld.long 0x00 8.--13. " THIGH ,High period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " TLOW ,Low period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "INTERFACE_TIMING_1_0,Interface Timing Register 1"
|
|
bitfld.long 0x04 24.--29. " TBUF ,Bus free time between STOP and START conditions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 16.--21. " TSU_STO ,Setup time for STOP condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x04 8.--13. " THD_STA ,Hold time for a START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 0.--5. " TSU_STA ,Setup time for a Repeated START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "HS_INTERFACE_TIMING_0_0,HS Interface Timing Register 0"
|
|
bitfld.long 0x08 8.--13. " HS_THIGH ,High period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 0.--5. " HS_TLOW ,Low period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "HS_INTERFACE_TIMING_1_0,HS Interface Timing Register 1"
|
|
bitfld.long 0x0C 16.--21. " HS_TSU_STO ,Setup time for STOP condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0C 8.--13. " HS_THD_STA ,Hold time for a START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--5. " HS_TSU_STA ,Setup time for a Repeated START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif !cpuis("TEGRAX1")
|
|
group.long 0xA8++0x07
|
|
line.long 0x00 "MASTER_RESET_CNTRL_0,I2C Master Reset Control Register"
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset" "Cleared,Asserted"
|
|
line.long 0x04 "SLV_RESET_CNTRL_0,I2C Slave Reset Control Register"
|
|
bitfld.long 0x04 0. " SOFT_RESET ,Soft reset" "Cleared,Asserted"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C-5"
|
|
base ad:0x7000D000
|
|
width 20.
|
|
if (((per.l(ad:0x7000D000))&0x10)==0x10)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CNFG_0,IC Controller Configuration Register"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Single,Multi"
|
|
bitfld.long 0x00 16. " HS_RND_TRIP_DLY_EFFECT ,Diagnostic bit to disable round trip delay effect on data rate in HS mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " MSTR_CLR_BUS_ON_TIMEOUT ,I2C master force clock low on timeout" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " DEBOUNCE_CNT ,De-bounce period for SDA and SCL lines" "No Debounce,2T,4T,6T,8T,10T,12T,14T"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NEW_MASTER_FSM ,Maintained for compatibility sake" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PACKET_MODE_EN ,Initiate transfer in packet mode" "NOP,GO"
|
|
bitfld.long 0x00 9. " SEND ,Master initiates the transaction in normal mode" "NOP,GO"
|
|
textline " "
|
|
bitfld.long 0x00 8. " NOACK ,No ACK mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CMD2 ,Read/Write Command for Slave 2" "Write,Read"
|
|
bitfld.long 0x00 6. " CMD1 ,Read/Write Command for Slave 1" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 5. " START ,Send Start byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SLV2 ,Enables a two slave transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--3. " LENGTH ,Number of bytes to be transmitted per transaction" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " A_MOD ,7-bit or a 10-bit slave address" "7-bit address,10-bit address"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CNFG_0,IC Controller Configuration Register"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Single,Multi"
|
|
bitfld.long 0x00 16. " HS_RND_TRIP_DLY_EFFECT ,Diagnostic bit to disable round trip delay effect on data rate in HS mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " MSTR_CLR_BUS_ON_TIMEOUT ,I2C master force clock low on timeout" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " DEBOUNCE_CNT ,De-bounce period for SDA and SCL lines" "No Debounce,2T,4T,6T,8T,10T,12T,14T"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NEW_MASTER_FSM ,Maintained for compatibility sake" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PACKET_MODE_EN ,Initiate transfer in packet mode" "NOP,GO"
|
|
bitfld.long 0x00 9. " SEND ,Master initiates the transaction in normal mode" "NOP,GO"
|
|
textline " "
|
|
bitfld.long 0x00 8. " NOACK ,No ACK mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CMD1 ,Read/Write Command for Slave 1" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 5. " START ,Send Start byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SLV2 ,Enables a two slave transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--3. " LENGTH ,Number of bytes to be transmitted per transaction" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " A_MOD ,7-bit or a 10-bit slave address" "7-bit address,10-bit address"
|
|
endif
|
|
if (((per.l(ad:0x7000D000))&0x01)==0x01)
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "CMD_ADDR0_0,I2C Slave-1 Address"
|
|
hexmask.long.word 0x00 0.--9. 1. " ADDR0 ,I2C Slave-1 Address"
|
|
line.long 0x04 "CMD_ADDR1_0,I2C Slave-2 Address"
|
|
hexmask.long.word 0x04 0.--9. 1. " ADDR1 ,I2C Slave-2 Address"
|
|
else
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "CMD_ADDR0_0,I2C Slave-1 Address"
|
|
hexmask.long.byte 0x00 1.--7. 1. " ADDR0 ,I2C Slave-1 Address"
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMD_ADDR0[0] ,Indicates read/write transaction" "Write,Read"
|
|
endif
|
|
line.long 0x04 "CMD_ADDR1_0,I2C Slave-2 Address"
|
|
hexmask.long.byte 0x04 1.--7. 1. " ADDR1 ,I2C Slave-2 Address"
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x04 0. " CMD_ADDR1[0] ,Indicates read/write transaction" "Write,Read"
|
|
endif
|
|
endif
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "CMD_DATA1_0,I2C Controller Data 1 Transmit/Receive"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA4 ,Fourth data byte to be sent/received"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA3 ,Third data byte to be sent/received"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA2 ,Second data byte to be sent/received"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA1 ,First data byte to be sent/received"
|
|
line.long 0x04 "CMD_DATA2_0,I2C Controller Data 2 Transmit/Receive"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA8 ,Eighth data byte to be sent/received"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA7 ,Seventh data byte to be sent/received"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA6 ,Sixth data byte to be sent/received"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA5 ,Fifth data byte to be sent/received"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "STATUS_0,I2C Controller Master Status"
|
|
bitfld.long 0x00 8. " BUSY ,Master busy" "Not busy,Busy"
|
|
bitfld.long 0x00 4.--7. " CMD2_STAT ,Transaction for Slave 2" "Successful,NOACK for byte 1,NOACK for byte 2,NOACK for byte 3,NOACK for byte 4,NOACK for byte 5,NOACK for byte 6,NOACK for byte 7,NOACK for byte 8,NOACK for byte 9,NOACK for byte 10,?..."
|
|
bitfld.long 0x00 0.--3. " CMD1_STAT ,Transaction for Slave 1" "Successful,NOACK for byte 1,NOACK for byte 2,NOACK for byte 3,NOACK for byte 4,NOACK for byte 5,NOACK for byte 6,NOACK for byte 7,NOACK for byte 8,NOACK for byte 9,NOACK for byte 10,?..."
|
|
sif (cpuis("TEGRAX2"))
|
|
if (((per.l(ad:0x7000D000+0x20))&0x100000)==0x100000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SL_CNFG_0,I2C Controller Slave Configuration"
|
|
bitfld.long 0x00 21. " SLV_XFER_ERR_CLK_STRETCH_EN ,Enables the slave stretch I2C SCL line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FIFO_XFER_EN ,FIFO transfer enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 8.--19. 1. " BUFFER_SIZE ,Payload size in bytes"
|
|
bitfld.long 0x00 7. " ACK_LAST_BYTE_VALID ,ACK the last byte valid (write-only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACK_LAST_BYTE ,ACK the last byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACK_WITHHOLD_EN ,Ack withhold feature enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PKT_MODE_EN ,Packet mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_SL ,Enable slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NEWSL ,Use new slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,Disable Slave acknowledge -The slave will not acknowledge reception of address or data byte" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESP ,Slave response to general call address" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SL_CNFG_0,I2C Controller Slave Configuration"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FIFO_XFER_EN ,FIFO transfer enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 8.--19. 1. " BUFFER_SIZE ,Payload size in bytes"
|
|
bitfld.long 0x00 7. " ACK_LAST_BYTE_VALID ,ACK the last byte valid (write-only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACK_LAST_BYTE ,ACK the last byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACK_WITHHOLD_EN ,Ack withhold feature enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PKT_MODE_EN ,Packet mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_SL ,Enable slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NEWSL ,Use new slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,Disable Slave acknowledge -The slave will not acknowledge reception of address or data byte" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESP ,Slave response to general call address" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SL_CNFG_0,I2C Controller Slave Configuration"
|
|
bitfld.long 0x00 20. " FIFO_XFER_EN ,FIFO transfer enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 8.--19. 1. " BUFFER_SIZE ,Payload size in bytes"
|
|
bitfld.long 0x00 7. " ACK_LAST_BYTE_VALID ,ACK the last byte valid(Write-Only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACK_LAST_BYTE ,ACK the last byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACK_WITHHOLD_EN ,Ack withhold feature enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PKT_MODE_EN ,Packet mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_SL ,Enable slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NEWSL ,Use new slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,Disable Slave acknowledge -The slave will not acknowledge reception of address or data byte" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESP ,Slave response to general call address" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SL_RCVD_0,I2C Controller Slave Receive/Transmit Data"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SL_DATA ,Slave received data"
|
|
if (((per.l(ad:0x7000D000+0x28))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SL_STATUS_0,I2C Controller Slave Status"
|
|
hexmask.long.byte 0x00 8.--14. 1. " HW_MSTR_ADR ,Hardware master address received via general call addressing"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,Interrupt generated by the slave when hardware master address is received" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " REPROG_SL ,Interrupt generated by the slave after the General Call Address is 0x04" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RST_SL ,Interrupt generated by the slave after the General Call Address is 0x06" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,Slave Transaction complete" "Completed,In progress"
|
|
bitfld.long 0x00 3. " SL_IRQ ,Interrupt generated by slave" "Not interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RCVD ,New transaction received status" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " RNW ,Slave transaction status" "Write,Read"
|
|
bitfld.long 0x00 0. " ZA ,Zero address status" "No response,Response"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SL_STATUS_0,I2C Controller Slave Status"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,Interrupt generated by the slave when hardware master address is received" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " REPROG_SL ,Interrupt generated by the slave after the General Call Address is 0x04" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RST_SL ,Interrupt generated by the slave after the General Call Address is 0x06" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,Slave Transaction complete" "Completed,In progress"
|
|
bitfld.long 0x00 3. " SL_IRQ ,Interrupt generated by slave" "Not interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RCVD ,New transaction received status" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " RNW ,Slave transaction status" "Write,Read"
|
|
bitfld.long 0x00 0. " ZA ,Zero address status" "No response,Response"
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SL_ADDR1_0,I2C Controller Slave Address 1 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SL_ADDR1 ,Slave address 1 (for a 10-bit slave address: least significant 8 bits)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SL_ADDR0 ,Slave address 0 (for a 10-bit slave address: least significant 8 bits)"
|
|
if (((per.l(ad:0x7000D000+0x30))&0x01)==0x00)&&(((per.l(ad:0x7000D000+0x30))&0x100)==0x00)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
elif (((per.l(ad:0x7000D000+0x30))&0x01)==0x00)&&(((per.l(ad:0x7000D000+0x30))&0x100)==0x100)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
bitfld.long 0x00 1.--2. " SL_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
elif (((per.l(ad:0x7000D000+0x30))&0x01)==0x01)&&(((per.l(ad:0x7000D000+0x30))&0x100)==0x00)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
bitfld.long 0x00 9.--10. " SL1_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
else
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
bitfld.long 0x00 9.--10. " SL1_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
bitfld.long 0x00 1.--2. " SL_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
endif
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "TLOW_SEXT_0,I2C Controller SMBUS Timeout Thresholds"
|
|
bitfld.long 0x00 27. " RST_SL_ON_TIMEOUT ,Reset Slave state machine on time-out" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TLOW_MEXT_EN ,Enable TLOW_MEXT counter" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " TLOW_SEXT_EN ,Enable TLOW_SEXT counter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TIMEOUT_EN ,Enable TIMEOUT counter" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOW_MEXT ,Cumulative clock low extend time (transfer period)"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOW_SEXT ,Cumulative clock low extend time (complete transfer)"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " TIMEOUT ,Clock low timeout period in milliseconds"
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "SL_DELAY_COUNT_0,I2C Slave Controller Delay Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " SL_DELAY_COUNT ,Timing between address-data cycles or data-data cycles"
|
|
line.long 0x04 "SL_INT_MASK_0,I2C Controller Slave Mask"
|
|
bitfld.long 0x04 7. " HW_MSTR_INT ,HW_MSTR_INT (Hardware master address is received) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " REPROG_SL ,REPROG_SL (General Call Address is 0x04) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " RST_SL ,RST_SL (General Call Address is 0x06) Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " END_TRANS ,END_TRANS (Transaction complete) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " SL_IRQ ,SL_IRQ (Interrupt generated) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCVD ,RCVD (Transaction received) Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ZA ,ZA (Zero address) Mask" "Disabled,Enabled"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SL_INT_SOURCE_0,I2C Controller Slave Interrupt Source"
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,HW_MSTR_INT (Hardware master address is received) Source" "Unset,Set"
|
|
bitfld.long 0x00 6. " REPROG_SL ,REPROG_SL (General Call Address is 0x04) Source" "Unset,Set"
|
|
bitfld.long 0x00 5. " RST_SL ,RST_SL (General Call Address is 0x06) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,END_TRANS (Transaction complete) Source" "Unset,Set"
|
|
bitfld.long 0x00 3. " SL_IRQ ,SL_IRQ (Interrupt generated) Source" "Unset,Set"
|
|
bitfld.long 0x00 2. " RCVD ,RCVD (Transaction received) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ZA ,ZA (Zero address) Source" "Unset,Set"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SL_INT_SET_0,I2C Controller Slave Interrupt Set"
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,HW_MSTR_INT (Hardware master address is received) Source" "Unset,Set"
|
|
bitfld.long 0x00 6. " REPROG_SL ,REPROG_SL (General Call Address is 0x04) Source" "Unset,Set"
|
|
bitfld.long 0x00 5. " RST_SL ,RST_SL (General Call Address is 0x06) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,END_TRANS (Transaction complete) Source" "Unset,Set"
|
|
bitfld.long 0x00 3. " SL_IRQ ,SL_IRQ (Interrupt generated) Source" "Unset,Set"
|
|
bitfld.long 0x00 2. " RCVD ,RCVD (Transaction received) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ZA ,ZA (Zero address) Source" "Unset,Set"
|
|
tree "Packet Mode"
|
|
width 29.
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "TX_PACKET_FIFO_0,TX Packet FIFO"
|
|
rgroup.long 0x54++0x07
|
|
line.long 0x00 "RX_FIFO_0,Header or I2C Specific Header or Data"
|
|
line.long 0x04 "PACKET_TRANSFER_STATUS_0,I2C Packet Transfer Status"
|
|
bitfld.long 0x04 24. " TRANSFER_COMPLETE ,The packet transfer for which last packet is set has been completed" "Unset,Set"
|
|
hexmask.long.byte 0x04 16.--23. 1. " TRANSFER_PKT_ID ,The current packet ID for which the transaction is happening on the bus"
|
|
textline " "
|
|
hexmask.long.word 0x04 4.--15. 1. " TRANSFER_BYTENUM ,The number of bytes transferred in the current packet"
|
|
bitfld.long 0x04 3. " NOACK_FOR_ADDR ,No ACK received for the address byte" "ACK,No ACK"
|
|
textline " "
|
|
bitfld.long 0x04 2. " NOACK_FOR_DATA ,No ACK received for the data byte" "ACK,No ACK"
|
|
bitfld.long 0x04 1. " ARB_LOST ,Arbitration lost for the current byte" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CONTROLLER_BUSY ,Controller is busy" "Not busy,Busy"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "FIFO_CONTROL_0,I2C FIFO Control Register"
|
|
bitfld.long 0x00 13.--15. " SLV_TX_FIFO_TRIG ,Slave Transmit FIFO trigger" "1 word,2 words,?..."
|
|
bitfld.long 0x00 10.--12. " SLV_RX_FIFO_TRIG ,Slave Receive FIFO trigger" "1 word,2 words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SLV_TX_FIFO_FLUSH ,Flush the TX FIFO" "No effect,Flush"
|
|
bitfld.long 0x00 8. " SLV_RX_FIFO_FLUSH ,Flush the RX FIFO" "No effect,Flush"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " TX_FIFO_TRIG ,Transmit FIFO trigger level" "1 word,2 words,?..."
|
|
bitfld.long 0x00 2.--4. " RX_FIFO_TRIG ,Receive FIFO trigger level" "1 word,2 words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX_FIFO_FLUSH ,Flush the TX FIFO" "No effect,Flush"
|
|
bitfld.long 0x00 0. " RX_FIFO_FLUSH ,Flush the RX FIFO" "No effect,Flush"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "FIFO_STATUS_0,I2C FIFO Status Register"
|
|
bitfld.long 0x00 25. " SLV_XFER_ERR_REASON ,Nature of the packet transfer error" "Terminated before end,Not terminated"
|
|
bitfld.long 0x00 20.--23. " SLV_TX_FIFO_EMPTY_CNT ,The number of slots that can be written to the slave TX" "TX FIFO Full,1 slot empty,2 slots empty,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SLV_RX_FIFO_FULL_CNT ,The number of slots to be read from the Slave RX" "RX FIFO empty,1 slot full,2 slots full,?..."
|
|
bitfld.long 0x00 4.--7. " TX_FIFO_EMPTY_CNT ,The number of slots that can be written to the TX FIFO" "TX FIFO Full,1 slot empty,2 slots empty,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " RX_FIFO_FULL_CNT ,The number of slots to be read from the RX FIFO" "RX FIFO empty,1 slot full,2 slots full,?..."
|
|
textline " "
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "INTERRUPT_MASK_REGISTER_0,I2C Interrupt Mask Register"
|
|
bitfld.long 0x00 28. " SLV_ACK_WITHHELD_INT_EN ,SLV_ACK_WITHHELD (Withheld - waiting for sw explicit info about ACK) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SLV_RD2WR_INT_EN ,SLV_RD2WR (Transaction switching from rd to wr) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SLV_WR2RD_INT_EN ,SLV_WR2RD (Transaction switching from wr to rd) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " SLV_PKT_XFER_ERR_INT_EN ,SLV_PKT_XFER_ERR (Request error) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ_INT_EN ,SLV_TX_BUFFER_REQ (Slave TX buffer is empty) Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ_INT_EN ,SLV_TX_BUFFER_REQ (Slave TX buffer is full) Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 23. " SLV_RX_BUFFER_FILLED_INT_EN ,SLV_RX_BUFFER_FILLED (Slave Rx buffer is full) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE_INT_EN ,SLV_PACKET_XFER_COMPLETE (Slave packet transfer complete) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SLV_TFIFO_OVF_REQ_INT_EN ,SLV_TFIFO_OVF_REQ (Slave TX FIFO overflow) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SLV_RFIFO_UNF_REQ_INT_EN ,SLV_RFIFO_UNF_REQ (Slave Rx FIFO underflow) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SLV_TFIFO_DATA_REQ_INT_EN ,SLV_TFIFO_DATA_REQ (Slave TX FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SLV_RFIFO_DATA_REQ_INT_EN ,SLV_RFIFO_DATA_REQ (Slave Rx FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " BUS_CLEAR_DONE_INT_EN ,BUS_CLEAR_DONE (Bus clear done status) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TLOW_MEXT_TIMEOUT_EN ,TLOW_MEXT_TIMEOUT_EN (SMBUS mext time-out) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TLOW_SEXT_TIMEOUT_EN ,TLOW_SEXT_TIMEOUT_EN (SMBUS sext time-out) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMEOUT_INT_EN ,TIMEOUT (SMBUS time-out) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PACKET_XFER_COMPLETE_INT_EN ,PACKET_XFER_COMPLETE (Packet has been transferred successfully) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE_INT_EN ,ALL_PACKETS_XFER_COMPLETE (All the packets transferred successfully) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TFIFO_OVF_INT_EN ,TFIFO_OVF (TX FIFO overflow) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFIFO_UNF_INT_EN ,RFIFO_UNF (Rx FIFO underflow) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NOACK_INT_EN ,NOACK (No ACK from slave) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ARB_LOST_INT_EN ,ARB_LOST (Arbitration lost) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TFIFO_DATA_REQ_INT_EN ,TFIFO_DATA_REQ (TX FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RFIFO_DATA_REQ_INT_EN ,RFIFO_DATA_REQ (RX FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "INTERRUPT_STATUS_REGISTER_0,I2C Interrupt Status Register"
|
|
eventfld.long 0x00 28. " SLV_ACK_WITHHELD ,Withheld - Waiting for sw explicit info about ACK" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 27. " SLV_RD2WR ,Transaction switching from rd to wr" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 26. " SLV_WR2RD ,Transaction switching from wr to rd" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " SLV_PKT_XFER_ERR ,Request error" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
eventfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is empty" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is full" "No interrupt,Interrupt"
|
|
endif
|
|
eventfld.long 0x00 23. " SLV_RX_BUFFER_FILLED ,Slave RX buffer is full" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE ,Slave packet transfer complete" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " SLV_TFIFO_OVF ,Slave TX FIFO overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 20. " SLV_RFIFO_UN ,Slave RX FIFO underflow" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 17. " SLV_TFIFO_DATA_REQ ,Slave TX FIFO data request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " SLV_RFIFO_DATA_REQ ,Slave Rx FIFO data request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " BUS_CLEAR_DONE ,Bus clear done status" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
eventfld.long 0x00 10. " TLOW_MEXT_TIMEOUT ,SMBUS mext time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " TLOW_SEXT_TIMEOUT ,SMBUS sext time-out" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 10. " TLOW_MEXT_TIMEOUT_EN ,SMBUS mext time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " TLOW_SEXT_TIMEOUT_EN ,SMBUS sext time-out" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 8. " TIMEOUT ,SMBUS time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " PACKET_XFER_COMPLETE ,Packet has been transferred successfully" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE ,All the packets transferred successfully" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " TFIFO_OVF ,TX FIFO overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RFIFO_UNF ,RX FIFO underflow" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " NOACK ,No ACK from slave" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ARB_LOST ,Arbitration lost" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 1. " TFIFO_DATA_REQ ,TX FIFO data request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " RFIFO_DATA_REQ ,RX FIFO data request" "No interrupt,Interrupt"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CLK_DIVISOR_REGISTER_0,I2C Clock Divisor Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " I2C_CLK_DIVISOR_STD_FAST_MODE ,Divisor - fast mode"
|
|
hexmask.long.word 0x00 0.--15. 1. " I2C_CLK_DIVISOR_HSMODE ,Divisor - high speed mode"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "INTERRUPT_SOURCE_REGISTER_0,I2C Interrupt Source Register"
|
|
bitfld.long 0x00 28. " SLV_ACK_WITHHELD ,Waiting for sw explicit info about ack - source" "Unset,Set"
|
|
bitfld.long 0x00 27. " SLV_RD2WR ,Transaction switching from rd to wr - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SLV_WR2RD ,Transaction switching from wr to rd - source" "Unset,Set"
|
|
bitfld.long 0x00 25. " SLV_PKT_XFER_ERR ,Error occurred during slave xfer - source" "Unset,Set"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is empty - source" "Unset,Set"
|
|
else
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is full - source" "Unset,Set"
|
|
endif
|
|
bitfld.long 0x00 23. " SLV_RX_BUFFER_FILLED ,Slave RX buffer is full - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE ,Slave packet transfer complete - source" "Unset,Set"
|
|
bitfld.long 0x00 21. " SLV_TFIFO_OVF ,Slave TX FIFO overflow - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SLV_RFIFO_UNF ,Slave RX FIFO underflow - source" "Unset,Set"
|
|
bitfld.long 0x00 17. " SLV_TFIFO_DATA_REQ ,Slave TX FIFO data request - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SLV_RFIFO_DATA_REQ ,Slave RX FIFO data request - source" "Unset,Set"
|
|
bitfld.long 0x00 11. " BUS_CLEAR_DONE ,Bus clear done - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TLOW_MEXT_TIMEOUT ,SMBUS mext time-out - source" "Unset,Set"
|
|
bitfld.long 0x00 9. " TLOW_SEXT_TIMEOUT ,SMBUS sext time-out - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMEOUT ,SMBUS time-out - source" "Unset,Set"
|
|
bitfld.long 0x00 7. " PACKET_XFER_COMPLETE ,Packet has been transferred successfully - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE ,All the packets transferred successfully - source" "Unset,Set"
|
|
bitfld.long 0x00 5. " TFIFO_OVF ,TX FIFO overflow - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFIFO_UNF ,RX FIFO underflow - source" "Unset,Set"
|
|
bitfld.long 0x00 3. " NOACK ,No ACK from slave - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ARB_LOST ,Arbitration lost - source" "Unset,Set"
|
|
bitfld.long 0x00 1. " TFIFO_DATA_REQ ,TX FIFO data request - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RFIFO_DATA_REQ ,RX FIFO data request - source" "Unset,Set"
|
|
group.long 0x74++0x07
|
|
line.long 0x00 "INTERRUPT_SET_REGISTER_0,I2C Interrupt Source register"
|
|
bitfld.long 0x00 28. " SLV_ACK_WITHHELD ,Waiting for sw explicit info about ack - source - source" "No effect,Set"
|
|
bitfld.long 0x00 27. " SLV_RD2WR ,Transaction switching from rd to wr - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SLV_WR2RD ,Transaction switching from wr to rd - source" "No effect,Set"
|
|
bitfld.long 0x00 25. " SLV_PKT_XFER_ERR ,Error occurred during slave XFER - source" "No effect,Set"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is empty - source" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is full - source" "No effect,Set"
|
|
endif
|
|
bitfld.long 0x00 23. " SLV_RX_BUFFER_FILLED ,Slave RX buffer is full - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE ,Slave packet transfer complete - source" "No effect,Set"
|
|
bitfld.long 0x00 21. " SLV_TFIFO_OVF ,Slave TX FIFO overflow - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SLV_RFIFO_UNF ,Slave RX FIFO underflow - source" "No effect,Set"
|
|
bitfld.long 0x00 11. " BUS_CLEAR_DONE ,Bus clear done - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TLOW_MEXT_TIMEOUT ,SMBUS mext time-out - source" "No effect,Set"
|
|
bitfld.long 0x00 9. " TLOW_SEXT_TIMEOUT ,SMBUS sext time-out - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMEOUT ,SMBUS time-out - source" "No effect,Set"
|
|
bitfld.long 0x00 7. " PACKET_XFER_COMPLETE ,Packet has been transferred successfully - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE ,All the packets transferred successfully - source" "No effect,Set"
|
|
bitfld.long 0x00 5. " TFIFO_OVF ,TX FIFO overflow - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFIFO_UNF ,RX FIFO underflow - source" "No effect,Set"
|
|
bitfld.long 0x00 3. " NOACK ,No ACK from slave - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ARB_LOST ,Arbitration lost - source" "No effect,Set"
|
|
line.long 0x04 "SLV_TX_PACKET_FIFO_0,I2C Slave TX Packet FIFO"
|
|
rgroup.long 0x7C++0x07
|
|
line.long 0x00 "SLV_RX_FIFO_0,I2C Slave RX FIFO"
|
|
line.long 0x04 "SLV_PACKET_STATUS_0,I2C Slave Packet Status"
|
|
bitfld.long 0x04 25. " ACK_WITHHELD ,ACK is withheld for last byte and slave is waiting for host" "Bus is released,ACK is withheld"
|
|
bitfld.long 0x04 24. " TRANSFER_COMPLETE ,All the packets have been transferred successfully" "Not completed,Completed"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--23. 1. " TRANSFER_PKT_ID ,Current packet ID for which the transaction is happening"
|
|
hexmask.long.word 0x04 4.--15. 1. " TRANSFER_BYTENUM ,Number of bytes transferred in the current packet"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "BUS_CLEAR_CONFIG_0,I2C Bus Clear Configure"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BC_SCLK_THRESHOLD ,Send the clock pulses until this threshold is met"
|
|
bitfld.long 0x00 2. " BC_STOP_COND ,Bus clear operation" "No stopped,Stopped"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 1. " BC_TERMINATE ,Terminate the bus clear operation" "THRESHOLD,IMMEDIATE"
|
|
else
|
|
bitfld.long 0x00 1. " BC_TERMINATE ,Terminate the bus clear operation" "IMMEDIATE,THRESHOLD"
|
|
endif
|
|
bitfld.long 0x00 0. " BC_ENABLE ,Starts bus clear operation" "Disabled,Enabled"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "BUS_CLEAR_STATUS_0,Bus Clear Status"
|
|
bitfld.long 0x00 0. " BC_STATUS ,Bus clear" "Not cleared,Cleared"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CONFIG_LOAD_0,Spare Register"
|
|
bitfld.long 0x00 2. " TIMEOUT_CONFIG_LOAD ,Loads the timeout configuration" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SLV_CONFIG_LOAD ,Loads the slave configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR_CONFIG_LOAD ,Loads the master configuration" "Disabled,Enabled"
|
|
sif (cpuis("TEGRAX2"))
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CLKEN_OVERRIDE_0,I2C Clock Enable Override 0"
|
|
bitfld.long 0x00 4. " I2C_BUS_CLEAR_CLKEN_OVR ,Override for 2nd level clock enable for I2C bus clear logic" "Gated,Always on"
|
|
bitfld.long 0x00 3. " I2C_SLV_HIF_CLKEN_OVR ,Override for 2nd level clock enable for I2C slave to host interface logic" "Gated,Always on"
|
|
textline " "
|
|
bitfld.long 0x00 2. " I2C_SLV_CORE_CLKEN_OVR ,Override for 2nd level clock enable for I2C slave core logic" "Gated,Always on"
|
|
bitfld.long 0x00 0. " I2C_MST_CORE_CLKEN_OVR ,Override for 2nd level clock enable for I2C master core logic" "Gated,Always on"
|
|
endif
|
|
group.long 0x94++0x0F
|
|
line.long 0x00 "INTERFACE_TIMING_0_0,Interface Timing Register 0"
|
|
bitfld.long 0x00 8.--13. " THIGH ,High period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " TLOW ,Low period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "INTERFACE_TIMING_1_0,Interface Timing Register 1"
|
|
bitfld.long 0x04 24.--29. " TBUF ,Bus free time between STOP and START conditions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 16.--21. " TSU_STO ,Setup time for STOP condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x04 8.--13. " THD_STA ,Hold time for a START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 0.--5. " TSU_STA ,Setup time for a Repeated START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "HS_INTERFACE_TIMING_0_0,HS Interface Timing Register 0"
|
|
bitfld.long 0x08 8.--13. " HS_THIGH ,High period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 0.--5. " HS_TLOW ,Low period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "HS_INTERFACE_TIMING_1_0,HS Interface Timing Register 1"
|
|
bitfld.long 0x0C 16.--21. " HS_TSU_STO ,Setup time for STOP condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0C 8.--13. " HS_THD_STA ,Hold time for a START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--5. " HS_TSU_STA ,Setup time for a Repeated START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif !cpuis("TEGRAX1")
|
|
group.long 0xA8++0x07
|
|
line.long 0x00 "MASTER_RESET_CNTRL_0,I2C Master Reset Control Register"
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset" "Cleared,Asserted"
|
|
line.long 0x04 "SLV_RESET_CNTRL_0,I2C Slave Reset Control Register"
|
|
bitfld.long 0x04 0. " SOFT_RESET ,Soft reset" "Cleared,Asserted"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C-6"
|
|
base ad:0x7000D100
|
|
width 20.
|
|
if (((per.l(ad:0x7000D000))&0x10)==0x10)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CNFG_0,IC Controller Configuration Register"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Single,Multi"
|
|
bitfld.long 0x00 16. " HS_RND_TRIP_DLY_EFFECT ,Diagnostic bit to disable round trip delay effect on data rate in HS mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " MSTR_CLR_BUS_ON_TIMEOUT ,I2C master force clock low on timeout" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " DEBOUNCE_CNT ,De-bounce period for SDA and SCL lines" "No Debounce,2T,4T,6T,8T,10T,12T,14T"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NEW_MASTER_FSM ,Maintained for compatibility sake" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PACKET_MODE_EN ,Initiate transfer in packet mode" "NOP,GO"
|
|
bitfld.long 0x00 9. " SEND ,Master initiates the transaction in normal mode" "NOP,GO"
|
|
textline " "
|
|
bitfld.long 0x00 8. " NOACK ,No ACK mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CMD2 ,Read/Write Command for Slave 2" "Write,Read"
|
|
bitfld.long 0x00 6. " CMD1 ,Read/Write Command for Slave 1" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 5. " START ,Send Start byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SLV2 ,Enables a two slave transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--3. " LENGTH ,Number of bytes to be transmitted per transaction" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " A_MOD ,7-bit or a 10-bit slave address" "7-bit address,10-bit address"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CNFG_0,IC Controller Configuration Register"
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("TEGRAX2")
|
|
bitfld.long 0x00 17. " MULTI_MASTER_MODE ,Select single or multi master mode" "Single,Multi"
|
|
bitfld.long 0x00 16. " HS_RND_TRIP_DLY_EFFECT ,Diagnostic bit to disable round trip delay effect on data rate in HS mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " MSTR_CLR_BUS_ON_TIMEOUT ,I2C master force clock low on timeout" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " DEBOUNCE_CNT ,De-bounce period for SDA and SCL lines" "No Debounce,2T,4T,6T,8T,10T,12T,14T"
|
|
textline " "
|
|
bitfld.long 0x00 11. " NEW_MASTER_FSM ,Maintained for compatibility sake" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PACKET_MODE_EN ,Initiate transfer in packet mode" "NOP,GO"
|
|
bitfld.long 0x00 9. " SEND ,Master initiates the transaction in normal mode" "NOP,GO"
|
|
textline " "
|
|
bitfld.long 0x00 8. " NOACK ,No ACK mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CMD1 ,Read/Write Command for Slave 1" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 5. " START ,Send Start byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SLV2 ,Enables a two slave transaction" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--3. " LENGTH ,Number of bytes to be transmitted per transaction" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " A_MOD ,7-bit or a 10-bit slave address" "7-bit address,10-bit address"
|
|
endif
|
|
if (((per.l(ad:0x7000D000))&0x01)==0x01)
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "CMD_ADDR0_0,I2C Slave-1 Address"
|
|
hexmask.long.word 0x00 0.--9. 1. " ADDR0 ,I2C Slave-1 Address"
|
|
line.long 0x04 "CMD_ADDR1_0,I2C Slave-2 Address"
|
|
hexmask.long.word 0x04 0.--9. 1. " ADDR1 ,I2C Slave-2 Address"
|
|
else
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "CMD_ADDR0_0,I2C Slave-1 Address"
|
|
hexmask.long.byte 0x00 1.--7. 1. " ADDR0 ,I2C Slave-1 Address"
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMD_ADDR0[0] ,Indicates read/write transaction" "Write,Read"
|
|
endif
|
|
line.long 0x04 "CMD_ADDR1_0,I2C Slave-2 Address"
|
|
hexmask.long.byte 0x04 1.--7. 1. " ADDR1 ,I2C Slave-2 Address"
|
|
sif (cpuis("TEGRAX1")||cpuis("TEGRAX2"))
|
|
textline " "
|
|
bitfld.long 0x04 0. " CMD_ADDR1[0] ,Indicates read/write transaction" "Write,Read"
|
|
endif
|
|
endif
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "CMD_DATA1_0,I2C Controller Data 1 Transmit/Receive"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA4 ,Fourth data byte to be sent/received"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA3 ,Third data byte to be sent/received"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATA2 ,Second data byte to be sent/received"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA1 ,First data byte to be sent/received"
|
|
line.long 0x04 "CMD_DATA2_0,I2C Controller Data 2 Transmit/Receive"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA8 ,Eighth data byte to be sent/received"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA7 ,Seventh data byte to be sent/received"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA6 ,Sixth data byte to be sent/received"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA5 ,Fifth data byte to be sent/received"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "STATUS_0,I2C Controller Master Status"
|
|
bitfld.long 0x00 8. " BUSY ,Master busy" "Not busy,Busy"
|
|
bitfld.long 0x00 4.--7. " CMD2_STAT ,Transaction for Slave 2" "Successful,NOACK for byte 1,NOACK for byte 2,NOACK for byte 3,NOACK for byte 4,NOACK for byte 5,NOACK for byte 6,NOACK for byte 7,NOACK for byte 8,NOACK for byte 9,NOACK for byte 10,?..."
|
|
bitfld.long 0x00 0.--3. " CMD1_STAT ,Transaction for Slave 1" "Successful,NOACK for byte 1,NOACK for byte 2,NOACK for byte 3,NOACK for byte 4,NOACK for byte 5,NOACK for byte 6,NOACK for byte 7,NOACK for byte 8,NOACK for byte 9,NOACK for byte 10,?..."
|
|
sif (cpuis("TEGRAX2"))
|
|
if (((per.l(ad:0x7000D000+0x20))&0x100000)==0x100000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SL_CNFG_0,I2C Controller Slave Configuration"
|
|
bitfld.long 0x00 21. " SLV_XFER_ERR_CLK_STRETCH_EN ,Enables the slave stretch I2C SCL line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FIFO_XFER_EN ,FIFO transfer enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 8.--19. 1. " BUFFER_SIZE ,Payload size in bytes"
|
|
bitfld.long 0x00 7. " ACK_LAST_BYTE_VALID ,ACK the last byte valid (write-only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACK_LAST_BYTE ,ACK the last byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACK_WITHHOLD_EN ,Ack withhold feature enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PKT_MODE_EN ,Packet mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_SL ,Enable slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NEWSL ,Use new slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,Disable Slave acknowledge -The slave will not acknowledge reception of address or data byte" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESP ,Slave response to general call address" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SL_CNFG_0,I2C Controller Slave Configuration"
|
|
textline " "
|
|
bitfld.long 0x00 20. " FIFO_XFER_EN ,FIFO transfer enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 8.--19. 1. " BUFFER_SIZE ,Payload size in bytes"
|
|
bitfld.long 0x00 7. " ACK_LAST_BYTE_VALID ,ACK the last byte valid (write-only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACK_LAST_BYTE ,ACK the last byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACK_WITHHOLD_EN ,Ack withhold feature enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PKT_MODE_EN ,Packet mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_SL ,Enable slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NEWSL ,Use new slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,Disable Slave acknowledge -The slave will not acknowledge reception of address or data byte" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESP ,Slave response to general call address" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SL_CNFG_0,I2C Controller Slave Configuration"
|
|
bitfld.long 0x00 20. " FIFO_XFER_EN ,FIFO transfer enabled" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 8.--19. 1. " BUFFER_SIZE ,Payload size in bytes"
|
|
bitfld.long 0x00 7. " ACK_LAST_BYTE_VALID ,ACK the last byte valid(Write-Only)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ACK_LAST_BYTE ,ACK the last byte" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ACK_WITHHOLD_EN ,Ack withhold feature enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PKT_MODE_EN ,Packet mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENABLE_SL ,Enable slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " NEWSL ,Use new slave" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " NACK ,Disable Slave acknowledge -The slave will not acknowledge reception of address or data byte" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESP ,Slave response to general call address" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SL_RCVD_0,I2C Controller Slave Receive/Transmit Data"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SL_DATA ,Slave received data"
|
|
if (((per.l(ad:0x7000D000+0x28))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SL_STATUS_0,I2C Controller Slave Status"
|
|
hexmask.long.byte 0x00 8.--14. 1. " HW_MSTR_ADR ,Hardware master address received via general call addressing"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,Interrupt generated by the slave when hardware master address is received" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " REPROG_SL ,Interrupt generated by the slave after the General Call Address is 0x04" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RST_SL ,Interrupt generated by the slave after the General Call Address is 0x06" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,Slave Transaction complete" "Completed,In progress"
|
|
bitfld.long 0x00 3. " SL_IRQ ,Interrupt generated by slave" "Not interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RCVD ,New transaction received status" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " RNW ,Slave transaction status" "Write,Read"
|
|
bitfld.long 0x00 0. " ZA ,Zero address status" "No response,Response"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SL_STATUS_0,I2C Controller Slave Status"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,Interrupt generated by the slave when hardware master address is received" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " REPROG_SL ,Interrupt generated by the slave after the General Call Address is 0x04" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RST_SL ,Interrupt generated by the slave after the General Call Address is 0x06" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,Slave Transaction complete" "Completed,In progress"
|
|
bitfld.long 0x00 3. " SL_IRQ ,Interrupt generated by slave" "Not interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RCVD ,New transaction received status" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " RNW ,Slave transaction status" "Write,Read"
|
|
bitfld.long 0x00 0. " ZA ,Zero address status" "No response,Response"
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SL_ADDR1_0,I2C Controller Slave Address 1 Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SL_ADDR1 ,Slave address 1 (for a 10-bit slave address: least significant 8 bits)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SL_ADDR0 ,Slave address 0 (for a 10-bit slave address: least significant 8 bits)"
|
|
if (((per.l(ad:0x7000D000+0x30))&0x01)==0x00)&&(((per.l(ad:0x7000D000+0x30))&0x100)==0x00)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
elif (((per.l(ad:0x7000D000+0x30))&0x01)==0x00)&&(((per.l(ad:0x7000D000+0x30))&0x100)==0x100)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
bitfld.long 0x00 1.--2. " SL_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
elif (((per.l(ad:0x7000D000+0x30))&0x01)==0x01)&&(((per.l(ad:0x7000D000+0x30))&0x100)==0x00)
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
bitfld.long 0x00 9.--10. " SL1_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
else
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SL_ADDR2_0,I2C Controller Slave Address 2 Register"
|
|
bitfld.long 0x00 16. " SELECT_SLAVE ,Select slave" "ADDR0,ADDR1"
|
|
bitfld.long 0x00 9.--10. " SL1_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SL1_VLD ,Addressing mode" "7bit,10bit"
|
|
bitfld.long 0x00 1.--2. " SL_ADDR_HI ,Two most significant bits of the address" "00,01,10,11"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VLD ,Addressing mode" "7bit,10bit"
|
|
endif
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "TLOW_SEXT_0,I2C Controller SMBUS Timeout Thresholds"
|
|
bitfld.long 0x00 27. " RST_SL_ON_TIMEOUT ,Reset Slave state machine on time-out" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TLOW_MEXT_EN ,Enable TLOW_MEXT counter" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " TLOW_SEXT_EN ,Enable TLOW_SEXT counter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TIMEOUT_EN ,Enable TIMEOUT counter" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOW_MEXT ,Cumulative clock low extend time (transfer period)"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOW_SEXT ,Cumulative clock low extend time (complete transfer)"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " TIMEOUT ,Clock low timeout period in milliseconds"
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "SL_DELAY_COUNT_0,I2C Slave Controller Delay Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " SL_DELAY_COUNT ,Timing between address-data cycles or data-data cycles"
|
|
line.long 0x04 "SL_INT_MASK_0,I2C Controller Slave Mask"
|
|
bitfld.long 0x04 7. " HW_MSTR_INT ,HW_MSTR_INT (Hardware master address is received) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " REPROG_SL ,REPROG_SL (General Call Address is 0x04) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " RST_SL ,RST_SL (General Call Address is 0x06) Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " END_TRANS ,END_TRANS (Transaction complete) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " SL_IRQ ,SL_IRQ (Interrupt generated) Mask" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCVD ,RCVD (Transaction received) Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ZA ,ZA (Zero address) Mask" "Disabled,Enabled"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SL_INT_SOURCE_0,I2C Controller Slave Interrupt Source"
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,HW_MSTR_INT (Hardware master address is received) Source" "Unset,Set"
|
|
bitfld.long 0x00 6. " REPROG_SL ,REPROG_SL (General Call Address is 0x04) Source" "Unset,Set"
|
|
bitfld.long 0x00 5. " RST_SL ,RST_SL (General Call Address is 0x06) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,END_TRANS (Transaction complete) Source" "Unset,Set"
|
|
bitfld.long 0x00 3. " SL_IRQ ,SL_IRQ (Interrupt generated) Source" "Unset,Set"
|
|
bitfld.long 0x00 2. " RCVD ,RCVD (Transaction received) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ZA ,ZA (Zero address) Source" "Unset,Set"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SL_INT_SET_0,I2C Controller Slave Interrupt Set"
|
|
bitfld.long 0x00 7. " HW_MSTR_INT ,HW_MSTR_INT (Hardware master address is received) Source" "Unset,Set"
|
|
bitfld.long 0x00 6. " REPROG_SL ,REPROG_SL (General Call Address is 0x04) Source" "Unset,Set"
|
|
bitfld.long 0x00 5. " RST_SL ,RST_SL (General Call Address is 0x06) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " END_TRANS ,END_TRANS (Transaction complete) Source" "Unset,Set"
|
|
bitfld.long 0x00 3. " SL_IRQ ,SL_IRQ (Interrupt generated) Source" "Unset,Set"
|
|
bitfld.long 0x00 2. " RCVD ,RCVD (Transaction received) Source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ZA ,ZA (Zero address) Source" "Unset,Set"
|
|
tree "Packet Mode"
|
|
width 29.
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "TX_PACKET_FIFO_0,TX Packet FIFO"
|
|
rgroup.long 0x54++0x07
|
|
line.long 0x00 "RX_FIFO_0,Header or I2C Specific Header or Data"
|
|
line.long 0x04 "PACKET_TRANSFER_STATUS_0,I2C Packet Transfer Status"
|
|
bitfld.long 0x04 24. " TRANSFER_COMPLETE ,The packet transfer for which last packet is set has been completed" "Unset,Set"
|
|
hexmask.long.byte 0x04 16.--23. 1. " TRANSFER_PKT_ID ,The current packet ID for which the transaction is happening on the bus"
|
|
textline " "
|
|
hexmask.long.word 0x04 4.--15. 1. " TRANSFER_BYTENUM ,The number of bytes transferred in the current packet"
|
|
bitfld.long 0x04 3. " NOACK_FOR_ADDR ,No ACK received for the address byte" "ACK,No ACK"
|
|
textline " "
|
|
bitfld.long 0x04 2. " NOACK_FOR_DATA ,No ACK received for the data byte" "ACK,No ACK"
|
|
bitfld.long 0x04 1. " ARB_LOST ,Arbitration lost for the current byte" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CONTROLLER_BUSY ,Controller is busy" "Not busy,Busy"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "FIFO_CONTROL_0,I2C FIFO Control Register"
|
|
bitfld.long 0x00 13.--15. " SLV_TX_FIFO_TRIG ,Slave Transmit FIFO trigger" "1 word,2 words,?..."
|
|
bitfld.long 0x00 10.--12. " SLV_RX_FIFO_TRIG ,Slave Receive FIFO trigger" "1 word,2 words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SLV_TX_FIFO_FLUSH ,Flush the TX FIFO" "No effect,Flush"
|
|
bitfld.long 0x00 8. " SLV_RX_FIFO_FLUSH ,Flush the RX FIFO" "No effect,Flush"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " TX_FIFO_TRIG ,Transmit FIFO trigger level" "1 word,2 words,?..."
|
|
bitfld.long 0x00 2.--4. " RX_FIFO_TRIG ,Receive FIFO trigger level" "1 word,2 words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " TX_FIFO_FLUSH ,Flush the TX FIFO" "No effect,Flush"
|
|
bitfld.long 0x00 0. " RX_FIFO_FLUSH ,Flush the RX FIFO" "No effect,Flush"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "FIFO_STATUS_0,I2C FIFO Status Register"
|
|
bitfld.long 0x00 25. " SLV_XFER_ERR_REASON ,Nature of the packet transfer error" "Terminated before end,Not terminated"
|
|
bitfld.long 0x00 20.--23. " SLV_TX_FIFO_EMPTY_CNT ,The number of slots that can be written to the slave TX" "TX FIFO Full,1 slot empty,2 slots empty,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SLV_RX_FIFO_FULL_CNT ,The number of slots to be read from the Slave RX" "RX FIFO empty,1 slot full,2 slots full,?..."
|
|
bitfld.long 0x00 4.--7. " TX_FIFO_EMPTY_CNT ,The number of slots that can be written to the TX FIFO" "TX FIFO Full,1 slot empty,2 slots empty,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " RX_FIFO_FULL_CNT ,The number of slots to be read from the RX FIFO" "RX FIFO empty,1 slot full,2 slots full,?..."
|
|
textline " "
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "INTERRUPT_MASK_REGISTER_0,I2C Interrupt Mask Register"
|
|
bitfld.long 0x00 28. " SLV_ACK_WITHHELD_INT_EN ,SLV_ACK_WITHHELD (Withheld - waiting for sw explicit info about ACK) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SLV_RD2WR_INT_EN ,SLV_RD2WR (Transaction switching from rd to wr) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SLV_WR2RD_INT_EN ,SLV_WR2RD (Transaction switching from wr to rd) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " SLV_PKT_XFER_ERR_INT_EN ,SLV_PKT_XFER_ERR (Request error) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ_INT_EN ,SLV_TX_BUFFER_REQ (Slave TX buffer is empty) Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ_INT_EN ,SLV_TX_BUFFER_REQ (Slave TX buffer is full) Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 23. " SLV_RX_BUFFER_FILLED_INT_EN ,SLV_RX_BUFFER_FILLED (Slave Rx buffer is full) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE_INT_EN ,SLV_PACKET_XFER_COMPLETE (Slave packet transfer complete) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SLV_TFIFO_OVF_REQ_INT_EN ,SLV_TFIFO_OVF_REQ (Slave TX FIFO overflow) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SLV_RFIFO_UNF_REQ_INT_EN ,SLV_RFIFO_UNF_REQ (Slave Rx FIFO underflow) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SLV_TFIFO_DATA_REQ_INT_EN ,SLV_TFIFO_DATA_REQ (Slave TX FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SLV_RFIFO_DATA_REQ_INT_EN ,SLV_RFIFO_DATA_REQ (Slave Rx FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " BUS_CLEAR_DONE_INT_EN ,BUS_CLEAR_DONE (Bus clear done status) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TLOW_MEXT_TIMEOUT_EN ,TLOW_MEXT_TIMEOUT_EN (SMBUS mext time-out) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TLOW_SEXT_TIMEOUT_EN ,TLOW_SEXT_TIMEOUT_EN (SMBUS sext time-out) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMEOUT_INT_EN ,TIMEOUT (SMBUS time-out) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PACKET_XFER_COMPLETE_INT_EN ,PACKET_XFER_COMPLETE (Packet has been transferred successfully) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE_INT_EN ,ALL_PACKETS_XFER_COMPLETE (All the packets transferred successfully) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " TFIFO_OVF_INT_EN ,TFIFO_OVF (TX FIFO overflow) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFIFO_UNF_INT_EN ,RFIFO_UNF (Rx FIFO underflow) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NOACK_INT_EN ,NOACK (No ACK from slave) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ARB_LOST_INT_EN ,ARB_LOST (Arbitration lost) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TFIFO_DATA_REQ_INT_EN ,TFIFO_DATA_REQ (TX FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RFIFO_DATA_REQ_INT_EN ,RFIFO_DATA_REQ (RX FIFO data request) Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "INTERRUPT_STATUS_REGISTER_0,I2C Interrupt Status Register"
|
|
eventfld.long 0x00 28. " SLV_ACK_WITHHELD ,Withheld - Waiting for sw explicit info about ACK" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 27. " SLV_RD2WR ,Transaction switching from rd to wr" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 26. " SLV_WR2RD ,Transaction switching from wr to rd" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " SLV_PKT_XFER_ERR ,Request error" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
eventfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is empty" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is full" "No interrupt,Interrupt"
|
|
endif
|
|
eventfld.long 0x00 23. " SLV_RX_BUFFER_FILLED ,Slave RX buffer is full" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE ,Slave packet transfer complete" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " SLV_TFIFO_OVF ,Slave TX FIFO overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 20. " SLV_RFIFO_UN ,Slave RX FIFO underflow" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 17. " SLV_TFIFO_DATA_REQ ,Slave TX FIFO data request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " SLV_RFIFO_DATA_REQ ,Slave Rx FIFO data request" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " BUS_CLEAR_DONE ,Bus clear done status" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
eventfld.long 0x00 10. " TLOW_MEXT_TIMEOUT ,SMBUS mext time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " TLOW_SEXT_TIMEOUT ,SMBUS sext time-out" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 10. " TLOW_MEXT_TIMEOUT_EN ,SMBUS mext time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " TLOW_SEXT_TIMEOUT_EN ,SMBUS sext time-out" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 8. " TIMEOUT ,SMBUS time-out" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " PACKET_XFER_COMPLETE ,Packet has been transferred successfully" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE ,All the packets transferred successfully" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " TFIFO_OVF ,TX FIFO overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RFIFO_UNF ,RX FIFO underflow" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " NOACK ,No ACK from slave" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ARB_LOST ,Arbitration lost" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 1. " TFIFO_DATA_REQ ,TX FIFO data request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " RFIFO_DATA_REQ ,RX FIFO data request" "No interrupt,Interrupt"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CLK_DIVISOR_REGISTER_0,I2C Clock Divisor Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " I2C_CLK_DIVISOR_STD_FAST_MODE ,Divisor - fast mode"
|
|
hexmask.long.word 0x00 0.--15. 1. " I2C_CLK_DIVISOR_HSMODE ,Divisor - high speed mode"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "INTERRUPT_SOURCE_REGISTER_0,I2C Interrupt Source Register"
|
|
bitfld.long 0x00 28. " SLV_ACK_WITHHELD ,Waiting for sw explicit info about ack - source" "Unset,Set"
|
|
bitfld.long 0x00 27. " SLV_RD2WR ,Transaction switching from rd to wr - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SLV_WR2RD ,Transaction switching from wr to rd - source" "Unset,Set"
|
|
bitfld.long 0x00 25. " SLV_PKT_XFER_ERR ,Error occurred during slave xfer - source" "Unset,Set"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is empty - source" "Unset,Set"
|
|
else
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is full - source" "Unset,Set"
|
|
endif
|
|
bitfld.long 0x00 23. " SLV_RX_BUFFER_FILLED ,Slave RX buffer is full - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE ,Slave packet transfer complete - source" "Unset,Set"
|
|
bitfld.long 0x00 21. " SLV_TFIFO_OVF ,Slave TX FIFO overflow - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SLV_RFIFO_UNF ,Slave RX FIFO underflow - source" "Unset,Set"
|
|
bitfld.long 0x00 17. " SLV_TFIFO_DATA_REQ ,Slave TX FIFO data request - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SLV_RFIFO_DATA_REQ ,Slave RX FIFO data request - source" "Unset,Set"
|
|
bitfld.long 0x00 11. " BUS_CLEAR_DONE ,Bus clear done - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TLOW_MEXT_TIMEOUT ,SMBUS mext time-out - source" "Unset,Set"
|
|
bitfld.long 0x00 9. " TLOW_SEXT_TIMEOUT ,SMBUS sext time-out - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMEOUT ,SMBUS time-out - source" "Unset,Set"
|
|
bitfld.long 0x00 7. " PACKET_XFER_COMPLETE ,Packet has been transferred successfully - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE ,All the packets transferred successfully - source" "Unset,Set"
|
|
bitfld.long 0x00 5. " TFIFO_OVF ,TX FIFO overflow - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFIFO_UNF ,RX FIFO underflow - source" "Unset,Set"
|
|
bitfld.long 0x00 3. " NOACK ,No ACK from slave - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ARB_LOST ,Arbitration lost - source" "Unset,Set"
|
|
bitfld.long 0x00 1. " TFIFO_DATA_REQ ,TX FIFO data request - source" "Unset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RFIFO_DATA_REQ ,RX FIFO data request - source" "Unset,Set"
|
|
group.long 0x74++0x07
|
|
line.long 0x00 "INTERRUPT_SET_REGISTER_0,I2C Interrupt Source register"
|
|
bitfld.long 0x00 28. " SLV_ACK_WITHHELD ,Waiting for sw explicit info about ack - source - source" "No effect,Set"
|
|
bitfld.long 0x00 27. " SLV_RD2WR ,Transaction switching from rd to wr - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SLV_WR2RD ,Transaction switching from wr to rd - source" "No effect,Set"
|
|
bitfld.long 0x00 25. " SLV_PKT_XFER_ERR ,Error occurred during slave XFER - source" "No effect,Set"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is empty - source" "No effect,Set"
|
|
else
|
|
bitfld.long 0x00 24. " SLV_TX_BUFFER_REQ ,Slave TX buffer is full - source" "No effect,Set"
|
|
endif
|
|
bitfld.long 0x00 23. " SLV_RX_BUFFER_FILLED ,Slave RX buffer is full - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SLV_PACKET_XFER_COMPLETE ,Slave packet transfer complete - source" "No effect,Set"
|
|
bitfld.long 0x00 21. " SLV_TFIFO_OVF ,Slave TX FIFO overflow - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SLV_RFIFO_UNF ,Slave RX FIFO underflow - source" "No effect,Set"
|
|
bitfld.long 0x00 11. " BUS_CLEAR_DONE ,Bus clear done - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TLOW_MEXT_TIMEOUT ,SMBUS mext time-out - source" "No effect,Set"
|
|
bitfld.long 0x00 9. " TLOW_SEXT_TIMEOUT ,SMBUS sext time-out - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMEOUT ,SMBUS time-out - source" "No effect,Set"
|
|
bitfld.long 0x00 7. " PACKET_XFER_COMPLETE ,Packet has been transferred successfully - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ALL_PACKETS_XFER_COMPLETE ,All the packets transferred successfully - source" "No effect,Set"
|
|
bitfld.long 0x00 5. " TFIFO_OVF ,TX FIFO overflow - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RFIFO_UNF ,RX FIFO underflow - source" "No effect,Set"
|
|
bitfld.long 0x00 3. " NOACK ,No ACK from slave - source" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ARB_LOST ,Arbitration lost - source" "No effect,Set"
|
|
line.long 0x04 "SLV_TX_PACKET_FIFO_0,I2C Slave TX Packet FIFO"
|
|
rgroup.long 0x7C++0x07
|
|
line.long 0x00 "SLV_RX_FIFO_0,I2C Slave RX FIFO"
|
|
line.long 0x04 "SLV_PACKET_STATUS_0,I2C Slave Packet Status"
|
|
bitfld.long 0x04 25. " ACK_WITHHELD ,ACK is withheld for last byte and slave is waiting for host" "Bus is released,ACK is withheld"
|
|
bitfld.long 0x04 24. " TRANSFER_COMPLETE ,All the packets have been transferred successfully" "Not completed,Completed"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--23. 1. " TRANSFER_PKT_ID ,Current packet ID for which the transaction is happening"
|
|
hexmask.long.word 0x04 4.--15. 1. " TRANSFER_BYTENUM ,Number of bytes transferred in the current packet"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "BUS_CLEAR_CONFIG_0,I2C Bus Clear Configure"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BC_SCLK_THRESHOLD ,Send the clock pulses until this threshold is met"
|
|
bitfld.long 0x00 2. " BC_STOP_COND ,Bus clear operation" "No stopped,Stopped"
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 1. " BC_TERMINATE ,Terminate the bus clear operation" "THRESHOLD,IMMEDIATE"
|
|
else
|
|
bitfld.long 0x00 1. " BC_TERMINATE ,Terminate the bus clear operation" "IMMEDIATE,THRESHOLD"
|
|
endif
|
|
bitfld.long 0x00 0. " BC_ENABLE ,Starts bus clear operation" "Disabled,Enabled"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "BUS_CLEAR_STATUS_0,Bus Clear Status"
|
|
bitfld.long 0x00 0. " BC_STATUS ,Bus clear" "Not cleared,Cleared"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CONFIG_LOAD_0,Spare Register"
|
|
bitfld.long 0x00 2. " TIMEOUT_CONFIG_LOAD ,Loads the timeout configuration" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SLV_CONFIG_LOAD ,Loads the slave configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTR_CONFIG_LOAD ,Loads the master configuration" "Disabled,Enabled"
|
|
sif (cpuis("TEGRAX2"))
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CLKEN_OVERRIDE_0,I2C Clock Enable Override 0"
|
|
bitfld.long 0x00 4. " I2C_BUS_CLEAR_CLKEN_OVR ,Override for 2nd level clock enable for I2C bus clear logic" "Gated,Always on"
|
|
bitfld.long 0x00 3. " I2C_SLV_HIF_CLKEN_OVR ,Override for 2nd level clock enable for I2C slave to host interface logic" "Gated,Always on"
|
|
textline " "
|
|
bitfld.long 0x00 2. " I2C_SLV_CORE_CLKEN_OVR ,Override for 2nd level clock enable for I2C slave core logic" "Gated,Always on"
|
|
bitfld.long 0x00 0. " I2C_MST_CORE_CLKEN_OVR ,Override for 2nd level clock enable for I2C master core logic" "Gated,Always on"
|
|
endif
|
|
group.long 0x94++0x0F
|
|
line.long 0x00 "INTERFACE_TIMING_0_0,Interface Timing Register 0"
|
|
bitfld.long 0x00 8.--13. " THIGH ,High period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " TLOW ,Low period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "INTERFACE_TIMING_1_0,Interface Timing Register 1"
|
|
bitfld.long 0x04 24.--29. " TBUF ,Bus free time between STOP and START conditions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 16.--21. " TSU_STO ,Setup time for STOP condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x04 8.--13. " THD_STA ,Hold time for a START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 0.--5. " TSU_STA ,Setup time for a Repeated START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "HS_INTERFACE_TIMING_0_0,HS Interface Timing Register 0"
|
|
bitfld.long 0x08 8.--13. " HS_THIGH ,High period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 0.--5. " HS_TLOW ,Low period of the SCL clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "HS_INTERFACE_TIMING_1_0,HS Interface Timing Register 1"
|
|
bitfld.long 0x0C 16.--21. " HS_TSU_STO ,Setup time for STOP condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0C 8.--13. " HS_THD_STA ,Hold time for a START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--5. " HS_TSU_STA ,Setup time for a Repeated START condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif !cpuis("TEGRAX1")
|
|
group.long 0xA8++0x07
|
|
line.long 0x00 "MASTER_RESET_CNTRL_0,I2C Master Reset Control Register"
|
|
bitfld.long 0x00 0. " SOFT_RESET ,Soft reset" "Cleared,Asserted"
|
|
line.long 0x04 "SLV_RESET_CNTRL_0,I2C Slave Reset Control Register"
|
|
bitfld.long 0x04 0. " SOFT_RESET ,Soft reset" "Cleared,Asserted"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "UART and VFIT Controller"
|
|
tree "UART-A"
|
|
base ad:0x70006000
|
|
width 15.
|
|
if (((per.l((ad:0x70006000+0x0C)))&0x80)==0x00)
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "RBR_A/THR_A,Receive/Transmit Holding Register"
|
|
in
|
|
textline " "
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IER_DLAB,Interrupt Enable Register"
|
|
bitfld.long 0x00 5. " IE_EORD ,Interrupt enable for end of received data" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IE_RX_TIMEOUT ,Interrupt enable for Rx FIFO timeout" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IE_MSI ,Interrupt enable for modem status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IE_RXS ,Interrupt enable for receiver line status interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE_THR ,Interrupt enable for transmitter holding register empty interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IE_RHR ,Interrupt enable for received data interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "IIR,Interrupt Enable And Divisor Latch MSByte Registers"
|
|
bitfld.long 0x00 6.--7. " EN_FIFO ,FIFO mode status" "Mode 16450,Mode 16550,?..."
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 1.--3. " IS_PRI ,Encoded interrupt ID" "Modem status,TX holding register empty,RX data available,Overrun/parity/framing error,Eord_timeout_intr,,Rx_timeout_intr,?..."
|
|
else
|
|
bitfld.long 0x00 1.--3. " IS_PRI ,Encoded interrupt ID" "Modem status,TX data available,RX data available,Overrun/parity/framing error,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " IS_STA ,Interrupt pending" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "THR_DLAB,UART Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLL_A ,Divisor latch LSB"
|
|
line.long 0x04 "IER_DLAB,Divisor Latch MSByte Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLM_A ,Divisor latch MSB"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "FCR,Interrupt Enable And Divisor Latch MSByte Registers"
|
|
bitfld.long 0x00 6.--7. " RX_TRIG ,RX trigger" "FIFO count > 1,FIFO count > 4,FIFO count > 8,FIFO count > 16"
|
|
bitfld.long 0x00 4.--5. " TX_TRIG ,TX trigger" "FIFO count > 16,FIFO count > 8,FIFO count > 4,FIFO count > 1"
|
|
bitfld.long 0x00 3. " DMA ,DMA mode change" "No effect,Change"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TX_CLR ,Clears the contents of the transmit FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 1. " RX_CLR ,Clears the contents of the receive FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 0. " FCR_EN_FIFO ,Enable the transmit and receive FIFO" "Disable,Enable"
|
|
endif
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "LCR,UART Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SET_B ,Set BREAK condition" "No break,Break"
|
|
bitfld.long 0x00 5. " SET_P ,Set parity to value in LCR" "No parity,Parity"
|
|
bitfld.long 0x00 4. " EVEN ,Even parity format" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PAR ,Parity sent" "No parity,Parity"
|
|
bitfld.long 0x00 2. " STOP ,Stop bits" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " WD_SIZE ,Word length" "5 bit,6 bit,7 bit,8 bit"
|
|
line.long 0x04 "MCR,UART Modem Control Register"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x04 10. " OLD_SIR_DECODE ,Diagnostics bit to use the required SIR decode path" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--9. " RI_POLARITY ,RI modem status interrupt trigger edge selection" "Rising,Falling,Both,?..."
|
|
bitfld.long 0x04 7. " DEL_QUAL_CTS_EN ,Diagnostics bit to use the old qualified CTS in TX state machine" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " RTS_EN ,RTS hardware flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CTS_EN ,CTS hardware flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LOOPBK ,Internal loop back enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RTS ,Force RTS" "Force hi,Force low"
|
|
textline " "
|
|
bitfld.long 0x04 0. " DTR ,Force DTR" "Force hi,Force low"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "LSR,UART Line Status Register"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 9. " RX_FIFO_EMPTY ,Receiver FIFO status" "Not empty,Empty"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " TX_FIFO_FULL ,Transmitter FIFO full status" "Not full,Full"
|
|
bitfld.long 0x00 7. " FIFOE ,Receive FIFO error" "No error,Error"
|
|
bitfld.long 0x00 6. " TMTY ,Transmit shift reg empty status" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " THRE ,Transmit holding register is empty" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " BRK ,BREAK condition detected on line" "No break,Break"
|
|
bitfld.long 0x00 3. " FERR ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 2. " PERR ,Parity error" "No error,Error"
|
|
bitfld.long 0x00 1. " OVRF ,Receiver overrun error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDR ,Receiver data ready" "No data in FIFO,Data in FIFO"
|
|
group.long 0x18++0x13
|
|
line.long 0x00 "MSR,UART Modem Status Register"
|
|
bitfld.long 0x00 7. " CD ,State of carrier detect pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RI ,State of ring indicator pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DSR ,State of data set ready pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CTS ,State of clear to send pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DCD ,Change (Delta) in CD state detected" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DRI ,Change (Delta) in RI state detected" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DDSR ,Change (Delta) in DSR state detected" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DCTS ,Change (Delta) in CTS state detected" "Disabled,Enabled"
|
|
line.long 0x04 "SPR,UART Scratch Pad Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SPR_A ,Scratch pad"
|
|
line.long 0x08 "IRDA_CSR,UART IrDA Pulse Coding CSR Register"
|
|
bitfld.long 0x08 7. " SIR_A ,Enable SIR coder" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " PWT_A ,Baud pulse" "3/16,4/16"
|
|
bitfld.long 0x08 3. " INVERT_RTS ,Inverts the normally inactive high nRTS pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " INVERT_CTS ,Inverts the normally inactive high nCTS pin" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " INVERT_TXD ,Inverts the normally inactive high TXD pin" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " INVERT_RXD ,Inverts the normally inactive high RXD pin" "Disabled,Enabled"
|
|
line.long 0x0C "RX_FIFO_CFG,UART RX FIFO Configuration Register"
|
|
bitfld.long 0x0C 7. " EN_RX_FIFO_TRIG ,Enable use of RX FIFO trigger count" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--5. " RX_FIFO_TRIG ,Set RX FIFO trigger level" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
line.long 0x10 "MIE,UART Modem Interrupt Enable Register"
|
|
bitfld.long 0x10 3. " DCD_INT_EN ,Interrupt enable for change in CD state detected" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DRI_INT_EN ,Interrupt enable for change in RI state detected" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DDSR_INT_EN ,Interrupt enable for change in DSR state detected" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DCTS_INT_EN ,Interrupt enable for change in CTS state detected" "Disabled,Enabled"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "VENDOR_STATUS,UART Controller Status Register"
|
|
bitfld.long 0x00 24.--29. " TX_FIFO_COUNTER ,TX FIFO current entries number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " RX_FIFO_COUNTER ,RX FIFO current entries number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TX_OVERRUN ,TX FIFO overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 2. " RX_OVERRUN ,RX FIFO overrun" "No overrun,Overrun"
|
|
textline " "
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 1. " UART_RX_IDLE ,RX path idle status" "Busy,Idle"
|
|
bitfld.long 0x00 0. " UART_TX_IDLE ,TX path idle status" "Busy,Idle"
|
|
endif
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "UART_ASR,UART Auto Sense Baud Register"
|
|
bitfld.long 0x00 31. " VALID ,Counting the clocks between two successive clock edges finished" "Not finished,Finished"
|
|
bitfld.long 0x00 30. " BUSY ,ASR busy" "Idle,Busy"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RX_RATE_SENSE_H ,High count of clock edges between two successive clock edges"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_RATE_SENSE_L ,Low count of clock edges between two successive clock edges"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART-B"
|
|
base ad:0x70006040
|
|
width 15.
|
|
if (((per.l((ad:0x70006040+0x0C)))&0x80)==0x00)
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "RBR_A/THR_A,Receive/Transmit Holding Register"
|
|
in
|
|
textline " "
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IER_DLAB,Interrupt Enable Register"
|
|
bitfld.long 0x00 5. " IE_EORD ,Interrupt enable for end of received data" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IE_RX_TIMEOUT ,Interrupt enable for Rx FIFO timeout" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IE_MSI ,Interrupt enable for modem status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IE_RXS ,Interrupt enable for receiver line status interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE_THR ,Interrupt enable for transmitter holding register empty interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IE_RHR ,Interrupt enable for received data interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "IIR,Interrupt Enable And Divisor Latch MSByte Registers"
|
|
bitfld.long 0x00 6.--7. " EN_FIFO ,FIFO mode status" "Mode 16450,Mode 16550,?..."
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 1.--3. " IS_PRI ,Encoded interrupt ID" "Modem status,TX holding register empty,RX data available,Overrun/parity/framing error,Eord_timeout_intr,,Rx_timeout_intr,?..."
|
|
else
|
|
bitfld.long 0x00 1.--3. " IS_PRI ,Encoded interrupt ID" "Modem status,TX data available,RX data available,Overrun/parity/framing error,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " IS_STA ,Interrupt pending" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "THR_DLAB,UART Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLL_A ,Divisor latch LSB"
|
|
line.long 0x04 "IER_DLAB,Divisor Latch MSByte Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLM_A ,Divisor latch MSB"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "FCR,Interrupt Enable And Divisor Latch MSByte Registers"
|
|
bitfld.long 0x00 6.--7. " RX_TRIG ,RX trigger" "FIFO count > 1,FIFO count > 4,FIFO count > 8,FIFO count > 16"
|
|
bitfld.long 0x00 4.--5. " TX_TRIG ,TX trigger" "FIFO count > 16,FIFO count > 8,FIFO count > 4,FIFO count > 1"
|
|
bitfld.long 0x00 3. " DMA ,DMA mode change" "No effect,Change"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TX_CLR ,Clears the contents of the transmit FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 1. " RX_CLR ,Clears the contents of the receive FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 0. " FCR_EN_FIFO ,Enable the transmit and receive FIFO" "Disable,Enable"
|
|
endif
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "LCR,UART Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SET_B ,Set BREAK condition" "No break,Break"
|
|
bitfld.long 0x00 5. " SET_P ,Set parity to value in LCR" "No parity,Parity"
|
|
bitfld.long 0x00 4. " EVEN ,Even parity format" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PAR ,Parity sent" "No parity,Parity"
|
|
bitfld.long 0x00 2. " STOP ,Stop bits" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " WD_SIZE ,Word length" "5 bit,6 bit,7 bit,8 bit"
|
|
line.long 0x04 "MCR,UART Modem Control Register"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x04 10. " OLD_SIR_DECODE ,Diagnostics bit to use the required SIR decode path" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--9. " RI_POLARITY ,RI modem status interrupt trigger edge selection" "Rising,Falling,Both,?..."
|
|
bitfld.long 0x04 7. " DEL_QUAL_CTS_EN ,Diagnostics bit to use the old qualified CTS in TX state machine" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " RTS_EN ,RTS hardware flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CTS_EN ,CTS hardware flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LOOPBK ,Internal loop back enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RTS ,Force RTS" "Force hi,Force low"
|
|
textline " "
|
|
bitfld.long 0x04 0. " DTR ,Force DTR" "Force hi,Force low"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "LSR,UART Line Status Register"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 9. " RX_FIFO_EMPTY ,Receiver FIFO status" "Not empty,Empty"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " TX_FIFO_FULL ,Transmitter FIFO full status" "Not full,Full"
|
|
bitfld.long 0x00 7. " FIFOE ,Receive FIFO error" "No error,Error"
|
|
bitfld.long 0x00 6. " TMTY ,Transmit shift reg empty status" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " THRE ,Transmit holding register is empty" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " BRK ,BREAK condition detected on line" "No break,Break"
|
|
bitfld.long 0x00 3. " FERR ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 2. " PERR ,Parity error" "No error,Error"
|
|
bitfld.long 0x00 1. " OVRF ,Receiver overrun error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDR ,Receiver data ready" "No data in FIFO,Data in FIFO"
|
|
group.long 0x18++0x13
|
|
line.long 0x00 "MSR,UART Modem Status Register"
|
|
bitfld.long 0x00 7. " CD ,State of carrier detect pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RI ,State of ring indicator pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DSR ,State of data set ready pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CTS ,State of clear to send pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DCD ,Change (Delta) in CD state detected" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DRI ,Change (Delta) in RI state detected" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DDSR ,Change (Delta) in DSR state detected" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DCTS ,Change (Delta) in CTS state detected" "Disabled,Enabled"
|
|
line.long 0x04 "SPR,UART Scratch Pad Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SPR_A ,Scratch pad"
|
|
line.long 0x08 "IRDA_CSR,UART IrDA Pulse Coding CSR Register"
|
|
bitfld.long 0x08 7. " SIR_A ,Enable SIR coder" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " PWT_A ,Baud pulse" "3/16,4/16"
|
|
bitfld.long 0x08 3. " INVERT_RTS ,Inverts the normally inactive high nRTS pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " INVERT_CTS ,Inverts the normally inactive high nCTS pin" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " INVERT_TXD ,Inverts the normally inactive high TXD pin" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " INVERT_RXD ,Inverts the normally inactive high RXD pin" "Disabled,Enabled"
|
|
line.long 0x0C "RX_FIFO_CFG,UART RX FIFO Configuration Register"
|
|
bitfld.long 0x0C 7. " EN_RX_FIFO_TRIG ,Enable use of RX FIFO trigger count" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--5. " RX_FIFO_TRIG ,Set RX FIFO trigger level" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
line.long 0x10 "MIE,UART Modem Interrupt Enable Register"
|
|
bitfld.long 0x10 3. " DCD_INT_EN ,Interrupt enable for change in CD state detected" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DRI_INT_EN ,Interrupt enable for change in RI state detected" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DDSR_INT_EN ,Interrupt enable for change in DSR state detected" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DCTS_INT_EN ,Interrupt enable for change in CTS state detected" "Disabled,Enabled"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "VENDOR_STATUS,UART Controller Status Register"
|
|
bitfld.long 0x00 24.--29. " TX_FIFO_COUNTER ,TX FIFO current entries number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " RX_FIFO_COUNTER ,RX FIFO current entries number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TX_OVERRUN ,TX FIFO overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 2. " RX_OVERRUN ,RX FIFO overrun" "No overrun,Overrun"
|
|
textline " "
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 1. " UART_RX_IDLE ,RX path idle status" "Busy,Idle"
|
|
bitfld.long 0x00 0. " UART_TX_IDLE ,TX path idle status" "Busy,Idle"
|
|
endif
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "UART_ASR,UART Auto Sense Baud Register"
|
|
bitfld.long 0x00 31. " VALID ,Counting the clocks between two successive clock edges finished" "Not finished,Finished"
|
|
bitfld.long 0x00 30. " BUSY ,ASR busy" "Idle,Busy"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RX_RATE_SENSE_H ,High count of clock edges between two successive clock edges"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_RATE_SENSE_L ,Low count of clock edges between two successive clock edges"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART-C"
|
|
base ad:0x70006200
|
|
width 15.
|
|
if (((per.l((ad:0x70006200+0x0C)))&0x80)==0x00)
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "RBR_A/THR_A,Receive/Transmit Holding Register"
|
|
in
|
|
textline " "
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IER_DLAB,Interrupt Enable Register"
|
|
bitfld.long 0x00 5. " IE_EORD ,Interrupt enable for end of received data" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IE_RX_TIMEOUT ,Interrupt enable for Rx FIFO timeout" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IE_MSI ,Interrupt enable for modem status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IE_RXS ,Interrupt enable for receiver line status interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE_THR ,Interrupt enable for transmitter holding register empty interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IE_RHR ,Interrupt enable for received data interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "IIR,Interrupt Enable And Divisor Latch MSByte Registers"
|
|
bitfld.long 0x00 6.--7. " EN_FIFO ,FIFO mode status" "Mode 16450,Mode 16550,?..."
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 1.--3. " IS_PRI ,Encoded interrupt ID" "Modem status,TX holding register empty,RX data available,Overrun/parity/framing error,Eord_timeout_intr,,Rx_timeout_intr,?..."
|
|
else
|
|
bitfld.long 0x00 1.--3. " IS_PRI ,Encoded interrupt ID" "Modem status,TX data available,RX data available,Overrun/parity/framing error,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " IS_STA ,Interrupt pending" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "THR_DLAB,UART Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLL_A ,Divisor latch LSB"
|
|
line.long 0x04 "IER_DLAB,Divisor Latch MSByte Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLM_A ,Divisor latch MSB"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "FCR,Interrupt Enable And Divisor Latch MSByte Registers"
|
|
bitfld.long 0x00 6.--7. " RX_TRIG ,RX trigger" "FIFO count > 1,FIFO count > 4,FIFO count > 8,FIFO count > 16"
|
|
bitfld.long 0x00 4.--5. " TX_TRIG ,TX trigger" "FIFO count > 16,FIFO count > 8,FIFO count > 4,FIFO count > 1"
|
|
bitfld.long 0x00 3. " DMA ,DMA mode change" "No effect,Change"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TX_CLR ,Clears the contents of the transmit FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 1. " RX_CLR ,Clears the contents of the receive FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 0. " FCR_EN_FIFO ,Enable the transmit and receive FIFO" "Disable,Enable"
|
|
endif
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "LCR,UART Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SET_B ,Set BREAK condition" "No break,Break"
|
|
bitfld.long 0x00 5. " SET_P ,Set parity to value in LCR" "No parity,Parity"
|
|
bitfld.long 0x00 4. " EVEN ,Even parity format" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PAR ,Parity sent" "No parity,Parity"
|
|
bitfld.long 0x00 2. " STOP ,Stop bits" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " WD_SIZE ,Word length" "5 bit,6 bit,7 bit,8 bit"
|
|
line.long 0x04 "MCR,UART Modem Control Register"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x04 10. " OLD_SIR_DECODE ,Diagnostics bit to use the required SIR decode path" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--9. " RI_POLARITY ,RI modem status interrupt trigger edge selection" "Rising,Falling,Both,?..."
|
|
bitfld.long 0x04 7. " DEL_QUAL_CTS_EN ,Diagnostics bit to use the old qualified CTS in TX state machine" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " RTS_EN ,RTS hardware flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CTS_EN ,CTS hardware flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LOOPBK ,Internal loop back enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RTS ,Force RTS" "Force hi,Force low"
|
|
textline " "
|
|
bitfld.long 0x04 0. " DTR ,Force DTR" "Force hi,Force low"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "LSR,UART Line Status Register"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 9. " RX_FIFO_EMPTY ,Receiver FIFO status" "Not empty,Empty"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " TX_FIFO_FULL ,Transmitter FIFO full status" "Not full,Full"
|
|
bitfld.long 0x00 7. " FIFOE ,Receive FIFO error" "No error,Error"
|
|
bitfld.long 0x00 6. " TMTY ,Transmit shift reg empty status" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " THRE ,Transmit holding register is empty" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " BRK ,BREAK condition detected on line" "No break,Break"
|
|
bitfld.long 0x00 3. " FERR ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 2. " PERR ,Parity error" "No error,Error"
|
|
bitfld.long 0x00 1. " OVRF ,Receiver overrun error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDR ,Receiver data ready" "No data in FIFO,Data in FIFO"
|
|
group.long 0x18++0x13
|
|
line.long 0x00 "MSR,UART Modem Status Register"
|
|
bitfld.long 0x00 7. " CD ,State of carrier detect pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RI ,State of ring indicator pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DSR ,State of data set ready pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CTS ,State of clear to send pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DCD ,Change (Delta) in CD state detected" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DRI ,Change (Delta) in RI state detected" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DDSR ,Change (Delta) in DSR state detected" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DCTS ,Change (Delta) in CTS state detected" "Disabled,Enabled"
|
|
line.long 0x04 "SPR,UART Scratch Pad Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SPR_A ,Scratch pad"
|
|
line.long 0x08 "IRDA_CSR,UART IrDA Pulse Coding CSR Register"
|
|
bitfld.long 0x08 7. " SIR_A ,Enable SIR coder" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " PWT_A ,Baud pulse" "3/16,4/16"
|
|
bitfld.long 0x08 3. " INVERT_RTS ,Inverts the normally inactive high nRTS pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " INVERT_CTS ,Inverts the normally inactive high nCTS pin" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " INVERT_TXD ,Inverts the normally inactive high TXD pin" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " INVERT_RXD ,Inverts the normally inactive high RXD pin" "Disabled,Enabled"
|
|
line.long 0x0C "RX_FIFO_CFG,UART RX FIFO Configuration Register"
|
|
bitfld.long 0x0C 7. " EN_RX_FIFO_TRIG ,Enable use of RX FIFO trigger count" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--5. " RX_FIFO_TRIG ,Set RX FIFO trigger level" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
line.long 0x10 "MIE,UART Modem Interrupt Enable Register"
|
|
bitfld.long 0x10 3. " DCD_INT_EN ,Interrupt enable for change in CD state detected" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DRI_INT_EN ,Interrupt enable for change in RI state detected" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DDSR_INT_EN ,Interrupt enable for change in DSR state detected" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DCTS_INT_EN ,Interrupt enable for change in CTS state detected" "Disabled,Enabled"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "VENDOR_STATUS,UART Controller Status Register"
|
|
bitfld.long 0x00 24.--29. " TX_FIFO_COUNTER ,TX FIFO current entries number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " RX_FIFO_COUNTER ,RX FIFO current entries number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TX_OVERRUN ,TX FIFO overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 2. " RX_OVERRUN ,RX FIFO overrun" "No overrun,Overrun"
|
|
textline " "
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 1. " UART_RX_IDLE ,RX path idle status" "Busy,Idle"
|
|
bitfld.long 0x00 0. " UART_TX_IDLE ,TX path idle status" "Busy,Idle"
|
|
endif
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "UART_ASR,UART Auto Sense Baud Register"
|
|
bitfld.long 0x00 31. " VALID ,Counting the clocks between two successive clock edges finished" "Not finished,Finished"
|
|
bitfld.long 0x00 30. " BUSY ,ASR busy" "Idle,Busy"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RX_RATE_SENSE_H ,High count of clock edges between two successive clock edges"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_RATE_SENSE_L ,Low count of clock edges between two successive clock edges"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART-D"
|
|
base ad:0x70006300
|
|
width 15.
|
|
if (((per.l((ad:0x70006300+0x0C)))&0x80)==0x00)
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "RBR_A/THR_A,Receive/Transmit Holding Register"
|
|
in
|
|
textline " "
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IER_DLAB,Interrupt Enable Register"
|
|
bitfld.long 0x00 5. " IE_EORD ,Interrupt enable for end of received data" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IE_RX_TIMEOUT ,Interrupt enable for Rx FIFO timeout" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IE_MSI ,Interrupt enable for modem status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IE_RXS ,Interrupt enable for receiver line status interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE_THR ,Interrupt enable for transmitter holding register empty interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IE_RHR ,Interrupt enable for received data interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "IIR,Interrupt Enable And Divisor Latch MSByte Registers"
|
|
bitfld.long 0x00 6.--7. " EN_FIFO ,FIFO mode status" "Mode 16450,Mode 16550,?..."
|
|
textline " "
|
|
sif (cpuis("TEGRAX2"))
|
|
bitfld.long 0x00 1.--3. " IS_PRI ,Encoded interrupt ID" "Modem status,TX holding register empty,RX data available,Overrun/parity/framing error,Eord_timeout_intr,,Rx_timeout_intr,?..."
|
|
else
|
|
bitfld.long 0x00 1.--3. " IS_PRI ,Encoded interrupt ID" "Modem status,TX data available,RX data available,Overrun/parity/framing error,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " IS_STA ,Interrupt pending" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "THR_DLAB,UART Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLL_A ,Divisor latch LSB"
|
|
line.long 0x04 "IER_DLAB,Divisor Latch MSByte Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLM_A ,Divisor latch MSB"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "FCR,Interrupt Enable And Divisor Latch MSByte Registers"
|
|
bitfld.long 0x00 6.--7. " RX_TRIG ,RX trigger" "FIFO count > 1,FIFO count > 4,FIFO count > 8,FIFO count > 16"
|
|
bitfld.long 0x00 4.--5. " TX_TRIG ,TX trigger" "FIFO count > 16,FIFO count > 8,FIFO count > 4,FIFO count > 1"
|
|
bitfld.long 0x00 3. " DMA ,DMA mode change" "No effect,Change"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TX_CLR ,Clears the contents of the transmit FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 1. " RX_CLR ,Clears the contents of the receive FIFO" "No effect,Clear"
|
|
bitfld.long 0x00 0. " FCR_EN_FIFO ,Enable the transmit and receive FIFO" "Disable,Enable"
|
|
endif
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "LCR,UART Line Control Register"
|
|
bitfld.long 0x00 7. " DLAB ,Divisor latch access bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SET_B ,Set BREAK condition" "No break,Break"
|
|
bitfld.long 0x00 5. " SET_P ,Set parity to value in LCR" "No parity,Parity"
|
|
bitfld.long 0x00 4. " EVEN ,Even parity format" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PAR ,Parity sent" "No parity,Parity"
|
|
bitfld.long 0x00 2. " STOP ,Stop bits" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " WD_SIZE ,Word length" "5 bit,6 bit,7 bit,8 bit"
|
|
line.long 0x04 "MCR,UART Modem Control Register"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x04 10. " OLD_SIR_DECODE ,Diagnostics bit to use the required SIR decode path" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--9. " RI_POLARITY ,RI modem status interrupt trigger edge selection" "Rising,Falling,Both,?..."
|
|
bitfld.long 0x04 7. " DEL_QUAL_CTS_EN ,Diagnostics bit to use the old qualified CTS in TX state machine" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " RTS_EN ,RTS hardware flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " CTS_EN ,CTS hardware flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LOOPBK ,Internal loop back enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RTS ,Force RTS" "Force hi,Force low"
|
|
textline " "
|
|
bitfld.long 0x04 0. " DTR ,Force DTR" "Force hi,Force low"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "LSR,UART Line Status Register"
|
|
sif cpuis("TEGRAX1")||cpuis("TEGRAX2")
|
|
bitfld.long 0x00 9. " RX_FIFO_EMPTY ,Receiver FIFO status" "Not empty,Empty"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " TX_FIFO_FULL ,Transmitter FIFO full status" "Not full,Full"
|
|
bitfld.long 0x00 7. " FIFOE ,Receive FIFO error" "No error,Error"
|
|
bitfld.long 0x00 6. " TMTY ,Transmit shift reg empty status" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " THRE ,Transmit holding register is empty" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " BRK ,BREAK condition detected on line" "No break,Break"
|
|
bitfld.long 0x00 3. " FERR ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 2. " PERR ,Parity error" "No error,Error"
|
|
bitfld.long 0x00 1. " OVRF ,Receiver overrun error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDR ,Receiver data ready" "No data in FIFO,Data in FIFO"
|
|
group.long 0x18++0x13
|
|
line.long 0x00 "MSR,UART Modem Status Register"
|
|
bitfld.long 0x00 7. " CD ,State of carrier detect pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RI ,State of ring indicator pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DSR ,State of data set ready pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CTS ,State of clear to send pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DCD ,Change (Delta) in CD state detected" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DRI ,Change (Delta) in RI state detected" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DDSR ,Change (Delta) in DSR state detected" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DCTS ,Change (Delta) in CTS state detected" "Disabled,Enabled"
|
|
line.long 0x04 "SPR,UART Scratch Pad Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SPR_A ,Scratch pad"
|
|
line.long 0x08 "IRDA_CSR,UART IrDA Pulse Coding CSR Register"
|
|
bitfld.long 0x08 7. " SIR_A ,Enable SIR coder" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " PWT_A ,Baud pulse" "3/16,4/16"
|
|
bitfld.long 0x08 3. " INVERT_RTS ,Inverts the normally inactive high nRTS pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " INVERT_CTS ,Inverts the normally inactive high nCTS pin" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " INVERT_TXD ,Inverts the normally inactive high TXD pin" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " INVERT_RXD ,Inverts the normally inactive high RXD pin" "Disabled,Enabled"
|
|
line.long 0x0C "RX_FIFO_CFG,UART RX FIFO Configuration Register"
|
|
bitfld.long 0x0C 7. " EN_RX_FIFO_TRIG ,Enable use of RX FIFO trigger count" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--5. " RX_FIFO_TRIG ,Set RX FIFO trigger level" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
line.long 0x10 "MIE,UART Modem Interrupt Enable Register"
|
|
bitfld.long 0x10 3. " DCD_INT_EN ,Interrupt enable for change in CD state detected" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DRI_INT_EN ,Interrupt enable for change in RI state detected" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DDSR_INT_EN ,Interrupt enable for change in DSR state detected" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DCTS_INT_EN ,Interrupt enable for change in CTS state detected" "Disabled,Enabled"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "VENDOR_STATUS,UART Controller Status Register"
|
|
bitfld.long 0x00 24.--29. " TX_FIFO_COUNTER ,TX FIFO current entries number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " RX_FIFO_COUNTER ,RX FIFO current entries number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TX_OVERRUN ,TX FIFO overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 2. " RX_OVERRUN ,RX FIFO overrun" "No overrun,Overrun"
|
|
textline " "
|
|
sif cpuis("TEGRAX1")
|
|
bitfld.long 0x00 1. " UART_RX_IDLE ,RX path idle status" "Busy,Idle"
|
|
bitfld.long 0x00 0. " UART_TX_IDLE ,TX path idle status" "Busy,Idle"
|
|
endif
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "UART_ASR,UART Auto Sense Baud Register"
|
|
bitfld.long 0x00 31. " VALID ,Counting the clocks between two successive clock edges finished" "Not finished,Finished"
|
|
bitfld.long 0x00 30. " BUSY ,ASR busy" "Idle,Busy"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RX_RATE_SENSE_H ,High count of clock edges between two successive clock edges"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RX_RATE_SENSE_L ,Low count of clock edges between two successive clock edges"
|
|
width 0x0B
|
|
tree.end
|
|
tree "VFIR"
|
|
base ad:0x70006100
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL_0,VFIR Control Register"
|
|
bitfld.long 0x00 31. " GLOBAL_ENABLE ,Entire IRDA module enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " GO ,Start transmit or receive operation" "Stop,Start"
|
|
bitfld.long 0x00 29. " AUTO_RESTART ,Restart another operation" "Stop,Restart"
|
|
bitfld.long 0x00 24. " FORCE_BAD_CRC ,Debugging bit to force a CRC error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TX_FIFO_CLR ,Clear the Transmitter FIFO" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " TX_ATN_LVL ,TX_ATN_LVL" "Not full,Slots_empty_4,Slots_empty_8,Slots_empty_12"
|
|
bitfld.long 0x00 18. " RX_FIFO_CLR ,Clear the Receiver FIFO" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " RX_ATN_LVL ,RX_ATN_LVL" "Not_empty,Slots_full_4,Slots_full_8,Slots_full_12"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START_SIP ,Self-clearing bit to initiate a Serial Ir Interaction Pulse" "0,1"
|
|
bitfld.long 0x00 12. " EN_PULSECORR ,Fixes single pulse errors caused by VFIR propagation effects" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DMA_EN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TX_TERM ,TX_TERM of outgoing frame" "Abort,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 9. " COUNT_ODATA ,End frame when the (OFDL) count is reached" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " FORCEBRK ,Break state (zero)" "TX enable,TX disable"
|
|
bitfld.long 0x00 7. " NEGATE_RX ,Invert polarity on incoming RX pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " NEGATE_TX ,Invert polarity on outgoing TX pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FREQUENCY ,Clock frequency" "8MHz,24MHz,48MHz,72MHz"
|
|
bitfld.long 0x00 3. " TRANSMIT ,Transfer direction" "Receive,Transmit"
|
|
bitfld.long 0x00 0.--2. " MODE ,Mode" "UART B,SIR,MIR,@,FIR,VFIR,@,@"
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "STS_0,VFIR Status and Interrupt Identification Register"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "IER_0,VFIR Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " IE_TX_FTRIG ,Enable Interrupt on Transmitter FIFO Trigger level reached" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " IE_RX_FTRIG ,Enable Interrupt on Receiver FIFO Trigger level reached" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " IE_TX_UNDRN ,Transmit a break for the receiving side to abort reception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " IE_MISSED_PACKET ,Enable Interrupt for Missed Packet error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " IE_RX_DETECT ,Enable Interrupt on Activity on Rx Pin" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IE_RX_ERR ,Enable Interrupt on Receiver Error" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IE_RX_FOVRN ,Enable Interrupt on Receiver FIFO overrun" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IE_RX_CRC ,Enable Interrupt for input CRC check failure" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IE_RX_EOF ,Enable Interrupt for Received End of Frame" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IE_DONE ,Enable Interrupt for Done Status" "Disabled,Enabled"
|
|
line.long 0x04 "OFDL_0,VFIR Outgoing Frame Data Length"
|
|
hexmask.long.word 0x04 0.--15. 1. " OFDL ,Length in bytes of the outgoing frame"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IFDL_0,VFIR Incoming Frame Data Length"
|
|
hexmask.long.word 0x00 0.--15. 1. " IFDL ,Length in bytes of the incoming data stream"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FIFO_0,VFIR FIFO"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SPI Controller"
|
|
tree "2B-1"
|
|
base ad:0x7000D400
|
|
width 11.
|
|
if (((d.l(ad:0x7000D400))&0x4000001F)==(0x40000003||0x40000007||0x4000000F||0x4000001F))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CS_SEL ,Select a slave in the multi-slave environment" "CS0,CS1,CS2,CS3"
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" "Drive Low,Drive High,,"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Transmission/Receipt Byte on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PACKED ,Packed mode enable bit" "Unpacked Mode,Packed Mode"
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
elif (((d.l(ad:0x7000D400))&0x4000001F)==(0x3||0x7||0xF||0x1F))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" ",,External Pull Down,External Pull High"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Byte Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PACKED ,Packed mode enable bit" "Unpacked Mode,Packed Mode"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,,,,,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
elif (((d.l(ad:0x7000D400))&0x4000001F)!=(0x40000003||0x40000007||0x4000000F||0x4000001F))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" ",,External Pull Down,External Pull High"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Byte Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,,,,,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CS_SEL ,Select a slave in the multi-slave environment" "CS0,CS1,CS2,CS3"
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" "Drive Low,Drive High,,"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Byte Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
endif
|
|
if (((d.l(ad:0x7000D400))&0x40000000)==0x40000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "COMMAND2,SPI Command2 Register"
|
|
bitfld.long 0x00 6.--11. " Tx_Clk_TAP_DELAY ,Delays the clock going out to the external device" "No delay,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " Rx_Clk_TAP_DELAY ,Delays the clock coming in from the external device" "No delay,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "COMMAND2,SPI Command2 Register (Useful only in Master Mode)"
|
|
endif
|
|
width 14.
|
|
textline " "
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CS_TIM1,CS Timing1 Register"
|
|
bitfld.long 0x00 28.--31. " CS_SETUP_TIME3 ,Specifies the setup time of the chip select CS3" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 24.--27. " CS_HOLD_TIME3 ,Specifies the hold time of the chip select CS3" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 20.--23. " CS_SETUP_TIME2 ,Specifies the setup time of the chip select CS2" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CS_HOLD_TIME2 ,Specifies the hold time of the chip select CS2" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 12.--15. " CS_SETUP_TIME1 ,Specifies the setup time of the chip select CS1" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 8.--11. " CS_HOLD_TIME1 ,Specifies the hold time of the chip select CS1" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CS_SETUP_TIME0 ,Specifies the setup time of the chip select CS0" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 0.--3. " CS_HOLD_TIME0 ,Specifies the hold time of the chip select CS0" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
if (((d.l(ad:0x7000D400+0x20))&0x80000000)==0x00)&&(((d.l(ad:0x7000D400))&0x80000000)==0x00)
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "CS_TIM2,CS Timing2 Register"
|
|
bitfld.long 0x00 29. " CS_ACTIVE_BETWEEN_PACKETS3 ,Specifies if CS stays active between two packets on CS3" "Inactive,Active"
|
|
bitfld.long 0x00 21. " CS_ACTIVE_BETWEEN_PACKETS2 ,Specifies if CS stays active between two packets on CS2" "Inactive,Active"
|
|
bitfld.long 0x00 13. " CS_ACTIVE_BETWEEN_PACKETS1 ,Specifies if CS stays active between two packets on CS1" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CS_ACTIVE_BETWEEN_PACKETS0 ,Specifies if CS stays active between two packets on CS0" "Inactive,Active"
|
|
line.long 0x04 "TRANS_STATUS,TRANSFER Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SLV_IDLE_COUNT ,Slave Continuous Mode"
|
|
else
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "CS_TIM2,CS Timing2 Register"
|
|
bitfld.long 0x00 29. " CS_ACTIVE_BETWEEN_PACKETS3 ,Specifies if CS stays active between two packets on CS3" "Inactive,Active"
|
|
bitfld.long 0x00 24.--28. " CYCLES_BETWEEN_PACKETS3 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21. " CS_ACTIVE_BETWEEN_PACKETS2 ,Specifies if CS stays active between two packets on CS2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " CYCLES_BETWEEN_PACKETS2 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13. " CS_ACTIVE_BETWEEN_PACKETS1 ,Specifies if CS stays active between two packets on CS1" "Inactive,Active"
|
|
bitfld.long 0x00 8.--12. " CYCLES_BETWEEN_PACKETS1 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CS_ACTIVE_BETWEEN_PACKETS0 ,Specifies if CS stays active between two packets on CS0" "Inactive,Active"
|
|
bitfld.long 0x00 0.--4. " CYCLES_BETWEEN_PACKETS0 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "TRANS_STATUS,TRANSFER Status Register"
|
|
eventfld.long 0x04 30. " RDY ,Ready bit" "Not ready,Ready"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SLV_IDLE_COUNT ,Slave Continuous Mode"
|
|
hexmask.long.word 0x04 0.--15. 1. " BLOCK_COUNT ,Counts the number of packets in a transaction"
|
|
endif
|
|
textline " "
|
|
if (((d.l(ad:0x7000D400))&0x40000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FIFO_STATUS,Control/Status FIFO Status Register"
|
|
bitfld.long 0x00 31. " CS_INACTIVE ,CS deasserted error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 30. " FRAME_END ,Continuous mode is terminated" "No,Yes"
|
|
hexmask.long.byte 0x00 23.--29. 1. " RX_FIFO_FULL_COUNT ,Indicates the number of slots in the receive FIFO"
|
|
hexmask.long.byte 0x00 16.--22. 1. " TX_FIFO_EMPTY_COUNT ,Indicates the number of slots in the transmit FIFO"
|
|
bitfld.long 0x00 15. " RX_FIFO_FLUSH ,Flush Rx FIFO" "NOP,FLUSH"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TX_FIFO_FLUSH ,Flush Tx FIFO" "NOP,FLUSH"
|
|
eventfld.long 0x00 8. " ERR ,Error flag" "No error,Error"
|
|
eventfld.long 0x00 7. " TX_FIFO_OVF ,TX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 6. " TX_FIFO_UNR ,TX FIFO Underrun" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " RX_FIFO_OVF ,RX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 4. " RX_FIFO_UNR ,RX FIFO Underrun" "No error,Error"
|
|
bitfld.long 0x00 3. " TX_FIFO_FULL ,TX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 2. " TX_FIFO_EMPTY ,TX FIFO Empty Status" "No empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_FIFO_FULL ,RX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 0. " RX_FIFO_EMPTY ,RX FIFO Empty Status" "No empty,Empty"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FIFO_STATUS,Control/Status FIFO Status Register"
|
|
textline " "
|
|
bitfld.long 0x00 30. " FRAME_END ,Continuous mode is terminated" "No,Yes"
|
|
hexmask.long.byte 0x00 23.--29. 1. " RX_FIFO_FULL_COUNT ,Number of slots in the receive FIFO"
|
|
hexmask.long.byte 0x00 16.--22. 1. " TX_FIFO_EMPTY_COUNT ,Number of slots in the transmit FIFO"
|
|
bitfld.long 0x00 15. " RX_FIFO_FLUSH ,Flush Rx FIFO" "NOP,FLUSH"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TX_FIFO_FLUSH ,Flush Tx FIFO" "NOP,FLUSH"
|
|
eventfld.long 0x00 8. " ERR ,Error flag" "No error,Error"
|
|
eventfld.long 0x00 7. " TX_FIFO_OVF ,TX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 6. " TX_FIFO_UNR ,TX FIFO Underrun" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " RX_FIFO_OVF ,RX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 4. " RX_FIFO_UNR ,RX FIFO Underrun" "No error,Error"
|
|
bitfld.long 0x00 3. " TX_FIFO_FULL ,TX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 2. " TX_FIFO_EMPTY ,TX FIFO Empty Status" "No empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_FIFO_FULL ,RX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 0. " RX_FIFO_EMPTY ,RX FIFO Empty Status" "No empty,Empty"
|
|
endif
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "TX_DATA,Transmit Data Register"
|
|
line.long 0x04 "RX_DATA,Receive Data Register"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DMA_CTL,DMA Control Register"
|
|
bitfld.long 0x00 31. " DMA ,Enable DMA Mode transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CONT ,Enable Continuous Mode transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE.RX ,Interrupt enable on receive completion" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " IE.TX ,Interrupt enable on transmit completion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " RX_TRIG ,Receive FIFO trigger level" "1 word,4 word,8 word,16 word"
|
|
bitfld.long 0x00 15.--16. " TX_TRIG ,Transmit FIFO trigger level" "1 word,4 word,8 word,16 word"
|
|
if (((d.l(ad:0x7000D400+0x20))&0x80000000)==0x00)&&(((d.l(ad:0x7000D400))&0x80000000)==0x00)
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "DMA_BLK,Block Size Register (Useful only in PIO or DMA mode)"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA_BLK,Block Size Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BLOCK_SIZE ,Size of data block to be transferred"
|
|
endif
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "FIFO1,TX FIFO Register"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "FIFO2,RX FIFO Register"
|
|
if (((d.l(ad:0x7000D400))&0x40000000)==0x40000000)
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "SPARE_CTLR,Spare Control Register"
|
|
bitfld.long 0x00 8.--10. " SPARE_CONTROL_REGISTER_BYTE2 ,Adjust the clock delay on internal registers" "0,1,2,3,4,5,6,7"
|
|
else
|
|
hgroup.long 0x18C++0x03
|
|
hide.long 0x00 "SPARE_CTLR,Spare Control Register (Useful only in Master Mode)"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "2B-2"
|
|
base ad:0x7000D600
|
|
width 11.
|
|
if (((d.l(ad:0x7000D600))&0x4000001F)==(0x40000003||0x40000007||0x4000000F||0x4000001F))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CS_SEL ,Select a slave in the multi-slave environment" "CS0,CS1,CS2,CS3"
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" "Drive Low,Drive High,,"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Transmission/Receipt Byte on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PACKED ,Packed mode enable bit" "Unpacked Mode,Packed Mode"
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
elif (((d.l(ad:0x7000D600))&0x4000001F)==(0x3||0x7||0xF||0x1F))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" ",,External Pull Down,External Pull High"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Byte Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PACKED ,Packed mode enable bit" "Unpacked Mode,Packed Mode"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,,,,,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
elif (((d.l(ad:0x7000D600))&0x4000001F)!=(0x40000003||0x40000007||0x4000000F||0x4000001F))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" ",,External Pull Down,External Pull High"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Byte Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,,,,,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CS_SEL ,Select a slave in the multi-slave environment" "CS0,CS1,CS2,CS3"
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" "Drive Low,Drive High,,"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Byte Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
endif
|
|
if (((d.l(ad:0x7000D600))&0x40000000)==0x40000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "COMMAND2,SPI Command2 Register"
|
|
bitfld.long 0x00 6.--11. " Tx_Clk_TAP_DELAY ,Delays the clock going out to the external device" "No delay,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " Rx_Clk_TAP_DELAY ,Delays the clock coming in from the external device" "No delay,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "COMMAND2,SPI Command2 Register (Useful only in Master Mode)"
|
|
endif
|
|
width 14.
|
|
textline " "
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CS_TIM1,CS Timing1 Register"
|
|
bitfld.long 0x00 28.--31. " CS_SETUP_TIME3 ,Specifies the setup time of the chip select CS3" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 24.--27. " CS_HOLD_TIME3 ,Specifies the hold time of the chip select CS3" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 20.--23. " CS_SETUP_TIME2 ,Specifies the setup time of the chip select CS2" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CS_HOLD_TIME2 ,Specifies the hold time of the chip select CS2" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 12.--15. " CS_SETUP_TIME1 ,Specifies the setup time of the chip select CS1" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 8.--11. " CS_HOLD_TIME1 ,Specifies the hold time of the chip select CS1" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CS_SETUP_TIME0 ,Specifies the setup time of the chip select CS0" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 0.--3. " CS_HOLD_TIME0 ,Specifies the hold time of the chip select CS0" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
if (((d.l(ad:0x7000D600+0x20))&0x80000000)==0x00)&&(((d.l(ad:0x7000D600))&0x80000000)==0x00)
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "CS_TIM2,CS Timing2 Register"
|
|
bitfld.long 0x00 29. " CS_ACTIVE_BETWEEN_PACKETS3 ,Specifies if CS stays active between two packets on CS3" "Inactive,Active"
|
|
bitfld.long 0x00 21. " CS_ACTIVE_BETWEEN_PACKETS2 ,Specifies if CS stays active between two packets on CS2" "Inactive,Active"
|
|
bitfld.long 0x00 13. " CS_ACTIVE_BETWEEN_PACKETS1 ,Specifies if CS stays active between two packets on CS1" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CS_ACTIVE_BETWEEN_PACKETS0 ,Specifies if CS stays active between two packets on CS0" "Inactive,Active"
|
|
line.long 0x04 "TRANS_STATUS,TRANSFER Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SLV_IDLE_COUNT ,Slave Continuous Mode"
|
|
else
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "CS_TIM2,CS Timing2 Register"
|
|
bitfld.long 0x00 29. " CS_ACTIVE_BETWEEN_PACKETS3 ,Specifies if CS stays active between two packets on CS3" "Inactive,Active"
|
|
bitfld.long 0x00 24.--28. " CYCLES_BETWEEN_PACKETS3 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21. " CS_ACTIVE_BETWEEN_PACKETS2 ,Specifies if CS stays active between two packets on CS2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " CYCLES_BETWEEN_PACKETS2 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13. " CS_ACTIVE_BETWEEN_PACKETS1 ,Specifies if CS stays active between two packets on CS1" "Inactive,Active"
|
|
bitfld.long 0x00 8.--12. " CYCLES_BETWEEN_PACKETS1 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CS_ACTIVE_BETWEEN_PACKETS0 ,Specifies if CS stays active between two packets on CS0" "Inactive,Active"
|
|
bitfld.long 0x00 0.--4. " CYCLES_BETWEEN_PACKETS0 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "TRANS_STATUS,TRANSFER Status Register"
|
|
eventfld.long 0x04 30. " RDY ,Ready bit" "Not ready,Ready"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SLV_IDLE_COUNT ,Slave Continuous Mode"
|
|
hexmask.long.word 0x04 0.--15. 1. " BLOCK_COUNT ,Counts the number of packets in a transaction"
|
|
endif
|
|
textline " "
|
|
if (((d.l(ad:0x7000D600))&0x40000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FIFO_STATUS,Control/Status FIFO Status Register"
|
|
bitfld.long 0x00 31. " CS_INACTIVE ,CS deasserted error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 30. " FRAME_END ,Continuous mode is terminated" "No,Yes"
|
|
hexmask.long.byte 0x00 23.--29. 1. " RX_FIFO_FULL_COUNT ,Indicates the number of slots in the receive FIFO"
|
|
hexmask.long.byte 0x00 16.--22. 1. " TX_FIFO_EMPTY_COUNT ,Indicates the number of slots in the transmit FIFO"
|
|
bitfld.long 0x00 15. " RX_FIFO_FLUSH ,Flush Rx FIFO" "NOP,FLUSH"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TX_FIFO_FLUSH ,Flush Tx FIFO" "NOP,FLUSH"
|
|
eventfld.long 0x00 8. " ERR ,Error flag" "No error,Error"
|
|
eventfld.long 0x00 7. " TX_FIFO_OVF ,TX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 6. " TX_FIFO_UNR ,TX FIFO Underrun" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " RX_FIFO_OVF ,RX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 4. " RX_FIFO_UNR ,RX FIFO Underrun" "No error,Error"
|
|
bitfld.long 0x00 3. " TX_FIFO_FULL ,TX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 2. " TX_FIFO_EMPTY ,TX FIFO Empty Status" "No empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_FIFO_FULL ,RX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 0. " RX_FIFO_EMPTY ,RX FIFO Empty Status" "No empty,Empty"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FIFO_STATUS,Control/Status FIFO Status Register"
|
|
textline " "
|
|
bitfld.long 0x00 30. " FRAME_END ,Continuous mode is terminated" "No,Yes"
|
|
hexmask.long.byte 0x00 23.--29. 1. " RX_FIFO_FULL_COUNT ,Number of slots in the receive FIFO"
|
|
hexmask.long.byte 0x00 16.--22. 1. " TX_FIFO_EMPTY_COUNT ,Number of slots in the transmit FIFO"
|
|
bitfld.long 0x00 15. " RX_FIFO_FLUSH ,Flush Rx FIFO" "NOP,FLUSH"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TX_FIFO_FLUSH ,Flush Tx FIFO" "NOP,FLUSH"
|
|
eventfld.long 0x00 8. " ERR ,Error flag" "No error,Error"
|
|
eventfld.long 0x00 7. " TX_FIFO_OVF ,TX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 6. " TX_FIFO_UNR ,TX FIFO Underrun" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " RX_FIFO_OVF ,RX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 4. " RX_FIFO_UNR ,RX FIFO Underrun" "No error,Error"
|
|
bitfld.long 0x00 3. " TX_FIFO_FULL ,TX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 2. " TX_FIFO_EMPTY ,TX FIFO Empty Status" "No empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_FIFO_FULL ,RX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 0. " RX_FIFO_EMPTY ,RX FIFO Empty Status" "No empty,Empty"
|
|
endif
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "TX_DATA,Transmit Data Register"
|
|
line.long 0x04 "RX_DATA,Receive Data Register"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DMA_CTL,DMA Control Register"
|
|
bitfld.long 0x00 31. " DMA ,Enable DMA Mode transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CONT ,Enable Continuous Mode transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE.RX ,Interrupt enable on receive completion" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " IE.TX ,Interrupt enable on transmit completion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " RX_TRIG ,Receive FIFO trigger level" "1 word,4 word,8 word,16 word"
|
|
bitfld.long 0x00 15.--16. " TX_TRIG ,Transmit FIFO trigger level" "1 word,4 word,8 word,16 word"
|
|
if (((d.l(ad:0x7000D600+0x20))&0x80000000)==0x00)&&(((d.l(ad:0x7000D600))&0x80000000)==0x00)
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "DMA_BLK,Block Size Register (Useful only in PIO or DMA mode)"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA_BLK,Block Size Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BLOCK_SIZE ,Size of data block to be transferred"
|
|
endif
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "FIFO1,TX FIFO Register"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "FIFO2,RX FIFO Register"
|
|
if (((d.l(ad:0x7000D600))&0x40000000)==0x40000000)
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "SPARE_CTLR,Spare Control Register"
|
|
bitfld.long 0x00 8.--10. " SPARE_CONTROL_REGISTER_BYTE2 ,Adjust the clock delay on internal registers" "0,1,2,3,4,5,6,7"
|
|
else
|
|
hgroup.long 0x18C++0x03
|
|
hide.long 0x00 "SPARE_CTLR,Spare Control Register (Useful only in Master Mode)"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "2B-3"
|
|
base ad:0x7000D800
|
|
width 11.
|
|
if (((d.l(ad:0x7000D800))&0x4000001F)==(0x40000003||0x40000007||0x4000000F||0x4000001F))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CS_SEL ,Select a slave in the multi-slave environment" "CS0,CS1,CS2,CS3"
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" "Drive Low,Drive High,,"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Transmission/Receipt Byte on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PACKED ,Packed mode enable bit" "Unpacked Mode,Packed Mode"
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
elif (((d.l(ad:0x7000D800))&0x4000001F)==(0x3||0x7||0xF||0x1F))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" ",,External Pull Down,External Pull High"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Byte Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PACKED ,Packed mode enable bit" "Unpacked Mode,Packed Mode"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,,,,,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
elif (((d.l(ad:0x7000D800))&0x4000001F)!=(0x40000003||0x40000007||0x4000000F||0x4000001F))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" ",,External Pull Down,External Pull High"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Byte Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,,,,,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CS_SEL ,Select a slave in the multi-slave environment" "CS0,CS1,CS2,CS3"
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" "Drive Low,Drive High,,"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Byte Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
endif
|
|
if (((d.l(ad:0x7000D800))&0x40000000)==0x40000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "COMMAND2,SPI Command2 Register"
|
|
bitfld.long 0x00 6.--11. " Tx_Clk_TAP_DELAY ,Delays the clock going out to the external device" "No delay,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " Rx_Clk_TAP_DELAY ,Delays the clock coming in from the external device" "No delay,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "COMMAND2,SPI Command2 Register (Useful only in Master Mode)"
|
|
endif
|
|
width 14.
|
|
textline " "
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CS_TIM1,CS Timing1 Register"
|
|
bitfld.long 0x00 28.--31. " CS_SETUP_TIME3 ,Specifies the setup time of the chip select CS3" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 24.--27. " CS_HOLD_TIME3 ,Specifies the hold time of the chip select CS3" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 20.--23. " CS_SETUP_TIME2 ,Specifies the setup time of the chip select CS2" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CS_HOLD_TIME2 ,Specifies the hold time of the chip select CS2" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 12.--15. " CS_SETUP_TIME1 ,Specifies the setup time of the chip select CS1" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 8.--11. " CS_HOLD_TIME1 ,Specifies the hold time of the chip select CS1" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CS_SETUP_TIME0 ,Specifies the setup time of the chip select CS0" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 0.--3. " CS_HOLD_TIME0 ,Specifies the hold time of the chip select CS0" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
if (((d.l(ad:0x7000D800+0x20))&0x80000000)==0x00)&&(((d.l(ad:0x7000D800))&0x80000000)==0x00)
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "CS_TIM2,CS Timing2 Register"
|
|
bitfld.long 0x00 29. " CS_ACTIVE_BETWEEN_PACKETS3 ,Specifies if CS stays active between two packets on CS3" "Inactive,Active"
|
|
bitfld.long 0x00 21. " CS_ACTIVE_BETWEEN_PACKETS2 ,Specifies if CS stays active between two packets on CS2" "Inactive,Active"
|
|
bitfld.long 0x00 13. " CS_ACTIVE_BETWEEN_PACKETS1 ,Specifies if CS stays active between two packets on CS1" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CS_ACTIVE_BETWEEN_PACKETS0 ,Specifies if CS stays active between two packets on CS0" "Inactive,Active"
|
|
line.long 0x04 "TRANS_STATUS,TRANSFER Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SLV_IDLE_COUNT ,Slave Continuous Mode"
|
|
else
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "CS_TIM2,CS Timing2 Register"
|
|
bitfld.long 0x00 29. " CS_ACTIVE_BETWEEN_PACKETS3 ,Specifies if CS stays active between two packets on CS3" "Inactive,Active"
|
|
bitfld.long 0x00 24.--28. " CYCLES_BETWEEN_PACKETS3 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21. " CS_ACTIVE_BETWEEN_PACKETS2 ,Specifies if CS stays active between two packets on CS2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " CYCLES_BETWEEN_PACKETS2 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13. " CS_ACTIVE_BETWEEN_PACKETS1 ,Specifies if CS stays active between two packets on CS1" "Inactive,Active"
|
|
bitfld.long 0x00 8.--12. " CYCLES_BETWEEN_PACKETS1 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CS_ACTIVE_BETWEEN_PACKETS0 ,Specifies if CS stays active between two packets on CS0" "Inactive,Active"
|
|
bitfld.long 0x00 0.--4. " CYCLES_BETWEEN_PACKETS0 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "TRANS_STATUS,TRANSFER Status Register"
|
|
eventfld.long 0x04 30. " RDY ,Ready bit" "Not ready,Ready"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SLV_IDLE_COUNT ,Slave Continuous Mode"
|
|
hexmask.long.word 0x04 0.--15. 1. " BLOCK_COUNT ,Counts the number of packets in a transaction"
|
|
endif
|
|
textline " "
|
|
if (((d.l(ad:0x7000D800))&0x40000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FIFO_STATUS,Control/Status FIFO Status Register"
|
|
bitfld.long 0x00 31. " CS_INACTIVE ,CS deasserted error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 30. " FRAME_END ,Continuous mode is terminated" "No,Yes"
|
|
hexmask.long.byte 0x00 23.--29. 1. " RX_FIFO_FULL_COUNT ,Indicates the number of slots in the receive FIFO"
|
|
hexmask.long.byte 0x00 16.--22. 1. " TX_FIFO_EMPTY_COUNT ,Indicates the number of slots in the transmit FIFO"
|
|
bitfld.long 0x00 15. " RX_FIFO_FLUSH ,Flush Rx FIFO" "NOP,FLUSH"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TX_FIFO_FLUSH ,Flush Tx FIFO" "NOP,FLUSH"
|
|
eventfld.long 0x00 8. " ERR ,Error flag" "No error,Error"
|
|
eventfld.long 0x00 7. " TX_FIFO_OVF ,TX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 6. " TX_FIFO_UNR ,TX FIFO Underrun" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " RX_FIFO_OVF ,RX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 4. " RX_FIFO_UNR ,RX FIFO Underrun" "No error,Error"
|
|
bitfld.long 0x00 3. " TX_FIFO_FULL ,TX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 2. " TX_FIFO_EMPTY ,TX FIFO Empty Status" "No empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_FIFO_FULL ,RX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 0. " RX_FIFO_EMPTY ,RX FIFO Empty Status" "No empty,Empty"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FIFO_STATUS,Control/Status FIFO Status Register"
|
|
textline " "
|
|
bitfld.long 0x00 30. " FRAME_END ,Continuous mode is terminated" "No,Yes"
|
|
hexmask.long.byte 0x00 23.--29. 1. " RX_FIFO_FULL_COUNT ,Number of slots in the receive FIFO"
|
|
hexmask.long.byte 0x00 16.--22. 1. " TX_FIFO_EMPTY_COUNT ,Number of slots in the transmit FIFO"
|
|
bitfld.long 0x00 15. " RX_FIFO_FLUSH ,Flush Rx FIFO" "NOP,FLUSH"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TX_FIFO_FLUSH ,Flush Tx FIFO" "NOP,FLUSH"
|
|
eventfld.long 0x00 8. " ERR ,Error flag" "No error,Error"
|
|
eventfld.long 0x00 7. " TX_FIFO_OVF ,TX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 6. " TX_FIFO_UNR ,TX FIFO Underrun" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " RX_FIFO_OVF ,RX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 4. " RX_FIFO_UNR ,RX FIFO Underrun" "No error,Error"
|
|
bitfld.long 0x00 3. " TX_FIFO_FULL ,TX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 2. " TX_FIFO_EMPTY ,TX FIFO Empty Status" "No empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_FIFO_FULL ,RX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 0. " RX_FIFO_EMPTY ,RX FIFO Empty Status" "No empty,Empty"
|
|
endif
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "TX_DATA,Transmit Data Register"
|
|
line.long 0x04 "RX_DATA,Receive Data Register"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DMA_CTL,DMA Control Register"
|
|
bitfld.long 0x00 31. " DMA ,Enable DMA Mode transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CONT ,Enable Continuous Mode transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE.RX ,Interrupt enable on receive completion" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " IE.TX ,Interrupt enable on transmit completion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " RX_TRIG ,Receive FIFO trigger level" "1 word,4 word,8 word,16 word"
|
|
bitfld.long 0x00 15.--16. " TX_TRIG ,Transmit FIFO trigger level" "1 word,4 word,8 word,16 word"
|
|
if (((d.l(ad:0x7000D800+0x20))&0x80000000)==0x00)&&(((d.l(ad:0x7000D800))&0x80000000)==0x00)
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "DMA_BLK,Block Size Register (Useful only in PIO or DMA mode)"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA_BLK,Block Size Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BLOCK_SIZE ,Size of data block to be transferred"
|
|
endif
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "FIFO1,TX FIFO Register"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "FIFO2,RX FIFO Register"
|
|
if (((d.l(ad:0x7000D800))&0x40000000)==0x40000000)
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "SPARE_CTLR,Spare Control Register"
|
|
bitfld.long 0x00 8.--10. " SPARE_CONTROL_REGISTER_BYTE2 ,Adjust the clock delay on internal registers" "0,1,2,3,4,5,6,7"
|
|
else
|
|
hgroup.long 0x18C++0x03
|
|
hide.long 0x00 "SPARE_CTLR,Spare Control Register (Useful only in Master Mode)"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "2B-4"
|
|
base ad:0x7000DA00
|
|
width 11.
|
|
if (((d.l(ad:0x7000DA00))&0x4000001F)==(0x40000003||0x40000007||0x4000000F||0x4000001F))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CS_SEL ,Select a slave in the multi-slave environment" "CS0,CS1,CS2,CS3"
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" "Drive Low,Drive High,,"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Transmission/Receipt Byte on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PACKED ,Packed mode enable bit" "Unpacked Mode,Packed Mode"
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
elif (((d.l(ad:0x7000DA00))&0x4000001F)==(0x3||0x7||0xF||0x1F))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" ",,External Pull Down,External Pull High"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Byte Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PACKED ,Packed mode enable bit" "Unpacked Mode,Packed Mode"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,,,,,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
elif (((d.l(ad:0x7000DA00))&0x4000001F)!=(0x40000003||0x40000007||0x4000000F||0x4000001F))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" ",,External Pull Down,External Pull High"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Byte Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,,,,,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CS_SEL ,Select a slave in the multi-slave environment" "CS0,CS1,CS2,CS3"
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" "Drive Low,Drive High,,"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Byte Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
endif
|
|
if (((d.l(ad:0x7000DA00))&0x40000000)==0x40000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "COMMAND2,SPI Command2 Register"
|
|
bitfld.long 0x00 6.--11. " Tx_Clk_TAP_DELAY ,Delays the clock going out to the external device" "No delay,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " Rx_Clk_TAP_DELAY ,Delays the clock coming in from the external device" "No delay,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "COMMAND2,SPI Command2 Register (Useful only in Master Mode)"
|
|
endif
|
|
width 14.
|
|
textline " "
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CS_TIM1,CS Timing1 Register"
|
|
bitfld.long 0x00 28.--31. " CS_SETUP_TIME3 ,Specifies the setup time of the chip select CS3" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 24.--27. " CS_HOLD_TIME3 ,Specifies the hold time of the chip select CS3" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 20.--23. " CS_SETUP_TIME2 ,Specifies the setup time of the chip select CS2" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CS_HOLD_TIME2 ,Specifies the hold time of the chip select CS2" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 12.--15. " CS_SETUP_TIME1 ,Specifies the setup time of the chip select CS1" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 8.--11. " CS_HOLD_TIME1 ,Specifies the hold time of the chip select CS1" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CS_SETUP_TIME0 ,Specifies the setup time of the chip select CS0" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 0.--3. " CS_HOLD_TIME0 ,Specifies the hold time of the chip select CS0" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
if (((d.l(ad:0x7000DA00+0x20))&0x80000000)==0x00)&&(((d.l(ad:0x7000DA00))&0x80000000)==0x00)
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "CS_TIM2,CS Timing2 Register"
|
|
bitfld.long 0x00 29. " CS_ACTIVE_BETWEEN_PACKETS3 ,Specifies if CS stays active between two packets on CS3" "Inactive,Active"
|
|
bitfld.long 0x00 21. " CS_ACTIVE_BETWEEN_PACKETS2 ,Specifies if CS stays active between two packets on CS2" "Inactive,Active"
|
|
bitfld.long 0x00 13. " CS_ACTIVE_BETWEEN_PACKETS1 ,Specifies if CS stays active between two packets on CS1" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CS_ACTIVE_BETWEEN_PACKETS0 ,Specifies if CS stays active between two packets on CS0" "Inactive,Active"
|
|
line.long 0x04 "TRANS_STATUS,TRANSFER Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SLV_IDLE_COUNT ,Slave Continuous Mode"
|
|
else
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "CS_TIM2,CS Timing2 Register"
|
|
bitfld.long 0x00 29. " CS_ACTIVE_BETWEEN_PACKETS3 ,Specifies if CS stays active between two packets on CS3" "Inactive,Active"
|
|
bitfld.long 0x00 24.--28. " CYCLES_BETWEEN_PACKETS3 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21. " CS_ACTIVE_BETWEEN_PACKETS2 ,Specifies if CS stays active between two packets on CS2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " CYCLES_BETWEEN_PACKETS2 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13. " CS_ACTIVE_BETWEEN_PACKETS1 ,Specifies if CS stays active between two packets on CS1" "Inactive,Active"
|
|
bitfld.long 0x00 8.--12. " CYCLES_BETWEEN_PACKETS1 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CS_ACTIVE_BETWEEN_PACKETS0 ,Specifies if CS stays active between two packets on CS0" "Inactive,Active"
|
|
bitfld.long 0x00 0.--4. " CYCLES_BETWEEN_PACKETS0 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "TRANS_STATUS,TRANSFER Status Register"
|
|
eventfld.long 0x04 30. " RDY ,Ready bit" "Not ready,Ready"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SLV_IDLE_COUNT ,Slave Continuous Mode"
|
|
hexmask.long.word 0x04 0.--15. 1. " BLOCK_COUNT ,Counts the number of packets in a transaction"
|
|
endif
|
|
textline " "
|
|
if (((d.l(ad:0x7000DA00))&0x40000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FIFO_STATUS,Control/Status FIFO Status Register"
|
|
bitfld.long 0x00 31. " CS_INACTIVE ,CS deasserted error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 30. " FRAME_END ,Continuous mode is terminated" "No,Yes"
|
|
hexmask.long.byte 0x00 23.--29. 1. " RX_FIFO_FULL_COUNT ,Indicates the number of slots in the receive FIFO"
|
|
hexmask.long.byte 0x00 16.--22. 1. " TX_FIFO_EMPTY_COUNT ,Indicates the number of slots in the transmit FIFO"
|
|
bitfld.long 0x00 15. " RX_FIFO_FLUSH ,Flush Rx FIFO" "NOP,FLUSH"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TX_FIFO_FLUSH ,Flush Tx FIFO" "NOP,FLUSH"
|
|
eventfld.long 0x00 8. " ERR ,Error flag" "No error,Error"
|
|
eventfld.long 0x00 7. " TX_FIFO_OVF ,TX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 6. " TX_FIFO_UNR ,TX FIFO Underrun" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " RX_FIFO_OVF ,RX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 4. " RX_FIFO_UNR ,RX FIFO Underrun" "No error,Error"
|
|
bitfld.long 0x00 3. " TX_FIFO_FULL ,TX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 2. " TX_FIFO_EMPTY ,TX FIFO Empty Status" "No empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_FIFO_FULL ,RX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 0. " RX_FIFO_EMPTY ,RX FIFO Empty Status" "No empty,Empty"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FIFO_STATUS,Control/Status FIFO Status Register"
|
|
textline " "
|
|
bitfld.long 0x00 30. " FRAME_END ,Continuous mode is terminated" "No,Yes"
|
|
hexmask.long.byte 0x00 23.--29. 1. " RX_FIFO_FULL_COUNT ,Number of slots in the receive FIFO"
|
|
hexmask.long.byte 0x00 16.--22. 1. " TX_FIFO_EMPTY_COUNT ,Number of slots in the transmit FIFO"
|
|
bitfld.long 0x00 15. " RX_FIFO_FLUSH ,Flush Rx FIFO" "NOP,FLUSH"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TX_FIFO_FLUSH ,Flush Tx FIFO" "NOP,FLUSH"
|
|
eventfld.long 0x00 8. " ERR ,Error flag" "No error,Error"
|
|
eventfld.long 0x00 7. " TX_FIFO_OVF ,TX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 6. " TX_FIFO_UNR ,TX FIFO Underrun" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " RX_FIFO_OVF ,RX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 4. " RX_FIFO_UNR ,RX FIFO Underrun" "No error,Error"
|
|
bitfld.long 0x00 3. " TX_FIFO_FULL ,TX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 2. " TX_FIFO_EMPTY ,TX FIFO Empty Status" "No empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_FIFO_FULL ,RX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 0. " RX_FIFO_EMPTY ,RX FIFO Empty Status" "No empty,Empty"
|
|
endif
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "TX_DATA,Transmit Data Register"
|
|
line.long 0x04 "RX_DATA,Receive Data Register"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DMA_CTL,DMA Control Register"
|
|
bitfld.long 0x00 31. " DMA ,Enable DMA Mode transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CONT ,Enable Continuous Mode transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE.RX ,Interrupt enable on receive completion" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " IE.TX ,Interrupt enable on transmit completion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " RX_TRIG ,Receive FIFO trigger level" "1 word,4 word,8 word,16 word"
|
|
bitfld.long 0x00 15.--16. " TX_TRIG ,Transmit FIFO trigger level" "1 word,4 word,8 word,16 word"
|
|
if (((d.l(ad:0x7000DA00+0x20))&0x80000000)==0x00)&&(((d.l(ad:0x7000DA00))&0x80000000)==0x00)
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "DMA_BLK,Block Size Register (Useful only in PIO or DMA mode)"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA_BLK,Block Size Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BLOCK_SIZE ,Size of data block to be transferred"
|
|
endif
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "FIFO1,TX FIFO Register"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "FIFO2,RX FIFO Register"
|
|
if (((d.l(ad:0x7000DA00))&0x40000000)==0x40000000)
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "SPARE_CTLR,Spare Control Register"
|
|
bitfld.long 0x00 8.--10. " SPARE_CONTROL_REGISTER_BYTE2 ,Adjust the clock delay on internal registers" "0,1,2,3,4,5,6,7"
|
|
else
|
|
hgroup.long 0x18C++0x03
|
|
hide.long 0x00 "SPARE_CTLR,Spare Control Register (Useful only in Master Mode)"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "2B-5"
|
|
base ad:0x7000DC00
|
|
width 11.
|
|
if (((d.l(ad:0x7000DC00))&0x4000001F)==(0x40000003||0x40000007||0x4000000F||0x4000001F))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CS_SEL ,Select a slave in the multi-slave environment" "CS0,CS1,CS2,CS3"
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" "Drive Low,Drive High,,"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Transmission/Receipt Byte on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PACKED ,Packed mode enable bit" "Unpacked Mode,Packed Mode"
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
elif (((d.l(ad:0x7000DC00))&0x4000001F)==(0x3||0x7||0xF||0x1F))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" ",,External Pull Down,External Pull High"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Byte Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PACKED ,Packed mode enable bit" "Unpacked Mode,Packed Mode"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,,,,,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
elif (((d.l(ad:0x7000DC00))&0x4000001F)!=(0x40000003||0x40000007||0x4000000F||0x4000001F))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" ",,External Pull Down,External Pull High"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Byte Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,,,,,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CS_SEL ,Select a slave in the multi-slave environment" "CS0,CS1,CS2,CS3"
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" "Drive Low,Drive High,,"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Byte Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
endif
|
|
if (((d.l(ad:0x7000DC00))&0x40000000)==0x40000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "COMMAND2,SPI Command2 Register"
|
|
bitfld.long 0x00 6.--11. " Tx_Clk_TAP_DELAY ,Delays the clock going out to the external device" "No delay,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " Rx_Clk_TAP_DELAY ,Delays the clock coming in from the external device" "No delay,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "COMMAND2,SPI Command2 Register (Useful only in Master Mode)"
|
|
endif
|
|
width 14.
|
|
textline " "
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CS_TIM1,CS Timing1 Register"
|
|
bitfld.long 0x00 28.--31. " CS_SETUP_TIME3 ,Specifies the setup time of the chip select CS3" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 24.--27. " CS_HOLD_TIME3 ,Specifies the hold time of the chip select CS3" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 20.--23. " CS_SETUP_TIME2 ,Specifies the setup time of the chip select CS2" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CS_HOLD_TIME2 ,Specifies the hold time of the chip select CS2" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 12.--15. " CS_SETUP_TIME1 ,Specifies the setup time of the chip select CS1" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 8.--11. " CS_HOLD_TIME1 ,Specifies the hold time of the chip select CS1" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CS_SETUP_TIME0 ,Specifies the setup time of the chip select CS0" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 0.--3. " CS_HOLD_TIME0 ,Specifies the hold time of the chip select CS0" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
if (((d.l(ad:0x7000DC00+0x20))&0x80000000)==0x00)&&(((d.l(ad:0x7000DC00))&0x80000000)==0x00)
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "CS_TIM2,CS Timing2 Register"
|
|
bitfld.long 0x00 29. " CS_ACTIVE_BETWEEN_PACKETS3 ,Specifies if CS stays active between two packets on CS3" "Inactive,Active"
|
|
bitfld.long 0x00 21. " CS_ACTIVE_BETWEEN_PACKETS2 ,Specifies if CS stays active between two packets on CS2" "Inactive,Active"
|
|
bitfld.long 0x00 13. " CS_ACTIVE_BETWEEN_PACKETS1 ,Specifies if CS stays active between two packets on CS1" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CS_ACTIVE_BETWEEN_PACKETS0 ,Specifies if CS stays active between two packets on CS0" "Inactive,Active"
|
|
line.long 0x04 "TRANS_STATUS,TRANSFER Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SLV_IDLE_COUNT ,Slave Continuous Mode"
|
|
else
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "CS_TIM2,CS Timing2 Register"
|
|
bitfld.long 0x00 29. " CS_ACTIVE_BETWEEN_PACKETS3 ,Specifies if CS stays active between two packets on CS3" "Inactive,Active"
|
|
bitfld.long 0x00 24.--28. " CYCLES_BETWEEN_PACKETS3 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21. " CS_ACTIVE_BETWEEN_PACKETS2 ,Specifies if CS stays active between two packets on CS2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " CYCLES_BETWEEN_PACKETS2 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13. " CS_ACTIVE_BETWEEN_PACKETS1 ,Specifies if CS stays active between two packets on CS1" "Inactive,Active"
|
|
bitfld.long 0x00 8.--12. " CYCLES_BETWEEN_PACKETS1 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CS_ACTIVE_BETWEEN_PACKETS0 ,Specifies if CS stays active between two packets on CS0" "Inactive,Active"
|
|
bitfld.long 0x00 0.--4. " CYCLES_BETWEEN_PACKETS0 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "TRANS_STATUS,TRANSFER Status Register"
|
|
eventfld.long 0x04 30. " RDY ,Ready bit" "Not ready,Ready"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SLV_IDLE_COUNT ,Slave Continuous Mode"
|
|
hexmask.long.word 0x04 0.--15. 1. " BLOCK_COUNT ,Counts the number of packets in a transaction"
|
|
endif
|
|
textline " "
|
|
if (((d.l(ad:0x7000DC00))&0x40000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FIFO_STATUS,Control/Status FIFO Status Register"
|
|
bitfld.long 0x00 31. " CS_INACTIVE ,CS deasserted error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 30. " FRAME_END ,Continuous mode is terminated" "No,Yes"
|
|
hexmask.long.byte 0x00 23.--29. 1. " RX_FIFO_FULL_COUNT ,Indicates the number of slots in the receive FIFO"
|
|
hexmask.long.byte 0x00 16.--22. 1. " TX_FIFO_EMPTY_COUNT ,Indicates the number of slots in the transmit FIFO"
|
|
bitfld.long 0x00 15. " RX_FIFO_FLUSH ,Flush Rx FIFO" "NOP,FLUSH"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TX_FIFO_FLUSH ,Flush Tx FIFO" "NOP,FLUSH"
|
|
eventfld.long 0x00 8. " ERR ,Error flag" "No error,Error"
|
|
eventfld.long 0x00 7. " TX_FIFO_OVF ,TX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 6. " TX_FIFO_UNR ,TX FIFO Underrun" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " RX_FIFO_OVF ,RX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 4. " RX_FIFO_UNR ,RX FIFO Underrun" "No error,Error"
|
|
bitfld.long 0x00 3. " TX_FIFO_FULL ,TX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 2. " TX_FIFO_EMPTY ,TX FIFO Empty Status" "No empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_FIFO_FULL ,RX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 0. " RX_FIFO_EMPTY ,RX FIFO Empty Status" "No empty,Empty"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FIFO_STATUS,Control/Status FIFO Status Register"
|
|
textline " "
|
|
bitfld.long 0x00 30. " FRAME_END ,Continuous mode is terminated" "No,Yes"
|
|
hexmask.long.byte 0x00 23.--29. 1. " RX_FIFO_FULL_COUNT ,Number of slots in the receive FIFO"
|
|
hexmask.long.byte 0x00 16.--22. 1. " TX_FIFO_EMPTY_COUNT ,Number of slots in the transmit FIFO"
|
|
bitfld.long 0x00 15. " RX_FIFO_FLUSH ,Flush Rx FIFO" "NOP,FLUSH"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TX_FIFO_FLUSH ,Flush Tx FIFO" "NOP,FLUSH"
|
|
eventfld.long 0x00 8. " ERR ,Error flag" "No error,Error"
|
|
eventfld.long 0x00 7. " TX_FIFO_OVF ,TX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 6. " TX_FIFO_UNR ,TX FIFO Underrun" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " RX_FIFO_OVF ,RX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 4. " RX_FIFO_UNR ,RX FIFO Underrun" "No error,Error"
|
|
bitfld.long 0x00 3. " TX_FIFO_FULL ,TX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 2. " TX_FIFO_EMPTY ,TX FIFO Empty Status" "No empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_FIFO_FULL ,RX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 0. " RX_FIFO_EMPTY ,RX FIFO Empty Status" "No empty,Empty"
|
|
endif
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "TX_DATA,Transmit Data Register"
|
|
line.long 0x04 "RX_DATA,Receive Data Register"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DMA_CTL,DMA Control Register"
|
|
bitfld.long 0x00 31. " DMA ,Enable DMA Mode transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CONT ,Enable Continuous Mode transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE.RX ,Interrupt enable on receive completion" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " IE.TX ,Interrupt enable on transmit completion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " RX_TRIG ,Receive FIFO trigger level" "1 word,4 word,8 word,16 word"
|
|
bitfld.long 0x00 15.--16. " TX_TRIG ,Transmit FIFO trigger level" "1 word,4 word,8 word,16 word"
|
|
if (((d.l(ad:0x7000DC00+0x20))&0x80000000)==0x00)&&(((d.l(ad:0x7000DC00))&0x80000000)==0x00)
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "DMA_BLK,Block Size Register (Useful only in PIO or DMA mode)"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA_BLK,Block Size Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BLOCK_SIZE ,Size of data block to be transferred"
|
|
endif
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "FIFO1,TX FIFO Register"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "FIFO2,RX FIFO Register"
|
|
if (((d.l(ad:0x7000DC00))&0x40000000)==0x40000000)
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "SPARE_CTLR,Spare Control Register"
|
|
bitfld.long 0x00 8.--10. " SPARE_CONTROL_REGISTER_BYTE2 ,Adjust the clock delay on internal registers" "0,1,2,3,4,5,6,7"
|
|
else
|
|
hgroup.long 0x18C++0x03
|
|
hide.long 0x00 "SPARE_CTLR,Spare Control Register (Useful only in Master Mode)"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "2B-6"
|
|
base ad:0x7000DE00
|
|
width 11.
|
|
if (((d.l(ad:0x7000DE00))&0x4000001F)==(0x40000003||0x40000007||0x4000000F||0x4000001F))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CS_SEL ,Select a slave in the multi-slave environment" "CS0,CS1,CS2,CS3"
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" "Drive Low,Drive High,,"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Transmission/Receipt Byte on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PACKED ,Packed mode enable bit" "Unpacked Mode,Packed Mode"
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
elif (((d.l(ad:0x7000DE00))&0x4000001F)==(0x3||0x7||0xF||0x1F))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" ",,External Pull Down,External Pull High"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Byte Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PACKED ,Packed mode enable bit" "Unpacked Mode,Packed Mode"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,,,,,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
elif (((d.l(ad:0x7000DE00))&0x4000001F)!=(0x40000003||0x40000007||0x4000000F||0x4000001F))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" ",,External Pull Down,External Pull High"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Byte Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,,,,,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COMMAND1,SPI Command1 Register"
|
|
bitfld.long 0x00 31. " PIO ,PIO Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MS ,Master/Slave mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 28.--29. " MODE ,SPI interface clock mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " CS_SEL ,Select a slave in the multi-slave environment" "CS0,CS1,CS2,CS3"
|
|
bitfld.long 0x00 25. " CS_POL_INACTIVE3 ,Inactive value of devices cs connected to CS3" "Low,High"
|
|
bitfld.long 0x00 24. " CS_POL_INACTIVE2 ,Inactive value of devices cs connected to CS2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CS_POL_INACTIVE1 ,Inactive value of devices cs connected to CS1" "Low,High"
|
|
bitfld.long 0x00 22. " CS_POL_INACTIVE0 ,Inactive value of devices cs connected to CS0" "Low,High"
|
|
bitfld.long 0x00 21. " CS_SW_HW ,CS control source" "Software,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CS_SW_VAL ,CS signal value" "Low,High"
|
|
bitfld.long 0x00 18.--19. " IDLE_SDA ,Inactive data signal format" "Drive Low,Drive High,,"
|
|
bitfld.long 0x00 17. " BIDIR ,Bidirectional Transfer Control Bit" "Normal Mode,Bidirectional Mode"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EN_LE_BIT ,Little Endian Bit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " EN_LE_BYTE ,Little Endian Byte Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BOTH_EN_BIT ,Enable Bit Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BOTH_EN_BYTE ,Enable Byte Transmission/Receipt on both MISO and MOSI at the same time" "Normal,Both"
|
|
bitfld.long 0x00 12. " RX_EN ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TX_EN ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " BIT_LEN ,Bit length in either Packed or Unpacked Mode" ",,,4 bit,5 bit,6 bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit,16 bit,17 bit,18 bit,19 bit,20 bit,21 bit,22 bit,23 bit,24 bit,25 bit,26 bit,27 bit,28 bit,29 bit,30 bit,31 bit,32 bit"
|
|
endif
|
|
if (((d.l(ad:0x7000DE00))&0x40000000)==0x40000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "COMMAND2,SPI Command2 Register"
|
|
bitfld.long 0x00 6.--11. " Tx_Clk_TAP_DELAY ,Delays the clock going out to the external device" "No delay,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " Rx_Clk_TAP_DELAY ,Delays the clock coming in from the external device" "No delay,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "COMMAND2,SPI Command2 Register (Useful only in Master Mode)"
|
|
endif
|
|
width 14.
|
|
textline " "
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CS_TIM1,CS Timing1 Register"
|
|
bitfld.long 0x00 28.--31. " CS_SETUP_TIME3 ,Specifies the setup time of the chip select CS3" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 24.--27. " CS_HOLD_TIME3 ,Specifies the hold time of the chip select CS3" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 20.--23. " CS_SETUP_TIME2 ,Specifies the setup time of the chip select CS2" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CS_HOLD_TIME2 ,Specifies the hold time of the chip select CS2" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 12.--15. " CS_SETUP_TIME1 ,Specifies the setup time of the chip select CS1" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 8.--11. " CS_HOLD_TIME1 ,Specifies the hold time of the chip select CS1" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CS_SETUP_TIME0 ,Specifies the setup time of the chip select CS0" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
bitfld.long 0x00 0.--3. " CS_HOLD_TIME0 ,Specifies the hold time of the chip select CS0" "No delay,1 clock delay,2 clock delay,3 clock delay,4 clock delay,5 clock delay,6 clock delay,7 clock delay,8 clock delay,9 clock delay,10 clock delay,11 clock delay,12 clock delay,13 clock delay,14 clock delay,15 clock delay"
|
|
if (((d.l(ad:0x7000DE00+0x20))&0x80000000)==0x00)&&(((d.l(ad:0x7000DE00))&0x80000000)==0x00)
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "CS_TIM2,CS Timing2 Register"
|
|
bitfld.long 0x00 29. " CS_ACTIVE_BETWEEN_PACKETS3 ,Specifies if CS stays active between two packets on CS3" "Inactive,Active"
|
|
bitfld.long 0x00 21. " CS_ACTIVE_BETWEEN_PACKETS2 ,Specifies if CS stays active between two packets on CS2" "Inactive,Active"
|
|
bitfld.long 0x00 13. " CS_ACTIVE_BETWEEN_PACKETS1 ,Specifies if CS stays active between two packets on CS1" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CS_ACTIVE_BETWEEN_PACKETS0 ,Specifies if CS stays active between two packets on CS0" "Inactive,Active"
|
|
line.long 0x04 "TRANS_STATUS,TRANSFER Status Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SLV_IDLE_COUNT ,Slave Continuous Mode"
|
|
else
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "CS_TIM2,CS Timing2 Register"
|
|
bitfld.long 0x00 29. " CS_ACTIVE_BETWEEN_PACKETS3 ,Specifies if CS stays active between two packets on CS3" "Inactive,Active"
|
|
bitfld.long 0x00 24.--28. " CYCLES_BETWEEN_PACKETS3 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 21. " CS_ACTIVE_BETWEEN_PACKETS2 ,Specifies if CS stays active between two packets on CS2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " CYCLES_BETWEEN_PACKETS2 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13. " CS_ACTIVE_BETWEEN_PACKETS1 ,Specifies if CS stays active between two packets on CS1" "Inactive,Active"
|
|
bitfld.long 0x00 8.--12. " CYCLES_BETWEEN_PACKETS1 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CS_ACTIVE_BETWEEN_PACKETS0 ,Specifies if CS stays active between two packets on CS0" "Inactive,Active"
|
|
bitfld.long 0x00 0.--4. " CYCLES_BETWEEN_PACKETS0 ,Specifies the number of cycles in the PIO/DMA Mode for communication on CS0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "TRANS_STATUS,TRANSFER Status Register"
|
|
eventfld.long 0x04 30. " RDY ,Ready bit" "Not ready,Ready"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SLV_IDLE_COUNT ,Slave Continuous Mode"
|
|
hexmask.long.word 0x04 0.--15. 1. " BLOCK_COUNT ,Counts the number of packets in a transaction"
|
|
endif
|
|
textline " "
|
|
if (((d.l(ad:0x7000DE00))&0x40000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FIFO_STATUS,Control/Status FIFO Status Register"
|
|
bitfld.long 0x00 31. " CS_INACTIVE ,CS deasserted error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 30. " FRAME_END ,Continuous mode is terminated" "No,Yes"
|
|
hexmask.long.byte 0x00 23.--29. 1. " RX_FIFO_FULL_COUNT ,Indicates the number of slots in the receive FIFO"
|
|
hexmask.long.byte 0x00 16.--22. 1. " TX_FIFO_EMPTY_COUNT ,Indicates the number of slots in the transmit FIFO"
|
|
bitfld.long 0x00 15. " RX_FIFO_FLUSH ,Flush Rx FIFO" "NOP,FLUSH"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TX_FIFO_FLUSH ,Flush Tx FIFO" "NOP,FLUSH"
|
|
eventfld.long 0x00 8. " ERR ,Error flag" "No error,Error"
|
|
eventfld.long 0x00 7. " TX_FIFO_OVF ,TX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 6. " TX_FIFO_UNR ,TX FIFO Underrun" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " RX_FIFO_OVF ,RX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 4. " RX_FIFO_UNR ,RX FIFO Underrun" "No error,Error"
|
|
bitfld.long 0x00 3. " TX_FIFO_FULL ,TX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 2. " TX_FIFO_EMPTY ,TX FIFO Empty Status" "No empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_FIFO_FULL ,RX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 0. " RX_FIFO_EMPTY ,RX FIFO Empty Status" "No empty,Empty"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FIFO_STATUS,Control/Status FIFO Status Register"
|
|
textline " "
|
|
bitfld.long 0x00 30. " FRAME_END ,Continuous mode is terminated" "No,Yes"
|
|
hexmask.long.byte 0x00 23.--29. 1. " RX_FIFO_FULL_COUNT ,Number of slots in the receive FIFO"
|
|
hexmask.long.byte 0x00 16.--22. 1. " TX_FIFO_EMPTY_COUNT ,Number of slots in the transmit FIFO"
|
|
bitfld.long 0x00 15. " RX_FIFO_FLUSH ,Flush Rx FIFO" "NOP,FLUSH"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TX_FIFO_FLUSH ,Flush Tx FIFO" "NOP,FLUSH"
|
|
eventfld.long 0x00 8. " ERR ,Error flag" "No error,Error"
|
|
eventfld.long 0x00 7. " TX_FIFO_OVF ,TX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 6. " TX_FIFO_UNR ,TX FIFO Underrun" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " RX_FIFO_OVF ,RX FIFO Overflow" "No error,Error"
|
|
eventfld.long 0x00 4. " RX_FIFO_UNR ,RX FIFO Underrun" "No error,Error"
|
|
bitfld.long 0x00 3. " TX_FIFO_FULL ,TX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 2. " TX_FIFO_EMPTY ,TX FIFO Empty Status" "No empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RX_FIFO_FULL ,RX FIFO Full Status" "No full,Full"
|
|
bitfld.long 0x00 0. " RX_FIFO_EMPTY ,RX FIFO Empty Status" "No empty,Empty"
|
|
endif
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "TX_DATA,Transmit Data Register"
|
|
line.long 0x04 "RX_DATA,Receive Data Register"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DMA_CTL,DMA Control Register"
|
|
bitfld.long 0x00 31. " DMA ,Enable DMA Mode transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CONT ,Enable Continuous Mode transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IE.RX ,Interrupt enable on receive completion" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " IE.TX ,Interrupt enable on transmit completion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " RX_TRIG ,Receive FIFO trigger level" "1 word,4 word,8 word,16 word"
|
|
bitfld.long 0x00 15.--16. " TX_TRIG ,Transmit FIFO trigger level" "1 word,4 word,8 word,16 word"
|
|
if (((d.l(ad:0x7000DE00+0x20))&0x80000000)==0x00)&&(((d.l(ad:0x7000DE00))&0x80000000)==0x00)
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "DMA_BLK,Block Size Register (Useful only in PIO or DMA mode)"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DMA_BLK,Block Size Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BLOCK_SIZE ,Size of data block to be transferred"
|
|
endif
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "FIFO1,TX FIFO Register"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "FIFO2,RX FIFO Register"
|
|
if (((d.l(ad:0x7000DE00))&0x40000000)==0x40000000)
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "SPARE_CTLR,Spare Control Register"
|
|
bitfld.long 0x00 8.--10. " SPARE_CONTROL_REGISTER_BYTE2 ,Adjust the clock delay on internal registers" "0,1,2,3,4,5,6,7"
|
|
else
|
|
hgroup.long 0x18C++0x03
|
|
hide.long 0x00 "SPARE_CTLR,Spare Control Register (Useful only in Master Mode)"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "PWM Controller"
|
|
base ad:0x7000A000
|
|
width 13.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PWM_CSR_0_0,PWM Output-0 Configuration Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enable pulse width modulator" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--30. 1. " PWM_0 ,Pulse width"
|
|
hexmask.long.word 0x00 0.--12. 1. " PFM_0 ,Frequency divider"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PWM_CSR_1_0,PWM Output-1 Configuration Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enable pulse width modulator" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--30. 1. " PWM_1 ,Pulse width"
|
|
hexmask.long.word 0x00 0.--12. 1. " PFM_1 ,Frequency divider"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PWM_CSR_2_0,PWM Output-2 Configuration Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enable pulse width modulator" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--30. 1. " PWM_2 ,Pulse width"
|
|
hexmask.long.word 0x00 0.--12. 1. " PFM_2 ,Frequency divider"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PWM_CSR_3_0,PWM Output-3 Configuration Control Register"
|
|
bitfld.long 0x00 31. " ENB ,Enable pulse width modulator" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--30. 1. " PWM_3 ,Pulse width"
|
|
hexmask.long.word 0x00 0.--12. 1. " PFM_3 ,Frequency divider"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Thermal Sensor and Thermal Throttling Controller (SOC_THERM)"
|
|
base ad:0x700E2000
|
|
width 22.
|
|
tree "Thermal Controller (THERMCTL)"
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "LEVEL0_GROUP_CPU_0,LEVEL0_GROUP_CPU_0"
|
|
hexmask.long.byte 0x00 17.--24. 1. " UP_THRESH , Threshold value for thermal sensor"
|
|
hexmask.long.byte 0x00 9.--16. 1. " DN_THRESH , Up threshold value for thermal sensor"
|
|
bitfld.long 0x00 8. " EN ,Enable for temperature monitoring" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TS , TSENSE Modifier" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " CPU , Initiate CPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x00 3.--4. " GPU ,Initiate GPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x00 0.--1. " S ,Status" "Bellow,In,Res,Above"
|
|
line.long 0x04 "LEVEL0_GROUP_GPU_0,LEVEL0_GROUP_GPU_0"
|
|
hexmask.long.byte 0x04 17.--24. 1. " UP_THRESH , Threshold value for thermal sensor"
|
|
hexmask.long.byte 0x04 9.--16. 1. " DN_THRESH , Up threshold value for thermal sensor"
|
|
bitfld.long 0x04 8. " EN ,Enable for temperature monitoring" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " TS , TSENSE Modifier" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5.--6. " CPU , Initiate CPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x04 3.--4. " GPU ,Initiate GPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x04 0.--1. " S ,Status" "Bellow,In,Res,Above"
|
|
line.long 0x08 "LEVEL0_GROUP_MEM_0,LEVEL0_GROUP_MEM_0"
|
|
hexmask.long.byte 0x08 17.--24. 1. " UP_THRESH , Threshold value for thermal sensor"
|
|
hexmask.long.byte 0x08 9.--16. 1. " DN_THRESH , Up threshold value for thermal sensor"
|
|
bitfld.long 0x08 8. " EN ,Enable for temperature monitoring" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " TS , TSENSE Modifier" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5.--6. " CPU , Initiate CPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x08 3.--4. " GPU ,Initiate GPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x08 0.--1. " S ,Status" "Bellow,In,Res,Above"
|
|
line.long 0x0C "LEVEL0_GROUP_TSENSE_0,LEVEL0_GROUP_TSENSE_0"
|
|
hexmask.long.byte 0x0C 17.--24. 1. " UP_THRESH , Threshold value for thermal sensor"
|
|
hexmask.long.byte 0x0C 9.--16. 1. " DN_THRESH , Up threshold value for thermal sensor"
|
|
bitfld.long 0x0C 8. " EN ,Enable for temperature monitoring" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5.--6. " CPU , Initiate CPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x0C 3.--4. " GPU ,Initiate GPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x0C 0.--1. " S ,Status" "Bellow,In,Res,Above"
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "LEVEL0_UP_STATS_0,Count for UP threshold breaches for level 0 used in the lab"
|
|
line.long 0x04 "LEVEL0_DN_STATS_0,Count for DN threshold breaches for level 0 used in the lab"
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "LEVEL1_GROUP_CPU_0,LEVEL1_GROUP_CPU_0"
|
|
hexmask.long.byte 0x00 17.--24. 1. " UP_THRESH , Threshold value for thermal sensor"
|
|
hexmask.long.byte 0x00 9.--16. 1. " DN_THRESH , Up threshold value for thermal sensor"
|
|
bitfld.long 0x00 8. " EN ,Enable for temperature monitoring" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TS , TSENSE Modifier" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " CPU , Initiate CPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x00 3.--4. " GPU ,Initiate GPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x00 0.--1. " S ,Status" "Bellow,In,Res,Above"
|
|
line.long 0x04 "LEVEL1_GROUP_GPU_0,LEVEL1_GROUP_GPU_0"
|
|
hexmask.long.byte 0x04 17.--24. 1. " UP_THRESH , Threshold value for thermal sensor"
|
|
hexmask.long.byte 0x04 9.--16. 1. " DN_THRESH , Up threshold value for thermal sensor"
|
|
bitfld.long 0x04 8. " EN ,Enable for temperature monitoring" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " TS , TSENSE Modifier" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5.--6. " CPU , Initiate CPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x04 3.--4. " GPU ,Initiate GPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x04 0.--1. " S ,Status" "Bellow,In,Res,Above"
|
|
line.long 0x08 "LEVEL1_GROUP_MEM_0,LEVEL1_GROUP_MEM_0"
|
|
hexmask.long.byte 0x08 17.--24. 1. " UP_THRESH , Threshold value for thermal sensor"
|
|
hexmask.long.byte 0x08 9.--16. 1. " DN_THRESH , Up threshold value for thermal sensor"
|
|
bitfld.long 0x08 8. " EN ,Enable for temperature monitoring" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " TS , TSENSE Modifier" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5.--6. " CPU , Initiate CPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x08 3.--4. " GPU ,Initiate GPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x08 0.--1. " S ,Status" "Bellow,In,Res,Above"
|
|
line.long 0x0C "LEVEL1_GROUP_TSENSE_0,LEVEL1_GROUP_TSENSE_0"
|
|
hexmask.long.byte 0x0C 17.--24. 1. " UP_THRESH , Threshold value for thermal sensor"
|
|
hexmask.long.byte 0x0C 9.--16. 1. " DN_THRESH , Up threshold value for thermal sensor"
|
|
bitfld.long 0x0C 8. " EN ,Enable for temperature monitoring" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5.--6. " CPU , Initiate CPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x0C 3.--4. " GPU ,Initiate GPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x0C 0.--1. " S ,Status" "Bellow,In,Res,Above"
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "LEVEL1_UP_STATS_0,Count for UP threshold breaches for level 1 used in the lab"
|
|
line.long 0x04 "LEVEL1_DN_STATS_0,Count for DN threshold breaches for level 1 used in the lab"
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "LEVEL2_GROUP_CPU_0,LEVEL2_GROUP_CPU_0"
|
|
hexmask.long.byte 0x00 17.--24. 1. " UP_THRESH , Threshold value for thermal sensor"
|
|
hexmask.long.byte 0x00 9.--16. 1. " DN_THRESH , Up threshold value for thermal sensor"
|
|
bitfld.long 0x00 8. " EN ,Enable for temperature monitoring" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TS , TSENSE Modifier" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " CPU , Initiate CPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x00 3.--4. " GPU ,Initiate GPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x00 0.--1. " S ,Status" "Bellow,In,Res,Above"
|
|
line.long 0x04 "LEVEL2_GROUP_GPU_0,LEVEL2_GROUP_GPU_0"
|
|
hexmask.long.byte 0x04 17.--24. 1. " UP_THRESH , Threshold value for thermal sensor"
|
|
hexmask.long.byte 0x04 9.--16. 1. " DN_THRESH , Up threshold value for thermal sensor"
|
|
bitfld.long 0x04 8. " EN ,Enable for temperature monitoring" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " TS , TSENSE Modifier" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5.--6. " CPU , Initiate CPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x04 3.--4. " GPU ,Initiate GPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x04 0.--1. " S ,Status" "Bellow,In,Res,Above"
|
|
line.long 0x08 "LEVEL2_GROUP_MEM_0,LEVEL2_GROUP_MEM_0"
|
|
hexmask.long.byte 0x08 17.--24. 1. " UP_THRESH , Threshold value for thermal sensor"
|
|
hexmask.long.byte 0x08 9.--16. 1. " DN_THRESH , Up threshold value for thermal sensor"
|
|
bitfld.long 0x08 8. " EN ,Enable for temperature monitoring" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " TS , TSENSE Modifier" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5.--6. " CPU , Initiate CPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x08 3.--4. " GPU ,Initiate GPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x08 0.--1. " S ,Status" "Bellow,In,Res,Above"
|
|
line.long 0x0C "LEVEL2_GROUP_TSENSE_0,LEVEL2_GROUP_TSENSE_0"
|
|
hexmask.long.byte 0x0C 17.--24. 1. " UP_THRESH , Threshold value for thermal sensor"
|
|
hexmask.long.byte 0x0C 9.--16. 1. " DN_THRESH , Up threshold value for thermal sensor"
|
|
bitfld.long 0x0C 8. " EN ,Enable for temperature monitoring" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5.--6. " CPU , Initiate CPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x0C 3.--4. " GPU ,Initiate GPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x0C 0.--1. " S ,Status" "Bellow,In,Res,Above"
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "LEVEL2_UP_STATS_0,Count for UP threshold breaches for level 2 used in the lab"
|
|
line.long 0x04 "LEVEL2_DN_STATS_0,Count for DN threshold breaches for level 2 used in the lab"
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "LEVEL3_GROUP_CPU_0,LEVEL3_GROUP_CPU_0"
|
|
hexmask.long.byte 0x00 17.--24. 1. " UP_THRESH , Threshold value for thermal sensor"
|
|
hexmask.long.byte 0x00 9.--16. 1. " DN_THRESH , Up threshold value for thermal sensor"
|
|
bitfld.long 0x00 8. " EN ,Enable for temperature monitoring" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TS , TSENSE Modifier" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " CPU , Initiate CPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x00 3.--4. " GPU ,Initiate GPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x00 0.--1. " S ,Status" "Bellow,In,Res,Above"
|
|
line.long 0x04 "LEVEL3_GROUP_GPU_0,LEVEL3_GROUP_GPU_0"
|
|
hexmask.long.byte 0x04 17.--24. 1. " UP_THRESH , Threshold value for thermal sensor"
|
|
hexmask.long.byte 0x04 9.--16. 1. " DN_THRESH , Up threshold value for thermal sensor"
|
|
bitfld.long 0x04 8. " EN ,Enable for temperature monitoring" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " TS , TSENSE Modifier" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5.--6. " CPU , Initiate CPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x04 3.--4. " GPU ,Initiate GPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x04 0.--1. " S ,Status" "Bellow,In,Res,Above"
|
|
line.long 0x08 "LEVEL3_GROUP_MEM_0,LEVEL3_GROUP_MEM_0"
|
|
hexmask.long.byte 0x08 17.--24. 1. " UP_THRESH , Threshold value for thermal sensor"
|
|
hexmask.long.byte 0x08 9.--16. 1. " DN_THRESH , Up threshold value for thermal sensor"
|
|
bitfld.long 0x08 8. " EN ,Enable for temperature monitoring" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " TS , TSENSE Modifier" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5.--6. " CPU , Initiate CPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x08 3.--4. " GPU ,Initiate GPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x08 0.--1. " S ,Status" "Bellow,In,Res,Above"
|
|
line.long 0x0C "LEVEL3_GROUP_TSENSE_0,LEVEL3_GROUP_TSENSE_0"
|
|
hexmask.long.byte 0x0C 17.--24. 1. " UP_THRESH , Threshold value for thermal sensor"
|
|
hexmask.long.byte 0x0C 9.--16. 1. " DN_THRESH , Up threshold value for thermal sensor"
|
|
bitfld.long 0x0C 8. " EN ,Enable for temperature monitoring" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5.--6. " CPU , Initiate CPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x0C 3.--4. " GPU ,Initiate GPU throttling if level N is active" "None,Lite,Heavy,"
|
|
bitfld.long 0x0C 0.--1. " S ,Status" "Bellow,In,Res,Above"
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "LEVEL3_UP_STATS_0,Count for UP threshold breaches for level 3 used in the lab"
|
|
line.long 0x04 "LEVEL3_DN_STATS_0,Count for DN threshold breaches for level 3 used in the lab"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "THERMTRIP_CTL_0,THERMTRIP_CTL_0"
|
|
bitfld.long 0x00 28. " ANY_EN ,Initiate THERMTRIP based on any monitoring group" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " MEM_EN ,Initiate THERMTRIP based on MEM monitoring group" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GPU_EN ,Initiate THERMTRIP based on GPU monitoring group" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " CPU_EN ,Initiate THERMTRIP based on CPU monitoring group" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " TSENSE_EN ,Initiate THERMTRIP based on TSENSE monitoring group" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " GPU_N_MEM ,Threshold for thermal shutdown for GPU group"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPU ,Threshold for thermal shutdown for CPU group"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TSENSE ,Threshold for thermal shutdown for TSENSE group"
|
|
textline " "
|
|
group.long 0x84++0x0B
|
|
line.long 0x00 "INTR_0_SET/CLR,THERMCTL Interrupt enable register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " MD3 ,MEM group down threshold interrupt enable for level 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " MU3 ,MEM group up threshold interrupt enable for level 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " MD2 ,MEM group down threshold interrupt enable for level 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " MU2 ,MEM group up threshold interrupt enable for level 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " MD1 ,MEM group down threshold interrupt enable for level 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " MU1 ,MEM group up threshold interrupt enable for level 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " MD0 ,MEM group down threshold interrupt enable for level 0" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " MU0 ,MEM group up threshold interrupt enable for level 0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " GD3 ,GPU group down threshold interrupt enable for level 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " GU3 ,GPU group up threshold interrupt enable for level 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " GD2 ,GPU group down threshold interrupt enable for level 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " GU2 ,GPU group up threshold interrupt enable for level 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " GD1 ,GPU group down threshold interrupt enable for level 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " GU1 ,GPU group up threshold interrupt enable for level 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " GD0 ,GPU group down threshold interrupt enable for level 0" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " GU0 ,GPU group up threshold interrupt enable for level 1" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " CD3 ,CPU group down threshold interrupt enable for level 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " CU3 ,CPU group up threshold interrupt enable for level 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " CD2 ,CPU group down threshold interrupt enable for level 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " CU2 ,CPU group up threshold interrupt enable for level 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " CD1 ,CPU group down threshold interrupt enable for level 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " CU1 ,CPU group up threshold interrupt enable for level 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " CD0 ,CPU group down threshold interrupt enable for level 0" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " CU0 ,CPU group up threshold interrupt enable for level 0" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " TD3 ,TSENSE group down threshold interrupt enable for level 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " TU3 ,TSENSE group up threshold interrupt enable for level 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " TD2 ,TSENSE group down threshold interrupt enable for level 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " TU2 ,TSENSE group up threshold interrupt enable for level 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " TD1 ,TSENSE group down threshold interrupt enable for level 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TU1 ,TSENSE group up threshold interrupt enable for level 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " TD0 ,TSENSE group down threshold interrupt enable for level 0" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TU0 ,TSENSE group up threshold interrupt enable for level 0" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x94++0x0B
|
|
line.long 0x00 "STATS_CTL_0,STATS_CTL_0"
|
|
bitfld.long 0x00 3. " CLEAR_DN ,Clear DN statistics for all levels" "No effect,Clear"
|
|
bitfld.long 0x00 2. " ENB_DN ,Enable DN statistics collection for all levels" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CLEAR_UP ,Clear statistics for all levels" "No effect,Clear"
|
|
bitfld.long 0x00 0. " ENB_UP ,Enable statistics collection for all levels" "Disabled,Enabled"
|
|
line.long 0x04 "SLOWDOWN_THRESHOLD_0,SLOWDOWN_THRESHOLD_0"
|
|
hexmask.long.byte 0x04 24.--31. 1. " MEM ,Slowdown threshold for MEM group"
|
|
hexmask.long.byte 0x04 16.--23. 1. " GPU ,Slowdown threshold for GPU group"
|
|
hexmask.long.byte 0x04 8.--15. 1. " CPU ,Slowdown threshold for CPU group"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TSENSE ,Slowdown threshold for TSENSE group"
|
|
line.long 0x08 "SLOWDOWN_CTL_0,SLOWDOWN_CTL_0"
|
|
bitfld.long 0x08 30.--31. " SLOWDOWN_SELECT ,Selects which one to throttle" "NONE,CPU,GPU,BOTH"
|
|
bitfld.long 0x08 4. " ANY_EN ,ANY_EN" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " MEM_EN ,MEM_EN" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " GPU_EN ,GPU_EN" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CPU_EN ,CPU_EN" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TSENSE_EN ,TSENSE_EN" "Disabled,Enabled"
|
|
tree.end
|
|
width 20.
|
|
tree "TSensor (TSENSOR)"
|
|
group.long 0xC0++0x0B
|
|
line.long 0x00 "CPU0_CONFIG0_0,CPU0 CONFIG0 0"
|
|
hexmask.long.tbyte 0x00 8.--27. 4. " TALL ,M count"
|
|
eventfld.long 0x00 5. " STATUS_CLR ,Clears MIN/MAX statistics" "No effect,Clear"
|
|
bitfld.long 0x00 4. " TCALC_OVERFLOW ,Add operation overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " OVERFLOW ,14-bit overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CPTR_OVERFLOW ,Capture overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RO_SEL ,Ring oscillator select" "TS,VS"
|
|
bitfld.long 0x00 0. " STOP ,Sensor stop" "Disabled,Enabled"
|
|
line.long 0x04 "CPU0_CONFIG1_0,CPU0 CONFIG1 0"
|
|
bitfld.long 0x04 31. " TEMP_ENABLE ,Temperature enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--29. " TEN_COUNT ,Time between en and capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 15.--20. " TIDDQ_EN ,Time between IDDQ and en" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x04 0.--9. 1. " TSAMPLE , N count"
|
|
line.long 0x08 "CPU0_CONFIG2_0,CPU0 CONFIG2 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " THERM_A ,THERM_A"
|
|
hexmask.long.word 0x08 0.--15. 1. " THERM_B ,THERM_B"
|
|
rgroup.long (0xC0+0x0C)++0x0B
|
|
line.long 0x00 "CPU0_STATUS0_0,CPU0 STATUS0 0"
|
|
bitfld.long 0x00 31. " CAPTURE_VALID ,Valid capture available" "Not valid,Valid"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPTURE ,Last valid raw capture"
|
|
line.long 0x04 "CPU0_STATUS1_0,"
|
|
bitfld.long 0x04 31. " TEMP_VALID ,Valid capture available" "Not valid,Valid"
|
|
hexmask.long.word 0x04 0.--15. 1. " TEMP ,Last valid translated temperature"
|
|
line.long 0x08 "CPU0_STATUS2_0,"
|
|
hexmask.long.word 0x08 16.--31. 1. " TEMP_MAX ,Maximum temperature registered since last clear"
|
|
hexmask.long.word 0x08 0.--15. 1. " TEMP_MIN ,Minimum temperature registered since last clear"
|
|
group.long 0xE0++0x0B
|
|
line.long 0x00 "CPU1_CONFIG0_0,CPU1 CONFIG0 0"
|
|
hexmask.long.tbyte 0x00 8.--27. 4. " TALL ,M count"
|
|
eventfld.long 0x00 5. " STATUS_CLR ,Clears MIN/MAX statistics" "No effect,Clear"
|
|
bitfld.long 0x00 4. " TCALC_OVERFLOW ,Add operation overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " OVERFLOW ,14-bit overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CPTR_OVERFLOW ,Capture overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RO_SEL ,Ring oscillator select" "TS,VS"
|
|
bitfld.long 0x00 0. " STOP ,Sensor stop" "Disabled,Enabled"
|
|
line.long 0x04 "CPU1_CONFIG1_0,CPU1 CONFIG1 0"
|
|
bitfld.long 0x04 31. " TEMP_ENABLE ,Temperature enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--29. " TEN_COUNT ,Time between en and capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 15.--20. " TIDDQ_EN ,Time between IDDQ and en" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x04 0.--9. 1. " TSAMPLE , N count"
|
|
line.long 0x08 "CPU1_CONFIG2_0,CPU1 CONFIG2 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " THERM_A ,THERM_A"
|
|
hexmask.long.word 0x08 0.--15. 1. " THERM_B ,THERM_B"
|
|
rgroup.long (0xE0+0x0C)++0x0B
|
|
line.long 0x00 "CPU1_STATUS0_0,CPU1 STATUS0 0"
|
|
bitfld.long 0x00 31. " CAPTURE_VALID ,Valid capture available" "Not valid,Valid"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPTURE ,Last valid raw capture"
|
|
line.long 0x04 "CPU1_STATUS1_0,"
|
|
bitfld.long 0x04 31. " TEMP_VALID ,Valid capture available" "Not valid,Valid"
|
|
hexmask.long.word 0x04 0.--15. 1. " TEMP ,Last valid translated temperature"
|
|
line.long 0x08 "CPU1_STATUS2_0,"
|
|
hexmask.long.word 0x08 16.--31. 1. " TEMP_MAX ,Maximum temperature registered since last clear"
|
|
hexmask.long.word 0x08 0.--15. 1. " TEMP_MIN ,Minimum temperature registered since last clear"
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "CPU2_CONFIG0_0,CPU2 CONFIG0 0"
|
|
hexmask.long.tbyte 0x00 8.--27. 4. " TALL ,M count"
|
|
eventfld.long 0x00 5. " STATUS_CLR ,Clears MIN/MAX statistics" "No effect,Clear"
|
|
bitfld.long 0x00 4. " TCALC_OVERFLOW ,Add operation overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " OVERFLOW ,14-bit overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CPTR_OVERFLOW ,Capture overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RO_SEL ,Ring oscillator select" "TS,VS"
|
|
bitfld.long 0x00 0. " STOP ,Sensor stop" "Disabled,Enabled"
|
|
line.long 0x04 "CPU2_CONFIG1_0,CPU2 CONFIG1 0"
|
|
bitfld.long 0x04 31. " TEMP_ENABLE ,Temperature enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--29. " TEN_COUNT ,Time between en and capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 15.--20. " TIDDQ_EN ,Time between IDDQ and en" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x04 0.--9. 1. " TSAMPLE , N count"
|
|
line.long 0x08 "CPU2_CONFIG2_0,CPU2 CONFIG2 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " THERM_A ,THERM_A"
|
|
hexmask.long.word 0x08 0.--15. 1. " THERM_B ,THERM_B"
|
|
rgroup.long (0x100+0x0C)++0x0B
|
|
line.long 0x00 "CPU2_STATUS0_0,CPU2 STATUS0 0"
|
|
bitfld.long 0x00 31. " CAPTURE_VALID ,Valid capture available" "Not valid,Valid"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPTURE ,Last valid raw capture"
|
|
line.long 0x04 "CPU2_STATUS1_0,"
|
|
bitfld.long 0x04 31. " TEMP_VALID ,Valid capture available" "Not valid,Valid"
|
|
hexmask.long.word 0x04 0.--15. 1. " TEMP ,Last valid translated temperature"
|
|
line.long 0x08 "CPU2_STATUS2_0,"
|
|
hexmask.long.word 0x08 16.--31. 1. " TEMP_MAX ,Maximum temperature registered since last clear"
|
|
hexmask.long.word 0x08 0.--15. 1. " TEMP_MIN ,Minimum temperature registered since last clear"
|
|
group.long 0x120++0x0B
|
|
line.long 0x00 "CPU3_CONFIG0_0,CPU3 CONFIG0 0"
|
|
hexmask.long.tbyte 0x00 8.--27. 4. " TALL ,M count"
|
|
eventfld.long 0x00 5. " STATUS_CLR ,Clears MIN/MAX statistics" "No effect,Clear"
|
|
bitfld.long 0x00 4. " TCALC_OVERFLOW ,Add operation overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " OVERFLOW ,14-bit overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CPTR_OVERFLOW ,Capture overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RO_SEL ,Ring oscillator select" "TS,VS"
|
|
bitfld.long 0x00 0. " STOP ,Sensor stop" "Disabled,Enabled"
|
|
line.long 0x04 "CPU3_CONFIG1_0,CPU3 CONFIG1 0"
|
|
bitfld.long 0x04 31. " TEMP_ENABLE ,Temperature enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--29. " TEN_COUNT ,Time between en and capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 15.--20. " TIDDQ_EN ,Time between IDDQ and en" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x04 0.--9. 1. " TSAMPLE , N count"
|
|
line.long 0x08 "CPU3_CONFIG2_0,CPU3 CONFIG2 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " THERM_A ,THERM_A"
|
|
hexmask.long.word 0x08 0.--15. 1. " THERM_B ,THERM_B"
|
|
rgroup.long (0x120+0x0C)++0x0B
|
|
line.long 0x00 "CPU3_STATUS0_0,CPU3 STATUS0 0"
|
|
bitfld.long 0x00 31. " CAPTURE_VALID ,Valid capture available" "Not valid,Valid"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPTURE ,Last valid raw capture"
|
|
line.long 0x04 "CPU3_STATUS1_0,"
|
|
bitfld.long 0x04 31. " TEMP_VALID ,Valid capture available" "Not valid,Valid"
|
|
hexmask.long.word 0x04 0.--15. 1. " TEMP ,Last valid translated temperature"
|
|
line.long 0x08 "CPU3_STATUS2_0,"
|
|
hexmask.long.word 0x08 16.--31. 1. " TEMP_MAX ,Maximum temperature registered since last clear"
|
|
hexmask.long.word 0x08 0.--15. 1. " TEMP_MIN ,Minimum temperature registered since last clear"
|
|
group.long 0x140++0x0B
|
|
line.long 0x00 "MEM0_CONFIG0_0,MEM0 CONFIG0 0"
|
|
hexmask.long.tbyte 0x00 8.--27. 4. " TALL ,M count"
|
|
eventfld.long 0x00 5. " STATUS_CLR ,Clears MIN/MAX statistics" "No effect,Clear"
|
|
bitfld.long 0x00 4. " TCALC_OVERFLOW ,Add operation overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " OVERFLOW ,14-bit overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CPTR_OVERFLOW ,Capture overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RO_SEL ,Ring oscillator select" "TS,VS"
|
|
bitfld.long 0x00 0. " STOP ,Sensor stop" "Disabled,Enabled"
|
|
line.long 0x04 "MEM0_CONFIG1_0,MEM0 CONFIG1 0"
|
|
bitfld.long 0x04 31. " TEMP_ENABLE ,Temperature enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--29. " TEN_COUNT ,Time between en and capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 15.--20. " TIDDQ_EN ,Time between IDDQ and en" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x04 0.--9. 1. " TSAMPLE , N count"
|
|
line.long 0x08 "MEM0_CONFIG2_0,MEM0 CONFIG2 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " THERM_A ,THERM_A"
|
|
hexmask.long.word 0x08 0.--15. 1. " THERM_B ,THERM_B"
|
|
rgroup.long (0x140+0x0C)++0x0B
|
|
line.long 0x00 "MEM0_STATUS0_0,MEM0 STATUS0 0"
|
|
bitfld.long 0x00 31. " CAPTURE_VALID ,Valid capture available" "Not valid,Valid"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPTURE ,Last valid raw capture"
|
|
line.long 0x04 "MEM0_STATUS1_0,"
|
|
bitfld.long 0x04 31. " TEMP_VALID ,Valid capture available" "Not valid,Valid"
|
|
hexmask.long.word 0x04 0.--15. 1. " TEMP ,Last valid translated temperature"
|
|
line.long 0x08 "MEM0_STATUS2_0,"
|
|
hexmask.long.word 0x08 16.--31. 1. " TEMP_MAX ,Maximum temperature registered since last clear"
|
|
hexmask.long.word 0x08 0.--15. 1. " TEMP_MIN ,Minimum temperature registered since last clear"
|
|
group.long 0x160++0x0B
|
|
line.long 0x00 "MEM1_CONFIG0_0,MEM1 CONFIG0 0"
|
|
hexmask.long.tbyte 0x00 8.--27. 4. " TALL ,M count"
|
|
eventfld.long 0x00 5. " STATUS_CLR ,Clears MIN/MAX statistics" "No effect,Clear"
|
|
bitfld.long 0x00 4. " TCALC_OVERFLOW ,Add operation overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " OVERFLOW ,14-bit overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CPTR_OVERFLOW ,Capture overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RO_SEL ,Ring oscillator select" "TS,VS"
|
|
bitfld.long 0x00 0. " STOP ,Sensor stop" "Disabled,Enabled"
|
|
line.long 0x04 "MEM1_CONFIG1_0,MEM1 CONFIG1 0"
|
|
bitfld.long 0x04 31. " TEMP_ENABLE ,Temperature enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--29. " TEN_COUNT ,Time between en and capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 15.--20. " TIDDQ_EN ,Time between IDDQ and en" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x04 0.--9. 1. " TSAMPLE , N count"
|
|
line.long 0x08 "MEM1_CONFIG2_0,MEM1 CONFIG2 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " THERM_A ,THERM_A"
|
|
hexmask.long.word 0x08 0.--15. 1. " THERM_B ,THERM_B"
|
|
rgroup.long (0x160+0x0C)++0x0B
|
|
line.long 0x00 "MEM1_STATUS0_0,MEM1 STATUS0 0"
|
|
bitfld.long 0x00 31. " CAPTURE_VALID ,Valid capture available" "Not valid,Valid"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPTURE ,Last valid raw capture"
|
|
line.long 0x04 "MEM1_STATUS1_0,"
|
|
bitfld.long 0x04 31. " TEMP_VALID ,Valid capture available" "Not valid,Valid"
|
|
hexmask.long.word 0x04 0.--15. 1. " TEMP ,Last valid translated temperature"
|
|
line.long 0x08 "MEM1_STATUS2_0,"
|
|
hexmask.long.word 0x08 16.--31. 1. " TEMP_MAX ,Maximum temperature registered since last clear"
|
|
hexmask.long.word 0x08 0.--15. 1. " TEMP_MIN ,Minimum temperature registered since last clear"
|
|
group.long 0x180++0x0B
|
|
line.long 0x00 "GPU_CONFIG0_0,GPU CONFIG0 0"
|
|
hexmask.long.tbyte 0x00 8.--27. 4. " TALL ,M count"
|
|
eventfld.long 0x00 5. " STATUS_CLR ,Clears MIN/MAX statistics" "No effect,Clear"
|
|
bitfld.long 0x00 4. " TCALC_OVERFLOW ,Add operation overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " OVERFLOW ,14-bit overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CPTR_OVERFLOW ,Capture overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RO_SEL ,Ring oscillator select" "TS,VS"
|
|
bitfld.long 0x00 0. " STOP ,Sensor stop" "Disabled,Enabled"
|
|
line.long 0x04 "GPU_CONFIG1_0,GPU CONFIG1 0"
|
|
bitfld.long 0x04 31. " TEMP_ENABLE ,Temperature enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--29. " TEN_COUNT ,Time between en and capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 15.--20. " TIDDQ_EN ,Time between IDDQ and en" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x04 0.--9. 1. " TSAMPLE , N count"
|
|
line.long 0x08 "GPU_CONFIG2_0,GPU CONFIG2 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " THERM_A ,THERM_A"
|
|
hexmask.long.word 0x08 0.--15. 1. " THERM_B ,THERM_B"
|
|
rgroup.long (0x180+0x0C)++0x0B
|
|
line.long 0x00 "GPU_STATUS0_0,GPU STATUS0 0"
|
|
bitfld.long 0x00 31. " CAPTURE_VALID ,Valid capture available" "Not valid,Valid"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPTURE ,Last valid raw capture"
|
|
line.long 0x04 "GPU_STATUS1_0,"
|
|
bitfld.long 0x04 31. " TEMP_VALID ,Valid capture available" "Not valid,Valid"
|
|
hexmask.long.word 0x04 0.--15. 1. " TEMP ,Last valid translated temperature"
|
|
line.long 0x08 "GPU_STATUS2_0,"
|
|
hexmask.long.word 0x08 16.--31. 1. " TEMP_MAX ,Maximum temperature registered since last clear"
|
|
hexmask.long.word 0x08 0.--15. 1. " TEMP_MIN ,Minimum temperature registered since last clear"
|
|
group.long 0x1A0++0x0B
|
|
line.long 0x00 "PLLX_CONFIG0_0,PLLX CONFIG0 0"
|
|
hexmask.long.tbyte 0x00 8.--27. 4. " TALL ,M count"
|
|
eventfld.long 0x00 5. " STATUS_CLR ,Clears MIN/MAX statistics" "No effect,Clear"
|
|
bitfld.long 0x00 4. " TCALC_OVERFLOW ,Add operation overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " OVERFLOW ,14-bit overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CPTR_OVERFLOW ,Capture overflow" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RO_SEL ,Ring oscillator select" "TS,VS"
|
|
bitfld.long 0x00 0. " STOP ,Sensor stop" "Disabled,Enabled"
|
|
line.long 0x04 "PLLX_CONFIG1_0,PLLX CONFIG1 0"
|
|
bitfld.long 0x04 31. " TEMP_ENABLE ,Temperature enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--29. " TEN_COUNT ,Time between en and capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 15.--20. " TIDDQ_EN ,Time between IDDQ and en" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x04 0.--9. 1. " TSAMPLE , N count"
|
|
line.long 0x08 "PLLX_CONFIG2_0,PLLX CONFIG2 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " THERM_A ,THERM_A"
|
|
hexmask.long.word 0x08 0.--15. 1. " THERM_B ,THERM_B"
|
|
rgroup.long (0x1A0+0x0C)++0x0B
|
|
line.long 0x00 "PLLX_STATUS0_0,PLLX STATUS0 0"
|
|
bitfld.long 0x00 31. " CAPTURE_VALID ,Valid capture available" "Not valid,Valid"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPTURE ,Last valid raw capture"
|
|
line.long 0x04 "PLLX_STATUS1_0,"
|
|
bitfld.long 0x04 31. " TEMP_VALID ,Valid capture available" "Not valid,Valid"
|
|
hexmask.long.word 0x04 0.--15. 1. " TEMP ,Last valid translated temperature"
|
|
line.long 0x08 "PLLX_STATUS2_0,"
|
|
hexmask.long.word 0x08 16.--31. 1. " TEMP_MAX ,Maximum temperature registered since last clear"
|
|
hexmask.long.word 0x08 0.--15. 1. " TEMP_MIN ,Minimum temperature registered since last clear"
|
|
group.long 0x1C0++0x13
|
|
line.long 0x00 "PDIV_0,PDIV 0"
|
|
bitfld.long 0x00 12.--15. " CPU_PDIV ,PDIV for TS_CPU0 TS_CPU3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " GPU_PDIV ,PDIV for TS_GPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " MEM_PDIV ,PDIV for TS_MEM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " PLLX_PDIV ,PDIV for TS_PLLX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "HOTSPOT_OFF_0,HOTSPOT OFF 0"
|
|
hexmask.long.byte 0x04 16.--23. 1. " CPU_HOTSPOT_OFF ,CPU hotspot offset from PLLX"
|
|
hexmask.long.byte 0x04 8.--15. 1. " GPU_HOTSPOT_OFF ,GPU hotspot offset from PLLX"
|
|
hexmask.long.byte 0x04 0.--7. 1. " MEM_HOTSPOT_OFF ,MEM hotspot offset from PLLX"
|
|
line.long 0x08 "TEMP1_0,TEMP1 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " CPU_TEMP ,Processed CPU temperature seen by thermal throttling logic"
|
|
hexmask.long.word 0x08 0.--15. 1. " GPU_TEMP ,Processed GPU temperature seen by thermal throttling logic"
|
|
line.long 0x0C "TEMP2_0,TEMP2 0"
|
|
hexmask.long.word 0x0C 16.--31. 1. " MEM_TEMP ,Processed MEM temperature seen by thermal throttling logic"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SENSOR_TEMP ,Processed sensor (PLLX) temperature seen by thermal throttling logic"
|
|
textline " "
|
|
line.long 0x10 "PWR_VLD_OVERRIDE_0,PWR VLD OVERRIDE 0"
|
|
bitfld.long 0x10 0. " INVALIDATE_ON_PWR_GATING ,Use CPU/GPU virtual power gating status" "No active,Active"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "TEMP_SW_OVERRIDE_0,TEMP SW OVERRIDE 0"
|
|
bitfld.long 0x00 0. " SW_OVERRIDE_EN ,Enable software override of TSENSOR TEMP registers" "Disabled,Enabled"
|
|
tree.end
|
|
width 32.
|
|
tree "External OC Alarm (EDP_OC)"
|
|
group.long 0x310++0x0B
|
|
line.long 0x00 "ALARM_OC1_CFG_0,ALARM_OC1_CFG_0"
|
|
bitfld.long 0x00 6. " LONG_LATENCY_THROTTL ,Hardware is expected to control the PLL for large amounts of time when this OC alarm is engaged" "No,Yes"
|
|
bitfld.long 0x00 5. " HW_RESTORE_EN ,Auto-restore system to unthrottled state after this alarm is deasserted" "Disabled,Enabled"
|
|
eventfld.long 0x00 4. " PWRGOOD_MASK ,PWRGOOD_MASK: Mask the throttling if power is not good" "Enabled,Disabled"
|
|
bitfld.long 0x00 2.--3. " THROTTLE_MODE ,To select sticky versus brief mode throttling" "Disabled,Sticky,Brief,"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ALARM_POLARITY ,ALARM_POLARITY" "Assert high,Assert low"
|
|
bitfld.long 0x00 0. " EN_THROTTLE ,Enable the throttling on this over current alarm" "Disabled,Enabled"
|
|
line.long 0x04 "ALARM_OC1_CNT_THRESHOLD_0,ALARM_OC1 Event count threshold to raise interrupt: 0-rise interrupt for every event"
|
|
line.long 0x08 "ALARM_OC1_THROTTLE_PERIOD_0,ALARM_OC1 Brief throttle period in microseconds"
|
|
rgroup.long (0x310+0xC)++0x03
|
|
line.long 0x00 "ALARM_OC1_COUNT_0,ALARM_OC1_COUNT_0 - Event count"
|
|
group.long (0x310+0x10)++0x03
|
|
line.long 0x00 "ALARM_OC1_FILTER_0,ALARM_OC1_FILTER_0 - Event count"
|
|
group.long 0x324++0x0B
|
|
line.long 0x00 "ALARM_OC2_CFG_0,ALARM_OC2_CFG_0"
|
|
bitfld.long 0x00 6. " LONG_LATENCY_THROTTL ,Hardware is expected to control the PLL for large amounts of time when this OC alarm is engaged" "No,Yes"
|
|
bitfld.long 0x00 5. " HW_RESTORE_EN ,Auto-restore system to unthrottled state after this alarm is deasserted" "Disabled,Enabled"
|
|
eventfld.long 0x00 4. " PWRGOOD_MASK ,PWRGOOD_MASK: Mask the throttling if power is not good" "Enabled,Disabled"
|
|
bitfld.long 0x00 2.--3. " THROTTLE_MODE ,To select sticky versus brief mode throttling" "Disabled,Sticky,Brief,"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ALARM_POLARITY ,ALARM_POLARITY" "Assert high,Assert low"
|
|
bitfld.long 0x00 0. " EN_THROTTLE ,Enable the throttling on this over current alarm" "Disabled,Enabled"
|
|
line.long 0x04 "ALARM_OC2_CNT_THRESHOLD_0,ALARM_OC2 Event count threshold to raise interrupt: 0-rise interrupt for every event"
|
|
line.long 0x08 "ALARM_OC2_THROTTLE_PERIOD_0,ALARM_OC2 Brief throttle period in microseconds"
|
|
rgroup.long (0x324+0xC)++0x03
|
|
line.long 0x00 "ALARM_OC2_COUNT_0,ALARM_OC2_COUNT_0 - Event count"
|
|
group.long (0x324+0x10)++0x03
|
|
line.long 0x00 "ALARM_OC2_FILTER_0,ALARM_OC2_FILTER_0 - Event count"
|
|
group.long 0x338++0x0B
|
|
line.long 0x00 "ALARM_OC3_CFG_0,ALARM_OC3_CFG_0"
|
|
bitfld.long 0x00 6. " LONG_LATENCY_THROTTL ,Hardware is expected to control the PLL for large amounts of time when this OC alarm is engaged" "No,Yes"
|
|
bitfld.long 0x00 5. " HW_RESTORE_EN ,Auto-restore system to unthrottled state after this alarm is deasserted" "Disabled,Enabled"
|
|
eventfld.long 0x00 4. " PWRGOOD_MASK ,PWRGOOD_MASK: Mask the throttling if power is not good" "Enabled,Disabled"
|
|
bitfld.long 0x00 2.--3. " THROTTLE_MODE ,To select sticky versus brief mode throttling" "Disabled,Sticky,Brief,"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ALARM_POLARITY ,ALARM_POLARITY" "Assert high,Assert low"
|
|
bitfld.long 0x00 0. " EN_THROTTLE ,Enable the throttling on this over current alarm" "Disabled,Enabled"
|
|
line.long 0x04 "ALARM_OC3_CNT_THRESHOLD_0,ALARM_OC3 Event count threshold to raise interrupt: 0-rise interrupt for every event"
|
|
line.long 0x08 "ALARM_OC3_THROTTLE_PERIOD_0,ALARM_OC3 Brief throttle period in microseconds"
|
|
rgroup.long (0x338+0xC)++0x03
|
|
line.long 0x00 "ALARM_OC3_COUNT_0,ALARM_OC3_COUNT_0 - Event count"
|
|
group.long (0x338+0x10)++0x03
|
|
line.long 0x00 "ALARM_OC3_FILTER_0,ALARM_OC3_FILTER_0 - Event count"
|
|
group.long 0x34C++0x0B
|
|
line.long 0x00 "ALARM_OC4_CFG_0,ALARM_OC4_CFG_0"
|
|
bitfld.long 0x00 6. " LONG_LATENCY_THROTTL ,Hardware is expected to control the PLL for large amounts of time when this OC alarm is engaged" "No,Yes"
|
|
bitfld.long 0x00 5. " HW_RESTORE_EN ,Auto-restore system to unthrottled state after this alarm is deasserted" "Disabled,Enabled"
|
|
eventfld.long 0x00 4. " PWRGOOD_MASK ,PWRGOOD_MASK: Mask the throttling if power is not good" "Enabled,Disabled"
|
|
bitfld.long 0x00 2.--3. " THROTTLE_MODE ,To select sticky versus brief mode throttling" "Disabled,Sticky,Brief,"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ALARM_POLARITY ,ALARM_POLARITY" "Assert high,Assert low"
|
|
bitfld.long 0x00 0. " EN_THROTTLE ,Enable the throttling on this over current alarm" "Disabled,Enabled"
|
|
line.long 0x04 "ALARM_OC4_CNT_THRESHOLD_0,ALARM_OC4 Event count threshold to raise interrupt: 0-rise interrupt for every event"
|
|
line.long 0x08 "ALARM_OC4_THROTTLE_PERIOD_0,ALARM_OC4 Brief throttle period in microseconds"
|
|
rgroup.long (0x34C+0xC)++0x03
|
|
line.long 0x00 "ALARM_OC4_COUNT_0,ALARM_OC4_COUNT_0 - Event count"
|
|
group.long (0x34C+0x10)++0x03
|
|
line.long 0x00 "ALARM_OC4_FILTER_0,ALARM_OC4_FILTER_0 - Event count"
|
|
textline " "
|
|
group.long 0x39C++0x0B
|
|
line.long 0x00 "INTR_0_SET/CLR,EDP_OC Interrupt enable register"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " CLDVFS_DIDT ,CLDVFS interrupt status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " OC4 ,OC event 4 interrupt status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " OC3 ,OC event 3 interrupt status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " OC2 ,OC event 2 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " OC1 ,OC event 1 interrupt status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " OC0 ,OC event 0 interrupt status" "No interrupt,Interrupt"
|
|
rgroup.long 0x3A8++0x03
|
|
line.long 0x00 "ALARM_OC1_STATS_0,ALARM_OC1_STATS_0 - Statistics for event count"
|
|
rgroup.long 0x3AC++0x03
|
|
line.long 0x00 "ALARM_OC2_STATS_0,ALARM_OC2_STATS_0 - Statistics for event count"
|
|
rgroup.long 0x3B0++0x03
|
|
line.long 0x00 "ALARM_OC3_STATS_0,ALARM_OC3_STATS_0 - Statistics for event count"
|
|
rgroup.long 0x3B4++0x03
|
|
line.long 0x00 "ALARM_OC4_STATS_0,ALARM_OC4_STATS_0 - Statistics for event count"
|
|
group.long 0x3C4++0x07
|
|
line.long 0x00 "ALARM_STATS_CTRL_0,ALARM_STATS_CTRL_0"
|
|
bitfld.long 0x00 1. " CLEAR_ALL ,Clear all statistics" "No effect,Clear"
|
|
bitfld.long 0x00 0. " ENB_ALL ,Enable all statistics collections for all counters" "Disabled,Enabled"
|
|
line.long 0x04 "CLDVFS_DIDT_CNT_THRESHOLD_0,CLDVFS_DIDT_CNT_THRESHOLD_0 - Event count threshold to raise interrupt"
|
|
rgroup.long 0x3CC++0x0B
|
|
line.long 0x00 "CLDVFS_DIDT_EVENT_COUNT_0,CLDVFS_DIDT_EVENT_COUNT_0"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Event count"
|
|
line.long 0x04 "CLDVFS_DIDT_EVENT_CNT_FILTER_0,CLDVFS_DIDT_EVENT_CNT_FILTER_0 - Event count"
|
|
line.long 0x08 "CLDVFS_DIDT_EVENT_STATS_0,CLDVFS_DIDT_EVENT_STATS_0 - Statistics for event count"
|
|
group.long 0x3D8++0x03
|
|
line.long 0x00 "ALARM_THROTTLE_PERIOD_CTL_0,ALARM_THROTTLE_PERIOD_CTL_0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NUM_CLKS_IN_1US ,Number of soc_therm clocks in 1us used to determine brief throttle length"
|
|
tree.end
|
|
width 28.
|
|
tree "Throttling Controller (THROTTLECTL)"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "GLOBAL_THROTTLE_CFG_0,GLOBAL THROTTLE CFG 0"
|
|
bitfld.long 0x00 3. " DFLL_PSKIP_CTRL ,Do not pause CPU pulse skipper when cldvfs2soc_therm_skipper1 in enabled" "No,Yes"
|
|
bitfld.long 0x00 2. " PSKIP_RESTORE_CTRL ,Software restores pulse skipper" "No,Yes"
|
|
bitfld.long 0x00 1. " SW_OVERRIDE_MODE ,Pulse skipper software override" "No,Yes"
|
|
bitfld.long 0x00 0. " ENB ,Single bit to disable all throttling" "Disabled,Enabled"
|
|
group.long 0x408++0x1B
|
|
line.long 0x00 "SW_CPU_PSKIP_CTRL_0,SW CPU PSKIP CTRL 0"
|
|
bitfld.long 0x00 31. " ENB ,Enable the throttling" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SUPER_CDIV_DIVIDEND ,DIVIDEND: Actual value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SUPER_CDIV_DIVISOR ,DIVISOR: Actual value"
|
|
line.long 0x04 "SW_CPU_PSKIP_RAMP_RATE_0,SW CPU PSKIP RAMP RATE 0"
|
|
bitfld.long 0x04 31. " SEQ_BYPASS_MODE ,Bypass throttle seq and directly apply settings" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 8.--23. 1. " PULSE_SKIP_DURATION ,Duration in soc_therm_clk cycles"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PULSE_SKIP_STEP ,Pulse skip step size"
|
|
line.long 0x08 "SW_GPU_PSKIP_CTRL_0,SW GPU PSKIP CTRL 0"
|
|
rbitfld.long 0x08 30. " LOW_MED_HIGH ,LOW/MEDIUM/HIGH interface is used" "Not used,Used"
|
|
bitfld.long 0x08 16.--18. " THROTTLE_DEPTH ,Configures LOW/MEDIUM/HIGH throttling" ",LOW,MEDIUM,,HIGH,,,"
|
|
hexmask.long.byte 0x08 8.--15. 1. " SLOW_MED_HIGH ,SLOW_MED_HIGH: Actual Value"
|
|
hexmask.long.byte 0x08 0.--7. 1. " SUPER_CDIV_DIVISOR ,DIVIDEND: Actual value"
|
|
line.long 0x0C "SW_GPU_PSKIP_RAMP_RATE_0,SW GPU PSKIP RAMP RATE 0"
|
|
bitfld.long 0x0C 31. " SEQ_BYPASS_MODE ,Bypass throttle seq and directly apply settings" "Disabled,Enabled"
|
|
hexmask.long.word 0x0C 8.--23. 1. " PULSE_SKIP_DURATION ,Duration in soc_therm_clk cycles"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PULSE_SKIP_STEP ,Pulse skip step size"
|
|
line.long 0x10 "CPU_PSKIP_STATUS_0,CPU PSKIP STATUS 0"
|
|
hexmask.long.byte 0x10 12.--19. 1. " CURR_PULSE_SKIP_M ,M counter"
|
|
hexmask.long.byte 0x10 4.--11. 1. " CURR_PULSE_SKIP_N ,N counter"
|
|
bitfld.long 0x10 1. " SW_OVERRIDE_STATUS ,SW OVERRIDE STATUS" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " ENB_STATUS ,ENB STATUS" "Disabled,Enabled"
|
|
line.long 0x14 "GPU_PSKIP_STATUS_0,GPU PSKIP STATUS 0"
|
|
hexmask.long.byte 0x14 12.--19. 1. " CURR_PULSE_SKIP_M ,M counter"
|
|
hexmask.long.byte 0x14 4.--11. 1. " CURR_PULSE_SKIP_N ,N counter"
|
|
bitfld.long 0x14 1. " SW_OVERRIDE_STATUS ,SW OVERRIDE STATUS" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " ENB_STATUS ,ENB STATUS" "Disabled,Enabled"
|
|
line.long 0x18 "GPU_PSKIP_STATUS_0,PRIORITY_LOCK_0"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRIORITY ,Maximum priority allowed for software programmable vectors"
|
|
rgroup.long 0x428++0x03
|
|
line.long 0x00 "THROTTLE_STATUS_0,THROTTLE STATUS 0"
|
|
bitfld.long 0x00 12. " PRIORITY_LOCK_BREACH ,PRIORITY LOCK BREACH" "Normal,Over limit"
|
|
hexmask.long.byte 0x00 4.--11. 1. " THROTTLE_SEQ_STATE ,Throttle state"
|
|
bitfld.long 0x00 0. " ENB_STATUS ,Global enable status" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x430++0x0F
|
|
line.long 0x00 "LITE_CPU_PSKIP_CTRL_0,LITE CPU PSKIP CTRL 0"
|
|
bitfld.long 0x00 31. " ENB ,Enable the throttling" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SUPER_CDIV_DIVIDEND ,DIVIDEND: Actual value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SUPER_CDIV_DIVISOR ,DIVISOR: Actual value"
|
|
line.long 0x04 "LITE_CPU_PSKIP_RAMP_RATE_0,LITE CPU PSKIP RAMP RATE 0"
|
|
bitfld.long 0x04 31. " SEQ_BYPASS_MODE ,Bypass throttle seq and directly apply settings" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 8.--23. 1. " PULSE_SKIP_DURATION ,Duration in soc_therm_clk cycles"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PULSE_SKIP_STEP ,Pulse skip step size"
|
|
line.long 0x08 "LITE_GPU_PSKIP_CTRL_0,LITE GPU PSKIP CTRL 0"
|
|
bitfld.long 0x08 31. " ENB ,Enable the throttling" "Disabled,Enabled"
|
|
rbitfld.long 0x08 30. " LOW_MED_HIGH ,LOW/MEDIUM/HIGH interface is used" "Not used,Used"
|
|
bitfld.long 0x08 16.--18. " THROTTLE_DEPTH ,Configures LOW/MEDIUM/HIGH throttling" ",LOW,MEDIUM,,HIGH,,,"
|
|
hexmask.long.byte 0x08 8.--15. 1. " SLOW_MED_HIGH ,SLOW_MED_HIGH: Actual Value"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " SUPER_CDIV_DIVISOR ,DIVISOR: Actual Value"
|
|
line.long 0x0C "LITE_GPU_PSKIP_RAMP_RATE_0,"
|
|
bitfld.long 0x0C 31. " SEQ_BYPASS_MODE ,Bypass throttle seq and directly apply settings" "Disabled,Enabled"
|
|
hexmask.long.word 0x0C 8.--23. 1. " PULSE_SKIP_DURATION ,Duration in soc_therm_clk cycles"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PULSE_SKIP_STEP ,Pulse skip step size"
|
|
group.long 0x444++0x07
|
|
line.long 0x00 "LITE_THROTTLE_PRIORITY_0,LITE THROTTLE PRIORITY 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Bigger value indicates higher priority"
|
|
line.long 0x04 "LITE_THROTTLE_DELAY_0,Number of soc_therm_clk cycles to delay the alert"
|
|
group.long 0x460++0x0F
|
|
line.long 0x00 "HEAVY_CPU_PSKIP_CTRL_0,HEAVY CPU PSKIP CTRL 0"
|
|
bitfld.long 0x00 31. " ENB ,Enable the throttling" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SUPER_CDIV_DIVIDEND ,DIVIDEND: Actual value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SUPER_CDIV_DIVISOR ,DIVIDEND: Actual value"
|
|
line.long 0x04 "HEAVY_CPU_PSKIP_RAMP_RATE_0,HEAVY CPU PSKIP RAMP RATE 0"
|
|
bitfld.long 0x04 31. " SEQ_BYPASS_MODE ,Bypass throttle seq and directly apply settings" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 8.--23. 1. " PULSE_SKIP_DURATION ,Duration in soc_therm_clk cycles"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PULSE_SKIP_STEP ,Pulse skip step size"
|
|
line.long 0x08 "HEAVY_GPU_PSKIP_CTRL_0,HEAVY GPU PSKIP CTRL 0"
|
|
bitfld.long 0x08 31. " ENB ,Enable the throttling" "Disabled,Enabled"
|
|
rbitfld.long 0x08 30. " LOW_MED_HIGH ,LOW/MEDIUM/HIGH interface is used" "Not used,Used"
|
|
bitfld.long 0x08 16.--18. " THROTTLE_DEPTH ,Configures LOW/MEDIUM/HIGH throttling" ",LOW,MEDIUM,,HIGH,,,"
|
|
hexmask.long.byte 0x08 8.--15. 1. " SLOW_MED_HIGH ,SLOW_MED_HIGH: Actual Value"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " SUPER_CDIV_DIVISOR ,Actual Value"
|
|
line.long 0x0C "HEAVY_GPU_PSKIP_RAMP_RATE_0,HEAVY GPU PSKIP RAMP RATE 0"
|
|
bitfld.long 0x0C 31. " SEQ_BYPASS_MODE ,Bypass throttle seq and directly apply settings" "Disabled,Enabled"
|
|
hexmask.long.word 0x0C 8.--23. 1. " PULSE_SKIP_DURATION ,Duration in soc_therm_clk cycles"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PULSE_SKIP_STEP ,Pulse skip step size"
|
|
group.long 0x474++0x07
|
|
line.long 0x00 "HEAVY_THROTTLE_PRIORITY_0,HEAVY THROTTLE PRIORITY 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Bigger value indicates higher priority"
|
|
line.long 0x04 "HEAVY_THROTTLE_DELAY_0,Number of soc_therm_clk cycles to delay the alert"
|
|
group.long 0x490++0x0F
|
|
line.long 0x00 "OC1_CPU_PSKIP_CTRL_0,OC1 CPU PSKIP CTRL 0"
|
|
bitfld.long 0x00 31. " ENB ,Enable the throttling" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SUPER_CDIV_DIVIDEND ,DIVIDEND: Actual value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SUPER_CDIV_DIVISOR ,DIVIDEND: Actual value"
|
|
line.long 0x04 "OC1_CPU_PSKIP_RAMP_RATE_0,OC1 CPU PSKIP RAMP RATE 0"
|
|
bitfld.long 0x04 31. " SEQ_BYPASS_MODE ,Bypass throttle seq and directly apply settings" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 8.--23. 1. " PULSE_SKIP_DURATION ,Duration in soc_therm_clk cycles"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PULSE_SKIP_STEP ,Pulse skip step size"
|
|
line.long 0x08 "OC1_GPU_PSKIP_CTRL_0,OC1 GPU PSKIP CTRL 0"
|
|
bitfld.long 0x08 31. " ENB ,Enable the throttling" "Disabled,Enabled"
|
|
rbitfld.long 0x08 30. " LOW_MED_HIGH ,LOW/MEDIUM/HIGH interface is used" "Not used,Used"
|
|
bitfld.long 0x08 16.--18. " THROTTLE_DEPTH ,Configures LOW/MEDIUM/HIGH throttling" ",LOW,MEDIUM,,HIGH,,,"
|
|
hexmask.long.byte 0x08 8.--15. 1. " SLOW_MED_HIGH ,SLOW_MED_HIGH: Actual Value"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " SUPER_CDIV_DIVISOR ,Actual Value"
|
|
line.long 0x0C "OC1_GPU_PSKIP_RAMP_RATE_0,OC1 GPU PSKIP RAMP RATE 0"
|
|
bitfld.long 0x0C 31. " SEQ_BYPASS_MODE ,Bypass throttle seq and directly apply settings" "Disabled,Enabled"
|
|
hexmask.long.word 0x0C 8.--23. 1. " PULSE_SKIP_DURATION ,Duration in soc_therm_clk cycles"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PULSE_SKIP_STEP ,Pulse skip step size"
|
|
group.long (0x490+0x14)++0x07
|
|
line.long 0x00 "OC1_THROTTLE_PRIORITY_0,OC1 THROTTLE PRIORITY 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Bigger value indicates higher priority"
|
|
line.long 0x04 "OC1_THROTTLE_DELAY_0,Number of soc_therm_clk cycles to delay the alert"
|
|
group.long 0x4D0++0x0F
|
|
line.long 0x00 "OC2_CPU_PSKIP_CTRL_0,OC2 CPU PSKIP CTRL 0"
|
|
bitfld.long 0x00 31. " ENB ,Enable the throttling" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SUPER_CDIV_DIVIDEND ,DIVIDEND: Actual value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SUPER_CDIV_DIVISOR ,DIVIDEND: Actual value"
|
|
line.long 0x04 "OC2_CPU_PSKIP_RAMP_RATE_0,OC1 CPU PSKIP RAMP RATE 0"
|
|
bitfld.long 0x04 31. " SEQ_BYPASS_MODE ,Bypass throttle seq and directly apply settings" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 8.--23. 1. " PULSE_SKIP_DURATION ,Duration in soc_therm_clk cycles"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PULSE_SKIP_STEP ,Pulse skip step size"
|
|
line.long 0x08 "OC2_GPU_PSKIP_CTRL_0,OC1 GPU PSKIP CTRL 0"
|
|
bitfld.long 0x08 31. " ENB ,Enable the throttling" "Disabled,Enabled"
|
|
rbitfld.long 0x08 30. " LOW_MED_HIGH ,LOW/MEDIUM/HIGH interface is used" "Not used,Used"
|
|
bitfld.long 0x08 16.--18. " THROTTLE_DEPTH ,Configures LOW/MEDIUM/HIGH throttling" ",LOW,MEDIUM,,HIGH,,,"
|
|
hexmask.long.byte 0x08 8.--15. 1. " SLOW_MED_HIGH ,SLOW_MED_HIGH: Actual Value"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " SUPER_CDIV_DIVISOR ,Actual Value"
|
|
line.long 0x0C "OC2_GPU_PSKIP_RAMP_RATE_0,OC2 GPU PSKIP RAMP RATE 0"
|
|
bitfld.long 0x0C 31. " SEQ_BYPASS_MODE ,Bypass throttle seq and directly apply settings" "Disabled,Enabled"
|
|
hexmask.long.word 0x0C 8.--23. 1. " PULSE_SKIP_DURATION ,Duration in soc_therm_clk cycles"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PULSE_SKIP_STEP ,Pulse skip step size"
|
|
group.long (0x4D0+0x14)++0x07
|
|
line.long 0x00 "OC2_THROTTLE_PRIORITY_0,OC2 THROTTLE PRIORITY 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Bigger value indicates higher priority"
|
|
line.long 0x04 "OC2_THROTTLE_DELAY_0,Number of soc_therm_clk cycles to delay the alert"
|
|
group.long 0x510++0x0F
|
|
line.long 0x00 "OC3_CPU_PSKIP_CTRL_0,OC3 CPU PSKIP CTRL 0"
|
|
bitfld.long 0x00 31. " ENB ,Enable the throttling" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SUPER_CDIV_DIVIDEND ,DIVIDEND: Actual value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SUPER_CDIV_DIVISOR ,DIVIDEND: Actual value"
|
|
line.long 0x04 "OC3_CPU_PSKIP_RAMP_RATE_0,OC1 CPU PSKIP RAMP RATE 0"
|
|
bitfld.long 0x04 31. " SEQ_BYPASS_MODE ,Bypass throttle seq and directly apply settings" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 8.--23. 1. " PULSE_SKIP_DURATION ,Duration in soc_therm_clk cycles"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PULSE_SKIP_STEP ,Pulse skip step size"
|
|
line.long 0x08 "OC3_GPU_PSKIP_CTRL_0,OC1 GPU PSKIP CTRL 0"
|
|
bitfld.long 0x08 31. " ENB ,Enable the throttling" "Disabled,Enabled"
|
|
rbitfld.long 0x08 30. " LOW_MED_HIGH ,LOW/MEDIUM/HIGH interface is used" "Not used,Used"
|
|
bitfld.long 0x08 16.--18. " THROTTLE_DEPTH ,Configures LOW/MEDIUM/HIGH throttling" ",LOW,MEDIUM,,HIGH,,,"
|
|
hexmask.long.byte 0x08 8.--15. 1. " SLOW_MED_HIGH ,SLOW_MED_HIGH: Actual Value"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " SUPER_CDIV_DIVISOR ,Actual Value"
|
|
line.long 0x0C "OC3_GPU_PSKIP_RAMP_RATE_0,OC3 GPU PSKIP RAMP RATE 0"
|
|
bitfld.long 0x0C 31. " SEQ_BYPASS_MODE ,Bypass throttle seq and directly apply settings" "Disabled,Enabled"
|
|
hexmask.long.word 0x0C 8.--23. 1. " PULSE_SKIP_DURATION ,Duration in soc_therm_clk cycles"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PULSE_SKIP_STEP ,Pulse skip step size"
|
|
group.long (0x510+0x14)++0x07
|
|
line.long 0x00 "OC3_THROTTLE_PRIORITY_0,OC3 THROTTLE PRIORITY 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Bigger value indicates higher priority"
|
|
line.long 0x04 "OC3_THROTTLE_DELAY_0,Number of soc_therm_clk cycles to delay the alert"
|
|
group.long 0x550++0x0F
|
|
line.long 0x00 "OC4_CPU_PSKIP_CTRL_0,OC4 CPU PSKIP CTRL 0"
|
|
bitfld.long 0x00 31. " ENB ,Enable the throttling" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SUPER_CDIV_DIVIDEND ,DIVIDEND: Actual value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SUPER_CDIV_DIVISOR ,DIVIDEND: Actual value"
|
|
line.long 0x04 "OC4_CPU_PSKIP_RAMP_RATE_0,OC1 CPU PSKIP RAMP RATE 0"
|
|
bitfld.long 0x04 31. " SEQ_BYPASS_MODE ,Bypass throttle seq and directly apply settings" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 8.--23. 1. " PULSE_SKIP_DURATION ,Duration in soc_therm_clk cycles"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PULSE_SKIP_STEP ,Pulse skip step size"
|
|
line.long 0x08 "OC4_GPU_PSKIP_CTRL_0,OC1 GPU PSKIP CTRL 0"
|
|
bitfld.long 0x08 31. " ENB ,Enable the throttling" "Disabled,Enabled"
|
|
rbitfld.long 0x08 30. " LOW_MED_HIGH ,LOW/MEDIUM/HIGH interface is used" "Not used,Used"
|
|
bitfld.long 0x08 16.--18. " THROTTLE_DEPTH ,Configures LOW/MEDIUM/HIGH throttling" ",LOW,MEDIUM,,HIGH,,,"
|
|
hexmask.long.byte 0x08 8.--15. 1. " SLOW_MED_HIGH ,SLOW_MED_HIGH: Actual Value"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " SUPER_CDIV_DIVISOR ,Actual Value"
|
|
line.long 0x0C "OC4_GPU_PSKIP_RAMP_RATE_0,OC4 GPU PSKIP RAMP RATE 0"
|
|
bitfld.long 0x0C 31. " SEQ_BYPASS_MODE ,Bypass throttle seq and directly apply settings" "Disabled,Enabled"
|
|
hexmask.long.word 0x0C 8.--23. 1. " PULSE_SKIP_DURATION ,Duration in soc_therm_clk cycles"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PULSE_SKIP_STEP ,Pulse skip step size"
|
|
group.long (0x550+0x14)++0x07
|
|
line.long 0x00 "OC4_THROTTLE_PRIORITY_0,OC4 THROTTLE PRIORITY 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Bigger value indicates higher priority"
|
|
line.long 0x04 "OC4_THROTTLE_DELAY_0,Number of soc_therm_clk cycles to delay the alert"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "Audio-Video Processor (AVP)"
|
|
tree "Arbitration Priority registers (ARB_PRIO)"
|
|
base ad:0x60003000
|
|
width 16.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "CPU_PRIORITY_0,Shared Resource Priority for CPU Register"
|
|
bitfld.long 0x00 27.--29. " VDE ,VDE" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 24.--26. " HOST1X ,HOST1X" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 21.--23. " APB ,Access Privilege to APB Bus Register" "Highest,1,2,Lowest,?..."
|
|
bitfld.long 0x00 18.--20. " PSB ,Access Privilege to PSB Register" "Highest,1,2,Lowest,?..."
|
|
bitfld.long 0x00 12.--14. " IROM0 ,IROM0" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 9.--11. " IRAM3 ,IRAM3" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 6.--8. " IRAM2 ,IRAM2" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 3.--5. " IRAM1 ,IRAM1" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " IRAM0 ,IRAM0" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0x04 "COP_PRIORITY_0,Shared Resource Priority for COP Register"
|
|
bitfld.long 0x04 27.--29. " VDE ,VDE" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x04 24.--26. " HOST1X ,HOST1X" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x04 21.--23. " APB , Access Privilege to APB Bus Register" "Highest,1,2,Lowest,?..."
|
|
bitfld.long 0x04 18.--20. " PSB , Access Privilege to PSB Register" "Highest,1,2,Lowest,?..."
|
|
bitfld.long 0x04 12.--14. " IROM0 ,IROM0" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x04 9.--11. " IRAM3 ,IRAM3" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x04 6.--8. " IRAM2 ,IRAM2" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x04 3.--5. " IRAM1 ,IRAM1" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " IRAM0 ,IRAM0" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0x08 "VCP_PRIORITY_0,Shared Resource Priority for VCP Register"
|
|
bitfld.long 0x08 27.--29. " VDE ,VDE" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x08 24.--26. " HOST1X ,HOST1X" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x08 21.--23. " APB , Access Privilege to APB Bus Register" "Highest,1,2,Lowest,?...."
|
|
bitfld.long 0x08 18.--20. " PSB , Access Privilege to PSB Register" "Highest,1,2,Lowest,?...."
|
|
bitfld.long 0x08 12.--14. " IROM0 ,IROM0" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x08 9.--11. " IRAM3 ,IRAM3" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x08 6.--8. " IRAM2 ,IRAM2" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x08 3.--5. " IRAM1 ,IRAM1" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " IRAM0 ,IRAM0" "Highest,1,2,3,4,5,6,Lowest"
|
|
line.long 0x0C "DMA_PRIORITY_0,Shared Resource Priority for DMA Register"
|
|
bitfld.long 0x0C 27.--29. " VDE ,VDE" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x0C 24.--26. " HOST1X ,HOST1X" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x0C 21.--23. " APB , Access Privilege to APB Bus Register" "Highest,1,2,Lowest,?...."
|
|
bitfld.long 0x0C 18.--20. " PSB , Access Privilege to PSB Register" "Highest,1,2,Lowest,?...."
|
|
bitfld.long 0x0C 12.--14. " IROM0 ,IROM0" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x0C 9.--11. " IRAM3 ,IRAM3" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x0C 6.--8. " IRAM2 ,IRAM2" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x0C 3.--5. " IRAM1 ,IRAM1" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--2. " IRAM0 ,IRAM0" "Highest,1,2,3,4,5,6,Lowest"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "UCQ_PRIORITY_0,Shared Resource Priority for DMA Register"
|
|
bitfld.long 0x00 27.--29. " VDE ,VDE" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 24.--26. " HOST1X ,HOST1X" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 21.--23. " APB ,Access Privilege to APB Bus Register" "Highest,1,2,Lowest,?..."
|
|
bitfld.long 0x00 18.--20. " PSB ,Access Privilege to PSB Register" "Highest,1,2,Lowest,?..."
|
|
bitfld.long 0x00 12.--14. " IROM0 ,IROM0" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 9.--11. " IRAM3 ,IRAM3" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 6.--8. " IRAM2 ,IRAM2" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 3.--5. " IRAM1 ,IRAM1" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " IRAM0 ,IRAM0" "Highest,1,2,3,4,5,6,Lowest"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Cache Controller (AVP_CACHE)"
|
|
base ad:0x50040000
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CONFIG_0 ,Configuration 0"
|
|
bitfld.long 0x00 31. " OBS_BUS_EN ,OBS_BUS capture register clocking enable" "FALSE,TRUE"
|
|
bitfld.long 0x00 16. " DISABLE_SAMELINE ,TAG RAM reading avoiding when consecutive reads are within the same cache line" "FALSE,TRUE"
|
|
bitfld.long 0x00 15. " TAG_CHECK_CLR_ERROR ,TAG CHECK CLR ERROR" "0,1"
|
|
bitfld.long 0x00 14. " TAG_CHECK_ABORT_ON_ERROR ,TAG CHECK ABORT ON ERROR" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FULL_LINE_DIRTY ,FULL LINE DIRTY" "FALSE,TRUE"
|
|
bitfld.long 0x00 12. " ENABLE_HANG_DETECT ,Hang Detect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DISABLE_RB ,Read Buffer Disable" "No,Yes"
|
|
bitfld.long 0x00 10. " DISABLE_RB ,Write Buffer disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MMU_TAG_MODE ,MMU Tag Mode" "PARALLEL,TAG_FIRST,MMU_FIRST,"
|
|
bitfld.long 0x00 7. " ENABLE_INTERRUPT ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " NEVER_ALLOCATE ,Never allocate new line" "FALSE,TRUE"
|
|
bitfld.long 0x00 3. " FORCE_WRITE_THROUGH ,Write Through cached writes" "FALSE,TRUE"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DISABLE_RANDOM_ALLOC ,LSFR Random Allocation disable" "No,Yes"
|
|
bitfld.long 0x00 1. " ENABLE_SKEW_ASSOC ,Skewed associativity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE_CACHE ,Chache Enable" "Disabled,Enabled"
|
|
line.long 0x04 "LOCK_0,LOCK 0"
|
|
bitfld.long 0x04 3. " LOCK_BITMAP[3] ,Lock way corresponding to LOCK_BITMAP[3]" "Unlocked,Locked"
|
|
bitfld.long 0x04 2. " LOCK_BITMAP[2] ,Lock way corresponding to LOCK_BITMAP[2]" "Unlocked,Locked"
|
|
bitfld.long 0x04 1. " LOCK_BITMAP[1] ,Lock way corresponding to LOCK_BITMAP[3]" "Unlocked,Locked"
|
|
bitfld.long 0x04 0. " LOCK_BITMAP[0] ,Lock way corresponding to LOCK_BITMAP[0]" "Unlocked,Locked"
|
|
rgroup.long 0x0C++0x0B
|
|
line.long 0x00 "SIZE_0,Hardcoded value that indicates the number of ways"
|
|
bitfld.long 0x00 0.--1. " MAX_WAY_INDEX ,Number of ways" "1 way,2 ways,3 ways,4 ways"
|
|
line.long 0x04 "LFSR_0,LFSR_0"
|
|
hexmask.long.byte 0x04 0.--7. 1. " STATUS ,Current status of the LFSR pseudo random generator"
|
|
line.long 0x08 "STATUS_0,STATUS_0"
|
|
hexmask.long 0x08 5.--31. 0x20 " CONFLICT_ADDR ,Physical address for which a TAG_CHECK_ERROR was generated"
|
|
bitfld.long 0x08 0. " TAG_CHECK_ERROR ,Multiple way for the same tag address indicator (Internal Error)" "No error,Error"
|
|
textline " "
|
|
width 26.
|
|
group.long 0xA0++0x07
|
|
line.long 0x00 "MMU_FALLBACK_ENTRY_0,MM FALLBACK ENTRY 0"
|
|
bitfld.long 0x00 3. " WR_ENA ,Enable Write" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RD_ENA ,Enable Read" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EXE_ENA ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CACHED ,Enable CASHED" "Disabled,Enabled"
|
|
line.long 0x04 "MMU_SHADOW_COPY_MASK_0_0,MMU SHADOW COPY MASK 00"
|
|
group.long 0xAC++0x07
|
|
line.long 0x00 "MMU_CFG_0,MMU Configuration 0"
|
|
bitfld.long 0x00 5. " CLR_ABORT ,Clean the abort statistics" "NOP,CLR"
|
|
bitfld.long 0x00 4. " ABORT_MODE ,Abort Mode" "STORE_FIRST,STORE_LAST"
|
|
bitfld.long 0x00 3. " SEG_CHECK_ALL_ENTRIES ,Enable Checking all entries in the MMU" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TLB_ENA ,Enable MMU TLB lookup optimization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEQ_ENA ,Enable MMU sequential access optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BLOCK_MAIN_ENTRY_WR ,Enable writing directly into the active MMU entries" "Disabled,Enabled"
|
|
line.long 0x04 "MMU_CMD_0,MMU CMD 0"
|
|
bitfld.long 0x04 0.--1. " CMD ,Command" "NOP,INIT,COPY_SHADOW,"
|
|
rgroup.long 0xB4++0x0B
|
|
line.long 0x00 "MMU_ABORT_STAT_0,MMU ABORT STAT 0"
|
|
bitfld.long 0x00 21. " PROT ,PROT" "FALSE,TRUE"
|
|
bitfld.long 0x00 20. " SEQ ,SEQ" "FALSE,TRUE"
|
|
bitfld.long 0x00 18.--19. " SIZE ,SIZE" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " TYPE ,TYPE" "EXE,RD,WR,"
|
|
textline " "
|
|
bitfld.long 0x00 4.--8. " ENTRY ,ENTRY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 3. " OVERLAP ,OVERLAP" "FALSE,TRUE"
|
|
bitfld.long 0x00 0.--2. " UNIT ,UNIT" "NONE,CACHE,SEQ,TLB,SEG,FALLBACK,?..."
|
|
line.long 0x04 "MMU_ABORT_ADDR_0,MMU ABORT ADDRESS 0"
|
|
line.long 0x08 "MMU_ACTIVE_ENTRIES_0_0,MMU ACTIVE ENTRIES 00"
|
|
width 8.
|
|
tree "MMU Shadow Entries"
|
|
group.long 0x400++0x0B "Shadow Entry 0"
|
|
line.long 0x00 "WORD_0,Shadow Entry 0 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 0 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 0 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x410++0x0B "Shadow Entry 1"
|
|
line.long 0x00 "WORD_0,Shadow Entry 1 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 1 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 1 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x420++0x0B "Shadow Entry 2"
|
|
line.long 0x00 "WORD_0,Shadow Entry 2 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 2 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 2 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x430++0x0B "Shadow Entry 3"
|
|
line.long 0x00 "WORD_0,Shadow Entry 3 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 3 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 3 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x440++0x0B "Shadow Entry 4"
|
|
line.long 0x00 "WORD_0,Shadow Entry 4 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 4 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 4 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x450++0x0B "Shadow Entry 5"
|
|
line.long 0x00 "WORD_0,Shadow Entry 5 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 5 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 5 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x460++0x0B "Shadow Entry 6"
|
|
line.long 0x00 "WORD_0,Shadow Entry 6 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 6 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 6 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x470++0x0B "Shadow Entry 7"
|
|
line.long 0x00 "WORD_0,Shadow Entry 7 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 7 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 7 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x480++0x0B "Shadow Entry 8"
|
|
line.long 0x00 "WORD_0,Shadow Entry 8 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 8 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 8 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x490++0x0B "Shadow Entry 9"
|
|
line.long 0x00 "WORD_0,Shadow Entry 9 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 9 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 9 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x4A0++0x0B "Shadow Entry 10"
|
|
line.long 0x00 "WORD_0,Shadow Entry 10 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 10 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 10 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x4B0++0x0B "Shadow Entry 11"
|
|
line.long 0x00 "WORD_0,Shadow Entry 11 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 11 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 11 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x4C0++0x0B "Shadow Entry 12"
|
|
line.long 0x00 "WORD_0,Shadow Entry 12 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 12 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 12 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x4D0++0x0B "Shadow Entry 13"
|
|
line.long 0x00 "WORD_0,Shadow Entry 13 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 13 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 13 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x4E0++0x0B "Shadow Entry 14"
|
|
line.long 0x00 "WORD_0,Shadow Entry 14 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 14 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 14 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x4F0++0x0B "Shadow Entry 15"
|
|
line.long 0x00 "WORD_0,Shadow Entry 15 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 15 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 15 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x500++0x0B "Shadow Entry 16"
|
|
line.long 0x00 "WORD_0,Shadow Entry 16 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 16 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 16 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x510++0x0B "Shadow Entry 17"
|
|
line.long 0x00 "WORD_0,Shadow Entry 17 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 17 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 17 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x520++0x0B "Shadow Entry 18"
|
|
line.long 0x00 "WORD_0,Shadow Entry 18 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 18 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 18 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x530++0x0B "Shadow Entry 19"
|
|
line.long 0x00 "WORD_0,Shadow Entry 19 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 19 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 19 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x540++0x0B "Shadow Entry 20"
|
|
line.long 0x00 "WORD_0,Shadow Entry 20 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 20 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 20 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x550++0x0B "Shadow Entry 21"
|
|
line.long 0x00 "WORD_0,Shadow Entry 21 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 21 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 21 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x560++0x0B "Shadow Entry 22"
|
|
line.long 0x00 "WORD_0,Shadow Entry 22 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 22 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 22 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x570++0x0B "Shadow Entry 23"
|
|
line.long 0x00 "WORD_0,Shadow Entry 23 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 23 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 23 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x580++0x0B "Shadow Entry 24"
|
|
line.long 0x00 "WORD_0,Shadow Entry 24 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 24 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 24 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x590++0x0B "Shadow Entry 25"
|
|
line.long 0x00 "WORD_0,Shadow Entry 25 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 25 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 25 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x5A0++0x0B "Shadow Entry 26"
|
|
line.long 0x00 "WORD_0,Shadow Entry 26 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 26 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 26 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x5B0++0x0B "Shadow Entry 27"
|
|
line.long 0x00 "WORD_0,Shadow Entry 27 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 27 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 27 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x5C0++0x0B "Shadow Entry 28"
|
|
line.long 0x00 "WORD_0,Shadow Entry 28 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 28 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 28 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x5D0++0x0B "Shadow Entry 29"
|
|
line.long 0x00 "WORD_0,Shadow Entry 29 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 29 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 29 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x5E0++0x0B "Shadow Entry 30"
|
|
line.long 0x00 "WORD_0,Shadow Entry 30 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 30 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 30 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x5F0++0x0B "Shadow Entry 31"
|
|
line.long 0x00 "WORD_0,Shadow Entry 31 Word 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "WORD_1,Shadow Entry 31 Word 1"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "WORD_2,Shadow Entry 31 Word 2"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
tree.end
|
|
width 10.
|
|
tree "MMU Main Entries"
|
|
group.long 0x800++0x0B "Main Entry 0"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 0 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 0 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 0 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x810++0x0B "Main Entry 1"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 1 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 1 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 1 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x820++0x0B "Main Entry 2"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 2 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 2 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 2 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x830++0x0B "Main Entry 3"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 3 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 3 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 3 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x840++0x0B "Main Entry 4"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 4 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 4 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 4 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x850++0x0B "Main Entry 5"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 5 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 5 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 5 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x860++0x0B "Main Entry 6"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 6 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 6 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 6 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x870++0x0B "Main Entry 7"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 7 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 7 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 7 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x880++0x0B "Main Entry 8"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 8 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 8 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 8 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x890++0x0B "Main Entry 9"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 9 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 9 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 9 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x8A0++0x0B "Main Entry 10"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 10 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 10 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 10 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x8B0++0x0B "Main Entry 11"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 11 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 11 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 11 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x8C0++0x0B "Main Entry 12"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 12 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 12 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 12 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x8D0++0x0B "Main Entry 13"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 13 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 13 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 13 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x8E0++0x0B "Main Entry 14"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 14 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 14 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 14 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x8F0++0x0B "Main Entry 15"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 15 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 15 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 15 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x900++0x0B "Main Entry 16"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 16 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 16 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 16 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x910++0x0B "Main Entry 17"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 17 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 17 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 17 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x920++0x0B "Main Entry 18"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 18 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 18 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 18 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x930++0x0B "Main Entry 19"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 19 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 19 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 19 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x940++0x0B "Main Entry 20"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 20 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 20 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 20 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x950++0x0B "Main Entry 21"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 21 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 21 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 21 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x960++0x0B "Main Entry 22"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 22 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 22 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 22 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x970++0x0B "Main Entry 23"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 23 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 23 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 23 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x980++0x0B "Main Entry 24"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 24 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 24 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 24 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x990++0x0B "Main Entry 25"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 25 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 25 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 25 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x9A0++0x0B "Main Entry 26"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 26 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 26 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 26 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x9B0++0x0B "Main Entry 27"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 27 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 27 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 27 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x9C0++0x0B "Main Entry 28"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 28 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 28 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 28 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x9D0++0x0B "Main Entry 29"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 29 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 29 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 29 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x9E0++0x0B "Main Entry 30"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 30 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 30 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 30 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
group.long 0x9F0++0x0B "Main Entry 31"
|
|
line.long 0x00 "MIN_ADDR,Main Entry 31 Word 0 (Max Address)"
|
|
hexmask.long 0x00 5.--31. 0x20 " MIN_ADDR , MIN_ADDR"
|
|
line.long 0x04 "MAX_ADDR,Main Entry 31 Word 1 (Min Address)"
|
|
hexmask.long 0x04 5.--31. 0x20 " MAX_ADDR , MAX_ADDR"
|
|
line.long 0x08 "CXRW,Main Entry 31 Word 2 (CXRW Attributes)"
|
|
bitfld.long 0x08 3. " WR_ENA ,Enable WR" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RD_ENA , Enable RD" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " EXA_ENE ,Enable EXE" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CASHED ,Enable CASHED" "Disabled,Enabled"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
textline ""
|