35680 lines
2.5 MiB
35680 lines
2.5 MiB
; --------------------------------------------------------------------------------
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; @Title: STM32F0x On-Chip Peripherals
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; @Props: Released
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; @Author: BIC, CNA, KNO, AST, KOL, AJK
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; @Changelog: 2012-06-25
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; 2015-04-15 MKK
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; 2016-06-24 AST
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; 2016-09-30 WIL
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; 2017-10-04 AJK
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; @Manufacturer: STM - ST Microelectronics N.V.
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; @Doc: RM_DM00031936.pdf (rev. 1)
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; DS_DM00047078.pdf (rev. 2)
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; DS_DM00039193.pdf (rev. 1)
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; DM00031936_new.pdf (rev. 7)
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; en.DM00059126.pdf (rev. 3)
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; en.DM00109263.pdf (Rev. 3)
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; en.DM00109264.pdf (rev. 5)
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; en.DM00110868.pdf (Rev. 3)
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; en.DM00115237.pdf (Rev. 3)
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; en.DM00135027.pdf (Rev. 3)
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; en.DM00091010.pdf (Rev. 3)
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; stm32f0RefManual.pdf (Rev. 5)
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; en.DM00031936.pdf (Rev. 9)
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; en.DM00039193.pdf (Rev. 7)
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; en.DM00059126.pdf (Rev. 4)
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; en.DM00088500.pdf (Rev. 3)
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; en.DM00091010.pdf (Rev. 4)
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; en.DM00110868.pdf (Rev. 5)
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; en.DM00141386.pdf (Rev. 3)
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; @Chip: STM32F038C6, STM32F038F6, STM32F038G6, STM32F038K6, STM32F048C6, STM32F048G6,
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; STM32F048T6, STM32F058C8, STM32F058R8, STM32F078CB, STM32F078RB, STM32F078VB,
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; STM32F091CB, STM32F091CC, STM32F091RB, STM32F091RC, STM32F091VB, STM32F091VC,
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; STM32F098CC, STM32F098RC, STM32F050C4, STM32F050C6, STM32F050K4, STM32F050K6,
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; STM32F051C4, STM32F051C6, STM32F051C8, STM32F051K4, STM32F051K6, STM32F051K8,
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; STM32F051R4, STM32F051R6, STM32F051R8, STM32F030C6, STM32F030C8, STM32F030F4,
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; STM32F030K6, STM32F030R8, STM32F031C4, STM32F031C6, STM32F031F4, STM32F031F6,
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; STM32F031G4, STM32F031G6, STM32F031K4, STM32F031K6, STM32F042C4, STM32F042C6,
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; STM32F042F4, STM32F042F6, STM32F042G4, STM32F042G6, STM32F042K4, STM32F042K6,
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; STM32F042T6, STM32F050G6, STM32F071CB, STM32F071RB, STM32F071V8, STM32F071VB,
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; STM32F072C8, STM32F072CB, STM32F072R8, STM32F072RB, STM32F072V8, STM32F072VB,
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; STM32F030CC, STM32F030RC, STM32F031E6, STM32F038E6, STM32F051T8, STM32F058T8,
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; STM32F070C6, STM32F070CB, STM32F070F6, STM32F070RB
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; @Core: Cortex-M0
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perstm32f0x.per 11800 2020-04-06 12:46:45Z apopow $
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;
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; Known problems:
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; --------------------------------------------------------------------------------
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; MODULE REGISTER DESCRIPTION
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; HDMI_CEC CEC_TXDT Lack of TXSTART explanation
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; TIM3 TIMx_BDTR Not described for STM32F030, STM32F030, STM32F070 MCU's
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config 16. 8.
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base ad:0x00
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tree.close "Core Registers (Cortex-M0)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Nested Vectored Interrupt Controller (NVIC)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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tree "Interrupt Enable Registers"
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group.long 0x100++0x03
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line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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tree.end
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tree "Interrupt Pending Registers"
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group.long 0x200++0x03
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line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "EFM (Embedded Flash Memory)"
|
|
base ad:0x40022000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FLASH_ACR,Flash Access Control Register"
|
|
rbitfld.long 0x00 5. " PRFTBS ,Prefetch buffer status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PRFTBE ,Prefetch buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " LATENCY ,Latency" "Zero wait state,One wait state,?..."
|
|
wgroup.long 0x04++0x07
|
|
line.long 0x00 "FLASH_KEYR,FPEC Key Register"
|
|
line.long 0x04 "FLASH_OPTKEYR,Flash OPTKEY Register"
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "FLASH_SR,Flash Status Register"
|
|
eventfld.long 0x00 5. " EOP ,End of operation" "Not asserted,Asserted"
|
|
eventfld.long 0x00 4. " WRPRTERR ,Write protection error" "No error,Error"
|
|
eventfld.long 0x00 2. " PGERR ,Programming error" "No error,Error"
|
|
textline " "
|
|
sif (cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098?C"))||cpuis("STM32F051T8")||cpuis("STM32F031E6")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
rbitfld.long 0x00 0. " BSY ,Busy" "Not busy,Busy"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0. " BSY ,Busy" "Not busy,Busy"
|
|
endif
|
|
line.long 0x04 "FLASH_CR,Flash Control Register"
|
|
bitfld.long 0x04 13. " OBL_LAUNCH ,Force option byte loading" "Not active,Active"
|
|
bitfld.long 0x04 12. " EOPIE ,End of operation interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OPTWRE ,Option bytes write enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " LOCK ,Lock" "Not locked,Locked"
|
|
bitfld.long 0x04 6. " STRT ,Triggers an ERASE operation" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 5. " OPTER ,Option byte erase" "No,Yes"
|
|
bitfld.long 0x04 4. " OPTPG ,Option byte programming" "No,Yes"
|
|
bitfld.long 0x04 2. " MER ,Erase of all user pages" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PER ,Page Erase" "No,Yes"
|
|
bitfld.long 0x04 0. " PG ,Flash programming" "No,Yes"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "FLASH_AR,Flash Address Register"
|
|
rgroup.long 0x1C++0x07
|
|
line.long 0x00 "FLASH_OBR,Option Byte Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA1 ,Data 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA0 ,Data 0"
|
|
textline " "
|
|
sif (cpuis("STM32F04*")||cpuis("STM32F09*"))
|
|
bitfld.long 0x00 15. " BOOT_SEL ,BOOT_SEL" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " RAM_PARITY_CHECK ,RAM_PARITY_CHECK" "Low,High"
|
|
bitfld.long 0x00 13. " VDDA_MONITOR ,VDDA_MONITOR" "Low,High"
|
|
bitfld.long 0x00 12. " NBOOT1 ,NBOOT1" "Low,High"
|
|
textline " "
|
|
sif (cpuis("STM32F04*")||cpuis("STM32F09*"))
|
|
bitfld.long 0x00 11. " nBOOT0 ,nBOOT0" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " NRST_STDBY ,NRST_STDBY" "Low,High"
|
|
bitfld.long 0x00 9. " NRST_STOP ,NRST_STOP" "Low,High"
|
|
bitfld.long 0x00 8. " WDG_SW ,WDG_SW" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " RDPRT ,Read protection level status" "Level 0,Level 1,,Level 2"
|
|
bitfld.long 0x00 0. " OPTERR ,Option byte error" "No error,Error"
|
|
line.long 0x04 "FLASH_WRPR,Write Protection Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " WRP ,Contains the write-protection option bytes loaded by the OBL"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
base ad:0x40023000
|
|
width 10.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CRC_DR, Data Register"
|
|
line.long 0x04 "CRC_IDR, Independent Data Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDR ,General-purpose 8-bit data register bits"
|
|
line.long 0x08 "CRC_CR, Control Register"
|
|
bitfld.long 0x08 7. " REV_OUT ,Reverse output data" "Not affected,Reversed"
|
|
bitfld.long 0x08 5.--6. " REV_IN ,Reverse input data" "Not affected,By byte,By half-word,By word"
|
|
textline " "
|
|
sif ((cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||cpuis("STM32F048?6")||(cpuis("STM32F058?8")&&!cpuis("STM32F058T8"))||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098?C")||cpuis("STM32F071*")||cpuis("STM32F072*")||(cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383VC")||(cpu()=="STM32F378CC")||cpuis("STM32F301*8")||cpuis("STM32F301*6")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F334*4")||cpuis("STM32F334*6")||cpuis("STM32F334*8")||(cpu()=="STM32F358CC")||(cpu()=="STM32F358RC")||(cpu()=="STM32F358VC")||(cpu()=="STM32F378RC")||(cpu()=="STM32F378VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE"))
|
|
bitfld.long 0x08 3.--4. " POLYSIZE ,Polynomial size" "32 bit,16-bit,8-bit,7-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 0. " RESET , Reset CRC bit" "No reset,Reset"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CRC_INIT,Initial CRC Value"
|
|
sif ((cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||cpuis("STM32F048?6")||(cpuis("STM32F058?8")&&!cpuis("STM32F058T8"))||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098?C")||cpuis("STM32F071*")||cpuis("STM32F072*")||(cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||(cpu()=="STM32F378CC")||(cpu()=="STM32F378RC")||(cpu()=="STM32F378VC")||cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F334*4")||cpuis("STM32F334*6")||cpuis("STM32F334*8")||(cpu()=="STM32F358CC")||(cpu()=="STM32F358RC")||(cpu()=="STM32F358VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE"))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CRC_POL,CRC Polynomial"
|
|
elif cpuis("STM32F038E6")||cpuis("STM32F058T8")||cpuis("STM32F051T8")||cpuis("STM32F031E6")
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CRC_POL,CRC Polynomial"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PWR (Power Control Register)"
|
|
base ad:0x40007000
|
|
if ((cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||(cpuis("STM32F058?8")&&!cpuis("STM32F058T8"))||cpuis("STM32F048?6")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*"))
|
|
width 9.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "PWR_CR,Power control register"
|
|
bitfld.long 0x00 8. " DBP ,Disable Backup Domain write protection" "No,Yes"
|
|
bitfld.long 0x00 5.--7. " PLS ,PVD Level Selection" "Threshold 0,Threshold 1,Threshold 2,Threshold 3,Threshold 4,Threshold 5,Threshold 6,Threshold 7"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PVDE ,Power Voltage Detector Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CSBF ,Clear STANDBY Flag" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x00 2. " CWUF ,Clear Wake-up Flag" "No effect,Cleared"
|
|
bitfld.long 0x00 1. " PDDS ,Power Down Deepsleep" "Stop,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LPDS ,Low-Power Deepsleep" "Normal,Low-power"
|
|
line.long 0x04 "PWR_CSR,Power control/status register"
|
|
sif (CPUIS("STM32F078VB")||CPUIS("STM32F091V*"))
|
|
bitfld.long 0x04 15. " EWUP8 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " EWUP7 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " EWUP6 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " EWUP5 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EWUP4 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " EWUP3 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT Ready" "Not ready,Ready"
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif CPUIS("STM32F038?6")||CPUIS("STM32F048?6")||CPUIS("STM32F058?8")
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP1 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " PVDO ,PVD Output" "VDD<PVD threshold,VDD>PVD threshold"
|
|
rbitfld.long 0x04 1. " SBF ,STANDBY Flag" "No standby,Standby"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " WUF ,Wake-Up Flag" "No wake-up,Wake-up"
|
|
textline " "
|
|
elif (CPUIS("STM32F038C6")||CPUIS("STM32F058C8")||CPUIS("STM32F058R8"))
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP1 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT Ready" "Not ready,Ready"
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif (CPUIS("STM32F038F6")||CPUIS("STM32F038G6")||CPUIS("STM32F038K6"))
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP1 pin" "Disabled,Enabled"
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT Ready" "Not ready,Ready"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif CPUIS(("STM32F048C6")||CPUIS("STM32F091R*")||CPUIS("STM32F091C*")||CPUIS("STM32F098CC")||cpuis("STM32F078CB"))
|
|
bitfld.long 0x04 14. " EWUP7 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " EWUP6 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EWUP4 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT Ready" "Not ready,Ready"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif (CPUIS("STM32F048G6")||CPUIS("STM32F048T6"))
|
|
bitfld.long 0x04 13. " EWUP6 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " EWUP4 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT Ready" "Not ready,Ready"
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif CPUIS("STM32F098RC")||cpuis("STM32F078RB")
|
|
bitfld.long 0x04 14. " EWUP7 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " EWUP6 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " EWUP5 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " EWUP4 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT Ready" "Not ready,Ready"
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 9.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "PWR_CR,Power Control Register"
|
|
sif ((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||(cpu()=="STM32F378CC")||(cpu()=="STM32F378RC")||(cpu()=="STM32F378VC"))
|
|
bitfld.long 0x00 11. " ENSD3 ,Enable SDADC3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENSD2 ,Enable SDADC2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ENSD1 ,Enable SDADC1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DBP ,Disable backup domain write protection" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " PLS ,PVD level selection" "Threshold 0,Threshold 1,Threshold 2,Threshold 3,Threshold 4,Threshold 5,Threshold 6,Threshold 7"
|
|
bitfld.long 0x00 4. " PVDE ,Power voltage detector enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 3. " CSBF ,Clear standby flag" "No effect,Cleared"
|
|
eventfld.long 0x00 2. " CWUF ,Clear wake-up flag" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PDDS ,Power down deep-sleep" "Stop,Standby"
|
|
bitfld.long 0x00 0. " LPDS ,Low-power deep-sleep" "Normal,Low-power"
|
|
textline " "
|
|
elif (cpu()=="STM32F030C6"||cpu()=="STM32F030C8"||cpu()=="STM32F030F4"||cpu()=="STM32F030K6"||cpu()=="STM32F030R8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
bitfld.long 0x00 8. " DBP ,Disable RTC domain write protection" "No,Yes"
|
|
eventfld.long 0x00 3. " CSBF ,Clear standby flag" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x00 2. " CWUF ,Clear wake-up flag" "No effect,Cleared"
|
|
bitfld.long 0x00 1. " PDDS ,Power down deep-sleep" "Stop,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LPDS ,Low-power deep-sleep" "Normal,Low-power"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8. " DBP ,Disable backup domain write protection" "No,Yes"
|
|
bitfld.long 0x00 5.--7. " PLS ,PVD level selection" "2.2V,2.3V,2.4V,2.5V,2.6V,2.7V,2.8V,2.9V"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PVDE ,Power voltage detector enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CSBF ,Clear Standby flag" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 2. " CWUF ,Clear wake-up flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " PDDS ,Power down deep-sleep" "Stop,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LPDS ,Low-power deep-sleep" "Normal,Low-power"
|
|
endif
|
|
line.long 0x04 "PWR_CSR,Power Control/Status Register"
|
|
sif ((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC"))
|
|
bitfld.long 0x04 9. " EWUP3 ,Enable WKUP3 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP1 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" "VDD<PVD threshold,VDD>PVD threshold"
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "No standby,Standby"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " WUF ,Wake-up Flag" "No wake-up,Wake-up"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F030RC")||cpuis("STM32F030CC")||cpuis("STM32F070RB")
|
|
bitfld.long 0x04 14. " EWUP7 ,Enable WKUP7 pin" "general purpose I/O,wakeup from Standby"
|
|
bitfld.long 0x04 13. " EWUP6 ,Enable WKUP6 pin" "general purpose I/O,wakeup from Standby"
|
|
bitfld.long 0x04 12. " EWUP5 ,Enable WKUP5 pin" "general purpose I/O,wakeup from Standby"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EWUP4 ,Enable WKUP4 pin" "general purpose I/O,wakeup from Standby"
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "general purpose I/O,wakeup from Standby"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP1 pin" "general purpose I/O,wakeup from Standby"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "No wakeup,Wakeup"
|
|
textline " "
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "general purpose I/O,wakeup from Standby"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP1 pin" "general purpose I/O,wakeup from Standby"
|
|
bitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " WUF ,Wakeup flag" "No wakeup,Wakeup"
|
|
textline " "
|
|
elif cpuis("STM32F301*6")||cpuis("STM32F301*8")
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT ready" "Not ready,Ready"
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F303?E")||cpuis("STM32F303?D")||cpuis("STM32F398?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x04 10. " EWUP3 ,Enable WKUP3 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT ready" "Not ready,Ready"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F302*")||cpuis("STM32F303*")||cpuis("STM32F051?4")||cpuis("STM32F051?6")||(cpuis("STM32F051?8")&&!cpuis("STM32F051T8"))
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif ((cpu()=="STM32F378CC")||(cpu()=="STM32F378RC")||(cpu()=="STM32F378VC"))
|
|
bitfld.long 0x04 10. " EWUP3 ,Enable WKUP3 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT ready" "Not ready,Ready"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("STM32F07*")||cpuis("STM32F091V*"))||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x04 15. " EWUP8 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " EWUP7 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " EWUP6 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " EWUP5 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EWUP4 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " EWUP3 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT ready" "Not ready,Ready"
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpu()=="STM32F030C6"||cpu()=="STM32F030C8"||cpu()=="STM32F030F4"||cpu()=="STM32F030K6"||cpu()=="STM32F030R8")
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP1 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "No standby,Standby"
|
|
rbitfld.long 0x04 0. " WUF ,Wake-up Flag" "No wake-up,Wake-up"
|
|
textline " "
|
|
elif cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"||cpuis("STM32F334*4")||cpuis("STM32F334*6")||cpuis("STM32F334*8")||cpuis("STM32F302**")||cpuis("STM32F303**")||cpuis("STM32F031?4)||cpuis("STM32F031?6)||cpuis("STM32F042?4")||cpuis("STM32F042?6")||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP1 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" "VDD<PVD threshold,VDD>PVD threshold"
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "No standby,Standby"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " WUF ,Wake-up Flag" "No wake-up,Wake-up"
|
|
textline " "
|
|
elif ((cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372V8")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372VB")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F372VC")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373RB")&&(cpu()!="STM32F373VC")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373RC")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F373V8")&&(cpu()!="STM32F373R8")&&(cpu()!="STM32F373VB")&&(cpu()!="STM32F383CC")&&(cpu()!="STM32F383RC")&&(cpu()!="STM32F383VC"))
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP1 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" "VDD<PVD threshold,VDD>PVD threshold"
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "No standby,Standby"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " WUF ,Wake-up Flag" "No wake-up,Wake-up"
|
|
textline " "
|
|
elif (cpuis("STM32F038C6")||cpuis("STM32F058C8")||cpuis("STM32F058R8"))
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP1 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT ready" "Not ready,Ready"
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("STM32F038F6")||cpuis("STM32F038G6")||cpuis("STM32F038K6"))
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP1 pin" "Disabled,Enabled"
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT ready" "Not ready,Ready"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis(("STM32F048C6")||cpuis("STM32F091R*")||cpuis("STM32F091C*")||cpuis("STM32F098CC"))
|
|
bitfld.long 0x04 14. " EWUP7 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " EWUP6 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EWUP4 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT ready" "Not ready,Ready"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("STM32F048G6")||cpuis("STM32F048T6"))
|
|
bitfld.long 0x04 13. " EWUP6 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " EWUP4 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT ready" "Not ready,Ready"
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F098RC")
|
|
bitfld.long 0x04 14. " EWUP7 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " EWUP6 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " EWUP5 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " EWUP4 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT ready" "Not ready,Ready"
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
sif (cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F031?4")||cpuis("STM32F031?6")||cpuis("STM32F052?4")||cpuis("STM32F052?6")||cpuis("STM32F071?B")||cpuis("STM32F071?8")||cpuis("STM32F072?8")||cpuis("STM32F072?B")||cpuis("STM32F050*")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB"))
|
|
tree "RCC (Reset and Clock Control)"
|
|
base ad:0x40021000
|
|
width 14.
|
|
if (((per.l(ad:0x40021000))&0x1000000)==0x0)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RCC_CR,Clock Control Register"
|
|
rbitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CSSON ,Clock security system enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " HSEBYP ,External high speed clock bypass" "Not bypassed,Bypassed"
|
|
rbitfld.long 0x00 17. " HSERDY ,External high speed clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " HSEON ,External high speed clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " HSICAL ,Internal high speed clock calibration"
|
|
bitfld.long 0x00 3.--7. " HSITRIM ,Internal high speed clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 1. " HSIRDY ,Internal high speed clock ready flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HSION ,Internal high speed clock enable" "Disabled,Enabled"
|
|
sif (cpuis("STM32F050*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RCC_CFGR,Clock Configuration Register"
|
|
bitfld.long 0x00 24.--26. " MCO ,Microcontroller clock output" "Disabled,,,HSI14,SYSCLK,HSI,HSE,PLL/2"
|
|
bitfld.long 0x00 18.--21. " PLLMUL ,PLL multiplication factor" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,16"
|
|
bitfld.long 0x00 17. " PLLXTPRE ,HSE divider for PLL entry" "HSE,HSE/2"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PLLSRC ,PLL entry clock source" "HSI/2,HSI/PREDIV"
|
|
bitfld.long 0x00 14. " ADCPRE ,ADC prescaler" "PLCK2/2,PLCK2/4"
|
|
bitfld.long 0x00 8.--10. " PPRE1 ,APB low speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HPRE ,AHB prescaler" "SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK/2,SYSCLK/4,SYSCLK/8,SYSCLK/16,SYSCLK/64,SYSCLK/128,SYSCLK/256,SYSCLK/512"
|
|
rbitfld.long 0x00 2.--3. " SWS ,System clock switch status" "HSI,HSE,PLL,Not applicable"
|
|
bitfld.long 0x00 0.--1. " SW ,System clock switch" "HSI,HSE,PLL,?..."
|
|
elif cpuis("STM32F058T8")||cpuis("STM32F051T8")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RCC_CFGR,Clock Configuration Register"
|
|
bitfld.long 0x00 31. " PLLNODIV ,Divider by 2 for PLL connection to MCO" "Enabled,Disabled"
|
|
bitfld.long 0x00 28.--30. " MCOPRE ,Microcontroller clock output prescaler" "1,2,4,8,16,32,64,128"
|
|
bitfld.long 0x00 24.--27. " MCO ,Microcontroller clock output" "Disabled,HSI14,LSI,LSE,SYSCLK,HSI,HSE,PLL,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18.--21. " PLLMUL ,PLL multiplication factor" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,16"
|
|
bitfld.long 0x00 17. " PLLXTPRE ,HSE divider for PLL entry" "HSE,HSE/2"
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
textline " "
|
|
bitfld.long 0x00 15.--16. " PLLSRC ,PLL entry clock source" ",HSI/PREDIV,HSE/PREDIV,?..."
|
|
textline " "
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 16. " PLLSRC ,PLL entry clock source" "HSI/2,HSI/PREDIV"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " ADCPRE ,ADC prescaler" "PLCK2/2,PLCK2/4"
|
|
bitfld.long 0x00 8.--10. " PPRE1 ,APB low speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HPRE ,AHB prescaler" "SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK/2,SYSCLK/4,SYSCLK/8,SYSCLK/16,SYSCLK/64,SYSCLK/128,SYSCLK/256,SYSCLK/512"
|
|
rbitfld.long 0x00 2.--3. " SWS ,System clock switch status" "HSI,HSE,PLL,?..."
|
|
bitfld.long 0x00 0.--1. " SW ,System clock switch" "HSI,HSE,PLL,?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RCC_CFGR,Clock Configuration Register"
|
|
bitfld.long 0x00 31. " PLLNODIV ,Divider by 2 for PLL connection to MCO" "Enabled,Disabled"
|
|
bitfld.long 0x00 28.--30. " MCOPRE ,Microcontroller clock output prescaler" "1,2,4,8,16,32,64,128"
|
|
bitfld.long 0x00 24.--27. " MCO ,Microcontroller clock output" "Disabled,HSI14,LSI,LSE,SYSCLK,HSI,HSE,PLL,HSI48,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18.--21. " PLLMUL ,PLL multiplication factor" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,16"
|
|
bitfld.long 0x00 17. " PLLXTPRE ,HSE divider for PLL entry" "HSE,HSE/2"
|
|
bitfld.long 0x00 15.--16. " PLLSRC ,PLL entry clock source" "HSI/2,HSI/PREDIV,HSE/PREDIV,HSI48/PREDIV"
|
|
textline " "
|
|
bitfld.long 0x00 14. " ADCPRE ,ADC prescaler" "PLCK2/2,PLCK2/4"
|
|
bitfld.long 0x00 8.--10. " PPRE1 ,APB low speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
bitfld.long 0x00 4.--7. " HPRE ,AHB prescaler" "SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK/2,SYSCLK/4,SYSCLK/8,SYSCLK/16,SYSCLK/64,SYSCLK/128,SYSCLK/256,SYSCLK/512"
|
|
textline " "
|
|
sif (cpuis("STM32F038*")||cpuis("STM32F058*"))
|
|
rbitfld.long 0x00 2.--3. " SWS ,System clock switch status" "HSI,HSE,PLL,?..."
|
|
bitfld.long 0x00 0.--1. " SW ,System clock switch" "HSI,HSE,PLL,?..."
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 2.--3. " SWS ,System clock switch status" "HSI,HSE,PLL,Not applicable"
|
|
bitfld.long 0x00 0.--1. " SW ,System clock switch" "HSI,HSE,PLL,HSI48"
|
|
endif
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RCC_CR,Clock Control Register"
|
|
rbitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CSSON ,Clock security system enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " HSEBYP ,External high speed clock bypass" "Not bypassed,Bypassed"
|
|
rbitfld.long 0x00 17. " HSERDY ,External high speed clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " HSEON ,External high speed clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " HSICAL ,Internal high speed clock calibration"
|
|
bitfld.long 0x00 3.--7. " HSITRIM ,Internal high speed clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 1. " HSIRDY ,Internal high speed clock ready flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HSION ,Internal high speed clock enable" "Disabled,Enabled"
|
|
sif (cpuis("STM32F050*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RCC_CFGR,Clock Configuration Register"
|
|
bitfld.long 0x00 24.--26. " MCO ,Microcontroller clock output" "Disabled,,,HSI14,SYSCLK,HSI,HSE,PLL/2"
|
|
bitfld.long 0x00 18.--21. " PLLMUL ,PLL multiplication factor" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,16"
|
|
bitfld.long 0x00 17. " PLLXTPRE ,HSE divider for PLL entry" "HSE,HSE/2"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PLLSRC ,PLL entry clock source" "HSI/2,HSI/PREDIV"
|
|
bitfld.long 0x00 14. " ADCPRE ,ADC prescaler" "PLCK2/2,PLCK2/4"
|
|
bitfld.long 0x00 8.--10. " PPRE1 ,APB low speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HPRE ,AHB prescaler" "SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK/2,SYSCLK/4,SYSCLK/8,SYSCLK/16,SYSCLK/64,SYSCLK/128,SYSCLK/256,SYSCLK/512"
|
|
rbitfld.long 0x00 2.--3. " SWS ,System clock switch status" "HSI,HSE,PLL,Not applicable"
|
|
bitfld.long 0x00 0.--1. " SW ,System clock switch" "HSI,HSE,PLL,?..."
|
|
elif cpuis("STM32F058T8")||cpuis("STM32F051T8")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RCC_CFGR,Clock Configuration Register"
|
|
bitfld.long 0x00 31. " PLLNODIV ,Divider by 2 for PLL connection to MCO" "Enabled,Disabled"
|
|
bitfld.long 0x00 28.--30. " MCOPRE ,Microcontroller clock output prescaler" "1,2,4,8,16,32,64,128"
|
|
bitfld.long 0x00 24.--27. " MCO ,Microcontroller clock output" "Disabled,HSI14,LSI,LSE,SYSCLK,HSI,HSE,PLL,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 18.--21. " PLLMUL ,PLL multiplication factor" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,16"
|
|
bitfld.long 0x00 17. " PLLXTPRE ,HSE divider for PLL entry" "HSE,HSE/2"
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
textline " "
|
|
bitfld.long 0x00 15.--16. " PLLSRC ,PLL entry clock source" ",HSI/PREDIV,HSE/PREDIV,?..."
|
|
textline " "
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 16. " PLLSRC ,PLL entry clock source" "HSI/2,HSI/PREDIV"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " ADCPRE ,ADC prescaler" "PLCK2/2,PLCK2/4"
|
|
bitfld.long 0x00 8.--10. " PPRE1 ,APB low speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
bitfld.long 0x00 4.--7. " HPRE ,AHB prescaler" "SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK/2,SYSCLK/4,SYSCLK/8,SYSCLK/16,SYSCLK/64,SYSCLK/128,SYSCLK/256,SYSCLK/512"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--3. " SWS ,System clock switch status" "HSI,HSE,PLL,?..."
|
|
bitfld.long 0x00 0.--1. " SW ,System clock switch" "HSI,HSE,PLL,?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RCC_CFGR,Clock Configuration Register"
|
|
bitfld.long 0x00 31. " PLLNODIV ,Divider by 2 for PLL connection to MCO" "Enabled,Disabled"
|
|
bitfld.long 0x00 28.--30. " MCOPRE ,Microcontroller clock output prescaler" "1,2,4,8,16,32,64,128"
|
|
bitfld.long 0x00 24.--27. " MCO ,Microcontroller clock output" "Disabled,HSI14,LSI,LSE,SYSCLK,HSI,HSE,PLL,HSI48,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 18.--21. " PLLMUL ,PLL multiplication factor" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,16"
|
|
bitfld.long 0x00 17. " PLLXTPRE ,HSE divider for PLL entry" "HSE,HSE/2"
|
|
textline " "
|
|
sif (cpuis("STM32F04*")||cpuis("STM32F07*")||cpuis("STM32F09*"))
|
|
bitfld.long 0x00 15.--16. " PLLSRC ,PLL entry clock source" "HSI/2,HSI/PREDIV,HSE/PREDIV,HSI48/PREDIV"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " ADCPRE ,ADC prescaler" "PLCK2/2,PLCK2/4"
|
|
bitfld.long 0x00 8.--10. " PPRE1 ,APB low speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
bitfld.long 0x00 4.--7. " HPRE ,AHB prescaler" "SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK/2,SYSCLK/4,SYSCLK/8,SYSCLK/16,SYSCLK/64,SYSCLK/128,SYSCLK/256,SYSCLK/512"
|
|
textline " "
|
|
sif (cpuis("STM32F038*")||cpuis("STM32F058*"))
|
|
rbitfld.long 0x00 2.--3. " SWS ,System clock switch status" "HSI,HSE,PLL,?..."
|
|
bitfld.long 0x00 0.--1. " SW ,System clock switch" "HSI,HSE,PLL,?..."
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 2.--3. " SWS ,System clock switch status" "HSI,HSE,PLL,HSI48"
|
|
bitfld.long 0x00 0.--1. " SW ,System clock switch" "HSI,HSE,PLL,HSI48"
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x08++0x17
|
|
line.long 0x00 "RCC_CIR,Clock Interrupt Register"
|
|
bitfld.long 0x00 23. " CSSC ,Clock security system interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x00 22. " HSI48RDYC ,HSI48 ready interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F038*")||cpuis("STM32F038E6"))&&(!cpuis("STM32F058*")||cpuis("STM32F058T8"))
|
|
bitfld.long 0x00 21. " HSI14RDYC ,HSI 14 MHz ready interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " PLLRDYC ,PLL ready interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " HSERDYC ,HSE ready interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " HSIRDYC ,HSI ready interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " LSERDYC ,LSE ready interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " LSIRDYC ,LSI ready interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
sif (!cpuis("STM32F038*")&&!cpuis("STM32F058*")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F031E6")&&!cpuis("STM32F051T8"))
|
|
bitfld.long 0x00 14. " HSI48RDYIE ,HSI48 ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " HSI14RDYIE ,HSI14 ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PLLRDYIE ,PLL ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " HSERDYIE ,HSE ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HSIRDYIE ,HSI ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LSERDYIE ,LSE ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LSIRDYIE ,LSI ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif ((cpuis("STM32F038?6"))||cpuis("STM32F048?6")||(cpuis("STM32F058?8")))||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098?C")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F051T8")
|
|
rbitfld.long 0x00 7. " CSSF ,Clock security system interrupt flag" "Not secured,Secured"
|
|
textline " "
|
|
sif (!cpuis("STM32F038*")&&!cpuis("STM32F058*"))&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F031E6")&&!cpuis("STM32F051T8")
|
|
rbitfld.long 0x00 6. " HSI48RDYF ,HSI48 ready interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 5. " HSI14RDYF ,HSI14 ready interrupt flag" "Not ready,Ready"
|
|
rbitfld.long 0x00 4. " PLLRDYF ,PLL ready interrupt flag" "Not ready,Ready"
|
|
rbitfld.long 0x00 3. " HSERDYF ,HSE ready interrupt flag" "Not ready,Ready"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " HSIRDYF ,HSI ready interrupt flag" "Not ready,Ready"
|
|
rbitfld.long 0x00 1. " LSERDYF ,LSE ready interrupt flag" "Not ready,Ready"
|
|
rbitfld.long 0x00 0. " LSIRDYF ,LSI ready interrupt flag" "Not ready,Ready"
|
|
else
|
|
bitfld.long 0x00 7. " CSSF ,Clock security system interrupt flag" "Not secured,Secured"
|
|
textline " "
|
|
sif (!cpuis("STM32F038*")&&!cpuis("STM32F058*")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F031E6")&&!cpuis("STM32F051T8"))
|
|
bitfld.long 0x00 6. " HSI48RDYF ,HSI48 ready interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " HSI14RDYF ,HSI14 ready interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x00 4. " PLLRDYF ,PLL ready interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x00 3. " HSERDYF ,HSE ready interrupt flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HSIRDYF ,HSI ready interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x00 1. " LSERDYF ,LSE ready interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " LSIRDYF ,LSI ready interrupt flag" "Not ready,Ready"
|
|
endif
|
|
line.long 0x04 "RCC_APB2RSTR,APB2 Peripheral Reset Register"
|
|
bitfld.long 0x04 22. " DBGMCURST ,Debug MCU reset" "No effect,Reset"
|
|
bitfld.long 0x04 18. " TIM17RST ,TIM17 timer reset" "No effect,Reset"
|
|
bitfld.long 0x04 17. " TIM16RST ,TIM16 timer reset" "No effect,Reset"
|
|
textline " "
|
|
sif (!cpuis("STM32F050*")&&!cpuis("STM32F031*")&&!cpuis("STM32F038*")&&!cpuis("STM32F048*")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070C6"))
|
|
bitfld.long 0x04 16. " TIM15RST ,TIM15 timer reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 14. " USART1RST ,USART1 reset" "No effect,Reset"
|
|
bitfld.long 0x04 12. " SPI1RST ,SPI1 reset" "No effect,Reset"
|
|
bitfld.long 0x04 11. " TIM1RST ,TIM1 Timer reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 9. " ADC1RST ,ADC interface reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpuis("STM32F091*")||cpuis("STM32F098?C"))
|
|
bitfld.long 0x04 7. " USART8RST ,USART8 reset" "No effect,Reset"
|
|
bitfld.long 0x04 6. " USART7RST ,USART7 reset" "No effect,Reset"
|
|
bitfld.long 0x04 5. " USART6RST ,USART6 reset" "No effect,Reset"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x04 5. " USART6RST ,USART6 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0. " SYSCFGCOMPRST ,SYSCFG and COMP reset" "No effect,Reset"
|
|
line.long 0x08 "RCC_APB1RSTR,APB1 Peripheral Reset Register"
|
|
sif (!cpuis("STM32F050*")&&!cpuis("STM32F031*")&&!cpuis("STM32F038*"))&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x08 30. " CECRST ,HDMI CEC reset" "No effect,Reset"
|
|
bitfld.long 0x08 29. " DACRST ,DAC interface reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 28. " PWRRST ,Power interface reset" "No effect,Reset"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x08 27. " CRSRST ,Clock recovery system interface reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x08 25. " CANRST ,CAN interface reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x08 23. " USBRST ,USB interface reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F050*")&&!cpuis("STM32F031*")&&!cpuis("STM32F038*")&&!cpuis("STM32F048*"))&&!cpuis("STM32F070F6")&&!cpuis("STM32F070C6")
|
|
bitfld.long 0x08 22. " I2C2RST ,I2C 2 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 21. " I2C1RST ,I2C 1 reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x08 20. " USART5RST ,USART5 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F070C6")&&!cpuis("STM32F070F6")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x08 19. " USART4RST ,USART4 reset" "No effect,Reset"
|
|
bitfld.long 0x08 18. " USART3RST ,USART3 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")
|
|
bitfld.long 0x08 17. " USART2RST ,USART2 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F050*")&&!cpuis("STM32F031*")&&!cpuis("STM32F038*")&&!cpuis("STM32F048T6")&&!cpuis("STM32F048G6"))&&!cpuis("STM32F070C6")&&!cpuis("STM32F070F6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x08 14. " SPI2RST ,SPI2 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 11. " WWDGRST ,Window watchdog reset" "No effect,Reset"
|
|
bitfld.long 0x08 8. " TIM14RST ,Timer14 reset" "No effect,Reset"
|
|
textline " "
|
|
sif (!cpuis("STM32F038*")&&!cpuis("STM32F048*")&&!cpuis("STM32F058*"))&&!cpuis("STM32F070C6")&&!cpuis("STM32F070F6")&&!cpuis("STM32F031E6")&&!cpuis("STM32F051T8")
|
|
bitfld.long 0x08 5. " TIM7RST ,Timer7 reset" "No effect,Reset"
|
|
bitfld.long 0x08 4. " TIM6RST ,Timer6 reset" "No effect,Reset"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x08 4. " TIM6RST ,Timer6 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 1. " TIM3RST ,Timer3 reset" "No effect,Reset"
|
|
sif !cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")
|
|
textline " "
|
|
bitfld.long 0x08 0. " TIM2RST ,Timer2 reset" "No effect,Reset"
|
|
endif
|
|
line.long 0x0C "RCC_AHBENR,AHB Peripheral Clock Enable Register"
|
|
sif (!cpuis("STM32F038*"))&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F031E6")
|
|
bitfld.long 0x0C 24. " TSCEN ,Touch sensing controller clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F038?6")||cpuis("STM32F058?8")||cpuis("STM32F048?6")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F051T8")
|
|
bitfld.long 0x0C 22. " IOPFEN ,I/O port F clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F078V*")||cpuis("STM32F091V*"))
|
|
bitfld.long 0x0C 21. " IOPEEN ,I/O port E clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F058R8")||cpuis("STM32F078RB")||cpuis("STM32F091R*")||cpuis("STM32F098RC")||cpuis("STM32F078V*")||cpuis("STM32F091V*"))||cpuis("STM32F030RC")||cpuis("STM32F070RB")
|
|
bitfld.long 0x0C 20. " IOPDEN ,I/O port D clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F038C6")||cpuis("STM32F048C6")||cpuis("STM32F048T6")||cpuis("STM32F058C8")||cpuis("STM32F078CB")||cpuis("STM32F091C*")||(cpuis("STM32F058R8")||cpuis("STM32F078RB")||cpuis("STM32F078VB")||cpuis("STM32F091R*")||cpuis("STM32F091V*")||cpuis("STM32F098*")))||cpuis("STM32F058T8")||cpuis("STM32F070RB")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F051T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x0C 19. " IOPCEN ,I/O port C clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x0C 22. " IOPFEN ,I/O port F clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " IOPEEN ,I/O port E clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " IOPDEN ,I/O port D clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " IOPCEN ,I/O port C clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 18. " IOPBEN ,I/O port B clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " IOPAEN ,I/O port A clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " CRCEN ,CRC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " FLITFEN ,FLITF clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRAMEN ,SRAM interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif ((cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||cpuis("STM32F048?6")||(cpuis("STM32F058?8")&&!cpuis("STM32F058T8"))||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098?C"))
|
|
bitfld.long 0x0C 1. " DM2AEN ,DMA clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 0. " DMAEN ,DMA clock enable" "Disabled,Enabled"
|
|
line.long 0x10 "RCC_APB2ENR,APB2 Peripheral Clock Enable Register"
|
|
bitfld.long 0x10 22. " DBGMCUEN ,Debug MCU clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " TIM17EN ,TIM17 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " TIM16EN ,TIM16 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F050*")&&!cpuis("STM32F031*")&&!cpuis("STM32F038*")&&!cpuis("STM32F048*"))&&!cpuis("STM32F070C6")&&!cpuis("STM32F070F6")
|
|
bitfld.long 0x10 16. " TIM15EN ,TIM15 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 14. " USART1EN ,USART1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " SPI1EN ,SPI1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 11. " TIM1EN ,TIM1 Timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " ADCEN ,ADC interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif ((cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||(cpuis("STM32F058?8")&&!cpuis("STM32F058T8"))||cpuis("STM32F078?B")||cpuis("STM32F048?6")||cpuis("STM32F091*")||cpuis("STM32F098?C"))
|
|
bitfld.long 0x10 7. " USART8EN ,USART8 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " USART7EN ,USART7 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " USART6EN ,USART6 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x10 5. " USART6EN ,USART6 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 0. " SYSCFGCOMPEN ,SYSCFG clock enable" "Disabled,Enabled"
|
|
line.long 0x14 "RCC_APB1ENR,APB1 Peripheral Clock Enable Register"
|
|
sif (!cpuis("STM32F050*")&&!cpuis("STM32F031*")&&!cpuis("STM32F038*"))&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x14 30. " CECEN ,HDMI CEC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 29. " DACEN ,DAC interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 28. " PWREN ,Power interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x14 27. " CRSEN ,Clock recovery system interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x14 25. " CANEN ,CAN interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x14 23. " USBEN ,USB interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F050*")&&!cpuis("STM32F031*")&&!(cpuis("STM32F038?6"))&&!cpuis("STM32F048*"))&&!cpuis("STM32F070C6")&&!cpuis("STM32F070F6")
|
|
bitfld.long 0x14 22. " I2C2EN ,I2C 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif ((cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||(cpuis("STM32F058?8")&&!cpuis("STM32F058T8"))||cpuis("STM32F078?B")||cpuis("STM32F048?6")||cpuis("STM32F091*")||cpuis("STM32F098?C"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x14 20. " USART5EN ,USART5 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F070C6")&&!cpuis("STM32F070F6")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x14 19. " USART4EN ,USART4 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " USART3EN ,USART3 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")
|
|
bitfld.long 0x14 17. " USART2EN ,USART2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F050*")&&!cpuis("STM32F031*")&&!cpuis("STM32F038*")&&!cpuis("STM32F048T6")&&!cpuis("STM32F048G6"))&&!cpuis("STM32F070C6")&&!cpuis("STM32F070F6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x14 14. " SPI2EN ,SPI2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 11. " WWDGEN ,Window watchdog clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " TIM14EN ,Timer 14 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F038*")&&!cpuis("STM32F048*")&&!cpuis("STM32F058*"))&&!cpuis("STM32F070F6")&&!cpuis("STM32F070C6")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x14 5. " TIM7EN ,Timer7 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " TIM6EN ,Timer6 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x14 4. " TIM6EN ,Timer6 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 1. " TIM3EN ,Timer3 clock enable" "Disabled,Enabled"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
textline " "
|
|
bitfld.long 0x14 0. " TIM2EN ,Timer2 clock enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40021000+0x20))&0x01)==0x01)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RCC_BDCR,Backup Domain Control Register"
|
|
bitfld.long 0x00 16. " BDRST ,Backup domain software reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSE"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " LSEDRV ,LSE oscillator drive capability" "Lower,Medium low,Medium high,Higher"
|
|
rbitfld.long 0x00 2. " LSEBYP ,External low speed oscillator bypass" "Not bypassed,Bypassed"
|
|
rbitfld.long 0x00 1. " LSERDY ,External low speed oscillator ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LSEON ,External low speed oscillator enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RCC_BDCR,Backup Domain Control Register"
|
|
bitfld.long 0x00 16. " BDRST ,Backup domain software reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSE"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " LSEDRV ,LSE oscillator drive capability" "Lower,Medium low,Medium high,Higher"
|
|
bitfld.long 0x00 2. " LSEBYP ,External low speed oscillator bypass" "Not bypassed,Bypassed"
|
|
rbitfld.long 0x00 1. " LSERDY ,External low speed oscillator ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LSEON ,External low speed oscillator enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x24++0x13
|
|
line.long 0x00 "RCC_CSR,Control/Status Register"
|
|
sif (cpuis("STM32F038?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F048?6")||cpuis("STM32F091*")||cpuis("STM32F098?C"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F051T8")
|
|
rbitfld.long 0x00 31. " LPWRRSTF ,Low-Power reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 30. " WWDGRSTF ,Window watchdog reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 29. " IWDGRSTF ,Independent watchdog reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 28. " SFTRSTF ,Software reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 27. " PORRSTF ,POR/PDR reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 26. " PINRSTF ,PIN reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " OBLRSTF ,Option byte loader reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " RMVF ,Remove reset flag" "Not activated,Reset"
|
|
textline " "
|
|
sif !cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 23. " V18PWRRSTF ,Reset flag of the 1.8 V domain" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 1. " LSIRDY ,Internal low speed oscillator Ready" "Not ready,Ready"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " LPWRRSTF ,Low-Power reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " WWDGRSTF ,Window watchdog reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " IWDGRSTF ,Independent watchdog reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SFTRSTF ,Software reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " PORRSTF ,POR/PDR reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " PINRSTF ,PIN reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OBLRSTF ,Option byte loader reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " RMVF ,Remove reset flag" "Not activated,Reset"
|
|
bitfld.long 0x00 23. " V18PWRRSTF ,Reset flag of the 1.8 V domain" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LSIRDY ,Internal low speed oscillator ready" "Not ready,Ready"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " LSION ,Internal low speed oscillator enable" "Disabled,Enabled"
|
|
line.long 0x04 "RCC_AHBRSTR,AHB Peripheral Reset Register"
|
|
sif (!cpuis("STM32F038*"))&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F031E6")
|
|
bitfld.long 0x04 24. " TSCRST ,Touch sensing controller reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F038?6")||cpuis("STM32F058?8")||cpuis("STM32F048?6")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F051T8")
|
|
bitfld.long 0x04 22. " IOPFRST ,I/O port F reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpuis("STM32F078V*")||cpuis("STM32F091V*"))
|
|
bitfld.long 0x04 21. " IOPERST ,I/O port E reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F058R8")||cpuis("STM32F078RB")||cpuis("STM32F091R*")||cpuis("STM32F098RC")||cpuis("STM32F078V*")||cpuis("STM32F091V*"))||cpuis("STM32F030RC")||cpuis("STM32F070RB")
|
|
bitfld.long 0x04 20. " IOPDRST ,I/O port D reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F038C6")||cpuis("STM32F048C6")||cpuis("STM32F048T6")||cpuis("STM32F058C8")||cpuis("STM32F078CB")||cpuis("STM32F091C*")||(cpuis("STM32F058R8")||cpuis("STM32F078RB")||cpuis("STM32F078VB")||cpuis("STM32F091R*")||cpuis("STM32F091V*")||cpuis("STM32F098*")))||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F051T8")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070RB")||cpuis("STM32F058T8")
|
|
bitfld.long 0x04 19. " IOPCRST ,I/O port C reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x04 22. " IOPFRST ,I/O port F reset" "No effect,Reset"
|
|
bitfld.long 0x04 21. " IOPERST ,I/O port E reset" "No effect,Reset"
|
|
bitfld.long 0x04 20. " IOPDRST ,I/O port D reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 19. " IOPCRST ,I/O port C reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 18. " IOPBRST ,I/O port B reset" "No effect,Reset"
|
|
bitfld.long 0x04 17. " IOPARST ,I/O port A reset" "No effect,Reset"
|
|
line.long 0x08 "RCC_CFGR2,Clock Configuration Register 2"
|
|
bitfld.long 0x08 0.--3. " PREDIV[3:0] ,PREDIV division factor" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
line.long 0x0C "RCC_CFGR3,Clock Configuration Register 3"
|
|
sif ((cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||(cpuis("STM32F058?8")&&!cpuis("STM32F058T8"))||cpuis("STM32F078?B")||cpuis("STM32F048?6")||cpuis("STM32F091*")||cpuis("STM32F098?C"))
|
|
bitfld.long 0x0C 18.--19. " USART3SW[1:0] ,USART3 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x0C 16.--17. " USART2SW[1:0] ,USART2 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 8. " ADCSW ,ADC clock source selection" "HSI14,PLCK"
|
|
textline " "
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
bitfld.long 0x0C 7. " USBSW ,USB clock source selection" "Disabled,PLL"
|
|
textline " "
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x0C 7. " USBSW ,USB clock source selection" "HSI48,PLL"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F050*")&&!cpuis("STM32F031*")&&!cpuis("STM32F038*"))&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x0C 6. " CECSW ,HDMI CEC clock source selection" "HSI,LSE"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 4. " I2C1SW ,I2C1 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x0C 0.--1. " USART1SW[1:0] ,USART1 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
line.long 0x10 "RCC_CR2,Clock Control Register 2"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
hexmask.long.byte 0x10 24.--31. 0x1 " HSI48CAL[7:0] ,HSI48 clock calibration"
|
|
textline " "
|
|
sif (cpuis("STM32F038?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F048?6")||cpuis("STM32F091*")||cpuis("STM32F098?C"))
|
|
rbitfld.long 0x10 17. " HSI48RDY ,HSI48 clock ready flag" "Not ready,Ready"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 17. " HSI48RDY ,HSI48 clock ready flag" "Not ready,Ready"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x10 16. " HSI14ON ,HSI14 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x10 8.--15. 0x1 " HSI14CAL[7:0] ,HSI14 clock calibration"
|
|
textline " "
|
|
bitfld.long 0x10 3.--7. " HSI14TRIM[4:0] ,HSI14 clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 2. " HSI14DIS ,HSI14 clock request from ADC disable" "No,Yes"
|
|
textline " "
|
|
sif (cpuis("STM32F038?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F048?6")||cpuis("STM32F091*")||cpuis("STM32F098?C"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F051T8")
|
|
rbitfld.long 0x10 1. " HSI14RDY ,HSI14 clock ready flag" "Not ready,Ready"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 1. " HSI14RDY ,HSI14 clock ready flag" "Not ready,Ready"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 0. " HSI14ON ,HSI14 clock enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "RCC (Reset and Clock Control)"
|
|
base ad:0x40021000
|
|
width 14.
|
|
group.long 0x00++0x37
|
|
line.long 0x00 "RCC_CR,Clock control register"
|
|
bitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Off,On"
|
|
bitfld.long 0x00 19. " CSSON ,Clock Security System enable" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 18. " HSEBYP ,External High Speed clock Bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 17. " HSERDY ,External High Speed clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " HSEON ,External High Speed clock enable" "Off,On"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " HSICAL ,Internal High Speed clock Calibration"
|
|
bitfld.long 0x00 3.--7. " HSITRIM ,Internal High Speed clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 1. " HSIRDY ,Internal High Speed clock ready flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HSION ,Internal High Speed clock enable" "Off,On"
|
|
line.long 0x04 "RCC_CFGR,Clock configuration register"
|
|
bitfld.long 0x04 24.--26. " MCO ,Microcontroller Clock Output" "No clock,,,HSI14,SYSCLK,HSI,HSE,PLL/2"
|
|
bitfld.long 0x04 18.--21. " PLLMUL ,PLL Multiplication Factor" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,16"
|
|
bitfld.long 0x04 17. " PLLXTPRE ,HSE divider for PLL entry" "HSE,HSE/2"
|
|
textline " "
|
|
bitfld.long 0x04 16. " PLLSRC ,PLL entry clock source" "HSI/2,HSE"
|
|
bitfld.long 0x04 14. " ADCPRE ,ADC prescaler" "PLCK2/2,PLCK2/4"
|
|
bitfld.long 0x04 8.--10. " PPRE1 ,APB Low speed prescaler" "HCLK,HCLK,HCLK,HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " HPRE ,AHB prescaler" "SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK,SYSCLK/2,SYSCLK/4,SYSCLK/8,SYSCLK/16,SYSCLK/64,SYSCLK/128,SYSCLK/256,SYSCLK/512"
|
|
bitfld.long 0x04 2.--3. " SWS ,System Clock Switch Status" "HSI,HSE,PLL,Not applicable"
|
|
bitfld.long 0x04 0.--1. " SW ,System clock Switch" "HSI,HSE,PLL,Not allowed"
|
|
line.long 0x08 "RCC_CIR,Clock interrupt register"
|
|
bitfld.long 0x08 23. " CSSC ,Clock Security System Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 21. " HSI14RDYC ,HSI 14 MHz Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " PLLRDYC ,PLL Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HSERDYC ,HSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 18. " HSIRDYC ,HSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 17. " LSERDYC ,LSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 16. " LSIRDYC ,LSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 13. " HSI14RDYIE ,HSI14 ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " PLLRDYIE ,PLL Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HSERDYIE ,HSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " HSIRDYIE ,HSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LSERDYIE ,LSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " LSIRDYIE ,LSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " CSSF ,Clock Security System Interrupt flag" "Not secured,Secured"
|
|
bitfld.long 0x08 5. " HSI14RDYF ,HSI14 ready interrupt flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PLLRDYF ,PLL Ready Interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x08 3. " HSERDYF ,HSE Ready Interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x08 2. " HSIRDYF ,HSI Ready Interrupt flag" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 1. " LSERDYF ,LSE Ready Interrupt flag" "Not ready,Ready"
|
|
bitfld.long 0x08 0. " LSIRDYF ,LSI Ready Interrupt flag" "Not ready,Ready"
|
|
line.long 0x0C "RCC_APB2RSTR,APB2 Peripheral reset register"
|
|
bitfld.long 0x0C 22. " DBGMCURST ,Debug MCU reset" "No effect,Reset"
|
|
bitfld.long 0x0C 18. " TIM17RST ,TIM17 timer reset" "No effect,Reset"
|
|
bitfld.long 0x0C 17. " TIM16RST ,TIM16 timer reset" "No effect,Reset"
|
|
textline " "
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")
|
|
bitfld.long 0x0C 16. " TIM15RST ,TIM15 timer reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 14. " USART1RST ,USART1 reset" "No effect,Reset"
|
|
bitfld.long 0x0C 12. " SPI1RST ,SPI 1 reset" "No effect,Reset"
|
|
bitfld.long 0x0C 11. " TIM1RST ,TIM1 Timer reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " ADC1RST ,ADC interface reset" "No effect,Reset"
|
|
bitfld.long 0x0C 0. " SYSCFGCOMPRST ,SYSCFG and COMP reset" "No effect,Reset"
|
|
line.long 0x10 "RCC_APB1RSTR,APB1 Peripheral reset register"
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")
|
|
bitfld.long 0x10 30. " CECRST ,HDMI CEC reset" "No effect,Reset"
|
|
bitfld.long 0x10 29. " DACRST ,DAC interface reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 28. " PWRRST ,Power interface reset" "No effect,Reset"
|
|
textline " "
|
|
sif (CPU()=="STM32F051C8"||CPU()=="STM32F051R8")
|
|
bitfld.long 0x10 22. " I2C2RST ,I2C 2 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 21. " I2C1RST ,I2C 1 reset" "No effect,Reset"
|
|
textline " "
|
|
sif (CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")
|
|
bitfld.long 0x10 17. " USART2RST ,USART 2 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (CPU()=="STM32F051C8"||CPU()=="STM32F051R8")
|
|
bitfld.long 0x10 14. " SPI2RST ,SPI 2 reset" "No effect,Reset"
|
|
bitfld.long 0x10 11. " WWDGRST ,Window Watchdog reset" "No effect,Reset"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x10 11. " WWDGRST ,Window Watchdog reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 8. " TIM14RST ,Timer 14 reset" "No effect,Reset"
|
|
textline " "
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")
|
|
bitfld.long 0x10 4. " TIM6RST ,Timer 6 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 1. " TIM3RST ,Timer 3 reset" "No effect,Reset"
|
|
bitfld.long 0x10 0. " TIM2RST ,Timer 2 reset" "No effect,Reset"
|
|
line.long 0x14 "RCC_AHBENR,AHB Peripheral Clock enable register"
|
|
bitfld.long 0x14 24. " TSCEN ,Touch sensing controller clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " IOPFEN ,I/O port F clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")
|
|
bitfld.long 0x14 20. " IOPDEN ,I/O port D clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8")
|
|
bitfld.long 0x14 19. " IOPCEN ,I/O port C clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 18. " IOPBEN ,I/O port B clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 17. " IOPAEN ,I/O port A clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " CRCEN ,CRC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " FLITFEN ,FLITF clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRAMEN ,SRAM interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " DMAEN ,DMA clock enable" "Disabled,Enabled"
|
|
line.long 0x18 "RCC_APB2ENR,APB2 Peripheral Clock enable register"
|
|
bitfld.long 0x18 22. " DBGMCUEN ,Debug MCU clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " TIM17EN ,TIM17 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " TIM16EN ,TIM16 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")
|
|
bitfld.long 0x18 16. " TIM15EN ,TIM15 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 14. " USART1EN ,USART1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 12. " SPI1EN ,SPI 1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " TIM1EN ,TIM1 Timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " ADC1EN ,ADC interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " SYSCFGCOMPEN ,SYSCFG clock enable" "Disabled,Enabled"
|
|
line.long 0x1C "RCC_APB1ENR,APB1 Peripheral Clock enable register"
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")
|
|
bitfld.long 0x1C 30. " CECEN ,HDMI CEC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 29. " DACEN ,DAC interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 28. " PWREN ,Power interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (CPU()=="STM32F051C8"||CPU()=="STM32F051K8"||CPU()=="STM32F051R8")
|
|
bitfld.long 0x1C 22. " I2C2EN ,I2C 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")
|
|
bitfld.long 0x1C 17. " USART2EN ,USART 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (CPU()=="STM32F051C8"||CPU()=="STM32F051K8"||CPU()=="STM32F051R8")
|
|
bitfld.long 0x1C 14. " SPI2EN ,SPI 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 11. " WWDGEN ,Window Watchdog clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x1C 11. " WWDGEN ,Window Watchdog clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 8. " TIM14EN ,Timer 14 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")
|
|
bitfld.long 0x1C 4. " TIM6EN ,Timer 6 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 1. " TIM3EN ,Timer 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " TIM2EN ,Timer 2 clock enable" "Disabled,Enabled"
|
|
line.long 0x20 "RCC_BDCR,Backup domain control register"
|
|
bitfld.long 0x20 16. " BDRST ,Backup domain software reset" "No reset,Reset"
|
|
bitfld.long 0x20 15. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSE"
|
|
textline " "
|
|
bitfld.long 0x20 3.--4. " LSEDRV ,LSE oscillator drive capability" "Lower,Medium low,Medium high,Higher"
|
|
bitfld.long 0x20 2. " LSEBYP ,External Low Speed oscillator Bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x20 1. " LSERDY ,External Low Speed oscillator Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x20 0. " LSEON ,External Low Speed oscillator enable" "Off,On"
|
|
line.long 0x24 "RCC_CSR,Control/status register"
|
|
bitfld.long 0x24 31. " LPWRRSTF ,Low-Power reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 30. " WWDGRSTF ,Window watchdog reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 29. " IWDGRSTF ,Independent Watchdog reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 28. " SFTRSTF ,Software Reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 27. " PORRSTF ,POR/PDR reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 26. " PINRSTF ,PIN reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 25. " OBLRSTF ,Option byte loader reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 24. " RMVF ,Remove reset flag" "Not activated,Reset"
|
|
bitfld.long 0x24 1. " LSIRDY ,Internal Low Speed oscillator Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x24 0. " LSION ,Internal Low Speed oscillator enable" "Off,On"
|
|
line.long 0x28 "RCC_AHBRSTR,AHB peripheral reset register"
|
|
bitfld.long 0x28 24. " TSCRST ,Touch sensing controller reset" "No effect,Reset"
|
|
bitfld.long 0x28 22. " IOPFRST ,I/O port F reset" "No effect,Reset"
|
|
textline " "
|
|
sif (CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")
|
|
bitfld.long 0x28 20. " IOPDRST ,I/O port D reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8")
|
|
bitfld.long 0x28 19. " IOPCRST ,I/O port C reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 18. " IOPBRST ,I/O port B reset" "No effect,Reset"
|
|
bitfld.long 0x28 17. " IOPARST ,I/O port A reset" "No effect,Reset"
|
|
line.long 0x2C "RCC_CFGR2,Clock configuration register 2"
|
|
bitfld.long 0x2C 0.--3. " PREDIV[3:0] ,PREDIV division factor" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
line.long 0x30 "RCC_CFGR3,Clock configuration register 3"
|
|
bitfld.long 0x30 8. " ADCSW ,ADC clock source selection" "HSI14,PLCK"
|
|
textline " "
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")
|
|
bitfld.long 0x30 6. " CECSW ,HDMI CEC clock source selection" "HSI,LSE"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x30 4. " I2C1SW ,I2C1 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x30 0.--1. " USART1SW[1:0] ,USART1 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
line.long 0x34 "RCC_CR2,Clock control register 2"
|
|
hexmask.long.byte 0x34 8.--15. 1. " HSI14CAL[7:0] ,HSI14 clock calibration"
|
|
bitfld.long 0x34 3.--7. " HSI14TRIM[4:0] ,HSI14 clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x34 2. " HSI14DIS ,HSI14 clock request from ADC disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x34 1. " HSI14RDY ,HSI14 clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x34 0. " HSI14ON ,HSI14 clock enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F091?C"))||(cpuis("STM32F098?C"))
|
|
tree "CRS (Clock recovery system)"
|
|
base ad:0x40006C00
|
|
width 14.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRS_CR,CRS Control Register"
|
|
sif (!CPUIS("STM32F038*")&&!CPUIS("STM32F058*"))
|
|
hexmask.long.byte 0x00 8.--13. 0x01 " TRIM[5:0] ,HSI48 oscillator smooth trimming"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " SWSYNC ,Generate software SYNC event" "Not occurred,Occurred"
|
|
textline " "
|
|
sif (!CPUIS("STM32F038*")&&!CPUIS("STM32F058*"))
|
|
bitfld.long 0x00 6. " AUTOTRIMEN ,Automatic trimming enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " CEN ,Frequency error counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ESYNCIE ,Expected SYNC interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ERRIE ,Synchronization or trimming error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SYNCWARNIE ,SYNC warning interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SYNCOKIE ,SYNC event OK interrupt enable" "Disabled,Enabled"
|
|
sif (CPUIS("STM32F048?6"))||(CPUIS("STM32F078?B"))||(CPUIS("STM32F091?B"))||(CPUIS("STM32F091?C"))||(CPUIS("STM32F098?C"))||(CPUIS("STM32L0?2*"))||(CPUIS("STM32L0?3*"))||(cpuis("STM32H743*")||cpuis("STM32H753*"))
|
|
if (((per.l(ad:0x40006C00))&0x20)==0x20)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRS_CFGR,CRS Configuration Register"
|
|
bitfld.long 0x00 31. " SYNCPOL ,SYNC polarity selection" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 28.--29. " SYNCSRC ,SYNC signal source selection" "GPIO,LSE,USB SOF,?..."
|
|
bitfld.long 0x00 24.--26. " SYNCDIV ,SYNC divider" "Not divided,/2,/4,/8,/16,/32,/64,/128"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " FELIM[7:0] ,Frequency error limit"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 0x01 " RELOAD[15:0] ,Counter reload value"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CRS_CFGR,CRS Configuration Register"
|
|
bitfld.long 0x00 31. " SYNCPOL ,SYNC polarity selection" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 28.--29. " SYNCSRC ,SYNC signal source selection" "GPIO,LSE,USB SOF,?..."
|
|
bitfld.long 0x00 24.--26. " SYNCDIV ,SYNC divider" "Not divided,/2,/4,/8,/16,/32,/64,/128"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " FELIM[7:0] ,Frequency error limit"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 0x01 " RELOAD[15:0] ,Counter reload value"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRS_CFGR,CRS Configuration Register"
|
|
bitfld.long 0x00 31. " SYNCPOL ,SYNC polarity selection" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 28.--29. " SYNCSRC ,SYNC signal source selection" "GPIO,LSE,USB SOF,?..."
|
|
bitfld.long 0x00 24.--26. " SYNCDIV ,SYNC divider" "Not divided,/2,/4,/8,/16,/32,/64,/128"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " FELIM[7:0] ,Frequency error limit"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 0x01 " RELOAD[15:0] ,Counter reload value"
|
|
endif
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CRS_ISR,CRS Interrupt And Status Register"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " FECAP[15:0] ,Frequency error capture"
|
|
bitfld.long 0x00 15. " FEDIR ,Frequency error direction" "Upcounting,Downcounting"
|
|
bitfld.long 0x00 10. " TRIMOVF ,Trimming overflow or underflow" "Not detected,Detected"
|
|
bitfld.long 0x00 9. " SYNCMISS ,SYNC missed" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SYNCERR ,SYNC error" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " ESYNCF ,Expected SYNC flag" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " ERRF ,Error flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " SYNCWARNF ,SYNC warning flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SYNCOKF ,SYNC event OK flag" "Not detected,Detected"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CRS_ICR,CRS Interrupt Flag Clear Register"
|
|
bitfld.long 0x00 3. " ESYNCC ,Expected SYNC clear flag" "Not affected,Cleared"
|
|
bitfld.long 0x00 2. " ERRC ,Error clear flag" "Not affected,Cleared"
|
|
bitfld.long 0x00 1. " SYNCWARNC ,SYNC warning clear flag" "Not affected,Cleared"
|
|
bitfld.long 0x00 0. " SYNCOKC ,SYNC event OK clear flag" "Not affected,Cleared"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "GPIO (General-Purpose I/O)"
|
|
sif (cpuis("STM32F030?4")||cpuis("STM32F030?6")||cpuis("STM32F030?8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070RB")||cpuis("STM32F070F6"))
|
|
tree "GPIO A"
|
|
base ad:0x48000000
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOA_MODER,GPIO port A mode register"
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOA_OTYPER,GPIO port A mode register"
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x04 15. " OT15 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 14. " OT14 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x04 8. " OT8 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 7. " OT7 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOA_OSPEEDR,GPIO port A output speed register"
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOA_PUPDR,GPIO port A pull-up/pull-down register"
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOA_IDR,GPIO port A input data register"
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x00 15. " IDR15 ,Port A input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " IDR14 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port A input data" "Low,High"
|
|
textline " "
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x00 8. " IDR8 ,Port A input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " IDR7 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port A input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOA_ODR,GPIO port A output data register"
|
|
sif !cpuis("STM32F070F6")
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
sif !cpuis("STM32F070F6")
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port A output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOA_LCKR,GPIO port A configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
textline " "
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x00 15. " LCK15 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " LCK14 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Port A lock bit" "Not locked,Locked"
|
|
sif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,,,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK/I2S1_CK,,TIM2_CH1_ETR,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,,,,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,TIM2_CH4,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",,TIM2_CH3,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,,TIM2_CH2,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",,TIM2_CH1_ETR,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,,TIM2_CH1_ETR,EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDAT,IR_OUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",USART1_TX,TIM1_CH2,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO,TIM3_CH1,TIM1_BKIN,,USART3_CTS,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS,USART2_CK,,,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TIM15_CH2,USART2_RX,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "TIM15_CH1,USART2_TX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,,,USART4_RX,TIM15_CH1N,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,,,USART4_TX,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS,USART2_RX,,EVENTOUT,USART4_RTS,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,USB_NOE,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,,I2C1_SDA,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" "TIM15_BKIN,USART1_TX,TIM1_CH2,,I2C1_SCL,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
elif cpuis("STM32F070C6")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO,TIM3_CH1,TIM1_BKIN,,,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS,USART2_CK,USB_NOE,,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",USART2_RX,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",USART2_TX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,USB_NOE,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,,I2C1_SDA,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",USART1_TX,TIM1_CH2,,I2C1_SCL,?..."
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO,TIM3_CH1,TIM1_BKIN,,USART3_CTS,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK,,,,,USART6_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS,USART2_CK,,,TIM14_CH1,USART6_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TIM15_CH1N,USART2_RX,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "TIM15_CH1,USART2_TX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,,,USART4_RX,TIM15_CH1N,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,,,USART4_TX,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS,USART2_RX,,EVENTOUT,USART4_RTS,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,,,I2C_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,,,I2C_SCL,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,,I2C1_SDA,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" "TIM15_BKIN,USART1_TX,TIM1_CH2,,I2C1_SCL,MCO,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
elif cpuis("STM32F030C8")||cpuis("STM32F030R8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO,TIM3_CH1,TIM1_BKIN,,,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS,USART2_CK,,,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TIM15_CH1N,USART2_RX,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "TIM15_CH1,USART2_TX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS,USART2_RX,,EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,,,I2C_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,,,I2C_SCL,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" "TIM15_BKIN,USART1_TX,TIM1_CH2,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
elif cpuis("STM32F030C6")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO,TIM3_CH1,TIM1_BKIN,,,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS,USART1_CK,,,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",USART1_RX,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",USART1_TX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART1_RTS,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART1_CTS,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS,USART1_RX,,EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART1_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,,,I2C_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,,,I2C_SCL,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,,I2C1_SDA,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",USART1_TX,TIM1_CH2,,I2C1_SCL,,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
elif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")||cpuis("STM32F038?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,TSC_G2_IO4,TIM14_CH1,TIM17_CH1,EVENTOUT,COMP2_OUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,TSC_G2_IO3,,TIM16_CH1,EVENTOUT,COMP1_OUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK/I2S1_CK,CEC,TIM2_CH1_ETR,TSC_G2_IO2,?..."
|
|
textline " "
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051R4"||CPU()=="STM32F051K4")||cpuis("STM32F038?6")
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,,,TSC_G2_IO1,TIM14_CH1,?..."
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TIM15_CH2,,TIM2_CH4,TSC_G1_IO4,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "TIM15_CH1,,TIM2_CH3,TSC_G1_IO3,,,,COMP2_OUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,,TIM2_CH2,TSC_G1_IO2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",,TIM2_CH1_ETR,TSC_G1_IO1,,,,COMP1_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,USART2_CK,,TSC_G2_IO1,TIM14_CH1,?..."
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TIM15_CH2,USART2_RX,TIM2_CH4,TSC_G1_IO4,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "TIM15_CH1,USART2_TX,TIM2_CH3,TSC_G1_IO3,,,,COMP2_OUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,TIM2_CH2,TSC_G1_IO2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,TIM2_CH1_ETR,TSC_G1_IO1,,,,COMP1_OUT,?..."
|
|
endif
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051R4"||CPU()=="STM32F051K4")||cpuis("STM32F038?6")
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,,TIM2_CH1_ETR,EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDAT,IR_OUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,TSC_G4_IO4,,,,COMP2_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,USART2_RX,TIM2_CH1_ETR,EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDAT,IR_OUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,TSC_G4_IO4,,,,COMP2_OUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,TSC_G4_IO3,,,,COMP1_OUT,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,TSC_G4_IO2,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" "TIM15_BKIN,USART1_TX,TIM1_CH2,TSC_G4_IO1,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
elif cpuis("STM32F051T8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,TSC_G2_IO4,TIM14_CH1,TIM17_CH1,EVENTOUT,COMP2_OUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,TSC_G2_IO3,,TIM16_CH1,EVENTOUT,COMP1_OUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK/I2S1_CK,CEC,TIM2_CH1_ETR,TSC_G2_IO2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,USART2_CK,,TSC_G2_IO1,TIM14_CH1,?..."
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TIM15_CH2,USART2_RX,TIM2_CH4,TSC_G1_IO4,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "TIM15_CH1,USART2_TX,TIM2_CH3,TSC_G1_IO3,,,,COMP2_OUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,TIM2_CH2,TSC_G1_IO2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,TIM2_CH1_ETR,TSC_G1_IO1,,,,COMP1_OUT,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,USART2_RX,TIM2_CH1_ETR,EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,TSC_G4_IO4,,,,COMP2_OUT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,TSC_G4_IO3,,,,COMP1_OUT,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,TSC_G4_IO2,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" "TIM15_BKIN,USART1_TX,TIM1_CH2,TSC_G4_IO1,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
elif cpuis("STM32F070F6")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO,TIM3_CH1,TIM1_BKIN,,,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS,USART2_CK,USB_NOE,,TIM14_CH1,?..."
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",USART2_RX,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",USART2_TX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS,USART2_RX,,EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,USB_NOE,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,,I2C1_SDA,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",USART1_TX,TIM1_CH2,,I2C1_SCL,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOA_BRR,Port bit reset register"
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x00 15. " BR15 ,Port A reset bit 15" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " BR14 ,Port A reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port A reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port A reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port A reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port A reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port A reset bit 9" "No effect,Reset"
|
|
textline " "
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x00 8. " BR8 ,Port A reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " BR7 ,Port A reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port A reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port A reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port A reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port A reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port A reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port A reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port A reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
sif (CPU()=="STM32F030F4")||cpuis("STM32F070F6")
|
|
tree "GPIO B"
|
|
base ad:0x48000400
|
|
width 16.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOB_MODER,GPIO port B mode register"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOB_OTYPER,GPIO port B mode register"
|
|
bitfld.long 0x04 1. " OT1 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOB_OSPEEDR,GPIO port B output speed register"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOB_PUPDR,GPIO port B pull-up/pull-down register"
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOB_IDR,GPIO port B input data register"
|
|
bitfld.long 0x00 1. " IDR1 ,Port B input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOB_ODR,GPIO port B output data register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port B output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOB_LCKR,GPIO port B configuration lock register"
|
|
bitfld.long 0x00 1. " LCK1 ,Port B lock bit" "Not locked,Locked"
|
|
sif (cpuis("STM32F030?4"))||(cpuis("STM32F030?6"))||(cpuis("STM32F030?8"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOB_BRR,Port bit reset register"
|
|
bitfld.long 0x00 1. " BR1 ,Port B reset bit 1" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
elif CPU()=="STM32F030R8"||CPU()=="STM32F030K6"||cpuis("STM32F030RC")||cpuis("STM32F030CC")||cpuis("STM32F070RB")||cpuis("STM32F070CB")||cpuis("STM32F070C6")||CPU()=="STM32F030C6"||CPU()=="STM32F030C8"
|
|
tree "GPIO B"
|
|
base ad:0x48000400
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOB_MODER,GPIO port B mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOB_OTYPER,GPIO port B mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OT7 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 2. " OT2 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 1. " OT1 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOB_OSPEEDR,GPIO port B output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOB_PUPDR,GPIO port B pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOB_IDR,GPIO port B input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDR2 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IDR1 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port B input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOB_ODR,GPIO port B output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port B output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOB_LCKR,GPIO port B configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LCK2 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Port B lock bit" "Not locked,Locked"
|
|
sif (cpuis("STM32F030?4"))||(cpuis("STM32F030?6"))||(cpuis("STM32F030?8"))||cpuis("STM32F038C6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO,TIM3_CH1,EVENTOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK,EVENTOUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,?..."
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
sif (cpuis("STM32F030?4"))||(cpuis("STM32F030?6"))||cpuis("STM32F038C6")
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" "SPI1_MOSI,,TIM1_CH3N,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" "SPI1_MISO,,TIM1_CH2N,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" "SPI1_SCK,,TIM1_CH1N,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" "SPI1_NSS,EVENTOUT,TIM1_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" "EVENTOUT,I2C1_SDA,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" ",I2C1_SCL,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" "SPI2_MOSI,TIM15_CH2,TIM1_CH3N,TIM15_CH1N,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" "SPI2_MISO,TIM15_CH1,TIM1_CH2N,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" "SPI2_SCK,,TIM1_CH1N,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" "SPI2_NSS,EVENTOUT,TIM1_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" "EVENTOUT,I2C2_SDA,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" ",I2C2_SCL,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "IR_OUT,I2C1_SDA,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",I2C1_SCL,TIM16_CH1,?..."
|
|
elif CPUIS("STM32F070C6")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO,TIM3_CH1,EVENTOUT,,,TIM17_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK,EVENTOUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,?..."
|
|
line.long 0x04 "GPIOB_AFRH,GPIO Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" ",TIM15_CH2,TIM1_CH3N,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" ",TIM15_CH1,TIM1_CH2N,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" ",,TIM1_CH1N,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" ",EVENTOUT,TIM1_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "IR_OUT,I2C1_SDA,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",I2C1_SCL,TIM16_CH1,?..."
|
|
elif CPUIS("STM32F070CB")||CPUIS("STM32F070RB")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,,USART4_CTS,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO,TIM3_CH1,EVENTOUT,,,TIM17_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK,EVENTOUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,,USART3_RTS,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,,USART3_CK,?..."
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" "SPI2_MOS,TIM15_CH2,TIM1_CH3N,TIM15_CH1N,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" "SPI2_MISO,TIM15_CH1,TIM1_CH2N,,USART3_RTS,I2C2_SDA,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" "SPI2_SCK,,TIM1_CH1N,,USART3_CTS,I2C2_SCL,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" "SPI2_NSS,EVENTOUT,TIM1_BKIN,,USART3_CK,TIM15_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" "EVENTOUT,I2C2_SDA,,,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" ",I2C2_SCL,,,USART3_TX,SPI2_SCK,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "IR_OUT,I2C1_SDA,TIM17_CH1,EVENTOUT,SPI2_NSS,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",I2C1_SCL,TIM16_CH1,?..."
|
|
elif CPUIS("STM32F030CC")||CPUIS("STM32F030RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,,USART4_CTS,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,USART5_CK_RTS,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO,TIM3_CH1,EVENTOUT,,USART5_RX,TIM17_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK,EVENTOUT,,,USART5_TX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,,USART3_RTS,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,,USART3_CK,?..."
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" "SPI2_MOSI,TIM15_CH2,TIM1_CH3N,TIM15_CH1N,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" "SPI2_MISO,TIM15_CH1,TIM1_CH2N,,USART3_RTS,I2C2_SDA,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" "SPI2_SCK,,TIM1_CH1N,,USART3_CTS,I2C2_SCL,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" "SPI2_NSS,EVENTOUT,TIM1_BKIN,,USART3_RTS,TIM15,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" "EVENTOUT,I2C2_SDA,,,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" ",I2C2_SCL,,,USART3_TX,SPI2_SCK,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "IR_OUT,I2C1_SDA,TIM17_CH1,EVENTOUT,,SPI2_NSS,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",I2C1_SCL,TIM16_CH1,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOB_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port B reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port B reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port B reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port B reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port B reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port B reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port B reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port B reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Port B reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port B reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port B reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port B reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port B reset bit 3" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BR2 ,Port B reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BR1 ,Port B reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port B reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif !cpuis("STM32F070F6")
|
|
tree "GPIO C"
|
|
base ad:0x48000800
|
|
width 18.
|
|
sif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||cpuis("STM32F098CC")||CPUIS("STM32F051T8")||CPUIS("STM32F030CC")||CPUIS("STM32F030C6")||CPUIS("STM32F030C8")||CPUIS("STM32F030R8")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOC_MODER,GPIO Port C Mode Register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif !cpuis("STM32F098CC")
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
endif
|
|
line.long 0x04 "GPIOC_OTYPER,GPIO port C mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif !cpuis("STM32F098CC")
|
|
bitfld.long 0x04 13. " OT13 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
endif
|
|
line.long 0x08 "GPIOC_OSPEEDR,GPIO Port C Output Speed Register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOC_PUPDR,GPIO port C pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
sif !cpuis("STM32F098CC")
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOC_IDR,GPIO Port C Input Data Register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port C input data" "Low,High"
|
|
textline " "
|
|
sif !cpuis("STM32F098CC")
|
|
bitfld.long 0x00 13. " IDR13 ,Port C input data" "Low,High"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOC_ODR,GPIO Port C Output Data Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port C output data" "Low,High"
|
|
textline " "
|
|
sif !cpuis("STM32F098CC")
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port C output data" "Low,High"
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOC_BRR,GPIO Port Bit Reset Register"
|
|
bitfld.long 0x00 15. " BR15 ,Port C reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port C reset bit 14" "No effect,Reset"
|
|
textline " "
|
|
sif !cpuis("STM32F098CC")
|
|
bitfld.long 0x00 13. " BR13 ,Port C reset bit 13" "No effect,Reset"
|
|
endif
|
|
else
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOC_MODER,GPIO Port C Mode Register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOC_OTYPER,GPIO Port C Mode Register"
|
|
bitfld.long 0x04 15. " OT15 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OT7 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOC_OSPEEDR,GPIO Port C Output Speed Register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOC_PUPDR,GPIO Port C Pull-up/Pull-down Register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOC_IDR,GPIO Port C Input Data Register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port C input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOC_ODR,GPIO Port C Output Data Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr ,Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port C output data" "Low,High"
|
|
sif (cpuis("STM32F078RB")||cpuis("STM32F078VB"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "TIM3_CH2,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "TIM3_CH1,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" "TSC_G3_IO1,USART3_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "EVENTOUT,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "EVENTOUT,SPI2_MOSI/I2S2_SD,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "EVENTOUT,SPI2_MISO/I2S2_MCK,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "EVENTOUT,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" "USART4_CK,USART3_CK,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" "USART4_RX,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" "USART4_TX,USART3_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "TIM3_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "TIM3_CH3,?..."
|
|
elif CPUIS("STM32F030RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "TIM3_CH2,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "TIM3_CH1,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",USART3_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "EVENTOUT,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "EVENTOUT,SPI2_MOS,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "EVENTOUT,SPI2_MISO,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "EVENTOUT,,USART6_RX,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "EVENTOUT,,USART6_TX,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO Alternate Function High Register"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" "USART4_CK,USART3_CK,USART5_TX,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" "USART4_RX,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" "USART4_TX,USART3_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "TIM3_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "TIM3_CH3,?..."
|
|
elif (cpuis("STM32F091R*")||cpuis("STM32F091V*")||cpuis("STM32F098RC"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "TIM3_CH2,USART7_RX,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "TIM3_CH1,USART7_TX,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" "TSC_G3_IO1,USART3_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "EVENTOUT,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "EVENTOUT,SPI2_MOSI/I2S2_SD,USART8_RX,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "EVENTOUT,SPI2_MISO/I2S2_MCK,USART8_TX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "EVENTOUT,USART7_RX,USART6_RX,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "EVENTOUT,USART7_TX,USART6_TX,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" "USART4_CK,USART3_CK,USART5_TX,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" "USART4_RX,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" "USART4_TX,USART3_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "TIM3_CH4,USART8_RX,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "TIM3_CH3,USART8_TX,?..."
|
|
elif (cpuis("STM32F058R8"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "TIM3_CH2,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "TIM3_CH1,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" "TSC_G3_IO1,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "EVENTOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "EVENTOUT,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "EVENTOUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "EVENTOUT,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "TIM3_CH4,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "TIM3_CH3,?..."
|
|
elif CPUIS("STM32F070RB")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "TIM3_CH2,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "TIM3_CH1,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",USART3_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "EVENTOUT,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "EVENTOUT,SPI2_MOSI,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "EVENTOUT,SPI2_MISO,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "EVENTOUT,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO Alternate Function High Register"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" "USART4_CK,USART3_CK,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" "USART4_RX,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" "USART4_TX,USART3_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "TIM3_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "TIM3_CH3,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOC_BRR,GPIO Port Bit Reset Register"
|
|
bitfld.long 0x00 15. " BR15 ,Port C reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port C reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port C reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port C reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port C reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port C reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port C reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port C reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Port C reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port C reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port C reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port C reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port C reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port C reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port C reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port C reset bit 0" "No effect,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F030C6")&&!cpuis("STM32F030C8")
|
|
tree "GPIO D"
|
|
base ad:0x48000C00
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOD_MODER,GPIO port D mode register"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOD_OTYPER,GPIO port D mode register"
|
|
bitfld.long 0x04 2. " OT2 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOD_OSPEEDR,GPIO port D output speed register"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOD_PUPDR,GPIO port D pull-up/pull-down register"
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOD_IDR,GPIO port D input data register"
|
|
bitfld.long 0x00 2. " IDR2 ,Port D input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOD_ODR,GPIO port D output data register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port D output data" "Low,High"
|
|
sif (cpuis("STM32F058R8")||CPUIS("STM32F070RB"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " ARFL2 ,Alternate function selection for port D bit 2" "TIM3_ETR,?..."
|
|
elif (cpuis("STM32F078R8"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " ARFL2 ,Alternate function selection for port D bit 2" "TIM3_ETR,USART3_RTS,?..."
|
|
elif (cpuis("STM32F091R*")||cpuis("STM32F098RC")||CPUIS("STM32F030RC"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " ARFL2 ,Alternate function selection for port D bit 2" "TIM3_ETR,USART3_RTS,USART5_RX,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOD_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 2. " BR2 ,Port D reset bit 2" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "GPIO F"
|
|
base ad:0x48001400
|
|
width 18.
|
|
sif (cpuis("STM32F078VB")||cpuis("STM32F091V*"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F mode register"
|
|
bitfld.long 0x04 10. " OT10 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 3. " OT3 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 2. " OT2 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
bitfld.long 0x00 10. " IDR10 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 3. " IDR3 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDR2 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOF_ODR,GPIO port F output data register"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR6_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR5_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR4_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port F output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOF_LCKR,GPIO port F configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
bitfld.long 0x00 10. " LCK10 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LCK3 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port F lock bit" "Not locked,Locked"
|
|
sif (cpuis("STM32F091V*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port F bit 3" "EVENTOUT,USART7_RX,USART6_CK_RTS,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port F bit 2" "EVENTOUT,USART7_TX,USART7_CK_RTS,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F bit 1" ",I2C1_SCL,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" "CRS_SYNC,I2C1_SDA,?..."
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port F bit 10" "TIM15_CH2,USART6_RX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port F bit 9" "TIM15_CH1,USART6_TX,?..."
|
|
endif
|
|
sif (cpuis("STM32F078VB"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port F bit 3" "EVENTOUT,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port F bit 2" "EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" "CRS_SYNC,?..."
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port F bit 10" "TIM15_CH2,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port F bit 9" "TIM15_CH1,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 10. " BR10 ,Port F reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port F reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port F reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 3. " BR3 ,Port F reset bit 3" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BR2 ,Port F reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port F reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port F reset bit 0" "No effect,Reset"
|
|
elif (cpu()=="STM32F051R4"||cpu()=="STM32F051R6"||cpu()=="STM32F051R8"||cpuis("STM32F058R8")||cpuis("STM32F030R8"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F mode register"
|
|
bitfld.long 0x04 7. " OT7 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
bitfld.long 0x00 7. " IDR7 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOF_ODR,GPIO port F output data register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port F output data" "Low,High"
|
|
sif (cpuis("STM32F058R8"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port F bit 7" "I2C2_SDA,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port F bit 6" "I2C2_SCL,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port F bit 5" "EVENTOUT,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port F bit 4" "EVENTOUT,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 7. " BR7 ,Port F reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port F reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port F reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port F reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BR1 ,Port F reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port F reset bit 0" "No effect,Reset"
|
|
elif (cpu()=="STM32F050C4"||cpu()=="STM32F050C6"||cpu()=="STM32F051C4"||cpu()=="STM32F051C6"||cpu()=="STM32F051C8"||cpuis("STM32F038C6")||cpuis("STM32F058C8"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F mode register"
|
|
bitfld.long 0x04 7. " OT7 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
bitfld.long 0x00 7. " IDR7 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOF_ODR,GPIO port F output data register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port F output data" "Low,High"
|
|
sif (cpuis("STM32F038C6"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port F bit 7" "I2C1_SCL,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port F bit 6" "I2C1_SDA,?..."
|
|
elif (cpuis("STM32F058C8"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port F bit 7" "I2C1_SCL,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port F bit 6" "I2C1_SDA,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 7. " BR7 ,Port F reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port F reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port F reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port F reset bit 0" "No effect,Reset"
|
|
else
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
sif (cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F mode register"
|
|
sif (cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
bitfld.long 0x04 11. " OT11 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
sif (cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
sif (cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
sif (cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
bitfld.long 0x00 11. " IDR11 ,Port F input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOF_ODR,GPIO port F output data register"
|
|
sif (cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port F output data" "Low,High"
|
|
sif !cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F031E6")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070RB")&&!cpuis("STM32F070F6")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOF_LCKR,GPIO port F configuration lock register"
|
|
bitfld.long 0x00 1. " LCK1 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port F lock bit" "Not locked,Locked"
|
|
endif
|
|
sif (cpuis("STM32F048G6")||cpuis("STM32F048T6")||cpuis("STM32F091C*")||cpuis("STM32F091R*")||cpuis("STM32F098CC")||cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F bit 1" "CRS_SYNC,I2C1_SDA,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" ",I2C1_SCL,?..."
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F bit 1" ",I2C1_SCL,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" ",I2C1_SDA,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 1. " BR1 ,Port F reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port F reset bit 0" "No effect,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
elif cpuis("STM32F042*")
|
|
tree "GPIO A"
|
|
base ad:0x48000000
|
|
width 15.
|
|
if (((per.l(ad:0x40010000))&0x10)==0x10)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIOA_MODER,GPIO port A mode register"
|
|
sif (!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif (cpuis("STM32F042F*"))||(cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
elif (cpuis("STM32F042C*"))||(cpuis("STM32F042T*"))||(cpuis("STM32F042K*"))
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIOA_MODER,GPIO port A mode register"
|
|
sif (!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif (cpuis("STM32F042F*"))||(cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
elif (cpuis("STM32F042C*"))||(cpuis("STM32F042T*"))||(cpuis("STM32F042K*"))
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
endif
|
|
if (((per.l(ad:0x40010000))&0x10)==0x10)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GPIOA_OTYPER,GPIO port A mode register"
|
|
sif (!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 15. " OT15 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " OT14 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 13. " OT13 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif (cpuis("STM32F042F*"))||(cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 12. " OT12 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 11. " OT11 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
elif (cpuis("STM32F042C*"))||(cpuis("STM32F042T*"))||(cpuis("STM32F042K*"))
|
|
bitfld.long 0x00 12. " OT12 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 11. " OT11 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OT10 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 9. " OT9 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 8. " OT8 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " OT7 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 6. " OT6 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 5. " OT5 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 4. " OT4 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OT3 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 2. " OT2 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 1. " OT1 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 0. " OT0 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GPIOA_OTYPER,GPIO port A mode register"
|
|
sif (!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 15. " OT15 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " OT14 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 13. " OT13 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif (cpuis("STM32F042F*"))||(cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 10. " OT10 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 9. " OT9 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
elif (cpuis("STM32F042C*"))||(cpuis("STM32F042T*"))||(cpuis("STM32F042K*"))
|
|
bitfld.long 0x00 12. " OT12 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 11. " OT11 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OT10 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 9. " OT9 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 8. " OT8 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " OT7 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 6. " OT6 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 5. " OT5 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 4. " OT4 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OT3 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 2. " OT2 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 1. " OT1 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 0. " OT0 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
endif
|
|
if (((per.l(ad:0x40010000))&0x10)==0x10)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GPIOA_OSPEEDR,GPIO port A output speed register"
|
|
sif (!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 30.--31. " OSPEEDR15 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28.--29. " OSPEEDR14 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 26.--27. " OSPEEDR13 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
sif (cpuis("STM32F042F*"))||(cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 24.--25. " OSPEEDR12 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 22.--23. " OSPEEDR11 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
elif (cpuis("STM32F042C*"))||(cpuis("STM32F042T*"))||(cpuis("STM32F042K*"))
|
|
bitfld.long 0x00 24.--25. " OSPEEDR12 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 22.--23. " OSPEEDR11 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " OSPEEDR10 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 18.--19. " OSPEEDR9 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 16.--17. " OSPEEDR8 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14.--15. " OSPEEDR7 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 12.--13. " OSPEEDR6 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 10.--11. " OSPEEDR5 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 8.--9. " OSPEEDR4 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " OSPEEDR3 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 4.--5. " OSPEEDR2 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 2.--3. " OSPEEDR1 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 0.--1. " OSPEEDR0 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GPIOA_OSPEEDR,GPIO port A output speed register"
|
|
sif (!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 30.--31. " OSPEEDR15 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28.--29. " OSPEEDR14 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 26.--27. " OSPEEDR13 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
sif (cpuis("STM32F042F*"))||(cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 20.--21. " OSPEEDR10 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 18.--19. " OSPEEDR9 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
elif (cpuis("STM32F042C*"))||(cpuis("STM32F042T*"))||(cpuis("STM32F042K*"))
|
|
bitfld.long 0x00 24.--25. " OSPEEDR12 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 22.--23. " OSPEEDR11 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " OSPEEDR10 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 18.--19. " OSPEEDR9 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 16.--17. " OSPEEDR8 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14.--15. " OSPEEDR7 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 12.--13. " OSPEEDR6 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 10.--11. " OSPEEDR5 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 8.--9. " OSPEEDR4 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " OSPEEDR3 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 4.--5. " OSPEEDR2 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 2.--3. " OSPEEDR1 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 0.--1. " OSPEEDR0 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
endif
|
|
if (((per.l(ad:0x40010000))&0x10)==0x10)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GPIOA_PUPDR,GPIO port A pull-up/pull-down register"
|
|
sif (!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 30.--31. " PUPDR15 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28.--29. " PUPDR14 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 26.--27. " PUPDR13 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
sif (cpuis("STM32F042F*"))||(cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 24.--25. " PUPDR12 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 22.--23. " PUPDR11 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
elif (cpuis("STM32F042C*"))||(cpuis("STM32F042T*"))||(cpuis("STM32F042K*"))
|
|
bitfld.long 0x00 24.--25. " PUPDR12 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 22.--23. " PUPDR11 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " PUPDR10 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 18.--19. " PUPDR9 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 16.--17. " PUPDR8 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14.--15. " PUPDR7 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 12.--13. " PUPDR6 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 10.--11. " PUPDR5 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 8.--9. " PUPDR4 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " PUPDR3 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 4.--5. " PUPDR2 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 2.--3. " PUPDR1 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 0.--1. " PUPDR0 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GPIOA_PUPDR,GPIO port A pull-up/pull-down register"
|
|
sif (!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 30.--31. " PUPDR15 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28.--29. " PUPDR14 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 26.--27. " PUPDR13 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
sif (cpuis("STM32F042F*"))||(cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 20.--21. " PUPDR10 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 18.--19. " PUPDR9 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
elif (cpuis("STM32F042C*"))||(cpuis("STM32F042T*"))||(cpuis("STM32F042K*"))
|
|
bitfld.long 0x00 24.--25. " PUPDR12 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 22.--23. " PUPDR11 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " PUPDR10 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 18.--19. " PUPDR9 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 16.--17. " PUPDR8 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14.--15. " PUPDR7 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 12.--13. " PUPDR6 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 10.--11. " PUPDR5 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 8.--9. " PUPDR4 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " PUPDR3 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 4.--5. " PUPDR2 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 2.--3. " PUPDR1 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x00 0.--1. " PUPDR0 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
endif
|
|
if (((per.l(ad:0x40010000))&0x10)==0x10)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOA_IDR,GPIO port A input data register"
|
|
sif (!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 15. " IDR15 ,Port A input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " IDR14 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port A input data" "Low,High"
|
|
textline " "
|
|
sif (cpuis("STM32F042F*"))||(cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 12. " IDR12 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port A input data" "Low,High"
|
|
textline " "
|
|
elif (cpuis("STM32F042C*"))||(cpuis("STM32F042T*"))||(cpuis("STM32F042K*"))
|
|
bitfld.long 0x00 12. " IDR12 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IDR10 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port A input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 8. " IDR8 ,Port A input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " IDR7 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port A input data" "Low,High"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOA_IDR,GPIO port A input data register"
|
|
sif (!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 15. " IDR15 ,Port A input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " IDR14 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port A input data" "Low,High"
|
|
textline " "
|
|
sif (cpuis("STM32F042F*"))||(cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 10. " IDR10 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port A input data" "Low,High"
|
|
textline " "
|
|
elif (cpuis("STM32F042C*"))||(cpuis("STM32F042T*"))||(cpuis("STM32F042K*"))
|
|
bitfld.long 0x00 12. " IDR12 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IDR10 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port A input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 8. " IDR8 ,Port A input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " IDR7 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port A input data" "Low,High"
|
|
endif
|
|
if (((per.l(ad:0x40010000))&0x10)==0x10)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOA_ODR,GPIO port A output data register"
|
|
sif (!cpuis("STM32F042F*"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
sif (cpuis("STM32F042F*"))||(cpuis("STM32F042G*"))
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
elif (cpuis("STM32F042C*"))||(cpuis("STM32F042T*"))||(cpuis("STM32F042K*"))
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042G*"))
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port A output data" "Low,High"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOA_ODR,GPIO port A output data register"
|
|
sif (!cpuis("STM32F042F*"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
sif (cpuis("STM32F042F*"))||(cpuis("STM32F042G*"))
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
elif (cpuis("STM32F042C*"))||(cpuis("STM32F042T*"))||(cpuis("STM32F042K*"))
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042G*"))
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port A output data" "Low,High"
|
|
endif
|
|
if (((per.l(ad:0x40010000))&0x10)==0x10)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOA_LCKR,GPIO port A configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
textline " "
|
|
sif (!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 15. " LCK15 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " LCK14 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpuis("STM32F042F*"))||(cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 12. " LCK12 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
elif (cpuis("STM32F042C*"))||(cpuis("STM32F042T*"))||(cpuis("STM32F042K*"))
|
|
bitfld.long 0x00 12. " LCK12 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 8. " LCK8 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LCK7 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " LCK4 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LCK3 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port A lock bit" "Not locked,Locked"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOA_LCKR,GPIO port A configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
textline " "
|
|
sif (!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 15. " LCK15 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " LCK14 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpuis("STM32F042F*"))||(cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 10. " LCK10 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
elif (cpuis("STM32F042C*"))||(cpuis("STM32F042T*"))||(cpuis("STM32F042K*"))
|
|
bitfld.long 0x00 12. " LCK12 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 8. " LCK8 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LCK7 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " LCK4 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LCK3 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port A lock bit" "Not locked,Locked"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,TSC_G2_IO4,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,TSC_G2_IO3,,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK/I2S1_CK,CEC,TIM2_CH1_ETR,TSC_G2_IO2,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,USART2_CK,USB_NOE,TSC_G2_IO1,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",USART2_RX,TIM2_CH4,TSC_G1_IO4,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",USART2_TX,TIM2_CH3,TSC_G1_IO3,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,TIM2_CH2,TSC_G1_IO2,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,TIM2_CH1_ETR,TSC_G1_IO1,?..."
|
|
if (((per.l(ad:0x40010000))&0x10)==0x10)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPIOA_AFRH,GPIO alternate function high register"
|
|
sif (!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,USART2_RX,TIM2_CH1_ETR,EVENTOUT,,USB_NOE,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x00 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,USB_NOE,?..."
|
|
textline " "
|
|
sif (cpuis("STM32F042F*"))||(cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,TSC_G4_IO4,CAN_TX,I2C1_SDA,?..."
|
|
bitfld.long 0x00 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,TSC_G4_IO3,CAN_RX,I2C1_SCL,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F042C*"))||(cpuis("STM32F042T*"))||(cpuis("STM32F042K*"))
|
|
bitfld.long 0x00 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,TSC_G4_IO4,CAN_TX,I2C1_SDA,?..."
|
|
bitfld.long 0x00 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,TSC_G4_IO3,CAN_RX,I2C1_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,TSC_G4_IO2,I2C1_SDA,?..."
|
|
bitfld.long 0x00 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",USART1_TX,TIM1_CH2,TSC_G4_IO1,I2C1_SCL,MCO,?..."
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,CRS_SYNC,?..."
|
|
textline " "
|
|
endif
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPIOA_AFRH,GPIO alternate function high register"
|
|
sif (!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,USART2_RX,TIM2_CH1_ETR,EVENTOUT,,USB_NOE,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x00 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,USB_NOE,?..."
|
|
textline " "
|
|
sif (cpuis("STM32F042F*"))||(cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,TSC_G4_IO2,I2C1_SDA,?..."
|
|
bitfld.long 0x00 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",USART1_TX,TIM1_CH2,TSC_G4_IO1,I2C1_SCL,MCO,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F042C*"))||(cpuis("STM32F042T*"))||(cpuis("STM32F042K*"))
|
|
bitfld.long 0x00 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,TSC_G4_IO4,CAN_TX,I2C1_SDA,?..."
|
|
bitfld.long 0x00 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,TSC_G4_IO3,CAN_RX,I2C1_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,TSC_G4_IO2,I2C1_SDA,?..."
|
|
bitfld.long 0x00 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",USART1_TX,TIM1_CH2,TSC_G4_IO1,I2C1_SCL,MCO,?..."
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,CRS_SYNC,?..."
|
|
textline " "
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40010000))&0x10)==0x10)
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOA_BRR,Port bit reset register"
|
|
sif (!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 15. " BR15 ,Port A reset bit 15" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " BR14 ,Port A reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port A reset bit 13" "No effect,Reset"
|
|
textline " "
|
|
sif (cpuis("STM32F042F*"))||(cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 12. " BR12 ,Port A reset bit 12" "No effect,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port A reset bit 11" "No effect,Reset"
|
|
textline " "
|
|
elif (cpuis("STM32F042C*"))||(cpuis("STM32F042T*"))||(cpuis("STM32F042K*"))
|
|
bitfld.long 0x00 12. " BR12 ,Port A reset bit 12" "No effect,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port A reset bit 11" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BR10 ,Port A reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port A reset bit 9" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 8. " BR8 ,Port A reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " BR7 ,Port A reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port A reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port A reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port A reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port A reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port A reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port A reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port A reset bit 0" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOA_BRR,Port bit reset register"
|
|
sif (!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 15. " BR15 ,Port A reset bit 15" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " BR14 ,Port A reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port A reset bit 13" "No effect,Reset"
|
|
textline " "
|
|
sif (cpuis("STM32F042F*"))||(cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 10. " BR10 ,Port A reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port A reset bit 9" "No effect,Reset"
|
|
textline " "
|
|
elif (cpuis("STM32F042C*"))||(cpuis("STM32F042T*"))||(cpuis("STM32F042K*"))
|
|
bitfld.long 0x00 12. " BR12 ,Port A reset bit 12" "No effect,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port A reset bit 11" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BR10 ,Port A reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port A reset bit 9" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 8. " BR8 ,Port A reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " BR7 ,Port A reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port A reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port A reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port A reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port A reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port A reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port A reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port A reset bit 0" "No effect,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO B"
|
|
base ad:0x48000400
|
|
width 15.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOB_MODER,GPIO port B mode register"
|
|
sif (cpuis(STM32F042C*))
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis(STM32F042F*))
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042K*"))&&(!cpuis(STM32F042F*))
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif (!cpuis(STM32F042F*))
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
line.long 0x04 "GPIOB_OTYPER,GPIO port B mode register"
|
|
sif (cpuis(STM32F042C*))
|
|
bitfld.long 0x04 15. " OT15 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis(STM32F042F*))
|
|
bitfld.long 0x04 8. " OT8 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OT7 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042K*"))&&(!cpuis(STM32F042F*))
|
|
bitfld.long 0x04 2. " OT2 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 1. " OT1 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif (!cpuis(STM32F042F*))
|
|
bitfld.long 0x04 0. " OT0 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
line.long 0x08 "GPIOB_OSPEEDR,GPIO port B output speed register"
|
|
sif (cpuis(STM32F042C*))
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis(STM32F042F*))
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042K*"))&&(!cpuis(STM32F042F*))
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042K*"))&&(!cpuis(STM32F042F*))
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
sif (!cpuis(STM32F042F*))
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
line.long 0x0C "GPIOB_PUPDR,GPIO port B pull-up/pull-down register"
|
|
sif (cpuis(STM32F042C*))
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis(STM32F042F*))
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042K*"))&&(!cpuis(STM32F042F*))
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042K*"))&&(!cpuis(STM32F042F*))
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
sif (!cpuis(STM32F042F*))
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOB_IDR,GPIO port B input data register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 15. " IDR15 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port B input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 8. " IDR8 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port B input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042K*"))&&(!cpuis(STM32F042F*))
|
|
bitfld.long 0x00 3. " IDR3 ,Port B input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042K*"))&&(!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 2. " IDR2 ,Port B input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " IDR1 ,Port B input data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis(STM32F042F*))
|
|
bitfld.long 0x00 0. " IDR0 ,Port B input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOB_ODR,GPIO port B output data register"
|
|
sif (cpuis("STM32F042C*"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042F*"))
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042K*"))&&(!cpuis(STM32F042F*))
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042K*"))&&(!cpuis(STM32F042F*))
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis(STM32F042F*))
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOB_LCKR,GPIO port B configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
textline " "
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 15. " LCK15 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LCK11 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis(STM32F042F*))
|
|
bitfld.long 0x00 8. " LCK8 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " LCK4 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042K*"))&&(!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 3. " LCK3 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042K*"))&&(!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 2. " LCK2 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " LCK1 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
sif (!cpuis(STM32F042F*))
|
|
bitfld.long 0x00 0. " LCK0 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
sif (!cpuis(STM32F042F*))
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,TSC_G5_IO4,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,TSC_G5_IO3,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,TSC_G5_IO2,,TIM17_BKIN,?..."
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042K*"))&&(!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,TSC_G5_IO1,?..."
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042K*"))&&(!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" ",,,TSC_G3_IO4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,TSC_G3_IO3,?..."
|
|
textline " "
|
|
sif (!cpuis(STM32F042F*))
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,TSC_G3_IO2,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F042C*"))||(cpuis("STM32F042G*"))||(cpuis("STM32F042K*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPIOB_AFRH,GPIO alternate function high register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" "SPI2_MOSI,,TIM1_CH3N,?..."
|
|
bitfld.long 0x00 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" "SPI2_MISO,,TIM1_CH2N,,,I2C2_SDA,?..."
|
|
bitfld.long 0x00 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" "SPI2_SCK,,TIM1_CH1N,,,I2C2_SCL,?..."
|
|
bitfld.long 0x00 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" "SPI2_NSS,EVENTOUT,TIM1_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" "EVENTOUT,I2C1_SDA,TIM2_CH4,?..."
|
|
bitfld.long 0x00 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" "CEC,I2C1_SCL,TIM2_CH3,TSC_SYNC,,SPI2_SCK,?..."
|
|
bitfld.long 0x00 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "IR_OUT,I2C1_SDA,TIM17_CH1,EVENTOUT,CAN_TX,SPI2_NSS,?..."
|
|
endif
|
|
bitfld.long 0x00 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" "CEC,I2C1_SCL,TIM16_CH1,TSC_SYNC,CAN_RX,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOB_BRR,Port bit reset register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 15. " BR15 ,Port B reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port B reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port B reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port B reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port B reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port B reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port B reset bit 9" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 8. " BR8 ,Port B reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Port B reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port B reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port B reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port B reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042K*"))&&(!cpuis(STM32F042F*))
|
|
bitfld.long 0x00 3. " BR3 ,Port B reset bit 3" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042K*"))&&(!cpuis("STM32F042F*"))
|
|
bitfld.long 0x00 2. " BR2 ,Port B reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " BR1 ,Port B reset bit 1" "No effect,Reset"
|
|
textline " "
|
|
sif (!cpuis(STM32F042F*))
|
|
bitfld.long 0x00 0. " BR0 ,Port B reset bit 0" "No effect,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("STM32F042C*"))||(cpuis("STM32F042T*"))
|
|
tree "GPIO C"
|
|
base ad:0x48000800
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOC_MODER,GPIO port C mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
sif (cpuis("STM32F048T6")||cpuis("STM32F098CC"))
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,,Analog"
|
|
else
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
endif
|
|
line.long 0x04 "GPIOC_OTYPER,GPIO port C mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x04 13. " OT13 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
endif
|
|
line.long 0x08 "GPIOC_OSPEEDR,GPIO port C output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
endif
|
|
line.long 0x0C "GPIOC_PUPDR,GPIO port C pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOC_IDR,GPIO port C input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port C input data" "Low,High"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x00 13. " IDR13 ,Port C input data" "Low,High"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOC_ODR,GPIO port C output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port C output data" "Low,High"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port C output data" "Low,High"
|
|
endif
|
|
sif !cpuis("STM32F058?8")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOC_LCKR,GPIO port C configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port C lock bit" "Not locked,Locked"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x00 13. " LCK13 ,Port C lock bit" "Not locked,Locked"
|
|
endif
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOC_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port C reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port C reset bit 14" "No effect,Reset"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x00 13. " BR13 ,Port C reset bit 13" "No effect,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "GPIO F"
|
|
base ad:0x48001400
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F mode register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x04 11. " OT11 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x04 10. " OT10 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 11. " IDR11 ,Port F input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 10. " IDR10 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port F input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOF_ODR,GPIO port F output data register"
|
|
sif (cpuis("STM32F042C*"))
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port F output data" "Low,High"
|
|
sif !CPUIS("STM32F031E6")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOF_LCKR,GPIO port F configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
textline " "
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 11. " LCK11 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 10. " LCK10 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LCK3 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " LCK1 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port F lock bit" "Not locked,Locked"
|
|
endif
|
|
sif (!cpuis("STM32F031*"))&&(!cpuis("STM32F050*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port F bit 3" "EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port F bit 2" "EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F042*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F bit 1" ",I2C1_SCL,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" "CRS_SYNC,I2C1_SDA,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F071*"))
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" "CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC"
|
|
endif
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port F bit 10" "TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port F bit 9" "TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1"
|
|
endif
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,GPIO port bit reset register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 11. " BR11 ,Port F reset bit 11" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 10. " BR10 ,Port F reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port F reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port F reset bit 6" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port F reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port F reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " BR1 ,Port F reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port F reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
elif (cpuis("STM32F031*"))
|
|
tree "GPIO A"
|
|
base ad:0x48000000
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GPIOA_MODER,GPIO port A mode register"
|
|
sif (!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))&&(!cpuis("STM32F031G*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GPIOA_OTYPER,GPIO port A mode register"
|
|
sif (!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 15. " OT15 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " OT14 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 13. " OT13 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))&&(!cpuis("STM32F031G*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 12. " OT12 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 11. " OT11 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " OT10 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 9. " OT9 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x00 8. " OT8 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " OT7 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 6. " OT6 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 5. " OT5 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 4. " OT4 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OT3 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 2. " OT2 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 1. " OT1 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 0. " OT0 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GPIOA_OSPEEDR,GPIO port A output speed register"
|
|
sif (!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 30.--31. " OSPEEDR15 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28.--29. " OSPEEDR14 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 26.--27. " OSPEEDR13 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))&&(!cpuis("STM32F031G*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 24.--25. " OSPEEDR12 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 22.--23. " OSPEEDR11 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20.--21. " OSPEEDR10 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 18.--19. " OSPEEDR9 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x00 16.--17. " OSPEEDR8 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14.--15. " OSPEEDR7 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 12.--13. " OSPEEDR6 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 10.--11. " OSPEEDR5 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 8.--9. " OSPEEDR4 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " OSPEEDR3 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 4.--5. " OSPEEDR2 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 2.--3. " OSPEEDR1 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x00 0.--1. " OSPEEDR0 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "GPIOA_PUPDR,GPIO port A pull-up/pull-down register"
|
|
sif (!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 30.--31. " PUPDR15 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28.--29. " PUPDR14 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x00 26.--27. " PUPDR13 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))&&(!cpuis("STM32F031G*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 24.--25. " PUPDR12 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x00 22.--23. " PUPDR11 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20.--21. " PUPDR10 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x00 18.--19. " PUPDR9 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x00 16.--17. " PUPDR8 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14.--15. " PUPDR7 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x00 12.--13. " PUPDR6 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x00 10.--11. " PUPDR5 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x00 8.--9. " PUPDR4 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " PUPDR3 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x00 4.--5. " PUPDR2 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x00 2.--3. " PUPDR1 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x00 0.--1. " PUPDR0 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOA_IDR,GPIO port A input data register"
|
|
sif (!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 15. " IDR15 ,Port A input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " IDR14 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port A input data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))&&(!cpuis("STM32F031G*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 12. " IDR12 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port A input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " IDR10 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port A input data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x00 8. " IDR8 ,Port A input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " IDR7 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port A input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOA_ODR,GPIO port A output data register"
|
|
sif (!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))&&(!cpuis("STM32F031G*")&&!CPUIS("STM32F031E6"))
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port A output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOA_LCKR,GPIO port A configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 15. " LCK15 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " LCK14 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))&&(!cpuis("STM32F031G*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 12. " LCK12 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " LCK10 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x00 8. " LCK8 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LCK7 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " LCK4 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LCK3 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port A lock bit" "Not locked,Locked"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,,,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK/I2S1_CK,,TIM2_CH1_ETR,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,USART1_RTS,,,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",USART1_CTS,TIM2_CH4,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",USART1_RX,TIM2_CH3,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART1_TX,TIM2_CH2,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART1_CKS,TIM2_CH1_ETR,?..."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPIOA_AFRH,GPIO alternate function high register"
|
|
sif (!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,USART1_RX,TIM2_CH1_ETR,EVENTOUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART1_TX,?..."
|
|
bitfld.long 0x00 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,?..."
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))&&(!cpuis("STM32F031G*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,?..."
|
|
bitfld.long 0x00 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,,I2C1_SDA,?..."
|
|
bitfld.long 0x00 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",USART1_TX,TIM1_CH2,,I2C1_SCL,?..."
|
|
textline " "
|
|
sif (!cpuis("STM32F042G*"))
|
|
bitfld.long 0x00 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOA_BRR,Port bit reset register"
|
|
sif (!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 15. " BR15 ,Port A reset bit 15" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " BR14 ,Port A reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port A reset bit 13" "No effect,Reset"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))&&(!cpuis("STM32F031G*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 12. " BR12 ,Port A reset bit 12" "No effect,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port A reset bit 11" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " BR10 ,Port A reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port A reset bit 9" "No effect,Reset"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x00 8. " BR8 ,Port A reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " BR7 ,Port A reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port A reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port A reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port A reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port A reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port A reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port A reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port A reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO B"
|
|
base ad:0x48000400
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOB_MODER,GPIO port B mode register"
|
|
sif cpuis("STM32F031C*")
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F031G*"))&&(!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif !CPUIS("STM32F031E6")
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32F031G*"))&&(!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
endif
|
|
line.long 0x04 "GPIOB_OTYPER,GPIO port B mode register"
|
|
sif cpuis("STM32F031C*")
|
|
bitfld.long 0x04 15. " OT15 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F031G*"))&&(!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x04 8. " OT8 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x04 7. " OT7 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif !CPUIS("STM32F031E6")
|
|
bitfld.long 0x04 4. " OT4 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 3. " OT3 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32F031G*"))&&(!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x04 2. " OT2 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 1. " OT1 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x04 0. " OT0 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
endif
|
|
line.long 0x08 "GPIOB_OSPEEDR,GPIO port B output speed register"
|
|
sif cpuis("STM32F031C*")
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F031G*"))&&(!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
sif !CPUIS("STM32F031E6")
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32F031G*"))&&(!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
endif
|
|
line.long 0x0C "GPIOB_PUPDR,GPIO port B pull-up/pull-down register"
|
|
sif cpuis("STM32F031C*")
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F031G*"))&&(!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
sif !CPUIS("STM32F031E6")
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32F031G*"))&&(!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOB_IDR,GPIO port B input data register"
|
|
sif cpuis("STM32F031C*")
|
|
bitfld.long 0x00 15. " IDR15 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port B input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F031G*"))&&(!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 8. " IDR8 ,Port B input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x00 7. " IDR7 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port B input data" "Low,High"
|
|
textline " "
|
|
sif !CPUIS("STM32F031E6")
|
|
bitfld.long 0x00 4. " IDR4 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 3. " IDR3 ,Port B input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32F031G*"))&&(!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 2. " IDR2 ,Port B input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " IDR1 ,Port B input data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x00 0. " IDR0 ,Port B input data" "Low,High"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOB_ODR,GPIO port B output data register"
|
|
sif cpuis("STM32F031C*")
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F031G*"))&&(!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F031F*"))
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
sif !CPUIS("STM32F031E6")
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_SET/CLR ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_SET/CLR ,Port B output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32F031G*"))&&(!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port B output data" "Low,High"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOB_LCKR,GPIO port B configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
textline " "
|
|
sif cpuis("STM32F031C*")
|
|
bitfld.long 0x00 15. " LCK15 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LCK11 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F031G*"))&&(!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 8. " LCK8 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x00 7. " LCK7 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
sif !CPUIS("STM32F031E6")
|
|
bitfld.long 0x00 4. " LCK4 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32F031G*"))&&(!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 2. " LCK2 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " LCK1 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x00 0. " LCK0 ,Port B lock bit" "Not locked,Locked"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,?..."
|
|
textline " "
|
|
sif !CPUIS("STM32F031E6")
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,?..."
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,?..."
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,?..."
|
|
endif
|
|
sif (cpuis("STM32F031C*"))||(cpuis("STM32F031K*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPIOB_AFRH,GPIO alternate function high register"
|
|
sif (!cpuis("STM32F031K*"))
|
|
bitfld.long 0x00 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" "SPI1_MOSI,,TIM1_CH3N,,?..."
|
|
bitfld.long 0x00 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" "SPI1_MISO,,TIM1_CH2N,?..."
|
|
bitfld.long 0x00 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" "SPI1_SCK,,TIM1_CH1N,?..."
|
|
bitfld.long 0x00 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" "SPI1_NSS,EVENTOUT,TIM1_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" "EVENTOUT,I2C1_SDA,TIM2_CH4,?..."
|
|
bitfld.long 0x00 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" ",I2C1_SCL,TIM2_CH3,?..."
|
|
bitfld.long 0x00 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "IR_OUT,I2C1_SDA,TIM17_CH1,EVENTOUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",I2C1_SCL,TIM16_CH1,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOB_BRR,GPIO port bit reset register"
|
|
sif cpuis("STM32F031C*")
|
|
bitfld.long 0x00 15. " BR15 ,Port B reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port B reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port B reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port B reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port B reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port B reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port B reset bit 9" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F031G*"))&&(!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 8. " BR8 ,Port B reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x00 7. " BR7 ,Port B reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port B reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port B reset bit 5" "No effect,Reset"
|
|
textline " "
|
|
sif !CPUIS("STM32F031E6")
|
|
bitfld.long 0x00 4. " BR4 ,Port B reset bit 4" "No effect,Reset"
|
|
bitfld.long 0x00 3. " BR3 ,Port B reset bit 3" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32F031G*"))&&(!cpuis("STM32F031F*")&&!CPUIS("STM32F031E6"))
|
|
bitfld.long 0x00 2. " BR2 ,Port B reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " BR1 ,Port B reset bit 1" "No effect,Reset"
|
|
textline " "
|
|
sif (!cpuis("STM32F031F*"))
|
|
bitfld.long 0x00 0. " BR0 ,Port B reset bit 0" "No effect,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("STM32F031C*"))
|
|
tree "GPIO C"
|
|
base ad:0x48000800
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOC_MODER,GPIO port C mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
sif (cpuis("STM32F048T6")||cpuis("STM32F098CC"))
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,,Analog"
|
|
else
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
endif
|
|
line.long 0x04 "GPIOC_OTYPER,GPIO port C mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x04 13. " OT13 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
endif
|
|
line.long 0x08 "GPIOC_OSPEEDR,GPIO port C output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
endif
|
|
line.long 0x0C "GPIOC_PUPDR,GPIO port C pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOC_IDR,GPIO port C input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port C input data" "Low,High"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x00 13. " IDR13 ,Port C input data" "Low,High"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOC_ODR,GPIO port C output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port C output data" "Low,High"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port C output data" "Low,High"
|
|
endif
|
|
sif !cpuis("STM32F058?8")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOC_LCKR,GPIO port C configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port C lock bit" "Not locked,Locked"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x00 13. " LCK13 ,Port C lock bit" "Not locked,Locked"
|
|
endif
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOC_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port C reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port C reset bit 14" "No effect,Reset"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x00 13. " BR13 ,Port C reset bit 13" "No effect,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "GPIO F"
|
|
base ad:0x48001400
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F mode register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x04 11. " OT11 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x04 10. " OT10 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 11. " IDR11 ,Port F input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 10. " IDR10 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port F input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOF_ODR,GPIO port F output data register"
|
|
sif (cpuis("STM32F042C*"))
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port F output data" "Low,High"
|
|
sif !CPUIS("STM32F031E6")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOF_LCKR,GPIO port F configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
textline " "
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 11. " LCK11 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 10. " LCK10 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LCK3 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " LCK1 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port F lock bit" "Not locked,Locked"
|
|
endif
|
|
sif (!cpuis("STM32F031*"))&&(!cpuis("STM32F050*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port F bit 3" "EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port F bit 2" "EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F042*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F bit 1" ",I2C1_SCL,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" "CRS_SYNC,I2C1_SDA,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F071*"))
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" "CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC"
|
|
endif
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port F bit 10" "TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port F bit 9" "TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1"
|
|
endif
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,GPIO port bit reset register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 11. " BR11 ,Port F reset bit 11" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 10. " BR10 ,Port F reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port F reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port F reset bit 6" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port F reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port F reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " BR1 ,Port F reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port F reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
elif (cpuis("STM32F071*"))||(cpuis("STM32F072*"))
|
|
tree "GPIO A"
|
|
base ad:0x48000000
|
|
width 15.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOA_MODER,GPIO port A mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOA_OTYPER,GPIO port A mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OT7 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOA_OSPEEDR,GPIO port A output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOA_PUPDR,GPIO port A pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOA_IDR,GPIO port A input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port A input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOA_ODR,GPIO port A output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port A output data" "Low,High"
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "GPIOA_LCKR,GPIO port A configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Port A lock bit" "Not locked,Locked"
|
|
line.long 0x04 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,TSC_G2_IO4,TIM14_CH1,TIM17_CH1,EVENTOUT,COMP2_OUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,TSC_G2_IO3,USART3_CTS,TIM16_CH1,EVENTOUT,COMP1_OUT,?..."
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK/I2S1_CK,CEC,TIM2_CH1_ETR,TSC_G2_IO2,?..."
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,USART2_CK,,TSC_G2_IO1,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TIM15_CH2,USART2_RX,TIM2_CH4,TSC_G1_IO4,?..."
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "TIM15_CH1,USART2_TX,TIM2_CH3,TSC_G1_IO3,,,,COMP2_OUT,?..."
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,TIM2_CH2,TSC_G1_IO2,USART4_RX,TIM15_CH1N,?..."
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,TIM2_CH1_ETR,TSC_G1_IO1,USART4_TX,,,COMP1_OUT,?..."
|
|
line.long 0x08 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,USART2_RX,TIM2_CH1_ETR,EVENTOUT,USART4_RTS,?..."
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
textline " "
|
|
sif (cpuis("STM32F071*"))
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F072*"))
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,USB_NOE,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071*"))
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,TSC_G4_IO4,,,,COMP2_OUT,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F072*"))
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,TSC_G4_IO4,CAN_TX,,,COMP2_OUT,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071*"))
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,TSC_G4_IO3,,,,COMP1_OUT,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F072*"))
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,TSC_G4_IO3,CAN_RX,,,COMP1_OUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,TSC_G4_IO2,?..."
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" "TIM15_BKIN,USART1_TX,TIM1_CH2,TSC_G4_IO1,?..."
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,CRS_SYNC,?..."
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOA_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port A reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port A reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port A reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port A reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port A reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port A reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port A reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port A reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Port A reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port A reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port A reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port A reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port A reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port A reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port A reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port A reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO B"
|
|
base ad:0x48000400
|
|
width 15.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOB_MODER,GPIO port B mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOB_OTYPER,GPIO port B mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OT7 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOB_OSPEEDR,GPIO port B output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOB_PUPDR,GPIO port B pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOB_IDR,GPIO port B input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port B input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOB_ODR,GPIO port B output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port B output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOB_LCKR,GPIO port B configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LCK15 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LCK11 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " LCK4 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LCK3 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port B lock bit" "Not locked,Locked"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,TSC_G5_IO4,USART4_CTS,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,TSC_G5_IO3,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,TSC_G5_IO2,,TIM17_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,TSC_G5_IO1,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" ",,,TSC_G3_IO4,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,TSC_G3_IO3,USART3_RTS,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,TSC_G3_IO2,USART3_CK,?..."
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" "SPI2_MOSI/I2S2_SD,TIM15_CH2,TIM1_CH3N,TIM15_CH1N,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" "SPI2_MISO/I2S2_MCK,TIM15_CH1,TIM1_CH2N,TSC_G6_IO4,USART3_RTS,I2C2_SDA,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" "SPI2_SCK/I2S2_CK,,TIM1_CH1N,TSC_G6_IO3,USART3_CTS,I2C2_SCL,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" "SPI2_NSS/I2S2_WS,EVENTOUT,TIM1_BKIN,TSC_G6_IO2,USART3_CK,TIM15_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" "EVENTOUT,I2C2_SDA,TIM2_CH4,TSC_G6_IO1,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" "CEC,I2C2_SCL,TIM2_CH3,TSC_SYNC,USART3_TX,SPI2_SCK/I2S2_CK,?..."
|
|
textline " "
|
|
sif (cpuis("STM32F071*"))
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "IR_OUT,I2C1_SDA,TIM17_CH1,EVENTOUT,,SPI2_NSS/I2S2_WS,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" "CEC,I2C1_SCL,TIM16_CH1,TSC_SYNC,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F072*"))
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "IR_OUT,I2C1_SDA,TIM17_CH1,EVENTOUT,CAN_TX,SPI2_NSS/I2S2_WS,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" "CEC,I2C1_SCL,TIM16_CH1,TSC_SYNC,CAN_RX,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOB_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port B reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port B reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port B reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port B reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port B reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port B reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port B reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port B reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Port B reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port B reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port B reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port B reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port B reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port B reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port B reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port B reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("STM32F071C*"))||(cpuis("STM32F072C*"))
|
|
tree "GPIO C"
|
|
base ad:0x48000800
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOC_MODER,GPIO port C mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
sif (cpuis("STM32F048T6")||cpuis("STM32F098CC"))
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,,Analog"
|
|
else
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
endif
|
|
line.long 0x04 "GPIOC_OTYPER,GPIO port C mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x04 13. " OT13 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
endif
|
|
line.long 0x08 "GPIOC_OSPEEDR,GPIO port C output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
endif
|
|
line.long 0x0C "GPIOC_PUPDR,GPIO port C pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOC_IDR,GPIO port C input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port C input data" "Low,High"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x00 13. " IDR13 ,Port C input data" "Low,High"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOC_ODR,GPIO port C output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port C output data" "Low,High"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port C output data" "Low,High"
|
|
endif
|
|
sif !cpuis("STM32F058?8")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOC_LCKR,GPIO port C configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port C lock bit" "Not locked,Locked"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x00 13. " LCK13 ,Port C lock bit" "Not locked,Locked"
|
|
endif
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOC_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port C reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port C reset bit 14" "No effect,Reset"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x00 13. " BR13 ,Port C reset bit 13" "No effect,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "GPIO C"
|
|
base ad:0x48000800
|
|
width 15.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOC_MODER,GPIO port C mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOC_OTYPER,GPIO port C mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OT7 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOC_OSPEEDR,GPIO port C output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOC_PUPDR,GPIO port C pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOC_IDR,GPIO port C input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port C input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOC_ODR,GPIO port C output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port C output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port C output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOC_LCKR,GPIO port C configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Port C lock bit" "Not locked,Locked"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "TIM3_CH2,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "TIM3_CH1,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" "TSC_G3_IO1,USART3_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "EVENTOUT,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "EVENTOUT,SPI2_MOSI/I2S2_SD,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "EVENTOUT,SPI2_MISO/I2S2_MCK,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "EVENTOUT,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" "USART4_CK,USART3_CK,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" "USART4_RX,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" "USART4_TX,USART3_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "TIM3_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "TIM3_CH3,?..."
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOC_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port C reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port C reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port C reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port C reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port C reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port C reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port C reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port C reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Port C reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port C reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port C reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port C reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port C reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port C reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port C reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port C reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))||(cpuis("STM32F071R*"))||(cpuis("STM32F072R*"))
|
|
tree "GPIO D"
|
|
base ad:0x48000C00
|
|
width 15.
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*")||cpuis("STM32F078VB")||cpuis("STM32F091V*"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOD_MODER,GPIO port D mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOD_OTYPER,GPIO port D mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OT7 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOD_OSPEEDR,GPIO port D output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOD_PUPDR,GPIO port D pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOD_IDR,GPIO port D input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port D input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOD_ODR,GPIO port D output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port D output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOD_LCKR,GPIO port D configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Port D lock bit" "Not locked,Locked"
|
|
sif (cpuis("STM32F072*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" "USART2_CK,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" "USART2_RX,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" "USART2_TX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port D bit 4" "USART2_RTS,SPI2_MOSI/I2S2_SD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port D bit 3" "USART2_CTS,SPI2_MISO/I2S2_MCK,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "TIM3_ETR,USART3_RTS,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port D bit 1" "CAN_TX,SPI2_SCK/I2S2_CK,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" "CAN_RX,SPI2_NSS/I2S2_WS,?..."
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" "CRS_SYNC,TSC_G8_IO4,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",TSC_G8_IO3,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",TSC_G8_IO2,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" "USART3_RTS,TSC_G8_IO1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" "USART3_CTS,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" "USART3_CK,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" "USART3_RX,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" "USART3_TX,?..."
|
|
elif (cpuis("STM32F071*")||cpuis("STM32F078VB"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" "USART2_CK,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" "USART2_RX,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" "USART2_TX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port D bit 4" "USART2_RTS,SPI2_MOSI/I2S2_SD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port D bit 3" "USART2_CTS,SPI2_MISO/I2S2_MCK,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "TIM3_ETR,USART3_RTS,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port D bit 1" ",SPI2_SCK/I2S2_CK,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" ",SPI2_NSS/I2S2_WS,?..."
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" "CRS_SYNC,TSC_G8_IO4,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",TSC_G8_IO3,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",TSC_G8_IO2,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" "USART3_RTS,TSC_G8_IO1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" "USART3_CTS,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" "USART3_CK,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" "USART3_RX,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" "USART3_TX,?..."
|
|
elif (cpuis("STM32F091V*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" "USART2_CK,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" "USART2_RX,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" "USART2_TX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port D bit 4" "USART2_RTS,SPI2_MOSI/I2S2_SD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port D bit 3" "USART2_CTS,SPI2_MISO/I2S2_MCK,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "TIM3_ETR,USART3_RTS,USART5_RX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port D bit 1" "CAN_TX,SPI2_SCK/I2S2_CK,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" "CAN_RX,SPI2_NSS/I2S2_WS,?..."
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" "CRS_SYNC,TSC_G8_IO4,USART7_CK_RTS,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" "USART8_RX,TSC_G8_IO3,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" "USART8_TX,TSC_G8_IO2,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" "USART3_RTS,TSC_G8_IO1,USART8_CK_RTS,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" "USART3_CTS,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" "USART3_CK,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" "USART3_RX,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" "USART3_TX,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOD_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port D reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port D reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port D reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port D reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port D reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port D reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port D reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port D reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Port D reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port D reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port D reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port D reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port D reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port D reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port D reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port D reset bit 0" "No effect,Reset"
|
|
elif (cpuis("STM32F071R*"))||(cpuis("STM32F072R*"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOD_MODER,GPIO port D mode register"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOD_OTYPER,GPIO port D mode register"
|
|
bitfld.long 0x04 2. " OT2 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOD_OSPEEDR,GPIO port D output speed register"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOD_PUPDR,GPIO port D pull-up/pull-down register"
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOD_IDR,GPIO port D input data register"
|
|
bitfld.long 0x00 2. " IDR2 ,Port D input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOD_ODR,GPIO port D output data register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port D output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOD_LCKR,GPIO port D configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
bitfld.long 0x00 2. " LCK2 ,Port D lock bit" "Not locked,Locked"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "TIM3_ETR,USART3_RTS,?..."
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOD_BRR,Port bit reset register"
|
|
bitfld.long 0x00 2. " BR2 ,Port D reset bit 2" "No effect,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
tree "GPIO E"
|
|
base ad:0x48001000
|
|
width 15.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOE_MODER,GPIO port E mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOE_OTYPER,GPIO port E mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OT7 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOE_OSPEEDR,GPIO port E output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOE_PUPDR,GPIO port E pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOE_IDR,GPIO port E input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port E input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOE_ODR,GPIO port E output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port E output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOE_LCKR,GPIO port E configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Port E lock bit" "Not locked,Locked"
|
|
sif (cpuis("STM32F072*")||cpuis("STM32F078VB"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E bit 7" "TIM1_ETR,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E bit 6" "TIM3_CH4,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E bit 5" "TIM3_CH3,TSC_G7_IO4,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port E bit 4" "TIM3_CH2,TSC_G7_IO3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port E bit 3" "TIM3_CH1,TSC_G7_IO2,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TIM3_ETR,TSC_G7_IO1,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port E bit 1" "TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" "TIM16_CH1,EVENTOUT,?..."
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E bit 15" "TIM1_BKIN,SPI1_MOSI/I2S1_SD,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E bit 14" "TIM1_CH4,SPI1_MISO/I2S1_MCK,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E bit 13" "TIM1_CH3,SPI1_SCK/I2S1_CK,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E bit 12" "TIM1_CH3N,SPI1_NSS/I2S1_WS,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E bit 11" "TIM1_CH2,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E bit 10" "TIM1_CH2N,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E bit 9" "TIM1_CH1,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E bit 8" "TIM1_CH1N,?..."
|
|
elif (cpuis("STM32F071*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E bit 7" "TIM1_ETR,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E bit 6" "TIM3_CH4,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E bit 5" "TIM3_CH3,TSC_G7_IO4,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port E bit 4" "TIM3_CH2,TSC_G7_IO3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port E bit 3" "TIM3_CH1,TSC_G7_IO2,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TIM3_ETR,TSC_G7_IO1,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port E bit 1" "TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" "TIM16_CH1,EVENTOUT,?..."
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E bit 15" "TIM1_BKIN,SPI1_MOSI/I2S1_SD,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E bit 14" "TIM1_CH4,SPI1_MISO/I2S1_MCK,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E bit 13" "TIM1_CH3,SPI1_SCK/I2S1_CK,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E bit 12" "TIM1_CH3N,SPI1_NSS/I2S1_WS,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E bit 11" "TIM1_CH2,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E bit 10" "TIM1_CH2N,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E bit 9" "TIM1_CH1,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E bit 8" "TIM1_CH1N,?..."
|
|
elif (cpuis("STM32F091V*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E bit 7" "TIM1_ETR,USART5_CK_RTS,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E bit 6" "TIM3_CH4,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E bit 5" "TIM3_CH3,TSC_G7_IO4,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port E bit 4" "TIM3_CH2,TSC_G7_IO3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port E bit 3" "TIM3_CH1,TSC_G7_IO2,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TIM3_ETR,TSC_G7_IO1,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port E bit 1" "TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" "TIM16_CH1,EVENTOUT,?..."
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E bit 15" "TIM1_BKIN,SPI1_MOSI/I2S1_SD,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E bit 14" "TIM1_CH4,SPI1_MISO/I2S1_MCK,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E bit 13" "TIM1_CH3,SPI1_SCK/I2S1_CK,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E bit 12" "TIM1_CH3N,SPI1_NSS/I2S1_WS,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E bit 11" "TIM1_CH2,USART5_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E bit 10" "TIM1_CH2N,USART5_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E bit 9" "TIM1_CH1,USART4_RX,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E bit 8" "TIM1_CH1N,USART4_TX,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOE_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port E reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port E reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port E reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port E reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port E reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port E reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port E reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port E reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Port E reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port E reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port E reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port E reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port E reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port E reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port E reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port E reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "GPIO F"
|
|
base ad:0x48001400
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F mode register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x04 11. " OT11 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x04 10. " OT10 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 11. " IDR11 ,Port F input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 10. " IDR10 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port F input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOF_ODR,GPIO port F output data register"
|
|
sif (cpuis("STM32F042C*"))
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port F output data" "Low,High"
|
|
sif !CPUIS("STM32F031E6")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOF_LCKR,GPIO port F configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
textline " "
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 11. " LCK11 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 10. " LCK10 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LCK3 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " LCK1 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port F lock bit" "Not locked,Locked"
|
|
endif
|
|
sif (!cpuis("STM32F031*"))&&(!cpuis("STM32F050*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port F bit 3" "EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port F bit 2" "EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F042*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F bit 1" ",I2C1_SCL,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" "CRS_SYNC,I2C1_SDA,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F071*"))
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" "CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC"
|
|
endif
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port F bit 10" "TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port F bit 9" "TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1"
|
|
endif
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,GPIO port bit reset register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 11. " BR11 ,Port F reset bit 11" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 10. " BR10 ,Port F reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port F reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port F reset bit 6" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port F reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port F reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " BR1 ,Port F reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port F reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
elif (cpuis("STM32F050*"))
|
|
tree "GPIO A"
|
|
base ad:0x48000000
|
|
width 15.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOA_MODER,GPIO port A mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOA_OTYPER,GPIO port A mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 5. " OT5 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 3. " OT3 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 1. " OT1 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOA_OSPEEDR,GPIO port A output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOA_PUPDR,GPIO port A pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOA_IDR,GPIO port A input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " IDR5 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 3. " IDR3 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IDR1 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port A input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOA_ODR,GPIO port A output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port A output data" "Low,High"
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "GPIOA_LCKR,GPIO port A configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " LCK4 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LCK2 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port A lock bit" "Not locked,Locked"
|
|
line.long 0x04 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,,,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK/I2S1_CK,,TIM2_CH1_ETR,?..."
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,USART1_RTS,,,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",USART1_CTS,TIM2_CH4,?..."
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",USART1_RX,TIM2_CH3,?..."
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART1_TX,TIM2_CH2,?..."
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART1_CKS,TIM2_CH1_ETR,?..."
|
|
line.long 0x08 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,USART1_RX,TIM2_CH1_ETR,EVENTOUT,?..."
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART1_TX,?..."
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDAT,IR_OUT,?..."
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,,I2C1_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",USART1_TX,TIM1_CH2,,I2C1_SCL,?..."
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOA_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port A reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port A reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port A reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port A reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port A reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port A reset bit 8" "No effect,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port A reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port A reset bit 6" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BR5 ,Port A reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port A reset bit 4" "No effect,Reset"
|
|
bitfld.long 0x00 3. " BR3 ,Port A reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port A reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BR1 ,Port A reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port A reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO B"
|
|
base ad:0x48000400
|
|
width 15.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOB_MODER,GPIO port B mode register"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOB_OTYPER,GPIO port B mode register"
|
|
bitfld.long 0x04 7. " OT7 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOB_OSPEEDR,GPIO port B output speed register"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOB_PUPDR,GPIO port B pull-up/pull-down register"
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOB_IDR,GPIO port B input data register"
|
|
bitfld.long 0x00 7. " IDR7 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port B input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOB_ODR,GPIO port B output data register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port B output data" "Low,High"
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "GPIOB_LCKR,GPIO port B configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
bitfld.long 0x00 7. " LCK7 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port B lock bit" "Not locked,Locked"
|
|
line.long 0x04 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,?..."
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,?..."
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,?..."
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,?..."
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,?..."
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,?..."
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOB_BRR,Port bit reset register"
|
|
bitfld.long 0x00 7. " BR7 ,Port B reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port B reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port B reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port B reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port B reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port B reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port B reset bit 0" "No effect,Reset"
|
|
width 0xB
|
|
tree.end
|
|
tree "GPIO F"
|
|
base ad:0x48001400
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F mode register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x04 11. " OT11 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x04 10. " OT10 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 11. " IDR11 ,Port F input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 10. " IDR10 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port F input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOF_ODR,GPIO port F output data register"
|
|
sif (cpuis("STM32F042C*"))
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port F output data" "Low,High"
|
|
sif !CPUIS("STM32F031E6")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOF_LCKR,GPIO port F configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
textline " "
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 11. " LCK11 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 10. " LCK10 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LCK3 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " LCK1 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port F lock bit" "Not locked,Locked"
|
|
endif
|
|
sif (!cpuis("STM32F031*"))&&(!cpuis("STM32F050*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port F bit 3" "EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port F bit 2" "EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F042*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F bit 1" ",I2C1_SCL,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" "CRS_SYNC,I2C1_SDA,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F071*"))
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" "CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC,CRS_SYNC"
|
|
endif
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port F bit 10" "TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2,TIM15_CH2"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port F bit 9" "TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1,TIM15_CH1"
|
|
endif
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,GPIO port bit reset register"
|
|
sif (cpuis("STM32F042C*"))
|
|
bitfld.long 0x00 11. " BR11 ,Port F reset bit 11" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*"))
|
|
bitfld.long 0x00 10. " BR10 ,Port F reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port F reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port F reset bit 6" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port F reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port F reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " BR1 ,Port F reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port F reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
sif (!cpuis("STM32F038?6")&&!cpuis("STM32F058?8")&&!cpuis("STM32F078?B")&&!cpuis("STM32F091*")&&!cpuis("STM32F098*")&&!cpuis("STM32F048*"))
|
|
tree "GPIO A"
|
|
base ad:0x48000000
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOA_MODER,GPIO port A mode register"
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOA_OTYPER,GPIO port A mode register"
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x04 15. " OT15 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 14. " OT14 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x04 8. " OT8 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 7. " OT7 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOA_OSPEEDR,GPIO port A output speed register"
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOA_PUPDR,GPIO port A pull-up/pull-down register"
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOA_IDR,GPIO port A input data register"
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x00 15. " IDR15 ,Port A input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " IDR14 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port A input data" "Low,High"
|
|
textline " "
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x00 8. " IDR8 ,Port A input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " IDR7 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port A input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOA_ODR,GPIO port A output data register"
|
|
sif !cpuis("STM32F070F6")
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
sif !cpuis("STM32F070F6")
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port A output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOA_LCKR,GPIO port A configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
textline " "
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x00 15. " LCK15 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " LCK14 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Port A lock bit" "Not locked,Locked"
|
|
sif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,,,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK/I2S1_CK,,TIM2_CH1_ETR,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,,,,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",,TIM2_CH4,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",,TIM2_CH3,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,,TIM2_CH2,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",,TIM2_CH1_ETR,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,,TIM2_CH1_ETR,EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDAT,IR_OUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",USART1_TX,TIM1_CH2,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO,TIM3_CH1,TIM1_BKIN,,USART3_CTS,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS,USART2_CK,,,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TIM15_CH2,USART2_RX,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "TIM15_CH1,USART2_TX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,,,USART4_RX,TIM15_CH1N,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,,,USART4_TX,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS,USART2_RX,,EVENTOUT,USART4_RTS,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,USB_NOE,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,,I2C1_SDA,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" "TIM15_BKIN,USART1_TX,TIM1_CH2,,I2C1_SCL,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
elif cpuis("STM32F070C6")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO,TIM3_CH1,TIM1_BKIN,,,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS,USART2_CK,USB_NOE,,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",USART2_RX,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",USART2_TX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,USB_NOE,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,,I2C1_SDA,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",USART1_TX,TIM1_CH2,,I2C1_SCL,?..."
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO,TIM3_CH1,TIM1_BKIN,,USART3_CTS,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK,,,,,USART6_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS,USART2_CK,,,TIM14_CH1,USART6_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TIM15_CH1N,USART2_RX,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "TIM15_CH1,USART2_TX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,,,USART4_RX,TIM15_CH1N,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,,,USART4_TX,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS,USART2_RX,,EVENTOUT,USART4_RTS,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,,,I2C_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,,,I2C_SCL,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,,I2C1_SDA,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" "TIM15_BKIN,USART1_TX,TIM1_CH2,,I2C1_SCL,MCO,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
elif cpuis("STM32F030C8")||cpuis("STM32F030R8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO,TIM3_CH1,TIM1_BKIN,,,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS,USART2_CK,,,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TIM15_CH1N,USART2_RX,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "TIM15_CH1,USART2_TX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS,USART2_RX,,EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,,,I2C_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,,,I2C_SCL,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" "TIM15_BKIN,USART1_TX,TIM1_CH2,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
elif cpuis("STM32F030C6")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO,TIM3_CH1,TIM1_BKIN,,,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS,USART1_CK,,,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",USART1_RX,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",USART1_TX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART1_RTS,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART1_CTS,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS,USART1_RX,,EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART1_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,,,I2C_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,,,I2C_SCL,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,,I2C1_SDA,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",USART1_TX,TIM1_CH2,,I2C1_SCL,,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
elif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")||cpuis("STM32F038?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,TSC_G2_IO4,TIM14_CH1,TIM17_CH1,EVENTOUT,COMP2_OUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,TSC_G2_IO3,,TIM16_CH1,EVENTOUT,COMP1_OUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK/I2S1_CK,CEC,TIM2_CH1_ETR,TSC_G2_IO2,?..."
|
|
textline " "
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051R4"||CPU()=="STM32F051K4")||cpuis("STM32F038?6")
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,,,TSC_G2_IO1,TIM14_CH1,?..."
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TIM15_CH2,,TIM2_CH4,TSC_G1_IO4,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "TIM15_CH1,,TIM2_CH3,TSC_G1_IO3,,,,COMP2_OUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,,TIM2_CH2,TSC_G1_IO2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",,TIM2_CH1_ETR,TSC_G1_IO1,,,,COMP1_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,USART2_CK,,TSC_G2_IO1,TIM14_CH1,?..."
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TIM15_CH2,USART2_RX,TIM2_CH4,TSC_G1_IO4,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "TIM15_CH1,USART2_TX,TIM2_CH3,TSC_G1_IO3,,,,COMP2_OUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,TIM2_CH2,TSC_G1_IO2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,TIM2_CH1_ETR,TSC_G1_IO1,,,,COMP1_OUT,?..."
|
|
endif
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051R4"||CPU()=="STM32F051K4")||cpuis("STM32F038?6")
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,,TIM2_CH1_ETR,EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDAT,IR_OUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,TSC_G4_IO4,,,,COMP2_OUT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,USART2_RX,TIM2_CH1_ETR,EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDAT,IR_OUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,TSC_G4_IO4,,,,COMP2_OUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,TSC_G4_IO3,,,,COMP1_OUT,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,TSC_G4_IO2,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" "TIM15_BKIN,USART1_TX,TIM1_CH2,TSC_G4_IO1,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
elif cpuis("STM32F051T8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,TSC_G2_IO4,TIM14_CH1,TIM17_CH1,EVENTOUT,COMP2_OUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,TSC_G2_IO3,,TIM16_CH1,EVENTOUT,COMP1_OUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK/I2S1_CK,CEC,TIM2_CH1_ETR,TSC_G2_IO2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,USART2_CK,,TSC_G2_IO1,TIM14_CH1,?..."
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TIM15_CH2,USART2_RX,TIM2_CH4,TSC_G1_IO4,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "TIM15_CH1,USART2_TX,TIM2_CH3,TSC_G1_IO3,,,,COMP2_OUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,TIM2_CH2,TSC_G1_IO2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,TIM2_CH1_ETR,TSC_G1_IO1,,,,COMP1_OUT,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,USART2_RX,TIM2_CH1_ETR,EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,TSC_G4_IO4,,,,COMP2_OUT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,TSC_G4_IO3,,,,COMP1_OUT,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,TSC_G4_IO2,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" "TIM15_BKIN,USART1_TX,TIM1_CH2,TSC_G4_IO1,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
elif cpuis("STM32F070F6")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO,TIM3_CH1,TIM1_BKIN,,,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS,USART2_CK,USB_NOE,,TIM14_CH1,?..."
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",USART2_RX,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",USART2_TX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS,USART2_RX,,EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,USB_NOE,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,,I2C1_SDA,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",USART1_TX,TIM1_CH2,,I2C1_SCL,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOA_BRR,Port bit reset register"
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x00 15. " BR15 ,Port A reset bit 15" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14. " BR14 ,Port A reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port A reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port A reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port A reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port A reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port A reset bit 9" "No effect,Reset"
|
|
textline " "
|
|
sif !cpuis("STM32F070F6")
|
|
bitfld.long 0x00 8. " BR8 ,Port A reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " BR7 ,Port A reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port A reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port A reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port A reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port A reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port A reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port A reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port A reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
sif (CPU()=="STM32F050K4"||CPU()=="STM32F050K6"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||cpuis("STM32F051T8"))
|
|
tree "GPIO B"
|
|
base ad:0x48000400
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOB_MODER,GPIO Port B Mode Register"
|
|
sif !CPUIS("STM32F051T8")
|
|
bitfld.long 0x00 30.--31. " MODER8 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28.--29. " MODER7 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER6 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER5 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER4 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER3 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER2 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER1 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MODER0 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOB_OTYPER,GPIO Port B Mode Register"
|
|
sif !CPUIS("STM32F051T8")
|
|
bitfld.long 0x04 31. " OT8 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 30. " OT7 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 29. " OT6 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 28. " OT5 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 27. " OT4 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 26. " OT3 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 25. " OT2 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 24. " OT1 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 23. " OT0 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOB_OSPEEDR,GPIO Port B Output Speed Register"
|
|
sif !CPUIS("STM32F051T8")
|
|
bitfld.long 0x08 30.--31. " OSPEEDR8 ,GPIO port B output speed register" "2-mhz,2-mhz,10-mhz,50-mhz"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 28.--29. " OSPEEDR7 ,GPIO port B output speed register" "2-mhz,2-mhz,10-mhz,50-mhz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR6 ,GPIO port B output speed register" "2-mhz,2-mhz,10-mhz,50-mhz"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR5 ,GPIO port B output speed register" "2-mhz,2-mhz,10-mhz,50-mhz"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR4 ,GPIO port B output speed register" "2-mhz,2-mhz,10-mhz,50-mhz"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR3 ,GPIO port B output speed register" "2-mhz,2-mhz,10-mhz,50-mhz"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR2 ,GPIO port B output speed register" "2-mhz,2-mhz,10-mhz,50-mhz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR1 ,GPIO port B output speed register" "2-mhz,2-mhz,10-mhz,50-mhz"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " OSPEEDR0 ,GPIO port B output speed register" "2-mhz,2-mhz,10-mhz,50-mhz"
|
|
line.long 0x0C "GPIOB_PUPDR,GPIO Port B pull-up/pull-down Register"
|
|
sif !CPUIS("STM32F051T8")
|
|
bitfld.long 0x0C 30.--31. " PUPDR8 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 28.--29. " PUPDR7 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR6 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " PUPDR5 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR4 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR3 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR2 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR1 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " PUPDR0 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOB_IDR,GPIO Port B Input Data Register"
|
|
sif !CPUIS("STM32F051T8")
|
|
bitfld.long 0x00 31. " IDR8 ,Port B input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 30. " IDR7 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 29. " IDR6 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 28. " IDR5 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IDR4 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 26. " IDR3 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 25. " IDR2 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 24. " IDR1 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IDR0 ,Port B input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOB_ODR,GPIO Port B Output Data Register"
|
|
sif !CPUIS("STM32F051T8")
|
|
setclrfld.long 0x00 31. 0x04 23. 0x04 7. " ODR8_SET/CLR ,Port B output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 30. 0x04 24. 0x04 8. " ODR7_SET/CLR ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 25. 0x04 9. " ODR6_SET/CLR ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 26. 0x04 10. " ODR5_SET/CLR ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x04 11. " ODR4_SET/CLR ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 28. 0x04 12. " ODR3_SET/CLR ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 29. 0x04 13. " ODR2_SET/CLR ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 30. 0x04 14. " ODR1_SET/CLR ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 31. 0x04 15. " ODR0_SET/CLR ,Port B output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOB_LCKR,GPIO Port B Configuration Lock Register"
|
|
bitfld.long 0x00 31. " LCKK ,Lock key" "Not activated,Activated"
|
|
textline " "
|
|
sif !CPUIS("STM32F051T8")
|
|
bitfld.long 0x00 30. " LCK8 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " LCK7 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " LCK6 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " LCK5 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " LCK4 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 25. " LCK3 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " LCK2 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LCK1 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 15. " LCK0 ,Port B lock bit" "Not locked,Locked"
|
|
sif (CPU()=="STM32F050K4"||CPU()=="STM32F050K6")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,?..."
|
|
bitfld.long 0x00 12.--15. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,?..."
|
|
line.long 0x04 "GPIOB_AFRH,GPIO Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH8 ,Alternate function selection for port B bit 8" ",I2C1_SCL,TIM16_CH1,?..."
|
|
elif (CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8")||cpuis("STM32F038k6")||cpuis("STM32F038k6")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,TSC_G5_IO4,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,TSC_G5_IO3,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,TSC_G5_IO2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,TSC_G5_IO1,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" ",,,TSC_G3_IO4,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,TSC_G3_IO3,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,TSC_G3_IO2,?..."
|
|
line.long 0x04 "GPIOB_AFRH,GPIO Alternate Function High Register"
|
|
bitfld.long 0x04 28.--31. " AFRH8 ,Alternate function selection for port B bit 8" "CEC,I2C1_SCL,TIM16_CH1,TSC_SYNC,?..."
|
|
elif CPUIS("STM32F051T8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,TSC_G5_IO4,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,TSC_G5_IO3,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,TSC_G5_IO2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,TSC_G5_IO1,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" ",,,TSC_G3_IO4,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,TSC_G3_IO3,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,TSC_G3_IO2,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOB_BRR,Port Bit Reset Register"
|
|
sif !CPUIS("STM32F051T8")
|
|
bitfld.long 0x00 31. " BR8 ,Port B reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 30. " BR7 ,Port B reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 29. " BR6 ,Port B reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 28. " BR5 ,Port B reset bit 5" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BR4 ,Port B reset bit 4" "No effect,Reset"
|
|
bitfld.long 0x00 26. " BR3 ,Port B reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 25. " BR2 ,Port B reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 24. " BR1 ,Port B reset bit 1" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 23. " BR0 ,Port B reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "GPIO B"
|
|
base ad:0x48000400
|
|
width 15.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOB_MODER,GPIO port B mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOB_OTYPER,GPIO port B mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OT7 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOB_OSPEEDR,GPIO port B output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOB_PUPDR,GPIO port B pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOB_IDR,GPIO port B input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port B input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOB_ODR,GPIO port B output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port B output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOB_LCKR,GPIO port B configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Port B lock bit" "Not locked,Locked"
|
|
sif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,?..."
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" ",,TIM1_CH3N,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" ",,TIM1_CH2N,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" ",,TIM1_CH1N,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" ",EVENTOUT,TIM1_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" "EVENTOUT,,TIM2_CH4,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" ",,TIM2_CH3,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "IR_OUT,I2C1_SDA,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",I2C1_SCL,TIM16_CH1,?..."
|
|
elif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,TSC_G5_IO4,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,TSC_G5_IO3,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,TSC_G5_IO2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,TSC_G5_IO1,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" ",,,TSC_G3_IO4,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,TSC_G3_IO3,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,TSC_G3_IO2,?..."
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
sif (CPU()=="STM32F051C8"||CPU()=="STM32F051R8")
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" "SPI2_MOSI,TIM15_CH2,TIM1_CH3N,TIM15_CH1N,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" "SPI2_MISO,TIM15_CH1,TIM1_CH2N,TSC_G6_IO4,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" "SPI2_SCK,,TIM1_CH1N,TSC_G6_IO3,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" "SPI2_NSS,EVENTOUT,TIM1_BKIN,TSC_G6_IO2,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" "EVENTOUT,I2C2_SDA,TIM2_CH4,TSC_G6_IO1,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" "CEC,I2C2_SCL,TIM2_CH3,TSC_SYNC,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" ",TIM15_CH2,TIM1_CH3N,TIM15_CH1N,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" ",TIM15_CH1,TIM1_CH2N,TSC_G6_IO4,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" ",,TIM1_CH1N,TSC_G6_IO3,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" ",EVENTOUT,TIM1_BKIN,TSC_G6_IO2,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" "EVENTOUT,,TIM2_CH4,TSC_G6_IO1,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" "CEC,,TIM2_CH3,TSC_SYNC,?..."
|
|
endif
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "IR_OUT,I2C1_SDA,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" "CEC,I2C1_SCL,TIM16_CH1,TSC_SYNC,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOB_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port B reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port B reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port B reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port B reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port B reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port B reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port B reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port B reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Port B reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port B reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port B reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port B reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port B reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port B reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port B reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port B reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8"||cpuis("STM32F051T8"))
|
|
tree "GPIO C"
|
|
base ad:0x48000800
|
|
width 18.
|
|
sif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||cpuis("STM32F098CC")||CPUIS("STM32F051T8")||CPUIS("STM32F030CC")||CPUIS("STM32F030C6")||CPUIS("STM32F030C8")||CPUIS("STM32F030R8")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOC_MODER,GPIO Port C Mode Register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif !cpuis("STM32F098CC")
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
endif
|
|
line.long 0x04 "GPIOC_OTYPER,GPIO port C mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif !cpuis("STM32F098CC")
|
|
bitfld.long 0x04 13. " OT13 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
endif
|
|
line.long 0x08 "GPIOC_OSPEEDR,GPIO Port C Output Speed Register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOC_PUPDR,GPIO port C pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
sif !cpuis("STM32F098CC")
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOC_IDR,GPIO Port C Input Data Register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port C input data" "Low,High"
|
|
textline " "
|
|
sif !cpuis("STM32F098CC")
|
|
bitfld.long 0x00 13. " IDR13 ,Port C input data" "Low,High"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOC_ODR,GPIO Port C Output Data Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port C output data" "Low,High"
|
|
textline " "
|
|
sif !cpuis("STM32F098CC")
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port C output data" "Low,High"
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOC_BRR,GPIO Port Bit Reset Register"
|
|
bitfld.long 0x00 15. " BR15 ,Port C reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port C reset bit 14" "No effect,Reset"
|
|
textline " "
|
|
sif !cpuis("STM32F098CC")
|
|
bitfld.long 0x00 13. " BR13 ,Port C reset bit 13" "No effect,Reset"
|
|
endif
|
|
else
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOC_MODER,GPIO Port C Mode Register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOC_OTYPER,GPIO Port C Mode Register"
|
|
bitfld.long 0x04 15. " OT15 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OT7 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOC_OSPEEDR,GPIO Port C Output Speed Register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOC_PUPDR,GPIO Port C Pull-up/Pull-down Register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOC_IDR,GPIO Port C Input Data Register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port C input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOC_ODR,GPIO Port C Output Data Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr ,Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port C output data" "Low,High"
|
|
sif (cpuis("STM32F078RB")||cpuis("STM32F078VB"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "TIM3_CH2,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "TIM3_CH1,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" "TSC_G3_IO1,USART3_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "EVENTOUT,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "EVENTOUT,SPI2_MOSI/I2S2_SD,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "EVENTOUT,SPI2_MISO/I2S2_MCK,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "EVENTOUT,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" "USART4_CK,USART3_CK,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" "USART4_RX,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" "USART4_TX,USART3_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "TIM3_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "TIM3_CH3,?..."
|
|
elif CPUIS("STM32F030RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "TIM3_CH2,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "TIM3_CH1,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",USART3_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "EVENTOUT,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "EVENTOUT,SPI2_MOS,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "EVENTOUT,SPI2_MISO,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "EVENTOUT,,USART6_RX,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "EVENTOUT,,USART6_TX,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO Alternate Function High Register"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" "USART4_CK,USART3_CK,USART5_TX,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" "USART4_RX,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" "USART4_TX,USART3_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "TIM3_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "TIM3_CH3,?..."
|
|
elif (cpuis("STM32F091R*")||cpuis("STM32F091V*")||cpuis("STM32F098RC"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "TIM3_CH2,USART7_RX,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "TIM3_CH1,USART7_TX,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" "TSC_G3_IO1,USART3_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "EVENTOUT,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "EVENTOUT,SPI2_MOSI/I2S2_SD,USART8_RX,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "EVENTOUT,SPI2_MISO/I2S2_MCK,USART8_TX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "EVENTOUT,USART7_RX,USART6_RX,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "EVENTOUT,USART7_TX,USART6_TX,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" "USART4_CK,USART3_CK,USART5_TX,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" "USART4_RX,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" "USART4_TX,USART3_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "TIM3_CH4,USART8_RX,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "TIM3_CH3,USART8_TX,?..."
|
|
elif (cpuis("STM32F058R8"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "TIM3_CH2,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "TIM3_CH1,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" "TSC_G3_IO1,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "EVENTOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "EVENTOUT,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "EVENTOUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "EVENTOUT,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "TIM3_CH4,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "TIM3_CH3,?..."
|
|
elif CPUIS("STM32F070RB")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "TIM3_CH2,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "TIM3_CH1,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",USART3_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "EVENTOUT,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "EVENTOUT,SPI2_MOSI,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "EVENTOUT,SPI2_MISO,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "EVENTOUT,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO Alternate Function High Register"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" "USART4_CK,USART3_CK,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" "USART4_RX,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" "USART4_TX,USART3_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "TIM3_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "TIM3_CH3,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOC_BRR,GPIO Port Bit Reset Register"
|
|
bitfld.long 0x00 15. " BR15 ,Port C reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port C reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port C reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port C reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port C reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port C reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port C reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port C reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Port C reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port C reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port C reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port C reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port C reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port C reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port C reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port C reset bit 0" "No effect,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")
|
|
tree "GPIO D"
|
|
base ad:0x48000C00
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOD_MODER,GPIO port D mode register"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOD_OTYPER,GPIO port D mode register"
|
|
bitfld.long 0x04 2. " OT2 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOD_OSPEEDR,GPIO port D output speed register"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOD_PUPDR,GPIO port D pull-up/pull-down register"
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOD_IDR,GPIO port D input data register"
|
|
bitfld.long 0x00 2. " IDR2 ,Port D input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOD_ODR,GPIO port D output data register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port D output data" "Low,High"
|
|
sif (cpuis("STM32F058R8")||CPUIS("STM32F070RB"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " ARFL2 ,Alternate function selection for port D bit 2" "TIM3_ETR,?..."
|
|
elif (cpuis("STM32F078R8"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " ARFL2 ,Alternate function selection for port D bit 2" "TIM3_ETR,USART3_RTS,?..."
|
|
elif (cpuis("STM32F091R*")||cpuis("STM32F098RC")||CPUIS("STM32F030RC"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " ARFL2 ,Alternate function selection for port D bit 2" "TIM3_ETR,USART3_RTS,USART5_RX,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOD_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 2. " BR2 ,Port D reset bit 2" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "GPIO F"
|
|
base ad:0x48001400
|
|
width 18.
|
|
sif (cpuis("STM32F078VB")||cpuis("STM32F091V*"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F mode register"
|
|
bitfld.long 0x04 10. " OT10 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 3. " OT3 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 2. " OT2 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
bitfld.long 0x00 10. " IDR10 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 3. " IDR3 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDR2 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOF_ODR,GPIO port F output data register"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR6_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR5_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR4_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port F output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOF_LCKR,GPIO port F configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
bitfld.long 0x00 10. " LCK10 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LCK3 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port F lock bit" "Not locked,Locked"
|
|
sif (cpuis("STM32F091V*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port F bit 3" "EVENTOUT,USART7_RX,USART6_CK_RTS,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port F bit 2" "EVENTOUT,USART7_TX,USART7_CK_RTS,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F bit 1" ",I2C1_SCL,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" "CRS_SYNC,I2C1_SDA,?..."
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port F bit 10" "TIM15_CH2,USART6_RX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port F bit 9" "TIM15_CH1,USART6_TX,?..."
|
|
endif
|
|
sif (cpuis("STM32F078VB"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port F bit 3" "EVENTOUT,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port F bit 2" "EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" "CRS_SYNC,?..."
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port F bit 10" "TIM15_CH2,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port F bit 9" "TIM15_CH1,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 10. " BR10 ,Port F reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port F reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port F reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 3. " BR3 ,Port F reset bit 3" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BR2 ,Port F reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port F reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port F reset bit 0" "No effect,Reset"
|
|
elif (cpu()=="STM32F051R4"||cpu()=="STM32F051R6"||cpu()=="STM32F051R8"||cpuis("STM32F058R8")||cpuis("STM32F030R8"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F mode register"
|
|
bitfld.long 0x04 7. " OT7 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
bitfld.long 0x00 7. " IDR7 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOF_ODR,GPIO port F output data register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port F output data" "Low,High"
|
|
sif (cpuis("STM32F058R8"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port F bit 7" "I2C2_SDA,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port F bit 6" "I2C2_SCL,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port F bit 5" "EVENTOUT,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port F bit 4" "EVENTOUT,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 7. " BR7 ,Port F reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port F reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port F reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port F reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BR1 ,Port F reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port F reset bit 0" "No effect,Reset"
|
|
elif (cpu()=="STM32F050C4"||cpu()=="STM32F050C6"||cpu()=="STM32F051C4"||cpu()=="STM32F051C6"||cpu()=="STM32F051C8"||cpuis("STM32F038C6")||cpuis("STM32F058C8"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F mode register"
|
|
bitfld.long 0x04 7. " OT7 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
bitfld.long 0x00 7. " IDR7 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOF_ODR,GPIO port F output data register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port F output data" "Low,High"
|
|
sif (cpuis("STM32F038C6"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port F bit 7" "I2C1_SCL,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port F bit 6" "I2C1_SDA,?..."
|
|
elif (cpuis("STM32F058C8"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port F bit 7" "I2C1_SCL,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port F bit 6" "I2C1_SDA,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 7. " BR7 ,Port F reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port F reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port F reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port F reset bit 0" "No effect,Reset"
|
|
else
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
sif (cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F mode register"
|
|
sif (cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
bitfld.long 0x04 11. " OT11 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
sif (cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
sif (cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
sif (cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
bitfld.long 0x00 11. " IDR11 ,Port F input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOF_ODR,GPIO port F output data register"
|
|
sif (cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port F output data" "Low,High"
|
|
sif !cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F031E6")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070RB")&&!cpuis("STM32F070F6")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOF_LCKR,GPIO port F configuration lock register"
|
|
bitfld.long 0x00 1. " LCK1 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port F lock bit" "Not locked,Locked"
|
|
endif
|
|
sif (cpuis("STM32F048G6")||cpuis("STM32F048T6")||cpuis("STM32F091C*")||cpuis("STM32F091R*")||cpuis("STM32F098CC")||cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F bit 1" "CRS_SYNC,I2C1_SDA,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" ",I2C1_SCL,?..."
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F bit 1" ",I2C1_SCL,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" ",I2C1_SDA,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 1. " BR1 ,Port F reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port F reset bit 0" "No effect,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F038?6")||cpuis("STM32F058?8")||cpuis("STM32F048?6")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*"))
|
|
sif (cpuis("STM32F038?6"))
|
|
tree "GPIO A"
|
|
base ad:0x48000000
|
|
width 18.
|
|
sif (cpuis("STM32F038K6")||cpuis("STM32F038C6"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOA_MODER,GPIO port A mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOA_OTYPER,GPIO port A mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OT7 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOA_OSPEEDR,GPIO port A output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOA_PUPDR,GPIO port A pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOA_IDR,GPIO port A input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port A input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOA_ODR,GPIO port A output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port A output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOA_LCKR,GPIO port A configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Port A lock bit" "Not locked,Locked"
|
|
elif (cpuis("STM32F038G6"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOA_MODER,GPIO port A mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOA_OTYPER,GPIO port A mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 5. " OT5 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 3. " OT3 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 1. " OT1 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOA_OSPEEDR,GPIO port A output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOA_PUPDR,GPIO port A pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOA_IDR,GPIO port A input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " IDR5 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 3. " IDR3 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IDR1 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port A input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOA_ODR,GPIO port A output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port A output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOA_LCKR,GPIO port A configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " LCK4 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LCK2 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port A lock bit" "Not locked,Locked"
|
|
elif CPUIS("STM32F038E6")
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOA_MODER,GPIO port A mode register"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOA_OTYPER,GPIO port A mode register"
|
|
bitfld.long 0x04 14. " OT14 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 10. " OT10 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 5. " OT5 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 3. " OT3 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 1. " OT1 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOA_OSPEEDR,GPIO port A output speed register"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOA_PUPDR,GPIO port A pull-up/pull-down register"
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOA_IDR,GPIO port A input data register"
|
|
bitfld.long 0x00 14. " IDR14 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IDR10 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port A input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOA_ODR,GPIO port A output data register"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port A output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOA_LCKR,GPIO port A configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
bitfld.long 0x00 14. " LCK14 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " LCK4 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LCK2 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port A lock bit" "Not locked,Locked"
|
|
elif (cpuis("STM32F038F6"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOA_MODER,GPIO port A mode register"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOA_OTYPER,GPIO port A mode register"
|
|
bitfld.long 0x04 14. " OT14 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 10. " OT10 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 5. " OT5 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 3. " OT3 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 1. " OT1 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOA_OSPEEDR,GPIO port A output speed register"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOA_PUPDR,GPIO port A pull-up/pull-down register"
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOA_IDR,GPIO port A input data register"
|
|
bitfld.long 0x00 14. " IDR14 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port A input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOA_ODR,GPIO port A output data register"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port A output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOA_LCKR,GPIO port A configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
bitfld.long 0x00 14. " LCK14 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LCK11 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " LCK4 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LCK2 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port A lock bit" "Not locked,Locked"
|
|
endif
|
|
sif (cpuis("STM32F038K6")||cpuis("STM32F038C6"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,,,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK/I2S1_CK,,TIM2_CH1_ETR,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,USART1_CK,,,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",USART1_RX,TIM2_CH4,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",USART1_TX,TIM2_CH3,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART1_RTS,TIM2_CH2,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART1_CTS,TIM2_CH1_ETR,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,USART1_RX,TIM2_CH1_ETR,EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART1_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,,I2C1_SDA,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",USART1_TX,TIM1_CH2,,I2C1_SCL,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOA_BRR,GPIO Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port A reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port A reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port A reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port A reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port A reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port A reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port A reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port A reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Port A reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port A reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port A reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port A reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port A reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port A reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port A reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port A reset bit 0" "No effect,Reset"
|
|
elif (cpuis("STM32F038G6"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,,,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK/I2S1_CK,,TIM2_CH1_ETR,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,USART1_CK,,,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",USART1_RX,TIM2_CH4,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",USART1_TX,TIM2_CH3,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART1_RTS,TIM2_CH2,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART1_CTS,TIM2_CH1_ETR,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,USART1_RX,TIM2_CH1_ETR,EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART1_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,,I2C1_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",USART1_TX,TIM1_CH2,,I2C1_SCL,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOA_BRR,GPIO Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port A reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port A reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port A reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port A reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port A reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port A reset bit 8" "No effect,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port A reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port A reset bit 6" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BR5 ,Port A reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port A reset bit 4" "No effect,Reset"
|
|
bitfld.long 0x00 3. " BR3 ,Port A reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port A reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BR1 ,Port A reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port A reset bit 0" "No effect,Reset"
|
|
elif (cpuis("STM32F038F6"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,,,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK/I2S1_CK,,TIM2_CH1_ETR,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,USART1_CK,,,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",USART1_RX,TIM2_CH4,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",USART1_TX,TIM2_CH3,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART1_RTS,TIM2_CH2,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART1_CTS,TIM2_CH1_ETR,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART1_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,,I2C1_SDA,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",USART1_TX,TIM1_CH2,,I2C1_SCL,?..."
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOA_BRR,GPIO Port bit reset register"
|
|
bitfld.long 0x00 14. " BR14 ,Port A reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port A reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port A reset bit 12" "No effect,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port A reset bit 11" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BR10 ,Port A reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port A reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port A reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port A reset bit 6" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BR5 ,Port A reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port A reset bit 4" "No effect,Reset"
|
|
bitfld.long 0x00 3. " BR3 ,Port A reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port A reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BR1 ,Port A reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port A reset bit 0" "No effect,Reset"
|
|
elif CPUIS("STM32F038E6")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,,,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK/I2S1_CK,,TIM2_CH1_ETR,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,USART1_CK,,,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",USART1_RX,TIM2_CH4,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",USART1_TX,TIM2_CH3,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART1_RTS,TIM2_CH2,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART1_CTS,TIM2_CH1_ETR,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO Alternate Function High Register"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART1_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,,I2C1_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",USART1_TX,TIM1_CH2,,I2C1_SCL,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOA_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 14. " BR14 ,Port A reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port A reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port A reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port A reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port A reset bit 8" "No effect,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port A reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port A reset bit 6" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BR5 ,Port A reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port A reset bit 4" "No effect,Reset"
|
|
bitfld.long 0x00 3. " BR3 ,Port A reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port A reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BR1 ,Port A reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port A reset bit 0" "No effect,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO B"
|
|
base ad:0x48000400
|
|
width 18.
|
|
sif (cpuis("STM32F038C6"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOB_MODER,GPIO port B mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOB_OTYPER,GPIO port B mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OT7 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOB_OSPEEDR,GPIO port B output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOB_PUPDR,GPIO port B pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOB_IDR,GPIO port B input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port B input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOB_ODR,GPIO port B output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port B output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOB_LCKR,GPIO port B configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port B lock bit" "Not locked,Locked"
|
|
elif (cpuis("STM32F038K6"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOB_MODER,GPIO port B mode register"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOB_OTYPER,GPIO port B mode register"
|
|
bitfld.long 0x04 8. " OT8 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 4. " OT4 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 3. " OT3 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOB_OSPEEDR,GPIO port B output speed register"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOB_PUPDR,GPIO port B pull-up/pull-down register"
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOB_IDR,GPIO port B input data register"
|
|
bitfld.long 0x00 8. " IDR8 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDR4 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 3. " IDR3 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port B input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOB_ODR,GPIO port B output data register"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port B output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOB_LCKR,GPIO port B configuration lock register"
|
|
bitfld.long 0x00 8. " LCK8 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port B lock bit" "Not locked,Locked"
|
|
elif CPUIS("STM32F038E6")
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOB_MODER,GPIO port B mode register"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOB_OTYPER,GPIO port B mode register"
|
|
bitfld.long 0x04 7. " OT7 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOB_OSPEEDR,GPIO port B output speed register"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOB_PUPDR,GPIO Port B pull-up/pull-down register"
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOB_IDR,GPIO port B input data register"
|
|
bitfld.long 0x00 7. " IDR7 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port B input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOB_ODR,GPIO port B output data register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port B output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOB_LCKR,GPIO port B configuration lock register"
|
|
bitfld.long 0x00 7. " LCK7 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Port B lock bit" "Not locked,Locked"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,?..."
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOB_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 7. " BR7 ,Port B reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port B reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port B reset bit 5" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port B reset bit 0" "No effect,Reset"
|
|
elif (cpuis("STM32F038G6"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOB_MODER,GPIO port B mode register"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOB_OTYPER,GPIO port B mode register"
|
|
bitfld.long 0x04 7. " OT7 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOB_OSPEEDR,GPIO port B output speed register"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOB_PUPDR,GPIO port B pull-up/pull-down register"
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOB_IDR,GPIO port B input data register"
|
|
bitfld.long 0x00 7. " IDR7 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port B input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOB_ODR,GPIO port B output data register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port B output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOB_LCKR,GPIO port B configuration lock register"
|
|
bitfld.long 0x00 7. " LCK7 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " LCK4 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LCK3 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port B lock bit" "Not locked,Locked"
|
|
endif
|
|
sif (cpuis("STM32F038C6"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,?..."
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" "SPI1_MOSI,,TIM1_CH3N,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" "SPI1_MISO,,TIM1_CH2N,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" "SPI1_SCK,,TIM1_CH1N,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" "SPI1_NSS,EVENTOUT,TIM1_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" "EVENTOUT,I2C1_SDA,TIM2_CH4,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" ",I2C1_SCL,TIM2_CH3,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "IR_OUT,I2C1_SDA,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",I2C1_SCL,TIM16_CH1,?..."
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOB_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port B reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port B reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port B reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port B reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port B reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port B reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port B reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port B reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Port B reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port B reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port B reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port B reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port B reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port B reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port B reset bit 0" "No effect,Reset"
|
|
elif (cpuis("STM32F038K6"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,?..."
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" ",I2C1_SCL,TIM16_CH1,?..."
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOB_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 8. " BR8 ,Port B reset bit 8" "No effect,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port B reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port B reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port B reset bit 5" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " BR4 ,Port B reset bit 4" "No effect,Reset"
|
|
bitfld.long 0x00 3. " BR3 ,Port B reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port B reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port B reset bit 0" "No effect,Reset"
|
|
elif (cpuis("STM32F038G6"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,?..."
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOB_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 7. " BR7 ,Port B reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port B reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port B reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port B reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port B reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port B reset bit 0" "No effect,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F048?6"))
|
|
tree "GPIO A"
|
|
base ad:0x48000000
|
|
width 15.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOA_MODER,GPIO port A mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif (!cpuis("STM32F048G6"))
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x00 "GPIOA_OTYPER,GPIO port A mode register"
|
|
bitfld.long 0x00 15. " OT15 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 14. " OT14 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 13. " OT13 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 12. " OT12 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OT11 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 10. " OT10 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 9. " OT9 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif (!cpuis("STM32F048G6"))
|
|
bitfld.long 0x00 8. " OT8 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " OT7 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 6. " OT6 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 5. " OT5 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 4. " OT4 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OT3 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 2. " OT2 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 1. " OT1 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x00 0. " OT0 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOA_OSPEEDR,GPIO port A output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
sif (!cpuis("STM32F048G6"))
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOA_PUPDR,GPIO port A pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
sif (!cpuis("STM32F048G6"))
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOA_IDR,GPIO port A input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port A input data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("STM32F048G6"))
|
|
bitfld.long 0x00 8. " IDR8 ,Port A input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " IDR7 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port A input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOA_ODR,GPIO port A output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("STM32F048G6"))
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port A output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port A output data" "Low,High"
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "GPIOA_LCKR,GPIO port A configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
sif (!cpuis("STM32F048G6"))
|
|
bitfld.long 0x00 8. " LCK8 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LCK7 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " LCK4 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LCK3 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port A lock bit" "Not locked,Locked"
|
|
line.long 0x04 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,TSC_G2_IO4,TIM14_CH1,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,TSC_G2_IO3,,TIM16_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK/I2S1_CK,CEC,TIM2_CH1_ETR,TSC_G2_IO2,?..."
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,USART2_CK,USB_NOE,TSC_G2_IO1,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" ",USART2_RX,TIM2_CH4,TSC_G1_IO4,?..."
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" ",USART2_TX,TIM2_CH3,TSC_G1_IO3,?..."
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,TIM2_CH2,TSC_G1_IO2,?..."
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,TIM2_CH1_ETR,TSC_G1_IO1,?..."
|
|
line.long 0x08 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,USART2_RX,TIM2_CH1_ETR,EVENTOUT,,USB_NOE,?..."
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,USB_NOE,?..."
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,TSC_G4_IO4,,I2C1_SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,TSC_G4_IO3,,I2C1_SCL,?..."
|
|
bitfld.long 0x08 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,TSC_G4_IO2,I2C1_SDA,?..."
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" ",USART1_TX,TIM1_CH2,TSC_G4_IO1,I2C1_SCL,MCO,?..."
|
|
sif (!cpuis("STM32F048G6"))
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,CRS_SYNC,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOA_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port A reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port A reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port A reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port A reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port A reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port A reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port A reset bit 9" "No effect,Reset"
|
|
textline " "
|
|
sif (!cpuis("STM32F048G6"))
|
|
bitfld.long 0x00 8. " BR8 ,Port A reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " BR7 ,Port A reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port A reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port A reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port A reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port A reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port A reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port A reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port A reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO B"
|
|
base ad:0x48000400
|
|
width 15.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOB_MODER,GPIO port B mode register"
|
|
sif (cpuis("STM32F048C6"))
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif (!cpuis("STM32F048C6")||(!cpuis("STM32F048G6")))
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
sif ((cpuis("STM32F048C6")))
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOB_OTYPER,GPIO port B mode register"
|
|
sif (cpuis("STM32F048C6"))
|
|
bitfld.long 0x04 15. " OT15 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " OT8 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 4. " OT4 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 3. " OT3 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif (!cpuis("STM32F048C6"))||(!cpuis("STM32F048G6"))
|
|
bitfld.long 0x04 2. " OT2 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F048C6"))
|
|
bitfld.long 0x04 1. " OT1 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0. " OT0 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOB_OSPEEDR,GPIO port B output speed register"
|
|
sif (cpuis("STM32F048C6"))
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
sif (!cpuis("STM32F048C6"))||(!cpuis("STM32F048G6"))
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F048C6"))
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOB_PUPDR,GPIO port B pull-up/pull-down register"
|
|
sif (cpuis("STM32F048C6"))
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
sif (!cpuis("STM32F048C6")||(!cpuis("STM32F048G6")))
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F048C6"))
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOB_IDR,GPIO port B input data register"
|
|
sif (cpuis("STM32F048C6"))
|
|
bitfld.long 0x00 15. " IDR15 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port B input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " IDR8 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDR4 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 3. " IDR3 ,Port B input data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("STM32F048C6")||(!cpuis("STM32F048G6")))
|
|
bitfld.long 0x00 2. " IDR2 ,Port B input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F048C6"))
|
|
bitfld.long 0x00 1. " IDR1 ,Port B input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " IDR0 ,Port B input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOB_ODR,GPIO port B output data register"
|
|
sif (cpuis("STM32F048C6"))
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port B output data" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("STM32F048C6")||(!cpuis("STM32F048G6")))
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F048C6"))
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port B output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port B output data" "Low,High"
|
|
group.long 0x1C++0x0B
|
|
line.long 0x00 "GPIOB_LCKR,GPIO port B configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
textline " "
|
|
sif (cpuis("STM32F048C6"))
|
|
bitfld.long 0x00 15. " LCK15 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " LCK9 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " LCK8 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
sif (!cpuis("STM32F048C6")||!cpuis("STM32F048G6"))
|
|
bitfld.long 0x00 2. " LCK2 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F048C6"))
|
|
bitfld.long 0x00 1. " LCK1 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " LCK0 ,Port B lock bit" "Not locked,Locked"
|
|
line.long 0x04 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x04 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,TSC_G5_IO4,?..."
|
|
bitfld.long 0x04 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,TSC_G5_IO3,?..."
|
|
bitfld.long 0x04 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,?..."
|
|
bitfld.long 0x04 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,TSC_G5_IO2,,TIM17_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,TSC_G5_IO1,?..."
|
|
textline " "
|
|
sif (!cpuis("STM32F048C6")||!cpuis("STM32F048G6"))
|
|
bitfld.long 0x04 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" ",,,TSC_G3_IO4,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F048C6"))
|
|
bitfld.long 0x04 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,TSC_G3_IO3,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,TSC_G3_IO2,?..."
|
|
line.long 0x08 "GPIOB_AFRH,GPIO alternate function high register"
|
|
sif (cpuis("STM32F048C6"))
|
|
bitfld.long 0x08 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" "SPI2_MOSI,,TIM1_CH3N,?..."
|
|
bitfld.long 0x08 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" "SPI2_MISO,,TIM1_CH2N,,,I2C1_SDA,?..."
|
|
bitfld.long 0x08 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" "SPI2_SCK,,TIM1_CH1N,,,I2C1_SCL,?..."
|
|
bitfld.long 0x08 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" "SPI2_NSS,EVENTOUT,TIM1_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "IR_OUT,I2C1_SDA,TIM17_CH1,EVENTOUT,,SPI2_NSS,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" "CEC,I2C1_SCL,TIM16_CH1,TSC_SYNC,?..."
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOB_BRR,Port bit reset register"
|
|
sif (cpuis("STM32F048C6"))
|
|
bitfld.long 0x00 15. " BR15 ,Port B reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port B reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port B reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port B reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port B reset bit 9" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " BR8 ,Port B reset bit 8" "No effect,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port B reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port B reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port B reset bit 5" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " BR4 ,Port B reset bit 4" "No effect,Reset"
|
|
bitfld.long 0x00 3. " BR3 ,Port B reset bit 3" "No effect,Reset"
|
|
textline " "
|
|
sif (!cpuis("STM32F048C6")||!cpuis("STM32F048G6"))
|
|
bitfld.long 0x00 2. " BR2 ,Port B reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F048C6"))
|
|
bitfld.long 0x00 1. " BR1 ,Port B reset bit 1" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " BR0 ,Port B reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*"))
|
|
tree "GPIO A"
|
|
base ad:0x48000000
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOA_MODER,GPIO port A mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOA_OTYPER,GPIO port A mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OT7 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOA_OSPEEDR,GPIO port A output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOA_PUPDR,GPIO port A pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
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|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port A configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
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|
line.long 0x00 "GPIOA_IDR,GPIO port A input data register"
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|
bitfld.long 0x00 15. " IDR15 ,Port A input data" "Low,High"
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|
bitfld.long 0x00 14. " IDR14 ,Port A input data" "Low,High"
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|
bitfld.long 0x00 13. " IDR13 ,Port A input data" "Low,High"
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|
bitfld.long 0x00 12. " IDR12 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port A input data" "Low,High"
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|
bitfld.long 0x00 10. " IDR10 ,Port A input data" "Low,High"
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|
bitfld.long 0x00 9. " IDR9 ,Port A input data" "Low,High"
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|
bitfld.long 0x00 8. " IDR8 ,Port A input data" "Low,High"
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|
textline " "
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|
bitfld.long 0x00 7. " IDR7 ,Port A input data" "Low,High"
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|
bitfld.long 0x00 6. " IDR6 ,Port A input data" "Low,High"
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|
bitfld.long 0x00 5. " IDR5 ,Port A input data" "Low,High"
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|
bitfld.long 0x00 4. " IDR4 ,Port A input data" "Low,High"
|
|
textline " "
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|
bitfld.long 0x00 3. " IDR3 ,Port A input data" "Low,High"
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|
bitfld.long 0x00 2. " IDR2 ,Port A input data" "Low,High"
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|
bitfld.long 0x00 1. " IDR1 ,Port A input data" "Low,High"
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|
bitfld.long 0x00 0. " IDR0 ,Port A input data" "Low,High"
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|
group.long 0x14++0x03
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|
line.long 0x00 "GPIOA_ODR,GPIO port A output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port A output data" "Low,High"
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|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port A output data" "Low,High"
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|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port A output data" "Low,High"
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|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr ,Port A output data" "Low,High"
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|
textline " "
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|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port A output data" "Low,High"
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|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port A output data" "Low,High"
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|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port A output data" "Low,High"
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|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port A output data" "Low,High"
|
|
textline " "
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|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port A output data" "Low,High"
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|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port A output data" "Low,High"
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|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port A output data" "Low,High"
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|
textline " "
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setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port A output data" "Low,High"
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|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port A output data" "Low,High"
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|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port A output data" "Low,High"
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|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port A output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOA_LCKR,GPIO port A configuration lock register"
|
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bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
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bitfld.long 0x00 15. " LCK15 ,Port A lock bit" "Not locked,Locked"
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bitfld.long 0x00 14. " LCK14 ,Port A lock bit" "Not locked,Locked"
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|
bitfld.long 0x00 13. " LCK13 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
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bitfld.long 0x00 12. " LCK12 ,Port A lock bit" "Not locked,Locked"
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bitfld.long 0x00 11. " LCK11 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port A lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port A lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Port A lock bit" "Not locked,Locked"
|
|
sif (cpuis("STM32F058?8"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,TSC_G2_IO4,TIM14_CH1,TIM17_CH1,EVENTOUT,COMP2_OUT,?..."
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|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,TSC_G2_IO3,,TIM16_CH1,EVENTOUT,COMP1_OUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK/I2S1_CK,CEC,TIM2_CH1_ETR,TSC_G2_IO2,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,USART2_CK,,TSC_G2_IO1,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TIM15_CH2,USART2_RX,TIM2_CH4,TSC_G1_IO4,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "TIM15_CH1,USART2_TX,TIM2_CH3,TSC_G1_IO3,,,,COMP2_OUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,TIM2_CH2,TSC_G1_IO2,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,TIM2_CH1_ETR,TSC_G1_IO1,,,,COMP1_OUT,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,USART2_RX,TIM2_CH1_ETR,EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,TSC_G4_IO4,,,,COMP2_OUT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,TSC_G4_IO3,,,,COMP1_OUT,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,TSC_G4_IO2,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" "TIM15_BKIN,USART1_TX,TIM1_CH2,TSC_G4_IO1,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,?..."
|
|
elif (cpuis("STM32F078?B"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,TSC_G2_IO4,TIM14_CH1,TIM17_CH1,EVENTOUT,COMP2_OUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,TSC_G2_IO3,USART3_CTS,TIM16_CH1,EVENTOUT,COMP1_OUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK/I2S1_CK,CEC,TIM2_CH1_ETR,TSC_G2_IO2,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,USART2_CK,,TSC_G2_IO1,TIM14_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TIM15_CH2,USART2_RX,TIM2_CH4,TSC_G1_IO4,,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "TIM15_CH1,USART2_TX,TIM2_CH3,TSC_G1_IO3,,,,COMP2_OUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,TIM2_CH2,TSC_G1_IO2,USART4_RX,TIM15_CH1N,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,TIM2_CH1_ETR,TSC_G1_IO1,USART4_TX,,,COMP1_OUT,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,USART2_RX,TIM2_CH1_ETR,EVENTOUT,USART4_RTS,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,USB_NOE,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,TSC_G4_IO4,,,,COMP2_OUT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,TSC_G4_IO3,,,,COMP1_OUT,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,TSC_G4_IO2,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" "TIM15_BKIN,USART1_TX,TIM1_CH2,TSC_G4_IO1,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,CRS_SYNC,?..."
|
|
elif (cpuis("STM32F091*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,TSC_G2_IO4,TIM14_CH1,TIM17_CH1,EVENTOUT,COMP2_OUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,TSC_G2_IO3,USART3_CTS,TIM16_CH1,EVENTOUT,COMP1_OUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK/I2S1_CK,CEC,TIM2_CH1_ETR,TSC_G2_IO2,,USART6_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,USART2_CK,,TSC_G2_IO1,TIM14_CH1,USART6_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TIM15_CH2,USART2_RX,TIM2_CH4,TSC_G1_IO4,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "TIM15_CH1,USART2_TX,TIM2_CH3,TSC_G1_IO3,,,,COMP2_OUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,TIM2_CH2,TSC_G1_IO2,USART4_RX,TIM15_CH1N,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,TIM2_CH1_ETR,TSC_G1_IO1,USART4_TX,,,COMP1_OUT,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,USART2_RX,TIM2_CH1_ETR,EVENTOUT,USART4_RTS,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,TSC_G4_IO4,CAN_TX,I2C2_SDA,,COMP2_OUT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,TSC_G4_IO3,CAN_RX,I2C2_SCL,,COMP1_OUT,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,TSC_G4_IO2,I2C1_SDA,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" "TIM15_BKIN,USART1_TX,TIM1_CH2,TSC_G4_IO1,I2C1_SCL,MCO,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,CRS_SYNC,?..."
|
|
elif (cpuis("STM32F098?C"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A bit 7" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM1_CH1N,TSC_G2_IO4,TIM14_CH1,TIM17_CH1,EVENTOUT,COMP2_OUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A bit 6" "SPI1_MISO/I2S1_MCK,TIM3_CH1,TIM1_BKIN,TSC_G2_IO3,USART3_CTS,TIM16_CH1,EVENTOUT,COMP1_OUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A bit 5" "SPI1_SCK/I2S1_CK,CEC,TIM2_CH1_ETR,TSC_G2_IO2,,USART6_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A bit 4" "SPI1_NSS/I2S1_WS,USART2_CK,,TSC_G2_IO1,TIM14_CH1,USART6_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A bit 3" "TIM15_CH2,USART2_RX,TIM2_CH4,TSC_G1_IO4,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A bit 2" "TIM15_CH1,USART2_TX,TIM2_CH3,TSC_G1_IO3,,,,COMP2_OUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A bit 1" "EVENTOUT,USART2_RTS,TIM2_CH2,TSC_G1_IO2,USART4_RX,TIM15_CH1N,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A bit 0" ",USART2_CTS,TIM2_CH1_ETR,TSC_G1_IO1,USART4_TX,,,COMP1_OUT,?..."
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A bit 15" "SPI1_NSS/I2S1_WS,USART2_RX,TIM2_CH1_ETR,EVENTOUT,USART4_RTS,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A bit 14" "SWCLK,USART2_TX,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A bit 13" "SWDIO,IR_OUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A bit 12" "EVENTOUT,USART1_RTS,TIM1_ETR,TSC_G4_IO4,CAN_TX,I2C2_SDA,,COMP2_OUT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A bit 11" "EVENTOUT,USART1_CTS,TIM1_CH4,TSC_G4_IO3,CAN_RX,I2C2_SCL,,COMP1_OUT,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A bit 10" "TIM17_BKIN,USART1_RX,TIM1_CH3,TSC_G4_IO2,I2C1_SDA,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A bit 9" "TIM15_BKIN,USART1_TX,TIM1_CH2,TSC_G4_IO1,I2C1_SCL,MCO,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A bit 8" "MCO,USART1_CK,TIM1_CH1,EVENTOUT,CRS_SYNC,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOA_BRR,GPIO Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port A reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port A reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port A reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port A reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port A reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port A reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port A reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port A reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Port A reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port A reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port A reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port A reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port A reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port A reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port A reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port A reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO B"
|
|
base ad:0x48000400
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOB_MODER,GPIO port B mode register"
|
|
sif !CPUIS("STM32F058T8")
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif (cpuis("STM32F091V?")||cpuis("STM32F091C?"))
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOB_OTYPER,GPIO port B mode register"
|
|
sif !CPUIS("STM32F058T8")
|
|
bitfld.long 0x04 15. " OT15 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 7. " OT7 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif (cpuis("STM32F091V?")||cpuis("STM32F091C?"))
|
|
bitfld.long 0x04 2. " OT2 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 1. " OT1 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOB_OSPEEDR,GPIO port B output speed register"
|
|
sif !CPUIS("STM32F058T8")
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
sif (cpuis("STM32F091V?")||cpuis("STM32F091C?"))
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOB_PUPDR,GPIO port B pull-up/pull-down register"
|
|
sif !CPUIS("STM32F058T8")
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
sif (cpuis("STM32F091V?")||cpuis("STM32F091C?"))
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port B configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOB_IDR,GPIO port B input data register"
|
|
sif !CPUIS("STM32F058T8")
|
|
bitfld.long 0x00 15. " IDR15 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port B input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " IDR7 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port B input data" "Low,High"
|
|
textline " "
|
|
sif (cpuis("STM32F091V?")||cpuis("STM32F091C?"))
|
|
bitfld.long 0x00 2. " IDR2 ,Port B input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " IDR1 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port B input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOB_ODR,GPIO port B output data register"
|
|
sif !CPUIS("STM32F058T8")
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_SET/CLR ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
sif (cpuis("STM32F091V?")||cpuis("STM32F091C?"))
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port B output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOB_LCKR,GPIO port B configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
textline " "
|
|
sif !CPUIS("STM32F058T8")
|
|
bitfld.long 0x00 15. " LCK15 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " LCK7 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpuis("STM32F091V?")||cpuis("STM32F091C?"))
|
|
bitfld.long 0x00 2. " LCK2 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " LCK1 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port B lock bit" "Not locked,Locked"
|
|
sif (cpuis("STM32F058?8"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,TSC_G5_IO4,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,TSC_G5_IO3,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,TSC_G5_IO2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,TSC_G5_IO1,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,TSC_G3_IO3,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,TSC_G3_IO2,?..."
|
|
sif !CPUIS("STM32F058T8")
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" "SPI2_MOSI,TIM15_CH2,TIM1_CH3N,TIM15_CH1N,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" "SPI2_MISO,TIM15_CH1,TIM1_CH2N,TSC_G6_IO4,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" "SPI2_SCK,,TIM1_CH1N,TSC_G6_IO3,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" "SPI2_NSS,EVENTOUT,TIM1_BKIN,TSC_G6_IO2,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" "EVENTOUT,I2C2_SDA,TIM2_CH4,TSC_G6_IO1,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" "CEC,I2C2_SCL,TIM2_CH3,TSC_SYNC,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "IR_OUT,I2C1_SDA,TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" "CEC,I2C1_SCL,TIM16_CH1,TSC_SYNC,?..."
|
|
endif
|
|
elif (cpuis("STM32F078?B"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,TSC_G5_IO4,USART4_CTS,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,TSC_G5_IO3,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,TSC_G5_IO2,,TIM17_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,TSC_G5_IO1,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,TSC_G3_IO3,USART3_RTS,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,TSC_G3_IO2,USART3_CK,?..."
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" "SPI2_MOSI/I2S2_SD,TIM15_CH2,TIM1_CH3N,TIM15_CH1N,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" "SPI2_MISO/I2S2_MCK,TIM15_CH1,TIM1_CH2N,TSC_G6_IO4,USART3_RTS,I2C2_SDA,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" "SPI2_SCK/I2S2_CK,,TIM1_CH1N,TSC_G6_IO3,USART3_CTS,I2C2_SCL,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" "SPI2_NSS/I2S2_WS,EVENTOUT,TIM1_BKIN,TSC_G6_IO2,USART3_CK,TIM15_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" "EVENTOUT,I2C2_SDA,TIM2_CH4,TSC_G6_IO1,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" "CEC,I2C2_SCL,TIM2_CH3,TSC_SYNC,USART3_TX,SPI2_SCK/I2S2_CK,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "IR_OUT,I2C1_SDA,TIM17_CH1,EVENTOUT,,SPI2_NSS/I2S2_WS,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" "CEC,I2C1_SCL,TIM16_CH1,TSC_SYNC,?..."
|
|
elif (cpuis("STM32F091*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,TSC_G5_IO4,USART4_CTS,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,TSC_G5_IO3,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,USART5_CK_RTS,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,TSC_G5_IO2,USART5_RX,TIM17_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,TSC_G5_IO1,USART5_TX,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B bit 2" ",,,TSC_G3_IO4,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,TSC_G3_IO3,USART3_RTS,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,TSC_G3_IO2,USART3_CK,?..."
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" "SPI2_MOSI/I2S2_SD,TIM15_CH2,TIM1_CH3N,TIM15_CH1N,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" "SPI2_MISO/I2S2_MCK,TIM15_CH1,TIM1_CH2N,TSC_G6_IO4,USART3_RTS,I2C2_SDA,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" "SPI2_SCK/I2S2_CK,,TIM1_CH1N,TSC_G6_IO3,USART3_CTS,I2C2_SCL,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" "SPI2_NSS/I2S2_WS,EVENTOUT,TIM1_BKIN,TSC_G6_IO2,USART3_CK,TIM15_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" "EVENTOUT,I2C2_SDA,TIM2_CH4,TSC_G6_IO1,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" "CEC,I2C2_SCL,TIM2_CH3,TSC_SYNC,USART3_TX,SPI2_SCK/I2S2_CK,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "IR_OUT,I2C1_SDA,TIM17_CH1,EVENTOUT,CAN_TX,SPI2_NSS/I2S2_WS,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" "CEC,I2C1_SCL,TIM16_CH1,TSC_SYNC,CAN_RX,?..."
|
|
elif (cpuis("STM32F098*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B bit 7" "USART1_RX,I2C1_SDA,TIM17_CH1N,TSC_G5_IO4,USART4_CTS,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B bit 6" "USART1_TX,I2C1_SCL,TIM16_CH1N,TSC_G5_IO3,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B bit 5" "SPI1_MOSI/I2S1_SD,TIM3_CH2,TIM16_BKIN,I2C1_SMBA,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B bit 4" "SPI1_MISO/I2S1_MCK,TIM3_CH1,EVENTOUT,TSC_G5_IO2,TIM17_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B bit 3" "SPI1_SCK/I2S1_CK,EVENTOUT,TIM2_CH2,TSC_G5_IO1,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B bit 1" "TIM14_CH1,TIM3_CH4,TIM1_CH3N,TSC_G3_IO3,USART3_RTS,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B bit 0" "EVENTOUT,TIM3_CH3,TIM1_CH2N,TSC_G3_IO2,USART3_CK,?..."
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B bit 15" "SPI2_MOSI/I2S2_SD,TIM15_CH2,TIM1_CH3N,TIM15_CH1N,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B bit 14" "SPI2_MISO/I2S2_MCK,TIM15_CH1,TIM1_CH2N,TSC_G6_IO4,USART3_RTS,I2C2_SDA,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B bit 13" "SPI2_SCK/I2S2_CK,,TIM1_CH1N,TSC_G6_IO3,USART3_CTS,I2C2_SCL,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B bit 12" "SPI2_NSS/I2S2_WS,EVENTOUT,TIM1_BKIN,TSC_G6_IO2,USART3_CK,TIM15_BKIN,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B bit 11" "EVENTOUT,I2C2_SDA,TIM2_CH4,TSC_G6_IO1,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B bit 10" "CEC,I2C2_SCL,TIM2_CH3,TSC_SYNC,USART3_TX,SPI2_SCK/I2S2_CK,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B bit 9" "IR_OUT,I2C1_SDA,TIM17_CH1,EVENTOUT,CAN_TX,SPI2_NSS/I2S2_WS,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B bit 8" "CEC,I2C1_SCL,TIM16_CH1,TSC_SYNC,CAN_RX,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOB_BRR,GPIO port bit reset register"
|
|
sif !CPUIS("STM32F058T8")
|
|
bitfld.long 0x00 15. " BR15 ,Port B reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port B reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port B reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port B reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port B reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port B reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port B reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port B reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " BR7 ,Port B reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port B reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port B reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port B reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port B reset bit 3" "No effect,Reset"
|
|
textline " "
|
|
sif (cpuis("STM32F091V?")||cpuis("STM32F091C?"))
|
|
bitfld.long 0x00 2. " BR2 ,Port B reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " BR1 ,Port B reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port B reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F038C6")||cpuis("STM32F048C6")||cpuis("STM32F048T6")||cpuis("STM32F058C8")||cpuis("STM32F078CB")||cpuis("STM32F091C*")||cpuis("STM32F058T8"))
|
|
tree "GPIO C"
|
|
base ad:0x48000800
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOC_MODER,GPIO port C mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
sif (cpuis("STM32F048T6")||cpuis("STM32F098CC"))
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,,Analog"
|
|
else
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
endif
|
|
line.long 0x04 "GPIOC_OTYPER,GPIO port C mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x04 13. " OT13 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
endif
|
|
line.long 0x08 "GPIOC_OSPEEDR,GPIO port C output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
endif
|
|
line.long 0x0C "GPIOC_PUPDR,GPIO port C pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOC_IDR,GPIO port C input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port C input data" "Low,High"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x00 13. " IDR13 ,Port C input data" "Low,High"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOC_ODR,GPIO port C output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port C output data" "Low,High"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port C output data" "Low,High"
|
|
endif
|
|
sif !cpuis("STM32F058?8")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOC_LCKR,GPIO port C configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port C lock bit" "Not locked,Locked"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x00 13. " LCK13 ,Port C lock bit" "Not locked,Locked"
|
|
endif
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOC_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port C reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port C reset bit 14" "No effect,Reset"
|
|
sif (!cpuis("STM32F048T6")&&!cpuis("STM32F098CC"))
|
|
bitfld.long 0x00 13. " BR13 ,Port C reset bit 13" "No effect,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F058R8")||cpuis("STM32F078RB")||cpuis("STM32F078VB")||cpuis("STM32F091R*")||cpuis("STM32F091V*")||cpuis("STM32F098*"))
|
|
tree "GPIO C"
|
|
base ad:0x48000800
|
|
width 18.
|
|
sif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||cpuis("STM32F098CC")||CPUIS("STM32F051T8")||CPUIS("STM32F030CC")||CPUIS("STM32F030C6")||CPUIS("STM32F030C8")||CPUIS("STM32F030R8")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOC_MODER,GPIO Port C Mode Register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif !cpuis("STM32F098CC")
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
endif
|
|
line.long 0x04 "GPIOC_OTYPER,GPIO port C mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif !cpuis("STM32F098CC")
|
|
bitfld.long 0x04 13. " OT13 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
endif
|
|
line.long 0x08 "GPIOC_OSPEEDR,GPIO Port C Output Speed Register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOC_PUPDR,GPIO port C pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
sif !cpuis("STM32F098CC")
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOC_IDR,GPIO Port C Input Data Register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port C input data" "Low,High"
|
|
textline " "
|
|
sif !cpuis("STM32F098CC")
|
|
bitfld.long 0x00 13. " IDR13 ,Port C input data" "Low,High"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOC_ODR,GPIO Port C Output Data Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port C output data" "Low,High"
|
|
textline " "
|
|
sif !cpuis("STM32F098CC")
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port C output data" "Low,High"
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOC_BRR,GPIO Port Bit Reset Register"
|
|
bitfld.long 0x00 15. " BR15 ,Port C reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port C reset bit 14" "No effect,Reset"
|
|
textline " "
|
|
sif !cpuis("STM32F098CC")
|
|
bitfld.long 0x00 13. " BR13 ,Port C reset bit 13" "No effect,Reset"
|
|
endif
|
|
else
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOC_MODER,GPIO Port C Mode Register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOC_OTYPER,GPIO Port C Mode Register"
|
|
bitfld.long 0x04 15. " OT15 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OT7 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOC_OSPEEDR,GPIO Port C Output Speed Register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOC_PUPDR,GPIO Port C Pull-up/Pull-down Register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port C configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOC_IDR,GPIO Port C Input Data Register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port C input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOC_ODR,GPIO Port C Output Data Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr ,Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port C output data" "Low,High"
|
|
sif (cpuis("STM32F078RB")||cpuis("STM32F078VB"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "TIM3_CH2,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "TIM3_CH1,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" "TSC_G3_IO1,USART3_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "EVENTOUT,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "EVENTOUT,SPI2_MOSI/I2S2_SD,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "EVENTOUT,SPI2_MISO/I2S2_MCK,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "EVENTOUT,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" "USART4_CK,USART3_CK,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" "USART4_RX,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" "USART4_TX,USART3_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "TIM3_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "TIM3_CH3,?..."
|
|
elif CPUIS("STM32F030RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "TIM3_CH2,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "TIM3_CH1,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",USART3_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "EVENTOUT,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "EVENTOUT,SPI2_MOS,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "EVENTOUT,SPI2_MISO,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "EVENTOUT,,USART6_RX,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "EVENTOUT,,USART6_TX,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO Alternate Function High Register"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" "USART4_CK,USART3_CK,USART5_TX,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" "USART4_RX,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" "USART4_TX,USART3_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "TIM3_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "TIM3_CH3,?..."
|
|
elif (cpuis("STM32F091R*")||cpuis("STM32F091V*")||cpuis("STM32F098RC"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "TIM3_CH2,USART7_RX,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "TIM3_CH1,USART7_TX,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" "TSC_G3_IO1,USART3_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "EVENTOUT,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "EVENTOUT,SPI2_MOSI/I2S2_SD,USART8_RX,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "EVENTOUT,SPI2_MISO/I2S2_MCK,USART8_TX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "EVENTOUT,USART7_RX,USART6_RX,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "EVENTOUT,USART7_TX,USART6_TX,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" "USART4_CK,USART3_CK,USART5_TX,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" "USART4_RX,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" "USART4_TX,USART3_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "TIM3_CH4,USART8_RX,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "TIM3_CH3,USART8_TX,?..."
|
|
elif (cpuis("STM32F058R8"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "TIM3_CH2,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "TIM3_CH1,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" "TSC_G3_IO1,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "EVENTOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "EVENTOUT,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "EVENTOUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "EVENTOUT,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "TIM3_CH4,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "TIM3_CH3,?..."
|
|
elif CPUIS("STM32F070RB")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO Alternate Function Low Register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C bit 7" "TIM3_CH2,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C bit 6" "TIM3_CH1,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C bit 5" ",USART3_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C bit 4" "EVENTOUT,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C bit 3" "EVENTOUT,SPI2_MOSI,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C bit 2" "EVENTOUT,SPI2_MISO,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C bit 1" "EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C bit 0" "EVENTOUT,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO Alternate Function High Register"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C bit 12" "USART4_CK,USART3_CK,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C bit 11" "USART4_RX,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C bit 10" "USART4_TX,USART3_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C bit 9" "TIM3_CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C bit 8" "TIM3_CH3,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOC_BRR,GPIO Port Bit Reset Register"
|
|
bitfld.long 0x00 15. " BR15 ,Port C reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port C reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port C reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port C reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port C reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port C reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port C reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port C reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Port C reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port C reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port C reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port C reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port C reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port C reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port C reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port C reset bit 0" "No effect,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F058R8")||cpuis("STM32F078RB")||cpuis("STM32F091R*")||cpuis("STM32F098RC"))
|
|
tree "GPIO D"
|
|
base ad:0x48000C00
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOD_MODER,GPIO port D mode register"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOD_OTYPER,GPIO port D mode register"
|
|
bitfld.long 0x04 2. " OT2 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOD_OSPEEDR,GPIO port D output speed register"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOD_PUPDR,GPIO port D pull-up/pull-down register"
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOD_IDR,GPIO port D input data register"
|
|
bitfld.long 0x00 2. " IDR2 ,Port D input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOD_ODR,GPIO port D output data register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port D output data" "Low,High"
|
|
sif (cpuis("STM32F058R8")||CPUIS("STM32F070RB"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " ARFL2 ,Alternate function selection for port D bit 2" "TIM3_ETR,?..."
|
|
elif (cpuis("STM32F078R8"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " ARFL2 ,Alternate function selection for port D bit 2" "TIM3_ETR,USART3_RTS,?..."
|
|
elif (cpuis("STM32F091R*")||cpuis("STM32F098RC")||CPUIS("STM32F030RC"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " ARFL2 ,Alternate function selection for port D bit 2" "TIM3_ETR,USART3_RTS,USART5_RX,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOD_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 2. " BR2 ,Port D reset bit 2" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F078V*")||cpuis("STM32F091V*"))
|
|
tree "GPIO D"
|
|
base ad:0x48000C00
|
|
width 15.
|
|
sif (cpuis("STM32F071V*"))||(cpuis("STM32F072V*")||cpuis("STM32F078VB")||cpuis("STM32F091V*"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOD_MODER,GPIO port D mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOD_OTYPER,GPIO port D mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OT7 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOD_OSPEEDR,GPIO port D output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOD_PUPDR,GPIO port D pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOD_IDR,GPIO port D input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port D input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOD_ODR,GPIO port D output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port D output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port D output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOD_LCKR,GPIO port D configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Port D lock bit" "Not locked,Locked"
|
|
sif (cpuis("STM32F072*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" "USART2_CK,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" "USART2_RX,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" "USART2_TX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port D bit 4" "USART2_RTS,SPI2_MOSI/I2S2_SD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port D bit 3" "USART2_CTS,SPI2_MISO/I2S2_MCK,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "TIM3_ETR,USART3_RTS,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port D bit 1" "CAN_TX,SPI2_SCK/I2S2_CK,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" "CAN_RX,SPI2_NSS/I2S2_WS,?..."
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" "CRS_SYNC,TSC_G8_IO4,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",TSC_G8_IO3,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",TSC_G8_IO2,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" "USART3_RTS,TSC_G8_IO1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" "USART3_CTS,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" "USART3_CK,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" "USART3_RX,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" "USART3_TX,?..."
|
|
elif (cpuis("STM32F071*")||cpuis("STM32F078VB"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" "USART2_CK,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" "USART2_RX,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" "USART2_TX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port D bit 4" "USART2_RTS,SPI2_MOSI/I2S2_SD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port D bit 3" "USART2_CTS,SPI2_MISO/I2S2_MCK,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "TIM3_ETR,USART3_RTS,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port D bit 1" ",SPI2_SCK/I2S2_CK,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" ",SPI2_NSS/I2S2_WS,?..."
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" "CRS_SYNC,TSC_G8_IO4,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" ",TSC_G8_IO3,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" ",TSC_G8_IO2,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" "USART3_RTS,TSC_G8_IO1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" "USART3_CTS,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" "USART3_CK,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" "USART3_RX,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" "USART3_TX,?..."
|
|
elif (cpuis("STM32F091V*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D bit 7" "USART2_CK,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D bit 6" "USART2_RX,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D bit 5" "USART2_TX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port D bit 4" "USART2_RTS,SPI2_MOSI/I2S2_SD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port D bit 3" "USART2_CTS,SPI2_MISO/I2S2_MCK,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "TIM3_ETR,USART3_RTS,USART5_RX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port D bit 1" "CAN_TX,SPI2_SCK/I2S2_CK,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D bit 0" "CAN_RX,SPI2_NSS/I2S2_WS,?..."
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D bit 15" "CRS_SYNC,TSC_G8_IO4,USART7_CK_RTS,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D bit 14" "USART8_RX,TSC_G8_IO3,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D bit 13" "USART8_TX,TSC_G8_IO2,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D bit 12" "USART3_RTS,TSC_G8_IO1,USART8_CK_RTS,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D bit 11" "USART3_CTS,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D bit 10" "USART3_CK,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D bit 9" "USART3_RX,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D bit 8" "USART3_TX,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOD_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port D reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port D reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port D reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port D reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port D reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port D reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port D reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port D reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Port D reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port D reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port D reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port D reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port D reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port D reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port D reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port D reset bit 0" "No effect,Reset"
|
|
elif (cpuis("STM32F071R*"))||(cpuis("STM32F072R*"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOD_MODER,GPIO port D mode register"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOD_OTYPER,GPIO port D mode register"
|
|
bitfld.long 0x04 2. " OT2 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOD_OSPEEDR,GPIO port D output speed register"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOD_PUPDR,GPIO port D pull-up/pull-down register"
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port D configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOD_IDR,GPIO port D input data register"
|
|
bitfld.long 0x00 2. " IDR2 ,Port D input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOD_ODR,GPIO port D output data register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port D output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOD_LCKR,GPIO port D configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
bitfld.long 0x00 2. " LCK2 ,Port D lock bit" "Not locked,Locked"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D bit 2" "TIM3_ETR,USART3_RTS,?..."
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOD_BRR,Port bit reset register"
|
|
bitfld.long 0x00 2. " BR2 ,Port D reset bit 2" "No effect,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F078V*")||cpuis("STM32F091V*"))
|
|
tree "GPIO E"
|
|
base ad:0x48001000
|
|
width 15.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOE_MODER,GPIO port E mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOE_OTYPER,GPIO port E mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OT7 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOE_OSPEEDR,GPIO port E output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOE_PUPDR,GPIO port E pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port E configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOE_IDR,GPIO port E input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IDR7 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port E input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOE_ODR,GPIO port E output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr , Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr , Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr , Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr , Port E output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr , Port E output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOE_LCKR,GPIO port E configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Activated,Activated"
|
|
bitfld.long 0x00 15. " LCK15 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " LCK7 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCK0 ,Port E lock bit" "Not locked,Locked"
|
|
sif (cpuis("STM32F072*")||cpuis("STM32F078VB"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E bit 7" "TIM1_ETR,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E bit 6" "TIM3_CH4,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E bit 5" "TIM3_CH3,TSC_G7_IO4,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port E bit 4" "TIM3_CH2,TSC_G7_IO3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port E bit 3" "TIM3_CH1,TSC_G7_IO2,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TIM3_ETR,TSC_G7_IO1,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port E bit 1" "TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" "TIM16_CH1,EVENTOUT,?..."
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E bit 15" "TIM1_BKIN,SPI1_MOSI/I2S1_SD,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E bit 14" "TIM1_CH4,SPI1_MISO/I2S1_MCK,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E bit 13" "TIM1_CH3,SPI1_SCK/I2S1_CK,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E bit 12" "TIM1_CH3N,SPI1_NSS/I2S1_WS,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E bit 11" "TIM1_CH2,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E bit 10" "TIM1_CH2N,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E bit 9" "TIM1_CH1,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E bit 8" "TIM1_CH1N,?..."
|
|
elif (cpuis("STM32F071*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E bit 7" "TIM1_ETR,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E bit 6" "TIM3_CH4,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E bit 5" "TIM3_CH3,TSC_G7_IO4,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port E bit 4" "TIM3_CH2,TSC_G7_IO3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port E bit 3" "TIM3_CH1,TSC_G7_IO2,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TIM3_ETR,TSC_G7_IO1,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port E bit 1" "TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" "TIM16_CH1,EVENTOUT,?..."
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E bit 15" "TIM1_BKIN,SPI1_MOSI/I2S1_SD,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E bit 14" "TIM1_CH4,SPI1_MISO/I2S1_MCK,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E bit 13" "TIM1_CH3,SPI1_SCK/I2S1_CK,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E bit 12" "TIM1_CH3N,SPI1_NSS/I2S1_WS,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E bit 11" "TIM1_CH2,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E bit 10" "TIM1_CH2N,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E bit 9" "TIM1_CH1,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E bit 8" "TIM1_CH1N,?..."
|
|
elif (cpuis("STM32F091V*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E bit 7" "TIM1_ETR,USART5_CK_RTS,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E bit 6" "TIM3_CH4,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E bit 5" "TIM3_CH3,TSC_G7_IO4,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port E bit 4" "TIM3_CH2,TSC_G7_IO3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port E bit 3" "TIM3_CH1,TSC_G7_IO2,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TIM3_ETR,TSC_G7_IO1,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port E bit 1" "TIM17_CH1,EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" "TIM16_CH1,EVENTOUT,?..."
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E bit 15" "TIM1_BKIN,SPI1_MOSI/I2S1_SD,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E bit 14" "TIM1_CH4,SPI1_MISO/I2S1_MCK,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E bit 13" "TIM1_CH3,SPI1_SCK/I2S1_CK,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E bit 12" "TIM1_CH3N,SPI1_NSS/I2S1_WS,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E bit 11" "TIM1_CH2,USART5_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E bit 10" "TIM1_CH2N,USART5_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E bit 9" "TIM1_CH1,USART4_RX,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E bit 8" "TIM1_CH1N,USART4_TX,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOE_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port E reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port E reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port E reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port E reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port E reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port E reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port E reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port E reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BR7 ,Port E reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port E reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port E reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port E reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port E reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port E reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port E reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port E reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "GPIO F"
|
|
base ad:0x48001400
|
|
width 18.
|
|
sif (cpuis("STM32F078VB")||cpuis("STM32F091V*"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F mode register"
|
|
bitfld.long 0x04 10. " OT10 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 3. " OT3 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 2. " OT2 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
bitfld.long 0x00 10. " IDR10 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 3. " IDR3 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDR2 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOF_ODR,GPIO port F output data register"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR6_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR5_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR4_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port F output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOF_LCKR,GPIO port F configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not activated,Activated"
|
|
bitfld.long 0x00 10. " LCK10 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " LCK3 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port F lock bit" "Not locked,Locked"
|
|
sif (cpuis("STM32F091V*"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port F bit 3" "EVENTOUT,USART7_RX,USART6_CK_RTS,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port F bit 2" "EVENTOUT,USART7_TX,USART7_CK_RTS,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F bit 1" ",I2C1_SCL,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" "CRS_SYNC,I2C1_SDA,?..."
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port F bit 10" "TIM15_CH2,USART6_RX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port F bit 9" "TIM15_CH1,USART6_TX,?..."
|
|
endif
|
|
sif (cpuis("STM32F078VB"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port F bit 3" "EVENTOUT,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port F bit 2" "EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" "CRS_SYNC,?..."
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port F bit 10" "TIM15_CH2,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port F bit 9" "TIM15_CH1,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 10. " BR10 ,Port F reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port F reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port F reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 3. " BR3 ,Port F reset bit 3" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BR2 ,Port F reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port F reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port F reset bit 0" "No effect,Reset"
|
|
elif (cpu()=="STM32F051R4"||cpu()=="STM32F051R6"||cpu()=="STM32F051R8"||cpuis("STM32F058R8")||cpuis("STM32F030R8"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F mode register"
|
|
bitfld.long 0x04 7. " OT7 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
bitfld.long 0x00 7. " IDR7 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOF_ODR,GPIO port F output data register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port F output data" "Low,High"
|
|
sif (cpuis("STM32F058R8"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port F bit 7" "I2C2_SDA,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port F bit 6" "I2C2_SCL,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port F bit 5" "EVENTOUT,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port F bit 4" "EVENTOUT,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 7. " BR7 ,Port F reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port F reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port F reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port F reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BR1 ,Port F reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port F reset bit 0" "No effect,Reset"
|
|
elif (cpu()=="STM32F050C4"||cpu()=="STM32F050C6"||cpu()=="STM32F051C4"||cpu()=="STM32F051C6"||cpu()=="STM32F051C8"||cpuis("STM32F038C6")||cpuis("STM32F058C8"))
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F mode register"
|
|
bitfld.long 0x04 7. " OT7 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 6. " OT6 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
bitfld.long 0x00 7. " IDR7 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 6. " IDR6 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOF_ODR,GPIO port F output data register"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port F output data" "Low,High"
|
|
sif (cpuis("STM32F038C6"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port F bit 7" "I2C1_SCL,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port F bit 6" "I2C1_SDA,?..."
|
|
elif (cpuis("STM32F058C8"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port F bit 7" "I2C1_SCL,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port F bit 6" "I2C1_SDA,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 7. " BR7 ,Port F reset bit 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " BR6 ,Port F reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port F reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port F reset bit 0" "No effect,Reset"
|
|
else
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
sif (cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F mode register"
|
|
sif (cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
bitfld.long 0x04 11. " OT11 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
sif (cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
sif (cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up/pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
sif (cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
bitfld.long 0x00 11. " IDR11 ,Port F input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOF_ODR,GPIO port F output data register"
|
|
sif (cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port F output data" "Low,High"
|
|
sif !cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F031E6")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070RB")&&!cpuis("STM32F070F6")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOF_LCKR,GPIO port F configuration lock register"
|
|
bitfld.long 0x00 1. " LCK1 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port F lock bit" "Not locked,Locked"
|
|
endif
|
|
sif (cpuis("STM32F048G6")||cpuis("STM32F048T6")||cpuis("STM32F091C*")||cpuis("STM32F091R*")||cpuis("STM32F098CC")||cpuis("STM32F048C6")||cpuis("STM32F098RC"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F bit 1" "CRS_SYNC,I2C1_SDA,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" ",I2C1_SCL,?..."
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F bit 1" ",I2C1_SCL,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" ",I2C1_SDA,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x00 1. " BR1 ,Port F reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port F reset bit 0" "No effect,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050*")||cpuis("STM32F051T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB"))
|
|
tree "SYSCFG (System configuration controller)"
|
|
base ad:0x40010000
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SYSCFG_CFGR1,SYSCFG configuration register 1"
|
|
sif CPUIS("STM32F070CB")||CPUIS("STM32F070RB")
|
|
bitfld.long 0x00 26. " USART3_DMA_RMP ,USART3 DMA request remapping bit" "No remap,Remap"
|
|
textline " "
|
|
elif cpuis("STM32F07*")
|
|
sif !CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.long 0x00 30. " TIM3_DMA_RMP ,TIM3 DMA request remapping bit" "No remap,Remap"
|
|
bitfld.long 0x00 29. " TIM2_DMA_RMP ,TIM2 DMA request remapping bit" "No remap,Remap"
|
|
bitfld.long 0x00 28. " TIM1_DMA_RMP ,TIM1 DMA request remapping bit" "No remap,Remap"
|
|
bitfld.long 0x00 27. " I2C1_DMA_RMP ,I2C1 DMA request remapping bit" "No remap,Remap"
|
|
textline " "
|
|
bitfld.long 0x00 26. " USART3_DMA_RMP ,USART3 DMA request remapping bit" "No remap,Remap"
|
|
bitfld.long 0x00 25. " USART2_DMA_RMP ,USART2 DMA request remapping bit" "No remap,Remap"
|
|
bitfld.long 0x00 24. " SPI2_DMA_RMP ,SPI2 DMA request remapping bit" "No remap,Remap"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif !CPUIS("STM32F030?8")
|
|
sif (cpuis("STM32F03*")||cpuis("STM32F04*")||CPUIS("STM32F09*")||CPUIS("STM32F070F6")||CPUIS("STM32F070C6"))
|
|
bitfld.long 0x00 23. " I2C_PA10_FM+ ,This bit enables I2C FM+ mode for PA10 I/O" "Standard,I2C FM+"
|
|
bitfld.long 0x00 22. " I2C_PA9_FM+ ,This bit enables I2C FM+ mode for PA9 I/O" "Standard,I2C FM+"
|
|
textline " "
|
|
sif !CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
sif (cpuis("STM32F07*")||cpuis("STM32F09*"))
|
|
bitfld.long 0x00 21. " I2C2_FMP ,FM+ driving capability activation for I2C2" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
endif
|
|
sif !cpuis("STM32F05*")&&!CPUIS("STM32F030?8")
|
|
bitfld.long 0x00 20. " I2C1_FMP ,FM+ driving capability activation for I2C1" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 19. " I2C_PB9_FM+ ,This bit enables I2C FM+ mode for PB9 I/Os" "Standard,I2C FM+"
|
|
bitfld.long 0x00 18. " I2C_PB8_FM+ ,This bit enables I2C FM+ mode for PB8 I/Os" "Standard,I2C FM+"
|
|
bitfld.long 0x00 17. " I2C_PB7_FM+ ,This bit enables I2C FM+ mode for PB7 I/Os" "Standard,I2C FM+"
|
|
bitfld.long 0x00 16. " I2C_PB6_FM+ ,This bit enables I2C FM+ mode for PB6 I/Os" "Standard,I2C FM+"
|
|
textline " "
|
|
sif (cpuis("STM32F07*"))
|
|
sif !CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.long 0x00 14. " TIM17_DMA_RMP2 ,TIM17 alternate DMA request remapping bit" "No remap,Remap"
|
|
bitfld.long 0x00 13. " TIM16_DMA_RMP2 ,TIM16 alternate DMA request remapping bit." "No remap,Remap"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif !CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")
|
|
sif (cpuis("STM32F03*")||cpuis("STM32F04*")||CPUIS("STM32F05*")||CPUIS("STM32F07*"))
|
|
bitfld.long 0x00 12. " TIM17_DMA_RMP ,TIM17 DMA request remapping bit" "No remap,Remap"
|
|
bitfld.long 0x00 11. " TIM16_DMA_RMP ,TIM16 DMA request remapping bit" "No remap,Remap"
|
|
bitfld.long 0x00 10. " USART1_RX_DMA_RMP ,USART1_RX DMA request remapping bit" "No remap,Remap"
|
|
bitfld.long 0x00 9. " USART1_TX_DMA_RMP ,USART1_TX DMA remapping bit" "No remap,Remap"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ADC_DMA_RMP ,ADC DMA remapping bit" "No remap,Remap"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F09*"))
|
|
bitfld.long 0x00 6.--7. " IRDA_ENV_SEL ,IRDA Modulation Envelope signal source selection" "Timer16,USART1,USART4,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F04*"))||(cpuis("STM32F04*")||CPUIS("STM32F070F6")||CPUIS("STM32F070C6"))
|
|
bitfld.long 0x00 4. " PA11_PA12_RMP ,PA11 and PA12 remapping bit" "No remap,Remap"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " MEM_MODE ,Memory mapping selection bits" "Main Flash,System Flash,Main Flash,Embedded SRAM"
|
|
group.long 0x08++0x13
|
|
sif (cpuis("STM32F050G6")||CPUIS("STM32F031G*"))
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,?..."
|
|
elif CPUIS("STM32F042K")
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,?..."
|
|
elif CPUIS("STM32F042T")
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,?..."
|
|
elif CPUIS("STM32F042G")
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" ",PB8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,?..."
|
|
elif CPUIS("STM32F031K")
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,?..."
|
|
elif CPUIS("STM32F031F*")||CPUIS("STM32F042F*")
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,?..."
|
|
elif CPUIS("STM32F072C*")||CPUIS("STM32F071CB")||CPUIS("STM32F031C*")||CPUIS("STM32F031C*")||CPUIS("STM32F042C")
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,?..."
|
|
elif CPUIS("STM32F072R*")||CPUIS("STM32F071RB")
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,?..."
|
|
elif CPUIS("STM32F072V*")||CPUIS("STM32F071V*")
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,PD3,PE3,PF3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,PE2,PF2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,PD0,PE0,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,PF6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,PD11,PE11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,PF10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,PF9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,PD15,PE15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,PD14,PE14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,PD13,PE13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,PD12,PE12,?..."
|
|
elif (cpuis("STM32F038F6"))
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,?..."
|
|
elif (cpuis("STM32F038G6"))
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,?..."
|
|
elif (cpuis("STM32F038K6"))
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,?..."
|
|
elif (cpuis("STM32F038C6"))
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,,,,PF7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,,,,PF6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,?..."
|
|
elif (cpuis("STM32F048G6"))
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,,,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" ",PB8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,?..."
|
|
elif (cpuis("STM32F048T6"))
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,,,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,?..."
|
|
elif (cpuis("STM32F048C6"))
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,,,,,PF11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,?..."
|
|
elif (cpuis("STM32F058C8"))
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,PD1,PE1,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,PD0,PE0,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,,,,PF7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,,,,PF6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,?..."
|
|
elif (cpuis("STM32F058R8"))
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,,PC2,PD2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,,,PF7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,,,PF6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,,,PF5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,,,PF4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,?..."
|
|
elif (cpuis("STM32F078CB"))
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,PD1,PE1,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,PD0,PE0,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,?..."
|
|
elif (cpuis("STM32F078RB")||cpuis("STM32F091R*")||cpuis("STM32F098RC"))
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,,PC2,PD2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,,,PF11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,?..."
|
|
elif (cpuis("STM32F078VB"))
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,PD3,PE3,PF3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,,PC2,PD2,PE2,PF2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,PD0,PE0,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,PF6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,PD11,PE11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,PF10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,PF9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,PD15,PE15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,PD14,PE14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,PD13,PE13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,PD12,PE12,?..."
|
|
elif (cpuis("STM32F091C*")||cpuis("STM32F098CC"))
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,PD1,PE1,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,PD0,PE0,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,?..."
|
|
textline " "
|
|
sif (!cpuis("STM32F098CC"))
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,?..."
|
|
elif (cpuis("STM32F091V*"))
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,PD3,PE3,PF3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,PE2,PF2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,PD0,PE0,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,PF6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,PD11,PE11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,PF10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,PF9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,PD15,PE15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,PD14,PE14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,PD13,PE13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,PD12,PE12,?..."
|
|
elif CPUIS("STM32F031E6")||CPUIS("STM32F038E6")
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,?..."
|
|
elif CPUIS("STM32F051T8")||CPUIS("STM32F058T8")
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,?..."
|
|
elif CPUIS("STM32F030CC")
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,,,,PF7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,,,,PF6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,?..."
|
|
elif CPUIS("STM32F030RC")
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,,,,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,,PC2,PD2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,,,PF7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,,,PF6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,,,PF5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,,,PF4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,?..."
|
|
elif CPUIS("STM32F070C6")||CPUIS("STM32F070CB")
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,?..."
|
|
elif CPUIS("STM32F070RB")
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,,,,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,?..."
|
|
elif CPUIS("STM32F070F6")
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,?..."
|
|
else
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,PD3,PE3,PF3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,PE2,PF2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,PD0,PE0,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,PF7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,PF6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,PF5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,PF4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,PD11,PE11,PF11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,PF10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,PF9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,PF8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,PD15,PE15,PF15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,PD14,PE14,PF14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,PD13,PE13,PF13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,PD12,PE12,PF12,?..."
|
|
endif
|
|
line.long 0x10 "SYSCFG_CFGR2,SYSCFG configuration register 2"
|
|
eventfld.long 0x10 8. " SRAM_PEF ,SRAM parity error" "No error,Error"
|
|
textline " "
|
|
sif !CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.long 0x10 2. " PVD_LOCK ,PVD lock enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 1. " SRAM_PARITY_LOCK ,SRAM parity lock bit" "Not locked,Locked"
|
|
bitfld.long 0x10 0. " LOCKUP_LOCK ,Cortex-M0 LOCKUP bit enable bit" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "SYSCFG (System configuration controller)"
|
|
base ad:0x40010000
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SYSCFG_CFGR1,SYSCFG configuration register 1"
|
|
sif cpuis("STM32F030?6")||cpuis("STM32F030?4")
|
|
bitfld.long 0x00 23. " I2C_PA10_FM+ ,Fast Mode Plus (FM+) driving capability activation bits" "Standard,FM+ mode"
|
|
bitfld.long 0x00 22. " I2C_PA9_FM+ ,Fast Mode Plus (FM+) driving capability activation bits" "Standard,FM+ mode"
|
|
bitfld.long 0x00 20. " I2C1_FM+ ,FM+ driving capability activation for I2C1" "I2C_Pxx_FM+,GPIOx_AFR"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030F4")
|
|
sif ((!cpuis("STM32F051K4"))&&(!cpuis("STM32F051K6"))&&(!cpuis("STM32F051K8")))
|
|
bitfld.long 0x00 19. " I2C_PB9_FM+ ,This bit enables I2C FM+ mode for PB9 I/Os" "Standard,I2C FM+"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " I2C_PB8_FM+ ,This bit enables I2C FM+ mode for PB8 I/Os" "Standard,I2C FM+"
|
|
textline " "
|
|
sif !cpuis("STM32F030K6")
|
|
bitfld.long 0x00 17. " I2C_PB7_FM+ ,This bit enables I2C FM+ mode for PB7 I/Os" "Standard,I2C FM+"
|
|
bitfld.long 0x00 16. " I2C_PB6_FM+ ,This bit enables I2C FM+ mode for PB6 I/Os" "Standard,I2C FM+"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 12. " TIM17_DMA_RMP ,TIM17 DMA request remapping bit" "No remap,Remap"
|
|
bitfld.long 0x00 11. " TIM16_DMA_RMP ,TIM16 DMA request remapping bit" "No remap,Remap"
|
|
bitfld.long 0x00 10. " USART1_RX_DMA_RMP ,USART1_RX DMA request remapping bit" "No remap,Remap"
|
|
textline " "
|
|
bitfld.long 0x00 9. " USART1_TX_DMA_RMP ,USART1_TX DMA remapping bit" "No remap,Remap"
|
|
bitfld.long 0x00 8. " ADC_DMA_RMP ,ADC DMA remapping bit" "No remap,Remap"
|
|
bitfld.long 0x00 0.--1. " MEM_MODE[1:0] ,Memory mapping selection bits" "Main Flash,System Flash,Main Flash,Embedded SRAM"
|
|
group.long 0x08++0x13
|
|
sif (cpuis("STM32F051R4")||cpuis("STM32F051R6")||cpuis("STM32F051R8")||cpuis("STM32F030R8"))
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,,,PF7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,,,PF6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,,,PF5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,,,PF4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,?..."
|
|
elif (cpuis("STM32F051C4")||cpuis("STM32F051C6")||cpuis("STM32F051C8"))
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,,,,PF7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,,,,PF6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,?..."
|
|
elif cpuis("STM32F030C6")||cpuis("STM32F030C8")
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,?..."
|
|
elif cpuis("STM32F030K6")
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,?..."
|
|
elif cpuis("STM32F030F4")
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,?..."
|
|
else
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,?..."
|
|
endif
|
|
line.long 0x10 "SYSCFG_CFGR2,SYSCFG configuration register 2"
|
|
eventfld.long 0x10 8. " SRAM_PEF ,SRAM parity error" "No error,Error"
|
|
textline " "
|
|
sif !cpuis("STM32F030*")
|
|
bitfld.long 0x10 2. " PVD_LOCK ,PVD lock enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 1. " SRAM_PARITY_LOCK ,SRAM parity lock bit" "Not locked,Locked"
|
|
bitfld.long 0x10 0. " LOCKUP_LOCK ,Cortex-M0 LOCKUP bit enable bit" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "DMA (Direct memory access controller)"
|
|
tree "DMA1"
|
|
base ad:0x40020000
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DMA_ISR,DMA interrupt status register"
|
|
sif (cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||CPUIS("STM32F031E6")||CPUIS("STM32F038E6")||CPUIS("STM32F051T8")||CPUIS("STM32F058T8")||cpuis("STM32F071*"))
|
|
bitfld.long 0x00 27. " TEIF7 ,Channel 7 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 26. " HTIF7 ,Channel 7 Half Transfer flag" "Not transferred,Transferred"
|
|
bitfld.long 0x00 25. " TCIF7 ,Channel 7 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " GIF7 ,Channel 7 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 23. " TEIF6 ,Channel 6 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 22. " HTIF6 ,Channel 6 Half Transfer flag" "Not transferred,Transferred"
|
|
bitfld.long 0x00 21. " TCIF6 ,Channel 6 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 20. " GIF6 ,Channel 6 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " TEIF5 ,Channel 5 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 18. " HTIF5 ,Channel 5 Half Transfer flag" "Not transferred,Transferred"
|
|
bitfld.long 0x00 17. " TCIF5 ,Channel 5 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 16. " GIF5 ,Channel 5 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TEIF4 ,Channel 4 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 14. " HTIF4 ,Channel 4 Half Transfer flag" "Not transferred,Transferred"
|
|
bitfld.long 0x00 13. " TCIF4 ,Channel 4 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 12. " GIF4 ,Channel 4 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TEIF3 ,Channel 3 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 10. " HTIF3 ,Channel 3 Half Transfer flag" "Not transferred,Transferred"
|
|
bitfld.long 0x00 9. " TCIF3 ,Channel 3 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 8. " GIF3 ,Channel 3 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TEIF2 ,Channel 2 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 6. " HTIF2 ,Channel 2 Half Transfer flag" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " TCIF2 ,Channel 2 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " GIF2 ,Channel 2 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIF1 ,Channel 1 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 2. " HTIF1 ,Channel 1 Half Transfer flag" "Not transferred,Transferred"
|
|
bitfld.long 0x00 1. " TCIF1 ,Channel 1 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " GIF1 ,Channel 1 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DMA_IFCR,DMA interrupt flag clear register"
|
|
sif (cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||CPUIS("STM32F031E6")||CPUIS("STM32F038E6")||CPUIS("STM32F051T8")||CPUIS("STM32F058T8")||cpuis("STM32F071*"))
|
|
bitfld.long 0x00 27. " CTEIF7 ,Channel 7 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 26. " CHTIF7 ,Channel 7 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " CTCIF7 ,Channel 7 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " CGIF7 ,Channel 7 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CTEIF6 ,Channel 6 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " CHTIF6 ,Channel 6 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " CTCIF6 ,Channel 6 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 20. " CGIF6 ,Channel 6 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " CTEIF5 ,Channel 5 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " CHTIF5 ,Channel 5 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CTCIF5 ,Channel 5 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CGIF5 ,Channel 5 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CTEIF4 ,Channel 4 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CHTIF4 ,Channel 4 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 13. " CTCIF4 ,Channel 4 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CGIF4 ,Channel 4 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTEIF3 ,Channel 3 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CHTIF3 ,Channel 3 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CTCIF3 ,Channel 3 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CGIF3 ,Channel 3 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTEIF2 ,Channel 2 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CHTIF2 ,Channel 2 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CTCIF2 ,Channel 2 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CGIF2 ,Channel 2 Global Interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CTEIF1 ,Channel 1 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CHTIF1 ,Channel 1 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CTCIF1 ,Channel 1 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
sif (cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||CPUIS("STM32F031E6")||CPUIS("STM32F038E6")||CPUIS("STM32F051T8")||CPUIS("STM32F058T8")||cpuis("STM32F071*"))
|
|
group.long 0x8++0x0F "Channel 1"
|
|
line.long 0x00 "DMA_CCR1,DMA channel 1 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR1,DMA channel 1 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR1,DMA channel 1 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR1,DMA channel 1 memory address register"
|
|
group.long 0x1C++0x0F "Channel 2"
|
|
line.long 0x00 "DMA_CCR2,DMA channel 2 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR2,DMA channel 2 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR2,DMA channel 2 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR2,DMA channel 2 memory address register"
|
|
group.long 0x30++0x0F "Channel 3"
|
|
line.long 0x00 "DMA_CCR3,DMA channel 3 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR3,DMA channel 3 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR3,DMA channel 3 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR3,DMA channel 3 memory address register"
|
|
group.long 0x44++0x0F "Channel 4"
|
|
line.long 0x00 "DMA_CCR4,DMA channel 4 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR4,DMA channel 4 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR4,DMA channel 4 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR4,DMA channel 4 memory address register"
|
|
group.long 0x58++0x0F "Channel 5"
|
|
line.long 0x00 "DMA_CCR5,DMA channel 5 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR5,DMA channel 5 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR5,DMA channel 5 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR5,DMA channel 5 memory address register"
|
|
group.long 0x6C++0x0F "Channel 6"
|
|
line.long 0x00 "DMA_CCR6,DMA channel 6 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR6,DMA channel 6 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR6,DMA channel 6 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR6,DMA channel 6 memory address register"
|
|
group.long 0x80++0x0F "Channel 7"
|
|
line.long 0x00 "DMA_CCR7,DMA channel 7 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR7,DMA channel 7 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR7,DMA channel 7 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR7,DMA channel 7 memory address register"
|
|
else
|
|
group.long 0x8++0x0F "Channel 1"
|
|
line.long 0x00 "DMA_CCR1,DMA channel 1 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR1,DMA channel 1 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR1,DMA channel 1 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR1,DMA channel 1 memory address register"
|
|
group.long 0x1C++0x0F "Channel 2"
|
|
line.long 0x00 "DMA_CCR2,DMA channel 2 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR2,DMA channel 2 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR2,DMA channel 2 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR2,DMA channel 2 memory address register"
|
|
group.long 0x30++0x0F "Channel 3"
|
|
line.long 0x00 "DMA_CCR3,DMA channel 3 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR3,DMA channel 3 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR3,DMA channel 3 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR3,DMA channel 3 memory address register"
|
|
group.long 0x44++0x0F "Channel 4"
|
|
line.long 0x00 "DMA_CCR4,DMA channel 4 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR4,DMA channel 4 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR4,DMA channel 4 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR4,DMA channel 4 memory address register"
|
|
group.long 0x58++0x0F "Channel 5"
|
|
line.long 0x00 "DMA_CCR5,DMA channel 5 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR5,DMA channel 5 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR5,DMA channel 5 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR5,DMA channel 5 memory address register"
|
|
endif
|
|
sif CPUIS("STM32F030CC")||CPUIS("STM32F030RC")
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "DMA_CSELR,DMA channel selection register"
|
|
bitfld.long 0x00 16.--19. " C5S ,DMA channel 5 selection" "TIM1_UP/TIM15_CH1_TIM15_UP_TIM15_TRIG_TIM15_COM/USART2_RX/SPI2_TX,I2C2_Rx/TIM1_CH3,,I2C2_RX,SPI2_TX,TIM1_CH3,,,,USART1_RX,USART2_RX,USART3_RX,USART4_RX,USART5_RX,USART6_RX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " C4S ,DMA channel 4 selection" "TIM1_CH4_TIM1_TRIG_TIM1_COM/TIM7_UP/USART2_TX/SPI2_RX/I2C2_TX/TIM3_CH1_TIM3_TRIG,TIM7_UP,I2C2_TX,SPI2_RX,,,TIM3_CH1_TIM3_TRIG,TIM16_CH1_TIM16_UP,USART1_TX,USART2_TX,USART3_TX,USART4_TX,USART5_TX,USART6_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " C3S ,DMA channel 3 selection" "TIM3_CH4_TIM3_UP/TIM6_UP/USART1_RX/SPI1_TX/I2C1_RX/TIM1_CH2/TIM16_CH1_TIM16_UP,TIM6_UP,I2C1_RX,SPI1_TX,TIM1_CH2,,,TIM16_CH1_TIM16_UP,USART1_RX,USART2_RX,USART3_RX,USART4_RX,USART5_RX,USART6_RX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " C2S ,DMA channel 2 selection" "TIM3_CH3/USART1_TX/SPI1_RX/I2C1_TX/TIM1_CH1,ADC,I2C1_TX,SPI1_RX,TIM1_CH1,,,TIM17_CH1_TIM17_UP,USART1_TX,USART2_TX,USART3_TX,USART4_TX,USART5_TX,USART6_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " C1S ,DMA channel 1 selection" "ADC/TIM17_CH1_TIM17_UP,ADC,,,,,,TIM17_CH1_TIM17_UP,USART1_RX,USART2_RX,USART3_RX,USART4_RX,USART5_RX,USART6_RX,?..."
|
|
endif
|
|
sif (cpuis("STM32F09*"))
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "DMA_CSELR,DMA channel selection register"
|
|
bitfld.long 0x00 24.--27. " C7S ,DMA channel 7 selection" "USART3_TX/USART4_TX,,I2C1_RX,SPI2_TX,,TIM2_CH2/TIM2_CH4,,TIM17_CH1/TIM17_UP,USART1_TX,USART2_TX,USART3_TX,USART4_TX,USART5_TX,USART6_TX,USART7_TX,USART8_TX"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " C6S ,DMA channel 6 selection" "USART3_RX/USART4_RX,,I2C1_TX,SPI2_RX,TIM1_CH1/TIM1_CH2/TIM1_CH3,,TIM3_CH1/TIM3_TRIG,TIM16_CH1/TIM16_UP,USART1_RX,USART2_RX,USART3_RX,USART4_RX,USART5_RX,USART6_RX,USART7_RX,USART8_RX"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " C5S ,DMA channel 5 selection" "TIM1_UP/TIM2_CH1/TIM15_CH1/TIM15_UP/TIM15_TRIG/TIM15_COM/USART2_RX/SPI2_TX/I2C2_RX/TIM1_CH3,,I2C2_RX,SPI2_TX,TIM1_CH3,,,,USART1_RX,USART2_RX,USART3_RX,USART4_RX,USART5_RX,USART6_RX,USART7_RX,USART8_RX"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " C4S ,DMA channel 4 selection" "TIM1_CH4/TIM1_TRIG/TIM1_COM/TIM7_UP/DAC_2/USART2_TX/SPI2_RX/I2C2_TX/TIM2_CH4/TIM3_CH1/TIM3_TRIG,TIM7_UP/DAC_2,I2C2_TX,SPI2_RX,,TIM2_CH4,TIM3_CH1/TIM3_TRIG,TIM16_CH1/TIM16_UP,USART1_TX,USART2_TX,USART3_TX,USART4_TX,USART5_TX,USART6_TX,USART7_TX,USART8_TX"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " C3S ,DMA channel 3 selection" "TIM3_CH4/TIM3_UP/TIM6_UP/DAC_1/USART1_RX/SPI1_TX/I2C1_RX/TIM1_CH2/TIM2_CH2/TIM16_CH1/TIM16_UP,TIM6_UP/DAC_1,I2C1_RX,SPI1_TX,TIM1_CH2,TIM2_CH2,,TIM16_CH1/TIM16_UP,USART1_RX,USART2_RX,USART3_RX,USART4_RX,USART5_RX,USART6_RX,USART7_RX,USART8_RX"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " C2S ,DMA channel 2 selection" "TIM2_UP/TIM3_CH3/USART1_TX/SPI1_RX/I2C1_TX/TIM1_CH1,ADC,I2C1_TX,SPI1_RX,TIM1_CH1,,,TIM17_CH1/TIM17_UP,USART1_TX,USART2_TX,USART3_TX,USART4_TX,USART5_TX,USART6_TX,USART7_TX,USART8_TX"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " C1S ,DMA channel 1 selection" "TIM2_CH3/ADC/TIM17_CH1/TIM17_UP,ADC,,,,,,TIM17_CH1/TIM17_UP,USART1_RX,USART2_RX,USART3_RX,USART4_RX,USART5_RX,USART6_RX,USART7_RX,USART8_RX"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*"))
|
|
tree "DMA2"
|
|
base ad:0x40020400
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DMA_ISR,DMA interrupt status register"
|
|
sif (cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||CPUIS("STM32F031E6")||CPUIS("STM32F038E6")||CPUIS("STM32F051T8")||CPUIS("STM32F058T8")||cpuis("STM32F071*"))
|
|
endif
|
|
bitfld.long 0x00 19. " TEIF5 ,Channel 5 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 18. " HTIF5 ,Channel 5 Half Transfer flag" "Not transferred,Transferred"
|
|
bitfld.long 0x00 17. " TCIF5 ,Channel 5 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 16. " GIF5 ,Channel 5 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TEIF4 ,Channel 4 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 14. " HTIF4 ,Channel 4 Half Transfer flag" "Not transferred,Transferred"
|
|
bitfld.long 0x00 13. " TCIF4 ,Channel 4 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 12. " GIF4 ,Channel 4 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TEIF3 ,Channel 3 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 10. " HTIF3 ,Channel 3 Half Transfer flag" "Not transferred,Transferred"
|
|
bitfld.long 0x00 9. " TCIF3 ,Channel 3 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 8. " GIF3 ,Channel 3 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TEIF2 ,Channel 2 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 6. " HTIF2 ,Channel 2 Half Transfer flag" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " TCIF2 ,Channel 2 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " GIF2 ,Channel 2 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIF1 ,Channel 1 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 2. " HTIF1 ,Channel 1 Half Transfer flag" "Not transferred,Transferred"
|
|
bitfld.long 0x00 1. " TCIF1 ,Channel 1 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " GIF1 ,Channel 1 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DMA_IFCR,DMA interrupt flag clear register"
|
|
sif (cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||CPUIS("STM32F031E6")||CPUIS("STM32F038E6")||CPUIS("STM32F051T8")||CPUIS("STM32F058T8")||cpuis("STM32F071*"))
|
|
endif
|
|
bitfld.long 0x00 19. " CTEIF5 ,Channel 5 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " CHTIF5 ,Channel 5 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CTCIF5 ,Channel 5 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CGIF5 ,Channel 5 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CTEIF4 ,Channel 4 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CHTIF4 ,Channel 4 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 13. " CTCIF4 ,Channel 4 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CGIF4 ,Channel 4 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTEIF3 ,Channel 3 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CHTIF3 ,Channel 3 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CTCIF3 ,Channel 3 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CGIF3 ,Channel 3 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTEIF2 ,Channel 2 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CHTIF2 ,Channel 2 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CTCIF2 ,Channel 2 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CGIF2 ,Channel 2 Global Interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CTEIF1 ,Channel 1 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CHTIF1 ,Channel 1 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CTCIF1 ,Channel 1 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
sif (cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*"))
|
|
group.long 0x8++0x0F "Channel 1"
|
|
line.long 0x00 "DMA_CCR1,DMA channel 1 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR1,DMA channel 1 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR1,DMA channel 1 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR1,DMA channel 1 memory address register"
|
|
endif
|
|
sif (cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*"))
|
|
group.long 0x1C++0x0F "Channel 2"
|
|
line.long 0x00 "DMA_CCR2,DMA channel 2 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR2,DMA channel 2 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR2,DMA channel 2 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR2,DMA channel 2 memory address register"
|
|
endif
|
|
sif (cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*"))
|
|
group.long 0x30++0x0F "Channel 3"
|
|
line.long 0x00 "DMA_CCR3,DMA channel 3 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR3,DMA channel 3 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR3,DMA channel 3 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR3,DMA channel 3 memory address register"
|
|
endif
|
|
sif (cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*"))
|
|
group.long 0x44++0x0F "Channel 4"
|
|
line.long 0x00 "DMA_CCR4,DMA channel 4 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR4,DMA channel 4 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR4,DMA channel 4 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR4,DMA channel 4 memory address register"
|
|
endif
|
|
sif (cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*"))
|
|
group.long 0x58++0x0F "Channel 5"
|
|
line.long 0x00 "DMA_CCR5,DMA channel 5 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8,16,32,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8,16,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR5,DMA channel 5 number of data register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR5,DMA channel 5 peripheral address register"
|
|
line.long 0x0C "DMA_CMAR5,DMA channel 5 memory address register"
|
|
endif
|
|
sif CPUIS("STM32F030CC")||CPUIS("STM32F030RC")
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "DMA_CSELR,DMA channel selection register"
|
|
bitfld.long 0x00 16.--19. " C5S ,DMA channel 5 selection" "TIM1_UP/TIM15_CH1_TIM15_UP_TIM15_TRIG_TIM15_COM/USART2_RX/SPI2_TX,I2C2_Rx/TIM1_CH3,,I2C2_RX,SPI2_TX,TIM1_CH3,,,,USART1_RX,USART2_RX,USART3_RX,USART4_RX,USART5_RX,USART6_RX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " C4S ,DMA channel 4 selection" "TIM1_CH4_TIM1_TRIG_TIM1_COM/TIM7_UP/USART2_TX/SPI2_RX/I2C2_TX/TIM3_CH1_TIM3_TRIG,TIM7_UP,I2C2_TX,SPI2_RX,,,TIM3_CH1_TIM3_TRIG,TIM16_CH1_TIM16_UP,USART1_TX,USART2_TX,USART3_TX,USART4_TX,USART5_TX,USART6_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " C3S ,DMA channel 3 selection" "TIM3_CH4_TIM3_UP/TIM6_UP/USART1_RX/SPI1_TX/I2C1_RX/TIM1_CH2/TIM16_CH1_TIM16_UP,TIM6_UP,I2C1_RX,SPI1_TX,TIM1_CH2,,,TIM16_CH1_TIM16_UP,USART1_RX,USART2_RX,USART3_RX,USART4_RX,USART5_RX,USART6_RX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " C2S ,DMA channel 2 selection" "TIM3_CH3/USART1_TX/SPI1_RX/I2C1_TX/TIM1_CH1,ADC,I2C1_TX,SPI1_RX,TIM1_CH1,,,TIM17_CH1_TIM17_UP,USART1_TX,USART2_TX,USART3_TX,USART4_TX,USART5_TX,USART6_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " C1S ,DMA channel 1 selection" "ADC/TIM17_CH1_TIM17_UP,ADC,,,,,,TIM17_CH1_TIM17_UP,USART1_RX,USART2_RX,USART3_RX,USART4_RX,USART5_RX,USART6_RX,?..."
|
|
endif
|
|
sif (cpuis("STM32F09*"))
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "DMA2_CSELR,DMA channel selection register"
|
|
bitfld.long 0x00 16.--19. " C5S ,DMA channel 5 selection" ",ADC,,,,,,,USART1_TX,USART2_TX,USART3_TX,USART4_TX,USART5_TX,USART6_TX,USART7_TX,USART8_TX"
|
|
bitfld.long 0x00 12.--15. " C4S ,DMA channel 4 selection" ",TIM7_UP/DAC_2,,SPI1_TX,,,,,USART1_TX,USART2_TX,USART3_TX,USART4_TX,USART5_TX,USART6_TX,USART7_TX,USART8_TX"
|
|
bitfld.long 0x00 8.--11. " C3S ,DMA channel 3 selection" ",TIM6_UP/DAC_1,,SPI1_RX,,,,,USART1_RX,USART2_RX,USART3_RX,USART4_RX,USART5_RX,USART6_RX,USART7_RX,USART8_RX"
|
|
bitfld.long 0x00 4.--7. " C2S ,DMA channel 2 selection" ",,I2C2_RX,,,,,,USART1_RX,USART2_RX,USART3_RX,USART4_RX,USART5_RX,USART6_RX,USART7_RX,USART8_RX"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " C1S ,DMA channel 1 selection" ",,I2C2_TX,,,,,,USART1_TX,USART2_TX,USART3_TX,USART4_TX,USART5_TX,USART6_TX,USART7_TX,USART8_TX"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "EXTI (Extended interrupts and events controller)"
|
|
base ad:0x40010400
|
|
width 12.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "EXTI_IMR,EXTI interrupt mask register"
|
|
sif (cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||CPUIS("STM32F051T8")||CPUIS("STM32F031E6")||CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB"))
|
|
bitfld.long 0x00 31. " MR31 , Interrupt mask on line 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " MR30 , Interrupt mask on line 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " MR29 , Interrupt mask on line 29" "Masked,Not masked"
|
|
bitfld.long 0x00 28. " MR28 , Interrupt mask on line 28" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F07*")||cpuis("STM32F09*")||CPUIS("STM32F051T8")||CPUIS("STM32F038E6")||CPUIS("STM32F031E6")||CPUIS("STM32F058T8")||CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB"))
|
|
bitfld.long 0x00 27. " MR27 , Interrupt mask on line 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " MR26 , Interrupt mask on line 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " MR25 , Interrupt mask on line 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " MR24 , Interrupt mask on line 24" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " MR23 , Interrupt mask on line 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " MR22 , Interrupt mask on line 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " MR21 , Interrupt mask on line 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " MR20 , Interrupt mask on line 20" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MR19 , Interrupt mask on line 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " MR18 , Interrupt mask on line 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " MR17 , Interrupt mask on line 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " MR16 , Interrupt mask on line 16" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MR15 , Interrupt mask on line 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " MR14 , Interrupt mask on line 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " MR13 , Interrupt mask on line 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " MR12 , Interrupt mask on line 12" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MR11 , Interrupt mask on line 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " MR10 , Interrupt mask on line 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " MR9 , Interrupt mask on line 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " MR8 , Interrupt mask on line 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MR7 , Interrupt mask on line 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " MR6 , Interrupt mask on line 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " MR5 , Interrupt mask on line 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " MR4 , Interrupt mask on line 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MR3 , Interrupt mask on line 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " MR2 , Interrupt mask on line 2" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " MR1 , Interrupt mask on line 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " MR0 , Interrupt mask on line 0" "Masked,Not masked"
|
|
line.long 0x04 "EXTI_EMR,EXTI event mask register"
|
|
sif (cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||CPUIS("STM32F051T8")||CPUIS("STM32F038E6")||CPUIS("STM32F031E6")||CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB"))
|
|
bitfld.long 0x04 31. " MR31 ,Event mask on line 31" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " MR30 ,Event mask on line 30" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " MR29 ,Event mask on line 29" "Masked,Not masked"
|
|
bitfld.long 0x04 28. " MR28 ,Event mask on line 28" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F07*")||cpuis("STM32F09*")||CPUIS("STM32F051T8")||CPUIS("STM32F038E6")||CPUIS("STM32F031E6")||CPUIS("STM32F058T8")||CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB"))
|
|
bitfld.long 0x04 27. " MR27 ,Event mask on line 27" "Masked,Not masked"
|
|
bitfld.long 0x04 26. " MR26 ,Event mask on line 26" "Masked,Not masked"
|
|
bitfld.long 0x04 25. " MR25 ,Event mask on line 25" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " MR24 ,Event mask on line 24" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 23. " MR23 ,Event mask on line 23" "Masked,Not masked"
|
|
bitfld.long 0x04 22. " MR22 ,Event mask on line 22" "Masked,Not masked"
|
|
bitfld.long 0x04 21. " MR21 ,Event mask on line 21" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " MR20 ,Event mask on line 20" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " MR19 ,Event mask on line 19" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " MR18 ,Event mask on line 18" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " MR17 ,Event mask on line 17" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " MR16 ,Event mask on line 16" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " MR15 ,Event mask on line 15" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " MR14 ,Event mask on line 14" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " MR13 ,Event mask on line 13" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " MR12 ,Event mask on line 12" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " MR11 ,Event mask on line 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " MR10 ,Event mask on line 10" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " MR9 ,Event mask on line 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " MR8 ,Event mask on line 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MR7 ,Event mask on line 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " MR6 ,Event mask on line 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " MR5 ,Event mask on line 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " MR4 ,Event mask on line 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " MR3 ,Event mask on line 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " MR2 ,Event mask on line 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " MR1 ,Event mask on line 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " MR0 ,Event mask on line 0" "Masked,Not masked"
|
|
line.long 0x08 "EXTI_RTSR,EXTI rising edge trigger selection register"
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x08 31. " TR31 ,Rising edge trigger event configuration bit of line 31" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||CPUIS("STM32F051T8")||CPUIS("STM32F038E6")||CPUIS("STM32F031E6")||CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB"))
|
|
bitfld.long 0x08 22. " TR22 ,Rising edge trigger event configuration bit of line 22" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " TR21 ,Rising edge trigger event configuration bit of line 21" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " TR20 ,Rising edge trigger event configuration bit of line 20" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 19. " TR19 ,Rising edge trigger event configuration bit of line 19" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " TR17 ,Rising edge trigger event configuration bit of line 17" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " TR16 ,Rising edge trigger event configuration bit of line 16" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " TR15 ,Rising edge trigger event configuration bit of line 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 14. " TR14 ,Rising edge trigger event configuration bit of line 14" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " TR13 ,Rising edge trigger event configuration bit of line 13" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " TR12 ,Rising edge trigger event configuration bit of line 12" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " TR11 ,Rising edge trigger event configuration bit of line 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " TR10 ,Rising edge trigger event configuration bit of line 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " TR9 ,Rising edge trigger event configuration bit of line 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " TR8 ,Rising edge trigger event configuration bit of line 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " TR7 ,Rising edge trigger event configuration bit of line 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " TR6 ,Rising edge trigger event configuration bit of line 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " TR5 ,Rising edge trigger event configuration bit of line 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TR4 ,Rising edge trigger event configuration bit of line 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TR3 ,Rising edge trigger event configuration bit of line 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " TR2 ,Rising edge trigger event configuration bit of line 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " TR1 ,Rising edge trigger event configuration bit of line 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TR0 ,Rising edge trigger event configuration bit of line 0" "Disabled,Enabled"
|
|
line.long 0x0C "EXTI_FTSR,Falling edge trigger selection register"
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x0C 31. " TR31 ,Falling edge trigger event configuration bit of line 31" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||CPUIS("STM32F051T8")||CPUIS("STM32F038E6")||CPUIS("STM32F031E6")||CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB"))
|
|
bitfld.long 0x0C 22. " TR22 ,Falling edge trigger event configuration bit of line 22" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " TR21 ,Falling edge trigger event configuration bit of line 21" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " TR20 ,Falling edge trigger event configuration bit of line 20" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 19. " TR19 ,Falling edge trigger event configuration bit of line 19" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " TR17 ,Falling edge trigger event configuration bit of line 17" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " TR16 ,Falling edge trigger event configuration bit of line 16" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " TR15 ,Falling edge trigger event configuration bit of line 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " TR14 ,Falling edge trigger event configuration bit of line 14" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " TR13 ,Falling edge trigger event configuration bit of line 13" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " TR12 ,Falling edge trigger event configuration bit of line 12" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " TR11 ,Falling edge trigger event configuration bit of line 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " TR10 ,Falling edge trigger event configuration bit of line 10" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " TR9 ,Falling edge trigger event configuration bit of line 9" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " TR8 ,Falling edge trigger event configuration bit of line 8" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " TR7 ,Falling edge trigger event configuration bit of line 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " TR6 ,Falling edge trigger event configuration bit of line 6" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " TR5 ,Falling edge trigger event configuration bit of line 5" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TR4 ,Falling edge trigger event configuration bit of line 4" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " TR3 ,Falling edge trigger event configuration bit of line 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " TR2 ,Falling edge trigger event configuration bit of line 2" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " TR1 ,Falling edge trigger event configuration bit of line 1" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " TR0 ,Falling edge trigger event configuration bit of line 0" "Disabled,Enabled"
|
|
line.long 0x10 "EXTI_SWIER,EXTI software interrupt event register"
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x10 31. " SWIER31 ,Software interrupt on line 31" "No effect,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||CPUIS("STM32F051T8")||CPUIS("STM32F038E6")||CPUIS("STM32F031E6")||CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB"))
|
|
bitfld.long 0x10 22. " SWIER22 ,Software interrupt on line 22" "No effect,Interrupt"
|
|
bitfld.long 0x10 21. " SWIER21 ,Software interrupt on line 21" "No effect,Interrupt"
|
|
bitfld.long 0x10 20. " SWIER20 ,Software interrupt on line 20" "No effect,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 19. " SWIER19 ,Software interrupt on line 19" "No effect,Interrupt"
|
|
bitfld.long 0x10 17. " SWIER17 ,Software interrupt on line 17" "No effect,Interrupt"
|
|
bitfld.long 0x10 16. " SWIER16 ,Software interrupt on line 16" "No effect,Interrupt"
|
|
bitfld.long 0x10 15. " SWIER15 ,Software interrupt on line 15" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 14. " SWIER14 ,Software interrupt on line 14" "No effect,Interrupt"
|
|
bitfld.long 0x10 13. " SWIER13 ,Software interrupt on line 13" "No effect,Interrupt"
|
|
bitfld.long 0x10 12. " SWIER12 ,Software interrupt on line 12" "No effect,Interrupt"
|
|
bitfld.long 0x10 11. " SWIER11 ,Software interrupt on line 11" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 10. " SWIER10 ,Software interrupt on line 10" "No effect,Interrupt"
|
|
bitfld.long 0x10 9. " SWIER9 ,Software interrupt on line 9" "No effect,Interrupt"
|
|
bitfld.long 0x10 8. " SWIER8 ,Software interrupt on line 8" "No effect,Interrupt"
|
|
bitfld.long 0x10 7. " SWIER7 ,Software interrupt on line 7" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 6. " SWIER6 ,Software interrupt on line 6" "No effect,Interrupt"
|
|
bitfld.long 0x10 5. " SWIER5 ,Software interrupt on line 5" "No effect,Interrupt"
|
|
bitfld.long 0x10 4. " SWIER4 ,Software interrupt on line 4" "No effect,Interrupt"
|
|
bitfld.long 0x10 3. " SWIER3 ,Software interrupt on line 3" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 2. " SWIER2 ,Software interrupt on line 2" "No effect,Interrupt"
|
|
bitfld.long 0x10 1. " SWIER1 ,Software interrupt on line 1" "No effect,Interrupt"
|
|
bitfld.long 0x10 0. " SWIER0 ,Software interrupt on line 0" "No effect,Interrupt"
|
|
line.long 0x14 "EXTI_PR,EXTI pending register"
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
eventfld.long 0x14 31. " PR31 ,Pending bit 31" "Not pending,Pending"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||CPUIS("STM32F051T8")||CPUIS("STM32F031E6")||CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB"))
|
|
eventfld.long 0x14 22. " PR22 ,Pending bit 22" "Not pending,Pending"
|
|
eventfld.long 0x14 21. " PR21 ,Pending bit 21" "Not pending,Pending"
|
|
eventfld.long 0x14 20. " PR20 ,Pending bit 20" "Not pending,Pending"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x14 19. " PR19 ,Pending bit 19" "Not pending,Pending"
|
|
eventfld.long 0x14 17. " PR17 ,Pending bit 17" "Not pending,Pending"
|
|
eventfld.long 0x14 16. " PR16 ,Pending bit 16" "Not pending,Pending"
|
|
eventfld.long 0x14 15. " PR15 ,Pending bit 15" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x14 14. " PR14 ,Pending bit 14" "Not pending,Pending"
|
|
eventfld.long 0x14 13. " PR13 ,Pending bit 13" "Not pending,Pending"
|
|
eventfld.long 0x14 12. " PR12 ,Pending bit 12" "Not pending,Pending"
|
|
eventfld.long 0x14 11. " PR11 ,Pending bit 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x14 10. " PR10 ,Pending bit 10" "Not pending,Pending"
|
|
eventfld.long 0x14 9. " PR9 ,Pending bit 9" "Not pending,Pending"
|
|
eventfld.long 0x14 8. " PR8 ,Pending bit 8" "Not pending,Pending"
|
|
eventfld.long 0x14 7. " PR7 ,Pending bit 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x14 6. " PR6 ,Pending bit 6" "Not pending,Pending"
|
|
eventfld.long 0x14 5. " PR5 ,Pending bit 5" "Not pending,Pending"
|
|
eventfld.long 0x14 4. " PR4 ,Pending bit 4" "Not pending,Pending"
|
|
eventfld.long 0x14 3. " PR3 ,Pending bit 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x14 2. " PR2 ,Pending bit 2" "Not pending,Pending"
|
|
eventfld.long 0x14 1. " PR1 ,Pending bit 1" "Not pending,Pending"
|
|
eventfld.long 0x14 0. " PR0 ,Pending bit 0" "Not pending,Pending"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC (Analog-to-digital converter)"
|
|
base ad:0x40012400
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ADC_ISR,ADC interrupt and status register"
|
|
eventfld.long 0x00 7. " AWD ,Analog watchdog flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " OVR ,ADC overrun" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " EOSEQ ,End of sequence flag" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 2. " EOC ,End of conversion flag" "Not completed,Completed"
|
|
eventfld.long 0x00 1. " EOSMP ,End of sampling flag" "Not reached,Reached"
|
|
eventfld.long 0x00 0. " ADRDY ,ADC ready" "Not ready,Ready"
|
|
if (((per.l(ad:0x40012400+0x08))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC_IER,ADC interrupt enable register"
|
|
bitfld.long 0x00 7. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EOSEQIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ADC_IER,ADC interrupt enable register"
|
|
bitfld.long 0x00 7. " AWDIE ,Analog watchdog interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EOSEQIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40012400+0x08))&0x80000017)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start conversion command" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
bitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
else
|
|
if (((per.l(ad:0x40012400+0x08))&0x01)==0x01)
|
|
if (((per.l(ad:0x40012400+0x08))&0x02)==0x02)
|
|
if (((per.l(ad:0x40012400+0x08))&0x04)==0x04)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ADC_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start conversion command" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
bitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start conversion command" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40012400+0x08))&0x04)==0x04)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start conversion command" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start conversion command" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40012400+0x08))&0x02)==0x02)
|
|
if (((per.l(ad:0x40012400+0x08))&0x04)==0x04)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ADC_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start conversion command" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
bitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ADC_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start conversion command" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
bitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40012400+0x08))&0x04)==0x04)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start conversion command" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ADC_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start conversion command" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
bitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40012400+0x08))&0x01)==0x01)
|
|
if (((per.l(ad:0x40012400+0x08))&0x04)==0x01)
|
|
if (((per.l(ad:0x40012400+0x0C))&0x01)==0x01)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ADC_CFGR1,ADC configuration register 1"
|
|
sif (cpuis("STM32F051R*")||cpuis("STM32F071RB")||cpuis("STM32F071V*")||cpuis("STM32F072R*")||cpuis("STM32F072V*")||cpuis("STM32F030R8")||cpuis("STM32F051K*")||cpuis("STM32F051C*")||cpuis("STM32F098RC*")||cpuis("STM32F091R?*")||cpuis("STM32F091V?")||cpuis("STM32F078R?*")||cpuis("STM32F078V?")||cpuis("STM32F058R?*")||CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB")||CPUIS("STM32F031E6")||CPUIS("STM32F038E6")||CPUIS("STM32F051T8")||CPUIS("STM32F058T8"))
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F042F*")||cpuis("STM32F031F*")||cpuis("STM32F030F4")||cpuis("STM32F050F*")||cpuis("STM32F038G*"))||cpuis("STM32F038E*")
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F038F*"))
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " AWDEN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWDSGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " AUTOFF ,Auto-off mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WAIT ,Wait conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "P,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--8. " EXTSEL ,External trigger selection" "TRG0,TRG1,TRG2,TRG3,TRG4,TRG5,TRG6,TRG7"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
bitfld.long 0x00 2. " SCANDIR ,Scan sequence direction" "Upward,Backward"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ADC_CFGR1,ADC configuration register 1"
|
|
sif (cpuis("STM32F051R*")||cpuis("STM32F071RB")||cpuis("STM32F071V*")||cpuis("STM32F072R*")||cpuis("STM32F072V*")||cpuis("STM32F030R8")||cpuis("STM32F051K*")||cpuis("STM32F051C*")||cpuis("STM32F098RC*")||cpuis("STM32F091R?*")||cpuis("STM32F091V?")||cpuis("STM32F078R?*")||cpuis("STM32F078V?")||cpuis("STM32F058R?*")||CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB")||CPUIS("STM32F031E6")||CPUIS("STM32F038E6")||CPUIS("STM32F051T8")||CPUIS("STM32F058T8"))
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F042F*")||cpuis("STM32F031F*")||cpuis("STM32F030F4")||cpuis("STM32F050F*")||cpuis("STM32F038G*"))||cpuis("STM32F038E*")
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F038F*"))
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " AWDEN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWDSGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " AUTOFF ,Auto-off mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WAIT ,Wait conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "P,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--8. " EXTSEL ,External trigger selection" "TRG0,TRG1,TRG2,TRG3,TRG4,TRG5,TRG6,TRG7"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
bitfld.long 0x00 2. " SCANDIR ,Scan sequence direction" "Upward,Backward"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40012400+0x0C))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC_CFGR1,ADC configuration register 1"
|
|
sif (cpuis("STM32F051R*")||cpuis("STM32F071RB")||cpuis("STM32F071V*")||cpuis("STM32F072R*")||cpuis("STM32F072V*")||cpuis("STM32F030R8")||cpuis("STM32F051K*")||cpuis("STM32F051C*")||cpuis("STM32F098RC*")||cpuis("STM32F091R?*")||cpuis("STM32F091V?")||cpuis("STM32F078R?*")||cpuis("STM32F078V?")||cpuis("STM32F058R?*")||CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB")||CPUIS("STM32F031E6")||CPUIS("STM32F038E6")||CPUIS("STM32F051T8")||CPUIS("STM32F058T8"))
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F042F*")||cpuis("STM32F031F*")||cpuis("STM32F030F4")||cpuis("STM32F050F*")||cpuis("STM32F038G*"))||cpuis("STM32F038E*")
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F038F*"))
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " AWDEN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWDSGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " AUTOFF ,Auto-off mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WAIT ,Wait conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "P,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--8. " EXTSEL ,External trigger selection" "TRG0,TRG1,TRG2,TRG3,TRG4,TRG5,TRG6,TRG7"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
bitfld.long 0x00 2. " SCANDIR ,Scan sequence direction" "Upward,Backward"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC_CFGR1,ADC configuration register 1"
|
|
sif (cpuis("STM32F051R*")||cpuis("STM32F071RB")||cpuis("STM32F071V*")||cpuis("STM32F072R*")||cpuis("STM32F072V*")||cpuis("STM32F030R8")||cpuis("STM32F051K*")||cpuis("STM32F051C*")||cpuis("STM32F098RC*")||cpuis("STM32F091R?*")||cpuis("STM32F091V?")||cpuis("STM32F078R?*")||cpuis("STM32F078V?")||cpuis("STM32F058R?*")||CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB")||CPUIS("STM32F031E6")||CPUIS("STM32F038E6")||CPUIS("STM32F051T8")||CPUIS("STM32F058T8"))
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F042F*")||cpuis("STM32F031F*")||cpuis("STM32F030F4")||cpuis("STM32F050F*")||cpuis("STM32F038G*"))||cpuis("STM32F038E*")
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F038F*"))
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " AWDEN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWDSGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " AUTOFF ,Auto-off mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WAIT ,Wait conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "P,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--8. " EXTSEL ,External trigger selection" "TRG0,TRG1,TRG2,TRG3,TRG4,TRG5,TRG6,TRG7"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
bitfld.long 0x00 2. " SCANDIR ,Scan sequence direction" "Upward,Backward"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40012400+0x08))&0x04)==0x01)
|
|
if (((per.l(ad:0x40012400+0x0C))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC_CFGR1,ADC configuration register 1"
|
|
sif (cpuis("STM32F051R*")||cpuis("STM32F071RB")||cpuis("STM32F071V*")||cpuis("STM32F072R*")||cpuis("STM32F072V*")||cpuis("STM32F030R8")||cpuis("STM32F051K*")||cpuis("STM32F051C*")||cpuis("STM32F098RC*")||cpuis("STM32F091R?*")||cpuis("STM32F091V?")||cpuis("STM32F078R?*")||cpuis("STM32F078V?")||cpuis("STM32F058R?*")||CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB")||CPUIS("STM32F031E6")||CPUIS("STM32F038E6")||CPUIS("STM32F051T8")||CPUIS("STM32F058T8"))
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F042F*")||cpuis("STM32F031F*")||cpuis("STM32F030F4")||cpuis("STM32F050F*")||cpuis("STM32F038G*"))||cpuis("STM32F038E*")
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F038F*"))
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,?..."
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,?..."
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 23. " AWDEN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWDSGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
rbitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 15. " AUTOFF ,Auto-off mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " WAIT ,Wait conversion mode" "Off,On"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "P,Overwritten"
|
|
rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
rbitfld.long 0x00 6.--8. " EXTSEL ,External trigger selection" "TRG0,TRG1,TRG2,TRG3,TRG4,TRG5,TRG6,TRG7"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
rbitfld.long 0x00 2. " SCANDIR ,Scan sequence direction" "Upward,Backward"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC_CFGR1,ADC configuration register 1"
|
|
sif (cpuis("STM32F051R*")||cpuis("STM32F071RB")||cpuis("STM32F071V*")||cpuis("STM32F072R*")||cpuis("STM32F072V*")||cpuis("STM32F030R8")||cpuis("STM32F051K*")||cpuis("STM32F051C*")||cpuis("STM32F098RC*")||cpuis("STM32F091R?*")||cpuis("STM32F091V?")||cpuis("STM32F078R?*")||cpuis("STM32F078V?")||cpuis("STM32F058R?*")||CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB"))
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F042F*")||cpuis("STM32F031F*")||cpuis("STM32F030F4")||cpuis("STM32F050F*")||cpuis("STM32F038G*"))||cpuis("STM32F038E*")
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F038F*"))
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,?..."
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,?..."
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 23. " AWDEN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWDSGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
rbitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 15. " AUTOFF ,Auto-off mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " WAIT ,Wait conversion mode" "Off,On"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "P,Overwritten"
|
|
rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
rbitfld.long 0x00 6.--8. " EXTSEL ,External trigger selection" "TRG0,TRG1,TRG2,TRG3,TRG4,TRG5,TRG6,TRG7"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
rbitfld.long 0x00 2. " SCANDIR ,Scan sequence direction" "Upward,Backward"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40012400+0x0C))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC_CFGR1,ADC configuration register 1"
|
|
sif (cpuis("STM32F051R*")||cpuis("STM32F071RB")||cpuis("STM32F071V*")||cpuis("STM32F072R*")||cpuis("STM32F072V*")||cpuis("STM32F030R8")||cpuis("STM32F051K*")||cpuis("STM32F051C*")||cpuis("STM32F098RC*")||cpuis("STM32F091R?*")||cpuis("STM32F091V?")||cpuis("STM32F078R?*")||cpuis("STM32F078V?")||cpuis("STM32F058R?*")||CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB")||CPUIS("STM32F031E6")||CPUIS("STM32F038E6")||CPUIS("STM32F051T8")||CPUIS("STM32F058T8"))
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F042F*")||cpuis("STM32F031F*")||cpuis("STM32F030F4")||cpuis("STM32F050F*")||cpuis("STM32F038G*"))||cpuis("STM32F038E*")
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F038F*"))
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " AWDEN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWDSGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " AUTOFF ,Auto-off mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WAIT ,Wait conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "P,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--8. " EXTSEL ,External trigger selection" "TRG0,TRG1,TRG2,TRG3,TRG4,TRG5,TRG6,TRG7"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
bitfld.long 0x00 2. " SCANDIR ,Scan sequence direction" "Upward,Backward"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC_CFGR1,ADC configuration register 1"
|
|
sif (cpuis("STM32F051R*")||cpuis("STM32F071RB")||cpuis("STM32F071V*")||cpuis("STM32F072R*")||cpuis("STM32F072V*")||cpuis("STM32F030R8")||cpuis("STM32F051K*")||cpuis("STM32F051C*")||cpuis("STM32F098RC*")||cpuis("STM32F091R?*")||cpuis("STM32F091V?")||cpuis("STM32F078R?*")||cpuis("STM32F078V?")||cpuis("STM32F058R?*")||CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB")||CPUIS("STM32F031E6")||CPUIS("STM32F038E6")||CPUIS("STM32F051T8")||CPUIS("STM32F058T8"))
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F042F*")||cpuis("STM32F031F*")||cpuis("STM32F030F4")||cpuis("STM32F050F*")||cpuis("STM32F038G*"))||cpuis("STM32F038E*")
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,?..."
|
|
textline " "
|
|
elif (cpuis("STM32F038F*"))
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " AWDEN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWDSGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " AUTOFF ,Auto-off mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WAIT ,Wait conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "P,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--8. " EXTSEL ,External trigger selection" "TRG0,TRG1,TRG2,TRG3,TRG4,TRG5,TRG6,TRG7"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
bitfld.long 0x00 2. " SCANDIR ,Scan sequence direction" "Upward,Backward"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40012400+0x08))&0x80000017)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ADC_CFGR2,ADC configuration register 2"
|
|
bitfld.long 0x00 30.--31. " CKMODE ,ADC clock mode" "ADCCLK,PCLK/2,PCLK/4,?..."
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ADC_CFGR2,ADC configuration register 2"
|
|
bitfld.long 0x00 30.--31. " CKMODE ,ADC clock mode" "ADCCLK,PCLK/2,PCLK/4,?..."
|
|
endif
|
|
if (((per.l(ad:0x40012400+0x08))&0x04)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ADC_SMPR,ADC sampling time register"
|
|
bitfld.long 0x00 0.--2. " SMP ,Sampling time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5 cycles"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ADC_TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x00 16.--27. 1. " HT ,Analog watchdog higher threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " LT ,Analog watchdog lower threshold"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ADC_CHSELR,ADC channel selection register"
|
|
sif (cpuis("STM32F051R*")||cpuis("STM32F071RB")||cpuis("STM32F071V*")||cpuis("STM32F072R*")||cpuis("STM32F072V*")||cpuis("STM32F030R8")||cpuis("STM32F051K*")||cpuis("STM32F051C*")||cpuis("STM32F098RC*")||cpuis("STM32F091R?*")||cpuis("STM32F091V?")||cpuis("STM32F078R?*")||cpuis("STM32F078V?")||cpuis("STM32F058R?*")||CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB")||CPUIS("STM32F031E6")||CPUIS("STM32F038E6")||CPUIS("STM32F051T8")||CPUIS("STM32F058T8"))
|
|
sif !CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.long 0x00 18. " CHSEL18 ,Channel-18 selection" "Not selected,Selected"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " CHSEL17 ,Channel-17 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " CHSEL16 ,Channel-16 selection" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHSEL15 ,Channel-15 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " CHSEL14 ,Channel-14 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " CHSEL13 ,Channel-13 selection" "Not selected,Selected"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042F*"))&&(!cpuis("STM32F031F*"))&&(!cpuis("STM32F030F4"))&&(!cpuis("STM32F050F*"))&&(!cpuis("STM32F038F6"))
|
|
bitfld.long 0x00 12. " CHSEL12 ,Channel-12 selection" "Not selected,Selected"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F038F6"))
|
|
bitfld.long 0x00 11. " CHSEL11 ,Channel-11 selection" "Not selected,Selected"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " CHSEL10 ,Channel-10 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " CHSEL9 ,Channel-9 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " CHSEL8 ,Channel-8 selection" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHSEL7 ,Channel-7 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " CHSEL6 ,Channel-6 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " CHSEL5 ,Channel-5 selection" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CHSEL4 ,Channel-4 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " CHSEL3 ,Channel-3 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " CHSEL2 ,Channel-2 selection" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CHSEL1 ,Channel-1 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " CHSEL0 ,Channel-0 selection" "Not selected,Selected"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ADC_SMPR,ADC sampling time register"
|
|
bitfld.long 0x00 0.--2. " SMP ,Sampling time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5 cycles"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ADC_TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x00 16.--27. 1. " HT ,Analog watchdog higher threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " LT ,Analog watchdog lower threshold"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "ADC_CHSELR,ADC channel selection register"
|
|
sif (cpuis("STM32F051R*")||cpuis("STM32F071RB")||cpuis("STM32F071V*")||cpuis("STM32F072R*")||cpuis("STM32F072V*")||cpuis("STM32F030R8")||cpuis("STM32F051K*")||cpuis("STM32F051C*")||cpuis("STM32F098RC*")||cpuis("STM32F091R?*")||cpuis("STM32F091V?")||cpuis("STM32F078R?*")||cpuis("STM32F078V?")||cpuis("STM32F058R?*")||CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB")||CPUIS("STM32F031E6")||CPUIS("STM32F038E6")||CPUIS("STM32F051T8")||CPUIS("STM32F058T8"))
|
|
sif !CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.long 0x00 18. " CHSEL18 ,Channel-18 selection" "Not selected,Selected"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " CHSEL17 ,Channel-17 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 16. " CHSEL16 ,Channel-16 selection" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHSEL15 ,Channel-15 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " CHSEL14 ,Channel-14 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " CHSEL13 ,Channel-13 selection" "Not selected,Selected"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F042F*"))&&(!cpuis("STM32F031F*"))&&(!cpuis("STM32F030F4"))&&(!cpuis("STM32F050F*"))&&(!cpuis("STM32F038F6"))
|
|
bitfld.long 0x00 12. " CHSEL12 ,Channel-12 selection" "Not selected,Selected"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F038F6"))
|
|
bitfld.long 0x00 11. " CHSEL11 ,Channel-11 selection" "Not selected,Selected"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " CHSEL10 ,Channel-10 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " CHSEL9 ,Channel-9 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " CHSEL8 ,Channel-8 selection" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHSEL7 ,Channel-7 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " CHSEL6 ,Channel-6 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " CHSEL5 ,Channel-5 selection" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CHSEL4 ,Channel-4 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 3. " CHSEL3 ,Channel-3 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " CHSEL2 ,Channel-2 selection" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CHSEL1 ,Channel-1 selection" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " CHSEL0 ,Channel-0 selection" "Not selected,Selected"
|
|
endif
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "ADC_DR,ADC data register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Converted data"
|
|
if (((per.l(ad:0x40012400+0x08))&0x04)==0x00)
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "ADC_CCR,ADC common configuration register"
|
|
sif !CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " VREFEN ,Temperature sensor and VREFINT enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "ADC_CCR,ADC common configuration register"
|
|
sif !CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " VREFEN ,Temperature sensor and VREFINT enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("STM32F071*"))||(cpuis("STM32F072*")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*"))
|
|
tree "DAC (Digital-to-analog converter)"
|
|
base ad:0x40007400
|
|
width 13.
|
|
if ((per.l(ad:0x40007400)&0x40004)==0x40004)
|
|
if ((per.l(ad:0x40007400)&0xC000C0)==(0xC00C0||0xC0080||0x800C0||0x80080))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0xC000C0)==(0xC0040||0x80040))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask/amplitude selector" "0,[1:0],[2:0],[3:0],[4:0],[5:0],[6:0],[7:0],[8:0],[9:0],[10:0],[11:0],[11:0],[11:0],[11:0],[11:0]"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0xC000C0)==(0xC0000||0x80000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0xC000C0)==(0x400C0||0x40080))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask/amplitude selector" "0,[1:0],[2:0],[3:0],[4:0],[5:0],[6:0],[7:0],[8:0],[9:0],[10:0],[11:0],[11:0],[11:0],[11:0],[11:0]"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0xC000C0)==(0x40040))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask/amplitude selector" "0,[1:0],[2:0],[3:0],[4:0],[5:0],[6:0],[7:0],[8:0],[9:0],[10:0],[11:0],[11:0],[11:0],[11:0],[11:0]"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask/amplitude selector" "0,[1:0],[2:0],[3:0],[4:0],[5:0],[6:0],[7:0],[8:0],[9:0],[10:0],[11:0],[11:0],[11:0],[11:0],[11:0]"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0xC000C0)==(0x40000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask/amplitude selector" "0,[1:0],[2:0],[3:0],[4:0],[5:0],[6:0],[7:0],[8:0],[9:0],[10:0],[11:0],[11:0],[11:0],[11:0],[11:0]"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0xC000C0)==(0x000C0||0x00080))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0xC000C0)==(0x00040))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask/amplitude selector" "0,[1:0],[2:0],[3:0],[4:0],[5:0],[6:0],[7:0],[8:0],[9:0],[10:0],[11:0],[11:0],[11:0],[11:0],[11:0]"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40007400)&0x40004)==0x40000)
|
|
if ((per.l(ad:0x40007400)&0xC00000)==(0xC0000||0x80000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0xC00000)==(0x40000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,DAC channel 2 mask/amplitude selector" "0,[1:0],[2:0],[3:0],[4:0],[5:0],[6:0],[7:0],[8:0],[9:0],[10:0],[11:0],[11:0],[11:0],[11:0],[11:0]"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,DAC channel2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,DAC channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
endif
|
|
elif ((per.l(ad:0x40007400)&0x40004)==0x00004)
|
|
if ((per.l(ad:0x40007400)&0xC0)==(0xC0||0x80))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask/amplitude selector" "1,3,7,15,31,63,127,255,511,1023,2047,4095,4095,4095,4095,4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0xC0)==(0x40))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel 1 mask/amplitude selector" "0,[1:0],[2:0],[3:0],[4:0],[5:0],[6:0],[7:0],[8:0],[9:0],[10:0],[11:0],[11:0],[11:0],[11:0],[11:0]"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,Timer 4 TRGO,EXTI line 9,Software trigger"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC Control Register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,DAC channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,DAC channel 2 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 18. " TEN2 ,DAC channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,DAC channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,DAC channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.l(ad:0x40007400)&0x40004)==0x40004)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DAC_SWTRIGR,DAC Software Trigger Register"
|
|
bitfld.long 0x00 1. " SWTRIG2 ,DAC channel 2 software trigger" "Disable,Enable"
|
|
bitfld.long 0x00 0. " SWTRIG1 ,DAC channel 1 software trigger" "Disable,Enable"
|
|
elif ((per.l(ad:0x40007400)&0x40004)==0x40000)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DAC_SWTRIGR,DAC Software Trigger Register"
|
|
bitfld.long 0x00 1. " SWTRIG2 ,DAC channel 2 software trigger" "Disable,Enable"
|
|
elif ((per.l(ad:0x40007400)&0x40004)==0x00004)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DAC_SWTRIGR,DAC Software Trigger Register"
|
|
bitfld.long 0x00 0. " SWTRIG1 ,DAC channel 1 software trigger" "Disable,Enable"
|
|
else
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "DAC_SWTRIGR,DAC Software Trigger Register"
|
|
endif
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "DAC_DHR12R1,DAC Channel 1 12-bit Right-aligned Data Holding Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DACC1DHR ,DAC channel1 12-bit right aligned data"
|
|
line.long 0x04 "DAC_DHR12L1,DAC Channel 1 12-bit Left Aligned Data Holding Register"
|
|
hexmask.long.word 0x04 4.--15. 1. " DACC1DHR ,DAC channel1 12-bit left aligned data"
|
|
line.long 0x08 "DAC_DHR8R1,DAC Channel 1 8-bit Right Aligned Data Holding Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DACC1DHR ,DAC channel1 8-bit right aligned data"
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "DAC_DHR12R2,DAC Channel 2 12-bit Right-aligned Data Holding Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DACC1DHR ,DAC channel2 12-bit right aligned data"
|
|
line.long 0x04 "DAC_DHR12L2,DAC Channel 2 12-bit Left Aligned Data Holding Register"
|
|
hexmask.long.word 0x04 4.--15. 1. " DACC1DHR ,DAC channel2 12-bit left aligned data"
|
|
line.long 0x08 "DAC_DHR8R2,DAC Channel 2 8-bit Right Aligned Data Holding Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DACC1DHR ,DAC channel2 8-bit right aligned data"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "DAC_DHR12RD,Dual DAC 12-bit right-aligned Data Holding Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " DACC2DHR ,DAC channel 2 12-bit right-aligned data"
|
|
hexmask.long.word 0x00 0.--11. 1. " DACC1DHR ,DAC channel 1 12-bit right-aligned data"
|
|
line.long 0x04 "DAC_DHR12LD,Dual DAC 12-bit left-aligned Data Holding Register"
|
|
hexmask.long.word 0x04 20.--31. 1. " DACC2DHR ,DAC channel 2 12-bit left-aligned data"
|
|
hexmask.long.word 0x04 4.--15. 1. " DACC1DHR ,DAC channel 1 12-bit left-aligned data"
|
|
line.long 0x08 "DAC_DHR8RD,Dual DAC 8-bit right-aligned Data Holding Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DACC2DHR ,DAC channel 2 8-bit right-aligned data"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DACC1DHR ,DAC channel 1 8-bit right-aligned data"
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "DAC_DOR1,DAC Channel1 Data Output Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DACC1DOR ,DAC channel 1 data output"
|
|
line.long 0x04 "DAC_DOR2,DAC Channel2 Data Output Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DACC2DOR ,DAC channel 2 data output"
|
|
if ((per.l(ad:0x40007400)&0x20042004)==0x20042004)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DAC_SR,DAC Status Register"
|
|
eventfld.long 0x00 29. " DMAUDR2 ,DAC channel 2 DMA underrun flag" "No error,Error"
|
|
eventfld.long 0x00 13. " DMAUDR1 ,DAC channel 1 DMA underrun flag" "No error,Error"
|
|
elif ((per.l(ad:0x40007400)&0x20040000)==0x20040000)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DAC_SR,DAC Status Register"
|
|
eventfld.long 0x00 29. " DMAUDR2 ,DAC channel 2 DMA underrun flag" "No error,Error"
|
|
elif ((per.l(ad:0x40007400)&0x00002004)==0x00002004)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DAC_SR,DAC Status Register"
|
|
eventfld.long 0x00 13. " DMAUDR1 ,DAC channel 1 DMA underrun flag" "No error,Error"
|
|
else
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "DAC_SR,DAC Status Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
elif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8"||cpuis("STM32F058?8")||cpuis("STM32F051T8"))
|
|
tree "DAC (Digital-to-analog converter)"
|
|
base ad:0x40007400
|
|
width 13.
|
|
if ((per.l(ad:0x40007400)&0x04)==0x04)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC Control Register"
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F058T8")||cpuis("STM32F051T8"))
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 unmask/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC channel1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel1 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 15 TRGO,Timer 2 TRGO,,EXTI line9,Software"
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC Control Register"
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F058T8")||cpuis("STM32F051T8"))
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC channel1 unmask/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel1 enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DAC_SWTRIGR,DAC Software Trigger Register"
|
|
bitfld.long 0x00 0. " SWTRIG1 ,DAC channel1 software trigger" "Disable,Enable"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "DAC_DHR12R1,DAC Channel1 12-bit Right-Aligned Data Holding Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DACC1DHR ,DAC channel1 12-bit right aligned data"
|
|
line.long 0x04 "DAC_DHR12L1,DAC Channel1 12-bit Left Aligned Data Holding Register"
|
|
hexmask.long.word 0x04 4.--15. 1. " DACC1DHR ,DAC channel1 12-bit left aligned data"
|
|
line.long 0x08 "DAC_DHR8R1,DAC Channel1 8-bit Right Aligned Data Holding Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " DACC1DHR ,DAC channel1 8-bit right aligned data"
|
|
sif (!cpuis("STM32F058?8")&&!cpuis("STM32F051T8"))
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "DAC_DHR12RD,Dual DAC 12-bit Right-Aligned Data Holding Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DACC2DHR ,DAC channel 1 12-bit right-aligned data"
|
|
line.long 0x04 "DAC_DHR12LD,Dual DAC 12-bit Left-Aligned Data Holding Register"
|
|
hexmask.long.word 0x04 4.--15. 1. " DACC1DHR ,DAC channel 1 12-bit left-aligned data"
|
|
line.long 0x08 "DAC_DHR8RD,Dual DAC 8-bit Right-Aligned Data Holding Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DACC1DHR ,DAC channel 1 8-bit right-aligned data"
|
|
endif
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DAC_DOR1,DAC Channel1 Data Output Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DACC1DOR ,DAC channel1 data output"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DAC_SR,DAC Status Register"
|
|
eventfld.long 0x00 13. " DMAUDR1 ,DAC channel1 DMA underrun flag" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
elif (cpuis("STM32F050G6"))
|
|
tree "DAC (Digital-to-analog converter)"
|
|
base ad:0x40007400
|
|
width 13.
|
|
if ((per.l(ad:0x40007400)&0x04)==0x04)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC control register"
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC channel 1 Trigger selection" "Timer 6 TRGO,,,,,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0x04)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC_CR,DAC control register"
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC channel1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC channel1 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,DAC channel 1 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,DAC channel 1 enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DAC_SWTRIGR,DAC Software Trigger Register"
|
|
bitfld.long 0x00 0. " SWTRIG1 ,DAC channel 1 software trigger" "Disable,Enable"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "DAC_DHR12R1,DAC channel 1 12-bit Right-aligned Data Holding Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DACC1DHR ,DAC channel1 12-bit Right aligned data"
|
|
line.long 0x04 "DAC_DHR12L1,DAC channel 1 12-bit Left aligned Data Holding Register"
|
|
hexmask.long.word 0x04 4.--15. 1. " DACC1DHR ,DAC channel1 12-bit Left aligned data"
|
|
line.long 0x08 "DAC_DHR8R1,DAC channel 1 8-bit Right aligned Data Holding Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DACC1DHR ,DAC channel1 8-bit Right aligned data"
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "DAC_DHR12R2,DAC channel 2 12-bit Right-aligned Data Holding Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DACC1DHR ,DAC channel2 12-bit Right aligned data"
|
|
line.long 0x04 "DAC_DHR12L2,DAC channel 2 12-bit Left aligned Data Holding Register"
|
|
hexmask.long.word 0x04 4.--15. 1. " DACC1DHR ,DAC channel2 12-bit Left aligned data"
|
|
line.long 0x08 "DAC_DHR8R2,DAC channel 2 8-bit Right aligned Data Holding Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DACC1DHR ,DAC channel2 8-bit Right aligned data"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DAC_DHR12RD,Dual DAC 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x00 16.--27. 1. " DACC2DHR ,DAC channel 2 12-bit right-aligned data"
|
|
hexmask.long.word 0x00 0.--11. 1. " DACC1DHR ,DAC channel 1 12-bit right-aligned data"
|
|
line.long 0x04 "DAC_DHR12LD,Dual DAC 12-bit left-aligned data holding register"
|
|
hexmask.long.word 0x04 20.--31. 1. " DACC2DHR ,DAC channel 2 12-bit left-aligned data"
|
|
hexmask.long.word 0x04 4.--15. 1. " DACC1DHR ,DAC channel 1 12-bit left-aligned data"
|
|
line.long 0x08 "DAC_DHR8RD,Dual DAC 8-bit right-aligned data holding register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DACC2DHR ,DAC channel 2 8-bit right-aligned data"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DACC1DHR ,DAC channel 1 8-bit right-aligned data"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DAC_DOR1,DAC channel1 Data Output Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DACC1DOR ,DAC channel 1 data output"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "DAC_DOR2,DAC channel2 Data Output Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DACC2DOR ,DAC channel 2 data output"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DAC_SR,DAC status register"
|
|
eventfld.long 0x00 13. " DMAUDR1 ,DAC channel 1 DMA underrun flag" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8"||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*"))||cpuis("STM32F051T8")
|
|
tree "COMP (Comparator)"
|
|
base ad:0x40010000
|
|
width 10.
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "COMP_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " COMP2LOCK ,Comparator 2 lock" "Read-write,Read-only"
|
|
textline " "
|
|
sif (cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||CPUIS("STM32F051T8"))
|
|
rbitfld.long 0x00 30. " COMP2OUT ,Comparator 2 output" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 30. " COMP2OUT ,Comparator 2 output" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28.--29. " COMP2HYST ,Comparator 2 hysteresis" "No,Low,Medium,High"
|
|
bitfld.long 0x00 27. " COMP2POL ,Comparator 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 24.--26. " COMP2OUTSEL ,Comparator 2 output selection" "No selection,Timer 1 break input,Timer 1 Input capture 1,Timer 1 OCrefclear input,Timer 2 input capture 4,Timer 2 OCrefclear input,Timer 3 input capture 1,Timer 3 OCrefclear input"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WNDWEN ,Window mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " COMP2INSEL ,Comparator 2 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,COMP2_INM4,COMP2_INM5,COMP2_INM6,?..."
|
|
bitfld.long 0x00 18.--19. " COMP2MODE ,Comparator 2 mode" "High speed,Medium speed,Low power,Ultra-low power"
|
|
textline " "
|
|
bitfld.long 0x00 16. " COMP2EN ,Comparator 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " COMP1LOCK ,Comparator 1 lock" "Read-write,Read-only"
|
|
textline " "
|
|
sif (cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||CPUIS("STM32F051T8"))
|
|
rbitfld.long 0x00 14. " COMP1OUT ,Comparator 1 output" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 14. " COMP1OUT ,Comparator 1 output" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " COMP1HYST ,Comparator 1 hysteresis" "No,Low,Medium,High"
|
|
bitfld.long 0x00 11. " COMP1POL ,Comparator 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8.--10. " COMP1OUTSEL ,Comparator 1 output selection" "No selection,Timer 1 break input,Timer 1 Input capture 1,Timer 1 OCrefclear input,Timer 2 input capture 4,Timer 2 OCrefclear input,Timer 3 input capture 1,Timer 3 OCrefclear input"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " COMP1INSEL ,Comparator 1 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,COMP1_INM4,COMP1_INM5,COMP1_INM6,?..."
|
|
bitfld.long 0x00 2.--3. " COMP1MODE ,Comparator 1 mode" "Ultra-low power,Low power,Medium speed,High speed"
|
|
bitfld.long 0x00 1. " COMP1SW1 ,This bit closes a switch between comparator 1 non-inverting input on PA0 and PA4 (DAC) I/O." "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " COMP1EN ,Comparator 1 enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F030?4"))||(cpuis("STM32F030?6"))||(cpuis("STM32F030?8")||(cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F058T8")||cpuis("STM32F051T8")||cpuis("STM32F038E6")||cpuis("STM32F031E6")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB"))
|
|
tree "ACT (Advanced-control timers)"
|
|
tree "TIM1"
|
|
base ad:0x40012C00
|
|
width 15.
|
|
if (((per.l(ad:0x40012C00))&0x01)==0x01)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM1_CR1,Control Register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
rbitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM1_CR1,Control Register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
if (((per.w(ad:0x40012C00+0x044))&0x300)!=0x00)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM1_CR2,Control Register 2"
|
|
rbitfld.word 0x00 14. " OIS4 ,Output idle state 4 (OC4 output)" "0,1"
|
|
rbitfld.word 0x00 13. " OIS3N ,Output idle state 3 (OC3N output)" "0,1"
|
|
rbitfld.word 0x00 12. " OIS3 ,Output idle state 3 (OC3 output)" "0,1"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " OIS2N ,Output idle state 2 (OC2N output)" "0,1"
|
|
rbitfld.word 0x00 10. " OIS2 ,Output idle state 2 (OC2 output)" "0,1"
|
|
rbitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1N output)" "0,1"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "CC1 event,Update event"
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG,COMG/rising edge TRGI"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM1_CR2,Control Register 2"
|
|
bitfld.word 0x00 14. " OIS4 ,Output idle state 4 (OC4 output)" "0,1"
|
|
bitfld.word 0x00 13. " OIS3N ,Output idle state 3 (OC3N output)" "0,1"
|
|
bitfld.word 0x00 12. " OIS3 ,Output idle state 3 (OC3 output)" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OIS2N ,Output idle state 2 (OC2N output)" "0,1"
|
|
bitfld.word 0x00 10. " OIS2 ,Output idle state 2 (OC2 output)" "0,1"
|
|
bitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1N output)" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "CC1 event,Update event"
|
|
bitfld.word 0x00 2. " CCUS ,Capture/compare control update selection" "COMG,COMG/rising edge TRGI"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/compare preloaded control" "Not preloaded,Preloaded"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "TIM1_SMCR,Slave Mode Control Register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/Slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM1_DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM1_SR,Status Register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " BIF ,Break interrupt flag" "No break,Break"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "No COM event,COM interrupt"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM1_EGR,Event Generation Register"
|
|
bitfld.word 0x00 7. " BG ,Break generation" "No action,Enable"
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Enable"
|
|
bitfld.word 0x00 5. " COMG ,Trigger generation" "No action,Enable"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 generation input/output" "No action/No action,Capture 4/compare 4"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "Not generate,Generate"
|
|
textline " "
|
|
if (((per.w(ad:0x40012C00+0x18))&0x303)==0x00)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x10)==0x10)
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x10)==0x10)
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0x40012C00+0x18))&0x303)==0x300)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x10)==0x10)
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x10)==0x10)
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0x40012C00+0x18))&0x300)==0x03)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x10)==0x10)
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x10)==0x10)
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM1_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.w(ad:0x40012C00+0x1C))&0x303)==0x00)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x0100)==0x0100)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1000)==0x1000)
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1000)==0x1000)
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x303)==0x300)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x0100)==0x0100)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1000)==0x1000)
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1000)==0x1000)
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x303)==0x03)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x0100)==0x0100)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1000)==0x1000)
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1000)==0x1000)
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)==0x300)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active/,PWM2/Inactive/"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x0100)==0x0100)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1000)==0x1000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1000)==0x1000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM1_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
width 11.
|
|
textline " "
|
|
if (((per.w((ad:0x40012C00+0x44)))&0x300)>0x100)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM1_CCER,Capture/Compare Enable Register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity input/output" "0/High,1/Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity input/output" "0/High,1/Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "0/High,1/Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "0/High,1/Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM1_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity input/output" "0/High,1/Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 output polarity" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity input/output" "0/High,1/Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "0/High,1/Low"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "0/High,1/Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
endif
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM1_CNT,TIM1 Counter"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM1_PSC,TIM1 Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM1_ARR,TIM1 Auto-Reload Register"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "TIM1_CCR1,TIM1 Capture/Compare Register 1"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "TIM1_CCR2,TIM1 Capture/Compare Register 2"
|
|
group.word 0x3C++0x01
|
|
line.word 0x00 "TIM1_CCR3,TIM1 Capture/compare Register 3"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "TIM1_CCR4,TIM1 Capture/compare Register 4"
|
|
if (((per.w(ad:0x40012C00+0x044))&0x300)==0x200)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM1_BDTR,TIM1 Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " OSSR ,Off-state selection for run mode" "OC/OCN disabled,OC/OCN enabled"
|
|
rbitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode" "OC/OCN disabled,OC/OCN forced IDLE"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "OFF,Level1,Level2,Level3"
|
|
hexmask.word.byte 0x00 0.--7. 0x01 " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40012C00+0x044))&0x300)==0x100)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM1_BDTR,TIM1 Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " BKP ,Break polarity" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for Run mode" "OC/OCN disabled,OC/OCN enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode" "OC/OCN disabled,OC/OCN forced IDLE"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "OFF,Level1,Level2,Level3"
|
|
hexmask.word.byte 0x00 0.--7. 0x01 " DTG ,Dead-time generator setup"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM1_BDTR,TIM1 Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for run mode" "OC/OCN disabled,OC/OCN enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode" "OC/OCN disabled,OC/OCN forced IDLE"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "OFF,Level1,Level2,Level3"
|
|
hexmask.word.byte 0x00 0.--7. 0x01 " DTG ,Dead-time generator setup"
|
|
endif
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "TIM1_DCR,DMA Control Register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM1_CR1,TIM1_CR2,TIM1_SMCR,TIM1_DIER,TIM1_SR,TIM1_EGR,TIM1_CCMR1,TIM1_CCMR2,TIM1_CCER,TIM1_CNT,TIM1_PSC,TIM1_ARR,TIM1_RCR,TIM1_CCR1,TIM1_CCR2,TIM1_CCR3,TIM1_CCR4,TIM1_BDTR,TIM1_DCR,TIM1_DMAR,...,?..."
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "TIM1_DMAR,DMA Address For Burst Mode"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree "ACT (Advanced-control timers)"
|
|
tree "TIM1"
|
|
base ad:0x40012C00
|
|
width 12.
|
|
if (((per.w(ad:0x40012C00))&0x60)>0)||((((per.w(ad:0x40012C00+0x08))&0x7)>=0x1)&&(((per.w(ad:0x40012C00+0x08))&0x7)<=0x3))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM1_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM1_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40012C00+0x44))&0x300)!=0x0)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM1_CR2,Control register 2"
|
|
rbitfld.word 0x00 14. " OIS4 ,OC4 output" "0,1"
|
|
rbitfld.word 0x00 13. " OIS3N ,OC3N output" "0,1"
|
|
rbitfld.word 0x00 12. " OIS3 ,OC3 output" "0,1"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " OIS2N ,OC2N output" "0,1"
|
|
rbitfld.word 0x00 10. " OIS2 ,OC2 output" "0,1"
|
|
rbitfld.word 0x00 9. " OIS1N ,OC1N output" "0,1"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " OIS1 ,OC1 output" "0,1"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare Control Update Selection" "COM bit only,COM bit/Rising edge"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare Preloaded Control" "Not preloaded,Preloaded"
|
|
else
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM1_CR2,Control register 2"
|
|
bitfld.word 0x00 14. " OIS4 ,OC4 output" "0,1"
|
|
bitfld.word 0x00 13. " OIS3N ,OC3N output" "0,1"
|
|
bitfld.word 0x00 12. " OIS3 ,OC3 output" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OIS2N ,OC2N output" "0,1"
|
|
bitfld.word 0x00 10. " OIS2 ,OC2 output" "0,1"
|
|
bitfld.word 0x00 9. " OIS1N ,OC1N output" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OIS1 ,OC1 output" "0,1"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare Control Update Selection" "COM bit only,COM bit/Rising edge"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare Preloaded Control" "Not preloaded,Preloaded"
|
|
endif
|
|
if (((per.l(ad:0x40012C00+0x8))&0x07)!=0x0)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM1_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
textline " "
|
|
sif (cpu()=="STM32F100C4"||cpu()=="STM32F100C6"||cpu()=="STM32F100R4"||cpu()=="STM32F100R6")
|
|
rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
textline " "
|
|
else
|
|
rbitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
else
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM1_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
textline " "
|
|
sif (cpu()=="STM32F100C4"||cpu()=="STM32F100C6"||cpu()=="STM32F100R4"||cpu()=="STM32F100R6")
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,,TI1F_ED,TI1FP1,TI1FP2,ETRF"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
endif
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM1_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM1_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " BIF ,Break interrupt Flag" "No break,Break"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMIF ,COM interrupt Flag" "No COM,COM"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM1_EGR,Event generation register"
|
|
bitfld.word 0x00 7. " BG ,Break Generation" "No effect,Generate"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No effect,Generate"
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare Control Update Generation" "No effect,Generate"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No effect,Generate"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No effect,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Generate"
|
|
if (((per.l(ad:0x40012C00+0x44))&0x300)==0x300)
|
|
if (((per.w((ad:0x40012C00+0x18)))&0x303)==0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40012C00+0x18)))&0x300)!=0x000)&&(((per.w((ad:0x40012C00+0x18)))&0x003)==0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40012C00+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40012C00+0x18)))&0x003)!=0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x18)))&0x303)==0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40012C00+0x18)))&0x300)!=0x000)&&(((per.w((ad:0x40012C00+0x18)))&0x003)==0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40012C00+0x18)))&0x300)==0x000)&&(((per.w((ad:0x40012C00+0x18)))&0x003)!=0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x11)==0x00)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x01)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x11)==0x10)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40012C00+0x44))&0x300)==0x300)
|
|
if (((per.w((ad:0x40012C00+0x1C)))&0x303)==0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40012C00+0x1C)))&0x300)!=0x000)&&(((per.w((ad:0x40012C00+0x1C)))&0x003)==0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40012C00+0x1C)))&0x300)==0x000)&&(((per.w((ad:0x40012C00+0x1C)))&0x003)!=0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
rbitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x1C)))&0x303)==0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "No effect,Clear"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40012C00+0x1C)))&0x300)!=0x000)&&(((per.w((ad:0x40012C00+0x1C)))&0x003)==0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "No effect,Clear"
|
|
rbitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
elif (((per.w((ad:0x40012C00+0x1C)))&0x300)==0x000)&&(((per.w((ad:0x40012C00+0x1C)))&0x003)!=0x000)
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
rbitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2"
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x00)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x0100)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
elif (((per.w((ad:0x40012C00+0x20)))&0x1100)==0x1000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
textline " "
|
|
if (((per.w(ad:0x40012C00+0x44))&0x300)==(0x200||0x300))
|
|
if (((per.w(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x303)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x300)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x03)!=0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x03)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x303)!=0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x303)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x300)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x03)!=0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x03)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
rbitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x303)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x300)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x03)!=0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x03)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x303)!=0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x303)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x300)==0x00)&&(((per.w(ad:0x40012C00+0x18))&0x03)!=0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40012C00+0x1C))&0x03)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x300)!=0x00)&&(((per.w(ad:0x40012C00+0x18))&0x03)==0x00)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2NP_CCC2P ,Capture/Compare 2 Complementary output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1NP_CC1P ,Capture/Compare 1 output polarity" "Non-inverted/rising edge,Inverted/falling edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output Polarity input/output" "Not inverted,Inverted"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 Complementary output Polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC3NE ,Capture/Compare 3 Complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output Polarity input/output" "Not inverted,Inverted"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 Complementary output Polarity" "High,Low"
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 Complementary output enable" "Off,On"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output Polarity input/output" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 Complementary output Polarity" "High,Low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 Complementary output enable" "Off,On"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output Polarity input/output" "Not inverted,Inverted"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM1_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM1_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM1_ARR,Auto-reload register"
|
|
group.word 0x30++0x1
|
|
line.word 0x00 "TIM1_RCR,Repetition counter register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition Counter Value"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM1_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM1_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM1_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM1_CCR4,Capture/compare register 4"
|
|
if (((per.l(ad:0x40012C00+0x44))&0x300)==0x100)
|
|
group.word 0x44++0x1
|
|
line.word 0x00 "TIM1_BDTR,Break and dead-time register"
|
|
bitfld.word 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
rbitfld.word 0x00 14. " AOE ,Automatic Output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
elif (((per.l(ad:0x40012C00+0x44))&0x300)==0x200)
|
|
group.word 0x44++0x1
|
|
line.word 0x00 "TIM1_BDTR,Break and dead-time register"
|
|
bitfld.word 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic Output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
else
|
|
group.word 0x44++0x1
|
|
line.word 0x00 "TIM1_BDTR,Break and dead-time register"
|
|
bitfld.word 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic Output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
endif
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM1_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM1_CR1,TIM1_CR2,TIM1_SMCR,TIM1_DIER,TIM1_SR,TIM1_EGR,TIM1_CCMR1,TIM1_CCMR2,TIM1_CCER,TIM1_CNT,TIM1_PSC,TIM1_ARR,TIM1_RCR,TIM1_CCR1,TIM1_CCR2,TIM1_CCR3,TIM1_CCR4,TIM1_BDTR,TIM1_DCR,TIM1_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM1_DMAR,DMA address for burst mode"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "General-purpose timer"
|
|
sif (!cpuis("STM32F030?4"))&&(!cpuis("STM32F030?6"))&&(!cpuis("STM32F030?8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB"))
|
|
tree "TIM2"
|
|
base ad:0x40000000
|
|
width 15.
|
|
if ((((per.w(ad:0x40000000))&0x60)>=0x10)||((((per.w(ad:0x40000000+0x08))&0x07)>=0x01)&&(((per.w(ad:0x40000000+0x08))&0x07)<=0x03)))
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM2_CR1,Control Register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
rbitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM2_CR1,Control Register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000))&0x01)==0x01)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM2_CR1,Control Register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
rbitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM2_CR1,Control Register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM2_CR2,Control Register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "CCx,Update"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "TIM2_SMCR,Slave Mode Control Register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM2_DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM2_SR,Status Register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM2_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Enable"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 generation input/output" "No action,Generate"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 generation input/output" "No action,Generate"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation input/output" "No action,Generate"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Generate"
|
|
textline " "
|
|
if (((per.w(ad:0x40000000+0x18))&0x303)==0x00)
|
|
if (((per.w((ad:0x40000000+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40000000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM2_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/ActivePWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM2_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM2_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM2_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x18))&0x03)==0x00)
|
|
if (((per.w((ad:0x40000000+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40000000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM2_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM2_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM2_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM2_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x18))&0x300)==0x00)
|
|
if (((per.w((ad:0x40000000+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40000000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM2_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM2_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM2_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM2_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000000+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40000000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM2_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM2_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM2_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM2_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.w(ad:0x40000000+0x1C))&0x303)==0x00)
|
|
if (((per.w((ad:0x40000000+0x20)))&0x0100)==0x0100)
|
|
if (((per.w((ad:0x40000000+0x20)))&0x1000)==0x1000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM2_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM2_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000000+0x20)))&0x1000)==0x1000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM2_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM2_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x1C))&0x03)==0x00)
|
|
if (((per.w((ad:0x40000000+0x20)))&0x0100)==0x0100)
|
|
if (((per.w((ad:0x40000000+0x20)))&0x1000)==0x1000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM2_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/ic3mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM2_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/ic3mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000000+0x20)))&0x1000)==0x1000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM2_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/ic3mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM2_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/ic3mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0x40000000+0x1C))&0x300)==0x00)
|
|
if (((per.w((ad:0x40000000+0x20)))&0x0100)==0x0100)
|
|
if (((per.w((ad:0x40000000+0x20)))&0x1000)==0x1000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM2_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM2_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000000+0x20)))&0x1000)==0x1000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM2_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM2_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000000+0x20)))&0x0100)==0x0100)
|
|
if (((per.w((ad:0x40000000+0x20)))&0x1000)==0x1000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM2_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM2_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000000+0x20)))&0x1000)==0x1000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM2_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM2_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
width 11.
|
|
textline " "
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM2_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM2_CNT,TIM2 Counter"
|
|
hexmask.long.word 0x00 16.--31. 1. " CNT[31:16] ,High counter value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Low counter value"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM2_PSC,TIM2 Prescaler"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TIM2_ARR,TIM2 Auto-Reload Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ARR[31:16] ,High auto-reload value"
|
|
hexmask.long.word 0x00 0.--15. 1. " ARR[15:0] ,Low Auto-reload value"
|
|
group.long 0x34++0x0F
|
|
line.long 0x00 "TIM2_CCR1,TIM2 Capture/Compare Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " CCR1[31:16] ,High capture/compare 1 value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low capture/compare 1 value"
|
|
line.long 0x04 "TIM2_CCR2,TIM2 Capture/Compare Register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " CCR2[31:16] ,High capture/compare 2 value"
|
|
hexmask.long.word 0x04 0.--15. 1. " CCR2[15:0] ,Low capture/compare 2 value"
|
|
line.long 0x08 "TIM2_CCR3,TIM2 Capture/compare Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " CCR3[31:16] ,High capture/compare 3 value"
|
|
hexmask.long.word 0x08 0.--15. 1. " CCR3[15:0] ,Low capture/compare 3 value"
|
|
line.long 0x0C "TIM2_CCR4,TIM2 Capture/compare Register 4"
|
|
hexmask.long.word 0x0C 16.--31. 1. " CCR4[31:16] ,High capture/compare 4 value"
|
|
hexmask.long.word 0x0C 0.--15. 1. " CCR4[15:0] ,Low capture/compare 4 value"
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "TIM2_DCR,DMA Control Register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM2_CR1,TIM2_CR2,TIM2_SMCR,TIM2_DIER,TIM2_SR,TIM2_EGR,TIM2_CCMR1,TIM2_CCMR2,TIM2_CCER,TIM2_CNT,TIM2_PSC,TIM2_ARR,TIM2_CCR1,TIM2_CCR2,TIM2_CCR3,TIM2_CCR4,TIM2_DCR,TIM2_DMAR,?..."
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "TIM2_DMAR,DMA Address for Burst Mode"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "TIM3"
|
|
base ad:0x40000400
|
|
width 15.
|
|
if ((((per.w(ad:0x40000400))&0x60)>=0x10)||((((per.w(ad:0x40000400+0x08))&0x07)>=0x01)&&(((per.w(ad:0x40000400+0x08))&0x07)<=0x03)))
|
|
if (((per.l(ad:0x40000400))&0x01)==0x01)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM3_CR1,Control Register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
rbitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM3_CR1,Control Register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000400))&0x01)==0x01)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM3_CR1,Control Register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
rbitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM3_CR1,Control Register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
textline " "
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM3_CR2,Control Register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,OC3REF,OC4REF"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "CCx,Update"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "TIM3_SMCR,Slave Mode Control Register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM3_DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM3_SR,Status Register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM3_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Enable"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 generation input/output" "No action,Generate"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 generation input/output" "No action,Generate"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation input/output" "No action,Generate"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Generate"
|
|
textline " "
|
|
if (((per.w(ad:0x40000400+0x18))&0x303)==0x00)
|
|
if (((per.w((ad:0x40000400+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40000400+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM3_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/ActivePWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM3_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000400+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM3_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM3_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0x40000400+0x18))&0x03)==0x00)
|
|
if (((per.w((ad:0x40000400+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40000400+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM3_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM3_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000400+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM3_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM3_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0x40000400+0x18))&0x300)==0x00)
|
|
if (((per.w((ad:0x40000400+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40000400+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM3_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM3_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000400+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM3_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM3_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000400+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40000400+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM3_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM3_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000400+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM3_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM3_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.w(ad:0x40000400+0x1C))&0x303)==0x00)
|
|
if (((per.w((ad:0x40000400+0x20)))&0x0100)==0x0100)
|
|
if (((per.w((ad:0x40000400+0x20)))&0x1000)==0x1000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM3_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM3_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000400+0x20)))&0x1000)==0x1000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM3_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM3_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0x40000400+0x1C))&0x03)==0x00)
|
|
if (((per.w((ad:0x40000400+0x20)))&0x0100)==0x0100)
|
|
if (((per.w((ad:0x40000400+0x20)))&0x1000)==0x1000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM3_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/ic3mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM3_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/ic3mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000400+0x20)))&0x1000)==0x1000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM3_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/ic3mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM3_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output compare 3 clear enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output compare 3 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output compare 3 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC3FE ,Output compare 3 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/ic3mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0x40000400+0x1C))&0x300)==0x00)
|
|
if (((per.w((ad:0x40000400+0x20)))&0x0100)==0x0100)
|
|
if (((per.w((ad:0x40000400+0x20)))&0x1000)==0x1000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM3_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM3_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000400+0x20)))&0x1000)==0x1000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM3_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM3_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output compare 4 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output compare 4 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC4PE ,Output compare 4 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output compare 4 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000400+0x20)))&0x0100)==0x0100)
|
|
if (((per.w((ad:0x40000400+0x20)))&0x1000)==0x1000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM3_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM3_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40000400+0x20)))&0x1000)==0x1000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM3_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "TIM3_CCMR2,Capture/Compare Mode Register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input capture 4 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input capture 4 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 selection" "Output,Input/IC4 mapped on TI4,Input/IC4 mapped on TI3,Input/IC4 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input capture 3 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input capture 3 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 selection" "Output,Input/IC3 mapped on TI3,Input/IC3 mapped on TI4,Input/IC3 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
width 11.
|
|
textline " "
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM3_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 15. " CC4NP ,Capture/Compare 4 output polarity" "High,Low"
|
|
bitfld.word 0x00 13. " CC4P ,Capture/Compare 4 output polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 12. " CC4E ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3NP ,Capture/Compare 3 output polarity" "High,Low"
|
|
bitfld.word 0x00 9. " CC3P ,Capture/Compare 3 output polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 8. " CC3E ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity" "High,Low"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity" "High,Low"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Non-inverted/High,Inverted/Low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM3_CNT,TIM3 Counter"
|
|
hexmask.long.word 0x00 16.--31. 1. " CNT[31:16] ,High counter value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Low counter value"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM3_PSC,TIM3 Prescaler"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TIM3_ARR,TIM3 Auto-Reload Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ARR[31:16] ,High auto-reload value"
|
|
hexmask.long.word 0x00 0.--15. 1. " ARR[15:0] ,Low Auto-reload value"
|
|
group.long 0x34++0x0F
|
|
line.long 0x00 "TIM3_CCR1,TIM3 Capture/Compare Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " CCR1[31:16] ,High capture/compare 1 value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR1[15:0] ,Low capture/compare 1 value"
|
|
line.long 0x04 "TIM3_CCR2,TIM3 Capture/Compare Register 2"
|
|
hexmask.long.word 0x04 16.--31. 1. " CCR2[31:16] ,High capture/compare 2 value"
|
|
hexmask.long.word 0x04 0.--15. 1. " CCR2[15:0] ,Low capture/compare 2 value"
|
|
line.long 0x08 "TIM3_CCR3,TIM3 Capture/compare Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " CCR3[31:16] ,High capture/compare 3 value"
|
|
hexmask.long.word 0x08 0.--15. 1. " CCR3[15:0] ,Low capture/compare 3 value"
|
|
line.long 0x0C "TIM3_CCR4,TIM3 Capture/compare Register 4"
|
|
hexmask.long.word 0x0C 16.--31. 1. " CCR4[31:16] ,High capture/compare 4 value"
|
|
hexmask.long.word 0x0C 0.--15. 1. " CCR4[15:0] ,Low capture/compare 4 value"
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "TIM3_DCR,DMA Control Register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM3_CR1,TIM3_CR2,TIM3_SMCR,TIM3_DIER,TIM3_SR,TIM3_EGR,TIM3_CCMR1,TIM3_CCMR2,TIM3_CCER,TIM3_CNT,TIM3_PSC,TIM3_ARR,TIM3_CCR1,TIM3_CCR2,TIM3_CCR3,TIM3_CCR4,TIM3_DCR,TIM3_DMAR,?..."
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "TIM3_DMAR,DMA Address for Burst Mode"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM14"
|
|
base ad:0x40002000
|
|
width 15.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM14_CR1,TIM14 Control Register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tCK_INT,2*tCK_INT,4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Counter overflow/ug bit,Counter overflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM14_DIER,TIM14 Interrupt Enable Register"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM14_SR,TIM14 Status Register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM14_EGR,TIM14 Event Generation Register"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action,Generate"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Generate"
|
|
if (((per.w((ad:0x40002000+0x18)))&0x03)==0x00)
|
|
if (((per.w((ad:0x40002000+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM14_CCMR1,TIM14 Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active level,Inactive level,OC1REF toggles,OC1REF forced low,OC1REF forced high,PWM mode 1,PWM mode 2"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "CC1 as output,CC1 as input,?..."
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM14_CCMR1,TIM14 Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active level,Inactive level,OC1REF toggles,OC1REF forced low,OC1REF forced high,PWM mode 1,PWM mode 2"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "CC1 as output,CC1 as input,?..."
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40002000+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM14_CCMR1,TIM14 Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "CC1 as output,CC1 as input,?..."
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM14_CCMR1,TIM14 Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "CC1 as output,CC1 as input,?..."
|
|
endif
|
|
endif
|
|
textline " "
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM14_CCER,TIM14 Capture/Compare Enable Register"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "0,1"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity output/input CC2NP=0|CC2NP=1" "High/Not inverted rising edge|,Low/Inverted falling edge|Not inverted both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Not active/Disabled,Active/Enabled"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM14_CNT,Counter"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM14_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM14_ARR,Auto-reload Register"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "TIM14_CCR1,Capture/Compare Register 1"
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "TIM14_OR,TIM14 Option Register"
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,Timer input 1 remap" "GPIO,RTC_CLK,HSE/32,MCO"
|
|
width 0x0B
|
|
tree.end
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8"||cpuis("STM32F030?8")||cpuis("STM32F071*")||cpuis("STM32F072*"))||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F070RB")||cpuis("STM32F070CB")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F051T8")
|
|
tree "TIM15"
|
|
base ad:0x40014000
|
|
width 15.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM15_CR1,Control Register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.l(ad:0x40014000+0x44))&0x300)==0x00)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM15_CR2,Control Register 2"
|
|
bitfld.word 0x00 10. " OIS2 ,Output idle state 2 (OC2 output)" "0,1"
|
|
bitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,?..."
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "CC,Update"
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "By COMG,By COMG/Rising"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preload control" "Not preloaded,Preloaded"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM15_CR2,Control Register 2"
|
|
rbitfld.word 0x00 10. " OIS2 ,Output idle state 2 (OC2 output)" "0,1"
|
|
rbitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
rbitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,Compare Pulse,OC1REF,OC2REF,?..."
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "CC,Update"
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "By COMG,By COMG/Rising"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preload control" "Not preloaded,Preloaded"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "TIM15_SMCR,Slave Mode Control Register"
|
|
bitfld.word 0x00 7. " MSM ,Master/Slave mode" "No action,Delayed"
|
|
textline " "
|
|
sif (CPU()=="STM32F100RC"||CPU()=="STM32F100RD"||CPU()=="STM32F100RE"||CPU()=="STM32F100VC"||CPU()=="STM32F100VD"||CPU()=="STM32F100VE"||CPU()=="STM32F100ZC"||CPU()=="STM32F100ZD"||CPU()=="STM32F100ZE"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")||(cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8")&&!CPUIS("STM32F058T8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F091?C"))||(cpuis("STM32F098?C"))
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,TI2FP2"
|
|
textline " "
|
|
elif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
textline " "
|
|
elif CPUIS("STM32F030CC")||CPUIS("STM32F030RC")||CPUIS("STM32F070C6")||CPUIS("STM32F070CB")||CPUIS("STM32F070F6")||CPUIS("STM32F070RB")
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" ",ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" ",,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset,Gated,Trigger,External clock"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM15_DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM15_SR,Status Register"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 overcapture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM15_EGR,Event Generation Register"
|
|
bitfld.word 0x00 7. " BG ,Break generation" "No action,Generate"
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Enabled"
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare control update generation" "No action,Update"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 generation input/output" "No action,Generate"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Generate"
|
|
if (((per.w((ad:0x40014000+0x18)))&0x303)==0x00)
|
|
if (((per.w((ad:0x40014000+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40014000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
elif (((per.w((ad:0x40014000+0x18)))&0x03)==0x00)
|
|
if (((per.w((ad:0x40014000+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40014000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
elif (((per.w((ad:0x40014000+0x18)))&0x300)==0x00)
|
|
if (((per.w((ad:0x40014000+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40014000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output compare 2 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/Active,PWM2/Inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output compare 2 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output compare 2 fast enable" "Normal/Min delay 5,Compared/Min delay 3"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014000+0x20)))&0x01)==0x01)
|
|
if (((per.w((ad:0x40014000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014000+0x20)))&0x10)==0x10)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM15_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input capture 2 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input capture 2 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 selection" "Output,Input/IC2 mapped on TI2,Input/IC2 mapped on TI1,Input/IC2 mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,Fck_int N=2,Fck_int N=4,Fck_int N=8,Fdts/2 N=6,Fdts/2 N=8,Fdts/4 N=6,Fdts/4 N=8,Fdts/8 N=6,Fdts/8 N=8,Fdts/16 N=5,Fdts/16 N=6,Fdts/16 N=8,Fdts/32 N=5,Fdts/32 N=6,Fdts/32 N=8"
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
width 12.
|
|
if (((per.l(ad:0x40014000+0x20))&0x03)==0x00)
|
|
if (((per.l(ad:0x40014000+0x20))&0x300)==0x00)
|
|
if (((per.l(ad:0x40014000+0x44))&0x300)==(0x200||0x300))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM15_CCER,Capture/Compare Enable Register"
|
|
rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity input/output" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "Active high,Active low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM15_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "Active high,Active low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40014000+0x44))&0x300)==(0x200||0x300))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM15_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity input/output" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "Not inverted/Rising edge,Inverted/Falling edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM15_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "Not inverted/Rising edge,Inverted/Falling edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40014000+0x20))&0x300)==0x00)
|
|
if (((per.l(ad:0x40014000+0x44))&0x300)==(0x200||0x300))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM15_CCER,Capture/Compare Enable Register"
|
|
rbitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity input/output" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "Active high,Active low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Not inverted/Rising edge,Inverted/Falling edge"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM15_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "Active high,Active low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Not inverted/Rising edge,Inverted/Falling edge"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40014000+0x44))&0x300)==(0x200||0x300))
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM15_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity input/output" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "Not inverted/Rising edge,Inverted/Falling edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Not inverted/Rising edge,Inverted/Falling edge"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM15_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity input/output" "Not inverted/Rising edge,Inverted/Falling edge"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable input/output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 output polarity input/output" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity input/output" "Not inverted/Rising edge,Inverted/Falling edge"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable input/output" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM15_CNT,Counter"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM15_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM15_ARR,Auto-reload Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "TIM15_RCR,Repetition Counter Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition counter value"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "TIM15_CCR1,Capture/Compare Register 1"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "TIM15_CCR2,Capture/Compare Register 2"
|
|
if (((per.w(ad:0x40014000+0x044))&0x300)==0x300)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM15_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014000+0x044))&0x300)==0x200)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM15_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014000+0x044))&0x300)==0x100)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM15_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM15_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "TIM15_DCR,DMA Control Register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM15_CR1,TIM15_CR2,TIM15_SMCR,TIM15_DIER,TIM15_SR,TIM15_EGR,TIM15_CCMR1,,TIM15_CCER,TIM15_CNT,TIM15_PSC,TIM15_ARR,TIM15_RCR,TIM15_CCR1,TIM15_CCR2,,,TIM15_BDTR,TIM15_DCR,TIM15_DMAR,?..."
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "TIM15_DMAR,DMA Address for Burst Mode"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "TIM16"
|
|
base ad:0x40014400
|
|
width 13.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM16_CR1,Control Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "No remapping,Remapping"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.w(ad:0x40014400+0x044))&0x300)==0x300)||(((per.w(ad:0x40014400+0x044))&0x300)==0x200)||(((per.w(ad:0x40014400+0x044))&0x300)==0x100)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM16_CR2,Control Register 2"
|
|
rbitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
rbitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "Event,Update event"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG,COMG/Rising"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM16_CR2,Control Register 2"
|
|
bitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "Event,Update event"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG,COMG/Rising"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM16_DIER,DMA/Interrupt Enable Register"
|
|
sif (!cpuis("STM32F038?6"))&&(!cpuis("STM32F048?6"))&&(!cpuis("STM32F058?8"))&&(!cpuis("STM32F078?B"))&&(!cpuis("STM32F091?B"))&&!cpuis("STM32F098?C")&&!cpuis("STM32F031E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F302?D")&&!cpuis("STM32F302?E")&&!CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F038?6"))&&(!cpuis("STM32F048?6"))&&(!cpuis("STM32F058?8"))&&(!cpuis("STM32F078?B"))&&(!cpuis("STM32F091?B"))&&(!cpuis("STM32F098?C")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F302?D")&&!cpuis("STM32F302?E")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE"))
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM16_SR,Status Register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 over-capture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM16_EGR,Event Generation Register"
|
|
bitfld.word 0x00 7. " BG ,Break generation" "No action,Generate"
|
|
textline " "
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare control update generation" "No update,Update"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Generate"
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.w((ad:0x40014400+0x18)))&0x03)==0x00)
|
|
if (((per.w((ad:0x40014400+0x20)))&0x01)==0x01)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014400+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014400+0x18)))&0x03)==0x00)
|
|
if (((per.w((ad:0x40014400+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014400+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((((per.w(ad:0x40014400+0x044))&0x300)==0x300)||(((per.w(ad:0x40014400+0x044))&0x300)==0x200))
|
|
if (((per.w((ad:0x40014400+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM16_CCER,Capture/Compare Enable Register"
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity OC1N" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM16_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. 3. " CC1NP-CC1P ,The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for capture operation" "Non-inverted/Rising edge,Inverted/Falling edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014400+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM16_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity OC1N" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity output" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM16_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. 3. " CC1NP-CC1P ,The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for capture operation" "Non-inverted/Rising edge,Inverted/Falling edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if ((per.w(ad:0x40014400)&0x800)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM16_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM16_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if ((per.w(ad:0x40014400)&0x800)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM16_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM16_CNT,Counter"
|
|
rbitfld.long 0x00 31. " UIFCPY ,UIF copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM16_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM16_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM16_ARR,Auto-Reload Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "TIM16_RCR,Repetition Counter Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition counter value"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "TIM16_CCR1,Capture/Compare Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if (((per.w(ad:0x40014400+0x044))&0x300)==0x300)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014400+0x044))&0x300)==0x200)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014400+0x044))&0x300)==0x100)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40014400+0x044))&0x300)==0x300)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014400+0x044))&0x300)==0x200)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014400+0x044))&0x300)==0x100)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for Idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
endif
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "TIM16_DCR,DMA Control Register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM16_CR1,TIM16_CR2,,TIM16_DIER,TIM16_SR,TIM16_EGR,TIM16_CMR1,,TIM16_CCER,TIM16_CNT,TIM16_PSC,TIM16_ARR,TIM16_RCR,TIM16_CCR1,,,,TIM16_BDTR,TIM16_DCR,TIM16_DMAR,TIM16_OR,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM16_CR1,TIM16_CR2,,TIM16_DIER,TIM16_SR,TIM16_EGR,TIM16_CMR1,,TIM16_CCER,TIM16_CNT,TIM16_PSC,TIM16_ARR,TIM16_RCR,TIM16_CCR1,,,,TIM16_BDTR,TIM16_DCR,TIM16_DMAR,?..."
|
|
endif
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "TIM16_DMAR,DMA Address for Full Transfer"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TIM16_OR,TIM16 Option Register"
|
|
bitfld.long 0x00 0.--1. " TI1_RMP ,Timer 16 input 1 connection" "GPIO,RTC_clock,HSE/32,MCO"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM17"
|
|
base ad:0x40014800
|
|
width 13.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM17_CR1,Control Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "No remapping,Remapping"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.w(ad:0x40014800+0x044))&0x300)==0x300)||(((per.w(ad:0x40014800+0x044))&0x300)==0x200)||(((per.w(ad:0x40014800+0x044))&0x300)==0x100)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM17_CR2,Control Register 2"
|
|
rbitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
rbitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "Event,Update event"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG,COMG/Rising"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM17_CR2,Control Register 2"
|
|
bitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "Event,Update event"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG,COMG/Rising"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM17_DIER,DMA/Interrupt Enable Register"
|
|
sif (!cpuis("STM32F038?6"))&&(!cpuis("STM32F048?6"))&&(!cpuis("STM32F058?8"))&&(!cpuis("STM32F078?B"))&&(!cpuis("STM32F091?B"))&&!cpuis("STM32F098?C")&&!cpuis("STM32F031E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F302?D")&&!cpuis("STM32F302?E")&&!CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F038?6"))&&(!cpuis("STM32F048?6"))&&(!cpuis("STM32F058?8"))&&(!cpuis("STM32F078?B"))&&(!cpuis("STM32F091?B"))&&(!cpuis("STM32F098?C")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F302?D")&&!cpuis("STM32F302?E")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE"))
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM17_SR,Status Register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 over-capture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM17_EGR,Event Generation Register"
|
|
bitfld.word 0x00 7. " BG ,Break generation" "No action,Generate"
|
|
textline " "
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare control update generation" "No update,Update"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Generate"
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.w((ad:0x40014800+0x18)))&0x03)==0x00)
|
|
if (((per.w((ad:0x40014800+0x20)))&0x01)==0x01)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014800+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014800+0x18)))&0x03)==0x00)
|
|
if (((per.w((ad:0x40014800+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014800+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((((per.w(ad:0x40014800+0x044))&0x300)==0x300)||(((per.w(ad:0x40014800+0x044))&0x300)==0x200))
|
|
if (((per.w((ad:0x40014800+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM17_CCER,Capture/Compare Enable Register"
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity OC1N" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM17_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. 3. " CC1NP-CC1P ,The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for capture operation" "Non-inverted/Rising edge,Inverted/Falling edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014800+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM17_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity OC1N" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity output" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM17_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. 3. " CC1NP-CC1P ,The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for capture operation" "Non-inverted/Rising edge,Inverted/Falling edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if ((per.w(ad:0x40014800)&0x800)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM17_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM17_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if ((per.w(ad:0x40014800)&0x800)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM17_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM17_CNT,Counter"
|
|
rbitfld.long 0x00 31. " UIFCPY ,UIF copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM17_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM17_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM17_ARR,Auto-Reload Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "TIM17_RCR,Repetition Counter Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition counter value"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "TIM17_CCR1,Capture/Compare Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if (((per.w(ad:0x40014800+0x044))&0x300)==0x300)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014800+0x044))&0x300)==0x200)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014800+0x044))&0x300)==0x100)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40014800+0x044))&0x300)==0x300)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014800+0x044))&0x300)==0x200)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014800+0x044))&0x300)==0x100)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for Idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
endif
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "TIM17_DCR,DMA Control Register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM17_CR1,TIM17_CR2,,TIM17_DIER,TIM17_SR,TIM17_EGR,TIM17_CMR1,,TIM17_CCER,TIM17_CNT,TIM17_PSC,TIM17_ARR,TIM17_RCR,TIM17_CCR1,,,,TIM17_BDTR,TIM17_DCR,TIM17_DMAR,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM17_CR1,TIM17_CR2,,TIM17_DIER,TIM17_SR,TIM17_EGR,TIM17_CMR1,,TIM17_CCER,TIM17_CNT,TIM17_PSC,TIM17_ARR,TIM17_RCR,TIM17_CCR1,,,,TIM17_BDTR,TIM17_DCR,TIM17_DMAR,?..."
|
|
endif
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "TIM17_DMAR,DMA Address for Full Transfer"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8"||cpuis("STM32F030?8")||cpuis("STM32F071*")||cpuis("STM32F072*")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070CB")||cpuis("STM32F070RB")||cpuis("STM32F051T8")||cpuis("STM32F058T8"))
|
|
tree "Basic Timer"
|
|
tree "TIM6"
|
|
base ad:0x40001000
|
|
width 11.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM6_CR1,Control Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 11. " UIFREM ,UIF status bit remapping" "No remapping,Remapping"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070RB")
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM6_CR2,Control Register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,?..."
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM6_DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM6_SR,Status Register"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM6_EGR,Event Generation Register"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No effect,Generate"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if ((per.l(ad:0x40003000)&0x800)==0x000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM6_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM6_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM6_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM6_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM6_ARR,Auto-Reload Register"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("STM32F07*")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F070RB")||cpuis("STM32F070CB")||cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
tree "TIM7"
|
|
base ad:0x40001400
|
|
width 11.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM7_CR1,Control Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 11. " UIFREM ,UIF status bit remapping" "No remapping,Remapping"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070RB")
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM7_CR2,Control Register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,?..."
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM7_DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM7_SR,Status Register"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM7_EGR,Event Generation Register"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No effect,Generate"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if ((per.l(ad:0x40003000)&0x800)==0x000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM7_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM7_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM7_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM7_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM7_ARR,Auto-Reload Register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "IWDG (Independent watchdog)"
|
|
base ad:0x40003000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "IWDG_KR,Key Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " KEY ,Key value"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "IWDG_PR,Prescaler Register"
|
|
bitfld.long 0x00 0.--2. " PR ,Prescaler divider" "/4,/8,/16,/32,/64,/128,/256,/256"
|
|
line.long 0x04 "IWDG_RLR,Reload Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " RL ,Watchdog counter reload value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "IWDG_SR,Status Register"
|
|
sif ((cpu()=="STM32F050C4")||(cpu()=="STM32F050C6")||(cpu()=="STM32F050K4")||(cpu()=="STM32F050K6")||(cpu()=="STM32F051C4")||(cpu()=="STM32F051C6")||(cpu()=="STM32F051C8")||(cpu()=="STM32F051K4")||(cpu()=="STM32F051K6")||(cpu()=="STM32F051K8")||(cpu()=="STM32F051R4")||(cpu()=="STM32F051R6")||(cpu()=="STM32F051R8")||(cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||(cpuis("STM32F7*"))||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB"))
|
|
bitfld.long 0x00 2. " WVU ,Watchdog counter window value update" "Completed,Running"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " RVU ,Watchdog counter reload value update" "Completed,Running"
|
|
bitfld.long 0x00 0. " PVU ,Watchdog prescaler value update" "Completed,Running"
|
|
sif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8"||(cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||(cpuis("STM32F7*"))||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB"))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IWDG_WINR,Window Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " WIN ,Watchdog counter window value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "WWDG (System window watchdog)"
|
|
base ad:0x40002C00
|
|
width 10.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "WWDG_CR,Control Register"
|
|
bitfld.long 0x00 7. " WDGA ,Activation bit" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " T ,7-bit counter"
|
|
line.long 0x04 "WWDG_CFR,Configuration Register"
|
|
bitfld.long 0x04 9. " EWI ,Early wakeup interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7.--8. " WDGTB ,Timer base" "Div by 1,Div by 2,Div by 4,Div by 8"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--6. 1. " W ,7-bit window value"
|
|
line.long 0x08 "WWDG_SR,Status Register"
|
|
bitfld.long 0x08 0. " EWIF ,Early wakeup interrupt flag" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTC (Real-time clock)"
|
|
base ad:0x40002800
|
|
width 14.
|
|
if (((per.l(ad:0x40002800+0x08)&0x40)==0x00)&&((per.l(ad:0x40002800)&0x300000)!=0x200000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RTC_TR,RTC Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x40002800+0x08)&0x40)==0x00)&&((per.l(ad:0x40002800)&0x300000)==0x200000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RTC_TR,RTC Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x40002800+0x08)&0x40)==0x40)&&((per.l(ad:0x40002800)&0x300000)==0x100000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RTC_TR,RTC Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RTC_TR,RTC Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
endif
|
|
if (((per.l(ad:0x40002800+0x04)&0x30)==0x30)&&((per.l(ad:0x40002800+0x04)&0x1000)==0x1000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RTC_DR,RTC Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. ".,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 20.--23. ".,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x40002800+0x004)&0x30)==0x30)&&((per.l(ad:0x40002800+0x004)&0x1000)==0x00))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RTC_DR,RTC Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. ".,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 20.--23. ".,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x40002800+0x04)&0x30)!=0x30)&&((per.l(ad:0x40002800+0x04)&0x1000)==0x1000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RTC_DR,RTC Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. ".,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 20.--23. ".,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RTC_DR,RTC Date Register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12. ".,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x00 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 20.--23. ".,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 16.--19. ",Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "RTC_CR,RTC Control Register"
|
|
bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,Alarm A,Alarm B,Wakeup"
|
|
bitfld.long 0x00 20. " POL ,Output polarity" "High,Low"
|
|
bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz"
|
|
textline " "
|
|
bitfld.long 0x00 18. " BKP ,Backup" "Not performed,Performed"
|
|
bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Subtracted"
|
|
bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added"
|
|
bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*")||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F051T8")
|
|
bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TSE ,Time stamp enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FMT ,Hour format" "24 hour/day,AM/PM"
|
|
bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 4. " REFCKON ,RTC_REFIN reference clock detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising edge,Falling edge"
|
|
textline " "
|
|
sif (cpuis("STM32F031*")||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||cpuis("STM32F072*")||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8"))
|
|
bitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,CK_SPRE,CK_SPRE,CK_SPRE+2^16,CK_SPRE+2^16"
|
|
endif
|
|
line.long 0x04 "RTC_ISR,RTC Initialization and Status Register"
|
|
rbitfld.long 0x04 16. " RECALPF ,Recalibration pending Flag" "Not detected,Detected"
|
|
textline " "
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))||cpuis("STM32F051*")||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")
|
|
bitfld.long 0x04 15. " TAMP3F ,RTC_TAMP3 detection flag" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x04 14. " TAMP2F ,RTC_TAMP2 detection flag" "Not detected,Detected"
|
|
bitfld.long 0x04 13. " TAMP1F ,RTC_TAMP1 detection flag" "Not detected,Detected"
|
|
bitfld.long 0x04 12. " TSOVF ,Time-stamp overflow flag" "Not overflowed,Overflowed"
|
|
bitfld.long 0x04 11. " TSF ,Time-stamp flag" "Not occurred,Occurred"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F051T8")
|
|
bitfld.long 0x04 10. " WUTF ,Wakeup timer flag (counter reached 0)" "Not reached,Reached"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " ALRAF ,Alarm A flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " INIT ,Initialization mode" "Free running,Enabled"
|
|
rbitfld.long 0x04 6. " INITF ,Initialization flag" "Not allowed,Allowed"
|
|
bitfld.long 0x04 5. " RSF ,Registers synchronization flag" "Not synchronized,Synchronized"
|
|
textline " "
|
|
rbitfld.long 0x04 4. " INITS ,Initialization status flag" "Not initialized,Initialized"
|
|
rbitfld.long 0x04 3. " SHPF ,Shift operation pending" "Not pending,Pending"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F051T8")
|
|
rbitfld.long 0x04 2. " WUTWF ,Wakeup timer configuration update" "Not allowed,Allowed"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x04 0. " ALRAWF ,Alarm A rite flag" "Not allowed,Allowed"
|
|
line.long 0x08 "RTC_PRER,RTC Prescaler Register"
|
|
hexmask.long.byte 0x08 16.--22. 0x01 " PREDIV_A ,Asynchronous prescaler factor"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--14. 0x01 " PREDIV_S ,Synchronous prescaler factor"
|
|
sif (cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8"))
|
|
if ((per.l(ad:0x40002800+0x0C)&0x04)==0x04)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_WUTR,RTC Wakeup Timer Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WUT ,Wakeup auto-reload value bits"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40002800+0x08)&0x40)==0x00)&&((per.l(ad:0x40002800+0x1C)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x000)&&((per.l(ad:0x40002800+0x00C)&0x081)!=0x000))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x08)&0x40)==0x00)&&((per.l(ad:0x40002800+0x1C)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x000)&&((per.l(ad:0x40002800+0x00C)&0x081)==0x000))
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x08)&0x40)==0x00)&&((per.l(ad:0x40002800+0x1C)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x00C)&0x081)!=0x000))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x08)&0x40)==0x00)&&((per.l(ad:0x40002800+0x1C)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x00C)&0x081)==0x000))
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,?..."
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,?..."
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,?..."
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x08)&0x40)==0x00)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x000)&&((per.l(ad:0x40002800+0x00C)&0x081)!=0x000))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x08)&0x40)==0x00)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x000)&&((per.l(ad:0x40002800+0x00C)&0x081)==0x000))
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x08)&0x40)==0x00)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x00C)&0x081)!=0x000))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x08)&0x40)==0x00)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x00C)&0x081)==0x000))
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00)&&((per.l(ad:0x40002800+0x0C)&0x81)!=0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00)&&((per.l(ad:0x40002800+0x0C)&0x81)==0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x81)!=0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x81)==0x00))
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00)&&((per.l(ad:0x40002800+0x0C)&0x81)!=0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Day unit,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00)&&((per.l(ad:0x40002800+0x0C)&0x81)==0x00))
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Day unit,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif ((per.l(ad:0x40002800+0x0C)&0x81)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Day unit,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC Alarm A Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,-,-,-,-,-,-,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Day unit,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
endif
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "RTC_WPR,RTC Write Protection Register"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " KEY ,Write protection key"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "RTC_SSR,RTC Sub Second Register"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SS ,Sub second value"
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "RTC_SHIFTR,RTC Shift Control Register"
|
|
bitfld.long 0x00 31. " ADD1S ,Add one second" "No effect,Added to the clock/calendar"
|
|
hexmask.long.word 0x00 0.--14. 0x01 " SUBFS ,Subtract a fraction of a second"
|
|
if ((per.l(ad:0x40002800+0x0C)&0x800)==0x00)
|
|
hgroup.long 0x30++0x07
|
|
hide.long 0x00 "RTC_TSTR,RTC Time Stamp Time Register"
|
|
hide.long 0x04 "RTC_TSDR,RTC Time Stamp Date Register"
|
|
elif (((per.l(ad:0x40002800+0x0C)&0x0800)==0x0800)&&((per.l(ad:0x40002800+0x08)&0x40)==0x00))
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "RTC_TSTR,RTC Time Stamp Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
line.long 0x04 "RTC_TSDR,RTC Time Stamp Date Register"
|
|
bitfld.long 0x04 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x04 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x04 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x04 12. ".,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x04 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "RTC_TSTR,RTC Time Stamp Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--14. ":,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. ":,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 22. " ,AM/PM notation" "AM,PM"
|
|
line.long 0x04 "RTC_TSDR,RTC Time Stamp Date Register"
|
|
bitfld.long 0x04 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x04 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x04 0.--3. ",Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x04 12. ".,Month tens in BCD format" "0,1"
|
|
bitfld.long 0x04 8.--11. ",Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
if ((per.l(ad:0x40002800+0x0C)&0x800)==0x800)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "RTC_TSSSR,RTC Time Stamp Sub Second Register"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SS ,Sub second value"
|
|
else
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "RTC_TSSSR,RTC Time Stamp Sub Second Register"
|
|
endif
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "RTC_CALR,RTC Calibration Register"
|
|
bitfld.long 0x00 15. " CALP ,Increase frequency of RTC by 488.5 ppm" "No RTCCLK,One RTCCLK"
|
|
bitfld.long 0x00 14. " CALW8 ,Use an 8-second calibration cycle period" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " CALW16 ,Use a 16-second calibration cycle period" "Not selected,Selected"
|
|
hexmask.long.word 0x00 0.--8. 0x01 " CALM ,Calibration minus"
|
|
if ((per.l(ad:0x40002800+0x40)&0x1800)!=0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RTC_TAFCR,RTC Tamper and Alternate Function Configuration Register"
|
|
bitfld.long 0x00 23. " PC15MODE ,PC15 mode" "Standby mode,Push-pull"
|
|
bitfld.long 0x00 22. " PC15VALUE ,PC15 value" "0,1"
|
|
bitfld.long 0x00 21. " PC14MODE ,PC14 mode" "Standby mode,Push-pull"
|
|
bitfld.long 0x00 20. " PC14VALUE ,PC14 value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PC13MODE ,PC13 mode" "Standby mode,Push-pull"
|
|
bitfld.long 0x00 18. " PC13VALUE ,RTC_ALARM output type/PC13 value" "Open-drain,Push-pull"
|
|
bitfld.long 0x00 15. " TAMPPUDIS ,Rtc_tampx pull-up disable" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " TAMPPRCH ,Rtc_tampx precharge duration" "1 RTCCLK cycle,2 RTCCLK cycles,4 RTCCLK cycles,8 RTCCLK cycles"
|
|
textline " "
|
|
bitfld.long 0x00 11.--12. " TAMPFLT ,Rtc_tampx filter count" "On edge,After 2 samples,After 4 samples,After 8 samples"
|
|
bitfld.long 0x00 8.--10. " TAMPFREQ ,Tamper sampling frequency" "RTCCLK/32768,RTCCLK/16384,RTCCLK/8192,RTCCLK/4096,RTCCLK/2048,RTCCLK/1024,RTCCLK/512,RTCCLK/256"
|
|
bitfld.long 0x00 7. " TAMPTS ,Activate timestamp on tamper detection event" "Timestamp not saved,Timestamp saved"
|
|
textline " "
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))||cpuis("STM32F051*")||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")
|
|
bitfld.long 0x00 6. " TAMP3TRG ,Active level for RTC_TAMP3 input" "Low,High"
|
|
bitfld.long 0x00 5. " TAMP3E ,RTC_TAMP3 detection enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 4. " TAMP2TRG ,Active level for RTC_TAMP1 input" "Low,High"
|
|
bitfld.long 0x00 3. " TAMP2E ,RTC_TAMP2 input detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TAMP1TRG ,Active level for RTC_TAMP1 input" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TAMP1E ,RTC_TAMP1 input detection enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RTC_TAFCR,RTC Tamper and Alternate Function Configuration Register"
|
|
bitfld.long 0x00 23. " PC15MODE ,PC15 mode" "Standby mode,Push-pull"
|
|
bitfld.long 0x00 22. " PC15VALUE ,PC15 value" "0,1"
|
|
bitfld.long 0x00 21. " PC14MODE ,PC14 mode" "Standby mode,Push-pull"
|
|
bitfld.long 0x00 20. " PC14VALUE ,PC14 value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PC13MODE ,PC13 mode" "Standby mode,Push-pull"
|
|
bitfld.long 0x00 18. " PC13VALUE ,RTC_ALARM output type/PC13 value" "Open-drain,Push-pull"
|
|
bitfld.long 0x00 15. " TAMPPUDIS ,Rtc_tampx pull-up disable" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " TAMPPRCH ,Rtc_tampx precharge duration" "1 RTCCLK cycle,2 RTCCLK cycles,4 RTCCLK cycles,8 RTCCLK cycles"
|
|
textline " "
|
|
bitfld.long 0x00 11.--12. " TAMPFLT ,Rtc_tampx filter count" "On edge,After 2 samples,After 4 samples,After 8 samples"
|
|
bitfld.long 0x00 8.--10. " TAMPFREQ ,Tamper sampling frequency" "RTCCLK/32768,RTCCLK/16384,RTCCLK/8192,RTCCLK/4096,RTCCLK/2048,RTCCLK/1024,RTCCLK/512,RTCCLK/256"
|
|
bitfld.long 0x00 7. " TAMPTS ,Activate timestamp on tamper detection event" "Timestamp not saved,Timestamp saved"
|
|
textline " "
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))||cpuis("STM32F051*")||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")
|
|
bitfld.long 0x00 6. " TAMP3TRG ,Active level for RTC_TAMP3 input" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 5. " TAMP3E ,RTC_TAMP3 detection enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 4. " TAMP2TRG ,Active level for RTC_TAMP1 input" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 3. " TAMP2E ,RTC_TAMP2 input detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TAMP1TRG ,Active level for RTC_TAMP1 input" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TAMP1E ,RTC_TAMP1 input detection enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.l(ad:0x40002800+0x0C)&0x81)!=0x00)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "RTC_ALRMASSR,RTC Alarm A Sub Second Register"
|
|
bitfld.long 0x00 24.--27. " MASKSS ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,All bits compared"
|
|
hexmask.long.word 0x00 0.--14. 0x01 " SS ,Sub seconds value"
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "RTC_ALRMASSR,RTC Alarm A Sub Second Register"
|
|
bitfld.long 0x00 24.--27. " MASKSS ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,All bits compared"
|
|
hexmask.long.word 0x00 0.--14. 0x01 " SS ,Sub seconds value"
|
|
endif
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))||cpuis("STM32F051*")||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
group.long 0x50++0x13
|
|
line.long 0x0 "BKP0R,RTC Backup Register 0"
|
|
line.long 0x4 "BKP1R,RTC Backup Register 1"
|
|
line.long 0x8 "BKP2R,RTC Backup Register 2"
|
|
line.long 0xC "BKP3R,RTC Backup Register 3"
|
|
line.long 0x10 "BKP4R,RTC Backup Register 4"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("STM32F030?4"))||(cpuis("STM32F030?6"))||(cpuis("STM32F030?8"))||(cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))||((cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||(cpuis("STM32F058?8")&&!cpuis("STM32F058T8"))||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*"))
|
|
tree "I2C (Inter-integrated circuit)"
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
width 18.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "I2C1_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable (Device mode/Host mode)" "Disabled/Not supported,Enabled/Supported"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif !CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302VB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F302VC")&&(cpu()!="STM32F302RB")&&(cpu()!="STM32F302RC")&&(cpu()!="STM32F303RB")&&(cpu()!="STM32F303RC")&&(cpu()!="STM32F303CB")&&(cpu()!="STM32F303VB")&&(cpu()!="STM32F303CC")&&(cpu()!="STM32F303VC")&&(cpu()!="STM32F313CC")&&(cpu()!="STM32F313RC")&&(cpu()!="STM32F313VC")&&(cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372V8")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372VB")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F372VC")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373RB")&&(cpu()!="STM32F373VC")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373RC")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F373V8")&&(cpu()!="STM32F373R8")&&(cpu()!="STM32F373VB")&&(cpu()!="STM32F383CC")&&(cpu()!="STM32F383RC")&&(cpu()!="STM32F383VC")&&!CPUIS("STM32F058T8")&&!CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.long 0x00 13. " SWRST ,Software reset" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 ti2cclk,12 ti2cclk,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
line.long 0x04 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x04 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
textline " "
|
|
bitfld.long 0x04 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x04 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed"
|
|
hexmask.long.byte 0x04 16.--23. 1. " NBYTES ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x04 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x04 14. " STOP ,Stop generation" "No stop,Stop"
|
|
bitfld.long 0x04 13. " START ,Start generation" "No start,Start/Restart"
|
|
textline " "
|
|
bitfld.long 0x04 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x04 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x04 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " SADD ,Slave address bit 9:8" "0,1,2,3"
|
|
hexmask.long.byte 0x04 1.--7. 1. " SADD ,Slave address bit 7:1"
|
|
bitfld.long 0x04 0. " SADD0 ,Slave address bit 0" "0,1"
|
|
line.long 0x08 "I2C1_OAR1,Own address 1 register"
|
|
bitfld.long 0x08 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit"
|
|
bitfld.long 0x08 8.--9. " OA1 ,Interface address" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x08 1.--7. 1. " OA1[7:1] ,Interface address"
|
|
bitfld.long 0x08 0. " OA1[0] ,Interface address" "0,1"
|
|
line.long 0x0C "I2C1_OAR2,Own address 2 register"
|
|
bitfld.long 0x0C 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8.--10. " OA2MSK ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
hexmask.long.byte 0x0C 1.--7. 1. " OA2 ,Interface address"
|
|
line.long 0x10 "I2C1_TIMINGR,Timing register"
|
|
bitfld.long 0x10 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--15. 1. " SCLH ,SCL high period"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SCLL ,SCL low period"
|
|
line.long 0x14 "I2C1_TIMEOUTR,Timeout register"
|
|
bitfld.long 0x14 31. " TEXTEN ,Extended clock timeout enable" "Disalbed,Enabled"
|
|
hexmask.long.word 0x14 16.--27. 1. " TIMEOUTB ,Bus timeout B"
|
|
bitfld.long 0x14 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 12. " TIDLE ,Idle clock timeout detection" "Low timeout,High timeout"
|
|
hexmask.long.word 0x14 0.--11. 1. " TIMEOUTA ,Bus Timeout A"
|
|
line.long 0x18 "I2C1_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. " ADDCODE ,Address match code"
|
|
rbitfld.long 0x18 16. " DIR ,Transfer direction" "Write,Read"
|
|
rbitfld.long 0x18 15. " BUSY ,Bus busy" "Not busy,Busy"
|
|
textline " "
|
|
rbitfld.long 0x18 13. " ALERT ,SMBus alert" "Not detected,Detected"
|
|
rbitfld.long 0x18 12. " TIMEOUT ,Timeout or tLOW detection flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x18 11. " PECERR ,PEC Error in reception" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x18 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred"
|
|
rbitfld.long 0x18 9. " ARLO ,Arbitration lost" "Not occurred,Occurred"
|
|
rbitfld.long 0x18 8. " BERR ,Bus error" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x18 7. " TCR ,Transfer Complete Reload" "Not completed,Completed"
|
|
rbitfld.long 0x18 6. " TC ,Transfer Complete" "Not completed,Completed"
|
|
rbitfld.long 0x18 5. " STOPF ,Stop detection flag" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x18 4. " NACKF ,Not Acknowledge received flag" "Not received,Received"
|
|
rbitfld.long 0x18 3. " ADDR ,Address matched" "Not matched,Matched"
|
|
rbitfld.long 0x18 2. " RXNE ,Receive data register not empty" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x18 1. " TXIS ,Transmit interrupt status" "Not empty,Empty"
|
|
bitfld.long 0x18 0. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "I2C1_ICR,Interrupt clear register"
|
|
bitfld.long 0x00 13. " ALERTCF ,Alert flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " TIMOUTCF ,Timeout detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 11. " PECCF ,PEC Error flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OVRCF ,Overrun/Underrun flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " ARLOCF ,Arbitration Lost flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " NACKCF ,Not Acknowledge flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " ADDRCF ,Address Matched flag clear" "No effect,Clear"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "I2C1_PECR,PEC register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PEC ,Packet error checking register"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "I2C1_RXDR,Receive data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,8-bit receive data"
|
|
if (((per.l(ad:0x40005418))&0x01)==0x01)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "I2C1_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "I2C1_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (CPU()=="STM32F051C8"||CPU()=="STM32F051K8"||CPU()=="STM32F051R8")
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
width 18.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "I2C2_CR1,Control register 1"
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif !CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302VB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F302VC")&&(cpu()!="STM32F302RB")&&(cpu()!="STM32F302RC")&&(cpu()!="STM32F303RB")&&(cpu()!="STM32F303RC")&&(cpu()!="STM32F303CB")&&(cpu()!="STM32F303VB")&&(cpu()!="STM32F303CC")&&(cpu()!="STM32F303VC")&&(cpu()!="STM32F313CC")&&(cpu()!="STM32F313RC")&&(cpu()!="STM32F313VC")&&(cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372V8")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372VB")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F372VC")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373RB")&&(cpu()!="STM32F373VC")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373RC")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F373V8")&&(cpu()!="STM32F373R8")&&(cpu()!="STM32F373VB")&&(cpu()!="STM32F383CC")&&(cpu()!="STM32F383RC")&&(cpu()!="STM32F383VC")&&!CPUIS("STM32F058T8")&&!CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.long 0x00 13. " SWRST ,Software reset" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 ti2cclk,12 ti2cclk,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
line.long 0x04 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x04 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x04 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed"
|
|
hexmask.long.byte 0x04 16.--23. 1. " NBYTES ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x04 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x04 14. " STOP ,Stop generation" "No stop,Stop"
|
|
bitfld.long 0x04 13. " START ,Start generation" "No start,Start/Restart"
|
|
textline " "
|
|
bitfld.long 0x04 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x04 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x04 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " SADD ,Slave address bit 9:8" "0,1,2,3"
|
|
hexmask.long.byte 0x04 1.--7. 1. " SADD ,Slave address bit 7:1"
|
|
bitfld.long 0x04 0. " SADD0 ,Slave address bit 0" "0,1"
|
|
line.long 0x08 "I2C2_OAR1,Own address 1 register"
|
|
bitfld.long 0x08 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit"
|
|
bitfld.long 0x08 8.--9. " OA1 ,Interface address" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x08 1.--7. 1. " OA1[7:1] ,Interface address"
|
|
bitfld.long 0x08 0. " OA1[0] ,Interface address" "0,1"
|
|
line.long 0x0C "I2C2_OAR2,Own address 2 register"
|
|
bitfld.long 0x0C 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8.--10. " OA2MSK ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
hexmask.long.byte 0x0C 1.--7. 1. " OA2 ,Interface address"
|
|
line.long 0x10 "I2C2_TIMINGR,Timing register"
|
|
bitfld.long 0x10 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--15. 1. " SCLH ,SCL high period"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SCLL ,SCL low period"
|
|
line.long 0x14 "I2C2_TIMEOUTR,Timeout register"
|
|
bitfld.long 0x14 31. " TEXTEN ,Extended clock timeout enable" "Disalbed,Enabled"
|
|
hexmask.long.word 0x14 16.--27. 1. " TIMEOUTB ,Bus timeout B"
|
|
bitfld.long 0x14 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 12. " TIDLE ,Idle clock timeout detection" "Low timeout,High timeout"
|
|
hexmask.long.word 0x14 0.--11. 1. " TIMEOUTA ,Bus Timeout A"
|
|
line.long 0x18 "I2C2_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. " ADDCODE ,Address match code"
|
|
rbitfld.long 0x18 16. " DIR ,Transfer direction" "Write,Read"
|
|
rbitfld.long 0x18 15. " BUSY ,Bus busy" "Not busy,Busy"
|
|
textline " "
|
|
rbitfld.long 0x18 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred"
|
|
rbitfld.long 0x18 9. " ARLO ,Arbitration lost" "Not occurred,Occurred"
|
|
rbitfld.long 0x18 8. " BERR ,Bus error" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x18 7. " TCR ,Transfer Complete Reload" "Not completed,Completed"
|
|
rbitfld.long 0x18 6. " TC ,Transfer Complete" "Not completed,Completed"
|
|
rbitfld.long 0x18 5. " STOPF ,Stop detection flag" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x18 4. " NACKF ,Not Acknowledge received flag" "Not received,Received"
|
|
rbitfld.long 0x18 3. " ADDR ,Address matched" "Not matched,Matched"
|
|
rbitfld.long 0x18 2. " RXNE ,Receive data register not empty" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x18 1. " TXIS ,Transmit interrupt status" "Not empty,Empty"
|
|
bitfld.long 0x18 0. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "I2C2_ICR,Interrupt clear register"
|
|
bitfld.long 0x00 10. " OVRCF ,Overrun/Underrun flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " ARLOCF ,Arbitration Lost flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " NACKCF ,Not Acknowledge flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " ADDRCF ,Address Matched flag clear" "No effect,Clear"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "I2C2_RXDR,Receive data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,8-bit receive data"
|
|
if (((per.l(ad:0x40005818))&0x01)==0x01)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "I2C2_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "I2C2_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
else
|
|
tree "I2C (Inter-integrated circuit)"
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
width 15.
|
|
if (((per.l(ad:0x40005400))&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C1_CR1,Control Register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable (Device mode/host mode)" "Disabled/not supported,Enabled/supported"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302VB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F302VC")&&(cpu()!="STM32F302RB")&&(cpu()!="STM32F302RC")&&(cpu()!="STM32F303RB")&&(cpu()!="STM32F303RC")&&(cpu()!="STM32F303CB")&&(cpu()!="STM32F303VB")&&(cpu()!="STM32F303CC")&&(cpu()!="STM32F303VC")&&(cpu()!="STM32F313CC")&&(cpu()!="STM32F313RC")&&(cpu()!="STM32F313VC")&&(cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372V8")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372VB")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F372VC")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373RB")&&(cpu()!="STM32F373VC")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373RC")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F373V8")&&(cpu()!="STM32F373R8")&&(cpu()!="STM32F373VB")&&(cpu()!="STM32F383CC")&&(cpu()!="STM32F383RC")&&(cpu()!="STM32F383VC")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x00 13. " SWRST ,Software reset" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 ti2cclk,2 ti2cclk,3 ti2cclk,4 ti2cclk,5 ti2cclk,6 ti2cclk,7 ti2cclk,8 ti2cclk,9 ti2cclk,10 ti2cclk,12 ti2cclk,12 ti2cclk,13 ti2cclk,14 ti2cclk,15 ti2cclk"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C1_CR1,Control Register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable (Device mode/host mode)" "Disabled/Not supported,Enabled/Supported"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus device default address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302VB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F302VC")&&(cpu()!="STM32F302RB")&&(cpu()!="STM32F302RC")&&(cpu()!="STM32F303RB")&&(cpu()!="STM32F303RC")&&(cpu()!="STM32F303CB")&&(cpu()!="STM32F303VB")&&(cpu()!="STM32F303CC")&&(cpu()!="STM32F303VC")&&(cpu()!="STM32F313CC")&&(cpu()!="STM32F313RC")&&(cpu()!="STM32F313VC")&&(cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372V8")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372VB")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F372VC")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373RB")&&(cpu()!="STM32F373VC")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373RC")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F373V8")&&(cpu()!="STM32F373R8")&&(cpu()!="STM32F373VB")&&(cpu()!="STM32F383CC")&&(cpu()!="STM32F383RC")&&(cpu()!="STM32F383VC")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x00 13. " SWRST ,Software reset" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 ti2cclk,2 ti2cclk,3 ti2cclk,4 ti2cclk,5 ti2cclk,6 ti2cclk,7 ti2cclk,8 ti2cclk,9 ti2cclk,10 ti2cclk,12 ti2cclk,12 ti2cclk,13 ti2cclk,14 ti2cclk,15 ti2cclk"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40005400+0x04))&0x2000)==0x2000)
|
|
if (((per.l(ad:0x40005400+0x04))&0x800)==0x800)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
textline " "
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No stop,Stop"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No start,Start/Restart"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
textline " "
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No stop,Stop"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No start,Start/Restart"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 1. " SADD[7:1] ,Slave address bit"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40005400+0x04))&0x800)==0x800)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
textline " "
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No stop,Stop"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No start,Start/Restart"
|
|
textline " "
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control Register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
textline " "
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No stop,Stop"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No start,Start/Restart"
|
|
textline " "
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 1. " SADD[7:1] ,Slave address bit"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40005400+0x08))&0x8000)==0x8000)
|
|
if (((per.l(ad:0x40005400+0x08))&0x400)==0x400)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C1_OAR1,Own Address 1 Register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA1[9:0] ,Interface address"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C1_OAR1,Own Address 1 Register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit"
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA1[7:1] ,Interface address"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40005400+0x08))&0x400)==0x400)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C1_OAR1,Own Address 1 Register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA1[9:0] ,Interface address"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C1_OAR1,Own Address 1 Register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit"
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA1[7:1] ,Interface address"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40005400+0x0C))&0x8000)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "I2C1_OAR2,Own Address 2 Register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--10. " OA2MSK ,Own address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA2 ,Interface address"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "I2C1_OAR2,Own Address 2 Register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " OA2MSK ,Own address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA2 ,Interface address"
|
|
endif
|
|
if (((per.l(ad:0x40005400))&0x01)==0x01)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C1_TIMINGR,Timing Register"
|
|
bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period"
|
|
else
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "I2C1_TIMINGR,Timing Register"
|
|
endif
|
|
if (((per.l(ad:0x40005400+0x14))&0x8000)==0x8000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C1_TIMEOUTR,Timeout Register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B"
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "Low timeout,High timeout"
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus timeout A"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C1_TIMEOUTR,Timeout Register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB ,Bus timeout B"
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "Low timeout,High timeout"
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA ,Bus timeout A"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "I2C1_ISR,Interrupt and Status Register"
|
|
hexmask.long.byte 0x00 17.--23. 0x02 " ADDCODE ,Address match code"
|
|
rbitfld.long 0x00 16. " DIR ,Transfer direction" "Write,Read"
|
|
rbitfld.long 0x00 15. " BUSY ,Bus busy" "Not busy,Busy"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " ALERT ,SMBus alert" "Not detected,Detected"
|
|
rbitfld.long 0x00 12. " TIMEOUT ,Timeout or tLOW detection flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 11. " PECERR ,PEC error in reception" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 9. " ARLO ,Arbitration lost" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 8. " BERR ,Bus error" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " TCR ,Transfer complete reload" "Not completed,Completed"
|
|
rbitfld.long 0x00 6. " TC ,Transfer complete" "Not completed,Completed"
|
|
rbitfld.long 0x00 5. " STOPF ,Stop detection flag" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " NACKF ,Not acknowledge received flag" "Not received,Received"
|
|
rbitfld.long 0x00 3. " ADDR ,Address matched" "Not matched,Matched"
|
|
rbitfld.long 0x00 2. " RXNE ,Receive data register not empty" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIS ,Transmit interrupt status" "Not empty,Empty"
|
|
bitfld.long 0x00 0. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "I2C1_ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 13. " ALERTCF ,Alert flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " TIMOUTCF ,Timeout detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 11. " PECCF ,PEC Error flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OVRCF ,Overrun/Underrun flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " ARLOCF ,Arbitration lost flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " NACKCF ,Not acknowledge flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " ADDRCF ,Address matched flag clear" "No effect,Clear"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "I2C1_PECR,PEC Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PEC ,Packet error checking register"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "I2C1_RXDR,Receive Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,8-bit receive data"
|
|
if (((per.l(ad:0x40005418))&0x01)==0x01)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "I2C1_TXDR,Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "I2C1_TXDR,Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("STM32F031*"))&&(!cpuis("STM32F042*"))&&(!cpuis("STM32F050G6"))&&(!cpuis("STM32F030F4"))&&(!cpuis("STM32F030K6"))&&(!cpuis("STM32F030C6"))&&(!cpuis("STM32F051K8"))&&!(cpuis("STM32F038?6")&&!cpuis("STM32F048*"))&&!cpuis("STM32F070C6")&&!cpuis("STM32F070F6")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
width 15.
|
|
if (((per.l(ad:0x40005800))&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C2_CR1,Control Register 1"
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302VB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F302VC")&&(cpu()!="STM32F302RB")&&(cpu()!="STM32F302RC")&&(cpu()!="STM32F303RB")&&(cpu()!="STM32F303RC")&&(cpu()!="STM32F303CB")&&(cpu()!="STM32F303VB")&&(cpu()!="STM32F303CC")&&(cpu()!="STM32F303VC")&&(cpu()!="STM32F313CC")&&(cpu()!="STM32F313RC")&&(cpu()!="STM32F313VC")&&(cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372V8")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372VB")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F372VC")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373RB")&&(cpu()!="STM32F373VC")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373RC")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F373V8")&&(cpu()!="STM32F373R8")&&(cpu()!="STM32F373VB")&&(cpu()!="STM32F383CC")&&(cpu()!="STM32F383RC")&&(cpu()!="STM32F383VC")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x00 13. " SWRST ,Software reset" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 ti2cclk,2 ti2cclk,3 ti2cclk,4 ti2cclk,5 ti2cclk,6 ti2cclk,7 ti2cclk,8 ti2cclk,9 ti2cclk,10 ti2cclk,12 ti2cclk,12 ti2cclk,13 ti2cclk,14 ti2cclk,15 ti2cclk"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C2_CR1,Control Register 1"
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302VB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F302VC")&&(cpu()!="STM32F302RB")&&(cpu()!="STM32F302RC")&&(cpu()!="STM32F303RB")&&(cpu()!="STM32F303RC")&&(cpu()!="STM32F303CB")&&(cpu()!="STM32F303VB")&&(cpu()!="STM32F303CC")&&(cpu()!="STM32F303VC")&&(cpu()!="STM32F313CC")&&(cpu()!="STM32F313RC")&&(cpu()!="STM32F313VC")&&(cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372V8")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372VB")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F372VC")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373RB")&&(cpu()!="STM32F373VC")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373RC")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F373V8")&&(cpu()!="STM32F373R8")&&(cpu()!="STM32F373VB")&&(cpu()!="STM32F383CC")&&(cpu()!="STM32F383RC")&&(cpu()!="STM32F383VC")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x00 13. " SWRST ,Software reset" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 ti2cclk,2 ti2cclk,3 ti2cclk,4 ti2cclk,5 ti2cclk,6 ti2cclk,7 ti2cclk,8 ti2cclk,9 ti2cclk,10 ti2cclk,12 ti2cclk,12 ti2cclk,13 ti2cclk,14 ti2cclk,15 ti2cclk"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXIE ,TX interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40005800+0x04))&0x2000)==0x2000)
|
|
if (((per.l(ad:0x40005800+0x04))&0x800)==0x800)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control Register 2"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No stop,Stop"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No start,Start/Restart"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control Register 2"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No stop,Stop"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No start,Start/Restart"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 1. " SADD[7:1] ,Slave address bit"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40005800+0x04))&0x800)==0x800)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control Register 2"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No stop,Stop"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No start,Start/Restart"
|
|
textline " "
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control Register 2"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No stop,Stop"
|
|
bitfld.long 0x00 13. " START ,Start generation" "No start,Start/Restart"
|
|
textline " "
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 1. " SADD[7:1] ,Slave address bit"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40005800+0x08))&0x8000)==0x8000)
|
|
if (((per.l(ad:0x40005800+0x08))&0x400)==0x400)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C2_OAR1,Own Address 1 Register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA1[9:0] ,Interface address"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C2_OAR1,Own Address 1 Register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit"
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA1[7:1] ,Interface address"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40005800+0x08))&0x400)==0x400)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C2_OAR1,Own Address 1 Register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit"
|
|
hexmask.long.word 0x00 0.--9. 1. " OA1[9:0] ,Interface address"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C2_OAR1,Own Address 1 Register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own address 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OA1MODE ,Own address 1 10-bit mode" "7-bit,10-bit"
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA1[7:1] ,Interface address"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40005800+0x0C))&0x8000)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "I2C2_OAR2,Own Address 2 Register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--10. " OA2MSK ,Own address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA2 ,Interface address"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "I2C2_OAR2,Own Address 2 Register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " OA2MSK ,Own address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA2 ,Interface address"
|
|
endif
|
|
if (((per.l(ad:0x40005800))&0x01)==0x01)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C2_TIMINGR,Timing Register"
|
|
bitfld.long 0x00 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH ,SCL high period"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,SCL low period"
|
|
else
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "I2C2_TIMINGR,Timing Register"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "I2C2_ISR,Interrupt and Status Register"
|
|
hexmask.long.byte 0x00 17.--23. 0x02 " ADDCODE ,Address match code"
|
|
rbitfld.long 0x00 16. " DIR ,Transfer direction" "Write,Read"
|
|
rbitfld.long 0x00 15. " BUSY ,Bus busy" "Not busy,Busy"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 9. " ARLO ,Arbitration lost" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 8. " BERR ,Bus error" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " TCR ,Transfer complete reload" "Not completed,Completed"
|
|
rbitfld.long 0x00 6. " TC ,Transfer complete" "Not completed,Completed"
|
|
rbitfld.long 0x00 5. " STOPF ,Stop detection flag" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " NACKF ,Not acknowledge received flag" "Not received,Received"
|
|
rbitfld.long 0x00 3. " ADDR ,Address matched" "Not matched,Matched"
|
|
rbitfld.long 0x00 2. " RXNE ,Receive data register not empty" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIS ,Transmit interrupt status" "Not empty,Empty"
|
|
bitfld.long 0x00 0. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "I2C2_ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 10. " OVRCF ,Overrun/Underrun flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " ARLOCF ,Arbitration lost flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " NACKCF ,Not acknowledge flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " ADDRCF ,Address matched flag clear" "No effect,Clear"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "I2C2_RXDR,Receive Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,8-bit receive data"
|
|
if (((per.l(ad:0x40005818))&0x01)==0x01)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "I2C2_TXDR,Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "I2C2_TXDR,Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091?B")||cpuis("STM32F091?C")||cpuis("STM32F098?C")||cpuis("STM32F031E6")||cpuis("STM32F051T8"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
tree "USART (Universal synchronous asynchronous receiver transmitter)"
|
|
sif (cpuis("STM32F038?6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F091?C"))||(cpuis("STM32F098?C")||cpuis("STM32F051T8")||cpuis("STM32F031E6"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
tree "USART1"
|
|
base ad:0x40013800
|
|
width 12.
|
|
if (((per.l(ad:0x40013800))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control Register 1"
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x00 28. 12. " M ,Word length" "1 start/8 data/n stop,1 start/9 data/n stop,1 start/7 data/n stop,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B")||cpuis("STM32F070F6")||cpuis("STM32F070C6"))
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 12. " M0 ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F058T8")||cpuis("STM32F051T8")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in stop mode" "Disabled,Enabled"
|
|
textline " "
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in stop mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40013800))&0x10001000)==0x1000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
if (((per.l(ad:0x40013800))&0x10001000)==0x1000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR[3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control Register 1"
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 28. 12. " M ,Word length" "1 start/8 data/n stop,1 start/9 data/n stop,1 start/7 data/n stop,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B")||cpuis("STM32F070F6")||cpuis("STM32F070C6"))
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 12. " M0 ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F058T8")||cpuis("STM32F051T8")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in stop mode" "Disabled,Enabled"
|
|
textline " "
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in stop mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40013800))&0x10001000)==0x1000)
|
|
if (((per.l(ad:0x40013800))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40013800))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40013800))&0x10001000)==0x1000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR[3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
if (((per.l(ad:0x40013800))&0x01)==0x00)
|
|
if (((per.l((ad:0x40013800+0x08)))&0x20)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC[7:0] ,Prescaler value"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC[4:0] ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40013800+0x08)))&0x20)==0x00)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC[7:0] ,Prescaler value"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC[4:0] ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
endif
|
|
else
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
if (((per.l(ad:0x40013800))&0x01)==0x00)
|
|
if (((per.l((ad:0x40013800+0x08)))&0x20)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40013800+0x08)))&0x20)==0x00)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
endif
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "USART_RQR,Request Register"
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "Not requested,Requested"
|
|
textline " "
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
elif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USART_ISR,Interrupt & Status Register"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag" "Not received,Received"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag" "Not received,Received"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not transmitted,Transmitted"
|
|
textline " "
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
textline " "
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||cpuis("STM32F070F6")||cpuis("STM32F070C6")
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "No flag,Flag"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "No flag,Flag"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "No flag,Flag"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "No end,End"
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "No end,End"
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "USART_ICR,Interrupt Flag Clear Register"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
textline " "
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "USART_RDR,Receive Data Register"
|
|
in
|
|
if (((per.l(ad:0x40013800+0x1C))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F091?C"))||(cpuis("STM32F098?C")||cpuis("STM32F051T8"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
tree "USART2"
|
|
base ad:0x40004400
|
|
width 12.
|
|
if (((per.l(ad:0x40004400))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control Register 1"
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x00 28. 12. " M ,Word length" "1 start/8 data/n stop,1 start/9 data/n stop,1 start/7 data/n stop,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B")||cpuis("STM32F070F6")||cpuis("STM32F070C6"))
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 12. " M0 ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F058T8")||cpuis("STM32F051T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in stop mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40004400))&0x10001000)==0x1000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
else
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
else
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
if (((per.l(ad:0x40004400))&0x10001000)==0x1000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
else
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
endif
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
else
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
else
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
else
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
else
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR[3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control Register 1"
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 28. 12. " M ,Word length" "1 start/8 data/n stop,1 start/9 data/n stop,1 start/7 data/n stop,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B")||cpuis("STM32F070F6")||cpuis("STM32F070C6"))
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 12. " M0 ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F058T8")||cpuis("STM32F051T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in stop mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40004400))&0x10001000)==0x1000)
|
|
if (((per.l(ad:0x40004400))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
else
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
else
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004400))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
else
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
else
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40004400))&0x10001000)==0x1000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
else
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
endif
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
else
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
else
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
else
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
else
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR[3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
if (((per.l(ad:0x40004400))&0x01)==0x00)
|
|
if (((per.l((ad:0x40004400+0x08)))&0x20)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40004400+0x08)))&0x20)==0x00)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
endif
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "USART_RQR,Request Register"
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
elif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
else
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USART_ISR,Interrupt & Status Register"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag" "Not received,Received"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not transmitted,Transmitted"
|
|
textline " "
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
else
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
textline " "
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||cpuis("STM32F070F6")||cpuis("STM32F070C6")
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "No flag,Flag"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "No flag,Flag"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "No end,End"
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "USART_ICR,Interrupt Flag Clear Register"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
else
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
textline " "
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "USART_RDR,Receive Data Register"
|
|
in
|
|
if (((per.l(ad:0x40004400+0x1C))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F091?C"))||(cpuis("STM32F098?C"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
tree "USART3"
|
|
base ad:0x40004800
|
|
width 12.
|
|
if (((per.l(ad:0x40004800))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control Register 1"
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x00 28. 12. " M ,Word length" "1 start/8 data/n stop,1 start/9 data/n stop,1 start/7 data/n stop,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B")||cpuis("STM32F070F6")||cpuis("STM32F070C6"))
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
else
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 12. " M0 ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F058T8")||cpuis("STM32F051T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in stop mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40004800))&0x10001000)==0x1000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
if (((per.l(ad:0x40004800))&0x10001000)==0x1000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
endif
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR[3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control Register 1"
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 28. 12. " M ,Word length" "1 start/8 data/n stop,1 start/9 data/n stop,1 start/7 data/n stop,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 27. " EOBIE ,End of block interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B")||cpuis("STM32F070F6")||cpuis("STM32F070C6"))
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
else
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 12. " M0 ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F058T8")||cpuis("STM32F051T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in stop mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40004800))&0x10001000)==0x1000)
|
|
if (((per.l(ad:0x40004800))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004800))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40004800))&0x10001000)==0x1000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
endif
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR[3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
if (((per.l(ad:0x40004800))&0x01)==0x00)
|
|
if (((per.l((ad:0x40004800+0x08)))&0x20)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40004800+0x08)))&0x20)==0x00)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
endif
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "USART_RQR,Request Register"
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
elif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USART_ISR,Interrupt & Status Register"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag" "Not received,Received"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not transmitted,Transmitted"
|
|
textline " "
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
textline " "
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||cpuis("STM32F070F6")||cpuis("STM32F070C6")
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "No flag,Flag"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
else
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "No flag,Flag"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "No end,End"
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "USART_ICR,Interrupt Flag Clear Register"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
textline " "
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
bitfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "USART_RDR,Receive Data Register"
|
|
in
|
|
if (((per.l(ad:0x40004800+0x1C))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART4"
|
|
base ad:0x40004C00
|
|
width 12.
|
|
if (((per.l(ad:0x40004C00))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control Register 1"
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x00 28. 12. " M ,Word length" "1 start/8 data/n stop,1 start/9 data/n stop,1 start/7 data/n stop,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B")||cpuis("STM32F070F6")||cpuis("STM32F070C6"))
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 12. " M0 ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F058T8")||cpuis("STM32F051T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40004C00))&0x10001000)==0x1000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
if (((per.l(ad:0x40004C00))&0x10001000)==0x1000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
endif
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control Register 1"
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 28. 12. " M ,Word length" "1 start/8 data/n stop,1 start/9 data/n stop,1 start/7 data/n stop,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B")||cpuis("STM32F070F6")||cpuis("STM32F070C6"))
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 12. " M0 ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F058T8")||cpuis("STM32F051T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40004C00))&0x10001000)==0x1000)
|
|
if (((per.l(ad:0x40004C00))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40004C00))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40004C00))&0x10001000)==0x1000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
endif
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
endif
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "USART_RQR,Request Register"
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
elif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
else
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USART_ISR,Interrupt & Status Register"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not transmitted,Transmitted"
|
|
textline " "
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
textline " "
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||cpuis("STM32F070F6")||cpuis("STM32F070C6")
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "No flag,Flag"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
else
|
|
endif
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "USART_ICR,Interrupt Flag Clear Register"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
textline " "
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "USART_RDR,Receive Data Register"
|
|
in
|
|
if (((per.l(ad:0x40004C00+0x1C))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F091?B"))||(cpuis("STM32F091?C"))||(cpuis("STM32F098?C"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
tree "USART5"
|
|
base ad:0x40005000
|
|
width 12.
|
|
if (((per.l(ad:0x40005000))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control Register 1"
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x00 28. 12. " M ,Word length" "1 start/8 data/n stop,1 start/9 data/n stop,1 start/7 data/n stop,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B")||cpuis("STM32F070F6")||cpuis("STM32F070C6"))
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 12. " M0 ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F058T8")||cpuis("STM32F051T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40005000))&0x10001000)==0x1000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
if (((per.l(ad:0x40005000))&0x10001000)==0x1000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
endif
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control Register 1"
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 28. 12. " M ,Word length" "1 start/8 data/n stop,1 start/9 data/n stop,1 start/7 data/n stop,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B")||cpuis("STM32F070F6")||cpuis("STM32F070C6"))
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 12. " M0 ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F058T8")||cpuis("STM32F051T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40005000))&0x10001000)==0x1000)
|
|
if (((per.l(ad:0x40005000))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40005000))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40005000))&0x10001000)==0x1000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
endif
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
endif
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "USART_RQR,Request Register"
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
elif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
else
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USART_ISR,Interrupt & Status Register"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not transmitted,Transmitted"
|
|
textline " "
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
textline " "
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||cpuis("STM32F070F6")||cpuis("STM32F070C6")
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "No flag,Flag"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
else
|
|
endif
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "USART_ICR,Interrupt Flag Clear Register"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
textline " "
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "USART_RDR,Receive Data Register"
|
|
in
|
|
if (((per.l(ad:0x40005000+0x1C))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART6"
|
|
base ad:0x40011400
|
|
width 12.
|
|
if (((per.l(ad:0x40011400))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control Register 1"
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x00 28. 12. " M ,Word length" "1 start/8 data/n stop,1 start/9 data/n stop,1 start/7 data/n stop,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B")||cpuis("STM32F070F6")||cpuis("STM32F070C6"))
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 12. " M0 ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F058T8")||cpuis("STM32F051T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40011400))&0x10001000)==0x1000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
if (((per.l(ad:0x40011400))&0x10001000)==0x1000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
endif
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control Register 1"
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 28. 12. " M ,Word length" "1 start/8 data/n stop,1 start/9 data/n stop,1 start/7 data/n stop,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B")||cpuis("STM32F070F6")||cpuis("STM32F070C6"))
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 12. " M0 ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F058T8")||cpuis("STM32F051T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40011400))&0x10001000)==0x1000)
|
|
if (((per.l(ad:0x40011400))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011400))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40011400))&0x10001000)==0x1000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
endif
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
endif
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "USART_RQR,Request Register"
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
elif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
else
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USART_ISR,Interrupt & Status Register"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not transmitted,Transmitted"
|
|
textline " "
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
textline " "
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||cpuis("STM32F070F6")||cpuis("STM32F070C6")
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "No flag,Flag"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
else
|
|
endif
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "USART_ICR,Interrupt Flag Clear Register"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
textline " "
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "USART_RDR,Receive Data Register"
|
|
in
|
|
if (((per.l(ad:0x40011400+0x1C))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")
|
|
tree "USART7"
|
|
base ad:0x40011800
|
|
width 12.
|
|
if (((per.l(ad:0x40011800))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control Register 1"
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x00 28. 12. " M ,Word length" "1 start/8 data/n stop,1 start/9 data/n stop,1 start/7 data/n stop,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B")||cpuis("STM32F070F6")||cpuis("STM32F070C6"))
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 12. " M0 ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F058T8")||cpuis("STM32F051T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40011800))&0x10001000)==0x1000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
if (((per.l(ad:0x40011800))&0x10001000)==0x1000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
endif
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control Register 1"
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 28. 12. " M ,Word length" "1 start/8 data/n stop,1 start/9 data/n stop,1 start/7 data/n stop,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B")||cpuis("STM32F070F6")||cpuis("STM32F070C6"))
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 12. " M0 ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F058T8")||cpuis("STM32F051T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40011800))&0x10001000)==0x1000)
|
|
if (((per.l(ad:0x40011800))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011800))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40011800))&0x10001000)==0x1000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
endif
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
endif
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "USART_RQR,Request Register"
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
elif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
else
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USART_ISR,Interrupt & Status Register"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not transmitted,Transmitted"
|
|
textline " "
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
textline " "
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||cpuis("STM32F070F6")||cpuis("STM32F070C6")
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "No flag,Flag"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
else
|
|
endif
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "USART_ICR,Interrupt Flag Clear Register"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
textline " "
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "USART_RDR,Receive Data Register"
|
|
in
|
|
if (((per.l(ad:0x40011800+0x1C))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART8"
|
|
base ad:0x40011C00
|
|
width 12.
|
|
if (((per.l(ad:0x40011C00))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control Register 1"
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
bitfld.long 0x00 28. 12. " M ,Word length" "1 start/8 data/n stop,1 start/9 data/n stop,1 start/7 data/n stop,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B")||cpuis("STM32F070F6")||cpuis("STM32F070C6"))
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 12. " M0 ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F058T8")||cpuis("STM32F051T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40011C00))&0x10001000)==0x1000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
if (((per.l(ad:0x40011C00))&0x10001000)==0x1000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
endif
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control Register 1"
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 28. 12. " M ,Word length" "1 start/8 data/n stop,1 start/9 data/n stop,1 start/7 data/n stop,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B")||cpuis("STM32F070F6")||cpuis("STM32F070C6"))
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
rbitfld.long 0x00 12. " M0 ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F058T8")||cpuis("STM32F051T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40011C00))&0x10001000)==0x1000)
|
|
if (((per.l(ad:0x40011C00))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40011C00))&0x04)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
bitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control Register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")||cpuis("STM32F048?6")||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||cpuis("STM32F078?B")
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Detect the baud rate,Falling edge,0x7f frame detection,0x55 frame detection"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
rbitfld.long 0x00 4. " ADDM7 ,7-bit address Detection/4-bit address detection" "4-bit,7-bit"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40011C00))&0x10001000)==0x1000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
endif
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control Register 3"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " DDRE ,DMA disable on reception error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
rbitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud Rate Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "USART_GTPR,Guard Time and Prescaler Register"
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "USART_RTOR,Receiver Timeout Register"
|
|
endif
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "USART_RQR,Request Register"
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
elif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
else
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USART_ISR,Interrupt & Status Register"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not transmitted,Transmitted"
|
|
textline " "
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
sif cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from mute mode" "Active mode,Mute mode"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
textline " "
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||cpuis("STM32F070F6")||cpuis("STM32F070C6")
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "No flag,Flag"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F070RB")
|
|
else
|
|
endif
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
else
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed"
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "USART_ICR,Interrupt Flag Clear Register"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (cpuis("STM32F048?6"))||(cpuis("STM32F051*"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
textline " "
|
|
sif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
elif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F070RB")||cpuis("STM32F070CB")
|
|
else
|
|
endif
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
elif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
else
|
|
endif
|
|
endif
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "USART_RDR,Receive Data Register"
|
|
in
|
|
if (((per.l(ad:0x40011C00+0x1C))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree.end
|
|
elif (cpuis("STM32F030?4"))||(cpuis("STM32F030?6"))||(cpuis("STM32F030?8"))||(cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))||(cpuis("STM32F050G6"))
|
|
tree "USART (Universal synchronous asynchronous receiver transmitter)"
|
|
tree "USART1"
|
|
base ad:0x40013800
|
|
width 11.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CR1,Control register 1"
|
|
sif cpuis("STM32F030*")
|
|
bitfld.long 0x00 28. 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop,1 Start/7 Data/n Stop,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
bitfld.long 0x00 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))
|
|
bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
line.long 0x04 "USART_CR2,Control register 2"
|
|
bitfld.long 0x04 31. " ADD[7:0] ,Address of the USART node 7" "0,1"
|
|
bitfld.long 0x04 30. ",Address of the USART node 6" "0,1"
|
|
bitfld.long 0x04 29. ",Address of the USART node 5" "0,1"
|
|
bitfld.long 0x04 28. ",Address of the USART node 4" "0,1"
|
|
bitfld.long 0x04 27. ",Address of the USART node 3" "0,1"
|
|
bitfld.long 0x04 26. ",Address of the USART node 2" "0,1"
|
|
bitfld.long 0x04 25. ",Address of the USART node 1" "0,1"
|
|
bitfld.long 0x04 24. ",Address of the USART node 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F050G6"))
|
|
bitfld.long 0x04 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x04 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
bitfld.long 0x04 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
bitfld.long 0x04 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x04 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " CPOL ,Clock polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x04 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
bitfld.long 0x04 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x04 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
line.long 0x08 "USART_CR3,Control register 3"
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
bitfld.long 0x08 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Inhibited,Generated"
|
|
bitfld.long 0x08 20.--21. " WUS[1:0] ,Wakeup from Stop mode interrupt flag selection" "Activated on address match,,Activated on Start bit detection,Activated on RXNE"
|
|
textline " "
|
|
bitfld.long 0x08 17.--19. " SCARCNT[2:0] ,Smartcard auto-retry count" "Disabled,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x08 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " DDRE ,DMA Disable on Reception Error" "No,Yes"
|
|
bitfld.long 0x08 12. " OVRDIS ,Overrun Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x08 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
bitfld.long 0x08 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x08 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
bitfld.long 0x08 2. " IRLP ,IrDA Power mode" "Normal,Low-power"
|
|
bitfld.long 0x08 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x08 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
if (((per.l((ad:0x40013800+0x0)))&0x8001)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40013800+0x0)))&0x8001)==0x8001)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40013800+0x0)))&0x8001)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " GT[7:0] ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " PSC[7:0] ,Prescaler value"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver timeout register"
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " BLEN[7:0] ,Block Length"
|
|
textline " "
|
|
endif
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "USART_RQR,Request register"
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USART_ISR,Interrupt & status register"
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag " "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from Mute mode" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Not set,Set"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "Not reached,Reached"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
textline " "
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "USART_ICR,Interrupt flag clear register"
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "Not affected,Cleared"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Cleared"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))
|
|
bitfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "Not affected,Cleared"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Cleared"
|
|
textline " "
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Cleared"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "Not affected,Cleared"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Cleared"
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Cleared"
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Cleared"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RDR,Receive data register"
|
|
hexmask.long.word 0x00 0.--8. 0x01 " RDR[8:0] ,Receive data vslue"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit data register"
|
|
hexmask.long.word 0x00 0.--8. 0x01 " TDR ,Transmit data value"
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("STM32F031*"))&&(!cpuis("STM32F050G6"))&&(!cpuis("STM32F030F4"))&&(!cpuis("STM32F030K6"))&&(!cpuis("STM32F030C6"))
|
|
tree "USART2"
|
|
base ad:0x40004400
|
|
width 11.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CR1,Control register 1"
|
|
sif cpuis("STM32F030*")
|
|
bitfld.long 0x00 28. 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop,1 Start/7 Data/n Stop,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
bitfld.long 0x00 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
line.long 0x04 "USART_CR2,Control register 2"
|
|
bitfld.long 0x04 31. " ADD[7:0] ,Address of the USART node 7" "0,1"
|
|
bitfld.long 0x04 30. ",Address of the USART node 6" "0,1"
|
|
bitfld.long 0x04 29. ",Address of the USART node 5" "0,1"
|
|
bitfld.long 0x04 28. ",Address of the USART node 4" "0,1"
|
|
bitfld.long 0x04 27. ",Address of the USART node 3" "0,1"
|
|
bitfld.long 0x04 26. ",Address of the USART node 2" "0,1"
|
|
bitfld.long 0x04 25. ",Address of the USART node 1" "0,1"
|
|
bitfld.long 0x04 24. ",Address of the USART node 0" "0,1"
|
|
textline " "
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
bitfld.long 0x04 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
bitfld.long 0x04 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
bitfld.long 0x04 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
bitfld.long 0x04 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " CPOL ,Clock polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x04 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
bitfld.long 0x04 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
line.long 0x08 "USART_CR3,Control register 3"
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
bitfld.long 0x08 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x08 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " DDRE ,DMA Disable on Reception Error" "No,Yes"
|
|
bitfld.long 0x08 12. " OVRDIS ,Overrun Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x08 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
bitfld.long 0x08 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
bitfld.long 0x08 2. " IRLP ,IrDA Power mode" "Normal,Low-power"
|
|
bitfld.long 0x08 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
if (((per.l((ad:0x40004400+0x0)))&0x8001)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40004400+0x0)))&0x8001)==0x8001)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40004400+0x0)))&0x8001)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver timeout register"
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " BLEN[7:0] ,Block Length"
|
|
textline " "
|
|
endif
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "USART_RQR,Request register"
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USART_ISR,Interrupt & status register"
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag " "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from Mute mode" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
textline " "
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Not set,Set"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "Not reached,Reached"
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "USART_ICR,Interrupt flag clear register"
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "Not affected,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Cleared"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
bitfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "Not affected,Cleared"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Cleared"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "Not affected,Cleared"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Cleared"
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Cleared"
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Cleared"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RDR,Receive data register"
|
|
hexmask.long.word 0x00 0.--8. 0x01 " RDR[8:0] ,Receive data vslue"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit data register"
|
|
hexmask.long.word 0x00 0.--8. 0x01 " TDR ,Transmit data value"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F071*"))||(cpuis("STM32F072*"))
|
|
tree "USART3"
|
|
base ad:0x40004800
|
|
width 11.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CR1,Control register 1"
|
|
sif cpuis("STM32F030*")
|
|
bitfld.long 0x00 28. 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop,1 Start/7 Data/n Stop,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
bitfld.long 0x00 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
line.long 0x04 "USART_CR2,Control register 2"
|
|
bitfld.long 0x04 31. " ADD[7:0] ,Address of the USART node 7" "0,1"
|
|
bitfld.long 0x04 30. ",Address of the USART node 6" "0,1"
|
|
bitfld.long 0x04 29. ",Address of the USART node 5" "0,1"
|
|
bitfld.long 0x04 28. ",Address of the USART node 4" "0,1"
|
|
bitfld.long 0x04 27. ",Address of the USART node 3" "0,1"
|
|
bitfld.long 0x04 26. ",Address of the USART node 2" "0,1"
|
|
bitfld.long 0x04 25. ",Address of the USART node 1" "0,1"
|
|
bitfld.long 0x04 24. ",Address of the USART node 0" "0,1"
|
|
textline " "
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x04 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
bitfld.long 0x04 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x04 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " CPOL ,Clock polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x04 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x04 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
line.long 0x08 "USART_CR3,Control register 3"
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
bitfld.long 0x08 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x08 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " DDRE ,DMA Disable on Reception Error" "No,Yes"
|
|
bitfld.long 0x08 12. " OVRDIS ,Overrun Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x08 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x08 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x08 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
if (((per.l((ad:0x40004400+0x0)))&0x8001)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40004400+0x0)))&0x8001)==0x8001)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40004400+0x0)))&0x8001)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver timeout register"
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " BLEN[7:0] ,Block Length"
|
|
textline " "
|
|
endif
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "USART_RQR,Request register"
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USART_ISR,Interrupt & status register"
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from Mute mode" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
textline " "
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "USART_ICR,Interrupt flag clear register"
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Cleared"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Cleared"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Cleared"
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Cleared"
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Cleared"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RDR,Receive data register"
|
|
hexmask.long.word 0x00 0.--8. 0x01 " RDR[8:0] ,Receive data vslue"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit data register"
|
|
hexmask.long.word 0x00 0.--8. 0x01 " TDR ,Transmit data value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART4"
|
|
base ad:0x40004C00
|
|
width 11.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CR1,Control register 1"
|
|
sif cpuis("STM32F030*")
|
|
bitfld.long 0x00 28. 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop,1 Start/7 Data/n Stop,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
bitfld.long 0x00 12. " M ,Word length" "1 Start/8 Data/n Stop,1 Start/9 Data/n Stop"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
line.long 0x04 "USART_CR2,Control register 2"
|
|
bitfld.long 0x04 31. " ADD[7:0] ,Address of the USART node 7" "0,1"
|
|
bitfld.long 0x04 30. ",Address of the USART node 6" "0,1"
|
|
bitfld.long 0x04 29. ",Address of the USART node 5" "0,1"
|
|
bitfld.long 0x04 28. ",Address of the USART node 4" "0,1"
|
|
bitfld.long 0x04 27. ",Address of the USART node 3" "0,1"
|
|
bitfld.long 0x04 26. ",Address of the USART node 2" "0,1"
|
|
bitfld.long 0x04 25. ",Address of the USART node 1" "0,1"
|
|
bitfld.long 0x04 24. ",Address of the USART node 0" "0,1"
|
|
textline " "
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x04 19. " MSBFIRST ,Most significant bit first" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
bitfld.long 0x04 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x04 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " CPOL ,Clock polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x04 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x04 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
line.long 0x08 "USART_CR3,Control register 3"
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
bitfld.long 0x08 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x08 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " DDRE ,DMA Disable on Reception Error" "No,Yes"
|
|
bitfld.long 0x08 12. " OVRDIS ,Overrun Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x08 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x08 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x08 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
if (((per.l((ad:0x40004400+0x0)))&0x8001)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40004400+0x0)))&0x8001)==0x8001)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40004400+0x0)))&0x8001)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver timeout register"
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
hexmask.long.byte 0x00 24.--31. 0x01 " BLEN[7:0] ,Block Length"
|
|
textline " "
|
|
endif
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "USART_RQR,Request register"
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested"
|
|
textline " "
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USART_ISR,Interrupt & status register"
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from Mute mode" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
textline " "
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "USART_ICR,Interrupt flag clear register"
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Cleared"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Cleared"
|
|
textline " "
|
|
sif (cpuis("STM32F031*"))||(cpuis("STM32F042*"))||(cpuis("STM32F071*"))||(cpuis("STM32F072*"))||(cpuis("STM32F050G6"))
|
|
endif
|
|
sif cpuis("STM32F071*")||cpuis("STM32F072*")
|
|
endif
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Cleared"
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Cleared"
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Cleared"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "RDR,Receive data register"
|
|
hexmask.long.word 0x00 0.--8. 0x01 " RDR[8:0] ,Receive data vslue"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit data register"
|
|
hexmask.long.word 0x00 0.--8. 0x01 " TDR ,Transmit data value"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
else
|
|
tree "USART (Universal synchronous asynchronous receiver transmitter)"
|
|
tree "USART1"
|
|
base ad:0x40013800
|
|
width 12.
|
|
if (((per.l(ad:0x40013800))&0x1)==0x0)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21.--25. " DEAT[4:0] ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT[4:0] ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
line.long 0x04 "USART_CR2,Control register 2"
|
|
bitfld.long 0x04 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21.--22. " ABRMOD[1:0] ,Auto baud rate mode" "Start bit,Falling edge,?..."
|
|
textline " "
|
|
bitfld.long 0x04 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x04 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
bitfld.long 0x04 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x04 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " STOP[1:0] ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
bitfld.long 0x04 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x04 9. " CPHA ,Clock phase" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x04 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x04 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
line.long 0x08 "USART_CR3,Control register 3"
|
|
bitfld.long 0x08 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20.--21. " WUS[1:0] ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
textline " "
|
|
bitfld.long 0x08 17.--19. " SCARCNT[2:0] ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x08 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " DDRE ,DMA Disable on Reception Error" "No,Yes"
|
|
bitfld.long 0x08 12. " OVRDIS ,Overrun Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x08 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x08 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
bitfld.long 0x08 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR[3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 21.--25. " DEAT[4:0] ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT[4:0] ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " M ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
line.long 0x04 "USART_CR2,Control register 2"
|
|
rbitfld.long 0x04 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 21.--22. " ABRMOD[1:0] ,Auto baud rate mode" "Start bit,Falling edge,?..."
|
|
textline " "
|
|
bitfld.long 0x04 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x04 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
rbitfld.long 0x04 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x04 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x04 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
rbitfld.long 0x04 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 12.--13. " STOP[1:0] ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
rbitfld.long 0x04 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x04 9. " CPHA ,Clock phase" "First,Second"
|
|
textline " "
|
|
rbitfld.long 0x04 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x04 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x04 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
textline " "
|
|
rbitfld.long 0x04 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
line.long 0x08 "USART_CR3,Control register 3"
|
|
bitfld.long 0x08 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x08 20.--21. " WUS[1:0] ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
textline " "
|
|
bitfld.long 0x08 17.--19. " SCARCNT[2:0] ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
rbitfld.long 0x08 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x08 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x08 13. " DDRE ,DMA Disable on Reception Error" "No,Yes"
|
|
rbitfld.long 0x08 12. " OVRDIS ,Overrun Disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x08 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
bitfld.long 0x08 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x08 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x08 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x08 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x08 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x08 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
rbitfld.long 0x08 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
rbitfld.long 0x08 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR[15:4] ,BRR[15:4]"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BRR[3:0] ,BRR[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l(ad:0x40013800))&0x1)==0x0)
|
|
if (((per.l((ad:0x40013800+0x08)))&0x20)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT[7:0] ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC[7:0] ,Prescaler value"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT[7:0] ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC[4:0] ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40013800+0x08)))&0x20)==0x00)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT[7:0] ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC[7:0] ,Prescaler value"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT[7:0] ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC[4:0] ,Prescaler value" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BLEN[7:0] ,Block Length "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO[23:0] ,Receiver timeout value"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "USART_RQR,Request register"
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USART_ISR,Interrupt & status register"
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag " "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected"
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from Mute mode" "Active mode,Mute mode"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "No flag,Flag"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "No end,End"
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "USART_ICR,Interrupt flag clear register"
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "Not cleared,Cleared"
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "Not cleared,Cleared"
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "Not cleared,Cleared"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "USART_RDR,Receive data register"
|
|
in
|
|
if (((per.l(ad:0x40013800))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit data register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR[8:0] ,Transmit data value"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit data register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR[8:0] ,Transmit data value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")
|
|
tree "USART2"
|
|
base ad:0x40004400
|
|
width 12.
|
|
if (((per.l(ad:0x40004400))&0x1)==0x0)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
bitfld.long 0x00 21.--25. " DEAT[4:0] ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT[4:0] ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " M ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
line.long 0x04 "USART_CR2,Control register 2"
|
|
bitfld.long 0x04 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x04 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
bitfld.long 0x04 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x04 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " STOP[1:0] ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
bitfld.long 0x04 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " CPOL ,Clock polarity" "Low,High"
|
|
bitfld.long 0x04 9. " CPHA ,Clock phase" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x04 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
line.long 0x08 "USART_CR3,Control register 3"
|
|
bitfld.long 0x08 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x08 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " DDRE ,DMA Disable on Reception Error" "No,Yes"
|
|
bitfld.long 0x08 12. " OVRDIS ,Overrun Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
bitfld.long 0x08 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x08 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
rbitfld.long 0x00 21.--25. " DEAT[4:0] ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT[4:0] ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " M ,Word length" "8 data bits,9 data bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXEIE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
line.long 0x04 "USART_CR2,Control register 2"
|
|
rbitfld.long 0x04 28.--31. " ADD[7:4] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x04 24.--27. " ADD[3:0] ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
rbitfld.long 0x04 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x04 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
textline " "
|
|
rbitfld.long 0x04 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x04 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x04 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
textline " "
|
|
rbitfld.long 0x04 12.--13. " STOP[1:0] ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
rbitfld.long 0x04 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 10. " CPOL ,Clock polarity" "Low,High"
|
|
rbitfld.long 0x04 9. " CPHA ,Clock phase" "First,Second"
|
|
textline " "
|
|
rbitfld.long 0x04 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
line.long 0x08 "USART_CR3,Control register 3"
|
|
rbitfld.long 0x08 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x08 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x08 13. " DDRE ,DMA Disable on Reception Error" "No,Yes"
|
|
rbitfld.long 0x08 12. " OVRDIS ,Overrun Disable" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x08 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
bitfld.long 0x08 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x08 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x08 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x08 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x08 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "USART_RTOR,Receiver timeout register"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "USART_RQR,Request register"
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested"
|
|
textline " "
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USART_ISR,Interrupt & status register"
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not complete,Complete"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "USART_ICR,Interrupt flag clear register"
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "Not cleared,Cleared"
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "Not cleared,Cleared"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "USART_RDR,Receive data register"
|
|
in
|
|
if (((per.l(ad:0x40004400))&0x80)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit data register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR[8:0] ,Transmit data value"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit data register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR[8:0] ,Transmit data value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
tree "SPI (Serial peripheral interface)"
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
width 12.
|
|
if (((per.l(ad:0x40013000))&0x40)==0x40)
|
|
if ((per.w((ad:0x40013000+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
rbitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
line.word 0x02 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
rbitfld.word 0x02 3. " NSSP ,NSS pulse management" "No NSS,NSS"
|
|
bitfld.word 0x02 2. " SSOE ,SS Output enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx Buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
line.word 0x02 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.w((ad:0x40013000+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
line.word 0x02 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
bitfld.word 0x02 3. " NSSP ,NSS pulse management" "No NSS,NSS"
|
|
bitfld.word 0x02 2. " SSOE ,SS Output enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
line.word 0x02 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI Status Register"
|
|
bitfld.word 0x00 11.--12. " FTLVL[1:0] ,FIFO transmission level" "Empty,1/4 FIFO,1/2 FIFO,FULL"
|
|
bitfld.word 0x00 9.--10. " FRLVL[1:0] ,FIFO reception level" "Empty,1/4 FIFO,1/2 FIFO,FULL"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "No error,Error"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI Data Register"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC Polynomial Register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC Register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC Register"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("STM32F030?C")||cpuis("STM32F070?B")
|
|
tree "SPI2"
|
|
base ad:0x40003800
|
|
width 12.
|
|
if (((per.l(ad:0x40003800))&0x40)==0x40)
|
|
if ((per.w((ad:0x40003800+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
rbitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
line.word 0x02 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
rbitfld.word 0x02 3. " NSSP ,NSS pulse management" "No NSS,NSS"
|
|
bitfld.word 0x02 2. " SSOE ,SS Output enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx Buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
line.word 0x02 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.w((ad:0x40003800+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
line.word 0x02 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
bitfld.word 0x02 3. " NSSP ,NSS pulse management" "No NSS,NSS"
|
|
bitfld.word 0x02 2. " SSOE ,SS Output enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
line.word 0x02 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI Status Register"
|
|
bitfld.word 0x00 11.--12. " FTLVL[1:0] ,FIFO transmission level" "Empty,1/4 FIFO,1/2 FIFO,FULL"
|
|
bitfld.word 0x00 9.--10. " FRLVL[1:0] ,FIFO reception level" "Empty,1/4 FIFO,1/2 FIFO,FULL"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "No error,Error"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI Data Register"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC Polynomial Register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC Register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC Register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
else
|
|
tree "SPI/I2S (Serial peripheral interface/inter-IC sound)"
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")||cpuis("STM32F051T8")
|
|
tree "SPI1/I2S1"
|
|
base ad:0x40013000
|
|
width 13.
|
|
if ((((per.w(ad:0x40013000+0x1C))&0x800)==0x00)&&(((per.w(ad:0x40013000+0x04))&0x10)==0x10))
|
|
if (((per.w(ad:0x40013000))&0x40)==0x40)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
endif
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x00)
|
|
if (((per.w(ad:0x40013000))&0x40)==0x40)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock,First data"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock,First data"
|
|
endif
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x800)
|
|
hgroup.word 0x00++0x01
|
|
hide.word 0x00 "SPI_CR1,SPI control register 1"
|
|
endif
|
|
if ((((per.w(ad:0x40013000+0x1C))&0x800)==0x00)&&(((per.w((ad:0x40013000+0x04)))&0x10)==0x10))
|
|
if (((per.w(ad:0x40013000))&0x40)==0x40)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x00)
|
|
if (((per.w(ad:0x40013000))&0x40)==0x40)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x800)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " UDR ,Under-run flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SPI_DR,SPI SATA register"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
if (((per.w(ad:0x40013000+0x1C))&0x800)==0x00)
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
else
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
endif
|
|
if (((per.w(ad:0x40013000+0x1C))&0x800)==0x800)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave - transmit,Slave - receive,Master - transmit,Master - receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "Philips,MSB,LSB,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High"
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,?..."
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length" "16-bit,32-bit"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master clock output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,I2SDIV * 2+1"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S linear prescaler"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
hgroup.word 0x20++0x01
|
|
hide.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (CPU()=="STM32F051C8"||CPU()=="STM32F051R8")
|
|
tree "SPI2"
|
|
base ad:0x40003800
|
|
width 13.
|
|
if ((((per.w(ad:0x40003800+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40003800+0x04))&0x10)==0x10))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x000)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock,First data"
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x800)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
endif
|
|
if ((((per.w(ad:0x40003800+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40003800+0x04))&0x10)==0x10))
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x000)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x800)
|
|
hgroup.word 0x04++0x1
|
|
hide.word 0x00 "SPI_CR2,SPI Control Register 2"
|
|
endif
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI Status Register"
|
|
bitfld.word 0x00 11.--12. " FTLVL ,FIFO Transmission Level" "Empty,1/4,1/2,Full"
|
|
bitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI Data Register"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC Polynomial Register"
|
|
if (((per.w((ad:0x40003800+0x1C)))&0x800)==0x000)
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC Register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC Register"
|
|
else
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC Register"
|
|
hexmask.word 0x00 0.--15. 1. " RXCRC ,Rx CRC Register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x00 0.--15. 1. " TxCRC ,Tx CRC Register"
|
|
endif
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPIx_I2S Configuration Register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
elif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6")
|
|
tree "SPI1/I2S1"
|
|
base ad:0x40013000
|
|
width 13.
|
|
if ((((per.w(ad:0x40013000+0x1C))&0x800)==0x00)&&(((per.w(ad:0x40013000+0x04))&0x10)==0x10))
|
|
if (((per.w(ad:0x40013000))&0x40)==0x40)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
endif
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x00)
|
|
if (((per.w(ad:0x40013000))&0x40)==0x40)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock,First data"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock,First data"
|
|
endif
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x800)
|
|
hgroup.word 0x00++0x01
|
|
hide.word 0x00 "SPI_CR1,SPI control register 1"
|
|
endif
|
|
if ((((per.w(ad:0x40013000+0x1C))&0x800)==0x00)&&(((per.w((ad:0x40013000+0x04)))&0x10)==0x10))
|
|
if (((per.w(ad:0x40013000))&0x40)==0x40)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x00)
|
|
if (((per.w(ad:0x40013000))&0x40)==0x40)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x800)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " UDR ,Under-run flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SPI_DR,SPI SATA register"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
if (((per.w(ad:0x40013000+0x1C))&0x800)==0x00)
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
else
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
endif
|
|
if (((per.w(ad:0x40013000+0x1C))&0x800)==0x800)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave - transmit,Slave - receive,Master - transmit,Master - receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "Philips,MSB,LSB,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High"
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,?..."
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length" "16-bit,32-bit"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master clock output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,I2SDIV * 2+1"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S linear prescaler"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
hgroup.word 0x20++0x01
|
|
hide.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
elif (cpuis("STM32F030?4")||cpuis("STM32F030?6")||cpuis("STM32F030?8"))
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
width 12.
|
|
if (((per.l(ad:0x40013000))&0x40)==0x40)
|
|
if ((per.w((ad:0x40013000+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
rbitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
line.word 0x02 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
rbitfld.word 0x02 3. " NSSP ,NSS pulse management" "No NSS,NSS"
|
|
bitfld.word 0x02 2. " SSOE ,SS Output enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx Buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
line.word 0x02 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.w((ad:0x40013000+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
line.word 0x02 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
bitfld.word 0x02 3. " NSSP ,NSS pulse management" "No NSS,NSS"
|
|
bitfld.word 0x02 2. " SSOE ,SS Output enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
line.word 0x02 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI Status Register"
|
|
bitfld.word 0x00 11.--12. " FTLVL[1:0] ,FIFO transmission level" "Empty,1/4 FIFO,1/2 FIFO,FULL"
|
|
bitfld.word 0x00 9.--10. " FRLVL[1:0] ,FIFO reception level" "Empty,1/4 FIFO,1/2 FIFO,FULL"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "No error,Error"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI Data Register"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC Polynomial Register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC Register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC Register"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("STM32F030?8")
|
|
tree "SPI2"
|
|
base ad:0x40003800
|
|
width 12.
|
|
if (((per.l(ad:0x40003800))&0x40)==0x40)
|
|
if ((per.w((ad:0x40003800+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
rbitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
line.word 0x02 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
rbitfld.word 0x02 3. " NSSP ,NSS pulse management" "No NSS,NSS"
|
|
bitfld.word 0x02 2. " SSOE ,SS Output enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx Buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
line.word 0x02 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.w((ad:0x40003800+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
line.word 0x02 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
bitfld.word 0x02 3. " NSSP ,NSS pulse management" "No NSS,NSS"
|
|
bitfld.word 0x02 2. " SSOE ,SS Output enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
line.word 0x02 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI Status Register"
|
|
bitfld.word 0x00 11.--12. " FTLVL[1:0] ,FIFO transmission level" "Empty,1/4 FIFO,1/2 FIFO,FULL"
|
|
bitfld.word 0x00 9.--10. " FRLVL[1:0] ,FIFO reception level" "Empty,1/4 FIFO,1/2 FIFO,FULL"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "No error,Error"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI Data Register"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC Polynomial Register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC Register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC Register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
elif (cpuis("STM32F031*"))||(cpuis("STM32F071*"))||(cpuis("STM32F050G6"))||cpuis("STM32F091RC")
|
|
tree "SPI1/I2S1"
|
|
base ad:0x40013000
|
|
width 13.
|
|
if (((per.w(ad:0x40013000+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40013000+0x04))&0x10)==0x10)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40013000+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock,First data"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x800)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "SPI_CR1,SPI control register 1"
|
|
endif
|
|
if ((((per.w(ad:0x40013000+0x1C))&0x800)==0x000)&&(((per.w((ad:0x40013000+0x04)))&0x10)==0x10))
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS[3:0] ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x00 11.--12. " FTLVL[1:0] ,FIFO Transmission Level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 9.--10. " FRLVL[1:0] ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40013000+0x04))&0x10)==0x00)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS[3:0] ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
rgroup.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
bitfld.word 0x00 11.--12. " FTLVL[1:0] ,FIFO Transmission Level" "Empty,1/4,1/2,Full"
|
|
bitfld.word 0x00 9.--10. " FRLVL[1:0] ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x800)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
rgroup.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
endif
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
hexmask.word 0x00 0.--15. 1. " DR[15:0] ,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x00 0.--15. 1. " CRCPOLY[15:0] ,CRC polynomial register"
|
|
if (((per.w(ad:0x40013000+0x1C))&0x800)==0x000)
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x00 0.--15. 1. " RXCRC[15:0] ,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x00 0.--15. 1. " TxCRC[15:0] ,Tx CRC register"
|
|
else
|
|
hgroup.word 0x14++0x1
|
|
hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hgroup.word 0x18++0x1
|
|
hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
endif
|
|
if (((per.w(ad:0x40013000+0x1C))&0x800)==0x800)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave - transmit,Slave - receive,Master - transmit,Master - receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "Philips,MSB,LSB,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High"
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,"
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length" "16-bit,32-bit"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master clock output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,I2SDIV * 2+1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S linear prescaler"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
hgroup.word 0x20++0x1
|
|
hide.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("STM32F071*"))||cpuis("STM32F091RC")
|
|
tree "SPI2/I2S2"
|
|
base ad:0x40003800
|
|
width 13.
|
|
if (((per.w(ad:0x40003800+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40003800+0x04))&0x10)==0x10)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40003800+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock,First data"
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x800)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "SPI_CR1,SPI control register 1"
|
|
endif
|
|
if ((((per.w(ad:0x40003800+0x1C))&0x800)==0x000)&&(((per.w((ad:0x40003800+0x04)))&0x10)==0x10))
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS[3:0] ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x00 11.--12. " FTLVL[1:0] ,FIFO Transmission Level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 9.--10. " FRLVL[1:0] ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40003800+0x04))&0x10)==0x00)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS[3:0] ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
rgroup.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
bitfld.word 0x00 11.--12. " FTLVL[1:0] ,FIFO Transmission Level" "Empty,1/4,1/2,Full"
|
|
bitfld.word 0x00 9.--10. " FRLVL[1:0] ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x800)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
rgroup.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
endif
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
hexmask.word 0x00 0.--15. 1. " DR[15:0] ,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x00 0.--15. 1. " CRCPOLY[15:0] ,CRC polynomial register"
|
|
if (((per.w(ad:0x40003800+0x1C))&0x800)==0x000)
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x00 0.--15. 1. " RXCRC[15:0] ,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x00 0.--15. 1. " TxCRC[15:0] ,Tx CRC register"
|
|
else
|
|
hgroup.word 0x14++0x1
|
|
hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hgroup.word 0x18++0x1
|
|
hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
endif
|
|
if (((per.w(ad:0x40003800+0x1C))&0x800)==0x800)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave - transmit,Slave - receive,Master - transmit,Master - receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "Philips,MSB,LSB,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High"
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,"
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length" "16-bit,32-bit"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master clock output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,I2SDIV * 2+1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S linear prescaler"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
hgroup.word 0x20++0x1
|
|
hide.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
elif ((cpuis("STM32F042*"))||(cpuis("STM32F072*"))||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||(cpuis("STM32F091*")&&(!cpuis("STM32F091RC"))||cpuis("STM32F098*")||cpuis("STM32F031E6")))
|
|
tree "SPI1/I2S1"
|
|
base ad:0x40013000
|
|
width 13.
|
|
if (((per.w(ad:0x40013000+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40013000+0x04))&0x10)==0x10)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40013000+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock,First data"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x800)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "SPI_CR1,SPI control register 1"
|
|
endif
|
|
if ((((per.w(ad:0x40013000+0x1C))&0x800)==0x000)&&(((per.w((ad:0x40013000+0x04)))&0x10)==0x10))
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS[3:0] ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x00 11.--12. " FTLVL[1:0] ,FIFO Transmission Level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 9.--10. " FRLVL[1:0] ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40013000+0x04))&0x10)==0x00)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS[3:0] ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
rgroup.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
bitfld.word 0x00 11.--12. " FTLVL[1:0] ,FIFO Transmission Level" "Empty,1/4,1/2,Full"
|
|
bitfld.word 0x00 9.--10. " FRLVL[1:0] ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x800)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
rgroup.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
endif
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
hexmask.word 0x00 0.--15. 1. " DR[15:0] ,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x00 0.--15. 1. " CRCPOLY[15:0] ,CRC polynomial register"
|
|
if (((per.w(ad:0x40013000+0x1C))&0x800)==0x000)
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x00 0.--15. 1. " RXCRC[15:0] ,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x00 0.--15. 1. " TxCRC[15:0] ,Tx CRC register"
|
|
else
|
|
hgroup.word 0x14++0x1
|
|
hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hgroup.word 0x18++0x1
|
|
hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
endif
|
|
if (((per.w(ad:0x40013000+0x1C))&0x800)==0x800)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave - transmit,Slave - receive,Master - transmit,Master - receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "Philips,MSB,LSB,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High"
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,"
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length" "16-bit,32-bit"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master clock output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,I2SDIV * 2+1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S linear prescaler"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
hgroup.word 0x20++0x1
|
|
hide.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("STM32F042C*")||cpuis("STM32F072*")||cpuis("STM32F048C6")||cpuis("STM32F058R8")
|
|
tree "SPI2"
|
|
base ad:0x40013000
|
|
width 12.
|
|
if (((per.l(ad:0x40003800))&0x40)==0x40)
|
|
if ((per.w((ad:0x40003800+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
rbitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
line.word 0x02 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
rbitfld.word 0x02 3. " NSSP ,NSS pulse management" "No NSS,NSS"
|
|
bitfld.word 0x02 2. " SSOE ,SS Output enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx Buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
line.word 0x02 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.w((ad:0x40003800+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock=first data,Second clock=first data"
|
|
line.word 0x02 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
bitfld.word 0x02 3. " NSSP ,NSS pulse management" "No NSS,NSS"
|
|
bitfld.word 0x02 2. " SSOE ,SS Output enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
line.word 0x02 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x02 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x02 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x02 12. " FRXTH ,FIFO reception threshold" "16 bit,8 bit"
|
|
bitfld.word 0x02 8.--11. " DS[3:0] ,Data size" ",,,,4 bit,5 bit,6bit,7 bit,8 bit,9 bit,10 bit,11 bit,12 bit,13 bit,14 bit,15 bit"
|
|
textline " "
|
|
bitfld.word 0x02 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x02 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x02 4. " FRF ,Frame format" "SPI Motorola,SPI TI"
|
|
textline " "
|
|
bitfld.word 0x02 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI Status Register"
|
|
bitfld.word 0x00 11.--12. " FTLVL[1:0] ,FIFO transmission level" "Empty,1/4 FIFO,1/2 FIFO,FULL"
|
|
bitfld.word 0x00 9.--10. " FRLVL[1:0] ,FIFO reception level" "Empty,1/4 FIFO,1/2 FIFO,FULL"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "No error,Error"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI Data Register"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC Polynomial Register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC Register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC Register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")
|
|
tree "SPI2/I2S2"
|
|
base ad:0x40013000
|
|
width 13.
|
|
if (((per.w(ad:0x40003800+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40003800+0x04))&0x10)==0x10)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40003800+0x04))&0x10)==0x00)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Unidirectional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock,First data"
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x800)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "SPI_CR1,SPI control register 1"
|
|
endif
|
|
if ((((per.w(ad:0x40003800+0x1C))&0x800)==0x000)&&(((per.w((ad:0x40003800+0x04)))&0x10)==0x10))
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS[3:0] ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x00 11.--12. " FTLVL[1:0] ,FIFO Transmission Level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 9.--10. " FRLVL[1:0] ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40003800+0x04))&0x10)==0x00)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS[3:0] ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
rgroup.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
bitfld.word 0x00 11.--12. " FTLVL[1:0] ,FIFO Transmission Level" "Empty,1/4,1/2,Full"
|
|
bitfld.word 0x00 9.--10. " FRLVL[1:0] ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x800)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
rgroup.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " UDR ,Underrun flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
endif
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
hexmask.word 0x00 0.--15. 1. " DR[15:0] ,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x00 0.--15. 1. " CRCPOLY[15:0] ,CRC polynomial register"
|
|
if (((per.w(ad:0x40003800+0x1C))&0x800)==0x000)
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x00 0.--15. 1. " RXCRC[15:0] ,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x00 0.--15. 1. " TxCRC[15:0] ,Tx CRC register"
|
|
else
|
|
hgroup.word 0x14++0x1
|
|
hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hgroup.word 0x18++0x1
|
|
hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
endif
|
|
if (((per.w(ad:0x40003800+0x1C))&0x800)==0x800)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave - transmit,Slave - receive,Master - transmit,Master - receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "Philips,MSB,LSB,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High"
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,"
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length" "16-bit,32-bit"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master clock output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,I2SDIV * 2+1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S linear prescaler"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
hgroup.word 0x20++0x1
|
|
hide.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F042*"))||(cpuis("STM32F072*"))||cpuis("STM32F091*")||cpuis("STM32F098*")
|
|
tree "bxCAN (Basic Extended Controller Area Network)"
|
|
base ad:0x40006400
|
|
width 12.
|
|
group.long 0x000++0x1F
|
|
line.long 0x000 "CAN_MCR,CAN master control register"
|
|
bitfld.long 0x000 16. " DBF ,Debug freeze" "Disabled,Enabled"
|
|
bitfld.long 0x000 15. " RESET ,bxCAN software master reset" "Normal,Reset"
|
|
bitfld.long 0x000 7. " TTCM ,Time Triggered Communication Mode" "Disabled,Enabled"
|
|
bitfld.long 0x000 6. " ABOM ,Automatic Bus-Off Management" "Software,Auto"
|
|
textline " "
|
|
bitfld.long 0x000 5. " AWUM ,Automatic Wake-Up Mode" "Software,Auto"
|
|
bitfld.long 0x000 4. " NART ,No Automatic Retransmission" "Retransmitted,Only once"
|
|
bitfld.long 0x000 3. " RFLM ,Receive FIFO Locked Mode" "Not locked,Locked"
|
|
bitfld.long 0x000 2. " TXFP ,Transmit FIFO Priority" "Identifier,Request order"
|
|
textline " "
|
|
bitfld.long 0x000 1. " SLEEP ,SLEEP Mode Request" "Exit,Enter"
|
|
bitfld.long 0x000 0. " INRQ ,Initialization Request" "Normal,Initialization"
|
|
line.long 0x004 "CAN_MSR,CAN master status register"
|
|
rbitfld.long 0x004 11. " RX ,CAN Rx Signal" "0,1"
|
|
rbitfld.long 0x004 10. " SAMP ,Last Sample Point" "0,1"
|
|
rbitfld.long 0x004 9. " RXM ,Receive Mode" "No effect,Receiver"
|
|
rbitfld.long 0x004 8. " TXM ,Transmit Mode" "No effect,Transmitter"
|
|
textline " "
|
|
eventfld.long 0x004 4. " SLAKI ,SLEEP Acknowledge Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x004 3. " WKUI ,Wake-Up Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x004 2. " ERRI ,Error Interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x004 1. " SLAK ,SLEEP Acknowledge" "In SLEEP,Left SLEEP"
|
|
textline " "
|
|
rbitfld.long 0x004 0. " INAK ,Initialization Acknowledge" "Left initialization,In initialization"
|
|
line.long 0x008 "CAN_TSR,CAN transmit status register"
|
|
rbitfld.long 0x008 31. " LOW2 ,Lowest Priority Flag for Mailbox 2" "0,1"
|
|
rbitfld.long 0x008 30. " LOW1 ,Lowest Priority Flag for Mailbox 1" "0,1"
|
|
rbitfld.long 0x008 29. " LOW0 ,Lowest Priority Flag for Mailbox 0" "0,1"
|
|
rbitfld.long 0x008 28. " TME2 ,Transmit Mailbox 2 Empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x008 27. " TME1 ,Transmit Mailbox 1 Empty" "Not empty,Empty"
|
|
rbitfld.long 0x008 26. " TME0 ,Transmit Mailbox 0 Empty" "Not empty,Empty"
|
|
rbitfld.long 0x008 24.--25. " CODE ,Mailbox Code" "0,1,2,3"
|
|
bitfld.long 0x008 23. " ABRQ2 ,Abort Request for Mailbox 2" "Mailbox empty,Abort"
|
|
textline " "
|
|
eventfld.long 0x008 19. " TERR2 ,Transmission Error of Mailbox 2" "No error,Error"
|
|
eventfld.long 0x008 18. " ALST2 ,Arbitration Lost for Mailbox 2" "No effect,Lost"
|
|
eventfld.long 0x008 17. " TXOK2 ,Transmission OK of Mailbox 2" "Failed,Successful"
|
|
eventfld.long 0x008 16. " RQCP2 ,Request Completed Mailbox 2" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x008 15. " ABRQ1 ,Abort Request for Mailbox 1" "Mailbox empty,Abort"
|
|
eventfld.long 0x008 11. " TERR1 ,Transmission Error of Mailbox 1" "No error,Error"
|
|
eventfld.long 0x008 10. " ALST1 ,Arbitration Lost for Mailbox 1" "No effect,Lost"
|
|
eventfld.long 0x008 9. " TXOK1 ,Transmission OK of Mailbox 1" "Failed,Successful"
|
|
textline " "
|
|
eventfld.long 0x008 8. " RQCP1 ,Request Completed Mailbox 1" "Not completed,Completed"
|
|
bitfld.long 0x008 7. " ABRQ0 ,Abort Request for Mailbox 0" "Mailbox empty,Abort"
|
|
eventfld.long 0x008 3. " TERR0 ,Transmission Error of Mailbox 0" "No error,Error"
|
|
eventfld.long 0x008 2. " ALST0 ,Arbitration Lost for Mailbox 0" "No effect,Lost"
|
|
textline " "
|
|
eventfld.long 0x008 1. " TXOK0 ,Transmission OK of Mailbox 0" "Failed,Successful"
|
|
eventfld.long 0x008 0. " RQCP0 ,Request Completed Mailbox 0" "Not completed,Completed"
|
|
line.long 0x00C "CAN_RF0R,CAN receive FIFO 0 register"
|
|
bitfld.long 0x00C 5. " RFOM0 ,Release FIFO 0 Output Mailbox" "Released,Release"
|
|
eventfld.long 0x00C 4. " FOVR0 ,FIFO 0 Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x00C 3. " FULL0 ,FIFO 0 Full" "No effect,Stored"
|
|
rbitfld.long 0x00C 0.--1. " FMP0 ,FIFO 0 Message Pending" "0,1,2,3"
|
|
line.long 0x010 "CAN_RF1R,CAN receive FIFO 1 register"
|
|
bitfld.long 0x010 5. " RFOM1 ,Release FIFO 1 Output Mailbox" "Released,Release"
|
|
eventfld.long 0x010 4. " FOVR1 ,FIFO 1 Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x010 3. " FULL1 ,FIFO 1 Full" "No effect,Stored"
|
|
rbitfld.long 0x010 0.--1. " FMP1 ,FIFO 1 Message Pending" "0,1,2,3"
|
|
line.long 0x014 "CAN_IER,CAN interrupt enable register"
|
|
bitfld.long 0x014 17. " SLKIE ,SLEEP Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x014 16. " WKUIE ,Wake-Up Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x014 15. " ERRIE ,Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x014 11. " LECIE ,Last Error Code Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x014 10. " BOFIE ,Bus-Off Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x014 9. " EPVIE ,Error Passive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x014 8. " EWGIE ,Error Warning Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x014 6. " FOVIE1 ,FIFO Overrun Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x014 5. " FFIE1 ,FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x014 4. " FMPIE1 ,FIFO Message Pending Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x014 3. " FOVIE0 ,FIFO Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x014 2. " FFIE0 ,FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x014 1. " FMPIE0 ,FIFO Message Pending Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x014 0. " TMEIE ,Transmit Mailbox Empty Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x018 "CAN_ESR,CAN error status register"
|
|
hexmask.long.byte 0x018 24.--31. 1. " REC ,Receive Error Counter"
|
|
hexmask.long.byte 0x018 16.--23. 1. " TEC ,Least significant byte of the 9-bit Transmit Error Counter"
|
|
bitfld.long 0x018 4.--6. " LEC ,Last Error Code" "No error,Stuff,Form,Acknowledgment,Bit recessive,Bit dominant,CRC,Set by software"
|
|
rbitfld.long 0x018 2. " BOFF ,Bus-Off Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x018 1. " EPVF ,Error Passive Flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x018 0. " EWGF ,Error Warning Flag" "Not occurred,Occurred"
|
|
line.long 0x01C "CAN_BTR,CAN bit timing register"
|
|
bitfld.long 0x01C 31. " SILM ,Silent Mode" "Normal,Silent"
|
|
bitfld.long 0x01C 30. " LBKM ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x01C 24.--25. " SJW ,Resynchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x01C 20.--22. " TS2 ,Time Segment 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x01C 16.--19. " TS1 ,Time Segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x01C 0.--9. 1. " BRP ,Baud Rate Prescaler"
|
|
tree "T0 Mailbox"
|
|
if (((per.l((ad:0x40006400+0x180)))&0x4)==0x4)
|
|
group.long 0x180++0x3
|
|
line.long 0x000 "CAN_TI0R,TX mailbox identifier register"
|
|
hexmask.long 0x000 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x000 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x000 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x000 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
else
|
|
group.long 0x180++0x3
|
|
line.long 0x000 "CAN_TI0R,TX mailbox identifier register"
|
|
hexmask.long.word 0x000 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x000 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x000 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x000 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
endif
|
|
group.long 0x184++0xb
|
|
line.long 0x000 "CAN_TDT0R,Mailbox data length control and time stamp register"
|
|
hexmask.long.word 0x000 16.--31. 1. " TIME ,Message Time Stamp"
|
|
bitfld.long 0x000 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,..."
|
|
line.long 0x004 "CAN_TDL0R,Mailbox data low register"
|
|
hexmask.long.byte 0x004 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x004 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x004 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x004 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x008 "CAN_TDH0R,Mailbox data high register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "T1 Mailbox"
|
|
if (((per.l((ad:0x40006400+0x190)))&0x4)==0x4)
|
|
group.long 0x190++0x3
|
|
line.long 0x000 "CAN_TI1R,TX mailbox identifier register"
|
|
hexmask.long 0x000 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x000 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x000 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x000 0. " TXRQ ,Transmit Mailbox Request" "No requested,Requested"
|
|
else
|
|
group.long 0x190++0x3
|
|
line.long 0x000 "CAN_TI1R,TX mailbox identifier register"
|
|
hexmask.long.word 0x000 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x000 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x000 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x000 0. " TXRQ ,Transmit Mailbox Request" "No requested,Requested"
|
|
endif
|
|
group.long 0x194++0xb
|
|
line.long 0x000 "CAN_TDT1R,Mailbox data length control and time stamp register"
|
|
hexmask.long.word 0x000 16.--31. 1. " TIME ,Message Time Stamp"
|
|
bitfld.long 0x000 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
line.long 0x004 "CAN_TDL1R,Mailbox data low register"
|
|
hexmask.long.byte 0x004 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x004 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x004 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x004 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x008 "CAN_TDH1R,Mailbox data high register"
|
|
hexmask.long.byte 0x008 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x008 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x008 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x008 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "T2 Mailbox"
|
|
if (((per.l((ad:0x40006400+0x1A0)))&0x4)==0x4)
|
|
group.long 0x1A0++0x003
|
|
line.long 0x000 "CAN_TI2R,TX mailbox identifier register"
|
|
hexmask.long 0x000 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x000 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x000 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x000 0. " TXRQ ,Transmit Mailbox Request" "No requested,Requested"
|
|
else
|
|
group.long 0x1A0++0x003
|
|
line.long 0x000 "CAN_TI2R,TX mailbox identifier register"
|
|
hexmask.long.word 0x000 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x000 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x000 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x000 0. " TXRQ ,Transmit Mailbox Request" "No requested,Requested"
|
|
endif
|
|
group.long 0x1A4++0x00b
|
|
line.long 0x000 "CAN_TDT2R,Mailbox data length control and time stamp register"
|
|
hexmask.long.word 0x000 16.--31. 1. " TIME ,Message Time Stamp"
|
|
bitfld.long 0x000 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
line.long 0x004 "CAN_TDL2R,Mailbox data low register"
|
|
hexmask.long.byte 0x004 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x004 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x004 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x004 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x008 "CAN_TDH2R,Mailbox data high register"
|
|
hexmask.long.byte 0x008 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x008 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x008 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x008 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "FIFO 0"
|
|
if (((per.l((ad:0x40006400+0x1B0)))&0x4)==0x4)
|
|
rgroup.long 0x1B0++0x003
|
|
line.long 0x000 "CAN_RI0R,Rx FIFO mailbox identifier register"
|
|
hexmask.long 0x000 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x000 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x000 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
else
|
|
rgroup.long 0x1B0++0x003
|
|
line.long 0x000 "CAN_RI0R,Rx FIFO mailbox identifier register"
|
|
hexmask.long.word 0x000 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x000 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x000 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
endif
|
|
rgroup.long 0x1B4++0x00b
|
|
line.long 0x000 "CAN_RDT0R,Receive FIFO mailbox data length control and time stamp register"
|
|
hexmask.long.word 0x000 16.--31. 1. " TIME ,Message Time Stamp"
|
|
hexmask.long.byte 0x000 8.--15. 1. " FMI ,Filter Match Index"
|
|
bitfld.long 0x000 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
line.long 0x004 "CAN_RDL0R,Receive FIFO mailbox data low register"
|
|
hexmask.long.byte 0x004 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x004 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x004 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x004 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x008 "CAN_RDH0R,Receive FIFO mailbox data low register"
|
|
hexmask.long.byte 0x008 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x008 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x008 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x008 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "FIFO 1"
|
|
if (((per.l((ad:0x40006400+0x1C0)))&0x4)==0x4)
|
|
rgroup.long 0x1C0++0x003
|
|
line.long 0x000 "CAN_RI1R,Rx FIFO mailbox identifier register"
|
|
hexmask.long 0x000 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x000 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x000 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
else
|
|
rgroup.long 0x1C0++0x003
|
|
line.long 0x000 "CAN_RI1R,Rx FIFO mailbox identifier register"
|
|
hexmask.long.word 0x000 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x000 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
bitfld.long 0x000 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
endif
|
|
rgroup.long 0x1C4++0x00b
|
|
line.long 0x000 "CAN_RDT1R,Receive FIFO mailbox data length control and time stamp register"
|
|
hexmask.long.word 0x000 16.--31. 1. " TIME ,Message Time Stamp"
|
|
hexmask.long.byte 0x000 8.--15. 1. " FMI ,Filter Match Index"
|
|
bitfld.long 0x000 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
|
|
line.long 0x004 "CAN_RDL1R,Receive FIFO mailbox data low register"
|
|
hexmask.long.byte 0x004 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x004 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x004 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x004 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x008 "CAN_RDH1R,Receive FIFO mailbox data high register"
|
|
hexmask.long.byte 0x008 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x008 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x008 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x008 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "Filter Registers"
|
|
group.long 0x200++0x007
|
|
line.long 0x000 "CAN_FMR,CAN filter master register"
|
|
hexmask.long.byte 0x000 8.--13. 1. " CAN2SB ,CAN2 start bank"
|
|
bitfld.long 0x000 0. " FINIT ,Filter Init Mode" "Active,Initialization"
|
|
line.long 0x004 "CAN_FM1R,CAN filter mode register"
|
|
bitfld.long 0x004 27. " FBM27 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 26. " FBM26 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 25. " FBM25 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 24. " FBM24 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x004 23. " FBM23 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 22. " FBM22 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 21. " FBM21 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 20. " FBM20 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x004 19. " FBM19 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 18. " FBM18 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 17. " FBM17 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 16. " FBM16 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x004 15. " FBM15 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 14. " FBM14 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 13. " FBM13 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 12. " FBM12 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x004 11. " FBM11 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 10. " FBM10 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 9. " FBM9 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 8. " FBM8 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x004 7. " FBM7 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 6. " FBM6 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 5. " FBM5 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 4. " FBM4 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x004 3. " FBM3 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 2. " FBM2 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 1. " FBM1 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x004 0. " FBM0 ,Filter Mode" "Mask,List"
|
|
group.long 0x20C++0x003
|
|
line.long 0x000 "CAN_FS1R,CAN filter scale register"
|
|
bitfld.long 0x000 27. " FSC27 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 26. " FSC26 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 25. " FSC25 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 24. " FSC24 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FSC23 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 22. " FSC22 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 21. " FSC21 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 20. " FSC20 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FSC19 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 18. " FSC18 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 17. " FSC17 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 16. " FSC16 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FSC15 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 14. " FSC14 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 13. " FSC13 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 12. " FSC12 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FSC11 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 10. " FSC10 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 9. " FSC9 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 8. " FSC8 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FSC7 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 6. " FSC6 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 5. " FSC5 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 4. " FSC4 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FSC3 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 2. " FSC2 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 1. " FSC1 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x000 0. " FSC0 ,Filter Scale Configuration" "Dual,Single"
|
|
group.long 0x214++0x003
|
|
line.long 0x000 "CAN_FFA1R,CAN filter FIFO assignment register"
|
|
bitfld.long 0x000 27. " FFA27 ,Filter FIFO Assignment for Filter 27" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 26. " FFA26 ,Filter FIFO Assignment for Filter 26" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 25. " FFA25 ,Filter FIFO Assignment for Filter 25" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 24. " FFA24 ,Filter FIFO Assignment for Filter 24" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FFA23 ,Filter FIFO Assignment for Filter 23" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 22. " FFA22 ,Filter FIFO Assignment for Filter 22" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 21. " FFA21 ,Filter FIFO Assignment for Filter 21" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 20. " FFA20 ,Filter FIFO Assignment for Filter 20" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FFA19 ,Filter FIFO Assignment for Filter 19" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 18. " FFA18 ,Filter FIFO Assignment for Filter 18" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 17. " FFA17 ,Filter FIFO Assignment for Filter 17" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 16. " FFA16 ,Filter FIFO Assignment for Filter 16" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FFA15 ,Filter FIFO Assignment for Filter 15" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 14. " FFA14 ,Filter FIFO Assignment for Filter 14" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 13. " FFA13 ,Filter FIFO Assignment for Filter 13" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 12. " FFA12 ,Filter FIFO Assignment for Filter 12" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FFA11 ,Filter FIFO Assignment for Filter 11" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 10. " FFA10 ,Filter FIFO Assignment for Filter 10" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 9. " FFA9 ,Filter FIFO Assignment for Filter 9" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 8. " FFA8 ,Filter FIFO Assignment for Filter 8" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FFA7 ,Filter FIFO Assignment for Filter 7" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 6. " FFA6 ,Filter FIFO Assignment for Filter 6" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 5. " FFA5 ,Filter FIFO Assignment for Filter 5" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 4. " FFA4 ,Filter FIFO Assignment for Filter 4" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FFA3 ,Filter FIFO Assignment for Filter 3" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 2. " FFA2 ,Filter FIFO Assignment for Filter 2" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 1. " FFA1 ,Filter FIFO Assignment for Filter 1" "FIFO0,FIFO1"
|
|
bitfld.long 0x000 0. " FFA0 ,Filter FIFO Assignment for Filter 0" "FIFO0,FIFO1"
|
|
group.long 0x21C++0x003
|
|
line.long 0x000 "CAN_FA1R,CAN filter activation register"
|
|
bitfld.long 0x000 27. " FACT27 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 26. " FACT26 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 25. " FACT25 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 24. " FACT24 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FACT23 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 22. " FACT22 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 21. " FACT21 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 20. " FACT20 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FACT19 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 18. " FACT18 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 17. " FACT17 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 16. " FACT16 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FACT15 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 14. " FACT14 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 13. " FACT13 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 12. " FACT12 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FACT11 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 10. " FACT10 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 9. " FACT9 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 8. " FACT8 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FACT7 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 6. " FACT6 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 5. " FACT5 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 4. " FACT4 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FACT3 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 2. " FACT2 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 1. " FACT1 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x000 0. " FACT0 ,Filter Active" "Not active,Active"
|
|
tree "Filter Bank Registers"
|
|
group.long 0x240++0x003
|
|
line.long 0x000 "CAN_F0R1,Filter bank 0_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x244++0x003
|
|
line.long 0x000 "CAN_F0R2,Filter bank 0_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x248++0x003
|
|
line.long 0x000 "CAN_F1R1,Filter bank 1_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x24C++0x003
|
|
line.long 0x000 "CAN_F1R2,Filter bank 1_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x250++0x003
|
|
line.long 0x000 "CAN_F2R1,Filter bank 2_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x254++0x003
|
|
line.long 0x000 "CAN_F2R2,Filter bank 2_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x258++0x003
|
|
line.long 0x000 "CAN_F3R1,Filter bank 3_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x25C++0x003
|
|
line.long 0x000 "CAN_F3R2,Filter bank 3_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x260++0x003
|
|
line.long 0x000 "CAN_F4R1,Filter bank 4_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x264++0x003
|
|
line.long 0x000 "CAN_F4R2,Filter bank 4_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x268++0x003
|
|
line.long 0x000 "CAN_F5R1,Filter bank 5_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x26C++0x003
|
|
line.long 0x000 "CAN_F5R2,Filter bank 5_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x270++0x003
|
|
line.long 0x000 "CAN_F6R1,Filter bank 6_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x274++0x003
|
|
line.long 0x000 "CAN_F6R2,Filter bank 6_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x278++0x003
|
|
line.long 0x000 "CAN_F7R1,Filter bank 7_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x27C++0x003
|
|
line.long 0x000 "CAN_F7R2,Filter bank 7_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x280++0x003
|
|
line.long 0x000 "CAN_F8R1,Filter bank 8_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x284++0x003
|
|
line.long 0x000 "CAN_F8R2,Filter bank 8_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x288++0x003
|
|
line.long 0x000 "CAN_F9R1,Filter bank 9_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x28C++0x003
|
|
line.long 0x000 "CAN_F9R2,Filter bank 9_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x290++0x003
|
|
line.long 0x000 "CAN_F10R1,Filter bank 10_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x294++0x003
|
|
line.long 0x000 "CAN_F10R2,Filter bank 10_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x298++0x003
|
|
line.long 0x000 "CAN_F11R1,Filter bank 11_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x29C++0x003
|
|
line.long 0x000 "CAN_F11R2,Filter bank 11_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2A0++0x003
|
|
line.long 0x000 "CAN_F12R1,Filter bank 12_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2A4++0x003
|
|
line.long 0x000 "CAN_F12R2,Filter bank 12_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2A8++0x003
|
|
line.long 0x000 "CAN_F13R1,Filter bank 13_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2AC++0x003
|
|
line.long 0x000 "CAN_F13R2,Filter bank 13_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2B0++0x003
|
|
line.long 0x000 "CAN_F14R1,Filter bank 14_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2B4++0x003
|
|
line.long 0x000 "CAN_F14R2,Filter bank 14_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2B8++0x003
|
|
line.long 0x000 "CAN_F15R1,Filter bank 15_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2BC++0x003
|
|
line.long 0x000 "CAN_F15R2,Filter bank 15_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2C0++0x003
|
|
line.long 0x000 "CAN_F16R1,Filter bank 16_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2C4++0x003
|
|
line.long 0x000 "CAN_F16R2,Filter bank 16_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2C8++0x003
|
|
line.long 0x000 "CAN_F17R1,Filter bank 17_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2CC++0x003
|
|
line.long 0x000 "CAN_F17R2,Filter bank 17_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2D0++0x003
|
|
line.long 0x000 "CAN_F18R1,Filter bank 18_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2D4++0x003
|
|
line.long 0x000 "CAN_F18R2,Filter bank 18_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2D8++0x003
|
|
line.long 0x000 "CAN_F19R1,Filter bank 19_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2DC++0x003
|
|
line.long 0x000 "CAN_F19R2,Filter bank 19_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2E0++0x003
|
|
line.long 0x000 "CAN_F20R1,Filter bank 20_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2E4++0x003
|
|
line.long 0x000 "CAN_F20R2,Filter bank 20_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2E8++0x003
|
|
line.long 0x000 "CAN_F21R1,Filter bank 21_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2EC++0x003
|
|
line.long 0x000 "CAN_F21R2,Filter bank 21_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2F0++0x003
|
|
line.long 0x000 "CAN_F22R1,Filter bank 22_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2F4++0x003
|
|
line.long 0x000 "CAN_F22R2,Filter bank 22_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2F8++0x003
|
|
line.long 0x000 "CAN_F23R1,Filter bank 23_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2FC++0x003
|
|
line.long 0x000 "CAN_F23R2,Filter bank 23_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x300++0x003
|
|
line.long 0x000 "CAN_F24R1,Filter bank 24_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x304++0x003
|
|
line.long 0x000 "CAN_F24R2,Filter bank 24_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x308++0x003
|
|
line.long 0x000 "CAN_F25R1,Filter bank 25_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x30C++0x003
|
|
line.long 0x000 "CAN_F25R2,Filter bank 25_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x310++0x003
|
|
line.long 0x000 "CAN_F26R1,Filter bank 26_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x314++0x003
|
|
line.long 0x000 "CAN_F26R2,Filter bank 26_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x318++0x003
|
|
line.long 0x000 "CAN_F27R1,Filter bank 27_1 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x31C++0x003
|
|
line.long 0x000 "CAN_F27R2,Filter bank 27_2 registers (identifier/mask)"
|
|
bitfld.long 0x000 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x000 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x000 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
tree.end
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32F042*"))||(cpuis("STM32F072*"))||cpuis("STM32F048?6")||cpuis("STM32F078?B")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
tree "USB (Universal Serial Bus)"
|
|
base ad:0x40005C00
|
|
width 12.
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "USB_CNTR,USB Control Register"
|
|
bitfld.long 0x00 15. " CTRM ,Correct transfer interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PMAOVRM ,Packet memory area over/underrun interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ERRM ,Error interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WKUPM ,Wake-up interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SUSPM ,Suspend mode interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RESETM ,USB reset interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SOFM ,Start of frame interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ESOFM ,Expected start of frame interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " L1REQM ,LPM L1 state request interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " L1RESUME ,LPM L1 resume request" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RESUME ,Resume request" "No effect,Requested"
|
|
bitfld.long 0x00 3. " FSUSP ,Force suspend" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LP_MODE ,Low-power mode" "No Low-power,Entered"
|
|
bitfld.long 0x00 1. " PDWN ,Power down" "Not powered down,Powered down"
|
|
bitfld.long 0x00 0. " FRES ,Force USB reset" "Cleared,Reset"
|
|
line.long 0x04 "USB_ISTR,USB Interrupt Status Register"
|
|
rbitfld.long 0x04 15. " CTR ,Correct transfer" "No effect,Correct"
|
|
bitfld.long 0x04 14. " PMAOVR ,Packet memory area over/underrun" "No Over/Underrun,Over/Underrun"
|
|
bitfld.long 0x04 13. " ERR ,Error" "No error,Error"
|
|
bitfld.long 0x04 12. " WKUP ,Wakeup" "No wakeup,Wakeup"
|
|
textline " "
|
|
bitfld.long 0x04 11. " SUSP ,Suspend mode request" "Not requested,Requested"
|
|
bitfld.long 0x04 10. " RESET ,USB reset request" "No reset,Reset"
|
|
bitfld.long 0x04 9. " SOF ,Start of frame" "No effect,Packet arrived"
|
|
bitfld.long 0x04 8. " ESOF ,Expected start of frame" "No effect,Packet expected"
|
|
textline " "
|
|
bitfld.long 0x04 7. " L1REQ ,LPM L1 state request" "Not requested,Requested"
|
|
rbitfld.long 0x04 4. " DIR ,Direction of transaction" "IN,OUT/2 pending transactions"
|
|
rbitfld.long 0x04 0.--3. " EP_ID ,Endpoint identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "USB_FNR,USB Frame Number Register"
|
|
bitfld.long 0x00 15. " RXDP ,Receive data + line status" "No data,Data"
|
|
bitfld.long 0x00 14. " RXDM ,Receive data - line status" "No data,Data"
|
|
bitfld.long 0x00 13. " LCK ,Locked" "Unlocked,Locked"
|
|
bitfld.long 0x00 11.--12. " LSOF ,Lost SOF" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--10. 1. " FN ,Frame number"
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "USB_DADDR,USB Device Address"
|
|
bitfld.long 0x00 7. " EF ,Enable function" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " ADD ,Device address"
|
|
line.long 0x04 "USB_BTABLE,Buffer Table Address"
|
|
hexmask.long.word 0x04 3.--15. 0x08 " BTABLE ,Buffer table"
|
|
sif (cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*"))||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "USB_LPMCSR,LPM Control and Status Register"
|
|
rbitfld.word 0x00 4.--7. " BESL ,BESL value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 3. " REMWAKE ,bRemoteWake value" "0,1"
|
|
bitfld.word 0x00 1. " LPMACK ,LPM token acknowledge enable" "NYET,ACK"
|
|
bitfld.word 0x00 0. " LPMEN ,LPM support enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "USB_BCDR,Battery Charging Detector"
|
|
bitfld.word 0x00 15. " DPPU ,DP pull-up control" "Disabled,Enabled"
|
|
rbitfld.word 0x00 7. " PS2DET ,DM pull-up detection status" "Normal port,PS2 port/Proprietary charger"
|
|
rbitfld.word 0x00 6. " SDET ,Secondary detection (SD) status" "CDP,DCP"
|
|
rbitfld.word 0x00 5. " PDET ,Primary detection (PD) status" "No BCD support,BCD support"
|
|
textline " "
|
|
rbitfld.word 0x00 4. " DCDET ,Data contact detection" "Not detected,Detected"
|
|
bitfld.word 0x00 3. " SDEN ,Secondary detection (SD) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " PDEN ,Primary detection (PD) mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " DCDEN ,Data contact detection (DCD) mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " BCDEN ,Battery charging detector" "Disabled,Enabled"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "USB_EP0R,USB Endpoint 0 Register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1"
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT"
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "USB_EP1R,USB Endpoint 1 Register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1"
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT"
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "USB_EP2R,USB Endpoint 2 Register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1"
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT"
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "USB_EP3R,USB Endpoint 3 Register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1"
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT"
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USB_EP4R,USB Endpoint 4 Register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1"
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT"
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USB_EP5R,USB Endpoint 5 Register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1"
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT"
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "USB_EP6R,USB Endpoint 6 Register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1"
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT"
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "USB_EP7R,USB Endpoint 7 Register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1"
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
rbitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT"
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree "USB BDT (USB Buffer descriptor table)"
|
|
base ad:0x40006000
|
|
width 15.
|
|
group.word 0x00++0x07
|
|
line.word 0x00 "USB_ADDR0_TX,Transmission Buffer Address 0"
|
|
hexmask.word 0x00 1.--15. 0x2 " ADDR0_TX ,Transmission buffer address"
|
|
line.word 0x02 "USB_COUNT0_TX,Transmission Byte Count 0"
|
|
hexmask.word 0x02 0.--9. 0x1 " COUNT0_TX ,Transmission byte count"
|
|
line.word 0x04 "USB_ADDR0_RX,Reception buffer Address 0"
|
|
hexmask.word 0x04 1.--15. 0x2 " ADDR0_RX ,Reception buffer address"
|
|
line.word 0x06 "USB_COUNT0_RX,Reception Byte Count 0"
|
|
bitfld.word 0x06 15. " BL_SIZE ,Block size" "2 byte,32 byte"
|
|
textline " "
|
|
bitfld.word 0x06 10.--14. " NUM_BLOCK ,Number of blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x06 0.--9. 0x1 " COUNT0_RX ,Reception byte count"
|
|
group.word 0x8++0x07
|
|
line.word 0x00 "USB_ADDR1_TX,Transmission Buffer Address 1"
|
|
hexmask.word 0x00 1.--15. 0x2 " ADDR1_TX ,Transmission buffer address"
|
|
line.word 0x02 "USB_COUNT1_TX,Transmission Byte Count 1"
|
|
hexmask.word 0x02 0.--9. 0x01 " COUNT1_TX ,Transmission byte count"
|
|
line.word 0x04 "USB_ADDR1_RX,Reception Buffer Address 1"
|
|
hexmask.word 0x04 1.--15. 0x2 " ADDR1_RX ,Reception buffer address"
|
|
line.word 0x06 "USB_COUNT1_RX,Reception Byte Count 1"
|
|
bitfld.word 0x06 15. " BL_SIZE ,Block size" "2 byte,32 byte"
|
|
textline " "
|
|
bitfld.word 0x06 10.--14. " NUM_BLOCK ,Number of blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x06 0.--9. 0x01 " COUNT1_RX ,Reception byte count"
|
|
group.word 0x10++0x07
|
|
line.word 0x00 "USB_ADDR2_TX,Transmission Buffer Address 2"
|
|
hexmask.word 0x00 1.--15. 0x2 " ADDR2_TX ,Transmission buffer address"
|
|
line.word 0x02 "USB_COUNT2_TX,Transmission Byte Count 2"
|
|
hexmask.word 0x02 0.--9. 0x01 " COUNT2_TX ,Transmission byte count"
|
|
line.word 0x04 "USB_ADDR2_RX,Reception Buffer Address 2"
|
|
hexmask.word 0x04 1.--15. 0x2 " ADDR2_RX ,Reception buffer address"
|
|
line.word 0x06 "USB_COUNT2_RX,Reception Byte Count 2"
|
|
bitfld.word 0x06 15. " BL_SIZE ,Block size" "2 byte,32 byte"
|
|
textline " "
|
|
bitfld.word 0x06 10.--14. " NUM_BLOCK ,Number of blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x06 0.--9. 0x01 " COUNT2_RX ,Reception byte count"
|
|
group.word 0x18++0x07
|
|
line.word 0x00 "USB_ADDR3_TX,Transmission Buffer Address 3"
|
|
hexmask.word 0x00 1.--15. 0x2 " ADDR3_TX ,Transmission buffer address"
|
|
line.word 0x02 "USB_COUNT3_TX,Transmission Byte Count 3"
|
|
hexmask.word 0x02 0.--9. 0x01 " COUNT3_TX ,Transmission byte count"
|
|
line.word 0x04 "USB_ADDR3_RX,Reception Buffer Address 3"
|
|
hexmask.word 0x04 1.--15. 0x2 " ADDR3_RX ,Reception buffer address"
|
|
line.word 0x06 "USB_COUNT3_RX,Reception Byte Count 3"
|
|
bitfld.word 0x06 15. " BL_SIZE ,Block size" "2 byte,32 byte"
|
|
textline " "
|
|
bitfld.word 0x06 10.--14. " NUM_BLOCK ,Number of blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x06 0.--9. 0x01 " COUNT3_RX ,Reception byte count"
|
|
group.word 0x20++0x07
|
|
line.word 0x00 "USB_ADDR4_TX,Transmission Buffer Address 4"
|
|
hexmask.word 0x00 1.--15. 0x2 " ADDR4_TX ,Transmission buffer address"
|
|
line.word 0x02 "USB_COUNT4_TX,Transmission Byte Count 4"
|
|
hexmask.word 0x02 0.--9. 0x01 " COUNT4_TX ,Transmission byte count"
|
|
line.word 0x04 "USB_ADDR4_RX,Reception Buffer Address 4"
|
|
hexmask.word 0x04 1.--15. 0x2 " ADDR4_RX ,Reception buffer address"
|
|
line.word 0x06 "USB_COUNT4_RX,Reception Byte Count 4"
|
|
bitfld.word 0x06 15. " BL_SIZE ,Block size" "2 byte,32 byte"
|
|
textline " "
|
|
bitfld.word 0x06 10.--14. " NUM_BLOCK ,Number of blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x06 0.--9. 0x01 " COUNT4_RX ,Reception byte count"
|
|
group.word 0x28++0x07
|
|
line.word 0x00 "USB_ADDR5_TX,Transmission Buffer Address 5"
|
|
hexmask.word 0x00 1.--15. 0x2 " ADDR5_TX ,Transmission buffer address"
|
|
line.word 0x02 "USB_COUNT5_TX,Transmission Byte Count 5"
|
|
hexmask.word 0x02 0.--9. 0x01 " COUNT5_TX ,Transmission byte count"
|
|
line.word 0x04 "USB_ADDR5_RX,Reception Buffer Address 5"
|
|
hexmask.word 0x04 1.--15. 0x2 " ADDR5_RX ,Reception buffer address"
|
|
line.word 0x06 "USB_COUNT5_RX,Reception Byte Count 5"
|
|
bitfld.word 0x06 15. " BL_SIZE ,Block size" "2 byte,32 byte"
|
|
textline " "
|
|
bitfld.word 0x06 10.--14. " NUM_BLOCK ,Number of blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x06 0.--9. 0x01 " COUNT5_RX ,Reception byte count"
|
|
group.word 0x30++0x07
|
|
line.word 0x00 "USB_ADDR6_TX,Transmission Buffer Address 6"
|
|
hexmask.word 0x00 1.--15. 0x2 " ADDR6_TX ,Transmission buffer address"
|
|
line.word 0x02 "USB_COUNT6_TX,Transmission Byte Count 6"
|
|
hexmask.word 0x02 0.--9. 0x01 " COUNT6_TX ,Transmission byte count"
|
|
line.word 0x04 "USB_ADDR6_RX,Reception Buffer Address 6"
|
|
hexmask.word 0x04 1.--15. 0x2 " ADDR6_RX ,Reception buffer address"
|
|
line.word 0x06 "USB_COUNT6_RX,Reception Byte Count 6"
|
|
bitfld.word 0x06 15. " BL_SIZE ,Block size" "2 byte,32 byte"
|
|
textline " "
|
|
bitfld.word 0x06 10.--14. " NUM_BLOCK ,Number of blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x06 0.--9. 0x01 " COUNT6_RX ,Reception byte count"
|
|
group.word 0x38++0x07
|
|
line.word 0x00 "USB_ADDR7_TX,Transmission Buffer Address 7"
|
|
hexmask.word 0x00 1.--15. 0x2 " ADDR7_TX ,Transmission buffer address"
|
|
line.word 0x02 "USB_COUNT7_TX,Transmission Byte Count 7"
|
|
hexmask.word 0x02 0.--9. 0x01 " COUNT7_TX ,Transmission byte count"
|
|
line.word 0x04 "USB_ADDR7_RX,Reception Buffer Address 7"
|
|
hexmask.word 0x04 1.--15. 0x2 " ADDR7_RX ,Reception buffer address"
|
|
line.word 0x06 "USB_COUNT7_RX,Reception Byte Count 7"
|
|
bitfld.word 0x06 15. " BL_SIZE ,Block size" "2 byte,32 byte"
|
|
textline " "
|
|
bitfld.word 0x06 10.--14. " NUM_BLOCK ,Number of blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
hexmask.word 0x06 0.--9. 0x01 " COUNT7_RX ,Reception byte count"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8"||cpuis("STM32F042*")||cpuis("STM32F072*")||cpuis("STM32F071*")||cpuis("STM32F050G6"))
|
|
tree "TSC (Touch sensing controller)"
|
|
base ad:0x40024000
|
|
width 12.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "TSC_CR,TSC control register"
|
|
bitfld.long 0x00 28.--31. " CTPH[3:0] ,Charge transfer pulse high" "1x t PGCLK,2x t PGCLK,3x t PGCLK,4x t PGCLK,5x t PGCLK,6x t PGCLK,7x t PGCLK,8x t PGCLK,9x t PGCLK,10x t PGCLK,11x t PGCLK,12x t PGCLK,13x t PGCLK,14x t PGCLK,15x t PGCLK,16x t PGCLK"
|
|
bitfld.long 0x00 24.--27. " CTPL[3:0] ,Charge transfer pulse low" "1x t PGCLK,2x t PGCLK,3x t PGCLK,4x t PGCLK,5x t PGCLK,6x t PGCLK,7x t PGCLK,8x t PGCLK,9x t PGCLK,10x t PGCLK,11x t PGCLK,12x t PGCLK,13x t PGCLK,14x t PGCLK,15x t PGCLK,16x t PGCLK"
|
|
hexmask.long.byte 0x00 17.--23. 1. " SSD[6:0] ,Spread spectrum deviation"
|
|
bitfld.long 0x00 16. " SSE ,Spread spectrum enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SSPSC ,Spread spectrum prescaler" "Fhclk,Fhclk /2"
|
|
bitfld.long 0x00 12.--14. " PGPSC[2:0] ,Pulse generator prescaler" "Fhclk,Fhclk /2,Fhclk /4,Fhclk /8,Fhclk /16,Fhclk /32,Fhclk /64,Fhclk /128"
|
|
bitfld.long 0x00 5.--7. " MCV[2:0] ,Max count value" "255,511,1023,2047,4095,8191,16383,?..."
|
|
bitfld.long 0x00 4. " IODEF ,I/O Default mode" "Output push-pull low,Input floating"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCPOL ,Synchronization pin polarity" "Falling edge,Rising edge and high level"
|
|
bitfld.long 0x00 2. " AM ,Acquisition mode" "Normal,Synchronized"
|
|
bitfld.long 0x00 1. " START ,Start a new acquisition" "Not started,Started"
|
|
bitfld.long 0x00 0. " TSCE ,Touch sensing controller enable" "Disabled,Enabled"
|
|
line.long 0x04 "TSC_IER,TSC interrupt enable register"
|
|
bitfld.long 0x04 1. " MCEIE ,Max count error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EOAIE ,End of acquisition interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "TSC_ICR,TSC interrupt clear register"
|
|
bitfld.long 0x08 1. " MCEIC ,Max count error interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x08 0. " EOAIC ,End of acquisition interrupt clear" "No effect,Cleared"
|
|
line.long 0x0C "TSC_ISR,TSC interrupt status register"
|
|
bitfld.long 0x0C 1. " MCEF ,Max count error flag" "Not detected,Detected"
|
|
bitfld.long 0x0C 0. " EOAF ,End of acquisition flag" "Not occurred,Occurred"
|
|
line.long 0x10 "TSC_IOHCR,TSC I/O hysteresis control register"
|
|
sif (cpu()=="STM32F302VB")||(cpu()=="STM32F302VC")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x10 31. " G8_IO4 ,G8_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " G8_IO3 ,G8_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " G8_IO2 ,G8_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " G8_IO1 ,G8_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " G7_IO4 ,G7_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " G7_IO3 ,G7_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 25. " G7_IO2 ,G7_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " G7_IO1 ,G7_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8"&&!CPUIS("STM32F050*")&&!CPUIS("STM32F042*"))
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373RB")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373RC")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F373R8")&&(cpu()!="STM32F383CC")&&(cpu()!="STM32F383RC")
|
|
bitfld.long 0x10 23. " G6_IO4 ,G6_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 22. " G6_IO3 ,G6_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " G6_IO2 ,G6_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " G6_IO1 ,G6_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 19. " G5_IO4 ,G5_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " G5_IO3 ,G5_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " G5_IO2 ,G5_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " G5_IO1 ,G5_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " G4_IO4 ,G4_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " G4_IO3 ,G4_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " G4_IO2 ,G4_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " G4_IO1 ,G4_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F303CB")&&(cpu()!="STM32F303CC")&&(cpu()!="STM32F313CC")&&(cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x10 11. " G3_IO4 ,G3_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x10 10. " G3_IO3 ,G3_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 9. " G3_IO2 ,G3_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
sif !CPUIS("STM32F050*")&&!CPUIS("STM32F042*")
|
|
bitfld.long 0x10 8. " G3_IO1 ,G3_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x10 7. " G2_IO4 ,G2_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " G2_IO3 ,G2_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " G2_IO2 ,G2_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " G2_IO1 ,G2_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 3. " G1_IO4 ,G1_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " G1_IO3 ,G1_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " G1_IO2 ,G1_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " G1_IO1 ,G1_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TSC_IOASCR,TSC I/O analog switch control register"
|
|
sif (cpu()=="STM32F302VB")||(cpu()=="STM32F302VC")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x00 31. " G8_IO4 ,G8_IO4 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 30. " G8_IO3 ,G8_IO3 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 29. " G8_IO2 ,G8_IO2 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 28. " G8_IO1 ,G8_IO1 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " G7_IO4 ,G7_IO4 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 26. " G7_IO3 ,G7_IO3 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 25. " G7_IO2 ,G7_IO2 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 24. " G7_IO1 ,G7_IO1 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
sif (CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8"&&!CPUIS("STM32F050*")&&!CPUIS("STM32F042*"))
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373RB")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373RC")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F373R8")&&(cpu()!="STM32F383CC")&&(cpu()!="STM32F383RC")
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F303CB")&&(cpu()!="STM32F303CC")&&(cpu()!="STM32F313CC")&&(cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
sif !CPUIS("STM32F050*")&&!CPUIS("STM32F042*")
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO4 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 analog switch enable" "Opened,Closed"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TSC_IOSCR,TSC I/O sampling control register"
|
|
sif (cpu()=="STM32F302VB")||(cpu()=="STM32F302VC")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x00 31. " G8_IO4 ,G8_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 30. " G8_IO3 ,G8_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 29. " G8_IO2 ,G8_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 28. " G8_IO1 ,G8_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 27. " G7_IO4 ,G7_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 26. " G7_IO3 ,G7_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 25. " G7_IO2 ,G7_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 24. " G7_IO1 ,G7_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8"&&!CPUIS("STM32F050*")&&!CPUIS("STM32F042*"))
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373RB")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373RC")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F373R8")&&(cpu()!="STM32F383CC")&&(cpu()!="STM32F383RC")
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F303CB")&&(cpu()!="STM32F303CC")&&(cpu()!="STM32F313CC")&&(cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 sampling mode" "Unused,Used"
|
|
textline " "
|
|
sif !CPUIS("STM32F050*")&&!CPUIS("STM32F042*")
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO4 sampling mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 sampling mode" "Unused,Used"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TSC_IOCCR,TSC I/O channel control register"
|
|
sif (cpu()=="STM32F302VB")||(cpu()=="STM32F302VC")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x00 31. " G8_IO4 ,G8_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 30. " G8_IO3 ,G8_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 29. " G8_IO2 ,G8_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 28. " G8_IO1 ,G8_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 27. " G7_IO4 ,G7_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 26. " G7_IO3 ,G7_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 25. " G7_IO2 ,G7_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 24. " G7_IO1 ,G7_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8"&&!CPUIS("STM32F050*")&&!CPUIS("STM32F042*"))
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373RB")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373RC")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F373R8")&&(cpu()!="STM32F383CC")&&(cpu()!="STM32F383RC")
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F303CB")&&(cpu()!="STM32F303CC")&&(cpu()!="STM32F313CC")&&(cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 channel mode" "Unused,Used"
|
|
textline " "
|
|
sif !CPUIS("STM32F050*")&&!CPUIS("STM32F042*")
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO4 channel mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 channel mode" "Unused,Used"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TSC_IOGCSR,TSC I/O group control status register"
|
|
sif (cpu()=="STM32F302VB")||(cpu()=="STM32F302VC")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x00 23. " G8S ,Analog I/O group 8 status" "Not started,Completed"
|
|
bitfld.long 0x00 22. " G7S ,Analog I/O group 7 status" "Not started,Completed"
|
|
textline " "
|
|
endif
|
|
sif (CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8"&&!CPUIS("STM32F050*")&&!CPUIS("STM32F042*"))
|
|
bitfld.long 0x00 21. " G6S ,Analog I/O group 6 status" "Not started,Completed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " G5S ,Analog I/O group 5 status" "Not started,Completed"
|
|
bitfld.long 0x00 19. " G4S ,Analog I/O group 4 status" "Not started,Completed"
|
|
bitfld.long 0x00 18. " G3S ,Analog I/O group 3 status" "Not started,Completed"
|
|
bitfld.long 0x00 17. " G2S ,Analog I/O group 2 status" "Not started,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " G1S ,Analog I/O group 1 status" "Not started,Completed"
|
|
textline " "
|
|
sif (cpu()=="STM32F302VB")||(cpu()=="STM32F302VC")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x00 7. " G8E ,Analog I/O group 8 status" "Not started,Completed"
|
|
bitfld.long 0x00 6. " G7E ,Analog I/O group 7 status" "Not started,Completed"
|
|
textline " "
|
|
endif
|
|
sif (CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8"&&!CPUIS("STM32F050*")&&!CPUIS("STM32F042*"))
|
|
bitfld.long 0x00 5. " G6E ,Analog I/O group 6 status" "Not started,Completed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " G5E ,Analog I/O group 5 status" "Not started,Completed"
|
|
bitfld.long 0x00 3. " G4E ,Analog I/O group 4 status" "Not started,Completed"
|
|
bitfld.long 0x00 2. " G3E ,Analog I/O group 3 status" "Not started,Completed"
|
|
bitfld.long 0x00 1. " G2E ,Analog I/O group 2 status" "Not started,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " G1E ,Analog I/O group 1 status" "Not started,Completed"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
rgroup.long 0x34++0x1B
|
|
else
|
|
group.long 0x34++0x1B
|
|
endif
|
|
line.long 0x0 "TSC_IOG1CR,TSC I/O group 1 counter register"
|
|
hexmask.long.word 0x0 0.--13. 1. " CNT[13:0] ,Counter value"
|
|
line.long 0x4 "TSC_IOG2CR,TSC I/O group 2 counter register"
|
|
hexmask.long.word 0x4 0.--13. 1. " CNT[13:0] ,Counter value"
|
|
line.long 0x8 "TSC_IOG3CR,TSC I/O group 3 counter register"
|
|
hexmask.long.word 0x8 0.--13. 1. " CNT[13:0] ,Counter value"
|
|
line.long 0xC "TSC_IOG4CR,TSC I/O group 4 counter register"
|
|
hexmask.long.word 0xC 0.--13. 1. " CNT[13:0] ,Counter value"
|
|
line.long 0x10 "TSC_IOG5CR,TSC I/O group 5 counter register"
|
|
hexmask.long.word 0x10 0.--13. 1. " CNT[13:0] ,Counter value"
|
|
line.long 0x14 "TSC_IOG6CR,TSC I/O group 6 counter register"
|
|
hexmask.long.word 0x14 0.--13. 1. " CNT[13:0] ,Counter value"
|
|
sif (cpu()=="STM32F302VB")||(cpu()=="STM32F302VC")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383VC")
|
|
rgroup.long 0x4C++0x1B
|
|
line.long 0x0 "TSC_IOG7CR,TSC I/O group 7 counter register"
|
|
hexmask.long.word 0x0 0.--13. 1. " CNT[13:0] ,Counter value"
|
|
line.long 0x4 "TSC_IOG8CR,TSC I/O group 8 counter register"
|
|
hexmask.long.word 0x4 0.--13. 1. " CNT[13:0] ,Counter value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
elif (cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F051T8"))
|
|
tree "TSC (Touch sensing controller)"
|
|
base ad:0x40024000
|
|
width 12.
|
|
if (((per.l(ad:0x40024000+0x0C))&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TSC_CR,TSC Control Register"
|
|
bitfld.long 0x00 28.--31. " CTPH ,Charge transfer pulse high" "1x t PGCLK,2x t PGCLK,3x t PGCLK,4x t PGCLK,5x t PGCLK,6x t PGCLK,7x t PGCLK,8x t PGCLK,9x t PGCLK,10x t PGCLK,11x t PGCLK,12x t PGCLK,13x t PGCLK,14x t PGCLK,15x t PGCLK,16x t PGCLK"
|
|
bitfld.long 0x00 24.--27. " CTPL ,Charge transfer pulse low" "1x t PGCLK,2x t PGCLK,3x t PGCLK,4x t PGCLK,5x t PGCLK,6x t PGCLK,7x t PGCLK,8x t PGCLK,9x t PGCLK,10x t PGCLK,11x t PGCLK,12x t PGCLK,13x t PGCLK,14x t PGCLK,15x t PGCLK,16x t PGCLK"
|
|
hexmask.long.byte 0x00 17.--23. 1. " SSD ,Spread spectrum deviation"
|
|
bitfld.long 0x00 16. " SSE ,Spread spectrum enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SSPSC ,Spread spectrum prescaler" "Fhclk,Fhclk /2"
|
|
bitfld.long 0x00 12.--14. " PGPSC ,Pulse generator prescaler" "Fhclk,Fhclk /2,Fhclk /4,Fhclk /8,Fhclk /16,Fhclk /32,Fhclk /64,Fhclk /128"
|
|
bitfld.long 0x00 5.--7. " MCV ,Max count value" "255,511,1023,2047,4095,8191,16383,?..."
|
|
bitfld.long 0x00 4. " IODEF ,I/O Default mode" "Output push-pull low,Input floating"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCPOL ,Synchronization pin polarity" "Falling edge,Rising edge and high level"
|
|
bitfld.long 0x00 2. " AM ,Acquisition mode" "Normal,Synchronized"
|
|
bitfld.long 0x00 1. " START ,Start a new acquisition" "Not started,Started"
|
|
bitfld.long 0x00 0. " TSCE ,Touch sensing controller enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "TSC_CR,TSC Control Register"
|
|
bitfld.long 0x00 28.--31. " CTPH ,Charge transfer pulse high" "1x t PGCLK,2x t PGCLK,3x t PGCLK,4x t PGCLK,5x t PGCLK,6x t PGCLK,7x t PGCLK,8x t PGCLK,9x t PGCLK,10x t PGCLK,11x t PGCLK,12x t PGCLK,13x t PGCLK,14x t PGCLK,15x t PGCLK,16x t PGCLK"
|
|
bitfld.long 0x00 24.--27. " CTPL ,Charge transfer pulse low" "1x t PGCLK,2x t PGCLK,3x t PGCLK,4x t PGCLK,5x t PGCLK,6x t PGCLK,7x t PGCLK,8x t PGCLK,9x t PGCLK,10x t PGCLK,11x t PGCLK,12x t PGCLK,13x t PGCLK,14x t PGCLK,15x t PGCLK,16x t PGCLK"
|
|
hexmask.long.byte 0x00 17.--23. 1. " SSD ,Spread spectrum deviation"
|
|
bitfld.long 0x00 16. " SSE ,Spread spectrum enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SSPSC ,Spread spectrum prescaler" "Fhclk,Fhclk /2"
|
|
bitfld.long 0x00 12.--14. " PGPSC ,Pulse generator prescaler" "Fhclk,Fhclk /2,Fhclk /4,Fhclk /8,Fhclk /16,Fhclk /32,Fhclk /64,Fhclk /128"
|
|
bitfld.long 0x00 5.--7. " MCV ,Max count value" "255,511,1023,2047,4095,8191,16383,?..."
|
|
bitfld.long 0x00 4. " IODEF ,I/O Default mode" "Output push-pull low,Input floating"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCPOL ,Synchronization pin polarity" "Falling edge,Rising edge and high level"
|
|
bitfld.long 0x00 2. " AM ,Acquisition mode" "Normal,Synchronized"
|
|
bitfld.long 0x00 1. " START ,Start a new acquisition" "Not started,Started"
|
|
bitfld.long 0x00 0. " TSCE ,Touch sensing controller enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "TSC_IER,TSC Interrupt Enable Register"
|
|
bitfld.long 0x00 1. " MCEIE ,Max count error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EOAIE ,End of acquisition interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "TSC_ICR,TSC Interrupt Clear Register"
|
|
bitfld.long 0x04 1. " MCEIC ,Max count error interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x04 0. " EOAIC ,End of acquisition interrupt clear" "No effect,Cleared"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "TSC_ISR,TSC Interrupt Status Register"
|
|
rbitfld.long 0x00 1. " MCEF ,Max count error flag" "Not detected,Detected"
|
|
rbitfld.long 0x00 0. " EOAF ,End of acquisition flag" "Not occurred,Occurred"
|
|
textline " "
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TSC_IOHCR,TSC I/O Hysteresis Control Register"
|
|
sif cpuis("STM32F091V?")||cpuis("STM32F078V?")
|
|
bitfld.long 0x00 31. " G8_IO4 ,G8_IO4 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " G8_IO3 ,G8_IO3 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " G8_IO2 ,G8_IO2 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " G8_IO1 ,G8_IO1 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " G7_IO4 ,G7_IO4 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " G7_IO3 ,G7_IO3 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " G7_IO2 ,G7_IO2 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " G7_IO1 ,G7_IO1 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F091*")||cpuis("STM32F078*")||cpuis("STM32F058R*")||cpuis("STM32F058C*")
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F058*")||cpuis("STM32F078*")||cpuis("STM32F048*")||cpuis("STM32F091*")||CPUIS("STM32F051T8")
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F058*")||cpuis("STM32F078*")||cpuis("STM32F048*")||cpuis("STM32F091*")||CPUIS("STM32F051T8")
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F058*"))&&(!cpuis("STM32F078*"))&&(!cpuis("STM32F048G*"))&&(!cpuis("STM32F048C*"))&&(!cpuis("STM32F098*"))
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F048T*"))&&(!cpuis("STM32F048G*"))
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F058R8")||(cpuis("STM32F078R*"))||(cpuis("STM32F078V*"))||(cpuis("STM32F091V*"))||(cpuis("STM32F091R*"))||(cpuis("STM32F098RC")))
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO3 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TSC_IOASCR,TSC I/O Analog Switch Control Register"
|
|
sif cpuis("STM32F091V?")||cpuis("STM32F078V?")
|
|
bitfld.long 0x00 31. " G8_IO4 ,G8_IO4 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " G8_IO3 ,G8_IO3 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " G8_IO2 ,G8_IO2 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " G8_IO1 ,G8_IO1 analog switch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " G7_IO4 ,G7_IO4 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " G7_IO3 ,G7_IO3 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " G7_IO2 ,G7_IO2 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " G7_IO1 ,G7_IO1 analog switch enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F091*")||cpuis("STM32F078*")||cpuis("STM32F058R*")||cpuis("STM32F058C*")
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 analog switch enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F058*")||cpuis("STM32F078*")||cpuis("STM32F048*")||cpuis("STM32F091*")||CPUIS("STM32F051T8")
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 analog switch enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F058*")||cpuis("STM32F078*")||cpuis("STM32F048*")||cpuis("STM32F091*")||CPUIS("STM32F051T8")
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 analog switch enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F058*"))&&(!cpuis("STM32F078*"))&&(!cpuis("STM32F048G*"))&&(!cpuis("STM32F048C*"))&&(!cpuis("STM32F098*"))
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 analog switch enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F048T*"))&&(!cpuis("STM32F048G*"))
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 analog switch enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 analog switch enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("STM32F058R8")||(cpuis("STM32F078R*"))||(cpuis("STM32F078V*"))||(cpuis("STM32F091V*"))||(cpuis("STM32F091R*"))||(cpuis("STM32F098RC")))
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 analog switch enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 analog switch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO3 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 analog switch enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40024000+0x0C))&0x01)==0x01)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TSC_IOSCR,TSC I/O Sampling Control Register"
|
|
sif cpuis("STM32F091V?")||cpuis("STM32F078V?")
|
|
bitfld.long 0x00 31. " G8_IO4 ,G8_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 30. " G8_IO3 ,G8_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 29. " G8_IO2 ,G8_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 28. " G8_IO1 ,G8_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 27. " G7_IO4 ,G7_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 26. " G7_IO3 ,G7_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 25. " G7_IO2 ,G7_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 24. " G7_IO1 ,G7_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F091*")||cpuis("STM32F078*")||cpuis("STM32F058R*")||cpuis("STM32F058C*")
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F058*")||cpuis("STM32F078*")||cpuis("STM32F048*")||cpuis("STM32F091*")||CPUIS("STM32F051T8")
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F058*")||cpuis("STM32F078*")||cpuis("STM32F048*")||cpuis("STM32F091*")||CPUIS("STM32F051T8")
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F058*"))&&(!cpuis("STM32F078*"))&&(!cpuis("STM32F048G*"))&&(!cpuis("STM32F048C*"))&&(!cpuis("STM32F098*"))
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F048T*"))&&(!cpuis("STM32F048G*"))
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 sampling mode" "Unused,Used"
|
|
textline " "
|
|
sif (cpuis("STM32F058R8")||(cpuis("STM32F078R*"))||(cpuis("STM32F078V*"))||(cpuis("STM32F091V*"))||(cpuis("STM32F091R*"))||(cpuis("STM32F098RC")))
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 sampling mode" "Unused,Used"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TSC_IOCCR,TSC I/O Channel Control Register"
|
|
sif cpuis("STM32F091V?")||cpuis("STM32F078V?")
|
|
bitfld.long 0x00 31. " G8_IO4 ,G8_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 30. " G8_IO3 ,G8_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 29. " G8_IO2 ,G8_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 28. " G8_IO1 ,G8_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 27. " G7_IO4 ,G7_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 26. " G7_IO3 ,G7_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 25. " G7_IO2 ,G7_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 24. " G7_IO1 ,G7_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F091*")||cpuis("STM32F078*")||cpuis("STM32F058R*")||cpuis("STM32F058C*")
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F058*")||cpuis("STM32F078*")||cpuis("STM32F048*")||cpuis("STM32F091*")||CPUIS("STM32F051T8")
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F058*")||cpuis("STM32F078*")||cpuis("STM32F048*")||cpuis("STM32F091*")||CPUIS("STM32F051T8")
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F058*"))&&(!cpuis("STM32F078*"))&&(!cpuis("STM32F048G*"))&&(!cpuis("STM32F048C*"))&&(!cpuis("STM32F098*"))
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F048T*"))&&(!cpuis("STM32F048G*"))
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 channel mode" "Unused,Used"
|
|
textline " "
|
|
sif (cpuis("STM32F058R8")||(cpuis("STM32F078R*"))||(cpuis("STM32F078V*"))||(cpuis("STM32F091V*"))||(cpuis("STM32F091R*"))||(cpuis("STM32F098RC")))
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 channel mode" "Unused,Used"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "TSC_IOSCR,TSC I/O Sampling Control Register"
|
|
sif cpuis("STM32F091V?")||cpuis("STM32F078V?")
|
|
bitfld.long 0x00 31. " G8_IO4 ,G8_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 30. " G8_IO3 ,G8_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 29. " G8_IO2 ,G8_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 28. " G8_IO1 ,G8_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 27. " G7_IO4 ,G7_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 26. " G7_IO3 ,G7_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 25. " G7_IO2 ,G7_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 24. " G7_IO1 ,G7_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F091*")||cpuis("STM32F078*")||cpuis("STM32F058R*")||cpuis("STM32F058C*")
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F058*")||cpuis("STM32F078*")||cpuis("STM32F048*")||cpuis("STM32F091*")||CPUIS("STM32F051T8")
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F058*")||cpuis("STM32F078*")||cpuis("STM32F048*")||cpuis("STM32F091*")||CPUIS("STM32F051T8")
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F058*"))&&(!cpuis("STM32F078*"))&&(!cpuis("STM32F048G*"))&&(!cpuis("STM32F048C*"))&&(!cpuis("STM32F098*"))
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F048T*"))&&(!cpuis("STM32F048G*"))
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 sampling mode" "Unused,Used"
|
|
textline " "
|
|
sif (cpuis("STM32F058R8")||(cpuis("STM32F078R*"))||(cpuis("STM32F078V*"))||(cpuis("STM32F091V*"))||(cpuis("STM32F091R*"))||(cpuis("STM32F098RC")))
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 sampling mode" "Unused,Used"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TSC_IOCCR,TSC I/O Channel Control Register"
|
|
sif cpuis("STM32F091V?")||cpuis("STM32F078V?")
|
|
bitfld.long 0x00 31. " G8_IO4 ,G8_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 30. " G8_IO3 ,G8_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 29. " G8_IO2 ,G8_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 28. " G8_IO1 ,G8_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 27. " G7_IO4 ,G7_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 26. " G7_IO3 ,G7_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 25. " G7_IO2 ,G7_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 24. " G7_IO1 ,G7_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F091*")||cpuis("STM32F078*")||cpuis("STM32F058R*")||cpuis("STM32F058C*")
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F058*")||cpuis("STM32F078*")||cpuis("STM32F048*")||cpuis("STM32F091*")||CPUIS("STM32F051T8")
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F058*")||cpuis("STM32F078*")||cpuis("STM32F048*")||cpuis("STM32F091*")||CPUIS("STM32F051T8")
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F058*"))&&(!cpuis("STM32F078*"))&&(!cpuis("STM32F048G*"))&&(!cpuis("STM32F048C*"))&&(!cpuis("STM32F098*"))
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F048T*"))&&(!cpuis("STM32F048G*"))
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 channel mode" "Unused,Used"
|
|
textline " "
|
|
sif (cpuis("STM32F058R8")||(cpuis("STM32F078R*"))||(cpuis("STM32F078V*"))||(cpuis("STM32F091V*"))||(cpuis("STM32F091R*"))||(cpuis("STM32F098RC")))
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 channel mode" "Unused,Used"
|
|
endif
|
|
textline " "
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TSC_IOGCSR,TSC I/O Group Control Status Register"
|
|
sif cpuis("STM32F091V?")||cpuis("STM32F078V?")
|
|
rbitfld.long 0x00 23. " G8S ,analog I/O group 8 status" "Not started/Ongoing,Completed"
|
|
rbitfld.long 0x00 22. " G7S ,analog I/O group 7 status" "Not started/Ongoing,Completed"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F091*")||cpuis("STM32F078*")||cpuis("STM32F058R*")||cpuis("STM32F058C*")
|
|
rbitfld.long 0x00 21. " G6S ,analog I/O group 6 status" "Not started/Ongoing,Completed"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 20. " G5S ,analog I/O group 5 status" "Not started/Ongoing,Completed"
|
|
rbitfld.long 0x00 19. " G4S ,analog I/O group 4 status" "Not started/Ongoing,Completed"
|
|
rbitfld.long 0x00 18. " G3S ,analog I/O group 3 status" "Not started/Ongoing,Completed"
|
|
rbitfld.long 0x00 17. " G2S ,analog I/O group 2 status" "Not started/Ongoing,Completed"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " G1S ,analog I/O group 1 status" "Not started/Ongoing,Completed"
|
|
textline " "
|
|
sif cpuis("STM32F091V?")||cpuis("STM32F078V?")
|
|
bitfld.long 0x00 7. " G8E ,analog I/O group 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " G7E ,analog I/O group 7 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F091*")||cpuis("STM32F078*")||cpuis("STM32F058R*")||cpuis("STM32F058C*")
|
|
bitfld.long 0x00 5. " G6E ,analog I/O group 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F098*")||cpuis("STM32F058*")||cpuis("STM32F078*")||cpuis("STM32F048*")||cpuis("STM32F091*")||CPUIS("STM32F051T8")
|
|
bitfld.long 0x00 4. " G5E ,analog I/O group 5 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " G4E ,analog I/O group 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " G3E ,analog I/O group 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " G2E ,analog I/O group 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " G1E ,analog I/O group 1 enable" "Disabled,Enabled"
|
|
rgroup.long (0x0+0x34)++0x03
|
|
line.long 0x00 "TSC_IOG1CR,TSC I/O Group 1 Counter Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value"
|
|
rgroup.long (0x4+0x34)++0x03
|
|
line.long 0x00 "TSC_IOG2CR,TSC I/O Group 2 Counter Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value"
|
|
rgroup.long (0x8+0x34)++0x03
|
|
line.long 0x00 "TSC_IOG3CR,TSC I/O Group 3 Counter Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value"
|
|
rgroup.long (0xC+0x34)++0x03
|
|
line.long 0x00 "TSC_IOG4CR,TSC I/O Group 4 Counter Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value"
|
|
rgroup.long (0x10+0x34)++0x03
|
|
line.long 0x00 "TSC_IOG5CR,TSC I/O Group 5 Counter Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value"
|
|
rgroup.long (0x14+0x34)++0x03
|
|
line.long 0x00 "TSC_IOG6CR,TSC I/O Group 6 Counter Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value"
|
|
rgroup.long (0x18+0x34)++0x03
|
|
line.long 0x00 "TSC_IOG7CR,TSC I/O Group 7 Counter Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value"
|
|
rgroup.long (0x1C+0x34)++0x03
|
|
line.long 0x00 "TSC_IOG8CR,TSC I/O Group 8 Counter Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " CNT ,Counter value"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif !cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8"||(cpuis("STM32F042*"))||(cpuis("STM32F07*"))||cpuis("STM32F048*")||cpuis("STM32F058*")||cpuis("STM32F078*")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F051T8"))
|
|
tree "HDMI-CEC (HDMI-CEC controller)"
|
|
base ad:0x40007800
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CEC_CR,CEC Control Register"
|
|
bitfld.long 0x00 2. " TXEOM ,Tx end of message" "TXDR with EOM=0,TXDR with EOM=1"
|
|
bitfld.long 0x00 1. " TXSOM ,Tx start of message" "No CEC transmission,CEC transmission"
|
|
bitfld.long 0x00 0. " CECEN ,CEC enable" "Disabled,Enabled"
|
|
if (((per.l((ad:0x40007800+0x0)))&0x1)==0x0)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CEC_CFGR,CEC Configuration Register"
|
|
bitfld.long 0x00 31. " LSTN ,Listen mode" "OAR,OAR/positive acknowledge"
|
|
hexmask.long.word 0x00 16.--30. 1. " OAR ,Own address"
|
|
bitfld.long 0x00 8. " SFTOP ,SFT option bit" "On TXSOM set,Automatically"
|
|
bitfld.long 0x00 7. " BRDNOGEN ,Avoid error-bit generation in broadcast" "BRESTP=1 and BREGEN=0 or LBPEGEN=0,Not generated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBPEGEN ,Generate error-bit on long bit period error" "Not generated,Generated"
|
|
bitfld.long 0x00 5. " BREGEN ,Generate error-bit on bit rising error" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BRESTP ,Rx-stop on bit rising error" "Not stopped,Stopped"
|
|
bitfld.long 0x00 3. " RXTOL ,Rx-tolerance" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " SFT ,Signal free time" "2.5 periods/4 periods/6 periods,0.5 periods,1.5 periods,2.5 periods,3.5 periods,4.5 periods,5.5 periods,6.5 periods"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CEC_CFGR,CEC Configuration Register"
|
|
bitfld.long 0x00 31. " LSTN ,Listen mode" "OAR,OAR/positive acknowledge"
|
|
hexmask.long.word 0x00 16.--30. 1. " OAR ,Own address"
|
|
bitfld.long 0x00 8. " SFTOP ,SFT option bit" "On TXSOM set,Automatically"
|
|
bitfld.long 0x00 7. " BRDNOGEN ,Avoid error-bit generation in broadcast" "BRESTP=1 and BREGEN=0 or LBPEGEN=0,Not generated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBPEGEN ,Generate error-bit on long bit period error" "Not generated,Generated"
|
|
bitfld.long 0x00 5. " BREGEN ,Generate error-bit on bit rising error" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BRESTP ,Rx-stop on bit rising error" "Not stopped,Stopped"
|
|
bitfld.long 0x00 3. " RXTOL ,Rx-tolerance" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " SFT ,Signal free time" "2.5 periods/4 periods/6 periods,0.5 periods,1.5 periods,2.5 periods,3.5 periods,4.5 periods,5.5 periods,6.5 periods"
|
|
endif
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "CEC_TXDR,CEC Tx Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXD ,Tx Data register"
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "CEC_RXDR,CEC Rx Data Register"
|
|
in
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CEC_ISR,CEC Interrupt and Status Register"
|
|
eventfld.long 0x00 12. " TXACKE ,Tx-missing acknowledge error" "No error,Error"
|
|
eventfld.long 0x00 11. " TXERR ,Tx-error" "No error,Error"
|
|
eventfld.long 0x00 10. " TXUDR ,Tx-buffer under-run" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " TXEND ,End of transmission" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TXBR ,Tx-byte request" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " ARBLST ,Arbitration lost" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " RXACKE ,Rx-missing acknowledge" "No error,Error"
|
|
eventfld.long 0x00 5. " LBPE ,Rx-long bit period error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 4. " SBPE ,Rx-short bit period error" "No error,Error"
|
|
eventfld.long 0x00 3. " BRE ,Rx-bit rising error" "No error,Error"
|
|
eventfld.long 0x00 2. " RXOVR ,Rx-overrun" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " RXEND ,End of reception" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " RXBR ,Rx-byte received" "Not received,Received"
|
|
if (((per.l(ad:0x40007800))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CEC_IER,CEC Interrupt Enable Register"
|
|
bitfld.long 0x00 12. " TXACKEIE ,Tx-missing acknowledge error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TXERRIE ,Tx-error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TXUDRIE ,Tx-buffer under-run interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TXENDIE ,End of transmission interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXBRIE ,Tx-byte request interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ARBLSTIE ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXACKEIE ,Rx-missing acknowledge error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBPEIE ,Long bit period error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SBPEIE ,Short bit period error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " BREIE ,Bit rising error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXOVRIE ,Rx-buffer overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXENDIE ,End of reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXBRIE ,Rx-byte received interrupt enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CEC_IER,CEC Interrupt Enable Register"
|
|
bitfld.long 0x00 12. " TXACKEIE ,Tx-missing acknowledge error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TXERRIE ,Tx-error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TXUDRIE ,Tx-buffer under-run interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TXENDIE ,End of transmission interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXBRIE ,Tx-byte request interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ARBLSTIE ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXACKEIE ,Rx-missing acknowledge error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBPEIE ,Long bit period error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SBPEIE ,Short bit period error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " BREIE ,Bit rising error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXOVRIE ,Rx-buffer overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXENDIE ,End of reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXBRIE ,Rx-byte received interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
endif
|
|
sif (!cpuis("STM32F030?4"))&&(!cpuis("STM32F030?6"))&&(!cpuis("STM32F030?8"))&&(!cpuis("STM32F031*"))&&(!cpuis("STM32F042*"))&&(!cpuis("STM32F071*"))&&(!cpuis("STM32F072*"))&&(!cpuis("STM32F050G6"))&&(!cpuis("STM32F038?6"))&&(!cpuis("STM32F048?6"))&&(!cpuis("STM32F058?8"))&&(!cpuis("STM32F078?B"))&&(!cpuis("STM32F091?B"))&&(!cpuis("STM32F091?C"))&&(!cpuis("STM32F098?C")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F051T8"))
|
|
tree "ESIG (Device electronic signature)"
|
|
base ad:0x1FFFF7CC
|
|
width 8.
|
|
rgroup.word 0x00++0x01
|
|
line.word 0x00 "F_SIZE,Flash Size Register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
sif (cpuis("STM32F031?4"))||(cpuis("STM32F031?6"))||(cpuis("STM32F051?4"))||(cpuis("STM32F051?6"))||(cpuis("STM32F051?8"))||(cpuis("STM32F071?8"))||(cpuis("STM32F071?B"))||(cpuis("STM32F042?4"))||(cpuis("STM32F042?6"))||(cpuis("STM32F072?8"))||(cpuis("STM32F072?B"))||(cpuis("STM32F038?6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F091?C"))||(cpuis("STM32F098?C"))
|
|
tree "ESIG (Device electronic signature)"
|
|
base ad:0x1FFFF7AC
|
|
width 12.
|
|
rgroup.long 0x00++0xB
|
|
line.long 0x00 "UID[31:0],Unique device ID register"
|
|
line.long 0x04 "UID[63:32],Unique device ID register"
|
|
sif (cpuis("STM32F050G6"))||(cpuis("STM32F038?6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F091?C"))||(cpuis("STM32F098?C"))
|
|
hexmask.long.tbyte 0x04 8.--31. 1. " UID[63:40] ,LOT_NUM[23:0]"
|
|
hexmask.long.byte 0x04 0.--7. 1. " UID[39:32] ,WAF_NUM[7:0]"
|
|
endif
|
|
line.long 0x08 "UID[95:64],Unique device ID register"
|
|
rgroup.word 0x20++0x1
|
|
line.word 0x00 "FLASH_SIZE,Flash size data register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
endif
|
|
sif (cpuis("STM32F050G6")||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091?B")||cpuis("STM32F091?C")||cpuis("STM32F098?C")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F051T8"))
|
|
tree "DBG (Debug support)"
|
|
base ad:0x40015800
|
|
width 16.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DBGMCU_IDCODE,MCU device ID code"
|
|
sif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")
|
|
hexmask.long.word 0x00 16.--31. 1. " REV_ID ,Revision Identifier"
|
|
bitfld.long 0x00 12.--15. " DIV_ID ,Division identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " DEV_ID ,Device Identifier"
|
|
textline " "
|
|
else
|
|
hexmask.long.word 0x00 16.--31. 1. " REV_ID ,Revision Identifier"
|
|
hexmask.long.word 0x00 0.--11. 1. " DEV_ID ,Device Identifier"
|
|
endif
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "DBGMCU_CR,Debug MCU Configuration Register"
|
|
sif (CPU()!="STM32F050C4"&&CPU()!="STM32F050C6"&&CPU()!="STM32F050K4"&&CPU()!="STM32F050K6"&&CPU()!="STM32F051C4"&&CPU()!="STM32F051C6"&&CPU()!="STM32F051C8"&&CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8"&&CPU()!="STM32F051R4"&&CPU()!="STM32F051R6"&&CPU()!="STM32F051R8")&&!(cpuis("STM32F038?6"))&&!(cpuis("STM32F048?6"))&&!(cpuis("STM32F058?8"))&&!(cpuis("STM32F078?B"))&&!(cpuis("STM32F091?B"))&&!(cpuis("STM32F098?C"))&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6.--7. " TRACE_MODE ,Trace Pin Assignment Control" "Asynchronous,Synchronous/TRACEDATA=1,Synchronous/TRACEDATA=2,Synchronous/TRACEDATA=4"
|
|
bitfld.long 0x00 5. " TRACE_IOEN ,Trace Pin Assignment Control" "Not assigned,Assigned"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F038?6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F098?C"))||(cpuis("STM32F410*"))||(cpuis("STM32F412*"))||(cpuis("STM32F469*"))||(cpuis("STM32F479*"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F051T8")
|
|
bitfld.long 0x00 2. " DBG_STANDBY ,Debug Standby mode" "FCLK=Off/HCLK=Off,FCLK=On/HCLK=On"
|
|
bitfld.long 0x00 1. " DBG_STOP ,Debug Stop Mode" "FCLK=Off/HCLK=Off,FCLK=On/HCLK=On"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F038?6"))&&!(cpuis("STM32F048?6"))&&!(cpuis("STM32F058?8"))&&!(cpuis("STM32F078?B"))&&!(cpuis("STM32F091?B"))&&!(cpuis("STM32F098?C"))&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 0. " DBG_SLEEP ,Debug Sleep Mode" "FCLK=On/HCLK=Off,FCLK=On/HCLK=On"
|
|
textline " "
|
|
endif
|
|
line.long 0x04 "DBGMCU_APB1_FZ,Debug MCU APB1 freeze register"
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*"))
|
|
sif (!cpuis("STM32F401*"))&&!(cpuis("STM32F411*"))&&!(cpuis("STM32F410*"))&&!(cpuis("STM32F413*"))&&!(cpuis("STM32F423?H"))
|
|
bitfld.long 0x04 26. " DBG_CAN2_STOP ,Debug CAN2 stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 25. " DBG_CAN1_STOP ,Debug CAN1 stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F466*")||cpuis("STM32F469*")||cpuis("STM32F479*"))||(cpuis("STM32F410*")&&!cpuis("STM32F410T*"))||(cpuis("STM32F412*"))||(cpuis("STM32F479*"))||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x04 24. " DBG_I2CFMP_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F410*")
|
|
bitfld.long 0x04 22. " DBG_I2C2_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 23. " DBG_I2C3_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 22. " DBG_I2C2_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 21. " DBG_I2C1_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 12. " DBG_IWDG_STOP ,Debug independent watchdog stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 11. " DBG_WWDG_STOP ,Debug Window Wachdog stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 10. " DBG_RTC_STOP ,RTC stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
sif (!cpuis("STM32F401*")&&!cpuis("STM32F411*")&&!cpuis("STM32F410*")&&!(cpuis("STM32F413*"))&&!(cpuis("STM32F423?H")))
|
|
bitfld.long 0x04 8. " DBG_TIM14_STOP ,TIM14 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 7. " DBG_TIM13_STOP ,TIM13 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DBG_TIM12_STOP ,TIM12 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 5. " DBG_TIM7_STOP ,TIM7 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
elif cpuis("STM32F410*")&&!(cpuis("STM32F413*"))&&!(cpuis("STM32F423?H"))
|
|
bitfld.long 0x04 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F413*"))&&!(cpuis("STM32F423?H"))
|
|
bitfld.long 0x04 3. " DBG_TIM5_STOP ,TIM5 counter stopped when core is halted" "Started,Stopped"
|
|
endif
|
|
sif !cpuis("STM32F410*")&&!(cpuis("STM32F413*"))&&!(cpuis("STM32F423?H"))
|
|
bitfld.long 0x04 2. " DBG_TIM4_STOP ,TIM4 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DBG_TIM3_STOP ,TIM3 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 0. " DBG_TIM2_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped"
|
|
endif
|
|
elif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")||(cpuis("STM32F050G6"))||(cpuis("STM32F038?6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F098?C"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F051T8")
|
|
sif (cpuis("STM32F050G6"))||(cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8")&&!cpuis("STM32F058T8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F098?C"))
|
|
bitfld.long 0x04 25. " DBG_CAN_STOP ,Debug CAN stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 21. " DBG_I2C1_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DBG_IWDG_STOP ,Debug independent watchdog stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 11. " DBG_WWDG_STOP ,Debug Window Watchdog stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DBG_RTC_STOP ,RTC stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 8. " DBG_TIM14_STOP ,TIM14 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
sif (cpuis("STM32F050G6"))||(cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8")&&!cpuis("STM32F058T8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F098?C"))||cpuis("STM32F070RB")||cpuis("STM32F070CB")||cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x04 5. " DBG_TIM7_STOP ,TIM7 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")||cpuis("STM32F058T8")||cpuis("STM32F051T8")
|
|
bitfld.long 0x04 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 1. " DBG_TIM3_STOP ,TIM3 counter stopped when core is halted" "Started,Stopped"
|
|
sif (!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB"))
|
|
textline " "
|
|
bitfld.long 0x04 0. " DBG_TIM2_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped"
|
|
endif
|
|
else
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x04 25. " DBG_CAN_STOP ,Debug CAN stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 22. " DBG_I2C2_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 21. " DBG_I2C1_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DBG_IWDG_STOP ,Debug Independent Watchdog stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 11. " DBG_WWDG_STOP ,Debug Window Watchdog stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x04 10. " DBG_RTC_STOP ,RTC stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x04 9. " DBG_TIM18_STOP ,TIM18 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 8. " DBG_TIM14_STOP ,TIM14 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DBG_TIM13_STOP ,TIM13 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 6. " DBG_TIM12_STOP ,TIM12 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 5. " DBG_TIM7_STOP ,TIM7 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
sif (cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x04 3. " DBG_TIM5_STOP ,TIM5 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 2. " DBG_TIM4_STOP ,TIM4 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 1. " DBG_TIM3_STOP ,TIM3 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 0. " DBG_TIM2_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped"
|
|
endif
|
|
line.long 0x08 "DBGMCU_APB2_FZ,Debug MCU APB2 freeze register"
|
|
sif !cpuis("STM32F413*")&&!cpuis("STM32F423?H")
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*"))
|
|
bitfld.long 0x08 18. " DBG_TIM11_STOP ,TIM11 counter stopped when core is halted" "Started,Stopped"
|
|
sif (!cpuis("STM32F410*"))
|
|
bitfld.long 0x08 17. " DBG_TIM10_STOP ,TIM10 counter stopped when core is halted" "Started,Stopped"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 16. " DBG_TIM9_STOP ,TIM9 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
sif (!cpuis("STM32F401*")&&!cpuis("STM32F411*")&&!cpuis("STM32F410*"))
|
|
bitfld.long 0x08 1. " DBG_TIM8_STOP ,TIM8 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 0. " DBG_TIM1_STOP ,TIM1 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
elif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")||(cpuis("STM32F050G6"))||(cpuis("STM32F038?6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F098?C"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F051T8")
|
|
bitfld.long 0x08 18. " DBG_TIM17_STOP ,TIM17 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x08 17. " DBG_TIM16_STOP ,TIM16 counter stopped when core is halted" "Started,Stopped"
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")||(cpuis("STM32F050G6"))||(cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F098?C"))||cpuis("STM32F051T8")||cpuis("STM32F070CB")||cpuis("STM32F070RB")||cpuis("STM32F030CC")||cpuis("STM32F030RC")
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|
textline " "
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|
bitfld.long 0x08 16. " DBG_TIM15_STOP ,TIM15 counter stopped when core is halted" "Started,Stopped"
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|
endif
|
|
textline " "
|
|
bitfld.long 0x08 11. " DBG_TIM1_STOP ,TIM1 counter stopped when core is halted" "Started,Stopped"
|
|
elif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
sif (cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x08 5. " DBG_TIM19_STOP ,TIM19 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 4. " DBG_TIM17_STOP ,TIM17 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x08 3. " DBG_TIM16_STOP ,TIM16 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 2. " DBG_TIM15_STOP ,TIM15 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.long 0x08 1. " DBG_TIM8_STOP ,TIM8 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x08 0. " DBG_TIM1_STOP ,TIM1 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x08 4. " DBG_TIM11_STOP ,TIM4 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x08 3. " DBG_TIM10_STOP ,TIM3 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 2. " DBG_TIM9_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
textline " "
|