28667 lines
1.9 MiB
28667 lines
1.9 MiB
; --------------------------------------------------------------------------------
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; @Title: R7FS3 On-Chip Peripherals
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; @Props: Released
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; @Author: KOL
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; @Changelog: 2016-11-07 KOL
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; @Manufacturer: RENESAS - Renesas Technology, Corp.
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; @Doc: r01do0002eu0100_synergy_r7fs3.pdf (Rev. 1, 2016-02-23)
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; r01ds0263eu0100_synergy_r7fs3.pdf (Rev. 1, 2016-02-23)
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; r01um0002eu0100_synergy_r7fs3.pdf (Rev. 1, 2016-02)
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; @Chip: R7FS3A77C2A01CBJ, R7FS3A77C2A01CLJ, R7FS3A77C2A01CLK,
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; R7FS3A77C3A01CFB, R7FS3A77C3A01CFM, R7FS3A77C3A01CFP,
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; R7FS3A77C3A01CNB
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; @Core: Cortex-M4
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perr7fs3.per 17736 2024-04-08 09:26:07Z kwisniewski $
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width 0x0B
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "DBGREG (Debug Register)"
|
|
base ad:0x4001B000
|
|
width 11.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DBGSTR,Debug Status Register"
|
|
bitfld.long 0x00 29. " CDBGPWRUPACK ,Debug power-up acknowledge" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 28. " CDBGPWRUPACK ,Debug power-up request" "Not requested,Requested"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DBGSTOPCR,Debug Stop Control Register"
|
|
bitfld.long 0x00 25. " DBGSTOP_RECCR ,Mask bit for SRAM ECC error reset/interrupt" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " DBGSTOP_RPER ,Mask bit for SRAM parity error reset/interrupt" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " DBGSTOP_LVD2 ,Mask bit for LVD2 reset/interrupt" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " DBGSTOP_LVD1 ,Mask bit for LVD1 reset/interrupt" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DBGSTOP_LVD0 ,Mask bit for LVD0 reset/interrupt" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " DBGSTOP_WDT ,Mask bit for WDT reset/interrupt" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " DBGSTOP_IWDT ,Mask bit for IWDT reset/interrupt" "Not masked,Masked"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TRACECTR,Trace Control Register"
|
|
bitfld.long 0x00 31. " ENETBFULL ,Enabled bit for halt request by ETB full" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "OCDREG (On-Chip Debug Register)"
|
|
base ad:0x80000000
|
|
width 9.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "IAUTH0,ID Authentication Code Register 0"
|
|
wgroup.long 0x100++0x03
|
|
line.long 0x00 "IAUTH1,ID Authentication Code Register 1"
|
|
wgroup.long 0x200++0x03
|
|
line.long 0x00 "IAUTH2,ID Authentication Code Register 2"
|
|
wgroup.long 0x300++0x03
|
|
line.long 0x00 "IAUTH3,ID Authentication Code Register 3"
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "MCUSTAT,MCU Status Register"
|
|
bitfld.long 0x00 2. " CPUSTOPCLK ,CPU stop clock" "Not stopped,Stopped"
|
|
bitfld.long 0x00 1. " CPUSLEEP ,CPU sleep" "Non-sleep mode,Sleep mode"
|
|
bitfld.long 0x00 0. " AUTH ,Authentication" "Failed,Succeeded"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "MCUCTRL,MCU Control Register"
|
|
bitfld.long 0x00 8. " DBIRQ ,Debug Interrupt Request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " EDBGRQ ,External Debug Request" "Not requested,Requested"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MMF (Memory Mirror Function)"
|
|
base ad:0x40001000
|
|
width 7.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "MMSFR,MemMirror Special Function Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,MMSFR key code"
|
|
hexmask.long.tbyte 0x00 7.--22. 0x80 " MEMMIRADDR ,Memory mirror address"
|
|
line.long 0x04 "MMEN,MemMirror Enable Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " KEY ,MMEN key code"
|
|
bitfld.long 0x04 0. " EN ,Memory mirror function enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Resets"
|
|
base ad:0x4001E0C0
|
|
width 8.
|
|
group.byte 0x350++0x00
|
|
line.byte 0x00 "RSTSR0,Reset Status Register 0"
|
|
bitfld.byte 0x00 3. " LVD2RF ,Voltage Monitor 2 Reset Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " LVD1RF ,Voltage Monitor 1 Reset Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 1. " LVD0RF ,Voltage Monitor 0 Reset Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " PORF ,Power-On Reset Detect Flag" "Not detected,Detected"
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "RSTSR1,Reset Status Register 1"
|
|
bitfld.word 0x00 12. " SPERF ,SP Error Reset Detect Flag" "Not detected,Detected"
|
|
bitfld.word 0x00 11. " BUSMRF ,Bus Master MPU Error Reset Detect Flag" "Not detected,Detected"
|
|
bitfld.word 0x00 10. " BUSSRF ,Bus Slave MPU Error Reset Detect Flag" "Not detected,Detected"
|
|
bitfld.word 0x00 9. " REERF ,SRAM ECC Error Reset Detect Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 8. " RPERF ,SRAM Parity Error Reset Detect Flag " "Not detected,Detected"
|
|
bitfld.word 0x00 2. " SWRF ,Software Reset Detect Flag" "Not detected,Detected"
|
|
bitfld.word 0x00 1. " WDTRF ,Watchdog Timer Reset Detect Flag" "Not detected,Detected"
|
|
bitfld.word 0x00 0. " IWDTRF ,Independent Watchdog Timer Reset Detect Flag" "Not detected,Detected"
|
|
group.byte 0x351++0x00
|
|
line.byte 0x00 "RSTSR2,Reset Status Register 2"
|
|
bitfld.byte 0x00 0. " CWSF ,Cold/Warm Start Determination Flag" "Cold,Warm"
|
|
width 0x0B
|
|
tree.end
|
|
tree "OSM (Option-Setting Memory)"
|
|
base ad:0x00000400
|
|
width 7.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "OFS0,Option Function Select Register 0"
|
|
bitfld.long 0x00 30. " WDTSTPCTL ,WDT Stop Control" "Not stopped,Stopped"
|
|
bitfld.long 0x00 28. " WDTRSTIRQS ,WDT Reset Interrupt Request Select" "NMI,Reseted"
|
|
bitfld.long 0x00 26.--27. " WDTRPSS ,WDT Window Start Position Select" "25%,50%,75%,100%"
|
|
bitfld.long 0x00 24.--25. " WDTRPES ,WDT Window End Position Select" "75%,50%,25%,0%"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " WDTCKS ,WDT Clock Frequency Division Ratio Select" ",/4,,,/64,,/512,/2048,/8192,,,,,,,/128"
|
|
bitfld.long 0x00 18.--19. " WDTTOPS ,WDT Timeout Period Select" "1024 cycles,4096 cycles,8192 cycles,16384 cycles"
|
|
bitfld.long 0x00 17. " WDTSTRT ,WDT Start Mode Select" "Auto-start mode,Register-start mode"
|
|
bitfld.long 0x00 14. " IWDTSTPCTL ,IWDT Stop Control" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IWDTRSTIRQS ,IWDT Reset Interrupt Request Select" "Non-maskable or maskable interrupt,Reset enabled"
|
|
bitfld.long 0x00 10.--11. " IWDTRPSS ,IWDT Window Start Position Select" "25%,50%,75%,100%"
|
|
bitfld.long 0x00 8.--9. " IWDTRPES ,IWDT Window End Position Select" "75%,50%,25%,0%"
|
|
bitfld.long 0x00 4.--7. " IWDTCKS ,IWDT-Dedicated Clock Frequency Division Ratio Select" "x1,,x1/16,x1/32,x1/64,x1/256,,,,,,,,,,x1/128"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " IWDTTOPS ,IWDT Timeout Period Select" "128 cycles,512 cycles,1024 cycles,2048 cycles"
|
|
bitfld.long 0x00 1. " IWDTSTRT ,IWDT Start Mode Select" "Auto-start mode,Disabled"
|
|
line.long 0x04 "OFS1,Option Function Select Register 1"
|
|
bitfld.long 0x04 12.--14. " HOCOFRQ1 ,HOCO Frequency Setting 1" "24 MHz,,32 MHz,,48 MHz,64 MHz,,"
|
|
bitfld.long 0x04 8. " HOCOEN ,HOCO Oscillation Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 3.--5. " VDSEL1 ,Voltage Detection 0 Level Select" "3.84 V,2.82 V,2.51 V,1.90 V,1.70 V,,,"
|
|
bitfld.long 0x04 2. " LVDAS ,Voltage Detection 0 Circuit Start" "Enabled,Disabled"
|
|
rgroup.long ad:0x01010008++0x03
|
|
line.long 0x00 "AWSC,Access Window Setting Control Register"
|
|
bitfld.long 0x00 14. " FSPR ,Protection of Access Window and Start-Up Area Select Function" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " BTFLG ,Start-Up Area Select Flag" "Exchanged,Not exchanged"
|
|
rgroup.long (ad:0x01010008+0x08)++0x03
|
|
line.long 0x00 "AWS,Access Window Setting Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " FAWE ,Access Window End Block Address"
|
|
hexmask.long.word 0x00 0.--11. 1. " FAWS ,Access Window Start Block Address"
|
|
group.long (ad:0x01010008+0x10)++0x03
|
|
line.long 0x00 "OSIS1,OCD/Serial Programmer ID Setting Register 1"
|
|
group.long (ad:0x01010008+0x18)++0x03
|
|
line.long 0x00 "OSIS2,OCD/Serial Programmer ID Setting Register 2"
|
|
group.long (ad:0x01010008+0x20)++0x03
|
|
line.long 0x00 "OSIS3,OCD/Serial Programmer ID Setting Register 3"
|
|
group.long (ad:0x01010008+0x28)++0x03
|
|
line.long 0x00 "OSIS4,OCD/Serial Programmer ID Setting Register 4"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LVD (Low Voltage Detection)"
|
|
base ad:0x4001E0E0
|
|
width 9.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "LVD1CR1,Voltage Monitor 1 Circuit Control Register 1"
|
|
bitfld.byte 0x00 2. " IRQSEL ,Voltage Monitor 1 Interrupt Type Select" "Not-maskable,Maskable"
|
|
bitfld.byte 0x00 0.--1. " IDTSEL ,Voltage Monitor 1 Interrupt Generation Condition Select" "Rise,Drop,Both,"
|
|
line.byte 0x01 "LVD1SR,Voltage Monitor 1 Circuit Status Register"
|
|
rbitfld.byte 0x01 1. " MON ,Voltage Monitor 1 Signal Monitor Flag" "Dropped,Rised or disabled"
|
|
bitfld.byte 0x01 0. " DET ,Voltage Monitor 1 Voltage Changen Detection Flag" "Not detected,Detected"
|
|
line.byte 0x02 "LVD2CR1,Voltage Monitor 2 Circuit Control Register 1"
|
|
bitfld.byte 0x02 2. " IRQSEL ,Voltage Monitor 2 Interrupt Type Select" "Not-maskable,Maskable"
|
|
bitfld.byte 0x02 0.--1. " IDTSEL ,Voltage Monitor 2 Interrupt Generation Condition Select" "Rise,Drop,Both,"
|
|
line.byte 0x03 "LVD2SR,Voltage Monitor 2 Circuit Status Register"
|
|
rbitfld.byte 0x03 1. " MON ,Voltage Monitor 2 Signal Monitor Flag" "Dropped,Rised or disabled"
|
|
bitfld.byte 0x03 0. " DET ,Voltage Monitor 2 Voltage Changen Detection Flag" "Not detected,Detected"
|
|
group.byte ad:0x4001E417++0x01
|
|
line.byte 0x00 "LVCMPCR,Voltage Monitor Circuit Control Register"
|
|
bitfld.byte 0x00 6. " LVD2E ,Voltage Detection 2 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LVD1E ,Voltage Detection 1 Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "LVDLVLR,Voltage Detection Level Select Register"
|
|
bitfld.byte 0x01 5.--7. " LVD2LVL ,Voltage Detection 2 Level Select" "4.29 V,4.14 V,4.02 V,3.84 V,,,,"
|
|
bitfld.byte 0x01 0.--4. " LVD1LVL ,Voltage Detection 1 Level Select" "4.29 V,4.14 V,4.02 V,3.84 V,3.10 V,3.00 V,2.90 V,2.79 V,2.68 V,2.58 V,2.48 V,2.20 V,1.96 V,1.86 V,1.75 V,1.65 V,?..."
|
|
group.byte (ad:0x4001E417+0x03)++0x01
|
|
line.byte 0x00 "LVD1CR0,Voltage Monitor 1 Circuit Control Register 0"
|
|
bitfld.byte 0x00 7. " RN ,Voltage Monitor 1 Reset Negate Select" "VCC > Vdet1 detected,LVD1 reset"
|
|
bitfld.byte 0x00 6. " RI ,Voltage Monitor 1 Circuit Mode Select" "Interrupt,Reset"
|
|
bitfld.byte 0x00 2. " CMPE ,Voltage Monitor 1 Circuit Comparison Result Output Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RIE ,Voltage Monitor 1 Interrupt/Reset Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "LVD2CR0,Voltage Monitor 2 Circuit Control Register 0"
|
|
bitfld.byte 0x01 7. " RN ,Voltage Monitor 2 Reset Negate Select" "VCC > Vdet2 detected,LVD2 reset"
|
|
bitfld.byte 0x01 6. " RI ,Voltage Monitor 2 Circuit Mode Select" "Interrupt,Reset"
|
|
bitfld.byte 0x01 2. " CMPE ,Voltage Monitor 2 Circuit Comparison Result Output Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " RIE ,Voltage Monitor 2 Interrupt/Reset Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CGC (Clock Generation Circuit)"
|
|
base ad:0x4001E020
|
|
width 11.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCKDIVCR,System Clock Division Control Register"
|
|
bitfld.long 0x00 28.--30. " FCK ,FlashIF clock (FCLK) select" "x1/1,x1/2,x1/4,x1/8,x1/16,x1/32,x1/64,"
|
|
bitfld.long 0x00 24.--26. " ICK ,System clock (ICLK) select" "x1/1,x1/2,x1/4,x1/8,x1/16,x1/32,x1/64,"
|
|
bitfld.long 0x00 16.--18. " BCK ,External bus clock (BCLK) select" "x1/1,x1/2,x1/4,x1/8,x1/16,x1/32,x1/64,"
|
|
bitfld.long 0x00 12.--14. " PCKA ,Peripheral module clock a (PCLKA) select" "x1/1,x1/2,x1/4,x1/8,x1/16,x1/32,x1/64,"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " PCKB ,Peripheral module clock b (PCLKB) select" "x1/1,x1/2,x1/4,x1/8,x1/16,x1/32,x1/64,"
|
|
bitfld.long 0x00 4.--6. " PCKC ,Peripheral module clock c (PCLKC) select" "x1/1,x1/2,x1/4,x1/8,x1/16,x1/32,x1/64,"
|
|
bitfld.long 0x00 0.--2. " PCKD ,Peripheral module clock d (PCLKD) select" "x1/1,x1/2,x1/4,x1/8,x1/16,x1/32,x1/64,"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCKSCR,System Clock Source Control Register"
|
|
bitfld.byte 0x00 0.--2. " CKSEL ,Clock source select" "HOCO,MOCO,LOCO,MOSC,SOSC,PLL,?..."
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "PLLCCR2,PLL Clock Control Register 2"
|
|
bitfld.byte 0x00 6.--7. " PLODIV ,PLL output frequency division ratio select" "/1,/2,/4,"
|
|
bitfld.byte 0x00 0.--4. " PLLMUL ,PLL frequency multiplication factor select" ",,,,,,,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18,x19,x20,x21,x22,x23,x24,x25,x26,x27,x28,x29,x30,x31,"
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "PLLCR,PLL Control Register"
|
|
bitfld.byte 0x00 0. " PLLSTP ,PLL stop control" "Not stopped,Stopped"
|
|
group.byte 0x10++0x02
|
|
line.byte 0x00 "BCKCR,External Bus Clock Control Register"
|
|
bitfld.byte 0x00 0. " BCLKDIV ,EBCLK pin output select" "BCLK,BCLK/2"
|
|
line.byte 0x01 "MEMWAIT,Memory Wait Cycle Control Register"
|
|
bitfld.byte 0x01 0. " MEMWAIT ,Memory wait cycle select" "Not waiting,Waiting"
|
|
line.byte 0x02 "MOSCCR,Main Clock Oscillator Control Register"
|
|
bitfld.byte 0x02 0. " MOSTP ,Main clock oscillator stop" "Not stopped,Stopped"
|
|
group.byte (ad:0x4001E410+0x70)++0x00
|
|
line.byte 0x00 "SOSCCR,Sub-Clock Oscillator Control Register"
|
|
bitfld.byte 0x00 0. " SOSTP ,Sub-Clock oscillator stop" "Not stopped,Stopped"
|
|
group.byte (ad:0x4001E410+0x80)++0x00
|
|
line.byte 0x00 "LOCOCR,Low-Speed On-Chip Oscillator Control Register"
|
|
bitfld.byte 0x00 0. " LCSTP ,LOCO stop" "Not stopped,Stopped"
|
|
if (((per.b(ad:0x4001E000+0xA0))&0x10)==0x10)||(((per.b(ad:0x4001E000+0xAA))&0x10)==0x10)||(((per.b(ad:0x4001E000+0x9E))&0x10)==0x10)
|
|
rgroup.byte 0x16++0x00
|
|
line.byte 0x00 "HOCOCR,High-Speed On-Chip Oscillator Control Register"
|
|
bitfld.byte 0x00 0. " HCSTP ,HOCO stop" "Not stopped,Stopped"
|
|
else
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "HOCOCR,High-Speed On-Chip Oscillator Control Register"
|
|
bitfld.byte 0x00 0. " HCSTP ,HOCO stop" "Not stopped,Stopped"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MOCOCR,Middle-Speed On-Chip Oscillator Control Register"
|
|
bitfld.byte 0x00 0. " MCSTP ,MOCO stop" "Not stopped,Stopped"
|
|
rgroup.byte 0x1C++0x00
|
|
line.byte 0x00 "OSCSF,Oscillation Stabilization Flag Register"
|
|
bitfld.byte 0x00 5. " PLLSF ,PLL clock oscillation stabilization flag" "Not stable,Stable"
|
|
bitfld.byte 0x00 3. " MOSCSF ,Main clock oscillation stabilization flag" "Not stable,Stable"
|
|
bitfld.byte 0x00 0. " HOCOSF ,HOCO clock oscillation stabilization flag" "Not stable,Stable"
|
|
group.byte 0x20++0x01
|
|
line.byte 0x00 "OSTDCR,Oscillation Stop Detection Control Register"
|
|
bitfld.byte 0x00 7. " OSTDE ,Oscillation stop detection function enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " OSTDIE ,Oscillation stop detection interrupt enable" "Disabled,Enabled"
|
|
line.byte 0x01 "OSTDSR,Oscillation Stop Detection Status Register"
|
|
bitfld.byte 0x01 0. " OSTDF ,Oscillation stop detection flag" "Not detected,Detected"
|
|
group.byte 0x82++0x00
|
|
line.byte 0x00 "MOSCWTCR,Main Clock Oscillator Wait Control Register"
|
|
bitfld.byte 0x00 0.--3. " MSTS ,Main clock oscillator wait time setting" "2 cycles,1024 cycles,2048 cycles,4096 cycles,8192 cycles,16384 cycles,32768 cycles,65536 cycles,131072 cycles,262144 cycles,?..."
|
|
if (((per.l(ad:0x00000404+0xA0))&0x7000)==(0x0000||0x2000||0x4000))
|
|
if (((per.b(ad:0x4001E000))&0x03)==0x02)
|
|
group.byte 0x85++0x00
|
|
line.byte 0x00 "HOCOWTCR,High-Speed On-Chip Oscillator Wait Control Register"
|
|
bitfld.byte 0x00 0.--2. " HSTS ,HOCO wait time setting" ",,,,,679 cycles,?..."
|
|
else
|
|
group.byte 0x85++0x00
|
|
line.byte 0x00 "HOCOWTCR,High-Speed On-Chip Oscillator Wait Control Register"
|
|
bitfld.byte 0x00 0.--2. " HSTS ,HOCO wait time setting" ",,,,,245 cycles,?..."
|
|
endif
|
|
elif (((per.l(ad:0x00000404))&0x7000)==0x5000)
|
|
group.byte 0x85++0x00
|
|
line.byte 0x00 "HOCOWTCR,High-Speed On-Chip Oscillator Wait Control Register"
|
|
bitfld.byte 0x00 0.--2. " HSTS ,HOCO wait time setting" ",,,,,,541 cycles,?..."
|
|
endif
|
|
group.byte (ad:0x4001E410+0x03)++0x00
|
|
line.byte 0x00 "MOMCR,Main Clock Oscillator Mode Oscillation Control Register"
|
|
bitfld.byte 0x00 6. " MOSEL ,Main clock oscillator switching" "Resonator,External clock input"
|
|
bitfld.byte 0x00 3. " MODRV1 ,Main clock oscillator drive capability 1 switching" "10 MHz to 20 MHz,1 MHz to 10 MHz"
|
|
group.byte (ad:0x4001E410+0x71)++0x00
|
|
line.byte 0x00 "SOMCR,Sub-Clock Oscillator Mode Control Register"
|
|
bitfld.byte 0x00 0.--1. " SODRV ,Sub-Clock oscillator drive apability switching" "Normal mode,Low power mode 1,Low power mode 2,Low power mode 3"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "SLCDSCKCR,Segment LCD Source Clock Control Register"
|
|
bitfld.byte 0x00 7. " LCDSCKEN ,LCD source clock out enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " LCDSCKSEL ,LCD source clock (LCDSRCCLK) select" "LOCO,SOSC,MOSC,,HOCO,?..."
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "CKOCR,Clock Out Control Register"
|
|
bitfld.byte 0x00 7. " CKOEN ,Clock out enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--6. " CKODIV ,Clock out input frequency division select" "x1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.byte 0x00 0.--2. " CKOSEL ,Clock out source select" "HOCO,MOCO,LOCO,MOSC,SOSC,?..."
|
|
group.byte 0x32++0x00
|
|
line.byte 0x00 "EBCKOCR,External Bus Clock Output Control Register"
|
|
bitfld.byte 0x00 0. " EBCKOEN ,EBCLK pin output control" "Disabled,Enabled"
|
|
group.byte (ad:0x4001E410+0x82)++0x00
|
|
line.byte 0x00 "LOCOUTCR,LOCO User Trimming Control Register"
|
|
group.byte 0x41++0x01
|
|
line.byte 0x00 "MOCOUTCR,MOCO User Trimming Control Register"
|
|
line.byte 0x01 "HOCOUTCR,HOCO User Trimming Control Register"
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "TRCKCR,Trace Clock Control Register"
|
|
bitfld.byte 0x00 7. " TRCKEN ,Trace clock operating enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--3. " TRCK ,Trace clock operation frequency select" "/1,/2,/4,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "CAC (Clock Frequency Accuracy Measurement Circuit)"
|
|
base ad:0x40044600
|
|
width 9.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "CACR0,CAC Control Register 0"
|
|
bitfld.byte 0x00 0. " CFME ,Clock frequency measurement enable" "Disabled,Enabled"
|
|
line.byte 0x01 "CACR1,CAC Control Register 1"
|
|
bitfld.byte 0x01 6.--7. " EDGES ,Valid edge select" "Rising,Falling,Rising/Falling,?..."
|
|
bitfld.byte 0x01 4.--5. " TCSS ,Measurement target clock frequency division ratio select" "/1,/4,/8,/32"
|
|
newline
|
|
bitfld.byte 0x01 1.--3. " FMCS ,Measurement target clock select" "Main,Sub,HOCO,MOCO,LOCO,PCLKB,IWDTCLK,?..."
|
|
bitfld.byte 0x01 0. " CACREFE ,CACREF pin input enable" "Disabled,Enabled"
|
|
line.byte 0x02 "CACR2,CAC Control Register 2"
|
|
bitfld.byte 0x02 6.--7. " DFS ,Digital filter select" "Disabled,/1,/4,/16"
|
|
bitfld.byte 0x02 4.--5. " RCDS ,Measurement reference clock frequency division ratio select" "/32,/128,/1024,/8192"
|
|
newline
|
|
bitfld.byte 0x02 1.--3. " RSCS ,Measurement reference clock select" "Main,Sub,HOCO,MOCO,LOCO,PCLKB,IWDTCLK,?..."
|
|
bitfld.byte 0x02 0. " RPS ,Reference signal select" "CACREF,Internal"
|
|
line.byte 0x03 "CAICR,CAC Interrupt Control Register"
|
|
bitfld.byte 0x03 6. " OVFFCL ,OVFF clear" "No effect,Clear"
|
|
bitfld.byte 0x03 5. " MENDFCL ,MENDF clear" "No effect,Clear"
|
|
newline
|
|
bitfld.byte 0x03 4. " FERRFCL ,FERRF clear" "No effect,Clear"
|
|
bitfld.byte 0x03 2. " OVFIE ,Overflow interrupt request enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x03 1. " MENDIE ,Measurement end interrupt request enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 0. " FERRIE ,Frequency error interrupt request enable" "Disabled,Enabled"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "CASTR,CAC Status Register"
|
|
bitfld.byte 0x00 2. " OVFF ,Overflow flag" "No overflow,Overflow"
|
|
bitfld.byte 0x00 1. " MENDF ,Measurement end flag" "In progress,Ended"
|
|
newline
|
|
bitfld.byte 0x00 0. " FERRF ,Frequency error flag" "No error,Error"
|
|
sif (cpuis("R7FS7*"))
|
|
group.word 0x06++0x05
|
|
line.word 0x00 "CAULVR,CAC Upper-Limit Value Setting Register"
|
|
line.word 0x02 "CALLVR,CAC Lower-Limit Value Setting Register"
|
|
line.word 0x4 "CACNTBR,CAC Counter Buffer Register"
|
|
else
|
|
group.word 0x06++0x03
|
|
line.word 0x00 "CAULVR,CAC Upper-Limit Value Setting Register"
|
|
line.word 0x02 "CALLVR,CAC Lower-Limit Value Setting Register"
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "CACNTBR,CAC Counter Buffer Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "LPM (Low Power Mode)"
|
|
base ad:0x4001E000
|
|
width 10.
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SBYCR,Standby Control Register"
|
|
bitfld.word 0x00 15. " SSBY ,Software Standby" "Sleep mode,Standby mode"
|
|
bitfld.word 0x00 14. " OPE ,Output Port Enable" "Disabled,Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MSTPCRA,Module Stop Control Register A"
|
|
bitfld.long 0x00 22. " MSTPA22 ,DMA Controller/Data Transfer Controller Module Stop" "Not Stopped,Stopped"
|
|
bitfld.long 0x00 6. " MSTPA6 ,ECCSRAM Module Stop" "Not Stopped,Stopped"
|
|
bitfld.long 0x00 1. " MSTPA1 ,SRAM1 Module Stop" "Not Stopped,Stopped"
|
|
bitfld.long 0x00 0. " MSTPA0 ,SRAM0 Module Stop" "Not Stopped,Stopped"
|
|
group.long ad:0x40047000++0x0B
|
|
line.long 0x00 "MSTPCRB,Module Stop Control Register B"
|
|
bitfld.long 0x00 31. " MSTPB31 ,Serial Communication Interface 0 Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x00 30. " MSTPB30 ,Serial Communication Interface 1 Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x00 29. " MSTPB29 ,Serial Communication Interface 2 Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x00 28. " MSTPB28 ,Serial Communication Interface 3 Module Stop" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 27. " MSTPB27 ,Serial Communication Interface 4 Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x00 22. " MSTPB22 ,Serial Communication Interface 9 Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x00 19. " MSTPB19 ,Serial Peripheral Interface 0 Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x00 18. " MSTPB18 ,Serial Peripheral Interface 1 Module Stop" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MSTPB11 ,Universal Serial Bus 2.0 FS Interface Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x00 9. " MSTPB9 ,I2C Bus Interface 0 Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x00 8. " MSTPB8 ,I2C Bus Interface 1 Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x00 7. " MSTPB7 ,I2C Bus Interface 2 Module Stop" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 6. " MSTPB6 ,Quad Serial Peripheral Interface Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x00 5. " MSTPB5 ,IrDA Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " MSTPB2 ,Controller Area Network Module Stop" "Not stopped,Stopped"
|
|
line.long 0x04 "MSTPCRC,Module Stop Control Register C"
|
|
bitfld.long 0x04 31. " MSTPC31 ,SCE5 Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x04 14. " MSTPC14 ,Event Link Controller Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x04 13. " MSTPC13 ,Data Operation Circuit Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x04 12. " MSTPC12 ,Secure Digital Host Interface/Multi Media Card Interface Module Stop" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 8. " MSTPC8 ,Synchronous Serial Interface 0 Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x04 7. " MSTPC7 ,Synchronous Serial Interface 1 Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x04 4. " MSTPC4 ,Segment LCD Controller Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x04 3. " MSTPC3 ,Capacitive Touch Sensing Unit Module Stop" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MSTPC1 ,Cyclic Redundancy Check Calculator Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x04 0. " MSTPC0 ,Clock Frequency Accuracy Measurement Circuit Module Stop" "Not stopped,Stopped"
|
|
line.long 0x08 "MSTPCRD,Module Stop Control Register D"
|
|
bitfld.long 0x08 31. " MSTPD31 ,Operational Amplifier Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x08 30. " MSTPD30 ,High-Speed Analog Comparator 1 Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x08 29. " MSTPD29 ,Low-Power Analog Comparator Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x08 28. " MSTPD28 ,High-Speed Analog Comparator 0 Module Stop" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 20. " MSTPD20 ,12-Bit D/A Converter Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x08 16. " MSTPD16 ,14-Bit A/D Converter Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x08 14. " MSTPD14 ,Port Output Enable for GPT Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x08 6. " MSTPD6 ,General PWM Timer 329 to 324 Module Stop" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 5. " MSTPD5 ,General PWM Timer 323 to 320 Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x08 3. " MSTPD3 ,Asynchronous General Purpose Timer 0 Module Stop" "Not stopped,Stopped"
|
|
bitfld.long 0x08 2. " MSTPD2 ,Asynchronous General Purpose Timer 1 Module Stop" "Not stopped,Stopped"
|
|
if (((per.b(ad:0x4001E020+0x16))&0x1)==0x0)&&(((per.b(ad:0x4001E020+0x1C))&0x1)==0x0)
|
|
rgroup.byte 0xA0++0x00
|
|
line.byte 0x00 "OPCCR,Operating Power Control Register"
|
|
bitfld.byte 0x00 4. " OPCMTSF ,Operating Power Control Mode Transition Status Flag" "Completed,Not completed"
|
|
bitfld.byte 0x00 0.--1. " OPCM ,Operating Power Control Mode Select" "High-speed,Middle-speed,Low-voltage,Low-speed"
|
|
else
|
|
group.byte 0xA0++0x00
|
|
line.byte 0x00 "OPCCR,Operating Power Control Register"
|
|
rbitfld.byte 0x00 4. " OPCMTSF ,Operating Power Control Mode Transition Status Flag" "Completed,Not completed"
|
|
bitfld.byte 0x00 0.--1. " OPCM ,Operating Power Control Mode Select" "High-speed,Middle-speed,Low-voltage,Low-speed"
|
|
endif
|
|
group.byte 0xAA++0x00
|
|
line.byte 0x00 "SOPCCR,Sub Operating Power Control Register"
|
|
rbitfld.byte 0x00 4. " SOPCMTSF ,Sub Operating Power Control Mode Transition Status Flag" "Completed,Not completed"
|
|
bitfld.byte 0x00 0. " SOPCM ,Sub Operating Power Control Mode Select" "Non-subosc mode,Subosc mode"
|
|
group.byte 0x92++0x00
|
|
line.byte 0x00 "SNZCR,Snooze Control Register"
|
|
bitfld.byte 0x00 7. " SNZE ,Snooze mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SNZDTCEN ,DTC Enable in Snooze mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RXDREQEN ,RXD0 Snooze Request Enable" "Ignored,Detected"
|
|
group.byte 0x94++0x00
|
|
line.byte 0x00 "SNZEDCR,Snooze End Control Register"
|
|
bitfld.byte 0x00 7. " SCI0UMTED ,SCI0 Address Mismatch Snooze End Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " AD0UMTED ,ADC140 Compare Mismatch Snooze End Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " AD0MATED ,ADC140 Compare Match Snooze End Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " DTCNZRED ,Not Last DTC Transmission Completion Snooze End Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " DTCZRED ,Last DTC Transmission Completion Snooze End Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " AGTUNFED ,AGT1 Underflow Snooze End Enable" "Disabled,Enabled"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "SNZREQCR,Snooze Request Control Register"
|
|
bitfld.long 0x00 30. " SNZREQEN30 ,AGT1 Compare Match B Snooze Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SNZREQEN29 ,AGT1 Compare Match A Snooze Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SNZREQEN28 ,AGT1 Underflow Snooze Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " SNZREQEN25 ,RTC Period Snooze Request Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SNZREQEN24 ,RTC Slarm Dnooze Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SNZREQEN23 ,ACMPLP Dnooze Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SNZREQEN17 ,Key Interrupt Snooze Request" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SNZREQEN15 ,IRQ15 Pin Snooze Request Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SNZREQEN14 ,IRQ14 Pin Snooze Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SNZREQEN13 ,IRQ13 Pin Snooze Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SNZREQEN12 ,IRQ12 Pin Snooze Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SNZREQEN11 ,IRQ11 Pin Snooze Request Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SNZREQEN10 ,IRQ10 Pin Snooze Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SNZREQEN9 ,IRQ9 Pin Snooze Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SNZREQEN8 ,IRQ8 Pin Snooze Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SNZREQEN7 ,IRQ7 Pin Snooze Request Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SNZREQEN6 ,IRQ6 Pin Snooze Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SNZREQEN5 ,IRQ5 Pin Snooze Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SNZREQEN4 ,IRQ4 Pin Snooze Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SNZREQEN3 ,IRQ3 Pin Snooze Request Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SNZREQEN2 ,IRQ2 Pin Snooze Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SNZREQEN1 ,IRQ1 Pin Snooze Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SNZREQEN0 ,IRQ0 Pin Snooze Request Enable" "Disabled,Enabled"
|
|
group.byte 0x9E++0x01
|
|
line.byte 0x00 "FLSTOP,Flash Operation Control Register"
|
|
rbitfld.byte 0x00 4. " FLSTPF ,Flash Memory Operation Status Flag" "Completed,Not completed"
|
|
bitfld.byte 0x00 0. " FLSTOP ,Selecting ON/OFF of the Flash Memory Operation" "Not stopped,Stopped"
|
|
line.byte 0x01 "PSMCR,Power Save Memory Control Register"
|
|
bitfld.byte 0x01 0.--1. " PSMC ,Power Save Memory Control" "All SRAM,48-KB SRAM,,"
|
|
group.byte 0x40E++0x00
|
|
line.byte 0x00 "SYOCDCR,System Control OCD Control Register"
|
|
bitfld.byte 0x00 7. " DBGEN ,Debugger Enable bit" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BBF (Battery Backup Function)"
|
|
base ad:0x4001E400
|
|
width 13.
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "VBTCR1,VBATT Control Register 1"
|
|
bitfld.byte 0x00 0. " BPWSWSTP ,Battery Power Supply Switch Stop" "Not stopped,Stopped"
|
|
group.byte 0xB0++0x02
|
|
line.byte 0x00 "VBTCR2,VBATT Control Register 2"
|
|
bitfld.byte 0x00 6.--7. " VBTLVDLVL ,VBATT Pin Low Voltage Detect Level Select" ",,2.3 V,2.1 V"
|
|
bitfld.byte 0x00 4. " VBTLVDEN ,VBATT Pin Low Voltage Detect Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "VBTSR,VBATT Status Register"
|
|
rbitfld.byte 0x01 4. " VBTRVLD ,VBATT_R Valid" "Not valid,Valid"
|
|
bitfld.byte 0x01 1. " VBTBLDF ,VBATT Battery Low Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 0. " VBTRDF ,VBATT_R Reset Detect Flag" "Not detected,Detected"
|
|
line.byte 0x02 "VBTCMPCR,VBATT Comparator Control register"
|
|
bitfld.byte 0x02 0. " VBTCMPE ,VBATT Pin Low Voltage Detect Circuit Output Enable" "Disabled,Enabled"
|
|
group.byte 0xB4++0x00
|
|
line.byte 0x00 "VBTLVDICR,VBATT Pin Low Voltage Detect Interrupt Control Register"
|
|
bitfld.byte 0x00 1. " VBTLVDISEL ,Pin Low Voltage Detect Interrupt Select" "Not maskable,Maskable"
|
|
bitfld.byte 0x00 0. " VBTLVDIE ,VBATT Pin Low Voltage Detect Interrupt Enable" "Disabled,Enabled"
|
|
tree "VBTBKR[0:511],VBATT Backup Registers"
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "VBTBKR[0],VBATT Backup Register 0"
|
|
group.byte 0x101++0x00
|
|
line.byte 0x00 "VBTBKR[1],VBATT Backup Register 1"
|
|
group.byte 0x102++0x00
|
|
line.byte 0x00 "VBTBKR[2],VBATT Backup Register 2"
|
|
group.byte 0x103++0x00
|
|
line.byte 0x00 "VBTBKR[3],VBATT Backup Register 3"
|
|
group.byte 0x104++0x00
|
|
line.byte 0x00 "VBTBKR[4],VBATT Backup Register 4"
|
|
group.byte 0x105++0x00
|
|
line.byte 0x00 "VBTBKR[5],VBATT Backup Register 5"
|
|
group.byte 0x106++0x00
|
|
line.byte 0x00 "VBTBKR[6],VBATT Backup Register 6"
|
|
group.byte 0x107++0x00
|
|
line.byte 0x00 "VBTBKR[7],VBATT Backup Register 7"
|
|
group.byte 0x108++0x00
|
|
line.byte 0x00 "VBTBKR[8],VBATT Backup Register 8"
|
|
group.byte 0x109++0x00
|
|
line.byte 0x00 "VBTBKR[9],VBATT Backup Register 9"
|
|
group.byte 0x10A++0x00
|
|
line.byte 0x00 "VBTBKR[10],VBATT Backup Register 10"
|
|
group.byte 0x10B++0x00
|
|
line.byte 0x00 "VBTBKR[11],VBATT Backup Register 11"
|
|
group.byte 0x10C++0x00
|
|
line.byte 0x00 "VBTBKR[12],VBATT Backup Register 12"
|
|
group.byte 0x10D++0x00
|
|
line.byte 0x00 "VBTBKR[13],VBATT Backup Register 13"
|
|
group.byte 0x10E++0x00
|
|
line.byte 0x00 "VBTBKR[14],VBATT Backup Register 14"
|
|
group.byte 0x10F++0x00
|
|
line.byte 0x00 "VBTBKR[15],VBATT Backup Register 15"
|
|
group.byte 0x110++0x00
|
|
line.byte 0x00 "VBTBKR[16],VBATT Backup Register 16"
|
|
group.byte 0x111++0x00
|
|
line.byte 0x00 "VBTBKR[17],VBATT Backup Register 17"
|
|
group.byte 0x112++0x00
|
|
line.byte 0x00 "VBTBKR[18],VBATT Backup Register 18"
|
|
group.byte 0x113++0x00
|
|
line.byte 0x00 "VBTBKR[19],VBATT Backup Register 19"
|
|
group.byte 0x114++0x00
|
|
line.byte 0x00 "VBTBKR[20],VBATT Backup Register 20"
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "VBTBKR[21],VBATT Backup Register 21"
|
|
group.byte 0x116++0x00
|
|
line.byte 0x00 "VBTBKR[22],VBATT Backup Register 22"
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "VBTBKR[23],VBATT Backup Register 23"
|
|
group.byte 0x118++0x00
|
|
line.byte 0x00 "VBTBKR[24],VBATT Backup Register 24"
|
|
group.byte 0x119++0x00
|
|
line.byte 0x00 "VBTBKR[25],VBATT Backup Register 25"
|
|
group.byte 0x11A++0x00
|
|
line.byte 0x00 "VBTBKR[26],VBATT Backup Register 26"
|
|
group.byte 0x11B++0x00
|
|
line.byte 0x00 "VBTBKR[27],VBATT Backup Register 27"
|
|
group.byte 0x11C++0x00
|
|
line.byte 0x00 "VBTBKR[28],VBATT Backup Register 28"
|
|
group.byte 0x11D++0x00
|
|
line.byte 0x00 "VBTBKR[29],VBATT Backup Register 29"
|
|
group.byte 0x11E++0x00
|
|
line.byte 0x00 "VBTBKR[30],VBATT Backup Register 30"
|
|
group.byte 0x11F++0x00
|
|
line.byte 0x00 "VBTBKR[31],VBATT Backup Register 31"
|
|
group.byte 0x120++0x00
|
|
line.byte 0x00 "VBTBKR[32],VBATT Backup Register 32"
|
|
group.byte 0x121++0x00
|
|
line.byte 0x00 "VBTBKR[33],VBATT Backup Register 33"
|
|
group.byte 0x122++0x00
|
|
line.byte 0x00 "VBTBKR[34],VBATT Backup Register 34"
|
|
group.byte 0x123++0x00
|
|
line.byte 0x00 "VBTBKR[35],VBATT Backup Register 35"
|
|
group.byte 0x124++0x00
|
|
line.byte 0x00 "VBTBKR[36],VBATT Backup Register 36"
|
|
group.byte 0x125++0x00
|
|
line.byte 0x00 "VBTBKR[37],VBATT Backup Register 37"
|
|
group.byte 0x126++0x00
|
|
line.byte 0x00 "VBTBKR[38],VBATT Backup Register 38"
|
|
group.byte 0x127++0x00
|
|
line.byte 0x00 "VBTBKR[39],VBATT Backup Register 39"
|
|
group.byte 0x128++0x00
|
|
line.byte 0x00 "VBTBKR[40],VBATT Backup Register 40"
|
|
group.byte 0x129++0x00
|
|
line.byte 0x00 "VBTBKR[41],VBATT Backup Register 41"
|
|
group.byte 0x12A++0x00
|
|
line.byte 0x00 "VBTBKR[42],VBATT Backup Register 42"
|
|
group.byte 0x12B++0x00
|
|
line.byte 0x00 "VBTBKR[43],VBATT Backup Register 43"
|
|
group.byte 0x12C++0x00
|
|
line.byte 0x00 "VBTBKR[44],VBATT Backup Register 44"
|
|
group.byte 0x12D++0x00
|
|
line.byte 0x00 "VBTBKR[45],VBATT Backup Register 45"
|
|
group.byte 0x12E++0x00
|
|
line.byte 0x00 "VBTBKR[46],VBATT Backup Register 46"
|
|
group.byte 0x12F++0x00
|
|
line.byte 0x00 "VBTBKR[47],VBATT Backup Register 47"
|
|
group.byte 0x130++0x00
|
|
line.byte 0x00 "VBTBKR[48],VBATT Backup Register 48"
|
|
group.byte 0x131++0x00
|
|
line.byte 0x00 "VBTBKR[49],VBATT Backup Register 49"
|
|
group.byte 0x132++0x00
|
|
line.byte 0x00 "VBTBKR[50],VBATT Backup Register 50"
|
|
group.byte 0x133++0x00
|
|
line.byte 0x00 "VBTBKR[51],VBATT Backup Register 51"
|
|
group.byte 0x134++0x00
|
|
line.byte 0x00 "VBTBKR[52],VBATT Backup Register 52"
|
|
group.byte 0x135++0x00
|
|
line.byte 0x00 "VBTBKR[53],VBATT Backup Register 53"
|
|
group.byte 0x136++0x00
|
|
line.byte 0x00 "VBTBKR[54],VBATT Backup Register 54"
|
|
group.byte 0x137++0x00
|
|
line.byte 0x00 "VBTBKR[55],VBATT Backup Register 55"
|
|
group.byte 0x138++0x00
|
|
line.byte 0x00 "VBTBKR[56],VBATT Backup Register 56"
|
|
group.byte 0x139++0x00
|
|
line.byte 0x00 "VBTBKR[57],VBATT Backup Register 57"
|
|
group.byte 0x13A++0x00
|
|
line.byte 0x00 "VBTBKR[58],VBATT Backup Register 58"
|
|
group.byte 0x13B++0x00
|
|
line.byte 0x00 "VBTBKR[59],VBATT Backup Register 59"
|
|
group.byte 0x13C++0x00
|
|
line.byte 0x00 "VBTBKR[60],VBATT Backup Register 60"
|
|
group.byte 0x13D++0x00
|
|
line.byte 0x00 "VBTBKR[61],VBATT Backup Register 61"
|
|
group.byte 0x13E++0x00
|
|
line.byte 0x00 "VBTBKR[62],VBATT Backup Register 62"
|
|
group.byte 0x13F++0x00
|
|
line.byte 0x00 "VBTBKR[63],VBATT Backup Register 63"
|
|
group.byte 0x140++0x00
|
|
line.byte 0x00 "VBTBKR[64],VBATT Backup Register 64"
|
|
group.byte 0x141++0x00
|
|
line.byte 0x00 "VBTBKR[65],VBATT Backup Register 65"
|
|
group.byte 0x142++0x00
|
|
line.byte 0x00 "VBTBKR[66],VBATT Backup Register 66"
|
|
group.byte 0x143++0x00
|
|
line.byte 0x00 "VBTBKR[67],VBATT Backup Register 67"
|
|
group.byte 0x144++0x00
|
|
line.byte 0x00 "VBTBKR[68],VBATT Backup Register 68"
|
|
group.byte 0x145++0x00
|
|
line.byte 0x00 "VBTBKR[69],VBATT Backup Register 69"
|
|
group.byte 0x146++0x00
|
|
line.byte 0x00 "VBTBKR[70],VBATT Backup Register 70"
|
|
group.byte 0x147++0x00
|
|
line.byte 0x00 "VBTBKR[71],VBATT Backup Register 71"
|
|
group.byte 0x148++0x00
|
|
line.byte 0x00 "VBTBKR[72],VBATT Backup Register 72"
|
|
group.byte 0x149++0x00
|
|
line.byte 0x00 "VBTBKR[73],VBATT Backup Register 73"
|
|
group.byte 0x14A++0x00
|
|
line.byte 0x00 "VBTBKR[74],VBATT Backup Register 74"
|
|
group.byte 0x14B++0x00
|
|
line.byte 0x00 "VBTBKR[75],VBATT Backup Register 75"
|
|
group.byte 0x14C++0x00
|
|
line.byte 0x00 "VBTBKR[76],VBATT Backup Register 76"
|
|
group.byte 0x14D++0x00
|
|
line.byte 0x00 "VBTBKR[77],VBATT Backup Register 77"
|
|
group.byte 0x14E++0x00
|
|
line.byte 0x00 "VBTBKR[78],VBATT Backup Register 78"
|
|
group.byte 0x14F++0x00
|
|
line.byte 0x00 "VBTBKR[79],VBATT Backup Register 79"
|
|
group.byte 0x150++0x00
|
|
line.byte 0x00 "VBTBKR[80],VBATT Backup Register 80"
|
|
group.byte 0x151++0x00
|
|
line.byte 0x00 "VBTBKR[81],VBATT Backup Register 81"
|
|
group.byte 0x152++0x00
|
|
line.byte 0x00 "VBTBKR[82],VBATT Backup Register 82"
|
|
group.byte 0x153++0x00
|
|
line.byte 0x00 "VBTBKR[83],VBATT Backup Register 83"
|
|
group.byte 0x154++0x00
|
|
line.byte 0x00 "VBTBKR[84],VBATT Backup Register 84"
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "VBTBKR[85],VBATT Backup Register 85"
|
|
group.byte 0x156++0x00
|
|
line.byte 0x00 "VBTBKR[86],VBATT Backup Register 86"
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "VBTBKR[87],VBATT Backup Register 87"
|
|
group.byte 0x158++0x00
|
|
line.byte 0x00 "VBTBKR[88],VBATT Backup Register 88"
|
|
group.byte 0x159++0x00
|
|
line.byte 0x00 "VBTBKR[89],VBATT Backup Register 89"
|
|
group.byte 0x15A++0x00
|
|
line.byte 0x00 "VBTBKR[90],VBATT Backup Register 90"
|
|
group.byte 0x15B++0x00
|
|
line.byte 0x00 "VBTBKR[91],VBATT Backup Register 91"
|
|
group.byte 0x15C++0x00
|
|
line.byte 0x00 "VBTBKR[92],VBATT Backup Register 92"
|
|
group.byte 0x15D++0x00
|
|
line.byte 0x00 "VBTBKR[93],VBATT Backup Register 93"
|
|
group.byte 0x15E++0x00
|
|
line.byte 0x00 "VBTBKR[94],VBATT Backup Register 94"
|
|
group.byte 0x15F++0x00
|
|
line.byte 0x00 "VBTBKR[95],VBATT Backup Register 95"
|
|
group.byte 0x160++0x00
|
|
line.byte 0x00 "VBTBKR[96],VBATT Backup Register 96"
|
|
group.byte 0x161++0x00
|
|
line.byte 0x00 "VBTBKR[97],VBATT Backup Register 97"
|
|
group.byte 0x162++0x00
|
|
line.byte 0x00 "VBTBKR[98],VBATT Backup Register 98"
|
|
group.byte 0x163++0x00
|
|
line.byte 0x00 "VBTBKR[99],VBATT Backup Register 99"
|
|
group.byte 0x164++0x00
|
|
line.byte 0x00 "VBTBKR[100],VBATT Backup Register 100"
|
|
group.byte 0x165++0x00
|
|
line.byte 0x00 "VBTBKR[101],VBATT Backup Register 101"
|
|
group.byte 0x166++0x00
|
|
line.byte 0x00 "VBTBKR[102],VBATT Backup Register 102"
|
|
group.byte 0x167++0x00
|
|
line.byte 0x00 "VBTBKR[103],VBATT Backup Register 103"
|
|
group.byte 0x168++0x00
|
|
line.byte 0x00 "VBTBKR[104],VBATT Backup Register 104"
|
|
group.byte 0x169++0x00
|
|
line.byte 0x00 "VBTBKR[105],VBATT Backup Register 105"
|
|
group.byte 0x16A++0x00
|
|
line.byte 0x00 "VBTBKR[106],VBATT Backup Register 106"
|
|
group.byte 0x16B++0x00
|
|
line.byte 0x00 "VBTBKR[107],VBATT Backup Register 107"
|
|
group.byte 0x16C++0x00
|
|
line.byte 0x00 "VBTBKR[108],VBATT Backup Register 108"
|
|
group.byte 0x16D++0x00
|
|
line.byte 0x00 "VBTBKR[109],VBATT Backup Register 109"
|
|
group.byte 0x16E++0x00
|
|
line.byte 0x00 "VBTBKR[110],VBATT Backup Register 110"
|
|
group.byte 0x16F++0x00
|
|
line.byte 0x00 "VBTBKR[111],VBATT Backup Register 111"
|
|
group.byte 0x170++0x00
|
|
line.byte 0x00 "VBTBKR[112],VBATT Backup Register 112"
|
|
group.byte 0x171++0x00
|
|
line.byte 0x00 "VBTBKR[113],VBATT Backup Register 113"
|
|
group.byte 0x172++0x00
|
|
line.byte 0x00 "VBTBKR[114],VBATT Backup Register 114"
|
|
group.byte 0x173++0x00
|
|
line.byte 0x00 "VBTBKR[115],VBATT Backup Register 115"
|
|
group.byte 0x174++0x00
|
|
line.byte 0x00 "VBTBKR[116],VBATT Backup Register 116"
|
|
group.byte 0x175++0x00
|
|
line.byte 0x00 "VBTBKR[117],VBATT Backup Register 117"
|
|
group.byte 0x176++0x00
|
|
line.byte 0x00 "VBTBKR[118],VBATT Backup Register 118"
|
|
group.byte 0x177++0x00
|
|
line.byte 0x00 "VBTBKR[119],VBATT Backup Register 119"
|
|
group.byte 0x178++0x00
|
|
line.byte 0x00 "VBTBKR[120],VBATT Backup Register 120"
|
|
group.byte 0x179++0x00
|
|
line.byte 0x00 "VBTBKR[121],VBATT Backup Register 121"
|
|
group.byte 0x17A++0x00
|
|
line.byte 0x00 "VBTBKR[122],VBATT Backup Register 122"
|
|
group.byte 0x17B++0x00
|
|
line.byte 0x00 "VBTBKR[123],VBATT Backup Register 123"
|
|
group.byte 0x17C++0x00
|
|
line.byte 0x00 "VBTBKR[124],VBATT Backup Register 124"
|
|
group.byte 0x17D++0x00
|
|
line.byte 0x00 "VBTBKR[125],VBATT Backup Register 125"
|
|
group.byte 0x17E++0x00
|
|
line.byte 0x00 "VBTBKR[126],VBATT Backup Register 126"
|
|
group.byte 0x17F++0x00
|
|
line.byte 0x00 "VBTBKR[127],VBATT Backup Register 127"
|
|
group.byte 0x180++0x00
|
|
line.byte 0x00 "VBTBKR[128],VBATT Backup Register 128"
|
|
group.byte 0x181++0x00
|
|
line.byte 0x00 "VBTBKR[129],VBATT Backup Register 129"
|
|
group.byte 0x182++0x00
|
|
line.byte 0x00 "VBTBKR[130],VBATT Backup Register 130"
|
|
group.byte 0x183++0x00
|
|
line.byte 0x00 "VBTBKR[131],VBATT Backup Register 131"
|
|
group.byte 0x184++0x00
|
|
line.byte 0x00 "VBTBKR[132],VBATT Backup Register 132"
|
|
group.byte 0x185++0x00
|
|
line.byte 0x00 "VBTBKR[133],VBATT Backup Register 133"
|
|
group.byte 0x186++0x00
|
|
line.byte 0x00 "VBTBKR[134],VBATT Backup Register 134"
|
|
group.byte 0x187++0x00
|
|
line.byte 0x00 "VBTBKR[135],VBATT Backup Register 135"
|
|
group.byte 0x188++0x00
|
|
line.byte 0x00 "VBTBKR[136],VBATT Backup Register 136"
|
|
group.byte 0x189++0x00
|
|
line.byte 0x00 "VBTBKR[137],VBATT Backup Register 137"
|
|
group.byte 0x18A++0x00
|
|
line.byte 0x00 "VBTBKR[138],VBATT Backup Register 138"
|
|
group.byte 0x18B++0x00
|
|
line.byte 0x00 "VBTBKR[139],VBATT Backup Register 139"
|
|
group.byte 0x18C++0x00
|
|
line.byte 0x00 "VBTBKR[140],VBATT Backup Register 140"
|
|
group.byte 0x18D++0x00
|
|
line.byte 0x00 "VBTBKR[141],VBATT Backup Register 141"
|
|
group.byte 0x18E++0x00
|
|
line.byte 0x00 "VBTBKR[142],VBATT Backup Register 142"
|
|
group.byte 0x18F++0x00
|
|
line.byte 0x00 "VBTBKR[143],VBATT Backup Register 143"
|
|
group.byte 0x190++0x00
|
|
line.byte 0x00 "VBTBKR[144],VBATT Backup Register 144"
|
|
group.byte 0x191++0x00
|
|
line.byte 0x00 "VBTBKR[145],VBATT Backup Register 145"
|
|
group.byte 0x192++0x00
|
|
line.byte 0x00 "VBTBKR[146],VBATT Backup Register 146"
|
|
group.byte 0x193++0x00
|
|
line.byte 0x00 "VBTBKR[147],VBATT Backup Register 147"
|
|
group.byte 0x194++0x00
|
|
line.byte 0x00 "VBTBKR[148],VBATT Backup Register 148"
|
|
group.byte 0x195++0x00
|
|
line.byte 0x00 "VBTBKR[149],VBATT Backup Register 149"
|
|
group.byte 0x196++0x00
|
|
line.byte 0x00 "VBTBKR[150],VBATT Backup Register 150"
|
|
group.byte 0x197++0x00
|
|
line.byte 0x00 "VBTBKR[151],VBATT Backup Register 151"
|
|
group.byte 0x198++0x00
|
|
line.byte 0x00 "VBTBKR[152],VBATT Backup Register 152"
|
|
group.byte 0x199++0x00
|
|
line.byte 0x00 "VBTBKR[153],VBATT Backup Register 153"
|
|
group.byte 0x19A++0x00
|
|
line.byte 0x00 "VBTBKR[154],VBATT Backup Register 154"
|
|
group.byte 0x19B++0x00
|
|
line.byte 0x00 "VBTBKR[155],VBATT Backup Register 155"
|
|
group.byte 0x19C++0x00
|
|
line.byte 0x00 "VBTBKR[156],VBATT Backup Register 156"
|
|
group.byte 0x19D++0x00
|
|
line.byte 0x00 "VBTBKR[157],VBATT Backup Register 157"
|
|
group.byte 0x19E++0x00
|
|
line.byte 0x00 "VBTBKR[158],VBATT Backup Register 158"
|
|
group.byte 0x19F++0x00
|
|
line.byte 0x00 "VBTBKR[159],VBATT Backup Register 159"
|
|
group.byte 0x1A0++0x00
|
|
line.byte 0x00 "VBTBKR[160],VBATT Backup Register 160"
|
|
group.byte 0x1A1++0x00
|
|
line.byte 0x00 "VBTBKR[161],VBATT Backup Register 161"
|
|
group.byte 0x1A2++0x00
|
|
line.byte 0x00 "VBTBKR[162],VBATT Backup Register 162"
|
|
group.byte 0x1A3++0x00
|
|
line.byte 0x00 "VBTBKR[163],VBATT Backup Register 163"
|
|
group.byte 0x1A4++0x00
|
|
line.byte 0x00 "VBTBKR[164],VBATT Backup Register 164"
|
|
group.byte 0x1A5++0x00
|
|
line.byte 0x00 "VBTBKR[165],VBATT Backup Register 165"
|
|
group.byte 0x1A6++0x00
|
|
line.byte 0x00 "VBTBKR[166],VBATT Backup Register 166"
|
|
group.byte 0x1A7++0x00
|
|
line.byte 0x00 "VBTBKR[167],VBATT Backup Register 167"
|
|
group.byte 0x1A8++0x00
|
|
line.byte 0x00 "VBTBKR[168],VBATT Backup Register 168"
|
|
group.byte 0x1A9++0x00
|
|
line.byte 0x00 "VBTBKR[169],VBATT Backup Register 169"
|
|
group.byte 0x1AA++0x00
|
|
line.byte 0x00 "VBTBKR[170],VBATT Backup Register 170"
|
|
group.byte 0x1AB++0x00
|
|
line.byte 0x00 "VBTBKR[171],VBATT Backup Register 171"
|
|
group.byte 0x1AC++0x00
|
|
line.byte 0x00 "VBTBKR[172],VBATT Backup Register 172"
|
|
group.byte 0x1AD++0x00
|
|
line.byte 0x00 "VBTBKR[173],VBATT Backup Register 173"
|
|
group.byte 0x1AE++0x00
|
|
line.byte 0x00 "VBTBKR[174],VBATT Backup Register 174"
|
|
group.byte 0x1AF++0x00
|
|
line.byte 0x00 "VBTBKR[175],VBATT Backup Register 175"
|
|
group.byte 0x1B0++0x00
|
|
line.byte 0x00 "VBTBKR[176],VBATT Backup Register 176"
|
|
group.byte 0x1B1++0x00
|
|
line.byte 0x00 "VBTBKR[177],VBATT Backup Register 177"
|
|
group.byte 0x1B2++0x00
|
|
line.byte 0x00 "VBTBKR[178],VBATT Backup Register 178"
|
|
group.byte 0x1B3++0x00
|
|
line.byte 0x00 "VBTBKR[179],VBATT Backup Register 179"
|
|
group.byte 0x1B4++0x00
|
|
line.byte 0x00 "VBTBKR[180],VBATT Backup Register 180"
|
|
group.byte 0x1B5++0x00
|
|
line.byte 0x00 "VBTBKR[181],VBATT Backup Register 181"
|
|
group.byte 0x1B6++0x00
|
|
line.byte 0x00 "VBTBKR[182],VBATT Backup Register 182"
|
|
group.byte 0x1B7++0x00
|
|
line.byte 0x00 "VBTBKR[183],VBATT Backup Register 183"
|
|
group.byte 0x1B8++0x00
|
|
line.byte 0x00 "VBTBKR[184],VBATT Backup Register 184"
|
|
group.byte 0x1B9++0x00
|
|
line.byte 0x00 "VBTBKR[185],VBATT Backup Register 185"
|
|
group.byte 0x1BA++0x00
|
|
line.byte 0x00 "VBTBKR[186],VBATT Backup Register 186"
|
|
group.byte 0x1BB++0x00
|
|
line.byte 0x00 "VBTBKR[187],VBATT Backup Register 187"
|
|
group.byte 0x1BC++0x00
|
|
line.byte 0x00 "VBTBKR[188],VBATT Backup Register 188"
|
|
group.byte 0x1BD++0x00
|
|
line.byte 0x00 "VBTBKR[189],VBATT Backup Register 189"
|
|
group.byte 0x1BE++0x00
|
|
line.byte 0x00 "VBTBKR[190],VBATT Backup Register 190"
|
|
group.byte 0x1BF++0x00
|
|
line.byte 0x00 "VBTBKR[191],VBATT Backup Register 191"
|
|
group.byte 0x1C0++0x00
|
|
line.byte 0x00 "VBTBKR[192],VBATT Backup Register 192"
|
|
group.byte 0x1C1++0x00
|
|
line.byte 0x00 "VBTBKR[193],VBATT Backup Register 193"
|
|
group.byte 0x1C2++0x00
|
|
line.byte 0x00 "VBTBKR[194],VBATT Backup Register 194"
|
|
group.byte 0x1C3++0x00
|
|
line.byte 0x00 "VBTBKR[195],VBATT Backup Register 195"
|
|
group.byte 0x1C4++0x00
|
|
line.byte 0x00 "VBTBKR[196],VBATT Backup Register 196"
|
|
group.byte 0x1C5++0x00
|
|
line.byte 0x00 "VBTBKR[197],VBATT Backup Register 197"
|
|
group.byte 0x1C6++0x00
|
|
line.byte 0x00 "VBTBKR[198],VBATT Backup Register 198"
|
|
group.byte 0x1C7++0x00
|
|
line.byte 0x00 "VBTBKR[199],VBATT Backup Register 199"
|
|
group.byte 0x1C8++0x00
|
|
line.byte 0x00 "VBTBKR[200],VBATT Backup Register 200"
|
|
group.byte 0x1C9++0x00
|
|
line.byte 0x00 "VBTBKR[201],VBATT Backup Register 201"
|
|
group.byte 0x1CA++0x00
|
|
line.byte 0x00 "VBTBKR[202],VBATT Backup Register 202"
|
|
group.byte 0x1CB++0x00
|
|
line.byte 0x00 "VBTBKR[203],VBATT Backup Register 203"
|
|
group.byte 0x1CC++0x00
|
|
line.byte 0x00 "VBTBKR[204],VBATT Backup Register 204"
|
|
group.byte 0x1CD++0x00
|
|
line.byte 0x00 "VBTBKR[205],VBATT Backup Register 205"
|
|
group.byte 0x1CE++0x00
|
|
line.byte 0x00 "VBTBKR[206],VBATT Backup Register 206"
|
|
group.byte 0x1CF++0x00
|
|
line.byte 0x00 "VBTBKR[207],VBATT Backup Register 207"
|
|
group.byte 0x1D0++0x00
|
|
line.byte 0x00 "VBTBKR[208],VBATT Backup Register 208"
|
|
group.byte 0x1D1++0x00
|
|
line.byte 0x00 "VBTBKR[209],VBATT Backup Register 209"
|
|
group.byte 0x1D2++0x00
|
|
line.byte 0x00 "VBTBKR[210],VBATT Backup Register 210"
|
|
group.byte 0x1D3++0x00
|
|
line.byte 0x00 "VBTBKR[211],VBATT Backup Register 211"
|
|
group.byte 0x1D4++0x00
|
|
line.byte 0x00 "VBTBKR[212],VBATT Backup Register 212"
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "VBTBKR[213],VBATT Backup Register 213"
|
|
group.byte 0x1D6++0x00
|
|
line.byte 0x00 "VBTBKR[214],VBATT Backup Register 214"
|
|
group.byte 0x1D7++0x00
|
|
line.byte 0x00 "VBTBKR[215],VBATT Backup Register 215"
|
|
group.byte 0x1D8++0x00
|
|
line.byte 0x00 "VBTBKR[216],VBATT Backup Register 216"
|
|
group.byte 0x1D9++0x00
|
|
line.byte 0x00 "VBTBKR[217],VBATT Backup Register 217"
|
|
group.byte 0x1DA++0x00
|
|
line.byte 0x00 "VBTBKR[218],VBATT Backup Register 218"
|
|
group.byte 0x1DB++0x00
|
|
line.byte 0x00 "VBTBKR[219],VBATT Backup Register 219"
|
|
group.byte 0x1DC++0x00
|
|
line.byte 0x00 "VBTBKR[220],VBATT Backup Register 220"
|
|
group.byte 0x1DD++0x00
|
|
line.byte 0x00 "VBTBKR[221],VBATT Backup Register 221"
|
|
group.byte 0x1DE++0x00
|
|
line.byte 0x00 "VBTBKR[222],VBATT Backup Register 222"
|
|
group.byte 0x1DF++0x00
|
|
line.byte 0x00 "VBTBKR[223],VBATT Backup Register 223"
|
|
group.byte 0x1E0++0x00
|
|
line.byte 0x00 "VBTBKR[224],VBATT Backup Register 224"
|
|
group.byte 0x1E1++0x00
|
|
line.byte 0x00 "VBTBKR[225],VBATT Backup Register 225"
|
|
group.byte 0x1E2++0x00
|
|
line.byte 0x00 "VBTBKR[226],VBATT Backup Register 226"
|
|
group.byte 0x1E3++0x00
|
|
line.byte 0x00 "VBTBKR[227],VBATT Backup Register 227"
|
|
group.byte 0x1E4++0x00
|
|
line.byte 0x00 "VBTBKR[228],VBATT Backup Register 228"
|
|
group.byte 0x1E5++0x00
|
|
line.byte 0x00 "VBTBKR[229],VBATT Backup Register 229"
|
|
group.byte 0x1E6++0x00
|
|
line.byte 0x00 "VBTBKR[230],VBATT Backup Register 230"
|
|
group.byte 0x1E7++0x00
|
|
line.byte 0x00 "VBTBKR[231],VBATT Backup Register 231"
|
|
group.byte 0x1E8++0x00
|
|
line.byte 0x00 "VBTBKR[232],VBATT Backup Register 232"
|
|
group.byte 0x1E9++0x00
|
|
line.byte 0x00 "VBTBKR[233],VBATT Backup Register 233"
|
|
group.byte 0x1EA++0x00
|
|
line.byte 0x00 "VBTBKR[234],VBATT Backup Register 234"
|
|
group.byte 0x1EB++0x00
|
|
line.byte 0x00 "VBTBKR[235],VBATT Backup Register 235"
|
|
group.byte 0x1EC++0x00
|
|
line.byte 0x00 "VBTBKR[236],VBATT Backup Register 236"
|
|
group.byte 0x1ED++0x00
|
|
line.byte 0x00 "VBTBKR[237],VBATT Backup Register 237"
|
|
group.byte 0x1EE++0x00
|
|
line.byte 0x00 "VBTBKR[238],VBATT Backup Register 238"
|
|
group.byte 0x1EF++0x00
|
|
line.byte 0x00 "VBTBKR[239],VBATT Backup Register 239"
|
|
group.byte 0x1F0++0x00
|
|
line.byte 0x00 "VBTBKR[240],VBATT Backup Register 240"
|
|
group.byte 0x1F1++0x00
|
|
line.byte 0x00 "VBTBKR[241],VBATT Backup Register 241"
|
|
group.byte 0x1F2++0x00
|
|
line.byte 0x00 "VBTBKR[242],VBATT Backup Register 242"
|
|
group.byte 0x1F3++0x00
|
|
line.byte 0x00 "VBTBKR[243],VBATT Backup Register 243"
|
|
group.byte 0x1F4++0x00
|
|
line.byte 0x00 "VBTBKR[244],VBATT Backup Register 244"
|
|
group.byte 0x1F5++0x00
|
|
line.byte 0x00 "VBTBKR[245],VBATT Backup Register 245"
|
|
group.byte 0x1F6++0x00
|
|
line.byte 0x00 "VBTBKR[246],VBATT Backup Register 246"
|
|
group.byte 0x1F7++0x00
|
|
line.byte 0x00 "VBTBKR[247],VBATT Backup Register 247"
|
|
group.byte 0x1F8++0x00
|
|
line.byte 0x00 "VBTBKR[248],VBATT Backup Register 248"
|
|
group.byte 0x1F9++0x00
|
|
line.byte 0x00 "VBTBKR[249],VBATT Backup Register 249"
|
|
group.byte 0x1FA++0x00
|
|
line.byte 0x00 "VBTBKR[250],VBATT Backup Register 250"
|
|
group.byte 0x1FB++0x00
|
|
line.byte 0x00 "VBTBKR[251],VBATT Backup Register 251"
|
|
group.byte 0x1FC++0x00
|
|
line.byte 0x00 "VBTBKR[252],VBATT Backup Register 252"
|
|
group.byte 0x1FD++0x00
|
|
line.byte 0x00 "VBTBKR[253],VBATT Backup Register 253"
|
|
group.byte 0x1FE++0x00
|
|
line.byte 0x00 "VBTBKR[254],VBATT Backup Register 254"
|
|
group.byte 0x1FF++0x00
|
|
line.byte 0x00 "VBTBKR[255],VBATT Backup Register 255"
|
|
group.byte 0x200++0x00
|
|
line.byte 0x00 "VBTBKR[256],VBATT Backup Register 256"
|
|
group.byte 0x201++0x00
|
|
line.byte 0x00 "VBTBKR[257],VBATT Backup Register 257"
|
|
group.byte 0x202++0x00
|
|
line.byte 0x00 "VBTBKR[258],VBATT Backup Register 258"
|
|
group.byte 0x203++0x00
|
|
line.byte 0x00 "VBTBKR[259],VBATT Backup Register 259"
|
|
group.byte 0x204++0x00
|
|
line.byte 0x00 "VBTBKR[260],VBATT Backup Register 260"
|
|
group.byte 0x205++0x00
|
|
line.byte 0x00 "VBTBKR[261],VBATT Backup Register 261"
|
|
group.byte 0x206++0x00
|
|
line.byte 0x00 "VBTBKR[262],VBATT Backup Register 262"
|
|
group.byte 0x207++0x00
|
|
line.byte 0x00 "VBTBKR[263],VBATT Backup Register 263"
|
|
group.byte 0x208++0x00
|
|
line.byte 0x00 "VBTBKR[264],VBATT Backup Register 264"
|
|
group.byte 0x209++0x00
|
|
line.byte 0x00 "VBTBKR[265],VBATT Backup Register 265"
|
|
group.byte 0x20A++0x00
|
|
line.byte 0x00 "VBTBKR[266],VBATT Backup Register 266"
|
|
group.byte 0x20B++0x00
|
|
line.byte 0x00 "VBTBKR[267],VBATT Backup Register 267"
|
|
group.byte 0x20C++0x00
|
|
line.byte 0x00 "VBTBKR[268],VBATT Backup Register 268"
|
|
group.byte 0x20D++0x00
|
|
line.byte 0x00 "VBTBKR[269],VBATT Backup Register 269"
|
|
group.byte 0x20E++0x00
|
|
line.byte 0x00 "VBTBKR[270],VBATT Backup Register 270"
|
|
group.byte 0x20F++0x00
|
|
line.byte 0x00 "VBTBKR[271],VBATT Backup Register 271"
|
|
group.byte 0x210++0x00
|
|
line.byte 0x00 "VBTBKR[272],VBATT Backup Register 272"
|
|
group.byte 0x211++0x00
|
|
line.byte 0x00 "VBTBKR[273],VBATT Backup Register 273"
|
|
group.byte 0x212++0x00
|
|
line.byte 0x00 "VBTBKR[274],VBATT Backup Register 274"
|
|
group.byte 0x213++0x00
|
|
line.byte 0x00 "VBTBKR[275],VBATT Backup Register 275"
|
|
group.byte 0x214++0x00
|
|
line.byte 0x00 "VBTBKR[276],VBATT Backup Register 276"
|
|
group.byte 0x215++0x00
|
|
line.byte 0x00 "VBTBKR[277],VBATT Backup Register 277"
|
|
group.byte 0x216++0x00
|
|
line.byte 0x00 "VBTBKR[278],VBATT Backup Register 278"
|
|
group.byte 0x217++0x00
|
|
line.byte 0x00 "VBTBKR[279],VBATT Backup Register 279"
|
|
group.byte 0x218++0x00
|
|
line.byte 0x00 "VBTBKR[280],VBATT Backup Register 280"
|
|
group.byte 0x219++0x00
|
|
line.byte 0x00 "VBTBKR[281],VBATT Backup Register 281"
|
|
group.byte 0x21A++0x00
|
|
line.byte 0x00 "VBTBKR[282],VBATT Backup Register 282"
|
|
group.byte 0x21B++0x00
|
|
line.byte 0x00 "VBTBKR[283],VBATT Backup Register 283"
|
|
group.byte 0x21C++0x00
|
|
line.byte 0x00 "VBTBKR[284],VBATT Backup Register 284"
|
|
group.byte 0x21D++0x00
|
|
line.byte 0x00 "VBTBKR[285],VBATT Backup Register 285"
|
|
group.byte 0x21E++0x00
|
|
line.byte 0x00 "VBTBKR[286],VBATT Backup Register 286"
|
|
group.byte 0x21F++0x00
|
|
line.byte 0x00 "VBTBKR[287],VBATT Backup Register 287"
|
|
group.byte 0x220++0x00
|
|
line.byte 0x00 "VBTBKR[288],VBATT Backup Register 288"
|
|
group.byte 0x221++0x00
|
|
line.byte 0x00 "VBTBKR[289],VBATT Backup Register 289"
|
|
group.byte 0x222++0x00
|
|
line.byte 0x00 "VBTBKR[290],VBATT Backup Register 290"
|
|
group.byte 0x223++0x00
|
|
line.byte 0x00 "VBTBKR[291],VBATT Backup Register 291"
|
|
group.byte 0x224++0x00
|
|
line.byte 0x00 "VBTBKR[292],VBATT Backup Register 292"
|
|
group.byte 0x225++0x00
|
|
line.byte 0x00 "VBTBKR[293],VBATT Backup Register 293"
|
|
group.byte 0x226++0x00
|
|
line.byte 0x00 "VBTBKR[294],VBATT Backup Register 294"
|
|
group.byte 0x227++0x00
|
|
line.byte 0x00 "VBTBKR[295],VBATT Backup Register 295"
|
|
group.byte 0x228++0x00
|
|
line.byte 0x00 "VBTBKR[296],VBATT Backup Register 296"
|
|
group.byte 0x229++0x00
|
|
line.byte 0x00 "VBTBKR[297],VBATT Backup Register 297"
|
|
group.byte 0x22A++0x00
|
|
line.byte 0x00 "VBTBKR[298],VBATT Backup Register 298"
|
|
group.byte 0x22B++0x00
|
|
line.byte 0x00 "VBTBKR[299],VBATT Backup Register 299"
|
|
group.byte 0x22C++0x00
|
|
line.byte 0x00 "VBTBKR[300],VBATT Backup Register 300"
|
|
group.byte 0x22D++0x00
|
|
line.byte 0x00 "VBTBKR[301],VBATT Backup Register 301"
|
|
group.byte 0x22E++0x00
|
|
line.byte 0x00 "VBTBKR[302],VBATT Backup Register 302"
|
|
group.byte 0x22F++0x00
|
|
line.byte 0x00 "VBTBKR[303],VBATT Backup Register 303"
|
|
group.byte 0x230++0x00
|
|
line.byte 0x00 "VBTBKR[304],VBATT Backup Register 304"
|
|
group.byte 0x231++0x00
|
|
line.byte 0x00 "VBTBKR[305],VBATT Backup Register 305"
|
|
group.byte 0x232++0x00
|
|
line.byte 0x00 "VBTBKR[306],VBATT Backup Register 306"
|
|
group.byte 0x233++0x00
|
|
line.byte 0x00 "VBTBKR[307],VBATT Backup Register 307"
|
|
group.byte 0x234++0x00
|
|
line.byte 0x00 "VBTBKR[308],VBATT Backup Register 308"
|
|
group.byte 0x235++0x00
|
|
line.byte 0x00 "VBTBKR[309],VBATT Backup Register 309"
|
|
group.byte 0x236++0x00
|
|
line.byte 0x00 "VBTBKR[310],VBATT Backup Register 310"
|
|
group.byte 0x237++0x00
|
|
line.byte 0x00 "VBTBKR[311],VBATT Backup Register 311"
|
|
group.byte 0x238++0x00
|
|
line.byte 0x00 "VBTBKR[312],VBATT Backup Register 312"
|
|
group.byte 0x239++0x00
|
|
line.byte 0x00 "VBTBKR[313],VBATT Backup Register 313"
|
|
group.byte 0x23A++0x00
|
|
line.byte 0x00 "VBTBKR[314],VBATT Backup Register 314"
|
|
group.byte 0x23B++0x00
|
|
line.byte 0x00 "VBTBKR[315],VBATT Backup Register 315"
|
|
group.byte 0x23C++0x00
|
|
line.byte 0x00 "VBTBKR[316],VBATT Backup Register 316"
|
|
group.byte 0x23D++0x00
|
|
line.byte 0x00 "VBTBKR[317],VBATT Backup Register 317"
|
|
group.byte 0x23E++0x00
|
|
line.byte 0x00 "VBTBKR[318],VBATT Backup Register 318"
|
|
group.byte 0x23F++0x00
|
|
line.byte 0x00 "VBTBKR[319],VBATT Backup Register 319"
|
|
group.byte 0x240++0x00
|
|
line.byte 0x00 "VBTBKR[320],VBATT Backup Register 320"
|
|
group.byte 0x241++0x00
|
|
line.byte 0x00 "VBTBKR[321],VBATT Backup Register 321"
|
|
group.byte 0x242++0x00
|
|
line.byte 0x00 "VBTBKR[322],VBATT Backup Register 322"
|
|
group.byte 0x243++0x00
|
|
line.byte 0x00 "VBTBKR[323],VBATT Backup Register 323"
|
|
group.byte 0x244++0x00
|
|
line.byte 0x00 "VBTBKR[324],VBATT Backup Register 324"
|
|
group.byte 0x245++0x00
|
|
line.byte 0x00 "VBTBKR[325],VBATT Backup Register 325"
|
|
group.byte 0x246++0x00
|
|
line.byte 0x00 "VBTBKR[326],VBATT Backup Register 326"
|
|
group.byte 0x247++0x00
|
|
line.byte 0x00 "VBTBKR[327],VBATT Backup Register 327"
|
|
group.byte 0x248++0x00
|
|
line.byte 0x00 "VBTBKR[328],VBATT Backup Register 328"
|
|
group.byte 0x249++0x00
|
|
line.byte 0x00 "VBTBKR[329],VBATT Backup Register 329"
|
|
group.byte 0x24A++0x00
|
|
line.byte 0x00 "VBTBKR[330],VBATT Backup Register 330"
|
|
group.byte 0x24B++0x00
|
|
line.byte 0x00 "VBTBKR[331],VBATT Backup Register 331"
|
|
group.byte 0x24C++0x00
|
|
line.byte 0x00 "VBTBKR[332],VBATT Backup Register 332"
|
|
group.byte 0x24D++0x00
|
|
line.byte 0x00 "VBTBKR[333],VBATT Backup Register 333"
|
|
group.byte 0x24E++0x00
|
|
line.byte 0x00 "VBTBKR[334],VBATT Backup Register 334"
|
|
group.byte 0x24F++0x00
|
|
line.byte 0x00 "VBTBKR[335],VBATT Backup Register 335"
|
|
group.byte 0x250++0x00
|
|
line.byte 0x00 "VBTBKR[336],VBATT Backup Register 336"
|
|
group.byte 0x251++0x00
|
|
line.byte 0x00 "VBTBKR[337],VBATT Backup Register 337"
|
|
group.byte 0x252++0x00
|
|
line.byte 0x00 "VBTBKR[338],VBATT Backup Register 338"
|
|
group.byte 0x253++0x00
|
|
line.byte 0x00 "VBTBKR[339],VBATT Backup Register 339"
|
|
group.byte 0x254++0x00
|
|
line.byte 0x00 "VBTBKR[340],VBATT Backup Register 340"
|
|
group.byte 0x255++0x00
|
|
line.byte 0x00 "VBTBKR[341],VBATT Backup Register 341"
|
|
group.byte 0x256++0x00
|
|
line.byte 0x00 "VBTBKR[342],VBATT Backup Register 342"
|
|
group.byte 0x257++0x00
|
|
line.byte 0x00 "VBTBKR[343],VBATT Backup Register 343"
|
|
group.byte 0x258++0x00
|
|
line.byte 0x00 "VBTBKR[344],VBATT Backup Register 344"
|
|
group.byte 0x259++0x00
|
|
line.byte 0x00 "VBTBKR[345],VBATT Backup Register 345"
|
|
group.byte 0x25A++0x00
|
|
line.byte 0x00 "VBTBKR[346],VBATT Backup Register 346"
|
|
group.byte 0x25B++0x00
|
|
line.byte 0x00 "VBTBKR[347],VBATT Backup Register 347"
|
|
group.byte 0x25C++0x00
|
|
line.byte 0x00 "VBTBKR[348],VBATT Backup Register 348"
|
|
group.byte 0x25D++0x00
|
|
line.byte 0x00 "VBTBKR[349],VBATT Backup Register 349"
|
|
group.byte 0x25E++0x00
|
|
line.byte 0x00 "VBTBKR[350],VBATT Backup Register 350"
|
|
group.byte 0x25F++0x00
|
|
line.byte 0x00 "VBTBKR[351],VBATT Backup Register 351"
|
|
group.byte 0x260++0x00
|
|
line.byte 0x00 "VBTBKR[352],VBATT Backup Register 352"
|
|
group.byte 0x261++0x00
|
|
line.byte 0x00 "VBTBKR[353],VBATT Backup Register 353"
|
|
group.byte 0x262++0x00
|
|
line.byte 0x00 "VBTBKR[354],VBATT Backup Register 354"
|
|
group.byte 0x263++0x00
|
|
line.byte 0x00 "VBTBKR[355],VBATT Backup Register 355"
|
|
group.byte 0x264++0x00
|
|
line.byte 0x00 "VBTBKR[356],VBATT Backup Register 356"
|
|
group.byte 0x265++0x00
|
|
line.byte 0x00 "VBTBKR[357],VBATT Backup Register 357"
|
|
group.byte 0x266++0x00
|
|
line.byte 0x00 "VBTBKR[358],VBATT Backup Register 358"
|
|
group.byte 0x267++0x00
|
|
line.byte 0x00 "VBTBKR[359],VBATT Backup Register 359"
|
|
group.byte 0x268++0x00
|
|
line.byte 0x00 "VBTBKR[360],VBATT Backup Register 360"
|
|
group.byte 0x269++0x00
|
|
line.byte 0x00 "VBTBKR[361],VBATT Backup Register 361"
|
|
group.byte 0x26A++0x00
|
|
line.byte 0x00 "VBTBKR[362],VBATT Backup Register 362"
|
|
group.byte 0x26B++0x00
|
|
line.byte 0x00 "VBTBKR[363],VBATT Backup Register 363"
|
|
group.byte 0x26C++0x00
|
|
line.byte 0x00 "VBTBKR[364],VBATT Backup Register 364"
|
|
group.byte 0x26D++0x00
|
|
line.byte 0x00 "VBTBKR[365],VBATT Backup Register 365"
|
|
group.byte 0x26E++0x00
|
|
line.byte 0x00 "VBTBKR[366],VBATT Backup Register 366"
|
|
group.byte 0x26F++0x00
|
|
line.byte 0x00 "VBTBKR[367],VBATT Backup Register 367"
|
|
group.byte 0x270++0x00
|
|
line.byte 0x00 "VBTBKR[368],VBATT Backup Register 368"
|
|
group.byte 0x271++0x00
|
|
line.byte 0x00 "VBTBKR[369],VBATT Backup Register 369"
|
|
group.byte 0x272++0x00
|
|
line.byte 0x00 "VBTBKR[370],VBATT Backup Register 370"
|
|
group.byte 0x273++0x00
|
|
line.byte 0x00 "VBTBKR[371],VBATT Backup Register 371"
|
|
group.byte 0x274++0x00
|
|
line.byte 0x00 "VBTBKR[372],VBATT Backup Register 372"
|
|
group.byte 0x275++0x00
|
|
line.byte 0x00 "VBTBKR[373],VBATT Backup Register 373"
|
|
group.byte 0x276++0x00
|
|
line.byte 0x00 "VBTBKR[374],VBATT Backup Register 374"
|
|
group.byte 0x277++0x00
|
|
line.byte 0x00 "VBTBKR[375],VBATT Backup Register 375"
|
|
group.byte 0x278++0x00
|
|
line.byte 0x00 "VBTBKR[376],VBATT Backup Register 376"
|
|
group.byte 0x279++0x00
|
|
line.byte 0x00 "VBTBKR[377],VBATT Backup Register 377"
|
|
group.byte 0x27A++0x00
|
|
line.byte 0x00 "VBTBKR[378],VBATT Backup Register 378"
|
|
group.byte 0x27B++0x00
|
|
line.byte 0x00 "VBTBKR[379],VBATT Backup Register 379"
|
|
group.byte 0x27C++0x00
|
|
line.byte 0x00 "VBTBKR[380],VBATT Backup Register 380"
|
|
group.byte 0x27D++0x00
|
|
line.byte 0x00 "VBTBKR[381],VBATT Backup Register 381"
|
|
group.byte 0x27E++0x00
|
|
line.byte 0x00 "VBTBKR[382],VBATT Backup Register 382"
|
|
group.byte 0x27F++0x00
|
|
line.byte 0x00 "VBTBKR[383],VBATT Backup Register 383"
|
|
group.byte 0x280++0x00
|
|
line.byte 0x00 "VBTBKR[384],VBATT Backup Register 384"
|
|
group.byte 0x281++0x00
|
|
line.byte 0x00 "VBTBKR[385],VBATT Backup Register 385"
|
|
group.byte 0x282++0x00
|
|
line.byte 0x00 "VBTBKR[386],VBATT Backup Register 386"
|
|
group.byte 0x283++0x00
|
|
line.byte 0x00 "VBTBKR[387],VBATT Backup Register 387"
|
|
group.byte 0x284++0x00
|
|
line.byte 0x00 "VBTBKR[388],VBATT Backup Register 388"
|
|
group.byte 0x285++0x00
|
|
line.byte 0x00 "VBTBKR[389],VBATT Backup Register 389"
|
|
group.byte 0x286++0x00
|
|
line.byte 0x00 "VBTBKR[390],VBATT Backup Register 390"
|
|
group.byte 0x287++0x00
|
|
line.byte 0x00 "VBTBKR[391],VBATT Backup Register 391"
|
|
group.byte 0x288++0x00
|
|
line.byte 0x00 "VBTBKR[392],VBATT Backup Register 392"
|
|
group.byte 0x289++0x00
|
|
line.byte 0x00 "VBTBKR[393],VBATT Backup Register 393"
|
|
group.byte 0x28A++0x00
|
|
line.byte 0x00 "VBTBKR[394],VBATT Backup Register 394"
|
|
group.byte 0x28B++0x00
|
|
line.byte 0x00 "VBTBKR[395],VBATT Backup Register 395"
|
|
group.byte 0x28C++0x00
|
|
line.byte 0x00 "VBTBKR[396],VBATT Backup Register 396"
|
|
group.byte 0x28D++0x00
|
|
line.byte 0x00 "VBTBKR[397],VBATT Backup Register 397"
|
|
group.byte 0x28E++0x00
|
|
line.byte 0x00 "VBTBKR[398],VBATT Backup Register 398"
|
|
group.byte 0x28F++0x00
|
|
line.byte 0x00 "VBTBKR[399],VBATT Backup Register 399"
|
|
group.byte 0x290++0x00
|
|
line.byte 0x00 "VBTBKR[400],VBATT Backup Register 400"
|
|
group.byte 0x291++0x00
|
|
line.byte 0x00 "VBTBKR[401],VBATT Backup Register 401"
|
|
group.byte 0x292++0x00
|
|
line.byte 0x00 "VBTBKR[402],VBATT Backup Register 402"
|
|
group.byte 0x293++0x00
|
|
line.byte 0x00 "VBTBKR[403],VBATT Backup Register 403"
|
|
group.byte 0x294++0x00
|
|
line.byte 0x00 "VBTBKR[404],VBATT Backup Register 404"
|
|
group.byte 0x295++0x00
|
|
line.byte 0x00 "VBTBKR[405],VBATT Backup Register 405"
|
|
group.byte 0x296++0x00
|
|
line.byte 0x00 "VBTBKR[406],VBATT Backup Register 406"
|
|
group.byte 0x297++0x00
|
|
line.byte 0x00 "VBTBKR[407],VBATT Backup Register 407"
|
|
group.byte 0x298++0x00
|
|
line.byte 0x00 "VBTBKR[408],VBATT Backup Register 408"
|
|
group.byte 0x299++0x00
|
|
line.byte 0x00 "VBTBKR[409],VBATT Backup Register 409"
|
|
group.byte 0x29A++0x00
|
|
line.byte 0x00 "VBTBKR[410],VBATT Backup Register 410"
|
|
group.byte 0x29B++0x00
|
|
line.byte 0x00 "VBTBKR[411],VBATT Backup Register 411"
|
|
group.byte 0x29C++0x00
|
|
line.byte 0x00 "VBTBKR[412],VBATT Backup Register 412"
|
|
group.byte 0x29D++0x00
|
|
line.byte 0x00 "VBTBKR[413],VBATT Backup Register 413"
|
|
group.byte 0x29E++0x00
|
|
line.byte 0x00 "VBTBKR[414],VBATT Backup Register 414"
|
|
group.byte 0x29F++0x00
|
|
line.byte 0x00 "VBTBKR[415],VBATT Backup Register 415"
|
|
group.byte 0x2A0++0x00
|
|
line.byte 0x00 "VBTBKR[416],VBATT Backup Register 416"
|
|
group.byte 0x2A1++0x00
|
|
line.byte 0x00 "VBTBKR[417],VBATT Backup Register 417"
|
|
group.byte 0x2A2++0x00
|
|
line.byte 0x00 "VBTBKR[418],VBATT Backup Register 418"
|
|
group.byte 0x2A3++0x00
|
|
line.byte 0x00 "VBTBKR[419],VBATT Backup Register 419"
|
|
group.byte 0x2A4++0x00
|
|
line.byte 0x00 "VBTBKR[420],VBATT Backup Register 420"
|
|
group.byte 0x2A5++0x00
|
|
line.byte 0x00 "VBTBKR[421],VBATT Backup Register 421"
|
|
group.byte 0x2A6++0x00
|
|
line.byte 0x00 "VBTBKR[422],VBATT Backup Register 422"
|
|
group.byte 0x2A7++0x00
|
|
line.byte 0x00 "VBTBKR[423],VBATT Backup Register 423"
|
|
group.byte 0x2A8++0x00
|
|
line.byte 0x00 "VBTBKR[424],VBATT Backup Register 424"
|
|
group.byte 0x2A9++0x00
|
|
line.byte 0x00 "VBTBKR[425],VBATT Backup Register 425"
|
|
group.byte 0x2AA++0x00
|
|
line.byte 0x00 "VBTBKR[426],VBATT Backup Register 426"
|
|
group.byte 0x2AB++0x00
|
|
line.byte 0x00 "VBTBKR[427],VBATT Backup Register 427"
|
|
group.byte 0x2AC++0x00
|
|
line.byte 0x00 "VBTBKR[428],VBATT Backup Register 428"
|
|
group.byte 0x2AD++0x00
|
|
line.byte 0x00 "VBTBKR[429],VBATT Backup Register 429"
|
|
group.byte 0x2AE++0x00
|
|
line.byte 0x00 "VBTBKR[430],VBATT Backup Register 430"
|
|
group.byte 0x2AF++0x00
|
|
line.byte 0x00 "VBTBKR[431],VBATT Backup Register 431"
|
|
group.byte 0x2B0++0x00
|
|
line.byte 0x00 "VBTBKR[432],VBATT Backup Register 432"
|
|
group.byte 0x2B1++0x00
|
|
line.byte 0x00 "VBTBKR[433],VBATT Backup Register 433"
|
|
group.byte 0x2B2++0x00
|
|
line.byte 0x00 "VBTBKR[434],VBATT Backup Register 434"
|
|
group.byte 0x2B3++0x00
|
|
line.byte 0x00 "VBTBKR[435],VBATT Backup Register 435"
|
|
group.byte 0x2B4++0x00
|
|
line.byte 0x00 "VBTBKR[436],VBATT Backup Register 436"
|
|
group.byte 0x2B5++0x00
|
|
line.byte 0x00 "VBTBKR[437],VBATT Backup Register 437"
|
|
group.byte 0x2B6++0x00
|
|
line.byte 0x00 "VBTBKR[438],VBATT Backup Register 438"
|
|
group.byte 0x2B7++0x00
|
|
line.byte 0x00 "VBTBKR[439],VBATT Backup Register 439"
|
|
group.byte 0x2B8++0x00
|
|
line.byte 0x00 "VBTBKR[440],VBATT Backup Register 440"
|
|
group.byte 0x2B9++0x00
|
|
line.byte 0x00 "VBTBKR[441],VBATT Backup Register 441"
|
|
group.byte 0x2BA++0x00
|
|
line.byte 0x00 "VBTBKR[442],VBATT Backup Register 442"
|
|
group.byte 0x2BB++0x00
|
|
line.byte 0x00 "VBTBKR[443],VBATT Backup Register 443"
|
|
group.byte 0x2BC++0x00
|
|
line.byte 0x00 "VBTBKR[444],VBATT Backup Register 444"
|
|
group.byte 0x2BD++0x00
|
|
line.byte 0x00 "VBTBKR[445],VBATT Backup Register 445"
|
|
group.byte 0x2BE++0x00
|
|
line.byte 0x00 "VBTBKR[446],VBATT Backup Register 446"
|
|
group.byte 0x2BF++0x00
|
|
line.byte 0x00 "VBTBKR[447],VBATT Backup Register 447"
|
|
group.byte 0x2C0++0x00
|
|
line.byte 0x00 "VBTBKR[448],VBATT Backup Register 448"
|
|
group.byte 0x2C1++0x00
|
|
line.byte 0x00 "VBTBKR[449],VBATT Backup Register 449"
|
|
group.byte 0x2C2++0x00
|
|
line.byte 0x00 "VBTBKR[450],VBATT Backup Register 450"
|
|
group.byte 0x2C3++0x00
|
|
line.byte 0x00 "VBTBKR[451],VBATT Backup Register 451"
|
|
group.byte 0x2C4++0x00
|
|
line.byte 0x00 "VBTBKR[452],VBATT Backup Register 452"
|
|
group.byte 0x2C5++0x00
|
|
line.byte 0x00 "VBTBKR[453],VBATT Backup Register 453"
|
|
group.byte 0x2C6++0x00
|
|
line.byte 0x00 "VBTBKR[454],VBATT Backup Register 454"
|
|
group.byte 0x2C7++0x00
|
|
line.byte 0x00 "VBTBKR[455],VBATT Backup Register 455"
|
|
group.byte 0x2C8++0x00
|
|
line.byte 0x00 "VBTBKR[456],VBATT Backup Register 456"
|
|
group.byte 0x2C9++0x00
|
|
line.byte 0x00 "VBTBKR[457],VBATT Backup Register 457"
|
|
group.byte 0x2CA++0x00
|
|
line.byte 0x00 "VBTBKR[458],VBATT Backup Register 458"
|
|
group.byte 0x2CB++0x00
|
|
line.byte 0x00 "VBTBKR[459],VBATT Backup Register 459"
|
|
group.byte 0x2CC++0x00
|
|
line.byte 0x00 "VBTBKR[460],VBATT Backup Register 460"
|
|
group.byte 0x2CD++0x00
|
|
line.byte 0x00 "VBTBKR[461],VBATT Backup Register 461"
|
|
group.byte 0x2CE++0x00
|
|
line.byte 0x00 "VBTBKR[462],VBATT Backup Register 462"
|
|
group.byte 0x2CF++0x00
|
|
line.byte 0x00 "VBTBKR[463],VBATT Backup Register 463"
|
|
group.byte 0x2D0++0x00
|
|
line.byte 0x00 "VBTBKR[464],VBATT Backup Register 464"
|
|
group.byte 0x2D1++0x00
|
|
line.byte 0x00 "VBTBKR[465],VBATT Backup Register 465"
|
|
group.byte 0x2D2++0x00
|
|
line.byte 0x00 "VBTBKR[466],VBATT Backup Register 466"
|
|
group.byte 0x2D3++0x00
|
|
line.byte 0x00 "VBTBKR[467],VBATT Backup Register 467"
|
|
group.byte 0x2D4++0x00
|
|
line.byte 0x00 "VBTBKR[468],VBATT Backup Register 468"
|
|
group.byte 0x2D5++0x00
|
|
line.byte 0x00 "VBTBKR[469],VBATT Backup Register 469"
|
|
group.byte 0x2D6++0x00
|
|
line.byte 0x00 "VBTBKR[470],VBATT Backup Register 470"
|
|
group.byte 0x2D7++0x00
|
|
line.byte 0x00 "VBTBKR[471],VBATT Backup Register 471"
|
|
group.byte 0x2D8++0x00
|
|
line.byte 0x00 "VBTBKR[472],VBATT Backup Register 472"
|
|
group.byte 0x2D9++0x00
|
|
line.byte 0x00 "VBTBKR[473],VBATT Backup Register 473"
|
|
group.byte 0x2DA++0x00
|
|
line.byte 0x00 "VBTBKR[474],VBATT Backup Register 474"
|
|
group.byte 0x2DB++0x00
|
|
line.byte 0x00 "VBTBKR[475],VBATT Backup Register 475"
|
|
group.byte 0x2DC++0x00
|
|
line.byte 0x00 "VBTBKR[476],VBATT Backup Register 476"
|
|
group.byte 0x2DD++0x00
|
|
line.byte 0x00 "VBTBKR[477],VBATT Backup Register 477"
|
|
group.byte 0x2DE++0x00
|
|
line.byte 0x00 "VBTBKR[478],VBATT Backup Register 478"
|
|
group.byte 0x2DF++0x00
|
|
line.byte 0x00 "VBTBKR[479],VBATT Backup Register 479"
|
|
group.byte 0x2E0++0x00
|
|
line.byte 0x00 "VBTBKR[480],VBATT Backup Register 480"
|
|
group.byte 0x2E1++0x00
|
|
line.byte 0x00 "VBTBKR[481],VBATT Backup Register 481"
|
|
group.byte 0x2E2++0x00
|
|
line.byte 0x00 "VBTBKR[482],VBATT Backup Register 482"
|
|
group.byte 0x2E3++0x00
|
|
line.byte 0x00 "VBTBKR[483],VBATT Backup Register 483"
|
|
group.byte 0x2E4++0x00
|
|
line.byte 0x00 "VBTBKR[484],VBATT Backup Register 484"
|
|
group.byte 0x2E5++0x00
|
|
line.byte 0x00 "VBTBKR[485],VBATT Backup Register 485"
|
|
group.byte 0x2E6++0x00
|
|
line.byte 0x00 "VBTBKR[486],VBATT Backup Register 486"
|
|
group.byte 0x2E7++0x00
|
|
line.byte 0x00 "VBTBKR[487],VBATT Backup Register 487"
|
|
group.byte 0x2E8++0x00
|
|
line.byte 0x00 "VBTBKR[488],VBATT Backup Register 488"
|
|
group.byte 0x2E9++0x00
|
|
line.byte 0x00 "VBTBKR[489],VBATT Backup Register 489"
|
|
group.byte 0x2EA++0x00
|
|
line.byte 0x00 "VBTBKR[490],VBATT Backup Register 490"
|
|
group.byte 0x2EB++0x00
|
|
line.byte 0x00 "VBTBKR[491],VBATT Backup Register 491"
|
|
group.byte 0x2EC++0x00
|
|
line.byte 0x00 "VBTBKR[492],VBATT Backup Register 492"
|
|
group.byte 0x2ED++0x00
|
|
line.byte 0x00 "VBTBKR[493],VBATT Backup Register 493"
|
|
group.byte 0x2EE++0x00
|
|
line.byte 0x00 "VBTBKR[494],VBATT Backup Register 494"
|
|
group.byte 0x2EF++0x00
|
|
line.byte 0x00 "VBTBKR[495],VBATT Backup Register 495"
|
|
group.byte 0x2F0++0x00
|
|
line.byte 0x00 "VBTBKR[496],VBATT Backup Register 496"
|
|
group.byte 0x2F1++0x00
|
|
line.byte 0x00 "VBTBKR[497],VBATT Backup Register 497"
|
|
group.byte 0x2F2++0x00
|
|
line.byte 0x00 "VBTBKR[498],VBATT Backup Register 498"
|
|
group.byte 0x2F3++0x00
|
|
line.byte 0x00 "VBTBKR[499],VBATT Backup Register 499"
|
|
group.byte 0x2F4++0x00
|
|
line.byte 0x00 "VBTBKR[500],VBATT Backup Register 500"
|
|
group.byte 0x2F5++0x00
|
|
line.byte 0x00 "VBTBKR[501],VBATT Backup Register 501"
|
|
group.byte 0x2F6++0x00
|
|
line.byte 0x00 "VBTBKR[502],VBATT Backup Register 502"
|
|
group.byte 0x2F7++0x00
|
|
line.byte 0x00 "VBTBKR[503],VBATT Backup Register 503"
|
|
group.byte 0x2F8++0x00
|
|
line.byte 0x00 "VBTBKR[504],VBATT Backup Register 504"
|
|
group.byte 0x2F9++0x00
|
|
line.byte 0x00 "VBTBKR[505],VBATT Backup Register 505"
|
|
group.byte 0x2FA++0x00
|
|
line.byte 0x00 "VBTBKR[506],VBATT Backup Register 506"
|
|
group.byte 0x2FB++0x00
|
|
line.byte 0x00 "VBTBKR[507],VBATT Backup Register 507"
|
|
group.byte 0x2FC++0x00
|
|
line.byte 0x00 "VBTBKR[508],VBATT Backup Register 508"
|
|
group.byte 0x2FD++0x00
|
|
line.byte 0x00 "VBTBKR[509],VBATT Backup Register 509"
|
|
group.byte 0x2FE++0x00
|
|
line.byte 0x00 "VBTBKR[510],VBATT Backup Register 510"
|
|
group.byte 0x2FF++0x00
|
|
line.byte 0x00 "VBTBKR[511],VBATT Backup Register 511"
|
|
tree.end
|
|
textline " "
|
|
group.byte 0xB6++0x00
|
|
line.byte 0x00 "VBTWCTLR,VBATT Wakeup Control Register"
|
|
bitfld.byte 0x00 0. " VWEN ,VBATT Wakeup Enable" "Disabled,Enabled"
|
|
group.byte 0xB8++0x07
|
|
line.byte 0x00 "VBTWCH0OTSR,VBATT Wakeup I/O 0 Output Trigger Select Register"
|
|
bitfld.byte 0x00 5. " CH0VAGTUTE ,VBATWIO0 Output AGT Underflow Signal Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " CH0VRTCATE ,VBATWIO0 Output RTC Alarm Signal Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " CH0VRTCTE ,VBATWIO0 Output RTC Periodic Signal Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " CH0VCH2TE ,VBATWIO0 Output VBATWIO2 Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " CH0VCH1TE ,VBATWIO0 Output VBATWIO1 Trigger Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "VBTWCH1OTSR,VBATT Wakeup I/O 1 Output Trigger Select Register"
|
|
bitfld.byte 0x01 5. " CH1VAGTUTE ,VBATWIO1 Output AGT Underflow Signal Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " CH1VRTCATE ,VBATWIO1 Output RTC Alarm Signal Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 3. " CH1VRTCTE ,VBATWIO1 Output RTC Periodic Signal Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " CH1VCH2TE ,VBATWIO1 Output VBATWIO2 Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 0. " CH1VCH0TE ,VBATWIO1 Output VBATWIO0 Trigger Enable" "Disabled,Enabled"
|
|
line.byte 0x02 "VBTWCH2OTSR,VBATT Wakeup I/O 2 Output Trigger Select Register"
|
|
bitfld.byte 0x02 5. " CH2VAGTUTE ,VBATWIO2 Output AGT Underflow Signal Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 4. " CH2VRTCATE ,VBATWIO2 Output RTC Alarm Signal Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 3. " CH2VRTCTE ,VBATWIO2 Output RTC Periodic Signal Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 1. " CH2VCH1TE ,VBATWIO2 Output VBATWIO1 Trigger Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x02 0. " CH2VCH0TE ,VBATWIO2 Output VBATWIO0 Trigger Enable" "Disabled,Enabled"
|
|
line.byte 0x03 "VBTICTLR,VBATT Input Control Register"
|
|
bitfld.byte 0x03 2. " VCH2INEN ,VBATT Wakeup I/O 2 Input Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 1. " VCH1INEN ,VBATT Wakeup I/O 1 Input Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 0. " VCH0INEN ,VBATT Wakeup I/O 0 Input Enable" "Disabled,Enabled"
|
|
line.byte 0x04 "VBTOCTLR,VBATT Output Control Register"
|
|
bitfld.byte 0x04 5. " VOUT2LSEL ,VBATT Wakeup I/O 2 Output Level Selection" "Low,High"
|
|
bitfld.byte 0x04 4. " VOUT1LSEL ,VBATT Wakeup I/O 1 Output Level Selection" "Low,High"
|
|
bitfld.byte 0x04 3. " VOUT0LSEL ,VBATT Wakeup I/O 0 Output Level Selection" "Low,High"
|
|
bitfld.byte 0x04 2. " VCH2OEN ,VBATT Wakeup I/O 2 Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x04 1. " VCH1OEN ,VBATT Wakeup I/O 1 Output Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x04 0. " VCH0OEN ,VBATT Wakeup I/O 0 Output Enable" "Disabled,Enabled"
|
|
line.byte 0x05 "VBTWTER,VBATT Wakeup Trigger Source Enable Register"
|
|
bitfld.byte 0x05 5. " VAGTUE ,AGT1 Underflow Signal Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x05 4. " VRTCAE ,RTC Alarm Signal Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x05 3. " VRTCIE ,RTC Periodic Signal Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x05 2. " VCH2E ,VBATWIO2 Pin Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x05 1. " VCH1E ,VBATWIO1 Pin Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x05 0. " VCH0E ,VBATWIO0 Pin Enable" "Disabled,Enabled"
|
|
line.byte 0x06 "VBTWEGR,VBATT Wakeup Trigger Source Edge Register"
|
|
bitfld.byte 0x06 2. " VCH2EG ,VBATWIO2 Wakeup Trigger Source Edge Select" "Falling,Rising"
|
|
bitfld.byte 0x06 1. " VCH1EG ,VBATWIO1 Wakeup Trigger Source Edge Select" "Falling,Rising"
|
|
bitfld.byte 0x06 0. " VCH0EG ,VBATWIO0 Wakeup Trigger Source Edge Select" "Falling,Rising"
|
|
line.byte 0x07 "VBTWFR,VBATT Wakeup Trigger Source Flag Register"
|
|
bitfld.byte 0x07 5. " VAGTUF ,VBATT AGT1 Underflow Wakeup Trigger Flag" "No trigger,Trigger"
|
|
bitfld.byte 0x07 4. " VRTCAF ,VBATT RTC-Alarm Wakeup Trigger Flag" "No trigger,Trigger"
|
|
bitfld.byte 0x07 3. " VRTCIF ,VBATT RTC-Periodic Wakeup Trigger Flag" "No trigger,Trigger"
|
|
bitfld.byte 0x07 2. " VCH2F ,VBATWIO2 Wakeup Trigger Flag" "No trigger,Trigger"
|
|
textline " "
|
|
bitfld.byte 0x07 1. " VCH1F ,VBATWIO1 Wakeup Trigger Flag" "No trigger,Trigger"
|
|
bitfld.byte 0x07 0. " VCH0F ,VBATWIO0 Wakeup Trigger Flag" "No trigger,Trigger"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RWP (Register Write Protection)"
|
|
base ad:0x4001E3FE
|
|
width 6.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRCR,Protect Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " PRKEY ,PRC Key Code"
|
|
bitfld.word 0x00 3. " PRC3 ,LVD Registers Protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " PRC1 ,Low Power Mode and Battery Backup Registers Protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " PRC0 ,Clock Generation Circuit Registers Protection" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ICU (Interrupt Controller Unit)"
|
|
base ad:0x40006000
|
|
width 9.
|
|
tree "IRQCR[0:15],IRQ Control Registers"
|
|
group.byte 0x0++0x00
|
|
line.byte 0x00 "IRQCR0,IRQ Control Register 0"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ0 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ0 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ0 Detection Sense Select" "Falling,Rising,Both,Low level"
|
|
group.byte 0x1++0x00
|
|
line.byte 0x00 "IRQCR1,IRQ Control Register 1"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ1 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ1 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ1 Detection Sense Select" "Falling,Rising,Both,Low level"
|
|
group.byte 0x2++0x00
|
|
line.byte 0x00 "IRQCR2,IRQ Control Register 2"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ2 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ2 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ2 Detection Sense Select" "Falling,Rising,Both,Low level"
|
|
group.byte 0x3++0x00
|
|
line.byte 0x00 "IRQCR3,IRQ Control Register 3"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ3 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ3 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ3 Detection Sense Select" "Falling,Rising,Both,Low level"
|
|
group.byte 0x4++0x00
|
|
line.byte 0x00 "IRQCR4,IRQ Control Register 4"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ4 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ4 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ4 Detection Sense Select" "Falling,Rising,Both,Low level"
|
|
group.byte 0x5++0x00
|
|
line.byte 0x00 "IRQCR5,IRQ Control Register 5"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ5 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ5 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ5 Detection Sense Select" "Falling,Rising,Both,Low level"
|
|
group.byte 0x6++0x00
|
|
line.byte 0x00 "IRQCR6,IRQ Control Register 6"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ6 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ6 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ6 Detection Sense Select" "Falling,Rising,Both,Low level"
|
|
group.byte 0x7++0x00
|
|
line.byte 0x00 "IRQCR7,IRQ Control Register 7"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ7 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ7 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ7 Detection Sense Select" "Falling,Rising,Both,Low level"
|
|
group.byte 0x8++0x00
|
|
line.byte 0x00 "IRQCR8,IRQ Control Register 8"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ8 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ8 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ8 Detection Sense Select" "Falling,Rising,Both,Low level"
|
|
group.byte 0x9++0x00
|
|
line.byte 0x00 "IRQCR9,IRQ Control Register 9"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ9 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ9 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ9 Detection Sense Select" "Falling,Rising,Both,Low level"
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "IRQCR10,IRQ Control Register 10"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ10 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ10 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ10 Detection Sense Select" "Falling,Rising,Both,Low level"
|
|
group.byte 0xB++0x00
|
|
line.byte 0x00 "IRQCR11,IRQ Control Register 11"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ11 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ11 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ11 Detection Sense Select" "Falling,Rising,Both,Low level"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "IRQCR12,IRQ Control Register 12"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ12 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ12 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ12 Detection Sense Select" "Falling,Rising,Both,Low level"
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "IRQCR13,IRQ Control Register 13"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ13 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ13 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ13 Detection Sense Select" "Falling,Rising,Both,Low level"
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "IRQCR14,IRQ Control Register 14"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ14 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ14 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ14 Detection Sense Select" "Falling,Rising,Both,Low level"
|
|
group.byte 0xF++0x00
|
|
line.byte 0x00 "IRQCR15,IRQ Control Register 15"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ15 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ15 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ15 Detection Sense Select" "Falling,Rising,Both,Low level"
|
|
tree.end
|
|
textline " "
|
|
rgroup.word 0x140++0x01
|
|
line.word 0x00 "NMISR,Non-Maskable Interrupt Status Register"
|
|
bitfld.word 0x00 12. " SPEST ,CPU Stack pointer monitor Interrupt Status Flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 11. " BUSMST ,MPU Bus Master Error Interrupt Status Flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 10. " BUSSST ,MPU Bus Slave Error Interrupt Status Flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 9. " RECCST ,SRAM ECC Error Interrupt Status Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 8. " RPEST ,SRAM Parity Error Interrupt Status Flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " NMIST ,NMI Status Flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " OSTST ,Oscillation Stop Detection Interrupt Status Flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 4. " VBATTST ,VBATT monitor Interrupt Status Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 3. " LVD2ST ,Voltage Monitor 2 Interrupt Status Flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 2. " LVD1ST ,Voltage Monitor 1 Interrupt Status Flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1. " WDTST ,WDT Underflow/Refresh Error Status Flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " IWDTST ,IWDT Underflow/Refresh Error Status Flag" "No interrupt,Interrupt"
|
|
group.word 0x120++0x01
|
|
line.word 0x00 "NMIER,Non-Maskable Interrupt Enable Register"
|
|
bitfld.word 0x00 12. " SPEEN ,CPU Stack Pointer Monitor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " BUSMEN ,MPU Bus Master Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " BUSSEN ,MPU Bus Slave Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " RECCEN ,SRAM ECC Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " RPEEN ,SRAM Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " NMIEN ,NMI Pin Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " OSTEN ,Oscillation Stop Detection Interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " VBATTEN ,VBATT monitor Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " LVD2EN ,Voltage Monitor 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " LVD1EN ,Voltage monitor 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WDTEN ,WDT Underflow/Refresh Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " IWDTEN ,IWDT Underflow/Refresh Error Interrupt Enable" "Disabled,Enabled"
|
|
group.word 0x130++0x01
|
|
line.word 0x00 "NMICLR,Non-Maskable Interrupt Status Clear Register"
|
|
bitfld.word 0x00 12. " SPECLR ,CPU Stack Pointer Monitor Interrupt Clear" "No effect,Cleared"
|
|
bitfld.word 0x00 11. " BUSMCLR ,Bus Master Error Clear" "No effect,Cleared"
|
|
bitfld.word 0x00 10. " BUSSCLR ,Bus Slave Error Clear" "No effect,Cleared"
|
|
bitfld.word 0x00 9. " RECCCLR ,SRAM ECC Error Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 8. " RPECLR ,SRAM Parity Error Clear" "No effect,Cleared"
|
|
bitfld.word 0x00 7. " NMICLR ,NMI Clear" "No effect,Cleared"
|
|
bitfld.word 0x00 6. " OSTCLR ,OST Clear" "No effect,Cleared"
|
|
bitfld.word 0x00 4. " VBATTCLR ,VBATT Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 3. " LVD2CLR ,LVD2 Clear" "No effect,Cleared"
|
|
bitfld.word 0x00 2. " LVD1CLR ,LVD1 Clear" "No effect,Cleared"
|
|
bitfld.word 0x00 1. " WDTCLR ,WDT Clear" "No effect,Cleared"
|
|
bitfld.word 0x00 0. " IWDTCLR ,IWDT Clear" "No effect,Cleared"
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "NMICR,NMI Pin Interrupt Control Register"
|
|
bitfld.byte 0x00 7. " NFLTEN ,NMI Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " NFCLKSEL ,NMI Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0. " NMIMD ,NMI Detection Set" "Falling,Rising"
|
|
tree "IELSR[0:63],ICU Event Link Setting Register"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "IELSR0,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "IELSR1,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "IELSR2,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "IELSR3,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "IELSR4,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "IELSR5,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "IELSR6,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "IELSR7,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "IELSR8,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "IELSR9,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "IELSR10,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "IELSR11,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "IELSR12,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x334++0x03
|
|
line.long 0x00 "IELSR13,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "IELSR14,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x33C++0x03
|
|
line.long 0x00 "IELSR15,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "IELSR16,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "IELSR17,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "IELSR18,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "IELSR19,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "IELSR20,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "IELSR21,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "IELSR22,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x35C++0x03
|
|
line.long 0x00 "IELSR23,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "IELSR24,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x364++0x03
|
|
line.long 0x00 "IELSR25,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x368++0x03
|
|
line.long 0x00 "IELSR26,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x36C++0x03
|
|
line.long 0x00 "IELSR27,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "IELSR28,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x374++0x03
|
|
line.long 0x00 "IELSR29,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x378++0x03
|
|
line.long 0x00 "IELSR30,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x37C++0x03
|
|
line.long 0x00 "IELSR31,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "IELSR32,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "IELSR33,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "IELSR34,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "IELSR35,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "IELSR36,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "IELSR37,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "IELSR38,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "IELSR39,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "IELSR40,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3A4++0x03
|
|
line.long 0x00 "IELSR41,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3A8++0x03
|
|
line.long 0x00 "IELSR42,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3AC++0x03
|
|
line.long 0x00 "IELSR43,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "IELSR44,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3B4++0x03
|
|
line.long 0x00 "IELSR45,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3B8++0x03
|
|
line.long 0x00 "IELSR46,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3BC++0x03
|
|
line.long 0x00 "IELSR47,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "IELSR48,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3C4++0x03
|
|
line.long 0x00 "IELSR49,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3C8++0x03
|
|
line.long 0x00 "IELSR50,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3CC++0x03
|
|
line.long 0x00 "IELSR51,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3D0++0x03
|
|
line.long 0x00 "IELSR52,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3D4++0x03
|
|
line.long 0x00 "IELSR53,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3D8++0x03
|
|
line.long 0x00 "IELSR54,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3DC++0x03
|
|
line.long 0x00 "IELSR55,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "IELSR56,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3E4++0x03
|
|
line.long 0x00 "IELSR57,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3E8++0x03
|
|
line.long 0x00 "IELSR58,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3EC++0x03
|
|
line.long 0x00 "IELSR59,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3F0++0x03
|
|
line.long 0x00 "IELSR60,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3F4++0x03
|
|
line.long 0x00 "IELSR61,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3F8++0x03
|
|
line.long 0x00 "IELSR62,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3FC++0x03
|
|
line.long 0x00 "IELSR63,ICU Event Link Setting Registers"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.word 0x00 0.--8. 1. " IELS ,ICU Event Link Select"
|
|
tree.end
|
|
textline " "
|
|
group.word 0x280++0x01
|
|
line.word 0x00 "DELSR0,DMAC Event Link Setting Register 0"
|
|
hexmask.word 0x00 0.--8. 1. " DELS ,DMAC Event Link Select"
|
|
group.word 0x284++0x01
|
|
line.word 0x00 "DELSR1,DMAC Event Link Setting Register 1"
|
|
hexmask.word 0x00 0.--8. 1. " DELS ,DMAC Event Link Select"
|
|
group.word 0x288++0x01
|
|
line.word 0x00 "DELSR2,DMAC Event Link Setting Register 2"
|
|
hexmask.word 0x00 0.--8. 1. " DELS ,DMAC Event Link Select"
|
|
group.word 0x28C++0x01
|
|
line.word 0x00 "DELSR3,DMAC Event Link Setting Register 3"
|
|
hexmask.word 0x00 0.--8. 1. " DELS ,DMAC Event Link Select"
|
|
group.word 0x200++0x01
|
|
line.word 0x00 "SELSR0,SYS Event Link Setting Register"
|
|
hexmask.word 0x00 0.--8. 1. " SELS ,SYS Event Link Select"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "WUPEN,Wake Up Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " IIC0WUPEN ,IIC0 Address Match Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " AGT1CBWUPEN ,AGT1 Compare Match B Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " AGT1CAWUPEN ,AGT1 Compare Match A Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " AGT1UDWUPEN ,AGT1 Underflow Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " USBFSWUPEN ,USBFS Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " RTCPRDWUPEN ,RTC Period Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RTCALMWUPEN ,RTC Alarm Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ACMPLP0WUPEN ,ACMPLP0 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " VBATTWUPEN ,VBATT Monitor Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " LVD2WUPEN ,LVD2 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " LVD1WUPEN ,LVD1 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " KEYWUPEN ,Key Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IWDTWUPEN ,IWDT Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " IRQWUPEN15 ,IRQ15 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " IRQWUPEN14 ,IRQ14 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " IRQWUPEN13 ,IRQ13 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IRQWUPEN12 ,IRQ12 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " IRQWUPEN11 ,IRQ11 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " IRQWUPEN10 ,IRQ10 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " IRQWUPEN9 ,IRQ9 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IRQWUPEN8 ,IRQ8 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " IRQWUPEN7 ,IRQ7 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IRQWUPEN6 ,IRQ6 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IRQWUPEN5 ,IRQ5 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQWUPEN4 ,IRQ4 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IRQWUPEN3 ,IRQ3 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IRQWUPEN2 ,IRQ2 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IRQWUPEN1 ,IRQ1 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRQWUPEN0 ,IRQ0 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
tree "Buses"
|
|
base ad:0x40003000
|
|
width 13.
|
|
group.word 0x802++0x01
|
|
line.word 0x00 "CS0CR,CS0 Control Register"
|
|
bitfld.word 0x00 8. " EMODE ,Endian Mode" "Little,Big"
|
|
bitfld.word 0x00 4.--5. " BSIZE ,External Bus Width Select" "16-bit,,8-bit,"
|
|
bitfld.word 0x00 0. " EXENB ,Operation Enable" "Disabled,Enabled"
|
|
group.word 0x812++0x01
|
|
line.word 0x00 "CS1CR,CS1 Control Register"
|
|
bitfld.word 0x00 8. " EMODE ,Endian Mode" "Little,Big"
|
|
bitfld.word 0x00 4.--5. " BSIZE ,External Bus Width Select" "16-bit,,8-bit,"
|
|
bitfld.word 0x00 0. " EXENB ,Operation Enable" "Disabled,Enabled"
|
|
group.word 0x822++0x01
|
|
line.word 0x00 "CS2CR,CS2 Control Register"
|
|
bitfld.word 0x00 8. " EMODE ,Endian Mode" "Little,Big"
|
|
bitfld.word 0x00 4.--5. " BSIZE ,External Bus Width Select" "16-bit,,8-bit,"
|
|
bitfld.word 0x00 0. " EXENB ,Operation Enable" "Disabled,Enabled"
|
|
group.word 0x832++0x01
|
|
line.word 0x00 "CS3CR,CS3 Control Register"
|
|
bitfld.word 0x00 8. " EMODE ,Endian Mode" "Little,Big"
|
|
bitfld.word 0x00 4.--5. " BSIZE ,External Bus Width Select" "16-bit,,8-bit,"
|
|
bitfld.word 0x00 0. " EXENB ,Operation Enable" "Disabled,Enabled"
|
|
group.word 0x80A++0x01
|
|
line.word 0x00 "CS0REC,CS0 Recovery Cycle Register"
|
|
bitfld.word 0x00 8.--11. " WRCV ,Write Recovery" "No cycles,1 cycle,2 cycless,3 cycless,4 cycless,5 cycless,6 cycless,7 cycless,8 cycless,9 cycless,10 cycless,11 cycles,12 cycless,13 cycless,14 cycless,15 cycless"
|
|
bitfld.word 0x00 0.--3. " RRCV ,Read Recovery" "No cycles,1 cycle,2 cycless,3 cycless,4 cycless,5 cycless,6 cycless,7 cycless,8 cycless,9 cycless,10 cycless,11 cycles,12 cycless,13 cycless,14 cycless,15 cycless"
|
|
group.word 0x81A++0x01
|
|
line.word 0x00 "CS1REC,CS1 Recovery Cycle Register"
|
|
bitfld.word 0x00 8.--11. " WRCV ,Write Recovery" "No cycles,1 cycle,2 cycless,3 cycless,4 cycless,5 cycless,6 cycless,7 cycless,8 cycless,9 cycless,10 cycless,11 cycles,12 cycless,13 cycless,14 cycless,15 cycless"
|
|
bitfld.word 0x00 0.--3. " RRCV ,Read Recovery" "No cycles,1 cycle,2 cycless,3 cycless,4 cycless,5 cycless,6 cycless,7 cycless,8 cycless,9 cycless,10 cycless,11 cycles,12 cycless,13 cycless,14 cycless,15 cycless"
|
|
group.word 0x82A++0x01
|
|
line.word 0x00 "CS2REC,CS2 Recovery Cycle Register"
|
|
bitfld.word 0x00 8.--11. " WRCV ,Write Recovery" "No cycles,1 cycle,2 cycless,3 cycless,4 cycless,5 cycless,6 cycless,7 cycless,8 cycless,9 cycless,10 cycless,11 cycles,12 cycless,13 cycless,14 cycless,15 cycless"
|
|
bitfld.word 0x00 0.--3. " RRCV ,Read Recovery" "No cycles,1 cycle,2 cycless,3 cycless,4 cycless,5 cycless,6 cycless,7 cycless,8 cycless,9 cycless,10 cycless,11 cycles,12 cycless,13 cycless,14 cycless,15 cycless"
|
|
group.word 0x83A++0x01
|
|
line.word 0x00 "CS3REC,CS3 Recovery Cycle Register"
|
|
bitfld.word 0x00 8.--11. " WRCV ,Write Recovery" "No cycles,1 cycle,2 cycless,3 cycless,4 cycless,5 cycless,6 cycless,7 cycless,8 cycless,9 cycless,10 cycless,11 cycles,12 cycless,13 cycless,14 cycless,15 cycless"
|
|
bitfld.word 0x00 0.--3. " RRCV ,Read Recovery" "No cycles,1 cycle,2 cycless,3 cycless,4 cycless,5 cycless,6 cycless,7 cycless,8 cycless,9 cycless,10 cycless,11 cycles,12 cycless,13 cycless,14 cycless,15 cycless"
|
|
group.word 0x880++0x01
|
|
line.word 0x00 "CSRECEN,CS Recovery Cycle Insertion Enable Register"
|
|
bitfld.word 0x00 7. " RCVEN7 ,Separate Bus Recovery Cycle Insertion Enable 7" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RCVEN6 ,Separate Bus Recovery Cycle Insertion Enable 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RCVEN5 ,Separate Bus Recovery Cycle Insertion Enable 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RCVEN4 ,Separate Bus Recovery Cycle Insertion Enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RCVEN3 ,Separate Bus Recovery Cycle Insertion Enable 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RCVEN2 ,Separate Bus Recovery Cycle Insertion Enable 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RCVEN1 ,Separate Bus Recovery Cycle Insertion Enable 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RCVEN0 ,Separate Bus Recovery Cycle Insertion Enable 0" "Disabled,Enabled"
|
|
group.word 0x2++0x01
|
|
line.word 0x00 "CS0MOD,CS0 Mode Register"
|
|
bitfld.word 0x00 15. " PRMOD ,Page Read Access Mode Select" "Normal,External"
|
|
bitfld.word 0x00 9. " PWENB ,Page Write Access Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRENB ,Page Read Access Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " EWENB ,External Wait Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " WRMOD ,Write Access Mode Select" "Byte,Single"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "CS1MOD,CS1 Mode Register"
|
|
bitfld.word 0x00 15. " PRMOD ,Page Read Access Mode Select" "Normal,External"
|
|
bitfld.word 0x00 9. " PWENB ,Page Write Access Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRENB ,Page Read Access Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " EWENB ,External Wait Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " WRMOD ,Write Access Mode Select" "Byte,Single"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "CS2MOD,CS2 Mode Register"
|
|
bitfld.word 0x00 15. " PRMOD ,Page Read Access Mode Select" "Normal,External"
|
|
bitfld.word 0x00 9. " PWENB ,Page Write Access Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRENB ,Page Read Access Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " EWENB ,External Wait Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " WRMOD ,Write Access Mode Select" "Byte,Single"
|
|
group.word 0x32++0x01
|
|
line.word 0x00 "CS3MOD,CS3 Mode Register"
|
|
bitfld.word 0x00 15. " PRMOD ,Page Read Access Mode Select" "Normal,External"
|
|
bitfld.word 0x00 9. " PWENB ,Page Write Access Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRENB ,Page Read Access Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " EWENB ,External Wait Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " WRMOD ,Write Access Mode Select" "Byte,Single"
|
|
if (((per.w(ad:0x40003000+0x2))&0x200)==0x200)&&(((per.w(ad:0x40003000+0x2))&0x100)==0x100)
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "CS0WCR1,CS0 Wait Control Register 1"
|
|
bitfld.long 0x00 24.--28. " CSRWAIT ,Normal Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 16.--20. " CSWWAIT ,Normal Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 8.--10. " CSPRWAIT ,Page Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " CSPWWAIT ,Page Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
elif (((per.w(ad:0x40003000+0x2))&0x200)==0x200)
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "CS0WCR1,CS0 Wait Control Register 1"
|
|
bitfld.long 0x00 24.--28. " CSRWAIT ,Normal Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 16.--20. " CSWWAIT ,Normal Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 0.--2. " CSPWWAIT ,Page Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
elif (((per.w(ad:0x40003000+0x2))&0x100)==0x100)
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "CS0WCR1,CS0 Wait Control Register 1"
|
|
bitfld.long 0x00 24.--28. " CSRWAIT ,Normal Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 16.--20. " CSWWAIT ,Normal Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 8.--10. " CSPRWAIT ,Page Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "CS0WCR1,CS0 Wait Control Register 1"
|
|
bitfld.long 0x00 24.--28. " CSRWAIT ,Normal Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 16.--20. " CSWWAIT ,Normal Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
endif
|
|
if (((per.w(ad:0x40003000+0x12))&0x200)==0x200)&&(((per.w(ad:0x40003000+0x12))&0x100)==0x100)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CS1WCR1,CS1 Wait Control Register 1"
|
|
bitfld.long 0x00 24.--28. " CSRWAIT ,Normal Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 16.--20. " CSWWAIT ,Normal Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 8.--10. " CSPRWAIT ,Page Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " CSPWWAIT ,Page Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
elif (((per.w(ad:0x40003000+0x12))&0x200)==0x200)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CS1WCR1,CS1 Wait Control Register 1"
|
|
bitfld.long 0x00 24.--28. " CSRWAIT ,Normal Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 16.--20. " CSWWAIT ,Normal Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 0.--2. " CSPWWAIT ,Page Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
elif (((per.w(ad:0x40003000+0x12))&0x100)==0x100)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CS1WCR1,CS1 Wait Control Register 1"
|
|
bitfld.long 0x00 24.--28. " CSRWAIT ,Normal Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 16.--20. " CSWWAIT ,Normal Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 8.--10. " CSPRWAIT ,Page Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CS1WCR1,CS1 Wait Control Register 1"
|
|
bitfld.long 0x00 24.--28. " CSRWAIT ,Normal Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 16.--20. " CSWWAIT ,Normal Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
endif
|
|
if (((per.w(ad:0x40003000+0x22))&0x200)==0x200)&&(((per.w(ad:0x40003000+0x22))&0x100)==0x100)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CS2WCR1,CS2 Wait Control Register 1"
|
|
bitfld.long 0x00 24.--28. " CSRWAIT ,Normal Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 16.--20. " CSWWAIT ,Normal Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 8.--10. " CSPRWAIT ,Page Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " CSPWWAIT ,Page Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
elif (((per.w(ad:0x40003000+0x22))&0x200)==0x200)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CS2WCR1,CS2 Wait Control Register 1"
|
|
bitfld.long 0x00 24.--28. " CSRWAIT ,Normal Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 16.--20. " CSWWAIT ,Normal Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 0.--2. " CSPWWAIT ,Page Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
elif (((per.w(ad:0x40003000+0x22))&0x100)==0x100)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CS2WCR1,CS2 Wait Control Register 1"
|
|
bitfld.long 0x00 24.--28. " CSRWAIT ,Normal Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 16.--20. " CSWWAIT ,Normal Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 8.--10. " CSPRWAIT ,Page Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CS2WCR1,CS2 Wait Control Register 1"
|
|
bitfld.long 0x00 24.--28. " CSRWAIT ,Normal Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 16.--20. " CSWWAIT ,Normal Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
endif
|
|
if (((per.w(ad:0x40003000+0x32))&0x200)==0x200)&&(((per.w(ad:0x40003000+0x32))&0x100)==0x100)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CS3WCR1,CS3 Wait Control Register 1"
|
|
bitfld.long 0x00 24.--28. " CSRWAIT ,Normal Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 16.--20. " CSWWAIT ,Normal Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 8.--10. " CSPRWAIT ,Page Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " CSPWWAIT ,Page Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
elif (((per.w(ad:0x40003000+0x32))&0x200)==0x200)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CS3WCR1,CS3 Wait Control Register 1"
|
|
bitfld.long 0x00 24.--28. " CSRWAIT ,Normal Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 16.--20. " CSWWAIT ,Normal Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 0.--2. " CSPWWAIT ,Page Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
elif (((per.w(ad:0x40003000+0x32))&0x100)==0x100)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CS3WCR1,CS3 Wait Control Register 1"
|
|
bitfld.long 0x00 24.--28. " CSRWAIT ,Normal Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 16.--20. " CSWWAIT ,Normal Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 8.--10. " CSPRWAIT ,Page Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CS3WCR1,CS3 Wait Control Register 1"
|
|
bitfld.long 0x00 24.--28. " CSRWAIT ,Normal Read Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
bitfld.long 0x00 16.--20. " CSWWAIT ,Normal Write Cycle Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycle"
|
|
endif
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "CS0WCR2,CS0 Wait Control Register 2"
|
|
bitfld.long 0x00 28.--30. " CSON ,CS Assert Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 24.--26. " WDON ,Write Data Output Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 20.--22. " WRON ,WR Assert Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 16.--18. " RDON ,RD Assert Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " WDOFF ,Write Data Output Extension Cycle Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 4.--6. " CSWOFF ,Write-Access CS Extension Cycle Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " CSROFF ,Read-Access CS Extension Cycle Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CS1WCR2,CS1 Wait Control Register 2"
|
|
bitfld.long 0x00 28.--30. " CSON ,CS Assert Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 24.--26. " WDON ,Write Data Output Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 20.--22. " WRON ,WR Assert Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 16.--18. " RDON ,RD Assert Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " WDOFF ,Write Data Output Extension Cycle Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 4.--6. " CSWOFF ,Write-Access CS Extension Cycle Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " CSROFF ,Read-Access CS Extension Cycle Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CS2WCR2,CS2 Wait Control Register 2"
|
|
bitfld.long 0x00 28.--30. " CSON ,CS Assert Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 24.--26. " WDON ,Write Data Output Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 20.--22. " WRON ,WR Assert Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 16.--18. " RDON ,RD Assert Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " WDOFF ,Write Data Output Extension Cycle Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 4.--6. " CSWOFF ,Write-Access CS Extension Cycle Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " CSROFF ,Read-Access CS Extension Cycle Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CS3WCR2,CS3 Wait Control Register 2"
|
|
bitfld.long 0x00 28.--30. " CSON ,CS Assert Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 24.--26. " WDON ,Write Data Output Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 20.--22. " WRON ,WR Assert Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 16.--18. " RDON ,RD Assert Wait Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " WDOFF ,Write Data Output Extension Cycle Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 4.--6. " CSWOFF ,Write-Access CS Extension Cycle Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " CSROFF ,Read-Access CS Extension Cycle Select" "No wait,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
group.word ad:0x40004000++0x01
|
|
line.word 0x00 "BUSMCNTM4I,Master Bus Control Register"
|
|
bitfld.word 0x00 15. " IERES ,Ignore Error Responses" "Reported,Not reported"
|
|
group.word (ad:0x40004000+0x4)++0x01
|
|
line.word 0x00 "BUSMCNTM4D,Master Bus Control Register"
|
|
bitfld.word 0x00 15. " IERES ,Ignore Error Responses" "Reported,Not reported"
|
|
group.word (ad:0x40004000+0x8)++0x01
|
|
line.word 0x00 "BUSMCNTSYS,Master Bus Control Register"
|
|
bitfld.word 0x00 15. " IERES ,Ignore Error Responses" "Reported,Not reported"
|
|
group.word (ad:0x40004000+0xC)++0x01
|
|
line.word 0x00 "BUSMCNTDMA,Master Bus Control Register"
|
|
bitfld.word 0x00 15. " IERES ,Ignore Error Responses" "Reported,Not reported"
|
|
group.word (ad:0x40004000+0x100)++0x01
|
|
line.word 0x00 "BUSSCNTFLI,Slave Bus Control Register"
|
|
bitfld.word 0x00 4.--5. " ARBMET ,Arbitration Method" "Fixed priority,Round-robin,,"
|
|
group.word (ad:0x40004000+0x108)++0x01
|
|
line.word 0x00 "BUSSCNTMBIU,Slave Bus Control Register"
|
|
bitfld.word 0x00 4.--5. " ARBMET ,Arbitration Method" "Fixed priority,Round-robin,,"
|
|
group.word (ad:0x40004000+0x10C)++0x01
|
|
line.word 0x00 "BUSSCNTRAM0,Slave Bus Control Register"
|
|
bitfld.word 0x00 4.--5. " ARBMET ,Arbitration Method" "Fixed priority,Round-robin,,"
|
|
group.word (ad:0x40004000+0x110)++0x01
|
|
line.word 0x00 "BUSSCNTRAM1,Slave Bus Control Register"
|
|
bitfld.word 0x00 4.--5. " ARBMET ,Arbitration Method" "Fixed priority,Round-robin,,"
|
|
group.word (ad:0x40004000+0x114)++0x01
|
|
line.word 0x00 "BUSSCNTP0B,Slave Bus Control Register"
|
|
bitfld.word 0x00 4.--5. " ARBMET ,Arbitration Method" "Fixed priority,Round-robin,,"
|
|
group.word (ad:0x40004000+0x118)++0x01
|
|
line.word 0x00 "BUSSCNTP2B,Slave Bus Control Register"
|
|
bitfld.word 0x00 4.--5. " ARBMET ,Arbitration Method" "Fixed priority,Round-robin,,"
|
|
group.word (ad:0x40004000+0x11C)++0x01
|
|
line.word 0x00 "BUSSCNTP3B,Slave Bus Control Register"
|
|
bitfld.word 0x00 4.--5. " ARBMET ,Arbitration Method" "Fixed priority,Round-robin,,"
|
|
group.word (ad:0x40004000+0x120)++0x01
|
|
line.word 0x00 "BUSSCNTP4B,Slave Bus Control Register"
|
|
bitfld.word 0x00 4.--5. " ARBMET ,Arbitration Method" "Fixed priority,Round-robin,,"
|
|
group.word (ad:0x40004000+0x128)++0x01
|
|
line.word 0x00 "BUSSCNTP6B,Slave Bus Control Register"
|
|
bitfld.word 0x00 4.--5. " ARBMET ,Arbitration Method" "Fixed priority,Round-robin,,"
|
|
group.word (ad:0x40004000+0x130)++0x01
|
|
line.word 0x00 "BUSSCNTFBU,Slave Bus Control Register"
|
|
bitfld.word 0x00 4.--5. " ARBMET ,Arbitration Method" "Fixed priority,Round-robin,,"
|
|
group.word (ad:0x40004000+0x134)++0x01
|
|
line.word 0x00 "BUSSCNTEXT,Slave Bus Control Register"
|
|
bitfld.word 0x00 4.--5. " ARBMET ,Arbitration Method" "Fixed priority,Round-robin,,"
|
|
group.word (ad:0x40004000+0x138)++0x01
|
|
line.word 0x00 "BUSSCNTEXT2,Slave Bus Control Register"
|
|
bitfld.word 0x00 4.--5. " ARBMET ,Arbitration Method" "Fixed priority,Round-robin,,"
|
|
rgroup.long (0x800+ad:0x40004000)++0x03
|
|
line.long 0x00 "BUS1ERRADD,Bus Error Address Register"
|
|
rgroup.long (0x810+ad:0x40004000)++0x03
|
|
line.long 0x00 "BUS2ERRADD,Bus Error Address Register"
|
|
rgroup.long (0x820+ad:0x40004000)++0x03
|
|
line.long 0x00 "BUS3ERRADD,Bus Error Address Register"
|
|
rgroup.long (0x830+ad:0x40004000)++0x03
|
|
line.long 0x00 "BUS4ERRADD,Bus Error Address Register"
|
|
rgroup.byte (0x804+ad:0x40004000)++0x03
|
|
line.byte 0x00 "BUS1ERRSTAT,Bus Error Status Register"
|
|
bitfld.byte 0x00 7. " ERRSTAT ,Bus Error Status" "No error,Error"
|
|
bitfld.byte 0x00 0. " ACCSTAT ,Error Access Status" "Write,Read"
|
|
rgroup.byte (0x814+ad:0x40004000)++0x03
|
|
line.byte 0x00 "BUS2ERRSTAT,Bus Error Status Register"
|
|
bitfld.byte 0x00 7. " ERRSTAT ,Bus Error Status" "No error,Error"
|
|
bitfld.byte 0x00 0. " ACCSTAT ,Error Access Status" "Write,Read"
|
|
rgroup.byte (0x824+ad:0x40004000)++0x03
|
|
line.byte 0x00 "BUS3ERRSTAT,Bus Error Status Register"
|
|
bitfld.byte 0x00 7. " ERRSTAT ,Bus Error Status" "No error,Error"
|
|
bitfld.byte 0x00 0. " ACCSTAT ,Error Access Status" "Write,Read"
|
|
rgroup.byte (0x834+ad:0x40004000)++0x03
|
|
line.byte 0x00 "BUS4ERRSTAT,Bus Error Status Register"
|
|
bitfld.byte 0x00 7. " ERRSTAT ,Bus Error Status" "No error,Error"
|
|
bitfld.byte 0x00 0. " ACCSTAT ,Error Access Status" "Write,Read"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "MPU (Memory Protection Unit)"
|
|
base ad:0x40000000
|
|
width 12.
|
|
tree "CPU Stack Pointer Monitor"
|
|
group.long 0xD08++0x07
|
|
line.long 0x00 "MSPMPUSA,Main Stack Pointer Monitor Start Address Register"
|
|
line.long 0x04 "MSPMPUEA,Main Stack Pointer Monitor End Address Register"
|
|
group.long 0xD18++0x07
|
|
line.long 0x00 "PSPMPUSA,Process Stack Pointer Monitor Start Address Register"
|
|
line.long 0x04 "PSPMPUEA,Process Stack Pointer Monitor End Address Register"
|
|
group.word 0xD00++0x01
|
|
line.word 0x00 "MSPMPUOAD,Stack Pointer Monitor Operation After Detection Register"
|
|
hexmask.word.BYTE 0x00 8.--15. 1. " KEY ,Key code"
|
|
bitfld.word 0x00 0. " OAD ,Operation after detection" "Interrupt,Reset"
|
|
group.word 0xD10++0x01
|
|
line.word 0x00 "PSPMPUOAD,Stack Pointer Monitor Operation After Detection Register"
|
|
hexmask.word.BYTE 0x00 8.--15. 1. " KEY ,Key code"
|
|
bitfld.word 0x00 0. " OAD ,Operation after detection" "Interrupt,Reset"
|
|
group.word 0xD04++0x01
|
|
line.word 0x00 "MSPMPUCTL,Stack Pointer Monitor Access Control Register"
|
|
bitfld.word 0x00 8. " ERROR ,Stack pointer monitor error flag" "No error,Error"
|
|
bitfld.word 0x00 0. " ENABLE ,Stack pointer monitor enable" "Disabled,Enabled"
|
|
group.word 0xD14++0x01
|
|
line.word 0x00 "PSPMPUCTL,Stack Pointer Monitor Access Control Register"
|
|
bitfld.word 0x00 8. " ERROR ,Stack pointer monitor error flag" "No error,Error"
|
|
bitfld.word 0x00 0. " ENABLE ,Stack pointer monitor enable" "Disabled,Enabled"
|
|
group.word 0xD06++0x01
|
|
line.word 0x00 "MSPMPUPT,Stack Pointer Monitor Protection Register"
|
|
hexmask.word.BYTE 0x00 8.--15. 1. " KEY ,Key code"
|
|
bitfld.word 0x00 0. " PROTECT ,Protection register" "Not protected,Protected"
|
|
group.word 0xD16++0x01
|
|
line.word 0x00 "PSPMPUPT,Stack Pointer Monitor Protection Register"
|
|
hexmask.word.BYTE 0x00 8.--15. 1. " KEY ,Key code"
|
|
bitfld.word 0x00 0. " PROTECT ,Protection register" "Not protected,Protected"
|
|
tree.end
|
|
tree "Bus Master MPU"
|
|
sif cpuis("R7FS5*")
|
|
group.long (0x200+0x4)++0x03
|
|
line.long 0x00 "MMPUSA0,Group A Region 0 Start Address Register"
|
|
group.long (0x200+0x14)++0x03
|
|
line.long 0x00 "MMPUSA1,Group A Region 1 Start Address Register"
|
|
group.long (0x200+0x24)++0x03
|
|
line.long 0x00 "MMPUSA2,Group A Region 2 Start Address Register"
|
|
group.long (0x200+0x34)++0x03
|
|
line.long 0x00 "MMPUSA3,Group A Region 3 Start Address Register"
|
|
group.long (0x200+0x44)++0x03
|
|
line.long 0x00 "MMPUSA4,Group A Region 4 Start Address Register"
|
|
group.long (0x200+0x54)++0x03
|
|
line.long 0x00 "MMPUSA5,Group A Region 5 Start Address Register"
|
|
group.long (0x200+0x64)++0x03
|
|
line.long 0x00 "MMPUSA6,Group A Region 6 Start Address Register"
|
|
group.long (0x200+0x74)++0x03
|
|
line.long 0x00 "MMPUSA7,Group A Region 7 Start Address Register"
|
|
group.long (0x200+0x84)++0x03
|
|
line.long 0x00 "MMPUSA8,Group A Region 8 Start Address Register"
|
|
group.long (0x200+0x94)++0x03
|
|
line.long 0x00 "MMPUSA9,Group A Region 9 Start Address Register"
|
|
group.long (0x200+0xA4)++0x03
|
|
line.long 0x00 "MMPUSA10,Group A Region 10 Start Address Register"
|
|
group.long (0x200+0xB4)++0x03
|
|
line.long 0x00 "MMPUSA11,Group A Region 11 Start Address Register"
|
|
group.long (0x200+0xC4)++0x03
|
|
line.long 0x00 "MMPUSA12,Group A Region 12 Start Address Register"
|
|
group.long (0x200+0xD4)++0x03
|
|
line.long 0x00 "MMPUSA13,Group A Region 13 Start Address Register"
|
|
group.long (0x200+0xE4)++0x03
|
|
line.long 0x00 "MMPUSA14,Group A Region 14 Start Address Register"
|
|
group.long (0x200+0xF4)++0x03
|
|
line.long 0x00 "MMPUSA15,Group A Region 15 Start Address Register"
|
|
group.long (0x200+0x104)++0x03
|
|
line.long 0x00 "MMPUSA16,Group A Region 16 Start Address Register"
|
|
group.long (0x200+0x114)++0x03
|
|
line.long 0x00 "MMPUSA17,Group A Region 17 Start Address Register"
|
|
group.long (0x200+0x124)++0x03
|
|
line.long 0x00 "MMPUSA18,Group A Region 18 Start Address Register"
|
|
group.long (0x200+0x134)++0x03
|
|
line.long 0x00 "MMPUSA19,Group A Region 19 Start Address Register"
|
|
group.long (0x200+0x144)++0x03
|
|
line.long 0x00 "MMPUSA20,Group A Region 20 Start Address Register"
|
|
group.long (0x200+0x154)++0x03
|
|
line.long 0x00 "MMPUSA21,Group A Region 21 Start Address Register"
|
|
group.long (0x200+0x164)++0x03
|
|
line.long 0x00 "MMPUSA22,Group A Region 22 Start Address Register"
|
|
group.long (0x200+0x174)++0x03
|
|
line.long 0x00 "MMPUSA23,Group A Region 23 Start Address Register"
|
|
group.long (0x200+0x184)++0x03
|
|
line.long 0x00 "MMPUSA24,Group A Region 24 Start Address Register"
|
|
group.long (0x200+0x194)++0x03
|
|
line.long 0x00 "MMPUSA25,Group A Region 25 Start Address Register"
|
|
group.long (0x200+0x1A4)++0x03
|
|
line.long 0x00 "MMPUSA26,Group A Region 26 Start Address Register"
|
|
group.long (0x200+0x1B4)++0x03
|
|
line.long 0x00 "MMPUSA27,Group A Region 27 Start Address Register"
|
|
group.long (0x200+0x1C4)++0x03
|
|
line.long 0x00 "MMPUSA28,Group A Region 28 Start Address Register"
|
|
group.long (0x200+0x1D4)++0x03
|
|
line.long 0x00 "MMPUSA29,Group A Region 29 Start Address Register"
|
|
group.long (0x200+0x1E4)++0x03
|
|
line.long 0x00 "MMPUSA30,Group A Region 30 Start Address Register"
|
|
group.long (0x200+0x8)++0x03
|
|
line.long 0x00 "MMPUEA0,Group A Region 0 End Address Register"
|
|
group.long (0x200+0x18)++0x03
|
|
line.long 0x00 "MMPUEA1,Group A Region 1 End Address Register"
|
|
group.long (0x200+0x28)++0x03
|
|
line.long 0x00 "MMPUEA2,Group A Region 2 End Address Register"
|
|
group.long (0x200+0x38)++0x03
|
|
line.long 0x00 "MMPUEA3,Group A Region 3 End Address Register"
|
|
group.long (0x200+0x48)++0x03
|
|
line.long 0x00 "MMPUEA4,Group A Region 4 End Address Register"
|
|
group.long (0x200+0x58)++0x03
|
|
line.long 0x00 "MMPUEA5,Group A Region 5 End Address Register"
|
|
group.long (0x200+0x68)++0x03
|
|
line.long 0x00 "MMPUEA6,Group A Region 6 End Address Register"
|
|
group.long (0x200+0x78)++0x03
|
|
line.long 0x00 "MMPUEA7,Group A Region 7 End Address Register"
|
|
group.long (0x200+0x88)++0x03
|
|
line.long 0x00 "MMPUEA8,Group A Region 8 End Address Register"
|
|
group.long (0x200+0x98)++0x03
|
|
line.long 0x00 "MMPUEA9,Group A Region 9 End Address Register"
|
|
group.long (0x200+0xA8)++0x03
|
|
line.long 0x00 "MMPUEA10,Group A Region 10 End Address Register"
|
|
group.long (0x200+0xB8)++0x03
|
|
line.long 0x00 "MMPUEA11,Group A Region 11 End Address Register"
|
|
group.long (0x200+0xC8)++0x03
|
|
line.long 0x00 "MMPUEA12,Group A Region 12 End Address Register"
|
|
group.long (0x200+0xD8)++0x03
|
|
line.long 0x00 "MMPUEA13,Group A Region 13 End Address Register"
|
|
group.long (0x200+0xE8)++0x03
|
|
line.long 0x00 "MMPUEA14,Group A Region 14 End Address Register"
|
|
group.long (0x200+0xF8)++0x03
|
|
line.long 0x00 "MMPUEA15,Group A Region 15 End Address Register"
|
|
group.long (0x200+0x108)++0x03
|
|
line.long 0x00 "MMPUEA16,Group A Region 16 End Address Register"
|
|
group.long (0x200+0x118)++0x03
|
|
line.long 0x00 "MMPUEA17,Group A Region 17 End Address Register"
|
|
group.long (0x200+0x128)++0x03
|
|
line.long 0x00 "MMPUEA18,Group A Region 18 End Address Register"
|
|
group.long (0x200+0x138)++0x03
|
|
line.long 0x00 "MMPUEA19,Group A Region 19 End Address Register"
|
|
group.long (0x200+0x148)++0x03
|
|
line.long 0x00 "MMPUEA20,Group A Region 20 End Address Register"
|
|
group.long (0x200+0x158)++0x03
|
|
line.long 0x00 "MMPUEA21,Group A Region 21 End Address Register"
|
|
group.long (0x200+0x168)++0x03
|
|
line.long 0x00 "MMPUEA22,Group A Region 22 End Address Register"
|
|
group.long (0x200+0x178)++0x03
|
|
line.long 0x00 "MMPUEA23,Group A Region 23 End Address Register"
|
|
group.long (0x200+0x188)++0x03
|
|
line.long 0x00 "MMPUEA24,Group A Region 24 End Address Register"
|
|
group.long (0x200+0x198)++0x03
|
|
line.long 0x00 "MMPUEA25,Group A Region 25 End Address Register"
|
|
group.long (0x200+0x1A8)++0x03
|
|
line.long 0x00 "MMPUEA26,Group A Region 26 End Address Register"
|
|
group.long (0x200+0x1B8)++0x03
|
|
line.long 0x00 "MMPUEA27,Group A Region 27 End Address Register"
|
|
group.long (0x200+0x1C8)++0x03
|
|
line.long 0x00 "MMPUEA28,Group A Region 28 End Address Register"
|
|
group.long (0x200+0x1D8)++0x03
|
|
line.long 0x00 "MMPUEA29,Group A Region 29 End Address Register"
|
|
group.long (0x200+0x1E8)++0x03
|
|
line.long 0x00 "MMPUEA30,Group A Region 30 End Address Register"
|
|
group.long (0x200+0x0)++0x03
|
|
line.long 0x00 "MMPUACA0,Group A Region 0 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x10)++0x03
|
|
line.long 0x00 "MMPUACA1,Group A Region 1 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x20)++0x03
|
|
line.long 0x00 "MMPUACA2,Group A Region 2 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x30)++0x03
|
|
line.long 0x00 "MMPUACA3,Group A Region 3 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x40)++0x03
|
|
line.long 0x00 "MMPUACA4,Group A Region 4 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x50)++0x03
|
|
line.long 0x00 "MMPUACA5,Group A Region 5 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x60)++0x03
|
|
line.long 0x00 "MMPUACA6,Group A Region 6 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x70)++0x03
|
|
line.long 0x00 "MMPUACA7,Group A Region 7 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x80)++0x03
|
|
line.long 0x00 "MMPUACA8,Group A Region 8 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x90)++0x03
|
|
line.long 0x00 "MMPUACA9,Group A Region 9 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0xA0)++0x03
|
|
line.long 0x00 "MMPUACA10,Group A Region 10 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0xB0)++0x03
|
|
line.long 0x00 "MMPUACA11,Group A Region 11 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0xC0)++0x03
|
|
line.long 0x00 "MMPUACA12,Group A Region 12 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0xD0)++0x03
|
|
line.long 0x00 "MMPUACA13,Group A Region 13 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0xE0)++0x03
|
|
line.long 0x00 "MMPUACA14,Group A Region 14 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0xF0)++0x03
|
|
line.long 0x00 "MMPUACA15,Group A Region 15 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x100)++0x03
|
|
line.long 0x00 "MMPUACA16,Group A Region 16 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x110)++0x03
|
|
line.long 0x00 "MMPUACA17,Group A Region 17 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x120)++0x03
|
|
line.long 0x00 "MMPUACA18,Group A Region 18 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x130)++0x03
|
|
line.long 0x00 "MMPUACA19,Group A Region 19 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x140)++0x03
|
|
line.long 0x00 "MMPUACA20,Group A Region 20 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x150)++0x03
|
|
line.long 0x00 "MMPUACA21,Group A Region 21 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x160)++0x03
|
|
line.long 0x00 "MMPUACA22,Group A Region 22 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x170)++0x03
|
|
line.long 0x00 "MMPUACA23,Group A Region 23 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x180)++0x03
|
|
line.long 0x00 "MMPUACA24,Group A Region 24 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x190)++0x03
|
|
line.long 0x00 "MMPUACA25,Group A Region 25 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x1A0)++0x03
|
|
line.long 0x00 "MMPUACA26,Group A Region 26 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x1B0)++0x03
|
|
line.long 0x00 "MMPUACA27,Group A Region 27 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x1C0)++0x03
|
|
line.long 0x00 "MMPUACA28,Group A Region 28 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x1D0)++0x03
|
|
line.long 0x00 "MMPUACA29,Group A Region 29 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x1E0)++0x03
|
|
line.long 0x00 "MMPUACA30,Group A Region 30 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "MMPUCTLA,Bus Master MPU Control Register"
|
|
hexmask.word.BYTE 0x00 8.--15. 1. " KEY ,Key code"
|
|
bitfld.word 0x00 1. " OAD ,Operation after detection" "Interrupt,Reset"
|
|
bitfld.word 0x00 0. " ENABLE ,Master group enable" "Disabled,Enabled"
|
|
group.word 0x102++0x01
|
|
line.word 0x00 "MMPUPTA,Group A Protection of Register"
|
|
hexmask.word.BYTE 0x00 8.--15. 1. " KEY ,Key code"
|
|
bitfld.word 0x00 0. " PROTECT ,Protection of register" "Not protected,Protected"
|
|
group.long (0x600+0x4)++0x03
|
|
line.long 0x00 "MMPUSB0,Group B Region 0 Start Address Register"
|
|
group.long (0x600+0x14)++0x03
|
|
line.long 0x00 "MMPUSB1,Group B Region 1 Start Address Register"
|
|
group.long (0x600+0x24)++0x03
|
|
line.long 0x00 "MMPUSB2,Group B Region 2 Start Address Register"
|
|
group.long (0x600+0x34)++0x03
|
|
line.long 0x00 "MMPUSB3,Group B Region 3 Start Address Register"
|
|
group.long (0x600+0x44)++0x03
|
|
line.long 0x00 "MMPUSB4,Group B Region 4 Start Address Register"
|
|
group.long (0x600+0x54)++0x03
|
|
line.long 0x00 "MMPUSB5,Group B Region 5 Start Address Register"
|
|
group.long (0x600+0x64)++0x03
|
|
line.long 0x00 "MMPUSB6,Group B Region 6 Start Address Register"
|
|
group.long (0x600+0x74)++0x03
|
|
line.long 0x00 "MMPUSB7,Group B Region 7 Start Address Register"
|
|
group.long (0x600+0x8)++0x03
|
|
line.long 0x00 "MMPUEB0,Group B Region 0 End Address Register"
|
|
group.long (0x600+0x18)++0x03
|
|
line.long 0x00 "MMPUEB1,Group B Region 1 End Address Register"
|
|
group.long (0x600+0x28)++0x03
|
|
line.long 0x00 "MMPUEB2,Group B Region 2 End Address Register"
|
|
group.long (0x600+0x38)++0x03
|
|
line.long 0x00 "MMPUEB3,Group B Region 3 End Address Register"
|
|
group.long (0x600+0x48)++0x03
|
|
line.long 0x00 "MMPUEB4,Group B Region 4 End Address Register"
|
|
group.long (0x600+0x58)++0x03
|
|
line.long 0x00 "MMPUEB5,Group B Region 5 End Address Register"
|
|
group.long (0x600+0x68)++0x03
|
|
line.long 0x00 "MMPUEB6,Group B Region 6 End Address Register"
|
|
group.long (0x600+0x78)++0x03
|
|
line.long 0x00 "MMPUEB7,Group B Region 7 End Address Register"
|
|
group.long (0x600+0x0)++0x03
|
|
line.long 0x00 "MMPUACB0,Group B Region 0 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x600+0x10)++0x03
|
|
line.long 0x00 "MMPUACB1,Group B Region 1 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x600+0x20)++0x03
|
|
line.long 0x00 "MMPUACB2,Group B Region 2 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x600+0x30)++0x03
|
|
line.long 0x00 "MMPUACB3,Group B Region 3 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x600+0x40)++0x03
|
|
line.long 0x00 "MMPUACB4,Group B Region 4 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x600+0x50)++0x03
|
|
line.long 0x00 "MMPUACB5,Group B Region 5 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x600+0x60)++0x03
|
|
line.long 0x00 "MMPUACB6,Group B Region 6 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x600+0x70)++0x03
|
|
line.long 0x00 "MMPUACB7,Group B Region 7 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.word 0x400++0x01
|
|
line.word 0x00 "MMPUCTLB,Bus Master MPU Control Register"
|
|
hexmask.word.BYTE 0x00 8.--15. 1. " KEY ,Key code"
|
|
bitfld.word 0x00 1. " OAD ,Operation after detection" "Interrupt,Reset"
|
|
bitfld.word 0x00 0. " ENABLE ,Master group enable" "Disabled,Enabled"
|
|
group.word 0x502++0x01
|
|
line.word 0x00 "MMPUPTB,Group B Protection of Register"
|
|
hexmask.word.BYTE 0x00 8.--15. 1. " KEY ,Key code"
|
|
bitfld.word 0x00 0. " PROTECT ,Protection of register" "Not protected,Protected"
|
|
sif !cpuis("R7FS5D5*")
|
|
group.long (0xA00+0x4)++0x03
|
|
line.long 0x00 "MMPUSC0,Group C Region 0 Start Address Register"
|
|
group.long (0xA00+0x14)++0x03
|
|
line.long 0x00 "MMPUSC1,Group C Region 1 Start Address Register"
|
|
group.long (0xA00+0x24)++0x03
|
|
line.long 0x00 "MMPUSC2,Group C Region 2 Start Address Register"
|
|
group.long (0xA00+0x34)++0x03
|
|
line.long 0x00 "MMPUSC3,Group C Region 3 Start Address Register"
|
|
group.long (0xA00+0x44)++0x03
|
|
line.long 0x00 "MMPUSC4,Group C Region 4 Start Address Register"
|
|
group.long (0xA00+0x54)++0x03
|
|
line.long 0x00 "MMPUSC5,Group C Region 5 Start Address Register"
|
|
group.long (0xA00+0x64)++0x03
|
|
line.long 0x00 "MMPUSC6,Group C Region 6 Start Address Register"
|
|
group.long (0xA00+0x74)++0x03
|
|
line.long 0x00 "MMPUSC7,Group C Region 7 Start Address Register"
|
|
group.long (0xA00+0x8)++0x03
|
|
line.long 0x00 "MMPUEC0,Group C Region 0 End Address Register"
|
|
group.long (0xA00+0x18)++0x03
|
|
line.long 0x00 "MMPUEC1,Group C Region 1 End Address Register"
|
|
group.long (0xA00+0x28)++0x03
|
|
line.long 0x00 "MMPUEC2,Group C Region 2 End Address Register"
|
|
group.long (0xA00+0x38)++0x03
|
|
line.long 0x00 "MMPUEC3,Group C Region 3 End Address Register"
|
|
group.long (0xA00+0x48)++0x03
|
|
line.long 0x00 "MMPUEC4,Group C Region 4 End Address Register"
|
|
group.long (0xA00+0x58)++0x03
|
|
line.long 0x00 "MMPUEC5,Group C Region 5 End Address Register"
|
|
group.long (0xA00+0x68)++0x03
|
|
line.long 0x00 "MMPUEC6,Group C Region 6 End Address Register"
|
|
group.long (0xA00+0x78)++0x03
|
|
line.long 0x00 "MMPUEC7,Group C Region 7 End Address Register"
|
|
group.long (0xA00+0x0)++0x03
|
|
line.long 0x00 "MMPUACC0,Group C Region 0 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0xA00+0x10)++0x03
|
|
line.long 0x00 "MMPUACC1,Group C Region 1 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0xA00+0x20)++0x03
|
|
line.long 0x00 "MMPUACC2,Group C Region 2 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0xA00+0x30)++0x03
|
|
line.long 0x00 "MMPUACC3,Group C Region 3 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0xA00+0x40)++0x03
|
|
line.long 0x00 "MMPUACC4,Group C Region 4 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0xA00+0x50)++0x03
|
|
line.long 0x00 "MMPUACC5,Group C Region 5 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0xA00+0x60)++0x03
|
|
line.long 0x00 "MMPUACC6,Group C Region 6 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0xA00+0x70)++0x03
|
|
line.long 0x00 "MMPUACC7,Group C Region 7 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.word 0x800++0x01
|
|
line.word 0x00 "MMPUCTLC,Bus Master MPU Control Register"
|
|
hexmask.word.BYTE 0x00 8.--15. 1. " KEY ,Key code"
|
|
bitfld.word 0x00 1. " OAD ,Operation after detection" "Interrupt,Reset"
|
|
bitfld.word 0x00 0. " ENABLE ,Master group enable" "Disabled,Enabled"
|
|
group.word 0x902++0x01
|
|
line.word 0x00 "MMPUPTC,Group C Protection of Register"
|
|
hexmask.word.BYTE 0x00 8.--15. 1. " KEY ,Key code"
|
|
bitfld.word 0x00 0. " PROTECT ,Protection of register" "Not protected,Protected"
|
|
endif
|
|
else
|
|
group.long (0x200+0x4)++0x03
|
|
line.long 0x00 "MMPUSA0,Group A Region 0 Start Address Register"
|
|
group.long (0x200+0x14)++0x03
|
|
line.long 0x00 "MMPUSA1,Group A Region 1 Start Address Register"
|
|
group.long (0x200+0x24)++0x03
|
|
line.long 0x00 "MMPUSA2,Group A Region 2 Start Address Register"
|
|
group.long (0x200+0x34)++0x03
|
|
line.long 0x00 "MMPUSA3,Group A Region 3 Start Address Register"
|
|
group.long (0x200+0x44)++0x03
|
|
line.long 0x00 "MMPUSA4,Group A Region 4 Start Address Register"
|
|
group.long (0x200+0x54)++0x03
|
|
line.long 0x00 "MMPUSA5,Group A Region 5 Start Address Register"
|
|
group.long (0x200+0x64)++0x03
|
|
line.long 0x00 "MMPUSA6,Group A Region 6 Start Address Register"
|
|
group.long (0x200+0x74)++0x03
|
|
line.long 0x00 "MMPUSA7,Group A Region 7 Start Address Register"
|
|
group.long (0x200+0x84)++0x03
|
|
line.long 0x00 "MMPUSA8,Group A Region 8 Start Address Register"
|
|
group.long (0x200+0x94)++0x03
|
|
line.long 0x00 "MMPUSA9,Group A Region 9 Start Address Register"
|
|
group.long (0x200+0xA4)++0x03
|
|
line.long 0x00 "MMPUSA10,Group A Region 10 Start Address Register"
|
|
group.long (0x200+0xB4)++0x03
|
|
line.long 0x00 "MMPUSA11,Group A Region 11 Start Address Register"
|
|
group.long (0x200+0xC4)++0x03
|
|
line.long 0x00 "MMPUSA12,Group A Region 12 Start Address Register"
|
|
group.long (0x200+0xD4)++0x03
|
|
line.long 0x00 "MMPUSA13,Group A Region 13 Start Address Register"
|
|
group.long (0x200+0xE4)++0x03
|
|
line.long 0x00 "MMPUSA14,Group A Region 14 Start Address Register"
|
|
group.long (0x200+0xF4)++0x03
|
|
line.long 0x00 "MMPUSA15,Group A Region 15 Start Address Register"
|
|
group.long (0x200+0x8)++0x03
|
|
line.long 0x00 "MMPUEA0,Group A Region 0 End Address Register"
|
|
group.long (0x200+0x18)++0x03
|
|
line.long 0x00 "MMPUEA1,Group A Region 1 End Address Register"
|
|
group.long (0x200+0x28)++0x03
|
|
line.long 0x00 "MMPUEA2,Group A Region 2 End Address Register"
|
|
group.long (0x200+0x38)++0x03
|
|
line.long 0x00 "MMPUEA3,Group A Region 3 End Address Register"
|
|
group.long (0x200+0x48)++0x03
|
|
line.long 0x00 "MMPUEA4,Group A Region 4 End Address Register"
|
|
group.long (0x200+0x58)++0x03
|
|
line.long 0x00 "MMPUEA5,Group A Region 5 End Address Register"
|
|
group.long (0x200+0x68)++0x03
|
|
line.long 0x00 "MMPUEA6,Group A Region 6 End Address Register"
|
|
group.long (0x200+0x78)++0x03
|
|
line.long 0x00 "MMPUEA7,Group A Region 7 End Address Register"
|
|
group.long (0x200+0x88)++0x03
|
|
line.long 0x00 "MMPUEA8,Group A Region 8 End Address Register"
|
|
group.long (0x200+0x98)++0x03
|
|
line.long 0x00 "MMPUEA9,Group A Region 9 End Address Register"
|
|
group.long (0x200+0xA8)++0x03
|
|
line.long 0x00 "MMPUEA10,Group A Region 10 End Address Register"
|
|
group.long (0x200+0xB8)++0x03
|
|
line.long 0x00 "MMPUEA11,Group A Region 11 End Address Register"
|
|
group.long (0x200+0xC8)++0x03
|
|
line.long 0x00 "MMPUEA12,Group A Region 12 End Address Register"
|
|
group.long (0x200+0xD8)++0x03
|
|
line.long 0x00 "MMPUEA13,Group A Region 13 End Address Register"
|
|
group.long (0x200+0xE8)++0x03
|
|
line.long 0x00 "MMPUEA14,Group A Region 14 End Address Register"
|
|
group.long (0x200+0xF8)++0x03
|
|
line.long 0x00 "MMPUEA15,Group A Region 15 End Address Register"
|
|
group.long (0x200+0x0)++0x03
|
|
line.long 0x00 "MMPUACA0,Group A Region 0 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x10)++0x03
|
|
line.long 0x00 "MMPUACA1,Group A Region 1 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x20)++0x03
|
|
line.long 0x00 "MMPUACA2,Group A Region 2 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x30)++0x03
|
|
line.long 0x00 "MMPUACA3,Group A Region 3 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x40)++0x03
|
|
line.long 0x00 "MMPUACA4,Group A Region 4 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x50)++0x03
|
|
line.long 0x00 "MMPUACA5,Group A Region 5 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x60)++0x03
|
|
line.long 0x00 "MMPUACA6,Group A Region 6 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x70)++0x03
|
|
line.long 0x00 "MMPUACA7,Group A Region 7 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x80)++0x03
|
|
line.long 0x00 "MMPUACA8,Group A Region 8 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0x90)++0x03
|
|
line.long 0x00 "MMPUACA9,Group A Region 9 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0xA0)++0x03
|
|
line.long 0x00 "MMPUACA10,Group A Region 10 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0xB0)++0x03
|
|
line.long 0x00 "MMPUACA11,Group A Region 11 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0xC0)++0x03
|
|
line.long 0x00 "MMPUACA12,Group A Region 12 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0xD0)++0x03
|
|
line.long 0x00 "MMPUACA13,Group A Region 13 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0xE0)++0x03
|
|
line.long 0x00 "MMPUACA14,Group A Region 14 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.long (0x200+0xF0)++0x03
|
|
line.long 0x00 "MMPUACA15,Group A Region 15 access control register"
|
|
bitfld.long 0x00 2. " WP ,Write protection" "Not protected,Protected"
|
|
bitfld.long 0x00 1. " RP ,Read protection" "Not protected,Protected"
|
|
bitfld.long 0x00 0. " ENABLE ,Region enable" "Disabled,Enabled"
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "MMPUCTLA,Bus Master MPU Control Register"
|
|
hexmask.word.BYTE 0x00 8.--15. 1. " KEY ,Key code"
|
|
bitfld.word 0x00 1. " OAD ,Operation after detection" "Interrupt,Reset"
|
|
bitfld.word 0x00 0. " ENABLE ,Master group enable" "Disabled,Enabled"
|
|
group.word 0x102++0x01
|
|
line.word 0x00 "MMPUPTA,Group A Protection of Register"
|
|
hexmask.word.BYTE 0x00 8.--15. 1. " KEY ,Key code"
|
|
bitfld.word 0x00 0. " PROTECT ,Protection of register" "Not protected,Protected"
|
|
endif
|
|
tree.end
|
|
tree "Bus Slave MPU"
|
|
group.word 0xC10++0x01
|
|
line.word 0x00 "SMPUMBIU,Access Control Register for Memory bus 3"
|
|
sif cpuis("R7FS5*")
|
|
bitfld.word 0x00 15. " WPSRAMHS ,SRAMHS write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RPSRAMHS ,SRAMHS read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " WPFLI ,Code flash memory write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " RPFLI ,Code flash memory read protection" "No effect,Enabled"
|
|
newline
|
|
sif !cpuis("R7FS5D5*")
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b read protection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
group.word 0xC14++0x01
|
|
line.word 0x00 "SMPUFBIU,Access Control Register for Internal peripheral bus 9"
|
|
sif cpuis("R7FS5*")
|
|
sif !cpuis("R7FS5D5*")
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "No effect,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "No effect,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b ReadProtection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WPCPU ,CPU write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RPCPU ,CPU read protection" "Disabled,Enabled"
|
|
group.word 0xC18++0x01
|
|
line.word 0x00 "SMPUSRAM0,Access Control Register for Memory bus 4"
|
|
sif cpuis("R7FS5*")
|
|
sif !cpuis("R7FS5D5*")
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b ReadProtection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WPCPU ,CPU write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RPCPU ,CPU read protection" "Disabled,Enabled"
|
|
group.word 0xC1C++0x01
|
|
line.word 0x00 "SMPUSRAM1,Access Control Register for Memory bus 5"
|
|
sif cpuis("R7FS5*")
|
|
sif !cpuis("R7FS5D5*")
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b ReadProtection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WPCPU ,CPU write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RPCPU ,CPU read protection" "Disabled,Enabled"
|
|
group.word 0xC20++0x01
|
|
line.word 0x00 "SMPUP0BIU,Access Control Register for Internal peripheral bus 1"
|
|
sif cpuis("R7FS5*")
|
|
sif !cpuis("R7FS5D5*")
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "No effect,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "No effect,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "No effect,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b ReadProtection" "No effect,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WPCPU ,CPU write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RPCPU ,CPU read protection" "Disabled,Enabled"
|
|
group.word 0xC24++0x01
|
|
line.word 0x00 "SMPUP3BIU,Access Control Register for Internal peripheral bus 3"
|
|
sif cpuis("R7FS5*")
|
|
sif !cpuis("R7FS5D5*")
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "No effect,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "No effect,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "No effect,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b ReadProtection" "No effect,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WPCPU ,CPU write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RPCPU ,CPU read protection" "Disabled,Enabled"
|
|
group.word 0xC28++0x01
|
|
line.word 0x00 "SMPUP7BIU,Access Control Register for Internal peripheral bus 7"
|
|
sif cpuis("R7FS5*")
|
|
sif !cpuis("R7FS5D5*")
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "No effect,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "No effect,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "No effect,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b ReadProtection" "No effect,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WPCPU ,CPU write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RPCPU ,CPU read protection" "Disabled,Enabled"
|
|
sif cpuis("R7FS5D9*")
|
|
group.word 0xC2C++0x01
|
|
line.word 0x00 "SMPUP8BIU,Access Control Register for Internal peripheral bus 8"
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "No effect,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "No effect,Enabled"
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "No effect,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b ReadProtection" "No effect,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WPCPU ,CPU write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RPCPU ,CPU read protection" "Disabled,Enabled"
|
|
endif
|
|
group.word 0xC30++0x01
|
|
line.word 0x00 "SMPUEXBIU,Access Control Register for CS area"
|
|
sif cpuis("R7FS5D9*")
|
|
sif !cpuis("R7FS5D5*")
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b ReadProtection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WPCPU ,CPU write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RPCPU ,CPU read protection" "Disabled,Enabled"
|
|
group.word 0xC34++0x01
|
|
line.word 0x00 "SMPUEXBIU2,Access Control Register for QSPI area"
|
|
sif cpuis("R7FS5D9*")
|
|
sif !cpuis("R7FS5D5*")
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b ReadProtection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WPCPU ,CPU write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RPCPU ,CPU read protection" "Disabled,Enabled"
|
|
group.word 0xC00++0x01
|
|
line.word 0x00 "SMPUCTL,Slave MPU Control Register"
|
|
hexmask.word.BYTE 0x00 8.--15. 1. " KEY ,Key code"
|
|
bitfld.word 0x00 1. " PROTECT ,Protection of register" "Not protected,Protected"
|
|
bitfld.word 0x00 0. " OAD ,Operation after detection" "Interrupt,Reset"
|
|
tree.end
|
|
tree "Security MPU"
|
|
sif cpuis("R7FS5*")
|
|
rgroup.long (ad:0x00000400+0x8)++0x03
|
|
line.long 0x00 "SECMPUPCS0,Security MPU Program Counter Start Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " SECMPUPCS0 ,Region start address"
|
|
rgroup.long (ad:0x00000400+0x10)++0x03
|
|
line.long 0x00 "SECMPUPCS1,Security MPU Program Counter Start Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " SECMPUPCS1 ,Region start address"
|
|
rgroup.long (ad:0x00000400+0xC)++0x03
|
|
line.long 0x00 "SECMPUPCE0,Security MPU Program Counter End Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " SECMPUPCE0 ,Region end address"
|
|
rgroup.long (ad:0x00000400+0x14)++0x03
|
|
line.long 0x00 "SECMPUPCE1,Security MPU Program Counter End Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " SECMPUPCE1 ,Region end address"
|
|
rgroup.long (ad:0x00000400+0x18)++0x23
|
|
line.long 0x00 "SECMPUS0,Security MPU Region 0 Start Address Register"
|
|
hexmask.long.tbyte 0x00 2.--23. 0x04 " SECMPUS0 ,Region start address register"
|
|
line.long 0x04 "SECMPUE0,Security MPU Region 0 End Address Register"
|
|
hexmask.long.tbyte 0x04 2.--23. 0x04 " SECMPUE0 ,Region end address register"
|
|
line.long 0x08 "SECMPUS1,Security MPU Region 1 Start Address Register"
|
|
hexmask.long.tbyte 0x08 2.--23. 0x04 " SECMPUS1 ,Region start address register"
|
|
line.long 0x0C "SECMPUE1,Security MPU Region 1 End Address Register"
|
|
hexmask.long.tbyte 0x0C 2.--23. 0x04 " SECMPUE1 ,Region end address register"
|
|
line.long 0x10 "SECMPUS2,Security MPU Region 2 Start Address Register"
|
|
hexmask.long.tbyte 0x10 2.--23. 0x04 " SECMPUS2 ,Region start address register"
|
|
line.long 0x14 "SECMPUE2,Security MPU Region 2 End Address Register"
|
|
hexmask.long.tbyte 0x14 2.--23. 0x04 " SECMPUE2 ,Region end address register"
|
|
line.long 0x18 "SECMPUS3,Security MPU Region 3 Start Address Register"
|
|
hexmask.long.tbyte 0x18 2.--23. 0x04 " SECMPUS3 ,Region start address register"
|
|
line.long 0x1C "SECMPUE3,Security MPU Region 3 End Address Register"
|
|
hexmask.long.tbyte 0x1C 2.--23. 0x04 " SECMPUE3 ,Region end address register"
|
|
rgroup.word (ad:0x00000400+0x38)++0x01
|
|
line.word 0x00 "SECMPUAC,Security MPU Access Control Register"
|
|
bitfld.word 0x00 9. " DISPC1 ,PC region 1 disable" "No,Yes"
|
|
bitfld.word 0x00 8. " DISPC0 ,PC region 0 disable" "No,Yes"
|
|
bitfld.word 0x00 3. " DIS3 ,Region 3 disable" "No,Yes"
|
|
bitfld.word 0x00 2. " DIS2 ,Region 2 disable" "No,Yes"
|
|
newline
|
|
bitfld.word 0x00 1. " DIS1 ,Region 1 disable" "No,Yes"
|
|
bitfld.word 0x00 0. " DIS0 ,Region 0 disable" "No,Yes"
|
|
else
|
|
rgroup.long (ad:0x00000400+0x8)++0x03
|
|
line.long 0x00 "SECMPUPCS0,Security MPU Program Counter Start Address Register"
|
|
rgroup.long (ad:0x00000400+0x10)++0x03
|
|
line.long 0x00 "SECMPUPCS1,Security MPU Program Counter Start Address Register"
|
|
rgroup.long (ad:0x00000400+0xC)++0x03
|
|
line.long 0x00 "SECMPUPCE0,Security MPU Program Counter End Address Register"
|
|
rgroup.long (ad:0x00000400+0x14)++0x03
|
|
line.long 0x00 "SECMPUPCE1,Security MPU Program Counter End Address Register"
|
|
rgroup.long (ad:0x00000400+0x18)++0x07
|
|
line.long 0x00 "SECMPUS0,Security MPU Region 0 Start Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 0x01 " SECMPUS0 ,Region start address register"
|
|
line.long 0x04 "SECMPUE0,Security MPU Region 0 End Address Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 0x01 " SECMPUE0 ,Region end address register"
|
|
rgroup.word (ad:0x00000400+0x38)++0x01
|
|
line.word 0x00 "SECMPUAC,Security MPU Access Control Register"
|
|
bitfld.word 0x00 9. " DISPC1 ,PC region 1 disable" "No,Yes"
|
|
bitfld.word 0x00 8. " DISPC0 ,PC region 0 disable" "No,Yes"
|
|
bitfld.word 0x00 0. " DIS0 ,Region 0 disable" "No,Yes"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMAC (DMA Controller)"
|
|
tree "DMAC 0"
|
|
base ad:0x40005000
|
|
width 8.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DMSAR0,DMA Source Address Register"
|
|
line.long 0x04 "DMDAR0,DMA Destination Address Register"
|
|
if (((per.w(ad:0x40005010))&0xC000)==0x0)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMCRA0,DMA Transfer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DMCRAL ,Lower bits of transfer count"
|
|
elif (((per.w(ad:0x40005010))&0xC000)==(0x4000||0x8000))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMCRA0,DMA Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " DMCRAH ,Upper bits of transfer count"
|
|
hexmask.long.word 0x00 0.--9. 1. " DMCRAL ,Lower bits of transfer count"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "DMCRB0,DMA Block Transfer Count Register"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "DMTMD0,DMA Transfer Mode Register"
|
|
bitfld.word 0x00 14.--15. " MD ,Transfer Mode Select" "Normal,Repeat,Block,"
|
|
bitfld.word 0x00 12.--13. " DTS ,Repeat Area Select" "Destination specified,Source specified,Not specified,"
|
|
bitfld.word 0x00 8.--9. " SZ ,Transfer Data Size Select" "8 bit,16 bit,32 bit,"
|
|
bitfld.word 0x00 0.--1. " DCTG ,Transfer Request Source Select" "Software,Interrupt,,"
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "DMINT0,DMA Interrupt Setting Register"
|
|
bitfld.byte 0x00 4. " DTIE ,Transfer End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " ESIE ,Transfer Escape End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RPTIE ,Repeat Size End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SARIE ,Source Address Extended Repeat Area Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " DARIE ,Destination Address Extended Repeat Area Overflow Interrupt Enable" "Disabled,Enabled"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "DMAMD0,DMA Address Mode Register"
|
|
bitfld.word 0x00 14.--15. " SM ,Source Address Update Mode" "Fixed,Offset addition,Incremented,Decremented"
|
|
bitfld.word 0x00 8.--12. " SARA ,Source Address Extended Repeat Area" "Not specified,2 bytes,4 bytes,8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,?..."
|
|
bitfld.word 0x00 6.--7. " DM ,Destination Address Update Mode" "Fixed,Offset addition,Incremented,Decremented"
|
|
bitfld.word 0x00 0.--4. " DARA ,Destination Address Extended Repeat Area" "Not specified,2 bytes,4 bytes,8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,?..."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DMOFR0,DMA Offset Register"
|
|
group.byte 0x1C++0x02
|
|
line.byte 0x00 "DMCNT0,DMA Transfer Enable Register"
|
|
bitfld.byte 0x00 0. " DTE ,DMA Transfer Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "DMREQ0,DMA Software Start Register"
|
|
bitfld.byte 0x01 4. " CLRS ,DMA Software Start Bit Auto Clear Select" "Cleared,Not cleared"
|
|
bitfld.byte 0x01 0. " SWREQ ,DMA Software Start" "Not requested,Requested"
|
|
line.byte 0x02 "DMSTS0,DMA Status Register"
|
|
bitfld.byte 0x02 7. " ACT ,DMA Active Flag" "Suspended,Not suspended"
|
|
bitfld.byte 0x02 4. " DTIF ,Transfer End Interrupt Flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x02 0. " ESIF ,Transfer Escape End Interrupt Flag" "No interrupt,Interrupt"
|
|
group.byte ad:0x40005200++0x00
|
|
line.byte 0x00 "DMAST,DMACA Module Activation Register"
|
|
bitfld.byte 0x00 0. " DMST ,DMAC Operation Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMAC 1"
|
|
base ad:0x40005040
|
|
width 8.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DMSAR1,DMA Source Address Register"
|
|
line.long 0x04 "DMDAR1,DMA Destination Address Register"
|
|
if (((per.w(ad:0x40005050))&0xC000)==0x0)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMCRA1,DMA Transfer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DMCRAL ,Lower bits of transfer count"
|
|
elif (((per.w(ad:0x40005050))&0xC000)==(0x4000||0x8000))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMCRA1,DMA Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " DMCRAH ,Upper bits of transfer count"
|
|
hexmask.long.word 0x00 0.--9. 1. " DMCRAL ,Lower bits of transfer count"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "DMCRB1,DMA Block Transfer Count Register"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "DMTMD1,DMA Transfer Mode Register"
|
|
bitfld.word 0x00 14.--15. " MD ,Transfer Mode Select" "Normal,Repeat,Block,"
|
|
bitfld.word 0x00 12.--13. " DTS ,Repeat Area Select" "Destination specified,Source specified,Not specified,"
|
|
bitfld.word 0x00 8.--9. " SZ ,Transfer Data Size Select" "8 bit,16 bit,32 bit,"
|
|
bitfld.word 0x00 0.--1. " DCTG ,Transfer Request Source Select" "Software,Interrupt,,"
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "DMINT1,DMA Interrupt Setting Register"
|
|
bitfld.byte 0x00 4. " DTIE ,Transfer End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " ESIE ,Transfer Escape End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RPTIE ,Repeat Size End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SARIE ,Source Address Extended Repeat Area Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " DARIE ,Destination Address Extended Repeat Area Overflow Interrupt Enable" "Disabled,Enabled"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "DMAMD1,DMA Address Mode Register"
|
|
bitfld.word 0x00 14.--15. " SM ,Source Address Update Mode" "Fixed,Offset addition,Incremented,Decremented"
|
|
bitfld.word 0x00 8.--12. " SARA ,Source Address Extended Repeat Area" "Not specified,2 bytes,4 bytes,8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,?..."
|
|
bitfld.word 0x00 6.--7. " DM ,Destination Address Update Mode" "Fixed,Offset addition,Incremented,Decremented"
|
|
bitfld.word 0x00 0.--4. " DARA ,Destination Address Extended Repeat Area" "Not specified,2 bytes,4 bytes,8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,?..."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DMOFR1,DMA Offset Register"
|
|
group.byte 0x1C++0x02
|
|
line.byte 0x00 "DMCNT1,DMA Transfer Enable Register"
|
|
bitfld.byte 0x00 0. " DTE ,DMA Transfer Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "DMREQ1,DMA Software Start Register"
|
|
bitfld.byte 0x01 4. " CLRS ,DMA Software Start Bit Auto Clear Select" "Cleared,Not cleared"
|
|
bitfld.byte 0x01 0. " SWREQ ,DMA Software Start" "Not requested,Requested"
|
|
line.byte 0x02 "DMSTS1,DMA Status Register"
|
|
bitfld.byte 0x02 7. " ACT ,DMA Active Flag" "Suspended,Not suspended"
|
|
bitfld.byte 0x02 4. " DTIF ,Transfer End Interrupt Flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x02 0. " ESIF ,Transfer Escape End Interrupt Flag" "No interrupt,Interrupt"
|
|
group.byte ad:0x40005200++0x00
|
|
line.byte 0x00 "DMAST,DMACA Module Activation Register"
|
|
bitfld.byte 0x00 0. " DMST ,DMAC Operation Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMAC 2"
|
|
base ad:0x40005080
|
|
width 8.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DMSAR2,DMA Source Address Register"
|
|
line.long 0x04 "DMDAR2,DMA Destination Address Register"
|
|
if (((per.w(ad:0x40005090))&0xC000)==0x0)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMCRA2,DMA Transfer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DMCRAL ,Lower bits of transfer count"
|
|
elif (((per.w(ad:0x40005090))&0xC000)==(0x4000||0x8000))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMCRA2,DMA Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " DMCRAH ,Upper bits of transfer count"
|
|
hexmask.long.word 0x00 0.--9. 1. " DMCRAL ,Lower bits of transfer count"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "DMCRB2,DMA Block Transfer Count Register"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "DMTMD2,DMA Transfer Mode Register"
|
|
bitfld.word 0x00 14.--15. " MD ,Transfer Mode Select" "Normal,Repeat,Block,"
|
|
bitfld.word 0x00 12.--13. " DTS ,Repeat Area Select" "Destination specified,Source specified,Not specified,"
|
|
bitfld.word 0x00 8.--9. " SZ ,Transfer Data Size Select" "8 bit,16 bit,32 bit,"
|
|
bitfld.word 0x00 0.--1. " DCTG ,Transfer Request Source Select" "Software,Interrupt,,"
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "DMINT2,DMA Interrupt Setting Register"
|
|
bitfld.byte 0x00 4. " DTIE ,Transfer End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " ESIE ,Transfer Escape End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RPTIE ,Repeat Size End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SARIE ,Source Address Extended Repeat Area Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " DARIE ,Destination Address Extended Repeat Area Overflow Interrupt Enable" "Disabled,Enabled"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "DMAMD2,DMA Address Mode Register"
|
|
bitfld.word 0x00 14.--15. " SM ,Source Address Update Mode" "Fixed,Offset addition,Incremented,Decremented"
|
|
bitfld.word 0x00 8.--12. " SARA ,Source Address Extended Repeat Area" "Not specified,2 bytes,4 bytes,8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,?..."
|
|
bitfld.word 0x00 6.--7. " DM ,Destination Address Update Mode" "Fixed,Offset addition,Incremented,Decremented"
|
|
bitfld.word 0x00 0.--4. " DARA ,Destination Address Extended Repeat Area" "Not specified,2 bytes,4 bytes,8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,?..."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DMOFR2,DMA Offset Register"
|
|
group.byte 0x1C++0x02
|
|
line.byte 0x00 "DMCNT2,DMA Transfer Enable Register"
|
|
bitfld.byte 0x00 0. " DTE ,DMA Transfer Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "DMREQ2,DMA Software Start Register"
|
|
bitfld.byte 0x01 4. " CLRS ,DMA Software Start Bit Auto Clear Select" "Cleared,Not cleared"
|
|
bitfld.byte 0x01 0. " SWREQ ,DMA Software Start" "Not requested,Requested"
|
|
line.byte 0x02 "DMSTS2,DMA Status Register"
|
|
bitfld.byte 0x02 7. " ACT ,DMA Active Flag" "Suspended,Not suspended"
|
|
bitfld.byte 0x02 4. " DTIF ,Transfer End Interrupt Flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x02 0. " ESIF ,Transfer Escape End Interrupt Flag" "No interrupt,Interrupt"
|
|
group.byte ad:0x40005200++0x00
|
|
line.byte 0x00 "DMAST,DMACA Module Activation Register"
|
|
bitfld.byte 0x00 0. " DMST ,DMAC Operation Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMAC 3"
|
|
base ad:0x400050C0
|
|
width 8.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DMSAR3,DMA Source Address Register"
|
|
line.long 0x04 "DMDAR3,DMA Destination Address Register"
|
|
if (((per.w(ad:0x400050D0))&0xC000)==0x0)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMCRA3,DMA Transfer Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DMCRAL ,Lower bits of transfer count"
|
|
elif (((per.w(ad:0x400050D0))&0xC000)==(0x4000||0x8000))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DMCRA3,DMA Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " DMCRAH ,Upper bits of transfer count"
|
|
hexmask.long.word 0x00 0.--9. 1. " DMCRAL ,Lower bits of transfer count"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "DMCRB3,DMA Block Transfer Count Register"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "DMTMD3,DMA Transfer Mode Register"
|
|
bitfld.word 0x00 14.--15. " MD ,Transfer Mode Select" "Normal,Repeat,Block,"
|
|
bitfld.word 0x00 12.--13. " DTS ,Repeat Area Select" "Destination specified,Source specified,Not specified,"
|
|
bitfld.word 0x00 8.--9. " SZ ,Transfer Data Size Select" "8 bit,16 bit,32 bit,"
|
|
bitfld.word 0x00 0.--1. " DCTG ,Transfer Request Source Select" "Software,Interrupt,,"
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "DMINT3,DMA Interrupt Setting Register"
|
|
bitfld.byte 0x00 4. " DTIE ,Transfer End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " ESIE ,Transfer Escape End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RPTIE ,Repeat Size End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SARIE ,Source Address Extended Repeat Area Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " DARIE ,Destination Address Extended Repeat Area Overflow Interrupt Enable" "Disabled,Enabled"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "DMAMD3,DMA Address Mode Register"
|
|
bitfld.word 0x00 14.--15. " SM ,Source Address Update Mode" "Fixed,Offset addition,Incremented,Decremented"
|
|
bitfld.word 0x00 8.--12. " SARA ,Source Address Extended Repeat Area" "Not specified,2 bytes,4 bytes,8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,?..."
|
|
bitfld.word 0x00 6.--7. " DM ,Destination Address Update Mode" "Fixed,Offset addition,Incremented,Decremented"
|
|
bitfld.word 0x00 0.--4. " DARA ,Destination Address Extended Repeat Area" "Not specified,2 bytes,4 bytes,8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1 KB,2 KB,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,?..."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DMOFR3,DMA Offset Register"
|
|
group.byte 0x1C++0x02
|
|
line.byte 0x00 "DMCNT3,DMA Transfer Enable Register"
|
|
bitfld.byte 0x00 0. " DTE ,DMA Transfer Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "DMREQ3,DMA Software Start Register"
|
|
bitfld.byte 0x01 4. " CLRS ,DMA Software Start Bit Auto Clear Select" "Cleared,Not cleared"
|
|
bitfld.byte 0x01 0. " SWREQ ,DMA Software Start" "Not requested,Requested"
|
|
line.byte 0x02 "DMSTS3,DMA Status Register"
|
|
bitfld.byte 0x02 7. " ACT ,DMA Active Flag" "Suspended,Not suspended"
|
|
bitfld.byte 0x02 4. " DTIF ,Transfer End Interrupt Flag" "No interrupt,Interrupt"
|
|
bitfld.byte 0x02 0. " ESIF ,Transfer Escape End Interrupt Flag" "No interrupt,Interrupt"
|
|
group.byte ad:0x40005200++0x00
|
|
line.byte 0x00 "DMAST,DMACA Module Activation Register"
|
|
bitfld.byte 0x00 0. " DMST ,DMAC Operation Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "DTC (Data Transfer Controller)"
|
|
base ad:0x40005400
|
|
width 8.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x0 "DTCCR,DTC Control Register"
|
|
bitfld.byte 0x0 4. " RRS ,DTC transfer information read skip enable" "Disabled,Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x0 "DTCVBR,DTC Vector Base Register"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x0 "DTCST,DTC Module Start Register"
|
|
bitfld.byte 0x0 0. " DTCST ,DTC module start register" "Stopped,Started"
|
|
rgroup.word 0x0E++0x01
|
|
line.word 0x0 "DTCSTS,DTC Status Register"
|
|
bitfld.word 0x0 15. " ACT ,DTC active flag" "Disabled,Enabled"
|
|
hexmask.word.byte 0x0 0.--7. 1. " VECN ,DTC-Activating vector number monitoring"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ELC (Event Link Controller)"
|
|
base ad:0x40041000
|
|
width 10.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x0 "ELCR,Event Link Controller Register"
|
|
bitfld.byte 0x0 7. " ELCON ,All event link enable" "Disabled,Enabled"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x0 "ELSEGR0,Event Link Software Event Generation Register 0"
|
|
bitfld.byte 0x0 7. " WI ,ELSEGR register write disable" "No,Yes"
|
|
bitfld.byte 0x0 6. " WE ,SEG bit write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " SEG ,Software event generation" "Normal operation,Software event"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x0 "ELSEGR1,Event Link Software Event Generation Register 1"
|
|
bitfld.byte 0x0 7. " WI ,ELSEGR register write disable" "No,Yes"
|
|
bitfld.byte 0x0 6. " WE ,SEG bit write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 0. " SEG ,Software Event Generation" "Normal operation,Software event"
|
|
group.word (0x10)++0x01
|
|
line.word 0x0 "ELSR0,Event Link Setting Register 0"
|
|
hexmask.word 0x0 0.--8. 1. " ELS ,Event link select"
|
|
group.word (0x14)++0x01
|
|
line.word 0x0 "ELSR1,Event Link Setting Register 1"
|
|
hexmask.word 0x0 0.--8. 1. " ELS ,Event link select"
|
|
group.word (0x18)++0x01
|
|
line.word 0x0 "ELSR2,Event Link Setting Register 2"
|
|
hexmask.word 0x0 0.--8. 1. " ELS ,Event link select"
|
|
group.word (0x1C)++0x01
|
|
line.word 0x0 "ELSR3,Event Link Setting Register 3"
|
|
hexmask.word 0x0 0.--8. 1. " ELS ,Event link select"
|
|
group.word (0x20)++0x01
|
|
line.word 0x0 "ELSR4,Event Link Setting Register 4"
|
|
hexmask.word 0x0 0.--8. 1. " ELS ,Event link select"
|
|
group.word (0x24)++0x01
|
|
line.word 0x0 "ELSR5,Event Link Setting Register 5"
|
|
hexmask.word 0x0 0.--8. 1. " ELS ,Event link select"
|
|
group.word (0x28)++0x01
|
|
line.word 0x0 "ELSR6,Event Link Setting Register 6"
|
|
hexmask.word 0x0 0.--8. 1. " ELS ,Event link select"
|
|
group.word (0x2C)++0x01
|
|
line.word 0x0 "ELSR7,Event Link Setting Register 7"
|
|
hexmask.word 0x0 0.--8. 1. " ELS ,Event link select"
|
|
group.word (0x30)++0x01
|
|
line.word 0x0 "ELSR8,Event Link Setting Register 8"
|
|
hexmask.word 0x0 0.--8. 1. " ELS ,Event link select"
|
|
group.word (0x34)++0x01
|
|
line.word 0x0 "ELSR9,Event Link Setting Register 9"
|
|
hexmask.word 0x0 0.--8. 1. " ELS ,Event link select"
|
|
group.word (0x38)++0x01
|
|
line.word 0x0 "ELSR10,Event Link Setting Register 10"
|
|
hexmask.word 0x0 0.--8. 1. " ELS ,Event link select"
|
|
group.word (0x3C)++0x01
|
|
line.word 0x0 "ELSR11,Event Link Setting Register 11"
|
|
hexmask.word 0x0 0.--8. 1. " ELS ,Event link select"
|
|
group.word (0x40)++0x01
|
|
line.word 0x0 "ELSR12,Event Link Setting Register 12"
|
|
hexmask.word 0x0 0.--8. 1. " ELS ,Event link select"
|
|
group.word (0x44)++0x01
|
|
line.word 0x0 "ELSR13,Event Link Setting Register 13"
|
|
hexmask.word 0x0 0.--8. 1. " ELS ,Event link select"
|
|
group.word (0x48)++0x01
|
|
line.word 0x0 "ELSR14,Event Link Setting Register 14"
|
|
hexmask.word 0x0 0.--8. 1. " ELS ,Event link select"
|
|
group.word (0x4C)++0x01
|
|
line.word 0x0 "ELSR15,Event Link Setting Register 15"
|
|
hexmask.word 0x0 0.--8. 1. " ELS ,Event link select"
|
|
group.word (0x50)++0x01
|
|
line.word 0x0 "ELSR16,Event Link Setting Register 16"
|
|
hexmask.word 0x0 0.--8. 1. " ELS ,Event link select"
|
|
group.word (0x54)++0x01
|
|
line.word 0x0 "ELSR17,Event Link Setting Register 17"
|
|
hexmask.word 0x0 0.--8. 1. " ELS ,Event link select"
|
|
group.word (0x58)++0x01
|
|
line.word 0x0 "ELSR18,Event Link Setting Register 18"
|
|
hexmask.word 0x0 0.--8. 1. " ELS ,Event link select"
|
|
width 0x0B
|
|
tree.end
|
|
tree "I/O Ports"
|
|
tree "Port 0"
|
|
base ad:0x40040000
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCNTR1,Port Control Register 1"
|
|
bitfld.long 0x00 31. " PODR15 ,P015 Output Data" "Low,High"
|
|
bitfld.long 0x00 30. " PODR14 ,P014 Output Data" "Low,High"
|
|
bitfld.long 0x00 29. " PODR13 ,P013 Output Data" "Low,High"
|
|
bitfld.long 0x00 28. " PODR12 ,P012 Output Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PODR11 ,P011 Output Data" "Low,High"
|
|
bitfld.long 0x00 26. " PODR10 ,P010 Output Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 25. " PODR09 ,P009 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 24. " PODR08 ,P008 Output Data" "Low,High"
|
|
bitfld.long 0x00 23. " PODR07 ,P007 Output Data" "Low,High"
|
|
bitfld.long 0x00 22. " PODR06 ,P006 Output Data" "Low,High"
|
|
bitfld.long 0x00 21. " PODR05 ,P005 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " PODR04 ,P004 Output Data" "Low,High"
|
|
bitfld.long 0x00 19. " PODR03 ,P003 Output Data" "Low,High"
|
|
bitfld.long 0x00 18. " PODR02 ,P002 Output Data" "Low,High"
|
|
bitfld.long 0x00 17. " PODR01 ,P001 Output Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PODR00 ,P000 Output Data" "Low,High"
|
|
bitfld.long 0x00 15. " PDR15 ,P015 Direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PDR14 ,P014 Direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDR13 ,P013 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PDR12 ,P012 Direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDR11 ,P011 Direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDR10 ,P010 Direction" "Input,Output"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 9. " PDR09 ,P009 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 8. " PDR08 ,P008 Direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDR07 ,P007 Direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDR06 ,P006 Direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDR05 ,P005 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " PDR04 ,P004 Direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDR03 ,P003 Direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDR02 ,P002 Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDR01 ,P001 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PDR00 ,P000 Direction" "Input,Output"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PCNTR2,Port Control Register 2"
|
|
bitfld.long 0x00 31. " EIDR15 ,P015 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 30. " EIDR14 ,P014 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 29. " EIDR13 ,P013 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 28. " EIDR12 ,P012 Event Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " EIDR11 ,P011 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 26. " EIDR10 ,P010 Event Input Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 25. " EIDR09 ,P009 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 24. " EIDR08 ,P008 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 23. " EIDR07 ,P007 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 22. " EIDR06 ,P006 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 21. " EIDR05 ,P005 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " EIDR04 ,P004 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 19. " EIDR03 ,P003 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 18. " EIDR02 ,P002 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 17. " EIDR01 ,P001 Event Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EIDR00 ,P000 Event Input Data" "Low,High"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "PCNTR3,Port Control Register 3"
|
|
bitfld.long 0x00 31. " PORR15 ,P015 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 30. " PORR14 ,P014 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 29. " PORR13 ,P013 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 28. " PORR12 ,P012 Output Reset" "No affect,Low"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PORR11 ,P011 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 26. " PORR10 ,P010 Output Reset" "No affect,Low"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 25. " PORR09 ,P009 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 24. " PORR08 ,P008 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 23. " PORR07 ,P007 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 22. " PORR06 ,P006 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 21. " PORR05 ,P005 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " PORR04 ,P004 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 19. " PORR03 ,P003 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 18. " PORR02 ,P002 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 17. " PORR01 ,P001 Output Reset" "No affect,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PORR00 ,P000 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 15. " POSR15 ,P015 Output Set" "No affect,High"
|
|
bitfld.long 0x00 14. " POSR14 ,P014 Output Set" "No affect,High"
|
|
bitfld.long 0x00 13. " POSR13 ,P013 Output Set" "No affect,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " POSR12 ,P012 Output Set" "No affect,High"
|
|
bitfld.long 0x00 11. " POSR11 ,P011 Output Set" "No affect,High"
|
|
bitfld.long 0x00 10. " POSR10 ,P010 Output Set" "No affect,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 9. " POSR09 ,P009 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 8. " POSR08 ,P008 Output Set" "No affect,High"
|
|
bitfld.long 0x00 7. " POSR07 ,P007 Output Set" "No affect,High"
|
|
bitfld.long 0x00 6. " POSR06 ,P006 Output Set" "No affect,High"
|
|
bitfld.long 0x00 5. " POSR05 ,P005 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " POSR04 ,P004 Output Set" "No affect,High"
|
|
bitfld.long 0x00 3. " POSR03 ,P003 Output Set" "No affect,High"
|
|
bitfld.long 0x00 2. " POSR02 ,P002 Output Set" "No affect,High"
|
|
bitfld.long 0x00 1. " POSR01 ,P001 Output Set" "No affect,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " POSR00 ,P000 Output Set" "No affect,High"
|
|
group.long 0x800++0x13
|
|
line.long 0x00 "P000PFS,Port 000 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,TS21,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P001PFS,Port 001 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,TS22,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P002PFS,Port 002 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x0C "P003PFS,Port 003 Pin Function Select Register"
|
|
bitfld.long 0x0C 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x0C 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x0C 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x0C 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x0C 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x10 "P004PFS,Port 004 Pin Function Select Register"
|
|
bitfld.long 0x10 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x10 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x10 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x10 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x10 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x10 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x10 0. " PODR ,Port Output Data" "Low,High"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.long 0x814++0x0F
|
|
line.long 0x00 "P005PFS,Port 005 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,TS26,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P006PFS,Port 006 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,TS27,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P007PFS,Port 007 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x0C "P008PFS,Port 008 Pin Function Select Register"
|
|
bitfld.long 0x0C 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,TS29,?..."
|
|
bitfld.long 0x0C 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x0C 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x0C 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x0C 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x0C 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x0C 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.long 0x824++0x03
|
|
line.long 0x00 "P009PFS,Port 009 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
group.long 0x828++0x17
|
|
line.long 0x00 "P010PFS,Port 010 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,TS30,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P011PFS,Port 011 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,TS31,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P012PFS,Port 012 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x0C "P013PFS,Port 013 Pin Function Select Register"
|
|
bitfld.long 0x0C 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x0C 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x0C 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x0C 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x0C 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x10 "P014PFS,Port 014 Pin Function Select Register"
|
|
bitfld.long 0x10 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x10 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x10 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x10 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x10 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x10 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x14 "P015PFS,Port 015 Pin Function Select Register"
|
|
bitfld.long 0x14 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x14 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x14 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x14 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x14 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x14 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x14 0. " PODR ,Port Output Data" "Low,High"
|
|
group.byte ad:0x40040D03++0x00
|
|
line.byte 0x00 "PWPR,Write-Protect Register"
|
|
bitfld.byte 0x00 7. " B0WI ,PFSWE Bit Write Disable" "No,Yes"
|
|
bitfld.byte 0x00 6. " PFSWE ,PFS Register Write Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port 1"
|
|
base ad:0x40040000
|
|
width 9.
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PCNTR1,Port Control Register 1"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 31. " PODR15 ,P115 Output Data" "Low,High"
|
|
bitfld.long 0x00 30. " PODR14 ,P114 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " PODR13 ,P113 Output Data" "Low,High"
|
|
bitfld.long 0x00 28. " PODR12 ,P112 Output Data" "Low,High"
|
|
bitfld.long 0x00 27. " PODR11 ,P111 Output Data" "Low,High"
|
|
bitfld.long 0x00 26. " PODR10 ,P110 Output Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PODR09 ,P109 Output Data" "Low,High"
|
|
bitfld.long 0x00 24. " PODR08 ,P108 Output Data" "Low,High"
|
|
bitfld.long 0x00 23. " PODR07 ,P107 Output Data" "Low,High"
|
|
bitfld.long 0x00 22. " PODR06 ,P106 Output Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PODR05 ,P105 Output Data" "Low,High"
|
|
bitfld.long 0x00 20. " PODR04 ,P104 Output Data" "Low,High"
|
|
bitfld.long 0x00 19. " PODR03 ,P103 Output Data" "Low,High"
|
|
bitfld.long 0x00 18. " PODR02 ,P102 Output Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PODR01 ,P101 Output Data" "Low,High"
|
|
bitfld.long 0x00 16. " PODR00 ,P100 Output Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 15. " PDR15 ,P115 Direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PDR14 ,P114 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " PDR13 ,P113 Direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDR12 ,P112 Direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDR11 ,P111 Direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDR10 ,P110 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PDR09 ,P109 Direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDR08 ,P108 Direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PDR07 ,P107 Direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDR06 ,P106 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PDR05 ,P105 Direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDR04 ,P104 Direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDR03 ,P103 Direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDR02 ,P102 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PDR01 ,P101 Direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDR00 ,P100 Direction" "Input,Output"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "PCNTR2,Port Control Register 2"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 31. " EIDR15 ,P115 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 30. " EIDR14 ,P114 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " EIDR13 ,P113 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 28. " EIDR12 ,P112 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 27. " EIDR11 ,P111 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 26. " EIDR10 ,P110 Event Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EIDR09 ,P109 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 24. " EIDR08 ,P108 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 23. " EIDR07 ,P107 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 22. " EIDR06 ,P106 Event Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EIDR05 ,P105 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 20. " EIDR04 ,P104 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 19. " EIDR03 ,P103 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 18. " EIDR02 ,P102 Event Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EIDR01 ,P101 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 16. " EIDR00 ,P100 Event Input Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 15. " PIDR15 ,P115 Direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PIDR14 ,P114 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " PIDR13 ,P113 Direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PIDR12 ,P112 Direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PIDR11 ,P111 Direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PIDR10 ,P110 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PIDR09 ,P109 Direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PIDR08 ,P108 Direction" "Input,Output"
|
|
bitfld.long 0x00 7. " PIDR07 ,P107 Direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PIDR06 ,P106 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PIDR05 ,P105 Direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PIDR04 ,P104 Direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PIDR03 ,P103 Direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PIDR02 ,P102 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PIDR01 ,P101 Direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PIDR00 ,P100 Direction" "Input,Output"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "PCNTR3,Port Control Register 3"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 31. " PORR15 ,P115 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 30. " PORR14 ,P114 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " PORR13 ,P113 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 28. " PORR12 ,P112 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 27. " PORR11 ,P111 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 26. " PORR10 ,P110 Output Reset" "No affect,Low"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PORR09 ,P109 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 24. " PORR08 ,P108 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 23. " PORR07 ,P107 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 22. " PORR06 ,P106 Output Reset" "No affect,Low"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PORR05 ,P105 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 20. " PORR04 ,P104 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 19. " PORR03 ,P103 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 18. " PORR02 ,P102 Output Reset" "No affect,Low"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PORR01 ,P101 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 16. " PORR00 ,P100 Output Reset" "No affect,Low"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 15. " POSR15 ,P115 Output Set" "No affect,High"
|
|
bitfld.long 0x00 14. " POSR14 ,P114 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " POSR13 ,P113 Output Set" "No affect,High"
|
|
bitfld.long 0x00 12. " POSR12 ,P112 Output Set" "No affect,High"
|
|
bitfld.long 0x00 11. " POSR11 ,P111 Output Set" "No affect,High"
|
|
bitfld.long 0x00 10. " POSR10 ,P110 Output Set" "No affect,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POSR09 ,P109 Output Set" "No affect,High"
|
|
bitfld.long 0x00 8. " POSR08 ,P108 Output Set" "No affect,High"
|
|
bitfld.long 0x00 7. " POSR07 ,P107 Output Set" "No affect,High"
|
|
bitfld.long 0x00 6. " POSR06 ,P106 Output Set" "No affect,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " POSR05 ,P105 Output Set" "No affect,High"
|
|
bitfld.long 0x00 4. " POSR04 ,P104 Output Set" "No affect,High"
|
|
bitfld.long 0x00 3. " POSR03 ,P103 Output Set" "No affect,High"
|
|
bitfld.long 0x00 2. " POSR02 ,P102 Output Set" "No affect,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " POSR01 ,P101 Output Set" "No affect,High"
|
|
bitfld.long 0x00 0. " POSR00 ,P100 Output Set" "No affect,High"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PCNTR4,Port Control Register 4"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 31. " EORR15 ,P115 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 30. " EORR14 ,P114 Event Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 29. " EORR13 ,P113 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 28. " EORR12 ,P112 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 27. " EORR11 ,P111 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 26. " EORR10 ,P110 Event Output Reset" "No affect,Low"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EORR09 ,P109 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 24. " EORR08 ,P108 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 23. " EORR07 ,P107 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 22. " EORR06 ,P106 Event Output Reset" "No affect,Low"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EORR05 ,P105 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 20. " EORR04 ,P104 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 19. " EORR03 ,P103 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 18. " EORR02 ,P102 Event Output Reset" "No affect,Low"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EORR01 ,P101 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 16. " EORR00 ,P100 Event Output Reset" "No affect,Low"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 15. " EOSR15 ,P115 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 14. " EOSR14 ,P114 Event Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " EOSR13 ,P113 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 12. " EOSR12 ,P112 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 11. " EOSR11 ,P111 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 10. " EOSR10 ,P110 Event Output Set" "No affect,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EOSR09 ,P109 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 8. " EOSR08 ,P108 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 7. " EOSR07 ,P107 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 6. " EOSR06 ,P106 Event Output Set" "No affect,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EOSR05 ,P105 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 4. " EOSR04 ,P104 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 3. " EOSR03 ,P103 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 2. " EOSR02 ,P102 Event Output Set" "No affect,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOSR01 ,P101 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 0. " EOSR00 ,P100 Event Output Set" "No affect,High"
|
|
group.long 0x840++0x37
|
|
line.long 0x00 "P100PFS,Port 100 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTIO0_A,GTETRGA_A,,RXD0_A/MISO0_A/SCL0_A,SCK1_A,MISOA_A,SCL1_B,KR00,,,D00,,VL1,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P101PFS,Port 101 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTEE0,GTETRGB_A,,TXD0_A/MOSI0_A/SDA0_A,CTS1_RTS1_A/SS1_A,MOSIA_A,SDA1_B,KR01,,,D01,,VL2,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P102PFS,Port 102 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTO0,GTOWLO_A,GTIOC2B_A,SCK0_A,,RSPCKA_A,,KR02,,ADTRG0_A,D02,,VL3,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x0C "P103PFS,Port 103 Pin Function Select Register"
|
|
bitfld.long 0x0C 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTOWUP_A,GTIOC2A_A,CTS0_RTS0_A/SS0_A,,SSLA0_A,,KR03,,,D03,,VL4,?..."
|
|
bitfld.long 0x0C 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x0C 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x0C 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x0C 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x0C 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x0C 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x10 "P104PFS,Port 104 Pin Function Select Register"
|
|
bitfld.long 0x10 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTETRGB_B,,,,SSLA1_A,,KR04,,,D04,,COM0,?..."
|
|
bitfld.long 0x10 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x10 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x10 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x10 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x10 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x10 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x10 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x14 "P105PFS,Port 105 Pin Function Select Register"
|
|
bitfld.long 0x14 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTETRGA_C,,,,SSLA2_A,,KR05,,,D05,,COM1,?..."
|
|
bitfld.long 0x14 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x14 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x14 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x14 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x14 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x14 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x14 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x18 "P106PFS,Port 106 Pin Function Select Register"
|
|
bitfld.long 0x18 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC8B_A,,,SSLA3_A,,KR06,,,D06,,COM2,?..."
|
|
bitfld.long 0x18 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x18 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x18 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x18 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x18 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x18 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x1C "P107PFS,Port 107 Pin Function Select Register"
|
|
bitfld.long 0x1C 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC8A_A,,,,,KR07,,,D07,,COM3,?..."
|
|
bitfld.long 0x1C 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x1C 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x1C 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x1C 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x1C 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x20 "P108PFS,Port 108 Pin Function Select Register"
|
|
bitfld.long 0x20 24.--28. " PSEL ,Peripheral Select" "TMS/SWDIO,,,GTIOC0B_A,,CTS9_RTS9_B/SS9_B,SSLB0_B,?..."
|
|
bitfld.long 0x20 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x20 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x20 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x20 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x20 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x20 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x20 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x24 "P109PFS,Port 109 Pin Function Select Register"
|
|
bitfld.long 0x24 24.--28. " PSEL ,Peripheral Select" "TDO/SWO,,GTOVUP_A,GTIOC1A_A,,TXD9_B/MOSI9_B/SDA9_B,MOSIB_B,,,CLKOUT_B,?..."
|
|
bitfld.long 0x24 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x24 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x24 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x24 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x24 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x24 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x24 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x28 "P110PFS,Port 110 Pin Function Select Register"
|
|
bitfld.long 0x28 24.--28. " PSEL ,Peripheral Select" "TDI,,GTOVLO_A,GTIOC1B_A,CTS2_RTS2_B/SS2_B,RXD9_B/MISO9_B/SCL9_B,MISOB_B,,,VCOUT,?..."
|
|
bitfld.long 0x28 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x28 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x28 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x28 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x28 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x28 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x28 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x2C "P111PFS,Port 111 Pin Function Select Register"
|
|
bitfld.long 0x2C 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC3A_A,SCK2_B,SCK9_B,RSPCKB_B,,,,,A05,,CAPH,?..."
|
|
bitfld.long 0x2C 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x2C 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x2C 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x2C 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x2C 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x2C 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x2C 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x2C 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x30 "P112PFS,Port 112 Pin Function Select Register"
|
|
bitfld.long 0x30 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC3B_A,TXD2_B/MOSI2_B/SDA2_B,,,,,,,A04,,CAPL,,,,,SSISCK0_B,?..."
|
|
bitfld.long 0x30 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x30 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x30 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x30 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x30 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x30 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x30 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x34 "P113PFS,Port 113 Pin Function Select Register"
|
|
bitfld.long 0x34 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,RXD2_B/MISO2_B/SCL2_B,,,,,,,A03,,SEG0/COM4,,,,,SSIWS0_B,?..."
|
|
bitfld.long 0x34 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x34 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x34 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x34 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x34 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x34 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x34 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x34 0. " PODR ,Port Output Data" "Low,High"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.long 0x878++0x07
|
|
line.long 0x00 "P114PFS,Port 114 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,A02,,SEG24,,,,,SSIRXD0_B,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P115PFS,Port 115 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,A01,,SEG25,,,,,SSITXD0_B,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
group.byte ad:0x40040D03++0x00
|
|
line.byte 0x00 "PWPR,Write-Protect Register"
|
|
bitfld.byte 0x00 7. " B0WI ,PFSWE Bit Write Disable" "No,Yes"
|
|
bitfld.byte 0x00 6. " PFSWE ,PFS Register Write Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port 2"
|
|
base ad:0x40040000
|
|
width 9.
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PCNTR1,Port Control Register 1"
|
|
bitfld.long 0x00 29. " PODR13 ,P213 Output Data" "Low,High"
|
|
bitfld.long 0x00 28. " PODR12 ,P212 Output Data" "Low,High"
|
|
bitfld.long 0x00 22. " PODR06 ,P206 Output Data" "Low,High"
|
|
bitfld.long 0x00 21. " PODR05 ,P205 Output Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PODR04 ,P204 Output Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 19. " PODR03 ,P203 Output Data" "Low,High"
|
|
bitfld.long 0x00 18. " PODR02 ,P202 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " PODR01 ,P201 Output Data" "Low,High"
|
|
bitfld.long 0x00 13. " PDR13 ,P213 Direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDR12 ,P212 Direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDR06 ,P206 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PDR05 ,P205 Direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDR04 ,P204 Direction" "Input,Output"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 3. " PDR03 ,P203 Direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDR02 ,P202 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " PDR01 ,P201 Direction" "Input,Output"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "PCNTR2,Port Control Register 2"
|
|
bitfld.long 0x00 31. " EIDR15 ,P215 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 30. " EIDR14 ,P214 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 29. " EIDR13 ,P213 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 28. " EIDR12 ,P212 Event Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EIDR06 ,P206 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 21. " EIDR05 ,P205 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 20. " EIDR04 ,P204 Event Input Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 19. " EIDR03 ,P203 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 18. " EIDR02 ,P202 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " EIDR01 ,P201 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 16. " EIDR00 ,P200 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 15. " PIDR15 ,P215 Direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PIDR14 ,P214 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PIDR13 ,P213 Direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PIDR12 ,P212 Direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PID06 ,P206 Direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PIDR05 ,P205 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PIDR04 ,P204 Direction" "Input,Output"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 3. " PIDR03 ,P203 Direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PIDR02 ,P202 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " PIDR01 ,P201 Direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PIDR00 ,P200 Direction" "Input,Output"
|
|
textline " "
|
|
wgroup.long 0x48++0x03
|
|
line.long 0x00 "PCNTR3,Port Control Register 3"
|
|
bitfld.long 0x00 31. " PORR15 ,P215 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 30. " PORR14 ,P214 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 29. " PORR13 ,P213 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 28. " PORR12 ,P212 Output Reset" "No affect,Low"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PORR06 ,P206 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 21. " PORR05 ,P205 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 20. " PORR04 ,P204 Output Reset" "No affect,Low"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 19. " PORR03 ,P203 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 18. " PORR02 ,P202 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " PORR01 ,P201 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 16. " PORR00 ,P200 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 15. " POSR15 ,P215 Output Set" "No affect,High"
|
|
bitfld.long 0x00 14. " POSR14 ,P214 Output Set" "No affect,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " POSR13 ,P213 Output Set" "No affect,High"
|
|
bitfld.long 0x00 12. " POSR12 ,P212 Output Set" "No affect,High"
|
|
bitfld.long 0x00 6. " POSR06 ,P206 Output Set" "No affect,High"
|
|
bitfld.long 0x00 5. " POSR05 ,P205 Output Set" "No affect,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " POSR04 ,P204 Output Set" "No affect,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 3. " POSR03 ,P203 Output Set" "No affect,High"
|
|
bitfld.long 0x00 2. " POSR02 ,P202 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " POSR01 ,P201 Output Set" "No affect,High"
|
|
bitfld.long 0x00 0. " POSR00 ,P200 Output Set" "No affect,High"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PCNTR4,Port Control Register 4"
|
|
bitfld.long 0x00 31. " EORR15 ,P215 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 30. " EORR14 ,P214 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 29. " EORR13 ,P213 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 28. " EORR12 ,P212 Event Output Reset" "No affect,Low"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EORR06 ,P206 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 21. " EORR05 ,P205 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 20. " EORR04 ,P204 Event Output Reset" "No affect,Low"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 19. " EORR03 ,P203 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 18. " EORR02 ,P202 Event Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " EORR01 ,P201 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 16. " EORR00 ,P200 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 15. " EOSR15 ,P215 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 14. " EOSR14 ,P214 Event Output Set" "No affect,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EOSR13 ,P213 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 12. " EOSR12 ,P212 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 6. " EOSR06 ,P206 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 5. " EOSR05 ,P205 Event Output Set" "No affect,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EOSR04 ,P204 Event Output Set" "No affect,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 3. " EOSR03 ,P203 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 2. " EOSR02 ,P202 Event Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " EOSR01 ,P201 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 0. " EOSR00 ,P200 Event Output Set" "No affect,High"
|
|
group.long 0x880++0x07
|
|
line.long 0x00 "P200PFS,Port 200 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P201PFS,Port 201 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.long 0x888++0x07
|
|
line.long 0x00 "P202PFS,Port 202 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC5B_A,SCK2_A,RXD9_A/MISO9_A/SCL9_A,MISOB_A,,,,,WR1/BC1,,SEG21,,,CRX0_A,,,,,SD0DAT6,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P203PFS,Port 203 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC5A_A,CTS2_RTS2_A/SS2_A,TXD9_A/MOSI9_A/SDA9_A,MOSIB_A,,,,,,TSCAP_B,SEG22,,,CTX0_A,,,,,SD0DAT5,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
group.long 0x890++0x0B
|
|
line.long 0x00 "P204PFS,Port 204 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTIO1_A,GTIW_A,GTIOC4B_B,SCK4_A,SCK9_A,RSPCKB_A,SCL0_B,,,CACREF_A,,TS00,SEG23,,,,,SSISCK1_A,USB_OVRCURB_A,,SD0DAT4,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P205PFS,Port 205 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTO1,GTIV_A,GTIOC4A_B,TXD4_A/MOSI4_A/SDA4_A,CTS9_RTS9_A/SS9_A,SSLB0_A,SCL1_A,,CLKOUT_A,,A16,TSCAP_A,,,,,,SSIWS1_A,USB_OVRCURA_A,,SD0DAT3,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P206PFS,Port 206 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTIV_A,GTIOC4A_B,TXD4_A/MOSI4_A/SDA4_A,CTS9_RTS9_A/SS9_A,SSLB0_A,SCL1_A,,CLKOUT_A,,A16,TSCAP_A,,,,,,SSIWS1_A,USB_OVRCURA_A,,SD0DAT3,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
group.long 0x8B0++0x23
|
|
line.long 0x00 "P212PFS,Port 212 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTEE1,GTETRGD_A,,,RXD1_A/MISO1_A/SCL1_A,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P213PFS,Port 213 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTETRGC_A,,,TXD1_A/MOSI1_A/SDA1_A,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P214PFS,Port 214 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x0C "P215PFS,Port 215 Pin Function Select Register"
|
|
bitfld.long 0x0C 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x0C 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x0C 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x0C 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x0C 0. " PODR ,Port Output Data" "Low,High"
|
|
group.byte ad:0x40040D03++0x00
|
|
line.byte 0x00 "PWPR,Write-Protect Register"
|
|
bitfld.byte 0x00 7. " B0WI ,PFSWE Bit Write Disable" "No,Yes"
|
|
bitfld.byte 0x00 6. " PFSWE ,PFS Register Write Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port 3"
|
|
base ad:0x40040000
|
|
width 9.
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "PCNTR1,Port Control Register 1"
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 31. " PODR15 ,P315 Output Data" "Low,High"
|
|
bitfld.long 0x00 30. " PODR14 ,P314 Output Data" "Low,High"
|
|
bitfld.long 0x00 29. " PODR13 ,P313 Output Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))
|
|
bitfld.long 0x00 28. " PODR12 ,P312 Output Data" "Low,High"
|
|
bitfld.long 0x00 27. " PODR11 ,P311 Output Data" "Low,High"
|
|
bitfld.long 0x00 26. " PODR10 ,P310 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " PODR09 ,P309 Output Data" "Low,High"
|
|
bitfld.long 0x00 24. " PODR08 ,P308 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 23. " PODR07 ,P307 Output Data" "Low,High"
|
|
bitfld.long 0x00 22. " PODR06 ,P306 Output Data" "Low,High"
|
|
bitfld.long 0x00 21. " PODR05 ,P305 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " PODR04 ,P304 Output Data" "Low,High"
|
|
bitfld.long 0x00 19. " PODR03 ,P303 Output Data" "Low,High"
|
|
bitfld.long 0x00 18. " PODR02 ,P302 Output Data" "Low,High"
|
|
bitfld.long 0x00 17. " PODR01 ,P301 Output Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PODR00 ,P300 Output Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 15. " PDR15 ,P315 Direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PDR14 ,P314 Direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDR13 ,P313 Direction" "Input,Output"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))
|
|
bitfld.long 0x00 12. " PDR12 ,P312 Direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDR11 ,P311 Direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDR10 ,P310 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " PDR09 ,P309 Direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDR08 ,P308 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 7. " PDR07 ,P307 Direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDR06 ,P306 Direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDR05 ,P305 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " PDR04 ,P304 Direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDR03 ,P303 Direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDR02 ,P302 Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDR01 ,P301 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PDR00 ,P300 Direction" "Input,Output"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "PCNTR2,Port Control Register 2"
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 31. " EIDR15 ,P315 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 30. " EIDR14 ,P314 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 29. " EIDR13 ,P313 Event Input Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))
|
|
bitfld.long 0x00 28. " EIDR12 ,P312 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 27. " EIDR11 ,P311 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 26. " EIDR10 ,P310 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " EIDR09 ,P309 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 24. " EIDR08 ,P308 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 23. " EIDR07 ,P307 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 22. " EIDR06 ,P306 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 21. " EIDR05 ,P305 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " EIDR04 ,P304 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 19. " EIDR03 ,P303 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 18. " EIDR02 ,P302 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 17. " EIDR01 ,P301 Event Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EIDR00 ,P300 Event Input Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 15. " PIDR15 ,P315 Direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PIDR14 ,P314 Direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PIDR13 ,P313 Direction" "Input,Output"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))
|
|
bitfld.long 0x00 12. " PIDR12 ,P312 Direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PIDR11 ,P311 Direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PIDR10 ,P310 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " PIDR09 ,P309 Direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PIDR08 ,P308 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 7. " PIDR07 ,P307 Direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PIDR06 ,P306 Direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PIDR05 ,P305 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " PIDR04 ,P304 Direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PIDR03 ,P303 Direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PIDR02 ,P302 Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PIDR01 ,P301 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PIDR00 ,P300 Direction" "Input,Output"
|
|
wgroup.long 0x68++0x03
|
|
line.long 0x00 "PCNTR3,Port Control Register 3"
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 31. " PORR15 ,P315 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 30. " PORR14 ,P314 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 29. " PORR13 ,P313 Output Reset" "No affect,Low"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))
|
|
bitfld.long 0x00 28. " PORR12 ,P312 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 27. " PORR11 ,P311 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 26. " PORR10 ,P310 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " PORR09 ,P309 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 24. " PORR08 ,P308 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 23. " PORR07 ,P307 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 22. " PORR06 ,P306 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 21. " PORR05 ,P305 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " PORR04 ,P304 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 19. " PORR03 ,P303 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 18. " PORR02 ,P302 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 17. " PORR01 ,P301 Output Reset" "No affect,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PORR00 ,P300 Output Reset" "No affect,Low"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 15. " POSR15 ,P315 Output Set" "No affect,High"
|
|
bitfld.long 0x00 14. " POSR14 ,P314 Output Set" "No affect,High"
|
|
bitfld.long 0x00 13. " POSR13 ,P313 Output Set" "No affect,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))
|
|
bitfld.long 0x00 12. " POSR12 ,P312 Output Set" "No affect,High"
|
|
bitfld.long 0x00 11. " POSR11 ,P311 Output Set" "No affect,High"
|
|
bitfld.long 0x00 10. " POSR10 ,P310 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " POSR09 ,P309 Output Set" "No affect,High"
|
|
bitfld.long 0x00 8. " POSR08 ,P308 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 7. " POSR07 ,P307 Output Set" "No affect,High"
|
|
bitfld.long 0x00 6. " POSR06 ,P306 Output Set" "No affect,High"
|
|
bitfld.long 0x00 5. " POSR05 ,P305 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " POSR04 ,P304 Output Set" "No affect,High"
|
|
bitfld.long 0x00 3. " POSR03 ,P303 Output Set" "No affect,High"
|
|
bitfld.long 0x00 2. " POSR02 ,P302 Output Set" "No affect,High"
|
|
bitfld.long 0x00 1. " POSR01 ,P301 Output Set" "No affect,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " POSR00 ,P300 Output Set" "No affect,High"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PCNTR4,Port Control Register 4"
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 31. " EORR15 ,P315 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 30. " EORR14 ,P314 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 29. " EORR13 ,P313 Event Output Reset" "No affect,Low"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))
|
|
bitfld.long 0x00 28. " EORR12 ,P312 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 27. " EORR11 ,P311 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 26. " EORR10 ,P310 Event Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " EORR09 ,P309 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 24. " EORR08 ,P308 Event Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 23. " EORR07 ,P307 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 22. " EORR06 ,P306 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 21. " EORR05 ,P305 Event Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " EORR04 ,P304 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 19. " EORR03 ,P303 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 18. " EORR02 ,P302 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 17. " EORR01 ,P301 Event Output Reset" "No affect,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EORR00 ,P300 Event Output Reset" "No affect,Low"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 15. " EOSR15 ,P315 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 14. " EOSR14 ,P314 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 13. " EOSR13 ,P313 Event Output Set" "No affect,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))
|
|
bitfld.long 0x00 12. " EOSR12 ,P312 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 11. " EOSR11 ,P311 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 10. " EOSR10 ,P310 Event Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " EOSR09 ,P309 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 8. " EOSR08 ,P308 Event Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 7. " EOSR07 ,P307 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 6. " EOSR06 ,P306 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 5. " EOSR05 ,P305 Event Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " EOSR04 ,P304 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 3. " EOSR03 ,P303 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 2. " EOSR02 ,P302 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 1. " EOSR01 ,P301 Event Output Set" "No affect,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EOSR00 ,P300 Event Output Set" "No affect,High"
|
|
group.long 0x8C0++0x23
|
|
line.long 0x10 "P300PFS,Port 300 Pin Function Select Register"
|
|
bitfld.long 0x10 24.--28. " PSEL ,Peripheral Select" "TCK/SWCLK,,,GTIOC0A_A,,,SSLB1_B,?..."
|
|
bitfld.long 0x10 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x10 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x10 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x10 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x10 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x10 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x10 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x14 "P301PFS,Port 301 Pin Function Select Register"
|
|
bitfld.long 0x14 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTOULO_A,GTIOC4B_A,RXD2_A/MISO2_A/SCL2_A,,SSLB2_B,,,,,A06,,SEG1/COM5,?..."
|
|
bitfld.long 0x14 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x14 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x14 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x14 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x14 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x14 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x14 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x18 "P302PFS,Port 302 Pin Function Select Register"
|
|
bitfld.long 0x18 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTOUUP_A,GTIOC4A_A,TXD2_A/MOSI2_A/SDA2_A,,SSLB3_B,,,,,A07,,SEG2/COM6,?..."
|
|
bitfld.long 0x18 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x18 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x18 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x18 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x18 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x18 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x18 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x1C "P303PFS,Port 303 Pin Function Select Register"
|
|
bitfld.long 0x1C 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC7B_A,,,,,,,,A08,,SEG3/COM7,?..."
|
|
bitfld.long 0x1C 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x1C 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x1C 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x1C 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x1C 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x1C 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x1C 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x20 "P304PFS,Port 304 Pin Function Select Register"
|
|
bitfld.long 0x20 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC7A_A,,,,,,,,A09,,SEG17,?..."
|
|
bitfld.long 0x20 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x20 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x20 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x20 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x20 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x20 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x20 0. " PODR ,Port Output Data" "Low,High"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.long 0x8D4++0x0B
|
|
line.long 0x00 "P305PFS,Port 305 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,A10,,SEG16,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P306PFS,Port 306 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,A11,,SEG15,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P307PFS,Port 307 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,A12,,SEG14,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.long 0x8E0++0x07
|
|
line.long 0x00 "P308PFS,Port 308 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,A13,,SEG13,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P309PFS,Port 309 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,A14,,SEG12,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))
|
|
group.long 0x8E8++0x0B
|
|
line.long 0x00 "P310PFS,Port 310 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,A15,,SEG11,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P311PFS,Port 311 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,CS2,,SEG10,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P312PFS,Port 312 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,CS3,,SEG9,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.long 0x8F4++0x0B
|
|
line.long 0x00 "P313PFS,Port 313 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,,SEG20,,,,,,,,SD0DAT7,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P314PFS,Port 314 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,,SEG4,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P315PFS,Port 315 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,,SEG5,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
group.byte ad:0x40040D03++0x00
|
|
line.byte 0x00 "PWPR,Write-Protect Register"
|
|
bitfld.byte 0x00 7. " B0WI ,PFSWE Bit Write Disable" "No,Yes"
|
|
bitfld.byte 0x00 6. " PFSWE ,PFS Register Write Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port 4"
|
|
base ad:0x40040000
|
|
width 9.
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "PCNTR1,Port Control Register 1"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 31. " PODR15 ,P415 Output Data" "Low,High"
|
|
bitfld.long 0x00 30. " PODR14 ,P414 Output Data" "Low,High"
|
|
bitfld.long 0x00 29. " PODR13 ,P413 Output Data" "Low,High"
|
|
bitfld.long 0x00 28. " PODR12 ,P412 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " PODR11 ,P411 Output Data" "Low,High"
|
|
bitfld.long 0x00 26. " PODR10 ,P410 Output Data" "Low,High"
|
|
bitfld.long 0x00 25. " PODR09 ,P409 Output Data" "Low,High"
|
|
bitfld.long 0x00 24. " PODR08 ,P408 Output Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PODR07 ,P407 Output Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 22. " PODR06 ,P406 Output Data" "Low,High"
|
|
bitfld.long 0x00 21. " PODR05 ,P405 Output Data" "Low,High"
|
|
bitfld.long 0x00 20. " PODR04 ,P404 Output Data" "Low,High"
|
|
bitfld.long 0x00 19. " PODR03 ,P403 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " PODR02 ,P402 Output Data" "Low,High"
|
|
bitfld.long 0x00 17. " PODR01 ,P401 Output Data" "Low,High"
|
|
bitfld.long 0x00 16. " PODR00 ,P400 Output Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 15. " PDR15 ,P415 Direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PDR14 ,P414 Direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDR13 ,P413 Direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDR12 ,P412 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " PDR11 ,P411 Direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDR10 ,P410 Direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDR09 ,P409 Direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDR08 ,P408 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PDR07 ,P407 Direction" "Input,Output"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 6. " PDR06 ,P406 Direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDR05 ,P405 Direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDR04 ,P404 Direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDR03 ,P403 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " PDR02 ,P402 Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDR01 ,P401 Direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDR00 ,P400 Direction" "Input,Output"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "PCNTR2,Port Control Register 2"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 31. " EIDR15 ,P415 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 30. " EIDR14 ,P414 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 29. " EIDR13 ,P413 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 28. " EIDR12 ,P412 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " EIDR11 ,P411 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 26. " EIDR10 ,P410 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 25. " EIDR09 ,P409 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 24. " EIDR08 ,P408 Event Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EIDR07 ,P407 Event Input Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 22. " EIDR06 ,P406 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 21. " EIDR05 ,P405 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 20. " EIDR04 ,P404 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 19. " EIDR03 ,P403 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " EIDR02 ,P402 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 17. " EIDR01 ,P401 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 16. " EIDR00 ,P400 Event Input Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 15. " PIDR15 ,P415 Direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PIDR14 ,P414 Direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PIDR13 ,P413 Direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PIDR12 ,P412 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " PIDR11 ,P411 Direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PIDR10 ,P410 Direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PIDR09 ,P409 Direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PIDR08 ,P408 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PIDR07 ,P407 Direction" "Input,Output"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 6. " PIDR06 ,P406 Direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PIDR05 ,P405 Direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PIDR04 ,P404 Direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PIDR03 ,P403 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " PIDR02 ,P402 Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PIDR01 ,P401 Direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PIDR00 ,P400 Direction" "Input,Output"
|
|
wgroup.long 0x88++0x03
|
|
line.long 0x00 "PCNTR3,Port Control Register 3"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 31. " PORR15 ,P415 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 30. " PORR14 ,P414 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 29. " PORR13 ,P413 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 28. " PORR12 ,P412 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " PORR11 ,P411 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 26. " PORR10 ,P410 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 25. " PORR09 ,P409 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 24. " PORR08 ,P408 Output Reset" "No affect,Low"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PORR07 ,P407 Output Reset" "No affect,Low"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 22. " PORR06 ,P406 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 21. " PORR05 ,P405 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 20. " PORR04 ,P404 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 19. " PORR03 ,P403 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " PORR02 ,P402 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 17. " PORR01 ,P401 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 16. " PORR00 ,P400 Output Reset" "No affect,Low"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 15. " POSR15 ,P415 Output Set" "No affect,High"
|
|
bitfld.long 0x00 14. " POSR14 ,P414 Output Set" "No affect,High"
|
|
bitfld.long 0x00 13. " POSR13 ,P413 Output Set" "No affect,High"
|
|
bitfld.long 0x00 12. " POSR12 ,P412 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " POSR11 ,P411 Output Set" "No affect,High"
|
|
bitfld.long 0x00 10. " POSR10 ,P410 Output Set" "No affect,High"
|
|
bitfld.long 0x00 9. " POSR09 ,P409 Output Set" "No affect,High"
|
|
bitfld.long 0x00 8. " POSR08 ,P408 Output Set" "No affect,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POSR07 ,P407 Output Set" "No affect,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 6. " POSR06 ,P406 Output Set" "No affect,High"
|
|
bitfld.long 0x00 5. " POSR05 ,P405 Output Set" "No affect,High"
|
|
bitfld.long 0x00 4. " POSR04 ,P404 Output Set" "No affect,High"
|
|
bitfld.long 0x00 3. " POSR03 ,P403 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " POSR02 ,P402 Output Set" "No affect,High"
|
|
bitfld.long 0x00 1. " POSR01 ,P401 Output Set" "No affect,High"
|
|
bitfld.long 0x00 0. " POSR00 ,P400 Output Set" "No affect,High"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PCNTR4,Port Control Register 4"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 31. " EORR15 ,P415 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 30. " EORR14 ,P414 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 29. " EORR13 ,P413 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 28. " EORR12 ,P412 Event Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " EORR11 ,P411 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 26. " EORR10 ,P410 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 25. " EORR09 ,P409 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 24. " EORR08 ,P408 Event Output Reset" "No affect,Low"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EORR07 ,P407 Event Output Reset" "No affect,Low"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 22. " EORR06 ,P406 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 21. " EORR05 ,P405 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 20. " EORR04 ,P404 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 19. " EORR03 ,P403 Event Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " EORR02 ,P402 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 17. " EORR01 ,P401 Event Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 16. " EORR00 ,P400 Event Output Reset" "No affect,Low"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 15. " EOSR15 ,P415 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 14. " EOSR14 ,P414 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 13. " EOSR13 ,P413 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 12. " EOSR12 ,P412 Event Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " EOSR11 ,P411 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 10. " EOSR10 ,P410 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 9. " EOSR09 ,P409 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 8. " EOSR08 ,P408 Event Output Set" "No affect,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EOSR07 ,P407 Event Output Set" "No affect,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 6. " EOSR06 ,P406 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 5. " EOSR05 ,P405 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 4. " EOSR04 ,P404 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 3. " EOSR03 ,P403 Event Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " EOSR02 ,P402 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 1. " EOSR01 ,P401 Event Output Set" "No affect,High"
|
|
bitfld.long 0x00 0. " EOSR00 ,P400 Event Output Set" "No affect,High"
|
|
group.long 0x900++0x07
|
|
line.long 0x00 "P400PFS,Port 400 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC6A_A,SCK4_B,,,SCL0_A,,,,,TS20,,,,,,AUDIO_CLK,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P401PFS,Port 401 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTETRGA_B,GTIOC6B_A,CTS4_RTS4_B/SS4_B,,,SDA0_A,,,,,TS19,,,,CTX0_B,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
if (((per.l(ad:0x40040000+0x908))&0x10004)==0x0)
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "P402PFS,Port 402 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B,RTCIC0/AGTIO0_B/AGTIO1_B"
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
else
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "P402PFS,Port 402 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,TS18,,,,CRX0_B,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
if (((per.l(ad:0x40040000+0x90C))&0x10004)==0x0)
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.long 0x90C++0x03
|
|
line.long 0x00 "P403PFS,Port 403 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C,RTCIC1/AGTIO0_C/AGTIO1_C"
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
else
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.long 0x90C++0x03
|
|
line.long 0x00 "P403PFS,Port 403 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC3A_B,,,,,,,,,TS17,,,,,,SSISCK0_A,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40040000+0x910))&0x10004)==0x0)
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "P404PFS,Port 404 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2,RTCIC2"
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
else
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "P404PFS,Port 404 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC3B_B,,,,,,,,,TS16,,,,,,SSIWS0_A,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.long 0x914++0x07
|
|
line.long 0x00 "P405PFS,Port 405 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC1A_B,,,,,,,,,TS15,,,,,,SSITXD0_A,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P406PFS,Port 406 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC1B_B,,,,,,,,,TS14,,,,,,SSIRXD0_A,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
group.long 0x91C++0x13
|
|
line.long 0x00 "P407PFS,Port 407 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,CTS4_RTS4_A/SS4_A,,SSLB3_A,SDA0_B,,RTCOUT,ADTRG0_B,,TS03,,,,,,,USB_VBUS,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P408PFS,Port 408 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTOWLO_B,,,RXD3_A/MISO3_A/SCL3_A,,,,,,,TS04,,,,,,,USB_ID_A,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P409PFS,Port 409 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTOWUP_B,,,TXD3_A/MOSI3_A/SDA3_A,,,,,,,TS05,,,,,,,USB_EXICEN_A,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x0C "P410PFS,Port 410 Pin Function Select Register"
|
|
bitfld.long 0x0C 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTOB1,GTOVLO_B,GTIOC9B_A,RXD0_B/MISO0_B/SCL0_B,SCK3_A,MISOA_B,,,,,,TS06,,,,,,,,,SD0DAT1,?..."
|
|
bitfld.long 0x0C 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x0C 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x0C 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x0C 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x0C 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x0C 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x10 "P411PFS,Port 411 Pin Function Select Register"
|
|
bitfld.long 0x10 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTOA1,GTOVUP_B,GTIOC9A_A,TXD0_B/MOSI0_B/SDA0_B,CTS3_RTS3_A/SS3_A,MOSIA_B,,,,,,TS07,,,,,,,,,SD0DAT0,?..."
|
|
bitfld.long 0x10 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x10 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x10 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x10 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x10 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x10 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x10 0. " PODR ,Port Output Data" "Low,High"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.long 0x930++0x0F
|
|
line.long 0x00 "P412PFS,Port 412 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTOULO_B,,SCK0_B,,RSPCKA_B,,,,,,TS08,,,,,,,,,SD0CMD,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P413PFS,Port 413 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTOUUP_B,,CTS0_RTS0_B/SS0_B,,SSLA0_B,,,,,,TS09,,,,,,,,,SD0CLK,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P414PFS,Port 414 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,SSLA1_B,,,,,,TS10,,,,,,,,,SD0WP,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x0C "P415PFS,Port 415 Pin Function Select Register"
|
|
bitfld.long 0x0C 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,SSLA2_B,,,,,,TS11,?..."
|
|
bitfld.long 0x0C 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x0C 12.--13. " EOF/EOR ,Event on Falling/Event on Rising" ",Rising,Falling,Both"
|
|
bitfld.long 0x0C 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x0C 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x0C 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
group.byte ad:0x40040D03++0x00
|
|
line.byte 0x00 "PWPR,Write-Protect Register"
|
|
bitfld.byte 0x00 7. " B0WI ,PFSWE Bit Write Disable" "No,Yes"
|
|
bitfld.byte 0x00 6. " PFSWE ,PFS Register Write Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port 5"
|
|
base ad:0x40040000
|
|
width 9.
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PCNTR1,Port Control Register 1"
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 28. " PODR12 ,P512 Output Data" "Low,High"
|
|
bitfld.long 0x00 27. " PODR11 ,P511 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 23. " PODR07 ,P507 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 22. " PODR06 ,P506 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 21. " PODR05 ,P505 Output Data" "Low,High"
|
|
bitfld.long 0x00 20. " PODR04 ,P504 Output Data" "Low,High"
|
|
bitfld.long 0x00 19. " PODR03 ,P503 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " PODR02 ,P502 Output Data" "Low,High"
|
|
bitfld.long 0x00 17. " PODR01 ,P501 Output Data" "Low,High"
|
|
bitfld.long 0x00 16. " PODR00 ,P500 Output Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 12. " PDR12 ,P512 Direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDR11 ,P511 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 7. " PDR07 ,P507 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 6. " PDR06 ,P506 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 5. " PDR05 ,P505 Direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDR04 ,P504 Direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDR03 ,P503 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " PDR02 ,P502 Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDR01 ,P501 Direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDR00 ,P500 Direction" "Input,Output"
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "PCNTR2,Port Control Register 2"
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 28. " EIDR12 ,P512 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 27. " EIDR11 ,P511 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 23. " EIDR07 ,P507 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 22. " EIDR06 ,P506 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 21. " EIDR05 ,P505 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 20. " EIDR04 ,P504 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 19. " EIDR03 ,P503 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " EIDR02 ,P502 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 17. " EIDR01 ,P501 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 16. " EIDR00 ,P500 Event Input Data" "Low,High"
|
|
wgroup.long 0xA8++0x03
|
|
line.long 0x00 "PCNTR3,Port Control Register 3"
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 28. " PORR12 ,P512 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 27. " PORR11 ,P511 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 23. " PORR07 ,P507 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 22. " PORR06 ,P506 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 21. " PORR05 ,P505 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 20. " PORR04 ,P504 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 19. " PORR03 ,P503 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " PORR02 ,P502 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 17. " PORR01 ,P501 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 16. " PORR00 ,P500 Output Reset" "No affect,Low"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 12. " POSR12 ,P512 Output Set" "No affect,High"
|
|
bitfld.long 0x00 11. " POSR11 ,P511 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 7. " POSR07 ,P507 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 6. " POSR06 ,P506 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x00 5. " POSR05 ,P505 Output Set" "No affect,High"
|
|
bitfld.long 0x00 4. " POSR04 ,P504 Output Set" "No affect,High"
|
|
bitfld.long 0x00 3. " POSR03 ,P503 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " POSR02 ,P502 Output Set" "No affect,High"
|
|
bitfld.long 0x00 1. " POSR01 ,P501 Output Set" "No affect,High"
|
|
bitfld.long 0x00 0. " POSR00 ,P500 Output Set" "No affect,High"
|
|
group.long 0x940++0x0B
|
|
line.long 0x00 "P500PFS,Port 500 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTOA0,GTIU_B,,,,,,,,,,,SEG48,,,,QSPCLK,,USB_VBUSEN_B,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P501PFS,Port 501 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTOB0,GTIV_B,,,,,,,,,,,SEG49,,,,QSSL,,USB_OVRCURA_B,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P502PFS,Port 502 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTIW_B,,,,,,,,,,,SEG50,,,,QIO0,,USB_OVRCURB_B,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.long 0x94C++0x0B
|
|
line.long 0x00 "P503PFS,Port 5 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTETRGC_B,,,,,,,,,,,SEG51,,,,QIO1,,USB_EXICEN_B,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P504PFS,Port 504 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTETRGD_B,,,,,,,,,,,,,,,QIO2,,USB_ID_B,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P505PFS,Port 505 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,,,,,,QIO3,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.long 0x958++0x03
|
|
line.long 0x00 "P506PFS,Port 506 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))
|
|
group.long 0x95C++0x03
|
|
line.long 0x00 "P507PFS,Port 507 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.long 0x96C++0x07
|
|
line.long 0x00 "P511PFS,Port 511 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC0B_B,RXD4_B/MISO4_B/SCL4_B,,,SDA2,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P512PFS,Port 512 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC0A_B,TXD4_B/MOSI4_B/SDA4_B,,,SCL2,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
group.byte ad:0x40040D03++0x00
|
|
line.byte 0x00 "PWPR,Write-Protect Register"
|
|
bitfld.byte 0x00 7. " B0WI ,PFSWE Bit Write Disable" "No,Yes"
|
|
bitfld.byte 0x00 6. " PFSWE ,PFS Register Write Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
tree "Port 6"
|
|
base ad:0x40040000
|
|
width 9.
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "PCNTR1,Port Control Register 1"
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 30. " PODR14 ,614 Output Data" "Low,High"
|
|
bitfld.long 0x00 29. " PODR13 ,613 Output Data" "Low,High"
|
|
bitfld.long 0x00 28. " PODR12 ,612 Output Data" "Low,High"
|
|
bitfld.long 0x00 27. " PODR11 ,611 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26. " PODR10 ,610 Output Data" "Low,High"
|
|
bitfld.long 0x00 25. " PODR09 ,609 Output Data" "Low,High"
|
|
bitfld.long 0x00 24. " PODR08 ,608 Output Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 22. " PODR06 ,606 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 21. " PODR05 ,605 Output Data" "Low,High"
|
|
bitfld.long 0x00 20. " PODR04 ,604 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " PODR03 ,603 Output Data" "Low,High"
|
|
bitfld.long 0x00 18. " PODR02 ,602 Output Data" "Low,High"
|
|
bitfld.long 0x00 17. " PODR01 ,601 Output Data" "Low,High"
|
|
bitfld.long 0x00 16. " PODR00 ,600 Output Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 14. " PDR14 ,614 Direction" "Input,Output"
|
|
bitfld.long 0x00 13. " PDR13 ,613 Direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDR12 ,612 Direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDR11 ,611 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " PDR10 ,610 Direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDR09 ,609 Direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDR08 ,608 Direction" "Input,Output"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 6. " PDR06 ,606 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 5. " PDR05 ,605 Direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDR04 ,604 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " PDR03 ,603 Direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDR02 ,602 Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDR01 ,601 Direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDR00 ,600 Direction" "Input,Output"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "PCNTR2,Port Control Register 2"
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 30. " EIDR14 ,614 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 29. " EIDR13 ,613 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 28. " EIDR12 ,612 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 27. " EIDR11 ,611 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26. " EIDR10 ,610 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 25. " EIDR09 ,609 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 24. " EIDR08 ,608 Event Input Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 22. " EIDR06 ,606 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 21. " EIDR05 ,605 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 20. " EIDR04 ,604 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " EIDR03 ,603 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 18. " EIDR02 ,602 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 17. " EIDR01 ,601 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 16. " EIDR00 ,600 Event Input Data" "Low,High"
|
|
wgroup.long 0xC8++0x03
|
|
line.long 0x00 "PCNTR3,Port Control Register 3"
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 30. " PORR14 ,614 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 29. " PORR13 ,613 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 28. " PORR12 ,612 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 27. " PORR11 ,611 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26. " PORR10 ,610 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 25. " PORR09 ,609 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 24. " PORR08 ,608 Output Reset" "No affect,Low"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 22. " PORR06 ,606 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 21. " PORR05 ,605 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 20. " PORR04 ,604 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " PORR03 ,603 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 18. " PORR02 ,602 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 17. " PORR01 ,601 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 16. " PORR00 ,600 Output Reset" "No affect,Low"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 14. " POSR14 ,614 Output Set" "No affect,High"
|
|
bitfld.long 0x00 13. " POSR13 ,613 Output Set" "No affect,High"
|
|
bitfld.long 0x00 12. " POSR12 ,612 Output Set" "No affect,High"
|
|
bitfld.long 0x00 11. " POSR11 ,611 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " POSR10 ,610 Output Set" "No affect,High"
|
|
bitfld.long 0x00 9. " POSR09 ,609 Output Set" "No affect,High"
|
|
bitfld.long 0x00 8. " POSR08 ,608 Output Set" "No affect,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 6. " POSR06 ,606 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 5. " POSR05 ,605 Output Set" "No affect,High"
|
|
bitfld.long 0x00 4. " POSR04 ,604 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " POSR03 ,603 Output Set" "No affect,High"
|
|
bitfld.long 0x00 2. " POSR02 ,602 Output Set" "No affect,High"
|
|
bitfld.long 0x00 1. " POSR01 ,601 Output Set" "No affect,High"
|
|
bitfld.long 0x00 0. " POSR00 ,600 Output Set" "No affect,High"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.long 0x980++0x0F
|
|
line.long 0x00 "P600PFS,Port 600 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,RD,,SEG41,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P601PFS,Port 601 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,WR/WR0,,SEG40,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P602PFS,Port 602 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,EBCLK,,SEG39,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x0C "P603PFS,Port 603 Pin Function Select Register"
|
|
bitfld.long 0x0C 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,D13,,SEG38,?..."
|
|
bitfld.long 0x0C 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x0C 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x0C 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x0C 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x0C 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x0C 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.long 0x990++0x07
|
|
line.long 0x00 "P604PFS,Port 604 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,D12,,SEG37,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P605PFS,Port 605 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,D11,,SEG36,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))
|
|
group.long 0x998++0x03
|
|
line.long 0x00 "P606PFS,Port 606 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,,SEG35,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.long 0x9A0++0x0B
|
|
line.long 0x00 "P608PFS,Port 608 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,A00/BC0,,SEG28,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P609PFS,Port 609 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,CS1,,SEG29,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P610PFS,Port 610 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,CS0,,SEG30,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.long 0x9AC++0x0B
|
|
line.long 0x00 "P611PFS,Port 611 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,,SEG31,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P612PFS,Port 612 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,D8,,SEG32,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P613PFS,Port 613 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,D9,,SEG33,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))
|
|
group.long 0x9B8++0x03
|
|
line.long 0x00 "P614PFS,Port 614 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,D10,,SEG34,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
group.byte ad:0x40040D03++0x00
|
|
line.byte 0x00 "PWPR,Write-Protect Register"
|
|
bitfld.byte 0x00 7. " B0WI ,PFSWE Bit Write Disable" "No,Yes"
|
|
bitfld.byte 0x00 6. " PFSWE ,PFS Register Write Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port 7"
|
|
base ad:0x40040000
|
|
width 9.
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "PCNTR1,Port Control Register 1"
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 29. " PODR13 ,P713 Output Data" "Low,High"
|
|
bitfld.long 0x00 28. " PODR12 ,P712 Output Data" "Low,High"
|
|
bitfld.long 0x00 27. " PODR11 ,P711 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 26. " PODR10 ,P710 Output Data" "Low,High"
|
|
bitfld.long 0x00 25. " PODR09 ,P709 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " PODR08 ,P708 Output Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 21. " PODR05 ,P705 Output Data" "Low,High"
|
|
bitfld.long 0x00 20. " PODR04 ,P704 Output Data" "Low,High"
|
|
bitfld.long 0x00 19. " PODR03 ,P703 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 18. " PODR02 ,P702 Output Data" "Low,High"
|
|
bitfld.long 0x00 17. " PODR01 ,P701 Output Data" "Low,High"
|
|
bitfld.long 0x00 16. " PODR00 ,P700 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 13. " PDR13 ,P713 Direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDR12 ,P712 Direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDR11 ,P711 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 10. " PDR10 ,P710 Direction" "Input,Output"
|
|
bitfld.long 0x00 9. " PDR09 ,P709 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " PDR08 ,P708 Direction" "Input,Output"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 5. " PDR05 ,P705 Direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDR04 ,P704 Direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDR03 ,P703 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 2. " PDR02 ,P702 Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDR01 ,P701 Direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDR00 ,P700 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "PCNTR2,Port Control Register 2"
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 29. " EIDR13 ,P713 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 28. " EIDR12 ,P712 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 27. " EIDR11 ,P711 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 26. " EIDR10 ,P710 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 25. " EIDR09 ,P709 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " EIDR08 ,P708 Event Input Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 21. " EIDR05 ,P705 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 20. " EIDR04 ,P704 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 19. " EIDR03 ,P703 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 18. " EIDR02 ,P702 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 17. " EIDR01 ,P701 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 16. " EIDR00 ,P700 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
wgroup.long 0xE8++0x03
|
|
line.long 0x00 "PCNTR3,Port Control Register 3"
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 29. " PORR13 ,P713 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 28. " PORR12 ,P712 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 27. " PORR11 ,P711 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 26. " PORR10 ,P710 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 25. " PORR09 ,P709 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " PORR08 ,P708 Output Reset" "No affect,Low"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 21. " PORR05 ,P705 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 20. " PORR04 ,P704 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 19. " PORR03 ,P703 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 18. " PORR02 ,P702 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 17. " PORR01 ,P701 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 16. " PORR00 ,P700 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 13. " POSR13 ,P713 Output Set" "No affect,High"
|
|
bitfld.long 0x00 12. " POSR12 ,P712 Output Set" "No affect,High"
|
|
bitfld.long 0x00 11. " POSR11 ,P711 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 10. " POSR10 ,P710 Output Set" "No affect,High"
|
|
bitfld.long 0x00 9. " POSR09 ,P709 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " POSR08 ,P708 Output Set" "No affect,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 5. " POSR05 ,P705 Output Set" "No affect,High"
|
|
bitfld.long 0x00 4. " POSR04 ,P704 Output Set" "No affect,High"
|
|
bitfld.long 0x00 3. " POSR03 ,P703 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 2. " POSR02 ,P702 Output Set" "No affect,High"
|
|
bitfld.long 0x00 1. " POSR01 ,P701 Output Set" "No affect,High"
|
|
bitfld.long 0x00 0. " POSR00 ,P700 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.long 0x9C0++0x0B
|
|
line.long 0x00 "P700PFS,Port 700 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC5A_B,,,,,,,,,TS32,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P701PFS,Port 701 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC5B_B,,,,,,,,,TS33,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P702PFS,Port 702 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC6A_B,,,,,,,,,TS34,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))
|
|
group.long 0x9CC++0x0B
|
|
line.long 0x00 "P703PFS,Port 703 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC6B_B,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P704PFS,Port 704 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P705PFS,Port 705 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "P708PFS,Port 708 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,RXD1_B/MISO1_B/SCL1_B,SSLA3_B,,,,CACREF_B,,TS12,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.long 0x9E4++0x07
|
|
line.long 0x00 "P709PFS,Port 709 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,TXD1_B/MOSI1_B/SDA1_B,,,,,,,TS13,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P710PFS,Port 710 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,SCK1_B,,,,,,,TS35,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))
|
|
group.long 0x9EC++0x0B
|
|
line.long 0x00 "P711PFS,Port 711 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,CTS1_RTS1_B/SS1_B,,,,,,,,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P712PFS,Port 712 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC2B_B,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P713PFS,Port 713 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC2A_B,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
group.byte ad:0x40040D03++0x00
|
|
line.byte 0x00 "PWPR,Write-Protect Register"
|
|
bitfld.byte 0x00 7. " B0WI ,PFSWE Bit Write Disable" "No,Yes"
|
|
bitfld.byte 0x00 6. " PFSWE ,PFS Register Write Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port 8"
|
|
base ad:0x40040000
|
|
width 9.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PCNTR1,Port Control Register 1"
|
|
bitfld.long 0x00 25. " PODR09 ,P809 Output Data" "Low,High"
|
|
bitfld.long 0x00 24. " PODR08 ,P808 Output Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 23. " PODR07 ,P807 Output Data" "Low,High"
|
|
bitfld.long 0x00 22. " PODR06 ,P806 Output Data" "Low,High"
|
|
bitfld.long 0x00 21. " PODR05 ,P805 Output Data" "Low,High"
|
|
bitfld.long 0x00 20. " PODR04 ,P804 Output Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PODR03 ,P803 Output Data" "Low,High"
|
|
bitfld.long 0x00 18. " PODR02 ,P802 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 17. " PODR01 ,P801 Output Data" "Low,High"
|
|
bitfld.long 0x00 16. " PODR00 ,P800 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " PDR09 ,P809 Direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDR08 ,P808 Direction" "Input,Output"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 7. " PDR07 ,P807 Direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDR06 ,P806 Direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDR05 ,P805 Direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDR04 ,P804 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PDR03 ,P803 Direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDR02 ,P802 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 1. " PDR01 ,P801 Direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDR00 ,P800 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "PCNTR2,Port Control Register 2"
|
|
bitfld.long 0x00 25. " EIDR09 ,P809 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 24. " EIDR08 ,P808 Event Input Data" "Low,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 23. " EIDR07 ,P807 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 22. " EIDR06 ,P806 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 21. " EIDR05 ,P805 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 20. " EIDR04 ,P804 Event Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EIDR03 ,P803 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 18. " EIDR02 ,P802 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 17. " EIDR01 ,P801 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 16. " EIDR00 ,P800 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
wgroup.long 0x108++0x03
|
|
line.long 0x00 "PCNTR3,Port Control Register 3"
|
|
bitfld.long 0x00 25. " PORR09 ,P809 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 24. " PORR08 ,P808 Output Reset" "No affect,Low"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 23. " PORR07 ,P807 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 22. " PORR06 ,P806 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 21. " PORR05 ,P805 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 20. " PORR04 ,P804 Output Reset" "No affect,Low"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PORR03 ,P803 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 18. " PORR02 ,P802 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 17. " PORR01 ,P801 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 16. " PORR00 ,P800 Output Reset" "No affect,Low"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " POSR09 ,P809 Output Set" "No affect,High"
|
|
bitfld.long 0x00 8. " POSR08 ,P808 Output Set" "No affect,High"
|
|
textline " "
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 7. " POSR07 ,P807 Output Set" "No affect,High"
|
|
bitfld.long 0x00 6. " POSR06 ,P806 Output Set" "No affect,High"
|
|
bitfld.long 0x00 5. " POSR05 ,P805 Output Set" "No affect,High"
|
|
bitfld.long 0x00 4. " POSR04 ,P804 Output Set" "No affect,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POSR03 ,P803 Output Set" "No affect,High"
|
|
bitfld.long 0x00 2. " POSR02 ,P802 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.long 0x00 1. " POSR01 ,P801 Output Set" "No affect,High"
|
|
bitfld.long 0x00 0. " POSR00 ,P800 Output Set" "No affect,High"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.long 0xA00++0x07
|
|
line.long 0x00 "P800PFS,Port 800 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,D14,,SEG44,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P801PFS,Port 801 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,D15,,SEG45,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))
|
|
group.long 0xA08++0x17
|
|
line.long 0x00 "P802PFS,Port 802 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,,SEG46,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P803PFS,Port 803 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,,SEG47,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P804PFS,Port 804 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,,SEG43,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x0C "P805PFS,Port 805 Pin Function Select Register"
|
|
bitfld.long 0x0C 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,,SEG42,?..."
|
|
bitfld.long 0x0C 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x0C 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x0C 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x0C 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x0C 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x0C 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x10 "P806PFS,Port 806 Pin Function Select Register"
|
|
bitfld.long 0x10 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,,SEG26,?..."
|
|
bitfld.long 0x10 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x10 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x10 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x10 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x10 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x10 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x14 "P807PFS,Port 807 Pin Function Select Register"
|
|
bitfld.long 0x14 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,,SEG27,?..."
|
|
bitfld.long 0x14 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x14 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x14 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x14 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x14 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x14 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.long 0xA20++0x07
|
|
line.long 0x00 "P808PFS,Port 808 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,,SEG18,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P809PFS,Port 809 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,,SEG19,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
endif
|
|
group.byte ad:0x40040D03++0x00
|
|
line.byte 0x00 "PWPR,Write-Protect Register"
|
|
bitfld.byte 0x00 7. " B0WI ,PFSWE Bit Write Disable" "No,Yes"
|
|
bitfld.byte 0x00 6. " PFSWE ,PFS Register Write Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))
|
|
tree "Port 9"
|
|
base ad:0x40040000
|
|
width 9.
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "PCNTR1,Port Control Register 1"
|
|
bitfld.long 0x00 18. " PODR02 ,P902 Output Data" "Low,High"
|
|
bitfld.long 0x00 17. " PODR01 ,P901 Output Data" "Low,High"
|
|
bitfld.long 0x00 16. " PODR00 ,P900 Output Data" "Low,High"
|
|
bitfld.long 0x00 2. " PDR02 ,P902 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PDR01 ,P901 Direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDR00 ,P900 Direction" "Input,Output"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "PCNTR2,Port Control Register 2"
|
|
bitfld.long 0x00 18. " EIDR02 ,P902 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 17. " EIDR01 ,P901 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 16. " EIDR00 ,P900 Event Input Data" "Low,High"
|
|
wgroup.long 0x128++0x03
|
|
line.long 0x00 "PCNTR3,Port Control Register 3"
|
|
bitfld.long 0x00 18. " PORR02 ,P902 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 17. " PORR01 ,P901 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 16. " PORR00 ,P900 Output Reset" "No affect,Low"
|
|
bitfld.long 0x00 2. " POSR02 ,P902 Output Set" "No affect,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " POSR01 ,P901 Output Set" "No affect,High"
|
|
bitfld.long 0x00 0. " POSR00 ,P900 Output Set" "No affect,High"
|
|
group.long 0xA40++0x0B
|
|
line.long 0x00 "P900PFS,Port 900 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,,SEG6,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x04 "P901PFS,Port 901 Pin Function Select Register"
|
|
bitfld.long 0x04 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,,SEG7,?..."
|
|
bitfld.long 0x04 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x04 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x04 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x04 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x04 0. " PODR ,Port Output Data" "Low,High"
|
|
line.long 0x08 "P902PFS,Port 902 Pin Function Select Register"
|
|
bitfld.long 0x08 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,,,,,,,,,SEG8,?..."
|
|
bitfld.long 0x08 16. " PMR ,Port Mode Control" "General,Peripheral"
|
|
bitfld.long 0x08 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x08 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x08 4. " PCR ,Pull-up Control" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x08 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x08 0. " PODR ,Port Output Data" "Low,High"
|
|
group.byte ad:0x40040D03++0x00
|
|
line.byte 0x00 "PWPR,Write-Protect Register"
|
|
bitfld.byte 0x00 7. " B0WI ,PFSWE Bit Write Disable" "No,Yes"
|
|
bitfld.byte 0x00 6. " PFSWE ,PFS Register Write Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "KINT (Key Interrupt Function)"
|
|
base ad:0x40080000
|
|
width 7.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x0 "KRCTL,Key Return Control Register"
|
|
bitfld.byte 0x0 7. " KRMD ,Usage of key interrupt flags" "Not used,Used"
|
|
bitfld.byte 0x0 0. " KREG ,Detection edge selection" "Falling edge,Rising edge"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x0 "KRF,Key Return Flag Register"
|
|
bitfld.byte 0x0 7. " KRF7 ,Key interrupt flag 7" "No interrupt,Interrupt"
|
|
bitfld.byte 0x0 6. " KRF6 ,Key interrupt flag 6" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x0 5. " KRF5 ,Key interrupt flag 5" "No interrupt,Interrupt"
|
|
bitfld.byte 0x0 4. " KRF4 ,Key interrupt flag 4" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x0 3. " KRF3 ,Key interrupt flag 3" "No interrupt,Interrupt"
|
|
bitfld.byte 0x0 2. " KRF2 ,Key interrupt flag 2" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.byte 0x0 1. " KRF1 ,Key interrupt flag 1" "No interrupt,Interrupt"
|
|
bitfld.byte 0x0 0. " KRF0 ,Key interrupt flag 0" "No interrupt,Interrupt"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x0 "KRM,Key Return Mode Register"
|
|
bitfld.byte 0x0 7. " KRM7 ,Key interrupt mode control 7" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " KRM6 ,Key interrupt mode control 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x0 5. " KRM5 ,Key interrupt mode control 5" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4. " KRM4 ,Key interrupt mode control 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x0 3. " KRM3 ,Key interrupt mode control 3" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " KRM2 ,Key interrupt mode control 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x0 1. " KRM1 ,Key interrupt mode control 1" "Disabled,Enabled"
|
|
bitfld.byte 0x0 0. " KRM0 ,Key interrupt mode control 0" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "POEG (Port Output Enable for GPT)"
|
|
tree "Group A"
|
|
base ad:0x40042000
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POEGGA,POEG Group A Setting Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,Noise Filter Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/128"
|
|
bitfld.long 0x00 29. " NFEN ,Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " INV ,GTETRG$2 Input Reverse" "Not reversed,Reversed"
|
|
rbitfld.long 0x00 16. " ST ,GTETRG$2 Input Status Flag" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CDRE1 ,ACMP_HS1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CDRE0 ,ACMP_HS0 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " OSTPE ,Oscillation Stop Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IOCE ,Output-disable Request Enable from GPT or ACMPHS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PIDE ,Port Input Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSF ,Software Stop Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " OSTPF ,Oscillation Stop Detection Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " IOCF ,Output-disable Request Detection Flag from GPT or ACMPHS" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PIDF ,Port Input Detection Flag" "Not occurred,Occurred"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Group B"
|
|
base ad:0x40042100
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POEGGB,POEG Group B Setting Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,Noise Filter Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/128"
|
|
bitfld.long 0x00 29. " NFEN ,Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " INV ,GTETRG$2 Input Reverse" "Not reversed,Reversed"
|
|
rbitfld.long 0x00 16. " ST ,GTETRG$2 Input Status Flag" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CDRE1 ,ACMP_HS1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CDRE0 ,ACMP_HS0 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " OSTPE ,Oscillation Stop Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IOCE ,Output-disable Request Enable from GPT or ACMPHS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PIDE ,Port Input Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSF ,Software Stop Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " OSTPF ,Oscillation Stop Detection Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " IOCF ,Output-disable Request Detection Flag from GPT or ACMPHS" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PIDF ,Port Input Detection Flag" "Not occurred,Occurred"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Group C"
|
|
base ad:0x40042200
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POEGGC,POEG Group C Setting Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,Noise Filter Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/128"
|
|
bitfld.long 0x00 29. " NFEN ,Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " INV ,GTETRG$2 Input Reverse" "Not reversed,Reversed"
|
|
rbitfld.long 0x00 16. " ST ,GTETRG$2 Input Status Flag" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CDRE1 ,ACMP_HS1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CDRE0 ,ACMP_HS0 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " OSTPE ,Oscillation Stop Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IOCE ,Output-disable Request Enable from GPT or ACMPHS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PIDE ,Port Input Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSF ,Software Stop Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " OSTPF ,Oscillation Stop Detection Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " IOCF ,Output-disable Request Detection Flag from GPT or ACMPHS" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PIDF ,Port Input Detection Flag" "Not occurred,Occurred"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Group D"
|
|
base ad:0x40042300
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POEGGD,POEG Group D Setting Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,Noise Filter Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/128"
|
|
bitfld.long 0x00 29. " NFEN ,Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " INV ,GTETRG$2 Input Reverse" "Not reversed,Reversed"
|
|
rbitfld.long 0x00 16. " ST ,GTETRG$2 Input Status Flag" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CDRE1 ,ACMP_HS1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CDRE0 ,ACMP_HS0 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " OSTPE ,Oscillation Stop Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IOCE ,Output-disable Request Enable from GPT or ACMPHS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PIDE ,Port Input Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSF ,Software Stop Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " OSTPF ,Oscillation Stop Detection Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " IOCF ,Output-disable Request Detection Flag from GPT or ACMPHS" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PIDF ,Port Input Detection Flag" "Not occurred,Occurred"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "GPT (General PWM Timer)"
|
|
tree "Channel 0"
|
|
base ad:0x40078000
|
|
width 10.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GTWP,General PWM Timer Write-Protection Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRKEY ,GTWP Key Code"
|
|
bitfld.long 0x00 0. " WP ,Register Write Disable" "No,Yes"
|
|
line.long 0x04 "GTSTR,General PWM Timer Software Start Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x04 9. " CSTRT9 ,Counter start register 9" "No effect,Started"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " CSTRT8 ,Counter start register 8" "No effect,Started"
|
|
bitfld.long 0x04 7. " CSTRT7 ,Counter start register 7" "No effect,Started"
|
|
bitfld.long 0x04 6. " CSTRT6 ,Counter start register 6" "No effect,Started"
|
|
bitfld.long 0x04 5. " CSTRT5 ,Counter start register 5" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CSTRT4 ,Counter start register 4" "No effect,Started"
|
|
bitfld.long 0x04 3. " CSTRT3 ,Counter start register 3" "No effect,Started"
|
|
bitfld.long 0x04 2. " CSTRT2 ,Counter start register 2" "No effect,Started"
|
|
bitfld.long 0x04 1. " CSTRT1 ,Counter start register 1" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CSTRT0 ,Counter start register 0" "No effect,Started"
|
|
line.long 0x08 "GTSTP,General PWM Timer Software Stop Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x08 9. " CSTOP9 ,Counter stop register 9" "No effect,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 8. " CSTOP8 ,Counter stop register 8" "No effect,Stopped"
|
|
bitfld.long 0x08 7. " CSTOP7 ,Counter stop register 7" "No effect,Stopped"
|
|
bitfld.long 0x08 6. " CSTOP6 ,Counter stop register 6" "No effect,Stopped"
|
|
bitfld.long 0x08 5. " CSTOP5 ,Counter stop register 5" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSTOP4 ,Counter stop register 4" "No effect,Stopped"
|
|
bitfld.long 0x08 3. " CSTOP3 ,Counter stop register 3" "No effect,Stopped"
|
|
bitfld.long 0x08 2. " CSTOP2 ,Counter stop register 2" "No effect,Stopped"
|
|
bitfld.long 0x08 1. " CSTOP1 ,Counter stop register 1" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSTOP0 ,Counter stop register 0" "No effect,Stopped"
|
|
line.long 0x0C "GTCLR,General PWM Timer Software Clear Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x0C 9. " CCLR9 ,Counter clear register 9" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 8. " CCLR8 ,Counter clear register 8" "No effect,Clear"
|
|
bitfld.long 0x0C 7. " CCLR7 ,Counter clear register 7" "No effect,Clear"
|
|
bitfld.long 0x0C 6. " CCLR6 ,Counter clear register 6" "No effect,Clear"
|
|
bitfld.long 0x0C 5. " CCLR5 ,Counter clear register 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CCLR4 ,Counter clear register 4" "No effect,Clear"
|
|
bitfld.long 0x0C 3. " CCLR3 ,Counter clear register 3" "No effect,Clear"
|
|
bitfld.long 0x0C 2. " CCLR2 ,Counter clear register 2" "No effect,Clear"
|
|
bitfld.long 0x0C 1. " CCLR1 ,Counter clear register 1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CCLR0 ,Counter clear register 0" "No effect,Clear"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SSELCH ,ELCH Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " SSELCG ,ELCG Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SSELCF ,ELCF Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SSELCE ,ELCE Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SSGTRGDF ,GTETRGD Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SSGTRGDR ,GTETRGD Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SSGTRGCF ,GTETRGC Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SSGTRGCR ,GTETRGC Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x04 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " PSELCH ,ELCH Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " PSELCG ,ELCG Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " PSELCF ,ELCF Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " PSELCE ,ELCE Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PSGTRGDF ,GTETRGD Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " PSGTRGDR ,GTETRGD Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " PSGTRGCF ,GTETRGC Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PSGTRGCR ,GTETRGC Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
line.long 0x08 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x08 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " CSELCH ,ELCH Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " CSELCG ,ELCG Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " CSELCF ,ELCF Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " CSELCE ,ELCE Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " CSGTRGDF ,GTETRGD Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " CSGTRGDR ,GTETRGD Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " CSGTRGCF ,GTETRGC Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSGTRGCR ,GTETRGC Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
line.long 0x0C "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x0C 23. " USELCH ,ELCH Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " USELCG ,ELCG Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " USELCF ,ELCF Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " USELCE ,ELCE Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " USGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " USGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " USGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " USGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x10 23. " DSELCH ,ELCH Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " DSELCG ,ELCG Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " DSELCF ,ELCF Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " DSELCE ,ELCE Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DSGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " DSGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " DSGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DSGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 23. " ASELCH ,ELCH Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ASELCG ,ELCG Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ASELCF ,ELCF Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ASELCE ,ELCE Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASGTRGDF ,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ASGTRGDR ,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASGTRGCF ,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ASGTRGCR ,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 23. " BSELCH ,ELCH Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " BSELCG ,ELCG Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BSELCF ,ELCF Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " BSELCE ,ELCE Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BSGTRGDF ,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BSGTRGDR ,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BSGTRGCF ,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BSGTRGCR ,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "/1,/4,/16,/64,/256,/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM mode,Saw-wave one-shot pulse mode,,,Triangle-wave PWM mode 1,Triangle-wave PWM mode 2,Triangle-wave PWM mode 3,"
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Not stopped"
|
|
line.long 0x04 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x04 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
bitfld.long 0x04 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 1. " UDF ,Forcible Count Direction Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 0. " UD ,Count Direction Setting" "Down,Up"
|
|
line.long 0x08 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x08 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "/1,/4,/16,/64"
|
|
bitfld.long 0x08 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x08 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 16.--20. " GTIOB ,Initial Output/Output At Cycle End/Output At GTCCRB Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
bitfld.long 0x08 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "/1,/4,/16,/64"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x08 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 0.--4. " GTIOA ,Initial Output/Output At Cycle End/Output At GTCCRA Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
line.long 0x0C "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x0C 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,Group C,Group D"
|
|
line.long 0x10 "GTST,General PWM Timer Status Register"
|
|
rbitfld.long 0x10 30. " OABLF ,Same Time Output Level Low Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 29. " OABHF ,Same Time Output Level High Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 24. " ODF ,Output Disable Flag" "Not requested,Requested"
|
|
rbitfld.long 0x10 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x10 7. " TCFPU ,Underflow Flag" "No underflow,Underflow"
|
|
bitfld.long 0x10 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x10 5. " TCFF ,Input Compare Match Flag F" "Not generated,Generated"
|
|
bitfld.long 0x10 4. " TCFE ,Input Compare Match Flag E" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x10 3. " TCFD ,Input Compare Match Flag D" "Not generated,Generated"
|
|
bitfld.long 0x10 2. " TCFC ,Input Compare Match Flag C" "Not generated,Generated"
|
|
bitfld.long 0x10 1. " TCFB ,Input Capture/Compare Match Flag B" "Not generated,Generated"
|
|
bitfld.long 0x10 0. " TCFA ,Input Capture/Compare Match Flag A" "Not generated,Generated"
|
|
line.long 0x14 "GTBER,General PWM Timer Buffer Enable Register"
|
|
bitfld.long 0x14 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not performed,Performed"
|
|
bitfld.long 0x14 20.--21. " PR ,GTPR Buffer Operation" "No buffer,Single buffer,,"
|
|
bitfld.long 0x14 18.--19. " CCRB ,GTCCRB Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
bitfld.long 0x14 16.--17. " CCRA ,GTCCRA Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
textline " "
|
|
bitfld.long 0x14 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x14 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "GTCCRE,General PWM Timer Compare Capture Register E"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "GTCCRD,General PWM Timer Compare Capture Register D"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "GTCCRF,General PWM Timer Compare Capture Register F"
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
line.long 0x04 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
group.long 0x88++0x07
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Without using GTDVU,GTDVU sets the compare match value"
|
|
line.long 0x04 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
if (((per.l(ad:0x40078FF0))&0x10000)==0x0)
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
else
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
bitfld.long 0x00 2. " WF ,Input W-Phase Soft Setting" "0,1"
|
|
bitfld.long 0x00 1. " VF ,Input V-Phase Soft Setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UF ,Input U-Phase Soft Setting" "0,1"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0x40078100
|
|
width 10.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GTWP,General PWM Timer Write-Protection Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRKEY ,GTWP Key Code"
|
|
bitfld.long 0x00 0. " WP ,Register Write Disable" "No,Yes"
|
|
line.long 0x04 "GTSTR,General PWM Timer Software Start Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x04 9. " CSTRT9 ,Counter start register 9" "No effect,Started"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " CSTRT8 ,Counter start register 8" "No effect,Started"
|
|
bitfld.long 0x04 7. " CSTRT7 ,Counter start register 7" "No effect,Started"
|
|
bitfld.long 0x04 6. " CSTRT6 ,Counter start register 6" "No effect,Started"
|
|
bitfld.long 0x04 5. " CSTRT5 ,Counter start register 5" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CSTRT4 ,Counter start register 4" "No effect,Started"
|
|
bitfld.long 0x04 3. " CSTRT3 ,Counter start register 3" "No effect,Started"
|
|
bitfld.long 0x04 2. " CSTRT2 ,Counter start register 2" "No effect,Started"
|
|
bitfld.long 0x04 1. " CSTRT1 ,Counter start register 1" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CSTRT0 ,Counter start register 0" "No effect,Started"
|
|
line.long 0x08 "GTSTP,General PWM Timer Software Stop Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x08 9. " CSTOP9 ,Counter stop register 9" "No effect,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 8. " CSTOP8 ,Counter stop register 8" "No effect,Stopped"
|
|
bitfld.long 0x08 7. " CSTOP7 ,Counter stop register 7" "No effect,Stopped"
|
|
bitfld.long 0x08 6. " CSTOP6 ,Counter stop register 6" "No effect,Stopped"
|
|
bitfld.long 0x08 5. " CSTOP5 ,Counter stop register 5" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSTOP4 ,Counter stop register 4" "No effect,Stopped"
|
|
bitfld.long 0x08 3. " CSTOP3 ,Counter stop register 3" "No effect,Stopped"
|
|
bitfld.long 0x08 2. " CSTOP2 ,Counter stop register 2" "No effect,Stopped"
|
|
bitfld.long 0x08 1. " CSTOP1 ,Counter stop register 1" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSTOP0 ,Counter stop register 0" "No effect,Stopped"
|
|
line.long 0x0C "GTCLR,General PWM Timer Software Clear Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x0C 9. " CCLR9 ,Counter clear register 9" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 8. " CCLR8 ,Counter clear register 8" "No effect,Clear"
|
|
bitfld.long 0x0C 7. " CCLR7 ,Counter clear register 7" "No effect,Clear"
|
|
bitfld.long 0x0C 6. " CCLR6 ,Counter clear register 6" "No effect,Clear"
|
|
bitfld.long 0x0C 5. " CCLR5 ,Counter clear register 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CCLR4 ,Counter clear register 4" "No effect,Clear"
|
|
bitfld.long 0x0C 3. " CCLR3 ,Counter clear register 3" "No effect,Clear"
|
|
bitfld.long 0x0C 2. " CCLR2 ,Counter clear register 2" "No effect,Clear"
|
|
bitfld.long 0x0C 1. " CCLR1 ,Counter clear register 1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CCLR0 ,Counter clear register 0" "No effect,Clear"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SSELCH ,ELCH Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " SSELCG ,ELCG Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SSELCF ,ELCF Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SSELCE ,ELCE Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SSGTRGDF ,GTETRGD Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SSGTRGDR ,GTETRGD Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SSGTRGCF ,GTETRGC Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SSGTRGCR ,GTETRGC Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x04 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " PSELCH ,ELCH Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " PSELCG ,ELCG Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " PSELCF ,ELCF Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " PSELCE ,ELCE Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PSGTRGDF ,GTETRGD Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " PSGTRGDR ,GTETRGD Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " PSGTRGCF ,GTETRGC Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PSGTRGCR ,GTETRGC Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
line.long 0x08 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x08 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " CSELCH ,ELCH Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " CSELCG ,ELCG Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " CSELCF ,ELCF Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " CSELCE ,ELCE Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " CSGTRGDF ,GTETRGD Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " CSGTRGDR ,GTETRGD Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " CSGTRGCF ,GTETRGC Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSGTRGCR ,GTETRGC Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
line.long 0x0C "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x0C 23. " USELCH ,ELCH Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " USELCG ,ELCG Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " USELCF ,ELCF Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " USELCE ,ELCE Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " USGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " USGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " USGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " USGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x10 23. " DSELCH ,ELCH Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " DSELCG ,ELCG Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " DSELCF ,ELCF Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " DSELCE ,ELCE Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DSGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " DSGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " DSGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DSGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 23. " ASELCH ,ELCH Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ASELCG ,ELCG Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ASELCF ,ELCF Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ASELCE ,ELCE Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASGTRGDF ,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ASGTRGDR ,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASGTRGCF ,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ASGTRGCR ,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 23. " BSELCH ,ELCH Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " BSELCG ,ELCG Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BSELCF ,ELCF Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " BSELCE ,ELCE Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BSGTRGDF ,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BSGTRGDR ,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BSGTRGCF ,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BSGTRGCR ,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "/1,/4,/16,/64,/256,/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM mode,Saw-wave one-shot pulse mode,,,Triangle-wave PWM mode 1,Triangle-wave PWM mode 2,Triangle-wave PWM mode 3,"
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Not stopped"
|
|
line.long 0x04 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x04 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
bitfld.long 0x04 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 1. " UDF ,Forcible Count Direction Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 0. " UD ,Count Direction Setting" "Down,Up"
|
|
line.long 0x08 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x08 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "/1,/4,/16,/64"
|
|
bitfld.long 0x08 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x08 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 16.--20. " GTIOB ,Initial Output/Output At Cycle End/Output At GTCCRB Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
bitfld.long 0x08 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "/1,/4,/16,/64"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x08 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 0.--4. " GTIOA ,Initial Output/Output At Cycle End/Output At GTCCRA Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
line.long 0x0C "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x0C 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,Group C,Group D"
|
|
line.long 0x10 "GTST,General PWM Timer Status Register"
|
|
rbitfld.long 0x10 30. " OABLF ,Same Time Output Level Low Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 29. " OABHF ,Same Time Output Level High Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 24. " ODF ,Output Disable Flag" "Not requested,Requested"
|
|
rbitfld.long 0x10 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x10 7. " TCFPU ,Underflow Flag" "No underflow,Underflow"
|
|
bitfld.long 0x10 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x10 5. " TCFF ,Input Compare Match Flag F" "Not generated,Generated"
|
|
bitfld.long 0x10 4. " TCFE ,Input Compare Match Flag E" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x10 3. " TCFD ,Input Compare Match Flag D" "Not generated,Generated"
|
|
bitfld.long 0x10 2. " TCFC ,Input Compare Match Flag C" "Not generated,Generated"
|
|
bitfld.long 0x10 1. " TCFB ,Input Capture/Compare Match Flag B" "Not generated,Generated"
|
|
bitfld.long 0x10 0. " TCFA ,Input Capture/Compare Match Flag A" "Not generated,Generated"
|
|
line.long 0x14 "GTBER,General PWM Timer Buffer Enable Register"
|
|
bitfld.long 0x14 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not performed,Performed"
|
|
bitfld.long 0x14 20.--21. " PR ,GTPR Buffer Operation" "No buffer,Single buffer,,"
|
|
bitfld.long 0x14 18.--19. " CCRB ,GTCCRB Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
bitfld.long 0x14 16.--17. " CCRA ,GTCCRA Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
textline " "
|
|
bitfld.long 0x14 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x14 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "GTCCRE,General PWM Timer Compare Capture Register E"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "GTCCRD,General PWM Timer Compare Capture Register D"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "GTCCRF,General PWM Timer Compare Capture Register F"
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
line.long 0x04 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
group.long 0x88++0x07
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Without using GTDVU,GTDVU sets the compare match value"
|
|
line.long 0x04 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
if (((per.l(ad:0x40078FF0))&0x10000)==0x0)
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
else
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
bitfld.long 0x00 2. " WF ,Input W-Phase Soft Setting" "0,1"
|
|
bitfld.long 0x00 1. " VF ,Input V-Phase Soft Setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UF ,Input U-Phase Soft Setting" "0,1"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0x40078200
|
|
width 10.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GTWP,General PWM Timer Write-Protection Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRKEY ,GTWP Key Code"
|
|
bitfld.long 0x00 0. " WP ,Register Write Disable" "No,Yes"
|
|
line.long 0x04 "GTSTR,General PWM Timer Software Start Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x04 9. " CSTRT9 ,Counter start register 9" "No effect,Started"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " CSTRT8 ,Counter start register 8" "No effect,Started"
|
|
bitfld.long 0x04 7. " CSTRT7 ,Counter start register 7" "No effect,Started"
|
|
bitfld.long 0x04 6. " CSTRT6 ,Counter start register 6" "No effect,Started"
|
|
bitfld.long 0x04 5. " CSTRT5 ,Counter start register 5" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CSTRT4 ,Counter start register 4" "No effect,Started"
|
|
bitfld.long 0x04 3. " CSTRT3 ,Counter start register 3" "No effect,Started"
|
|
bitfld.long 0x04 2. " CSTRT2 ,Counter start register 2" "No effect,Started"
|
|
bitfld.long 0x04 1. " CSTRT1 ,Counter start register 1" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CSTRT0 ,Counter start register 0" "No effect,Started"
|
|
line.long 0x08 "GTSTP,General PWM Timer Software Stop Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x08 9. " CSTOP9 ,Counter stop register 9" "No effect,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 8. " CSTOP8 ,Counter stop register 8" "No effect,Stopped"
|
|
bitfld.long 0x08 7. " CSTOP7 ,Counter stop register 7" "No effect,Stopped"
|
|
bitfld.long 0x08 6. " CSTOP6 ,Counter stop register 6" "No effect,Stopped"
|
|
bitfld.long 0x08 5. " CSTOP5 ,Counter stop register 5" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSTOP4 ,Counter stop register 4" "No effect,Stopped"
|
|
bitfld.long 0x08 3. " CSTOP3 ,Counter stop register 3" "No effect,Stopped"
|
|
bitfld.long 0x08 2. " CSTOP2 ,Counter stop register 2" "No effect,Stopped"
|
|
bitfld.long 0x08 1. " CSTOP1 ,Counter stop register 1" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSTOP0 ,Counter stop register 0" "No effect,Stopped"
|
|
line.long 0x0C "GTCLR,General PWM Timer Software Clear Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x0C 9. " CCLR9 ,Counter clear register 9" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 8. " CCLR8 ,Counter clear register 8" "No effect,Clear"
|
|
bitfld.long 0x0C 7. " CCLR7 ,Counter clear register 7" "No effect,Clear"
|
|
bitfld.long 0x0C 6. " CCLR6 ,Counter clear register 6" "No effect,Clear"
|
|
bitfld.long 0x0C 5. " CCLR5 ,Counter clear register 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CCLR4 ,Counter clear register 4" "No effect,Clear"
|
|
bitfld.long 0x0C 3. " CCLR3 ,Counter clear register 3" "No effect,Clear"
|
|
bitfld.long 0x0C 2. " CCLR2 ,Counter clear register 2" "No effect,Clear"
|
|
bitfld.long 0x0C 1. " CCLR1 ,Counter clear register 1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CCLR0 ,Counter clear register 0" "No effect,Clear"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SSELCH ,ELCH Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " SSELCG ,ELCG Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SSELCF ,ELCF Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SSELCE ,ELCE Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SSGTRGDF ,GTETRGD Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SSGTRGDR ,GTETRGD Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SSGTRGCF ,GTETRGC Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SSGTRGCR ,GTETRGC Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x04 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " PSELCH ,ELCH Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " PSELCG ,ELCG Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " PSELCF ,ELCF Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " PSELCE ,ELCE Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PSGTRGDF ,GTETRGD Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " PSGTRGDR ,GTETRGD Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " PSGTRGCF ,GTETRGC Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PSGTRGCR ,GTETRGC Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
line.long 0x08 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x08 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " CSELCH ,ELCH Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " CSELCG ,ELCG Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " CSELCF ,ELCF Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " CSELCE ,ELCE Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " CSGTRGDF ,GTETRGD Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " CSGTRGDR ,GTETRGD Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " CSGTRGCF ,GTETRGC Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSGTRGCR ,GTETRGC Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
line.long 0x0C "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x0C 23. " USELCH ,ELCH Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " USELCG ,ELCG Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " USELCF ,ELCF Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " USELCE ,ELCE Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " USGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " USGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " USGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " USGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x10 23. " DSELCH ,ELCH Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " DSELCG ,ELCG Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " DSELCF ,ELCF Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " DSELCE ,ELCE Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DSGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " DSGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " DSGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DSGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 23. " ASELCH ,ELCH Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ASELCG ,ELCG Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ASELCF ,ELCF Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ASELCE ,ELCE Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASGTRGDF ,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ASGTRGDR ,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASGTRGCF ,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ASGTRGCR ,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 23. " BSELCH ,ELCH Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " BSELCG ,ELCG Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BSELCF ,ELCF Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " BSELCE ,ELCE Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BSGTRGDF ,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BSGTRGDR ,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BSGTRGCF ,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BSGTRGCR ,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "/1,/4,/16,/64,/256,/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM mode,Saw-wave one-shot pulse mode,,,Triangle-wave PWM mode 1,Triangle-wave PWM mode 2,Triangle-wave PWM mode 3,"
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Not stopped"
|
|
line.long 0x04 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x04 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
bitfld.long 0x04 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 1. " UDF ,Forcible Count Direction Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 0. " UD ,Count Direction Setting" "Down,Up"
|
|
line.long 0x08 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x08 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "/1,/4,/16,/64"
|
|
bitfld.long 0x08 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x08 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 16.--20. " GTIOB ,Initial Output/Output At Cycle End/Output At GTCCRB Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
bitfld.long 0x08 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "/1,/4,/16,/64"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x08 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 0.--4. " GTIOA ,Initial Output/Output At Cycle End/Output At GTCCRA Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
line.long 0x0C "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x0C 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,Group C,Group D"
|
|
line.long 0x10 "GTST,General PWM Timer Status Register"
|
|
rbitfld.long 0x10 30. " OABLF ,Same Time Output Level Low Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 29. " OABHF ,Same Time Output Level High Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 24. " ODF ,Output Disable Flag" "Not requested,Requested"
|
|
rbitfld.long 0x10 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x10 7. " TCFPU ,Underflow Flag" "No underflow,Underflow"
|
|
bitfld.long 0x10 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x10 5. " TCFF ,Input Compare Match Flag F" "Not generated,Generated"
|
|
bitfld.long 0x10 4. " TCFE ,Input Compare Match Flag E" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x10 3. " TCFD ,Input Compare Match Flag D" "Not generated,Generated"
|
|
bitfld.long 0x10 2. " TCFC ,Input Compare Match Flag C" "Not generated,Generated"
|
|
bitfld.long 0x10 1. " TCFB ,Input Capture/Compare Match Flag B" "Not generated,Generated"
|
|
bitfld.long 0x10 0. " TCFA ,Input Capture/Compare Match Flag A" "Not generated,Generated"
|
|
line.long 0x14 "GTBER,General PWM Timer Buffer Enable Register"
|
|
bitfld.long 0x14 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not performed,Performed"
|
|
bitfld.long 0x14 20.--21. " PR ,GTPR Buffer Operation" "No buffer,Single buffer,,"
|
|
bitfld.long 0x14 18.--19. " CCRB ,GTCCRB Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
bitfld.long 0x14 16.--17. " CCRA ,GTCCRA Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
textline " "
|
|
bitfld.long 0x14 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x14 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "GTCCRE,General PWM Timer Compare Capture Register E"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "GTCCRD,General PWM Timer Compare Capture Register D"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "GTCCRF,General PWM Timer Compare Capture Register F"
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
line.long 0x04 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
group.long 0x88++0x07
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Without using GTDVU,GTDVU sets the compare match value"
|
|
line.long 0x04 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
if (((per.l(ad:0x40078FF0))&0x10000)==0x0)
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
else
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
bitfld.long 0x00 2. " WF ,Input W-Phase Soft Setting" "0,1"
|
|
bitfld.long 0x00 1. " VF ,Input V-Phase Soft Setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UF ,Input U-Phase Soft Setting" "0,1"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 3"
|
|
base ad:0x40078300
|
|
width 10.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GTWP,General PWM Timer Write-Protection Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRKEY ,GTWP Key Code"
|
|
bitfld.long 0x00 0. " WP ,Register Write Disable" "No,Yes"
|
|
line.long 0x04 "GTSTR,General PWM Timer Software Start Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x04 9. " CSTRT9 ,Counter start register 9" "No effect,Started"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " CSTRT8 ,Counter start register 8" "No effect,Started"
|
|
bitfld.long 0x04 7. " CSTRT7 ,Counter start register 7" "No effect,Started"
|
|
bitfld.long 0x04 6. " CSTRT6 ,Counter start register 6" "No effect,Started"
|
|
bitfld.long 0x04 5. " CSTRT5 ,Counter start register 5" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CSTRT4 ,Counter start register 4" "No effect,Started"
|
|
bitfld.long 0x04 3. " CSTRT3 ,Counter start register 3" "No effect,Started"
|
|
bitfld.long 0x04 2. " CSTRT2 ,Counter start register 2" "No effect,Started"
|
|
bitfld.long 0x04 1. " CSTRT1 ,Counter start register 1" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CSTRT0 ,Counter start register 0" "No effect,Started"
|
|
line.long 0x08 "GTSTP,General PWM Timer Software Stop Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x08 9. " CSTOP9 ,Counter stop register 9" "No effect,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 8. " CSTOP8 ,Counter stop register 8" "No effect,Stopped"
|
|
bitfld.long 0x08 7. " CSTOP7 ,Counter stop register 7" "No effect,Stopped"
|
|
bitfld.long 0x08 6. " CSTOP6 ,Counter stop register 6" "No effect,Stopped"
|
|
bitfld.long 0x08 5. " CSTOP5 ,Counter stop register 5" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSTOP4 ,Counter stop register 4" "No effect,Stopped"
|
|
bitfld.long 0x08 3. " CSTOP3 ,Counter stop register 3" "No effect,Stopped"
|
|
bitfld.long 0x08 2. " CSTOP2 ,Counter stop register 2" "No effect,Stopped"
|
|
bitfld.long 0x08 1. " CSTOP1 ,Counter stop register 1" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSTOP0 ,Counter stop register 0" "No effect,Stopped"
|
|
line.long 0x0C "GTCLR,General PWM Timer Software Clear Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x0C 9. " CCLR9 ,Counter clear register 9" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 8. " CCLR8 ,Counter clear register 8" "No effect,Clear"
|
|
bitfld.long 0x0C 7. " CCLR7 ,Counter clear register 7" "No effect,Clear"
|
|
bitfld.long 0x0C 6. " CCLR6 ,Counter clear register 6" "No effect,Clear"
|
|
bitfld.long 0x0C 5. " CCLR5 ,Counter clear register 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CCLR4 ,Counter clear register 4" "No effect,Clear"
|
|
bitfld.long 0x0C 3. " CCLR3 ,Counter clear register 3" "No effect,Clear"
|
|
bitfld.long 0x0C 2. " CCLR2 ,Counter clear register 2" "No effect,Clear"
|
|
bitfld.long 0x0C 1. " CCLR1 ,Counter clear register 1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CCLR0 ,Counter clear register 0" "No effect,Clear"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SSELCH ,ELCH Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " SSELCG ,ELCG Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SSELCF ,ELCF Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SSELCE ,ELCE Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SSGTRGDF ,GTETRGD Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SSGTRGDR ,GTETRGD Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SSGTRGCF ,GTETRGC Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SSGTRGCR ,GTETRGC Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x04 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " PSELCH ,ELCH Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " PSELCG ,ELCG Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " PSELCF ,ELCF Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " PSELCE ,ELCE Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PSGTRGDF ,GTETRGD Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " PSGTRGDR ,GTETRGD Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " PSGTRGCF ,GTETRGC Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PSGTRGCR ,GTETRGC Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
line.long 0x08 "GTCSR,General PWM Timer Clear Source Select Register"
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|
bitfld.long 0x08 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
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|
bitfld.long 0x08 23. " CSELCH ,ELCH Event Source Counter Clear Enable" "Disabled,Enabled"
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|
bitfld.long 0x08 22. " CSELCG ,ELCG Event Source Counter Clear Enable" "Disabled,Enabled"
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|
bitfld.long 0x08 21. " CSELCF ,ELCF Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " CSELCE ,ELCE Event Source Counter Clear Enable" "Disabled,Enabled"
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|
bitfld.long 0x08 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
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|
bitfld.long 0x08 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
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|
bitfld.long 0x08 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
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|
bitfld.long 0x08 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
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|
bitfld.long 0x08 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
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|
bitfld.long 0x08 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
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|
bitfld.long 0x08 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
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|
bitfld.long 0x08 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
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|
bitfld.long 0x08 9. " CSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x08 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
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|
bitfld.long 0x08 7. " CSGTRGDF ,GTETRGD Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
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|
bitfld.long 0x08 6. " CSGTRGDR ,GTETRGD Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
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|
bitfld.long 0x08 5. " CSGTRGCF ,GTETRGC Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x08 4. " CSGTRGCR ,GTETRGC Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
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|
bitfld.long 0x08 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
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|
bitfld.long 0x08 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
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|
bitfld.long 0x08 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x08 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
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|
line.long 0x0C "GTUPSR,General PWM Timer Up Count Source Select Register"
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|
bitfld.long 0x0C 23. " USELCH ,ELCH Event Source Counter Count Up Enable" "Disabled,Enabled"
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|
bitfld.long 0x0C 22. " USELCG ,ELCG Event Source Counter Count Up Enable" "Disabled,Enabled"
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|
bitfld.long 0x0C 21. " USELCF ,ELCF Event Source Counter Count Up Enable" "Disabled,Enabled"
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|
bitfld.long 0x0C 20. " USELCE ,ELCE Event Source Counter Count Up Enable" "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x0C 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
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|
bitfld.long 0x0C 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
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|
bitfld.long 0x0C 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
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|
bitfld.long 0x0C 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x0C 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
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|
bitfld.long 0x0C 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
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|
bitfld.long 0x0C 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
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|
bitfld.long 0x0C 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x0C 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
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|
bitfld.long 0x0C 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
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|
bitfld.long 0x0C 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
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|
bitfld.long 0x0C 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x0C 7. " USGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
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|
bitfld.long 0x0C 6. " USGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " USGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " USGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
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|
line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
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|
bitfld.long 0x10 23. " DSELCH ,ELCH Event Source Counter Count Down Enable" "Disabled,Enabled"
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|
bitfld.long 0x10 22. " DSELCG ,ELCG Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " DSELCF ,ELCF Event Source Counter Count Down Enable" "Disabled,Enabled"
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|
bitfld.long 0x10 20. " DSELCE ,ELCE Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
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|
bitfld.long 0x10 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
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|
bitfld.long 0x10 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
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|
bitfld.long 0x10 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
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|
bitfld.long 0x10 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x10 7. " DSGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " DSGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " DSGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DSGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 23. " ASELCH ,ELCH Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ASELCG ,ELCG Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ASELCF ,ELCF Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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|
bitfld.long 0x00 20. " ASELCE ,ELCE Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASGTRGDF ,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ASGTRGDR ,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASGTRGCF ,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ASGTRGCR ,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
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bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
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group.long 0x28++0x03
|
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line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
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bitfld.long 0x00 23. " BSELCH ,ELCH Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " BSELCG ,ELCG Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BSELCF ,ELCF Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " BSELCE ,ELCE Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BSGTRGDF ,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BSGTRGDR ,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BSGTRGCF ,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BSGTRGCR ,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "/1,/4,/16,/64,/256,/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM mode,Saw-wave one-shot pulse mode,,,Triangle-wave PWM mode 1,Triangle-wave PWM mode 2,Triangle-wave PWM mode 3,"
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Not stopped"
|
|
line.long 0x04 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x04 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
bitfld.long 0x04 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 1. " UDF ,Forcible Count Direction Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 0. " UD ,Count Direction Setting" "Down,Up"
|
|
line.long 0x08 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x08 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "/1,/4,/16,/64"
|
|
bitfld.long 0x08 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x08 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 16.--20. " GTIOB ,Initial Output/Output At Cycle End/Output At GTCCRB Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
bitfld.long 0x08 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "/1,/4,/16,/64"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x08 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 0.--4. " GTIOA ,Initial Output/Output At Cycle End/Output At GTCCRA Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
line.long 0x0C "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x0C 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,Group C,Group D"
|
|
line.long 0x10 "GTST,General PWM Timer Status Register"
|
|
rbitfld.long 0x10 30. " OABLF ,Same Time Output Level Low Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 29. " OABHF ,Same Time Output Level High Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 24. " ODF ,Output Disable Flag" "Not requested,Requested"
|
|
rbitfld.long 0x10 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x10 7. " TCFPU ,Underflow Flag" "No underflow,Underflow"
|
|
bitfld.long 0x10 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x10 5. " TCFF ,Input Compare Match Flag F" "Not generated,Generated"
|
|
bitfld.long 0x10 4. " TCFE ,Input Compare Match Flag E" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x10 3. " TCFD ,Input Compare Match Flag D" "Not generated,Generated"
|
|
bitfld.long 0x10 2. " TCFC ,Input Compare Match Flag C" "Not generated,Generated"
|
|
bitfld.long 0x10 1. " TCFB ,Input Capture/Compare Match Flag B" "Not generated,Generated"
|
|
bitfld.long 0x10 0. " TCFA ,Input Capture/Compare Match Flag A" "Not generated,Generated"
|
|
line.long 0x14 "GTBER,General PWM Timer Buffer Enable Register"
|
|
bitfld.long 0x14 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not performed,Performed"
|
|
bitfld.long 0x14 20.--21. " PR ,GTPR Buffer Operation" "No buffer,Single buffer,,"
|
|
bitfld.long 0x14 18.--19. " CCRB ,GTCCRB Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
bitfld.long 0x14 16.--17. " CCRA ,GTCCRA Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
textline " "
|
|
bitfld.long 0x14 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x14 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "GTCCRE,General PWM Timer Compare Capture Register E"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "GTCCRD,General PWM Timer Compare Capture Register D"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "GTCCRF,General PWM Timer Compare Capture Register F"
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
line.long 0x04 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
group.long 0x88++0x07
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Without using GTDVU,GTDVU sets the compare match value"
|
|
line.long 0x04 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
if (((per.l(ad:0x40078FF0))&0x10000)==0x0)
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
else
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
bitfld.long 0x00 2. " WF ,Input W-Phase Soft Setting" "0,1"
|
|
bitfld.long 0x00 1. " VF ,Input V-Phase Soft Setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UF ,Input U-Phase Soft Setting" "0,1"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 4"
|
|
base ad:0x40078400
|
|
width 10.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GTWP,General PWM Timer Write-Protection Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRKEY ,GTWP Key Code"
|
|
bitfld.long 0x00 0. " WP ,Register Write Disable" "No,Yes"
|
|
line.long 0x04 "GTSTR,General PWM Timer Software Start Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x04 9. " CSTRT9 ,Counter start register 9" "No effect,Started"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " CSTRT8 ,Counter start register 8" "No effect,Started"
|
|
bitfld.long 0x04 7. " CSTRT7 ,Counter start register 7" "No effect,Started"
|
|
bitfld.long 0x04 6. " CSTRT6 ,Counter start register 6" "No effect,Started"
|
|
bitfld.long 0x04 5. " CSTRT5 ,Counter start register 5" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CSTRT4 ,Counter start register 4" "No effect,Started"
|
|
bitfld.long 0x04 3. " CSTRT3 ,Counter start register 3" "No effect,Started"
|
|
bitfld.long 0x04 2. " CSTRT2 ,Counter start register 2" "No effect,Started"
|
|
bitfld.long 0x04 1. " CSTRT1 ,Counter start register 1" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CSTRT0 ,Counter start register 0" "No effect,Started"
|
|
line.long 0x08 "GTSTP,General PWM Timer Software Stop Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x08 9. " CSTOP9 ,Counter stop register 9" "No effect,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 8. " CSTOP8 ,Counter stop register 8" "No effect,Stopped"
|
|
bitfld.long 0x08 7. " CSTOP7 ,Counter stop register 7" "No effect,Stopped"
|
|
bitfld.long 0x08 6. " CSTOP6 ,Counter stop register 6" "No effect,Stopped"
|
|
bitfld.long 0x08 5. " CSTOP5 ,Counter stop register 5" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSTOP4 ,Counter stop register 4" "No effect,Stopped"
|
|
bitfld.long 0x08 3. " CSTOP3 ,Counter stop register 3" "No effect,Stopped"
|
|
bitfld.long 0x08 2. " CSTOP2 ,Counter stop register 2" "No effect,Stopped"
|
|
bitfld.long 0x08 1. " CSTOP1 ,Counter stop register 1" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSTOP0 ,Counter stop register 0" "No effect,Stopped"
|
|
line.long 0x0C "GTCLR,General PWM Timer Software Clear Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x0C 9. " CCLR9 ,Counter clear register 9" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 8. " CCLR8 ,Counter clear register 8" "No effect,Clear"
|
|
bitfld.long 0x0C 7. " CCLR7 ,Counter clear register 7" "No effect,Clear"
|
|
bitfld.long 0x0C 6. " CCLR6 ,Counter clear register 6" "No effect,Clear"
|
|
bitfld.long 0x0C 5. " CCLR5 ,Counter clear register 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CCLR4 ,Counter clear register 4" "No effect,Clear"
|
|
bitfld.long 0x0C 3. " CCLR3 ,Counter clear register 3" "No effect,Clear"
|
|
bitfld.long 0x0C 2. " CCLR2 ,Counter clear register 2" "No effect,Clear"
|
|
bitfld.long 0x0C 1. " CCLR1 ,Counter clear register 1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CCLR0 ,Counter clear register 0" "No effect,Clear"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SSELCH ,ELCH Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " SSELCG ,ELCG Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SSELCF ,ELCF Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SSELCE ,ELCE Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SSGTRGDF ,GTETRGD Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SSGTRGDR ,GTETRGD Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SSGTRGCF ,GTETRGC Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SSGTRGCR ,GTETRGC Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x04 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " PSELCH ,ELCH Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " PSELCG ,ELCG Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " PSELCF ,ELCF Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " PSELCE ,ELCE Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PSGTRGDF ,GTETRGD Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " PSGTRGDR ,GTETRGD Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " PSGTRGCF ,GTETRGC Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PSGTRGCR ,GTETRGC Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
line.long 0x08 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x08 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " CSELCH ,ELCH Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " CSELCG ,ELCG Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " CSELCF ,ELCF Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " CSELCE ,ELCE Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " CSGTRGDF ,GTETRGD Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " CSGTRGDR ,GTETRGD Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " CSGTRGCF ,GTETRGC Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSGTRGCR ,GTETRGC Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
line.long 0x0C "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x0C 23. " USELCH ,ELCH Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " USELCG ,ELCG Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " USELCF ,ELCF Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " USELCE ,ELCE Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " USGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " USGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " USGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " USGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x10 23. " DSELCH ,ELCH Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " DSELCG ,ELCG Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " DSELCF ,ELCF Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " DSELCE ,ELCE Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DSGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " DSGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " DSGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DSGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 23. " ASELCH ,ELCH Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ASELCG ,ELCG Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ASELCF ,ELCF Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ASELCE ,ELCE Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASGTRGDF ,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ASGTRGDR ,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASGTRGCF ,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ASGTRGCR ,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 23. " BSELCH ,ELCH Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " BSELCG ,ELCG Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BSELCF ,ELCF Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " BSELCE ,ELCE Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BSGTRGDF ,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BSGTRGDR ,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BSGTRGCF ,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BSGTRGCR ,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "/1,/4,/16,/64,/256,/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM mode,Saw-wave one-shot pulse mode,,,Triangle-wave PWM mode 1,Triangle-wave PWM mode 2,Triangle-wave PWM mode 3,"
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Not stopped"
|
|
line.long 0x04 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x04 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
bitfld.long 0x04 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 1. " UDF ,Forcible Count Direction Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 0. " UD ,Count Direction Setting" "Down,Up"
|
|
line.long 0x08 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x08 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "/1,/4,/16,/64"
|
|
bitfld.long 0x08 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x08 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 16.--20. " GTIOB ,Initial Output/Output At Cycle End/Output At GTCCRB Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
bitfld.long 0x08 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "/1,/4,/16,/64"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x08 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 0.--4. " GTIOA ,Initial Output/Output At Cycle End/Output At GTCCRA Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
line.long 0x0C "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x0C 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,Group C,Group D"
|
|
line.long 0x10 "GTST,General PWM Timer Status Register"
|
|
rbitfld.long 0x10 30. " OABLF ,Same Time Output Level Low Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 29. " OABHF ,Same Time Output Level High Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 24. " ODF ,Output Disable Flag" "Not requested,Requested"
|
|
rbitfld.long 0x10 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x10 7. " TCFPU ,Underflow Flag" "No underflow,Underflow"
|
|
bitfld.long 0x10 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x10 5. " TCFF ,Input Compare Match Flag F" "Not generated,Generated"
|
|
bitfld.long 0x10 4. " TCFE ,Input Compare Match Flag E" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x10 3. " TCFD ,Input Compare Match Flag D" "Not generated,Generated"
|
|
bitfld.long 0x10 2. " TCFC ,Input Compare Match Flag C" "Not generated,Generated"
|
|
bitfld.long 0x10 1. " TCFB ,Input Capture/Compare Match Flag B" "Not generated,Generated"
|
|
bitfld.long 0x10 0. " TCFA ,Input Capture/Compare Match Flag A" "Not generated,Generated"
|
|
line.long 0x14 "GTBER,General PWM Timer Buffer Enable Register"
|
|
bitfld.long 0x14 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not performed,Performed"
|
|
bitfld.long 0x14 20.--21. " PR ,GTPR Buffer Operation" "No buffer,Single buffer,,"
|
|
bitfld.long 0x14 18.--19. " CCRB ,GTCCRB Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
bitfld.long 0x14 16.--17. " CCRA ,GTCCRA Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
textline " "
|
|
bitfld.long 0x14 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x14 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "GTCCRE,General PWM Timer Compare Capture Register E"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "GTCCRD,General PWM Timer Compare Capture Register D"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "GTCCRF,General PWM Timer Compare Capture Register F"
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
line.long 0x04 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
group.long 0x88++0x07
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Without using GTDVU,GTDVU sets the compare match value"
|
|
line.long 0x04 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
if (((per.l(ad:0x40078FF0))&0x10000)==0x0)
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
else
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
bitfld.long 0x00 2. " WF ,Input W-Phase Soft Setting" "0,1"
|
|
bitfld.long 0x00 1. " VF ,Input V-Phase Soft Setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UF ,Input U-Phase Soft Setting" "0,1"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 5"
|
|
base ad:0x40078500
|
|
width 10.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GTWP,General PWM Timer Write-Protection Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRKEY ,GTWP Key Code"
|
|
bitfld.long 0x00 0. " WP ,Register Write Disable" "No,Yes"
|
|
line.long 0x04 "GTSTR,General PWM Timer Software Start Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x04 9. " CSTRT9 ,Counter start register 9" "No effect,Started"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " CSTRT8 ,Counter start register 8" "No effect,Started"
|
|
bitfld.long 0x04 7. " CSTRT7 ,Counter start register 7" "No effect,Started"
|
|
bitfld.long 0x04 6. " CSTRT6 ,Counter start register 6" "No effect,Started"
|
|
bitfld.long 0x04 5. " CSTRT5 ,Counter start register 5" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CSTRT4 ,Counter start register 4" "No effect,Started"
|
|
bitfld.long 0x04 3. " CSTRT3 ,Counter start register 3" "No effect,Started"
|
|
bitfld.long 0x04 2. " CSTRT2 ,Counter start register 2" "No effect,Started"
|
|
bitfld.long 0x04 1. " CSTRT1 ,Counter start register 1" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CSTRT0 ,Counter start register 0" "No effect,Started"
|
|
line.long 0x08 "GTSTP,General PWM Timer Software Stop Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x08 9. " CSTOP9 ,Counter stop register 9" "No effect,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 8. " CSTOP8 ,Counter stop register 8" "No effect,Stopped"
|
|
bitfld.long 0x08 7. " CSTOP7 ,Counter stop register 7" "No effect,Stopped"
|
|
bitfld.long 0x08 6. " CSTOP6 ,Counter stop register 6" "No effect,Stopped"
|
|
bitfld.long 0x08 5. " CSTOP5 ,Counter stop register 5" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSTOP4 ,Counter stop register 4" "No effect,Stopped"
|
|
bitfld.long 0x08 3. " CSTOP3 ,Counter stop register 3" "No effect,Stopped"
|
|
bitfld.long 0x08 2. " CSTOP2 ,Counter stop register 2" "No effect,Stopped"
|
|
bitfld.long 0x08 1. " CSTOP1 ,Counter stop register 1" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSTOP0 ,Counter stop register 0" "No effect,Stopped"
|
|
line.long 0x0C "GTCLR,General PWM Timer Software Clear Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x0C 9. " CCLR9 ,Counter clear register 9" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 8. " CCLR8 ,Counter clear register 8" "No effect,Clear"
|
|
bitfld.long 0x0C 7. " CCLR7 ,Counter clear register 7" "No effect,Clear"
|
|
bitfld.long 0x0C 6. " CCLR6 ,Counter clear register 6" "No effect,Clear"
|
|
bitfld.long 0x0C 5. " CCLR5 ,Counter clear register 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CCLR4 ,Counter clear register 4" "No effect,Clear"
|
|
bitfld.long 0x0C 3. " CCLR3 ,Counter clear register 3" "No effect,Clear"
|
|
bitfld.long 0x0C 2. " CCLR2 ,Counter clear register 2" "No effect,Clear"
|
|
bitfld.long 0x0C 1. " CCLR1 ,Counter clear register 1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CCLR0 ,Counter clear register 0" "No effect,Clear"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SSELCH ,ELCH Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " SSELCG ,ELCG Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SSELCF ,ELCF Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SSELCE ,ELCE Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SSGTRGDF ,GTETRGD Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SSGTRGDR ,GTETRGD Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SSGTRGCF ,GTETRGC Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SSGTRGCR ,GTETRGC Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x04 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " PSELCH ,ELCH Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " PSELCG ,ELCG Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " PSELCF ,ELCF Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " PSELCE ,ELCE Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PSGTRGDF ,GTETRGD Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " PSGTRGDR ,GTETRGD Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " PSGTRGCF ,GTETRGC Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PSGTRGCR ,GTETRGC Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
line.long 0x08 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x08 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " CSELCH ,ELCH Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " CSELCG ,ELCG Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " CSELCF ,ELCF Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " CSELCE ,ELCE Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " CSGTRGDF ,GTETRGD Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " CSGTRGDR ,GTETRGD Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " CSGTRGCF ,GTETRGC Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSGTRGCR ,GTETRGC Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
line.long 0x0C "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x0C 23. " USELCH ,ELCH Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " USELCG ,ELCG Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " USELCF ,ELCF Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " USELCE ,ELCE Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " USGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " USGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " USGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " USGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x10 23. " DSELCH ,ELCH Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " DSELCG ,ELCG Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " DSELCF ,ELCF Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " DSELCE ,ELCE Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DSGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " DSGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " DSGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DSGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 23. " ASELCH ,ELCH Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ASELCG ,ELCG Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ASELCF ,ELCF Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ASELCE ,ELCE Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASGTRGDF ,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ASGTRGDR ,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASGTRGCF ,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ASGTRGCR ,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 23. " BSELCH ,ELCH Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " BSELCG ,ELCG Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BSELCF ,ELCF Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " BSELCE ,ELCE Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BSGTRGDF ,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BSGTRGDR ,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BSGTRGCF ,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BSGTRGCR ,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "/1,/4,/16,/64,/256,/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM mode,Saw-wave one-shot pulse mode,,,Triangle-wave PWM mode 1,Triangle-wave PWM mode 2,Triangle-wave PWM mode 3,"
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Not stopped"
|
|
line.long 0x04 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x04 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
bitfld.long 0x04 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 1. " UDF ,Forcible Count Direction Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 0. " UD ,Count Direction Setting" "Down,Up"
|
|
line.long 0x08 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x08 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "/1,/4,/16,/64"
|
|
bitfld.long 0x08 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x08 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 16.--20. " GTIOB ,Initial Output/Output At Cycle End/Output At GTCCRB Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
bitfld.long 0x08 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "/1,/4,/16,/64"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x08 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 0.--4. " GTIOA ,Initial Output/Output At Cycle End/Output At GTCCRA Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
line.long 0x0C "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x0C 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,Group C,Group D"
|
|
line.long 0x10 "GTST,General PWM Timer Status Register"
|
|
rbitfld.long 0x10 30. " OABLF ,Same Time Output Level Low Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 29. " OABHF ,Same Time Output Level High Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 24. " ODF ,Output Disable Flag" "Not requested,Requested"
|
|
rbitfld.long 0x10 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x10 7. " TCFPU ,Underflow Flag" "No underflow,Underflow"
|
|
bitfld.long 0x10 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x10 5. " TCFF ,Input Compare Match Flag F" "Not generated,Generated"
|
|
bitfld.long 0x10 4. " TCFE ,Input Compare Match Flag E" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x10 3. " TCFD ,Input Compare Match Flag D" "Not generated,Generated"
|
|
bitfld.long 0x10 2. " TCFC ,Input Compare Match Flag C" "Not generated,Generated"
|
|
bitfld.long 0x10 1. " TCFB ,Input Capture/Compare Match Flag B" "Not generated,Generated"
|
|
bitfld.long 0x10 0. " TCFA ,Input Capture/Compare Match Flag A" "Not generated,Generated"
|
|
line.long 0x14 "GTBER,General PWM Timer Buffer Enable Register"
|
|
bitfld.long 0x14 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not performed,Performed"
|
|
bitfld.long 0x14 20.--21. " PR ,GTPR Buffer Operation" "No buffer,Single buffer,,"
|
|
bitfld.long 0x14 18.--19. " CCRB ,GTCCRB Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
bitfld.long 0x14 16.--17. " CCRA ,GTCCRA Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
textline " "
|
|
bitfld.long 0x14 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x14 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "GTCCRE,General PWM Timer Compare Capture Register E"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "GTCCRD,General PWM Timer Compare Capture Register D"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "GTCCRF,General PWM Timer Compare Capture Register F"
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
line.long 0x04 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
group.long 0x88++0x07
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Without using GTDVU,GTDVU sets the compare match value"
|
|
line.long 0x04 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
if (((per.l(ad:0x40078FF0))&0x10000)==0x0)
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
else
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
bitfld.long 0x00 2. " WF ,Input W-Phase Soft Setting" "0,1"
|
|
bitfld.long 0x00 1. " VF ,Input V-Phase Soft Setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UF ,Input U-Phase Soft Setting" "0,1"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 6"
|
|
base ad:0x40078600
|
|
width 10.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GTWP,General PWM Timer Write-Protection Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRKEY ,GTWP Key Code"
|
|
bitfld.long 0x00 0. " WP ,Register Write Disable" "No,Yes"
|
|
line.long 0x04 "GTSTR,General PWM Timer Software Start Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x04 9. " CSTRT9 ,Counter start register 9" "No effect,Started"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " CSTRT8 ,Counter start register 8" "No effect,Started"
|
|
bitfld.long 0x04 7. " CSTRT7 ,Counter start register 7" "No effect,Started"
|
|
bitfld.long 0x04 6. " CSTRT6 ,Counter start register 6" "No effect,Started"
|
|
bitfld.long 0x04 5. " CSTRT5 ,Counter start register 5" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CSTRT4 ,Counter start register 4" "No effect,Started"
|
|
bitfld.long 0x04 3. " CSTRT3 ,Counter start register 3" "No effect,Started"
|
|
bitfld.long 0x04 2. " CSTRT2 ,Counter start register 2" "No effect,Started"
|
|
bitfld.long 0x04 1. " CSTRT1 ,Counter start register 1" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CSTRT0 ,Counter start register 0" "No effect,Started"
|
|
line.long 0x08 "GTSTP,General PWM Timer Software Stop Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x08 9. " CSTOP9 ,Counter stop register 9" "No effect,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 8. " CSTOP8 ,Counter stop register 8" "No effect,Stopped"
|
|
bitfld.long 0x08 7. " CSTOP7 ,Counter stop register 7" "No effect,Stopped"
|
|
bitfld.long 0x08 6. " CSTOP6 ,Counter stop register 6" "No effect,Stopped"
|
|
bitfld.long 0x08 5. " CSTOP5 ,Counter stop register 5" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSTOP4 ,Counter stop register 4" "No effect,Stopped"
|
|
bitfld.long 0x08 3. " CSTOP3 ,Counter stop register 3" "No effect,Stopped"
|
|
bitfld.long 0x08 2. " CSTOP2 ,Counter stop register 2" "No effect,Stopped"
|
|
bitfld.long 0x08 1. " CSTOP1 ,Counter stop register 1" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSTOP0 ,Counter stop register 0" "No effect,Stopped"
|
|
line.long 0x0C "GTCLR,General PWM Timer Software Clear Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x0C 9. " CCLR9 ,Counter clear register 9" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 8. " CCLR8 ,Counter clear register 8" "No effect,Clear"
|
|
bitfld.long 0x0C 7. " CCLR7 ,Counter clear register 7" "No effect,Clear"
|
|
bitfld.long 0x0C 6. " CCLR6 ,Counter clear register 6" "No effect,Clear"
|
|
bitfld.long 0x0C 5. " CCLR5 ,Counter clear register 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CCLR4 ,Counter clear register 4" "No effect,Clear"
|
|
bitfld.long 0x0C 3. " CCLR3 ,Counter clear register 3" "No effect,Clear"
|
|
bitfld.long 0x0C 2. " CCLR2 ,Counter clear register 2" "No effect,Clear"
|
|
bitfld.long 0x0C 1. " CCLR1 ,Counter clear register 1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CCLR0 ,Counter clear register 0" "No effect,Clear"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SSELCH ,ELCH Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " SSELCG ,ELCG Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SSELCF ,ELCF Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SSELCE ,ELCE Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SSGTRGDF ,GTETRGD Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SSGTRGDR ,GTETRGD Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SSGTRGCF ,GTETRGC Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SSGTRGCR ,GTETRGC Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x04 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " PSELCH ,ELCH Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " PSELCG ,ELCG Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " PSELCF ,ELCF Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " PSELCE ,ELCE Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PSGTRGDF ,GTETRGD Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " PSGTRGDR ,GTETRGD Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " PSGTRGCF ,GTETRGC Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PSGTRGCR ,GTETRGC Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
line.long 0x08 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x08 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " CSELCH ,ELCH Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " CSELCG ,ELCG Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " CSELCF ,ELCF Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " CSELCE ,ELCE Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " CSGTRGDF ,GTETRGD Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " CSGTRGDR ,GTETRGD Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " CSGTRGCF ,GTETRGC Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSGTRGCR ,GTETRGC Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
line.long 0x0C "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x0C 23. " USELCH ,ELCH Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " USELCG ,ELCG Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " USELCF ,ELCF Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " USELCE ,ELCE Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " USGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " USGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " USGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " USGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x10 23. " DSELCH ,ELCH Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " DSELCG ,ELCG Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " DSELCF ,ELCF Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " DSELCE ,ELCE Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DSGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " DSGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " DSGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DSGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 23. " ASELCH ,ELCH Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ASELCG ,ELCG Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ASELCF ,ELCF Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ASELCE ,ELCE Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASGTRGDF ,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ASGTRGDR ,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASGTRGCF ,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ASGTRGCR ,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 23. " BSELCH ,ELCH Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " BSELCG ,ELCG Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BSELCF ,ELCF Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " BSELCE ,ELCE Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BSGTRGDF ,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BSGTRGDR ,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BSGTRGCF ,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BSGTRGCR ,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "/1,/4,/16,/64,/256,/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM mode,Saw-wave one-shot pulse mode,,,Triangle-wave PWM mode 1,Triangle-wave PWM mode 2,Triangle-wave PWM mode 3,"
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Not stopped"
|
|
line.long 0x04 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x04 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
bitfld.long 0x04 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 1. " UDF ,Forcible Count Direction Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 0. " UD ,Count Direction Setting" "Down,Up"
|
|
line.long 0x08 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x08 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "/1,/4,/16,/64"
|
|
bitfld.long 0x08 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x08 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 16.--20. " GTIOB ,Initial Output/Output At Cycle End/Output At GTCCRB Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
bitfld.long 0x08 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "/1,/4,/16,/64"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x08 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 0.--4. " GTIOA ,Initial Output/Output At Cycle End/Output At GTCCRA Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
line.long 0x0C "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x0C 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,Group C,Group D"
|
|
line.long 0x10 "GTST,General PWM Timer Status Register"
|
|
rbitfld.long 0x10 30. " OABLF ,Same Time Output Level Low Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 29. " OABHF ,Same Time Output Level High Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 24. " ODF ,Output Disable Flag" "Not requested,Requested"
|
|
rbitfld.long 0x10 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x10 7. " TCFPU ,Underflow Flag" "No underflow,Underflow"
|
|
bitfld.long 0x10 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x10 5. " TCFF ,Input Compare Match Flag F" "Not generated,Generated"
|
|
bitfld.long 0x10 4. " TCFE ,Input Compare Match Flag E" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x10 3. " TCFD ,Input Compare Match Flag D" "Not generated,Generated"
|
|
bitfld.long 0x10 2. " TCFC ,Input Compare Match Flag C" "Not generated,Generated"
|
|
bitfld.long 0x10 1. " TCFB ,Input Capture/Compare Match Flag B" "Not generated,Generated"
|
|
bitfld.long 0x10 0. " TCFA ,Input Capture/Compare Match Flag A" "Not generated,Generated"
|
|
line.long 0x14 "GTBER,General PWM Timer Buffer Enable Register"
|
|
bitfld.long 0x14 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not performed,Performed"
|
|
bitfld.long 0x14 20.--21. " PR ,GTPR Buffer Operation" "No buffer,Single buffer,,"
|
|
bitfld.long 0x14 18.--19. " CCRB ,GTCCRB Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
bitfld.long 0x14 16.--17. " CCRA ,GTCCRA Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
textline " "
|
|
bitfld.long 0x14 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x14 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "GTCCRE,General PWM Timer Compare Capture Register E"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "GTCCRD,General PWM Timer Compare Capture Register D"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "GTCCRF,General PWM Timer Compare Capture Register F"
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
line.long 0x04 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
group.long 0x88++0x07
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Without using GTDVU,GTDVU sets the compare match value"
|
|
line.long 0x04 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
if (((per.l(ad:0x40078FF0))&0x10000)==0x0)
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
else
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
bitfld.long 0x00 2. " WF ,Input W-Phase Soft Setting" "0,1"
|
|
bitfld.long 0x00 1. " VF ,Input V-Phase Soft Setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UF ,Input U-Phase Soft Setting" "0,1"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 7"
|
|
base ad:0x40078700
|
|
width 10.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GTWP,General PWM Timer Write-Protection Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRKEY ,GTWP Key Code"
|
|
bitfld.long 0x00 0. " WP ,Register Write Disable" "No,Yes"
|
|
line.long 0x04 "GTSTR,General PWM Timer Software Start Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x04 9. " CSTRT9 ,Counter start register 9" "No effect,Started"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " CSTRT8 ,Counter start register 8" "No effect,Started"
|
|
bitfld.long 0x04 7. " CSTRT7 ,Counter start register 7" "No effect,Started"
|
|
bitfld.long 0x04 6. " CSTRT6 ,Counter start register 6" "No effect,Started"
|
|
bitfld.long 0x04 5. " CSTRT5 ,Counter start register 5" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CSTRT4 ,Counter start register 4" "No effect,Started"
|
|
bitfld.long 0x04 3. " CSTRT3 ,Counter start register 3" "No effect,Started"
|
|
bitfld.long 0x04 2. " CSTRT2 ,Counter start register 2" "No effect,Started"
|
|
bitfld.long 0x04 1. " CSTRT1 ,Counter start register 1" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CSTRT0 ,Counter start register 0" "No effect,Started"
|
|
line.long 0x08 "GTSTP,General PWM Timer Software Stop Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x08 9. " CSTOP9 ,Counter stop register 9" "No effect,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 8. " CSTOP8 ,Counter stop register 8" "No effect,Stopped"
|
|
bitfld.long 0x08 7. " CSTOP7 ,Counter stop register 7" "No effect,Stopped"
|
|
bitfld.long 0x08 6. " CSTOP6 ,Counter stop register 6" "No effect,Stopped"
|
|
bitfld.long 0x08 5. " CSTOP5 ,Counter stop register 5" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSTOP4 ,Counter stop register 4" "No effect,Stopped"
|
|
bitfld.long 0x08 3. " CSTOP3 ,Counter stop register 3" "No effect,Stopped"
|
|
bitfld.long 0x08 2. " CSTOP2 ,Counter stop register 2" "No effect,Stopped"
|
|
bitfld.long 0x08 1. " CSTOP1 ,Counter stop register 1" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSTOP0 ,Counter stop register 0" "No effect,Stopped"
|
|
line.long 0x0C "GTCLR,General PWM Timer Software Clear Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x0C 9. " CCLR9 ,Counter clear register 9" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 8. " CCLR8 ,Counter clear register 8" "No effect,Clear"
|
|
bitfld.long 0x0C 7. " CCLR7 ,Counter clear register 7" "No effect,Clear"
|
|
bitfld.long 0x0C 6. " CCLR6 ,Counter clear register 6" "No effect,Clear"
|
|
bitfld.long 0x0C 5. " CCLR5 ,Counter clear register 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CCLR4 ,Counter clear register 4" "No effect,Clear"
|
|
bitfld.long 0x0C 3. " CCLR3 ,Counter clear register 3" "No effect,Clear"
|
|
bitfld.long 0x0C 2. " CCLR2 ,Counter clear register 2" "No effect,Clear"
|
|
bitfld.long 0x0C 1. " CCLR1 ,Counter clear register 1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CCLR0 ,Counter clear register 0" "No effect,Clear"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SSELCH ,ELCH Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " SSELCG ,ELCG Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SSELCF ,ELCF Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SSELCE ,ELCE Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SSGTRGDF ,GTETRGD Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SSGTRGDR ,GTETRGD Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SSGTRGCF ,GTETRGC Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SSGTRGCR ,GTETRGC Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x04 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " PSELCH ,ELCH Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " PSELCG ,ELCG Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " PSELCF ,ELCF Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " PSELCE ,ELCE Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PSGTRGDF ,GTETRGD Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " PSGTRGDR ,GTETRGD Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " PSGTRGCF ,GTETRGC Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PSGTRGCR ,GTETRGC Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
line.long 0x08 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x08 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " CSELCH ,ELCH Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " CSELCG ,ELCG Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " CSELCF ,ELCF Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " CSELCE ,ELCE Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " CSGTRGDF ,GTETRGD Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " CSGTRGDR ,GTETRGD Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " CSGTRGCF ,GTETRGC Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSGTRGCR ,GTETRGC Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
line.long 0x0C "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x0C 23. " USELCH ,ELCH Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " USELCG ,ELCG Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " USELCF ,ELCF Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " USELCE ,ELCE Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " USGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " USGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " USGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " USGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x10 23. " DSELCH ,ELCH Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " DSELCG ,ELCG Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " DSELCF ,ELCF Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " DSELCE ,ELCE Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DSGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " DSGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " DSGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DSGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 23. " ASELCH ,ELCH Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ASELCG ,ELCG Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ASELCF ,ELCF Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ASELCE ,ELCE Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASGTRGDF ,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ASGTRGDR ,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASGTRGCF ,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ASGTRGCR ,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 23. " BSELCH ,ELCH Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " BSELCG ,ELCG Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BSELCF ,ELCF Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " BSELCE ,ELCE Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BSGTRGDF ,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BSGTRGDR ,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BSGTRGCF ,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BSGTRGCR ,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "/1,/4,/16,/64,/256,/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM mode,Saw-wave one-shot pulse mode,,,Triangle-wave PWM mode 1,Triangle-wave PWM mode 2,Triangle-wave PWM mode 3,"
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Not stopped"
|
|
line.long 0x04 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x04 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
bitfld.long 0x04 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 1. " UDF ,Forcible Count Direction Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 0. " UD ,Count Direction Setting" "Down,Up"
|
|
line.long 0x08 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x08 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "/1,/4,/16,/64"
|
|
bitfld.long 0x08 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x08 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 16.--20. " GTIOB ,Initial Output/Output At Cycle End/Output At GTCCRB Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
bitfld.long 0x08 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "/1,/4,/16,/64"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x08 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 0.--4. " GTIOA ,Initial Output/Output At Cycle End/Output At GTCCRA Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
line.long 0x0C "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x0C 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,Group C,Group D"
|
|
line.long 0x10 "GTST,General PWM Timer Status Register"
|
|
rbitfld.long 0x10 30. " OABLF ,Same Time Output Level Low Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 29. " OABHF ,Same Time Output Level High Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 24. " ODF ,Output Disable Flag" "Not requested,Requested"
|
|
rbitfld.long 0x10 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x10 7. " TCFPU ,Underflow Flag" "No underflow,Underflow"
|
|
bitfld.long 0x10 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x10 5. " TCFF ,Input Compare Match Flag F" "Not generated,Generated"
|
|
bitfld.long 0x10 4. " TCFE ,Input Compare Match Flag E" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x10 3. " TCFD ,Input Compare Match Flag D" "Not generated,Generated"
|
|
bitfld.long 0x10 2. " TCFC ,Input Compare Match Flag C" "Not generated,Generated"
|
|
bitfld.long 0x10 1. " TCFB ,Input Capture/Compare Match Flag B" "Not generated,Generated"
|
|
bitfld.long 0x10 0. " TCFA ,Input Capture/Compare Match Flag A" "Not generated,Generated"
|
|
line.long 0x14 "GTBER,General PWM Timer Buffer Enable Register"
|
|
bitfld.long 0x14 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not performed,Performed"
|
|
bitfld.long 0x14 20.--21. " PR ,GTPR Buffer Operation" "No buffer,Single buffer,,"
|
|
bitfld.long 0x14 18.--19. " CCRB ,GTCCRB Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
bitfld.long 0x14 16.--17. " CCRA ,GTCCRA Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
textline " "
|
|
bitfld.long 0x14 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x14 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "GTCCRE,General PWM Timer Compare Capture Register E"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "GTCCRD,General PWM Timer Compare Capture Register D"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "GTCCRF,General PWM Timer Compare Capture Register F"
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
line.long 0x04 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
group.long 0x88++0x07
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Without using GTDVU,GTDVU sets the compare match value"
|
|
line.long 0x04 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
if (((per.l(ad:0x40078FF0))&0x10000)==0x0)
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
else
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
bitfld.long 0x00 2. " WF ,Input W-Phase Soft Setting" "0,1"
|
|
bitfld.long 0x00 1. " VF ,Input V-Phase Soft Setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UF ,Input U-Phase Soft Setting" "0,1"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 8"
|
|
base ad:0x40078800
|
|
width 10.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GTWP,General PWM Timer Write-Protection Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRKEY ,GTWP Key Code"
|
|
bitfld.long 0x00 0. " WP ,Register Write Disable" "No,Yes"
|
|
line.long 0x04 "GTSTR,General PWM Timer Software Start Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x04 9. " CSTRT9 ,Counter start register 9" "No effect,Started"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " CSTRT8 ,Counter start register 8" "No effect,Started"
|
|
bitfld.long 0x04 7. " CSTRT7 ,Counter start register 7" "No effect,Started"
|
|
bitfld.long 0x04 6. " CSTRT6 ,Counter start register 6" "No effect,Started"
|
|
bitfld.long 0x04 5. " CSTRT5 ,Counter start register 5" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CSTRT4 ,Counter start register 4" "No effect,Started"
|
|
bitfld.long 0x04 3. " CSTRT3 ,Counter start register 3" "No effect,Started"
|
|
bitfld.long 0x04 2. " CSTRT2 ,Counter start register 2" "No effect,Started"
|
|
bitfld.long 0x04 1. " CSTRT1 ,Counter start register 1" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CSTRT0 ,Counter start register 0" "No effect,Started"
|
|
line.long 0x08 "GTSTP,General PWM Timer Software Stop Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x08 9. " CSTOP9 ,Counter stop register 9" "No effect,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 8. " CSTOP8 ,Counter stop register 8" "No effect,Stopped"
|
|
bitfld.long 0x08 7. " CSTOP7 ,Counter stop register 7" "No effect,Stopped"
|
|
bitfld.long 0x08 6. " CSTOP6 ,Counter stop register 6" "No effect,Stopped"
|
|
bitfld.long 0x08 5. " CSTOP5 ,Counter stop register 5" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSTOP4 ,Counter stop register 4" "No effect,Stopped"
|
|
bitfld.long 0x08 3. " CSTOP3 ,Counter stop register 3" "No effect,Stopped"
|
|
bitfld.long 0x08 2. " CSTOP2 ,Counter stop register 2" "No effect,Stopped"
|
|
bitfld.long 0x08 1. " CSTOP1 ,Counter stop register 1" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSTOP0 ,Counter stop register 0" "No effect,Stopped"
|
|
line.long 0x0C "GTCLR,General PWM Timer Software Clear Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x0C 9. " CCLR9 ,Counter clear register 9" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 8. " CCLR8 ,Counter clear register 8" "No effect,Clear"
|
|
bitfld.long 0x0C 7. " CCLR7 ,Counter clear register 7" "No effect,Clear"
|
|
bitfld.long 0x0C 6. " CCLR6 ,Counter clear register 6" "No effect,Clear"
|
|
bitfld.long 0x0C 5. " CCLR5 ,Counter clear register 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CCLR4 ,Counter clear register 4" "No effect,Clear"
|
|
bitfld.long 0x0C 3. " CCLR3 ,Counter clear register 3" "No effect,Clear"
|
|
bitfld.long 0x0C 2. " CCLR2 ,Counter clear register 2" "No effect,Clear"
|
|
bitfld.long 0x0C 1. " CCLR1 ,Counter clear register 1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CCLR0 ,Counter clear register 0" "No effect,Clear"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SSELCH ,ELCH Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " SSELCG ,ELCG Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SSELCF ,ELCF Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SSELCE ,ELCE Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SSGTRGDF ,GTETRGD Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SSGTRGDR ,GTETRGD Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SSGTRGCF ,GTETRGC Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SSGTRGCR ,GTETRGC Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x04 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " PSELCH ,ELCH Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " PSELCG ,ELCG Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " PSELCF ,ELCF Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " PSELCE ,ELCE Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PSGTRGDF ,GTETRGD Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " PSGTRGDR ,GTETRGD Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " PSGTRGCF ,GTETRGC Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PSGTRGCR ,GTETRGC Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
line.long 0x08 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x08 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " CSELCH ,ELCH Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " CSELCG ,ELCG Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " CSELCF ,ELCF Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " CSELCE ,ELCE Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " CSGTRGDF ,GTETRGD Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " CSGTRGDR ,GTETRGD Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " CSGTRGCF ,GTETRGC Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSGTRGCR ,GTETRGC Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
line.long 0x0C "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x0C 23. " USELCH ,ELCH Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " USELCG ,ELCG Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " USELCF ,ELCF Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " USELCE ,ELCE Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " USGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " USGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " USGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " USGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x10 23. " DSELCH ,ELCH Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " DSELCG ,ELCG Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " DSELCF ,ELCF Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " DSELCE ,ELCE Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DSGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " DSGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " DSGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DSGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 23. " ASELCH ,ELCH Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ASELCG ,ELCG Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ASELCF ,ELCF Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ASELCE ,ELCE Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASGTRGDF ,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ASGTRGDR ,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASGTRGCF ,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ASGTRGCR ,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 23. " BSELCH ,ELCH Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " BSELCG ,ELCG Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BSELCF ,ELCF Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " BSELCE ,ELCE Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BSGTRGDF ,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BSGTRGDR ,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BSGTRGCF ,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BSGTRGCR ,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "/1,/4,/16,/64,/256,/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM mode,Saw-wave one-shot pulse mode,,,Triangle-wave PWM mode 1,Triangle-wave PWM mode 2,Triangle-wave PWM mode 3,"
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Not stopped"
|
|
line.long 0x04 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x04 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
bitfld.long 0x04 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 1. " UDF ,Forcible Count Direction Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 0. " UD ,Count Direction Setting" "Down,Up"
|
|
line.long 0x08 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x08 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "/1,/4,/16,/64"
|
|
bitfld.long 0x08 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x08 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 16.--20. " GTIOB ,Initial Output/Output At Cycle End/Output At GTCCRB Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
bitfld.long 0x08 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "/1,/4,/16,/64"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x08 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 0.--4. " GTIOA ,Initial Output/Output At Cycle End/Output At GTCCRA Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
line.long 0x0C "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x0C 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,Group C,Group D"
|
|
line.long 0x10 "GTST,General PWM Timer Status Register"
|
|
rbitfld.long 0x10 30. " OABLF ,Same Time Output Level Low Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 29. " OABHF ,Same Time Output Level High Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 24. " ODF ,Output Disable Flag" "Not requested,Requested"
|
|
rbitfld.long 0x10 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x10 7. " TCFPU ,Underflow Flag" "No underflow,Underflow"
|
|
bitfld.long 0x10 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x10 5. " TCFF ,Input Compare Match Flag F" "Not generated,Generated"
|
|
bitfld.long 0x10 4. " TCFE ,Input Compare Match Flag E" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x10 3. " TCFD ,Input Compare Match Flag D" "Not generated,Generated"
|
|
bitfld.long 0x10 2. " TCFC ,Input Compare Match Flag C" "Not generated,Generated"
|
|
bitfld.long 0x10 1. " TCFB ,Input Capture/Compare Match Flag B" "Not generated,Generated"
|
|
bitfld.long 0x10 0. " TCFA ,Input Capture/Compare Match Flag A" "Not generated,Generated"
|
|
line.long 0x14 "GTBER,General PWM Timer Buffer Enable Register"
|
|
bitfld.long 0x14 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not performed,Performed"
|
|
bitfld.long 0x14 20.--21. " PR ,GTPR Buffer Operation" "No buffer,Single buffer,,"
|
|
bitfld.long 0x14 18.--19. " CCRB ,GTCCRB Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
bitfld.long 0x14 16.--17. " CCRA ,GTCCRA Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
textline " "
|
|
bitfld.long 0x14 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x14 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "GTCCRE,General PWM Timer Compare Capture Register E"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "GTCCRD,General PWM Timer Compare Capture Register D"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "GTCCRF,General PWM Timer Compare Capture Register F"
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
line.long 0x04 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
group.long 0x88++0x07
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Without using GTDVU,GTDVU sets the compare match value"
|
|
line.long 0x04 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
if (((per.l(ad:0x40078FF0))&0x10000)==0x0)
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
else
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
bitfld.long 0x00 2. " WF ,Input W-Phase Soft Setting" "0,1"
|
|
bitfld.long 0x00 1. " VF ,Input V-Phase Soft Setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UF ,Input U-Phase Soft Setting" "0,1"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
tree "Channel 9"
|
|
base ad:0x40078900
|
|
width 10.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GTWP,General PWM Timer Write-Protection Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRKEY ,GTWP Key Code"
|
|
bitfld.long 0x00 0. " WP ,Register Write Disable" "No,Yes"
|
|
line.long 0x04 "GTSTR,General PWM Timer Software Start Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x04 9. " CSTRT9 ,Counter start register 9" "No effect,Started"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8. " CSTRT8 ,Counter start register 8" "No effect,Started"
|
|
bitfld.long 0x04 7. " CSTRT7 ,Counter start register 7" "No effect,Started"
|
|
bitfld.long 0x04 6. " CSTRT6 ,Counter start register 6" "No effect,Started"
|
|
bitfld.long 0x04 5. " CSTRT5 ,Counter start register 5" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CSTRT4 ,Counter start register 4" "No effect,Started"
|
|
bitfld.long 0x04 3. " CSTRT3 ,Counter start register 3" "No effect,Started"
|
|
bitfld.long 0x04 2. " CSTRT2 ,Counter start register 2" "No effect,Started"
|
|
bitfld.long 0x04 1. " CSTRT1 ,Counter start register 1" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CSTRT0 ,Counter start register 0" "No effect,Started"
|
|
line.long 0x08 "GTSTP,General PWM Timer Software Stop Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x08 9. " CSTOP9 ,Counter stop register 9" "No effect,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 8. " CSTOP8 ,Counter stop register 8" "No effect,Stopped"
|
|
bitfld.long 0x08 7. " CSTOP7 ,Counter stop register 7" "No effect,Stopped"
|
|
bitfld.long 0x08 6. " CSTOP6 ,Counter stop register 6" "No effect,Stopped"
|
|
bitfld.long 0x08 5. " CSTOP5 ,Counter stop register 5" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSTOP4 ,Counter stop register 4" "No effect,Stopped"
|
|
bitfld.long 0x08 3. " CSTOP3 ,Counter stop register 3" "No effect,Stopped"
|
|
bitfld.long 0x08 2. " CSTOP2 ,Counter stop register 2" "No effect,Stopped"
|
|
bitfld.long 0x08 1. " CSTOP1 ,Counter stop register 1" "No effect,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSTOP0 ,Counter stop register 0" "No effect,Stopped"
|
|
line.long 0x0C "GTCLR,General PWM Timer Software Clear Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.long 0x0C 9. " CCLR9 ,Counter clear register 9" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 8. " CCLR8 ,Counter clear register 8" "No effect,Clear"
|
|
bitfld.long 0x0C 7. " CCLR7 ,Counter clear register 7" "No effect,Clear"
|
|
bitfld.long 0x0C 6. " CCLR6 ,Counter clear register 6" "No effect,Clear"
|
|
bitfld.long 0x0C 5. " CCLR5 ,Counter clear register 5" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CCLR4 ,Counter clear register 4" "No effect,Clear"
|
|
bitfld.long 0x0C 3. " CCLR3 ,Counter clear register 3" "No effect,Clear"
|
|
bitfld.long 0x0C 2. " CCLR2 ,Counter clear register 2" "No effect,Clear"
|
|
bitfld.long 0x0C 1. " CCLR1 ,Counter clear register 1" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CCLR0 ,Counter clear register 0" "No effect,Clear"
|
|
group.long 0x10++0x13
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SSELCH ,ELCH Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " SSELCG ,ELCG Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SSELCF ,ELCF Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SSELCE ,ELCE Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SSGTRGDF ,GTETRGD Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SSGTRGDR ,GTETRGD Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SSGTRGCF ,GTETRGC Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SSGTRGCR ,GTETRGC Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x04 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " PSELCH ,ELCH Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " PSELCG ,ELCG Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " PSELCF ,ELCF Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " PSELCE ,ELCE Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PSGTRGDF ,GTETRGD Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " PSGTRGDR ,GTETRGD Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " PSGTRGCF ,GTETRGC Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PSGTRGCR ,GTETRGC Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
line.long 0x08 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x08 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " CSELCH ,ELCH Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " CSELCG ,ELCG Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " CSELCF ,ELCF Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " CSELCE ,ELCE Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " CSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " CSGTRGDF ,GTETRGD Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " CSGTRGDR ,GTETRGD Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " CSGTRGCF ,GTETRGC Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSGTRGCR ,GTETRGC Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
line.long 0x0C "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x0C 23. " USELCH ,ELCH Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " USELCG ,ELCG Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " USELCF ,ELCF Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " USELCE ,ELCE Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " USGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " USGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " USGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " USGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x10 23. " DSELCH ,ELCH Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " DSELCG ,ELCG Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " DSELCF ,ELCF Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " DSELCE ,ELCE Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DSGTRGDF ,GTETRGD Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " DSGTRGDR ,GTETRGD Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " DSGTRGCF ,GTETRGC Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DSGTRGCR ,GTETRGC Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 23. " ASELCH ,ELCH Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ASELCG ,ELCG Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ASELCF ,ELCF Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ASELCE ,ELCE Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASGTRGDF ,GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ASGTRGDR ,GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ASGTRGCF ,GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ASGTRGCR ,GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 23. " BSELCH ,ELCH Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " BSELCG ,ELCG Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BSELCF ,ELCF Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " BSELCE ,ELCE Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BSGTRGDF ,GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BSGTRGDR ,GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " BSGTRGCF ,GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BSGTRGCR ,GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "/1,/4,/16,/64,/256,/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM mode,Saw-wave one-shot pulse mode,,,Triangle-wave PWM mode 1,Triangle-wave PWM mode 2,Triangle-wave PWM mode 3,"
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Not stopped"
|
|
line.long 0x04 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x04 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
bitfld.long 0x04 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Depend on compare match,Depend on compare match,0%,100%"
|
|
bitfld.long 0x04 1. " UDF ,Forcible Count Direction Setting" "Not forcibly,Forcibly"
|
|
bitfld.long 0x04 0. " UD ,Count Direction Setting" "Down,Up"
|
|
line.long 0x08 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x08 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "/1,/4,/16,/64"
|
|
bitfld.long 0x08 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x08 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 16.--20. " GTIOB ,Initial Output/Output At Cycle End/Output At GTCCRB Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
bitfld.long 0x08 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "/1,/4,/16,/64"
|
|
textline " "
|
|
bitfld.long 0x08 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" ",Hi-Z,0,1"
|
|
bitfld.long 0x08 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x08 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x08 0.--4. " GTIOA ,Initial Output/Output At Cycle End/Output At GTCCRA Compare Match" "Low/retained/retained,Low/retained/low,Low/retained/high,Low/retained/toggled,Low/low/retained,Low/low/low,Low/low/high,Low/low/toggled,Low/high/retained,Low/high/low,Low/high/high,Low/high/toggled,Low/toggled/retained,Low/toggled/low,Low/toggled/high,Low/toggled/toggled,High/retained/retained,High/retained/low,High/retained/high,High/retained/toggled,High/low/retained,High/low/low,High/low/high,High/low/toggled,High/high/retained,High/high/low,High/high/high,High/high/toggled,High/toggled/retained,High/toggled/low,High/toggled/high,High/toggled/toggled"
|
|
line.long 0x0C "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x0C 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,Group C,Group D"
|
|
line.long 0x10 "GTST,General PWM Timer Status Register"
|
|
rbitfld.long 0x10 30. " OABLF ,Same Time Output Level Low Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 29. " OABHF ,Same Time Output Level High Flag" "Not same time,Same time"
|
|
rbitfld.long 0x10 24. " ODF ,Output Disable Flag" "Not requested,Requested"
|
|
rbitfld.long 0x10 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x10 7. " TCFPU ,Underflow Flag" "No underflow,Underflow"
|
|
bitfld.long 0x10 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x10 5. " TCFF ,Input Compare Match Flag F" "Not generated,Generated"
|
|
bitfld.long 0x10 4. " TCFE ,Input Compare Match Flag E" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x10 3. " TCFD ,Input Compare Match Flag D" "Not generated,Generated"
|
|
bitfld.long 0x10 2. " TCFC ,Input Compare Match Flag C" "Not generated,Generated"
|
|
bitfld.long 0x10 1. " TCFB ,Input Capture/Compare Match Flag B" "Not generated,Generated"
|
|
bitfld.long 0x10 0. " TCFA ,Input Capture/Compare Match Flag A" "Not generated,Generated"
|
|
line.long 0x14 "GTBER,General PWM Timer Buffer Enable Register"
|
|
bitfld.long 0x14 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not performed,Performed"
|
|
bitfld.long 0x14 20.--21. " PR ,GTPR Buffer Operation" "No buffer,Single buffer,,"
|
|
bitfld.long 0x14 18.--19. " CCRB ,GTCCRB Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
bitfld.long 0x14 16.--17. " CCRA ,GTCCRA Buffer Operation" "No buffer,Single buffer,Double buffer,Double buffer"
|
|
textline " "
|
|
bitfld.long 0x14 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x14 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "GTCCRE,General PWM Timer Compare Capture Register E"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "GTCCRD,General PWM Timer Compare Capture Register D"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "GTCCRF,General PWM Timer Compare Capture Register F"
|
|
group.long 0x64++0x07
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
line.long 0x04 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
group.long 0x88++0x07
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Without using GTDVU,GTDVU sets the compare match value"
|
|
line.long 0x04 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
if (((per.l(ad:0x40078FF0))&0x10000)==0x0)
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
else
|
|
group.long ad:0x40078FF0++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "/1,/4,/16,/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disabled Source Selection" "Group A,Group B,Group C,Group D"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "Not reversed,Reversed"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Positive,Negative"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level,PWM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level,PWM"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "External,Soft"
|
|
bitfld.long 0x00 8. " EN ,Enable-Phase Output Control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "External,Software"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input V-Phase Monitor" "External,Software"
|
|
rbitfld.long 0x00 4. " U ,Input U-Phase Monitor" "External,Software"
|
|
bitfld.long 0x00 2. " WF ,Input W-Phase Soft Setting" "0,1"
|
|
bitfld.long 0x00 1. " VF ,Input V-Phase Soft Setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UF ,Input U-Phase Soft Setting" "0,1"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "AGT (Asynchronous General Purpose Timer)"
|
|
tree "Channel 0"
|
|
base ad:0x40084000
|
|
width 10.
|
|
group.word 0x00++0x05
|
|
line.word 0x00 "AGT,AGT Counter Register"
|
|
line.word 0x02 "AGTCMA,AGT Compare Match A Register"
|
|
line.word 0x04 "AGTCMB,AGT Compare Match B Register"
|
|
group.byte 0x08++0x02
|
|
line.byte 0x00 "AGTCR,AGT Control Register"
|
|
bitfld.byte 0x00 7. " TCMBF ,Compare match B flag" "No match,Match"
|
|
bitfld.byte 0x00 6. " TCMAF ,Compare match A flag" "No match,Match"
|
|
bitfld.byte 0x00 5. " TUNDF ,Underflow flag" "No match,Match"
|
|
bitfld.byte 0x00 4. " TEDGF ,Active edge judgment flag" "Not received,Received"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TSTOP ,AGT count forced stop" "Not stopped,Stopped"
|
|
rbitfld.byte 0x00 1. " TCSTF ,AGT count status flag" "Not started,Started"
|
|
bitfld.byte 0x00 0. " TSTART ,AGT count start" "Not started,Started"
|
|
line.byte 0x01 "AGTMR1,AGT Mode Register 1"
|
|
bitfld.byte 0x01 4.--6. " TCK ,Count source" ",PCLKB/8,,,AGTLCLK/CKS,,AGTLCLK/CKS,"
|
|
bitfld.byte 0x01 3. " TEDGPL ,Edge polarity" "Single edge,Both edge"
|
|
bitfld.byte 0x01 0.--2. " TMOD ,Operating mode" "Timer,Pulse output,Event counter,Pulse with measurement,Pulse period measurement,?..."
|
|
line.byte 0x02 "AGTMR2,AGT Mode Register 2"
|
|
bitfld.byte 0x02 7. " LPM ,Low Power Mode" "Normal,Low power"
|
|
bitfld.byte 0x02 0.--2. " CKS ,AGTLCLK/AGTSCLK count source clock frequency division ratio" "1/1,1/2,1/4,1/8,1/16,1/32,1/64,1/128"
|
|
if (((per.b(ad:0x40084000+0x09))&0x7)==0x0)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,During polarity period,,"
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTO0 output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0x40084000+0x09))&0x7)==0x1)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,During polarity period,,"
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTO0 output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TEDGSEL ,I/O polarity switch - level at which output is started" "High,Low"
|
|
elif (((per.b(ad:0x40084000+0x09))&0x7)==0x2)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,During polarity period,,"
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTO0 output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TEDGSEL ,I/O polarity switch - counting edge" "Rising,Falling"
|
|
elif (((per.b(ad:0x40084000+0x09))&0x7)==0x3)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,During polarity period,,"
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTO0 output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TEDGSEL ,I/O polarity switch - measured width level" "Low-level,High-level"
|
|
elif (((per.b(ad:0x40084000+0x09))&0x7)==0x4)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,During polarity period,,"
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTO0 output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TEDGSEL ,I/O polarity switch - edge to measure from" "Rising edge,Falling edge"
|
|
else
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,During polarity period,,"
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTO0 output enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x0D++0x02
|
|
line.byte 0x00 "AGTISR,AGT Event Pin Select Register"
|
|
bitfld.byte 0x00 2. " EEPS ,AGTEE0 polarity selection" "Low-level,High-level"
|
|
line.byte 0x01 "AGTCMSR,AGT Compare Match Function Select Register"
|
|
bitfld.byte 0x01 6. " TOPOLB ,AGTOB0 polarity select" "Low,High"
|
|
bitfld.byte 0x01 5. " TOEB ,AGTOB0 output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " TCMEB ,Compare match B register enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " TOPOLA ,AGTOA0 polarity select" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " TOEA ,AGTOA0 output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " TCMEA ,Compare match A register enable" "Disabled,Enabled"
|
|
line.byte 0x02 "AGTIOSEL,AGT Pin Select Register"
|
|
bitfld.byte 0x02 4. " TIES ,AGTIO0 Input Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0.--1. " SEL ,AGTIO0 Pin Select" "AGTIO0_A,,AGTIO0_B,AGTIO0_C"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0x40084100
|
|
width 10.
|
|
group.word 0x00++0x05
|
|
line.word 0x00 "AGT,AGT Counter Register"
|
|
line.word 0x02 "AGTCMA,AGT Compare Match A Register"
|
|
line.word 0x04 "AGTCMB,AGT Compare Match B Register"
|
|
group.byte 0x08++0x02
|
|
line.byte 0x00 "AGTCR,AGT Control Register"
|
|
bitfld.byte 0x00 7. " TCMBF ,Compare match B flag" "No match,Match"
|
|
bitfld.byte 0x00 6. " TCMAF ,Compare match A flag" "No match,Match"
|
|
bitfld.byte 0x00 5. " TUNDF ,Underflow flag" "No match,Match"
|
|
bitfld.byte 0x00 4. " TEDGF ,Active edge judgment flag" "Not received,Received"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TSTOP ,AGT count forced stop" "Not stopped,Stopped"
|
|
rbitfld.byte 0x00 1. " TCSTF ,AGT count status flag" "Not started,Started"
|
|
bitfld.byte 0x00 0. " TSTART ,AGT count start" "Not started,Started"
|
|
line.byte 0x01 "AGTMR1,AGT Mode Register 1"
|
|
bitfld.byte 0x01 4.--6. " TCK ,Count source" ",PCLKB/8,,,AGTLCLK/CKS,,AGTLCLK/CKS,"
|
|
bitfld.byte 0x01 3. " TEDGPL ,Edge polarity" "Single edge,Both edge"
|
|
bitfld.byte 0x01 0.--2. " TMOD ,Operating mode" "Timer,Pulse output,Event counter,Pulse with measurement,Pulse period measurement,?..."
|
|
line.byte 0x02 "AGTMR2,AGT Mode Register 2"
|
|
bitfld.byte 0x02 7. " LPM ,Low Power Mode" "Normal,Low power"
|
|
bitfld.byte 0x02 0.--2. " CKS ,AGTLCLK/AGTSCLK count source clock frequency division ratio" "1/1,1/2,1/4,1/8,1/16,1/32,1/64,1/128"
|
|
if (((per.b(ad:0x40084100+0x09))&0x7)==0x0)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,During polarity period,,"
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTO1 output enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0x40084100+0x09))&0x7)==0x1)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,During polarity period,,"
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTO1 output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TEDGSEL ,I/O polarity switch - level at which output is started" "High,Low"
|
|
elif (((per.b(ad:0x40084100+0x09))&0x7)==0x2)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,During polarity period,,"
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTO1 output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TEDGSEL ,I/O polarity switch - counting edge" "Rising,Falling"
|
|
elif (((per.b(ad:0x40084100+0x09))&0x7)==0x3)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,During polarity period,,"
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTO1 output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TEDGSEL ,I/O polarity switch - measured width level" "Low-level,High-level"
|
|
elif (((per.b(ad:0x40084100+0x09))&0x7)==0x4)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,During polarity period,,"
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTO1 output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TEDGSEL ,I/O polarity switch - edge to measure from" "Rising edge,Falling edge"
|
|
else
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,During polarity period,,"
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTO1 output enable" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x0D++0x02
|
|
line.byte 0x00 "AGTISR,AGT Event Pin Select Register"
|
|
bitfld.byte 0x00 2. " EEPS ,AGTEE1 polarity selection" "Low-level,High-level"
|
|
line.byte 0x01 "AGTCMSR,AGT Compare Match Function Select Register"
|
|
bitfld.byte 0x01 6. " TOPOLB ,AGTOB1 polarity select" "Low,High"
|
|
bitfld.byte 0x01 5. " TOEB ,AGTOB1 output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " TCMEB ,Compare match B register enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " TOPOLA ,AGTOA1 polarity select" "Low,High"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " TOEA ,AGTOA1 output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " TCMEA ,Compare match A register enable" "Disabled,Enabled"
|
|
line.byte 0x02 "AGTIOSEL,AGT Pin Select Register"
|
|
bitfld.byte 0x02 4. " TIES ,AGTIO1 Input Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0.--1. " SEL ,AGTIO1 Pin Select" "AGTIO1_A,,AGTIO1_B,AGTIO1_C"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "RTC (Realtime Clock)"
|
|
base ad:0x40044000
|
|
width 10.
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "R64CNT,64-Hz Counter"
|
|
bitfld.byte 0x00 6. " F1HZ ,1 hz" "0,1"
|
|
bitfld.byte 0x00 5. " F2HZ ,2 hz" "0,1"
|
|
bitfld.byte 0x00 4. " F4HZ ,4 hz" "0,1"
|
|
bitfld.byte 0x00 3. " F8HZ ,8 hz" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 2. " F16HZ ,16 hz" "0,1"
|
|
bitfld.byte 0x00 1. " F32HZ ,32 hz" "0,1"
|
|
bitfld.byte 0x00 0. " F64HZ ,64 hz" "0,1"
|
|
if (((per.b(ad:0x40044000+0x24))&0x80)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "RSECCNT,Second Counter"
|
|
bitfld.byte 0x00 4.--6. " SEC10 ,10-Second count" "0,1,2,3,4,5,-,-"
|
|
bitfld.byte 0x00 0.--3. " SEC1 ,1-Second count" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "RMINCNT,Minute Counter"
|
|
bitfld.byte 0x00 4.--6. " MIN10 ,10-Minute count" "0,1,2,3,4,5,-,-"
|
|
bitfld.byte 0x00 0.--3. " MIN1 ,1-Minute count" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
if (((per.b(ad:0x40044000+0x24))&0x40)==0x40)
|
|
if (((per.b(ad:0x40044000+0x06))&0x30)<0x20)
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "RHRCNT,Hour Counter"
|
|
bitfld.byte 0x00 6. " PM ,PM" "AM,PM"
|
|
bitfld.byte 0x00 4.--5. " HR10 ,Counting ten's position of hours" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " HR1 ,Counting one's position of hours" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.b(ad:0x40044000+0x06))&0x30)==0x20)
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "RHRCNT,Hour Counter"
|
|
bitfld.byte 0x00 6. " PM ,PM" "AM,PM"
|
|
bitfld.byte 0x00 4.--5. " HR10 ,Counting ten's position of hours" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " HR1 ,Counting one's position of hours" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "RHRCNT,Hour Counter"
|
|
bitfld.byte 0x00 6. " PM ,PM" "AM,PM"
|
|
bitfld.byte 0x00 4.--5. " HR10 ,Counting ten's position of hours" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " HR1 ,Counting one's position of hours" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40044000+0x06))&0x30)<0x20)
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "RHRCNT,Hour Counter"
|
|
bitfld.byte 0x00 6. " PM ,PM" "AM,PM"
|
|
bitfld.byte 0x00 4.--5. " HR10 ,Counting ten's position of hours" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " HR1 ,Counting one's position of hours" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "RHRCNT,Hour Counter"
|
|
bitfld.byte 0x00 6. " PM ,PM" "AM,PM"
|
|
bitfld.byte 0x00 4.--5. " HR10 ,Counting ten's position of hours" "0,1,-,-"
|
|
bitfld.byte 0x00 0.--3. " HR1 ,Counting one's position of hours" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
endif
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "RWKCNT,Day-of-Week Counter"
|
|
bitfld.byte 0x00 0.--2. " DAYW ,Day-of-Week counting" "Sunday,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,-"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "BCNT0,Binary Counter 0"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "BCNT1,Binary Counter 1"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "BCNT2,Binary Counter 2"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "BCNT3,Binary Counter 3"
|
|
endif
|
|
if (((per.b(ad:0x40044000+0xC))&0x1F)==(0x4||0x6||0x9||0x11))
|
|
if (((per.b(ad:0x40044000+0xA))&0x30)<0x30)
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "RDAYCNT,Day Counter"
|
|
bitfld.byte 0x00 4.--5. " DATE10 ,Counting ten's position of dates" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " DATE1 ,Counting one's position of dates" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "RDAYCNT,Day Counter"
|
|
bitfld.byte 0x00 4.--5. " DATE10 ,Counting ten's position of dates" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " DATE1 ,Counting one's position of dates" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
elif ((((per.b(ad:0x40044000+0xC))&0x1F)==0x1)||(((per.b(ad:0x40044000+0xC))&0x1F)==0x3)||(((per.b(ad:0x40044000+0xC))&0x1F)==0x5)||(((per.b(ad:0x40044000+0xC))&0x1F)==0x7)||(((per.b(ad:0x40044000+0xC))&0x1F)==0x8)||(((per.b(ad:0x40044000+0xC))&0x1F)==0x10)||(((per.b(ad:0x40044000+0xC))&0x1F)==0x12))
|
|
if (((per.b(ad:0x40044000+0xA))&0x30)<0x30)
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "RDAYCNT,Day Counter"
|
|
bitfld.byte 0x00 4.--5. " DATE10 ,Counting ten's position of dates" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " DATE1 ,Counting one's position of dates" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "RDAYCNT,Day Counter"
|
|
bitfld.byte 0x00 4.--5. " DATE10 ,Counting ten's position of dates" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " DATE1 ,Counting one's position of dates" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
elif ((((per.b(ad:0x40044000+0xC))&0x1F)==0x2))
|
|
if ((((per.w(ad:0x40044000+0x0E))&0xFF)==(0x00||0x4||0x8||0x12||0x16||0x20||0x24||0x28)))||((((per.w(ad:0x40044000+0x0E))&0xFF)==(0x32||0x36||0x40||0x44||0x48)))||((((per.w(ad:0x40044000+0x0E))&0xFF)==(0x52||0x56||0x60||0x64||0x68||0x72||0x76||0x80)))||((((per.w(ad:0x40044000+0x0E))&0xFF)==(0x84||0x88||0x92||0x96)))
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "RDAYCNT,Day Counter"
|
|
bitfld.byte 0x00 4.--5. " DATE10 ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " DATE1 ,Counting one's position of dates" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "RDAYCNT,Day Counter"
|
|
bitfld.byte 0x00 4.--5. " DATE10 ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " DATE1 ,Counting one's position of dates" "0,1,2,3,4,5,6,7,8,-,-,-,-,-,-,-"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40044000+0xC))&0x1F)==0x00)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "RMONCNT,Month Counter"
|
|
bitfld.byte 0x00 4. " MON10 ,Counting ten's position of months" "-,1"
|
|
bitfld.byte 0x00 0.--3. " MON1 ,Counting one's position of months" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.b(ad:0x40044000+0xC))&0x10)<0x10)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "RMONCNT,Month Counter"
|
|
bitfld.byte 0x00 4. " MON10 ,Counting ten's position of months" "0,1"
|
|
bitfld.byte 0x00 0.--3. " MON1 ,Counting one's position of months" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "RMONCNT,Month Counter"
|
|
bitfld.byte 0x00 4. " MON10 ,Counting ten's position of months" "0,1"
|
|
bitfld.byte 0x00 0.--3. " MON1 ,Counting one's position of months" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
if (((per.b(ad:0x40044000+0x24))&0x01)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "RYRCNT,Year Counter"
|
|
bitfld.word 0x00 4.--7. " YR10 ,10-Year count" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.word 0x00 0.--3. " YR1 ,1-Year count" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
rgroup.word 0x0E++0x01
|
|
line.word 0x00 "RYRCNT,Year Counter"
|
|
bitfld.word 0x00 4.--7. " YR10 ,10-Year count" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.word 0x00 0.--3. " YR1 ,1-Year count" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
if (((per.b(ad:0x40044000+0x24))&0x80)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "RSECAR,Second Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,ENB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--6. " SEC10 ,10-Second count" "0,1,2,3,4,5,,"
|
|
bitfld.byte 0x00 0.--3. " SEC1 ,1-Second count" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "RMINCNT,Minute Alarm register"
|
|
bitfld.byte 0x00 7. " ENB ,ENB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--6. " MIN10 ,10-Minute count" "0,1,2,3,4,5,,"
|
|
bitfld.byte 0x00 0.--3. " MIN1 ,1-Minute count" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
if (((per.b(ad:0x40044000+0x24))&0x40)==0x40)
|
|
if (((per.b(ad:0x40044000+0x14))&0x30)<0x20)
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "RHRAR,Hour Alarm Register"
|
|
bitfld.byte 0x00 6. " PM ,PM" "AM,PM"
|
|
bitfld.byte 0x00 4.--5. " HR10 ,Counting ten's position of hours" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " HR1 ,Counting one's position of hours" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.b(ad:0x40044000+0x14))&0x30)==0x20)
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "RHRAR,Hour Alarm Register"
|
|
bitfld.byte 0x00 6. " PM ,PM" "AM,PM"
|
|
bitfld.byte 0x00 4.--5. " HR10 ,Counting ten's position of hours" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " HR1 ,Counting one's position of hours" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "RHRAR,Hour Alarm Register"
|
|
bitfld.byte 0x00 6. " PM ,PM" "AM,PM"
|
|
bitfld.byte 0x00 4.--5. " HR10 ,Counting ten's position of hours" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " HR1 ,Counting one's position of hours" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40044000+0x14))&0x30)<0x20)
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "RHRAR,Hour Alarm Register"
|
|
bitfld.byte 0x00 6. " PM ,PM" "AM,PM"
|
|
bitfld.byte 0x00 4.--5. " HR10 ,Counting ten's position of hours" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " HR1 ,Counting one's position of hours" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "RHRAR,Hour Alarm Register"
|
|
bitfld.byte 0x00 6. " PM ,PM" "AM,PM"
|
|
bitfld.byte 0x00 4.--5. " HR10 ,Counting ten's position of hours" "0,1,-,-"
|
|
bitfld.byte 0x00 0.--3. " HR1 ,Counting one's position of hours" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
endif
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "RWKAR,Day-of-Week Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,ENB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " DAYW ,Day-of-Week setting" "Sunday,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,-"
|
|
if ((((per.b(ad:0x40044000+0x1A))&0x1F)==0x4)||(((per.b(ad:0x40044000+0x1A))&0x1F)==0x6)||(((per.b(ad:0x40044000+0x1A))&0x1F)==0x9)||(((per.b(ad:0x40044000+0x1A))&0x1F)==0x11))
|
|
if (((per.b(ad:0x40044000+0x18))&0x30)<0x30)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "RDAYAR,Date Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,ENB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " DATE10 ,Counting ten's position of dates" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " DATE1 ,Counting one's position of dates" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "RDAYAR,Date Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,ENB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " DATE10 ,Counting ten's position of dates" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " DATE1 ,Counting one's position of dates" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
elif ((((per.b(ad:0x40044000+0x1A))&0x1F)==0x1)||(((per.b(ad:0x40044000+0x1A))&0x1F)==0x3)||(((per.b(ad:0x40044000+0x1A))&0x1F)==0x5)||(((per.b(ad:0x40044000+0x1A))&0x1F)==0x7)||(((per.b(ad:0x40044000+0x1A))&0x1F)==0x8)||(((per.b(ad:0x40044000+0x1A))&0x1F)==0x10)||(((per.b(ad:0x40044000+0x1A))&0x1F)==0x12))
|
|
if (((per.b(ad:0x40044000+0x18))&0x30)<0x30)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "RDAYAR,Date Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,ENB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " DATE10 ,Counting ten's position of dates" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " DATE1 ,Counting one's position of dates" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "RDAYAR,Date Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,ENB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " DATE10 ,Counting ten's position of dates" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " DATE1 ,Counting one's position of dates" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
else
|
|
if ((((per.w(ad:0x40044000+0x0E))&0xFF)==(0x00||0x4||0x8||0x12||0x16||0x20||0x24||0x28)))||((((per.w(ad:0x40044000+0x0E))&0xFF)==(0x32||0x36||0x40||0x44||0x48)))||((((per.w(ad:0x40044000+0x0E))&0xFF)==(0x52||0x56||0x60||0x64||0x68||0x72||0x76||0x80)))||((((per.w(ad:0x40044000+0x0E))&0xFF)==(0x84||0x88||0x92||0x96)))
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "RDAYAR,Date Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,ENB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " DATE10 ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " DATE1 ,Counting one's position of dates" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "RDAYAR,Date Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,ENB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " DATE10 ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " DATE1 ,Counting one's position of dates" "0,1,2,3,4,5,6,7,8,-,-,-,-,-,-,-"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40044000+0x1A))&0x1F)==0x00)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "RMONAR,Month Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,ENB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MON10 ,Counting ten's position of months" "-,1"
|
|
bitfld.byte 0x00 0.--3. " MON1 ,Counting one's position of months" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.b(ad:0x40044000+0x1A))&0x10)<0x10)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "RMONAR,Month Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,ENB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MON10 ,Counting ten's position of months" "0,1"
|
|
bitfld.byte 0x00 0.--3. " MON1 ,Counting one's position of months" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "RMONAR,Month Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,ENB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " MON10 ,Counting ten's position of months" "0,1"
|
|
bitfld.byte 0x00 0.--3. " MON1 ,Counting one's position of months" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "RYRAR,Year Alarm Register"
|
|
bitfld.word 0x00 4.--7. " YR10 ,10-Year count" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.word 0x00 0.--3. " YR1 ,1-Year count" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "RYRAREN,Year Alarm Enable Register"
|
|
bitfld.byte 0x00 7. " ENB ,Compare enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "BCNT0AR,Binary Counter 0 Alarm Register"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "BCNT1AR,Binary Counter 1 Alarm Register"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "BCNT2AR,Binary Counter 2 Alarm Register"
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "BCNT3AR,Binary Counter 3 Alarm Register"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "BCNT0AER,Binary Counter 0 Alarm Enable Register"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "BCNT1AER,Binary Counter 1 Alarm Enable Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "BCNT2AER,Binary Counter 2 Alarm Enable Register"
|
|
hexmask.word.BYTE 0x00 0.--7. 1. " ENB[23:16] ,Binary counter alarm enable register"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "BCNT3AER,Binary Counter 3 Alarm Enable Register"
|
|
endif
|
|
if (((per.w(ad:0x40044000+0x28))&0x1)==0x1)
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "RCR1,RTC Control Register 1"
|
|
bitfld.byte 0x00 4.--7. " PES ,Periodic interrupt select" ",,,,,,1/128,1/128,1/64,1/32,1/16,1/8,1/4,1/2,1,2"
|
|
bitfld.byte 0x00 3. " RTCOS ,RTCOUT output select" "1Hz,64Hz"
|
|
bitfld.byte 0x00 2. " PIE ,Periodic interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " CIE ,Carry interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " AIE ,Alarm interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "RCR1,RTC Control Register 1"
|
|
bitfld.byte 0x00 4.--7. " PES ,Periodic interrupt select" ",,,,,,1/256,1/128,1/64,1/32,1/16,1/8,1/4,1/2,1,2"
|
|
bitfld.byte 0x00 3. " RTCOS ,RTCOUT output select" "1Hz,64Hz"
|
|
bitfld.byte 0x00 2. " PIE ,Periodic interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " CIE ,Carry interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " AIE ,Alarm interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40044000+0x24))&0x80)==0x00)
|
|
if (((per.w(ad:0x40044000+0x28))&0x1)==0x1)
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "RCR2,RTC Control Register 2"
|
|
bitfld.byte 0x00 7. " CNTMD ,Count mode select" "Calendar,Binary"
|
|
bitfld.byte 0x00 6. " HR24 , hours mode" "12,24"
|
|
bitfld.byte 0x00 3. " RTCOE ,RTCOUT output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 2. " ADJ30 ,30-Second adjustment" "Not adjusting,Adjusting"
|
|
bitfld.byte 0x00 1. " RESET ,RTC software reset" "No reset,Reset"
|
|
bitfld.byte 0x00 0. " START ,Start" "Stopped,Operating normally"
|
|
else
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "RCR2,RTC Control Register 2"
|
|
bitfld.byte 0x00 7. " CNTMD ,Count mode select" "Calendar,Binary"
|
|
bitfld.byte 0x00 6. " HR24 , hours mode" "12,24"
|
|
bitfld.byte 0x00 5. " AADJP ,Automatic adjustment period select" "1min,10sec"
|
|
bitfld.byte 0x00 4. " AADJE ,Automatic adjustment enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 3. " RTCOE ,RTCOUT output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " ADJ30 ,30-Second adjustment" "Not adjusting,Adjusting"
|
|
bitfld.byte 0x00 1. " RESET ,RTC software reset" "No reset,Reset"
|
|
bitfld.byte 0x00 0. " START ,Start" "Stopped,Operating normally"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40044000+0x28))&0x1)==0x1)
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "RCR2,RTC Control Register 2"
|
|
bitfld.byte 0x00 7. " CNTMD ,Count mode select" "Calendar,Binary"
|
|
bitfld.byte 0x00 3. " RTCOE ,RTCOUT output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RESET ,RTC software reset" "No reset,Reset"
|
|
bitfld.byte 0x00 0. " START ,Start" "Stopped,Operating normally"
|
|
else
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "RCR2,RTC Control Register 2"
|
|
bitfld.byte 0x00 7. " CNTMD ,Count mode select" "Calendar,Binary"
|
|
bitfld.byte 0x00 5. " AADJP ,Automatic adjustment period select" "1min,10sec"
|
|
bitfld.byte 0x00 4. " AADJE ,Automatic adjustment enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " RTCOE ,RTCOUT output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " RESET ,RTC software reset" "No reset,Reset"
|
|
bitfld.byte 0x00 0. " START ,Start" "Stopped,Operating normally"
|
|
endif
|
|
endif
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "RCR4,RTC Control Register 4"
|
|
bitfld.byte 0x00 0. " RCKSEL ,Count source select" "Sub-clock,LOCO"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "RFRL,Frequency Register"
|
|
group.byte 0x2E++0x00
|
|
line.byte 0x00 "RADJ,Time Error Adjustment Register"
|
|
bitfld.byte 0x00 6.--7. " PMADJ ,Plus-Minus" "Not performed,Addition to prescaler,Subtraction from prescaler,?..."
|
|
bitfld.byte 0x00 0.--5. " ADJ ,Adjustment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "RTCCR0,Time Capture Control Register 0"
|
|
bitfld.byte 0x00 4.--5. " TCNF ,Time capture noise filter control" "Off,,/1,/32"
|
|
bitfld.byte 0x00 2. " TCST ,Time capture status" "Not detected,Detected"
|
|
bitfld.byte 0x00 0.--1. " TCCT ,Time capture control" "No event,Rising,Falling,Both"
|
|
group.byte 0x42++0x00
|
|
line.byte 0x00 "RTCCR1,Time Capture Control Register 1"
|
|
bitfld.byte 0x00 4.--5. " TCNF ,Time capture noise filter control" "Off,,/1,/32"
|
|
bitfld.byte 0x00 2. " TCST ,Time capture status" "Not detected,Detected"
|
|
bitfld.byte 0x00 0.--1. " TCCT ,Time capture control" "No event,Rising,Falling,Both"
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "RTCCR2,Time Capture Control Register 2"
|
|
bitfld.byte 0x00 4.--5. " TCNF ,Time capture noise filter control" "Off,,/1,/32"
|
|
bitfld.byte 0x00 2. " TCST ,Time capture status" "Not detected,Detected"
|
|
bitfld.byte 0x00 0.--1. " TCCT ,Time capture control" "No event,Rising,Falling,Both"
|
|
if (((per.b(ad:0x40044000))&0x80)==0x00)
|
|
rgroup.byte 0x52++0x00
|
|
line.byte 0x00 "RSECCP0,Second Capture Register 0"
|
|
bitfld.byte 0x00 4.--6. " SEC10 ,10-Second capture" "0,1,2,3,4,5,-,-"
|
|
bitfld.byte 0x00 0.--3. " SEC1 ,1-Second capture" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
rgroup.byte 0x52++0x00
|
|
line.byte 0x00 "BCNT0CP0,BCNT0 Capture Register 0"
|
|
endif
|
|
if (((per.b(ad:0x40044000))&0x80)==0x00)
|
|
rgroup.byte 0x62++0x00
|
|
line.byte 0x00 "RSECCP1,Second Capture Register 1"
|
|
bitfld.byte 0x00 4.--6. " SEC10 ,10-Second capture" "0,1,2,3,4,5,-,-"
|
|
bitfld.byte 0x00 0.--3. " SEC1 ,1-Second capture" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
rgroup.byte 0x62++0x00
|
|
line.byte 0x00 "BCNT0CP1,BCNT0 Capture Register 1"
|
|
endif
|
|
if (((per.b(ad:0x40044000))&0x80)==0x00)
|
|
rgroup.byte 0x72++0x00
|
|
line.byte 0x00 "RSECCP2,Second Capture Register 2"
|
|
bitfld.byte 0x00 4.--6. " SEC10 ,10-Second capture" "0,1,2,3,4,5,-,-"
|
|
bitfld.byte 0x00 0.--3. " SEC1 ,1-Second capture" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
rgroup.byte 0x72++0x00
|
|
line.byte 0x00 "BCNT0CP2,BCNT0 Capture Register 2"
|
|
endif
|
|
if (((per.b(ad:0x40044000))&0x80)==0x00)
|
|
rgroup.byte 0x54++0x00
|
|
line.byte 0x00 "RMINCP0,Minute Capture Register 0"
|
|
bitfld.byte 0x00 4.--6. " MIN10 ,10-Minute capture" "0,1,2,3,4,5,-,-"
|
|
bitfld.byte 0x00 0.--3. " MIN1 ,1-Minute capture" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
rgroup.byte 0x54++0x00
|
|
line.byte 0x00 "BCNT1CP0,BCNT1 Capture Register 0"
|
|
endif
|
|
if (((per.b(ad:0x40044000))&0x80)==0x00)
|
|
rgroup.byte 0x64++0x00
|
|
line.byte 0x00 "RMINCP1,Minute Capture Register 1"
|
|
bitfld.byte 0x00 4.--6. " MIN10 ,10-Minute capture" "0,1,2,3,4,5,-,-"
|
|
bitfld.byte 0x00 0.--3. " MIN1 ,1-Minute capture" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
rgroup.byte 0x64++0x00
|
|
line.byte 0x00 "BCNT1CP1,BCNT1 Capture Register 1"
|
|
endif
|
|
if (((per.b(ad:0x40044000))&0x80)==0x00)
|
|
rgroup.byte 0x74++0x00
|
|
line.byte 0x00 "RMINCP2,Minute Capture Register 2"
|
|
bitfld.byte 0x00 4.--6. " MIN10 ,10-Minute capture" "0,1,2,3,4,5,-,-"
|
|
bitfld.byte 0x00 0.--3. " MIN1 ,1-Minute capture" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
rgroup.byte 0x74++0x00
|
|
line.byte 0x00 "BCNT1CP2,BCNT1 Capture Register 2"
|
|
endif
|
|
if (((per.b(ad:0x40044000))&0x80)==0x00)
|
|
rgroup.byte 0x56++0x00
|
|
line.byte 0x00 "RHRCP0,Hour Capture Register 0"
|
|
bitfld.byte 0x00 6. " PM ,PM" "AM,PM"
|
|
bitfld.byte 0x00 4.--5. " HR10 ,10-Hour capture" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " HR1 ,1-Hour capture" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
rgroup.byte 0x56++0x00
|
|
line.byte 0x00 "BCNT2CP0,BCNT2 Capture Register 0"
|
|
endif
|
|
if (((per.b(ad:0x40044000))&0x80)==0x00)
|
|
rgroup.byte 0x66++0x00
|
|
line.byte 0x00 "RHRCP1,Hour Capture Register 1"
|
|
bitfld.byte 0x00 6. " PM ,PM" "AM,PM"
|
|
bitfld.byte 0x00 4.--5. " HR10 ,10-Hour capture" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " HR1 ,1-Hour capture" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
rgroup.byte 0x66++0x00
|
|
line.byte 0x00 "BCNT2CP1,BCNT2 Capture Register 1"
|
|
endif
|
|
if (((per.b(ad:0x40044000))&0x80)==0x00)
|
|
rgroup.byte 0x76++0x00
|
|
line.byte 0x00 "RHRCP2,Hour Capture Register 2"
|
|
bitfld.byte 0x00 6. " PM ,PM" "AM,PM"
|
|
bitfld.byte 0x00 4.--5. " HR10 ,10-Hour capture" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. " HR1 ,1-Hour capture" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
rgroup.byte 0x76++0x00
|
|
line.byte 0x00 "BCNT2CP2,BCNT2 Capture Register 2"
|
|
endif
|
|
if (((per.b(ad:0x40044000))&0x80)==0x00)
|
|
rgroup.byte 0x5A++0x00
|
|
line.byte 0x00 "RDAYCP0,Date Capture Register 0"
|
|
bitfld.byte 0x00 4.--5. " DATE10 ,10-Day capture" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " DATE1 ,1-Day capture" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
rgroup.byte 0x5A++0x00
|
|
line.byte 0x00 "BCNT3CP0,BCNT3 Capture Register 0"
|
|
endif
|
|
if (((per.b(ad:0x40044000))&0x80)==0x00)
|
|
rgroup.byte 0x6A++0x00
|
|
line.byte 0x00 "RDAYCP1,Date Capture Register 1"
|
|
bitfld.byte 0x00 4.--5. " DATE10 ,10-Day capture" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " DATE1 ,1-Day capture" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
rgroup.byte 0x6A++0x00
|
|
line.byte 0x00 "BCNT3CP1,BCNT3 Capture Register 1"
|
|
endif
|
|
if (((per.b(ad:0x40044000))&0x80)==0x00)
|
|
rgroup.byte 0x7A++0x00
|
|
line.byte 0x00 "RDAYCP2,Date Capture Register 2"
|
|
bitfld.byte 0x00 4.--5. " DATE10 ,10-Day capture" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " DATE1 ,1-Day capture" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
rgroup.byte 0x7A++0x00
|
|
line.byte 0x00 "BCNT3CP2,BCNT3 Capture Register 2"
|
|
endif
|
|
if (((per.b(ad:0x40044000))&0x80)==0x00)
|
|
rgroup.byte 0x5C++0x00
|
|
line.byte 0x00 "RMONCP0,Month Capture Register 0"
|
|
bitfld.byte 0x00 4. " MON10 ,10-Month capture" "0,1"
|
|
bitfld.byte 0x00 0.--3. " MON1 ,1-Month capture" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
hgroup.byte 0x5C++0x00
|
|
hide.byte 0x00 "RMONCP0,Month Capture Register 0"
|
|
endif
|
|
if (((per.b(ad:0x40044000))&0x80)==0x00)
|
|
rgroup.byte 0x6C++0x00
|
|
line.byte 0x00 "RMONCP1,Month Capture Register 1"
|
|
bitfld.byte 0x00 4. " MON10 ,10-Month capture" "0,1"
|
|
bitfld.byte 0x00 0.--3. " MON1 ,1-Month capture" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
hgroup.byte 0x6C++0x00
|
|
hide.byte 0x00 "RMONCP1,Month Capture Register 1"
|
|
endif
|
|
if (((per.b(ad:0x40044000))&0x80)==0x00)
|
|
rgroup.byte 0x7C++0x00
|
|
line.byte 0x00 "RMONCP2,Month Capture Register 2"
|
|
bitfld.byte 0x00 4. " MON10 ,10-Month capture" "0,1"
|
|
bitfld.byte 0x00 0.--3. " MON1 ,1-Month capture" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
hgroup.byte 0x7C++0x00
|
|
hide.byte 0x00 "RMONCP2,Month Capture Register 2"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x40044200
|
|
width 10.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "WDTRR,WDT Refresh Register"
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "WDTCR,WDT Control Register"
|
|
bitfld.word 0x00 12.--13. " RPSS ,Window Start Position Selection" "25%,50%,75%,100%"
|
|
bitfld.word 0x00 8.--9. " RPES ,Window End Position Selection" "75%,50%,25%,0%"
|
|
bitfld.word 0x00 4.--7. " CKS ,Clock Division Ratio Selection" ",/4,,,/64,,/512,/2048,/8192,,,,,,,/128"
|
|
bitfld.word 0x00 0.--1. " TOPS ,Timeout Period Selection" "1024 cycles,4096 cycles,8192 cycles,16384 cycles"
|
|
line.word 0x02 "WDTSR,WDT Status Register"
|
|
bitfld.word 0x02 15. " REFEF ,Refresh Error Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x02 14. " UNDFF ,Underflow Flag" "Not occurred,Occurred"
|
|
hexmask.word 0x02 0.--13. 1. " CNTVAL ,Down-Counter Value"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "WDTRCR,WDT Reset Control Register"
|
|
bitfld.byte 0x00 7. " RSTIRQS ,Reset Interrupt Request Selection" "Normal,Reset"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "WDTCSTPR,WDT Count Stop Control Register"
|
|
bitfld.byte 0x00 7. " SLCSTP ,Sleep-Mode Count Stop Control" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "IWDT (Independent Watchdog Timer)"
|
|
base ad:0x40044400
|
|
width 8.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "IWDTRR,IWDT Refresh Register"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IWDTSR,IWDT Status Register"
|
|
bitfld.word 0x00 15. " REFEF ,Refresh error flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 14. " UNDFF ,Underflow flag" "Not occurred,Occurred"
|
|
hexmask.word 0x00 0.--13. 1. " CNTVAL ,Counter value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "USBFS (USB 2.0 Full-Speed Module)"
|
|
base ad:0x40090000
|
|
width 12.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SYSCFG,System Configuration Control Register"
|
|
bitfld.word 0x00 10. " SCKE ,USB Clock Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CNEN ,CNEN Single End Receiver Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " DCFM ,Controller Function Select" "Device,Host"
|
|
bitfld.word 0x00 5. " DRPD ,D_Plus/D_Minus Line Resistor Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DPRPU ,D_Plus Line Resistor Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " DMRPU ,D_Minus Line Resistor Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " USBE ,USBFS Operation Enable" "Disabled,Enabled"
|
|
if (((per.w(ad:0x40090000))&0x10)==0x0)&&(((per.w(ad:0x40090000))&0x8)==0x0)
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "SYSSTS0,System Configuration Status Register 0"
|
|
bitfld.word 0x00 15. " OVCMONA ,External USB_OVRCURA Input Pin Monitor" "Low,High"
|
|
bitfld.word 0x00 14. " OVCMONB ,External USB_OVRCURB Input Pin Monitor" "Low,High"
|
|
bitfld.word 0x00 6. " HTACT ,USB Host Sequencer Status Monitor" "Stopped,Not stopped"
|
|
bitfld.word 0x00 2. " IDMON ,External ID0 Input Pin Monitor" "Low,High"
|
|
elif (((per.w(ad:0x40090000))&0x10)==0x10)&&(((per.w(ad:0x40090000))&0x8)==0x0)
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "SYSSTS0,System Configuration Status Register 0"
|
|
bitfld.word 0x00 15. " OVCMONA ,External USB_OVRCURA Input Pin Monitor" "Low,High"
|
|
bitfld.word 0x00 14. " OVCMONB ,External USB_OVRCURB Input Pin Monitor" "Low,High"
|
|
bitfld.word 0x00 6. " HTACT ,USB Host Sequencer Status Monitor" "Stopped,Not stopped"
|
|
bitfld.word 0x00 2. " IDMON ,External ID0 Input Pin Monitor" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " LNST ,USB Data Line Status Monitor" "SE0,J-State,K-State,SE1"
|
|
elif (((per.w(ad:0x40090000))&0x8)==0x8)&&(((per.w(ad:0x40090000))&0x10)==0x0)
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "SYSSTS0,System Configuration Status Register 0"
|
|
bitfld.word 0x00 15. " OVCMONA ,External USB_OVRCURA Input Pin Monitor" "Low,High"
|
|
bitfld.word 0x00 14. " OVCMONB ,External USB_OVRCURB Input Pin Monitor" "Low,High"
|
|
bitfld.word 0x00 6. " HTACT ,USB Host Sequencer Status Monitor" "Stopped,Not stopped"
|
|
bitfld.word 0x00 2. " IDMON ,External ID0 Input Pin Monitor" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " LNST ,USB Data Line Status Monitor" "SE0,K-State,J-State,SE1"
|
|
endif
|
|
if (((per.w(ad:0x40090000))&0x40)==0x40)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "DVSTCTR0,Device State Control Register 0"
|
|
bitfld.word 0x00 11. " HNPBTOA ,Host Negotiation Protocol (HNP) Control" "Normal,Suspend"
|
|
bitfld.word 0x00 10. " EXICEN ,USB_EXICEN Output Pin Control" "Low,High"
|
|
bitfld.word 0x00 9. " VBUSEN ,USB_VBUSEN Output Pin Control" "Low,High"
|
|
bitfld.word 0x00 8. " WKUP ,Wakeup Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " RWUPE ,Wakeup Detection Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " USBRST ,USB Bus Reset Output" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RESUME ,Resume Output" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " UACT ,USB Bus Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--2. " RHST ,USB Bus Reset Status" "Indeterminate speed,Low-speed,Full-speed,Reset,Reset,Reset,Reset,Reset"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "DVSTCTR0,Device State Control Register 0"
|
|
bitfld.word 0x00 11. " HNPBTOA ,Host Negotiation Protocol (HNP) Control" "Normal,Suspend"
|
|
bitfld.word 0x00 10. " EXICEN ,USB_EXICEN Output Pin Control" "Low,High"
|
|
bitfld.word 0x00 9. " VBUSEN ,USB_VBUSEN Output Pin Control" "Low,High"
|
|
bitfld.word 0x00 8. " WKUP ,Wakeup Output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " RWUPE ,Wakeup Detection Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " USBRST ,USB Bus Reset Output" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RESUME ,Resume Output" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " UACT ,USB Bus Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--2. " RHST ,USB Bus Reset Status" "Indeterminate speed,Reset/Low-speed,Reset/Full-speed,?..."
|
|
endif
|
|
if (((per.w(ad:0x40090000+0x20))&0x400)==0x0)
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "CFIFOL,CFIFO Port Register"
|
|
else
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "CFIFO,CFIFO Port Register"
|
|
in
|
|
endif
|
|
if (((per.w(ad:0x40090000+0x28))&0x400)==0x0)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "D0FIFOL,D0FIFO Port Register"
|
|
else
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "D0FIFO,D0FIFO Port Register"
|
|
in
|
|
endif
|
|
if (((per.w(ad:0x40090000+0x2C))&0x400)==0x0)
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "D1FIFOL,D1FIFO Port Register"
|
|
else
|
|
hgroup.word 0x1C++0x01
|
|
hide.word 0x00 "D1FIFO,D1FIFO Port Register"
|
|
in
|
|
endif
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "CFIFOSEL,CFIFO Port Select Register"
|
|
bitfld.word 0x00 15. " RCNT ,Read Count Mode" "Cleared,Decremented"
|
|
bitfld.word 0x00 14. " REW ,Buffer Pointer Rewind" "Not rewound,Rewound"
|
|
bitfld.word 0x00 10. " MBW ,CFIFO Port Access Bit Width" "8-bit,16-bit"
|
|
bitfld.word 0x00 8. " BIGEND ,CFIFO Port Endian Control" "Little,Big"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ISEL ,CFIFO Port Access Direction When DCP is Selected" "Reading,Writing"
|
|
bitfld.word 0x00 0.--3. " CURPIPE ,CFIFO Port Access Pipe Specification" "DCP,Pipe 1,Pipe 2,Pipe 3,Pipe 4,Pipe 5,Pipe 6,Pipe 7,Pipe 8,Pipe 9,?..."
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "D0FIFOSEL,D0FIFO Port Select Register"
|
|
bitfld.word 0x00 15. " RCNT ,Read Count Mode" "Cleared,Decremented"
|
|
bitfld.word 0x00 14. " REW ,Buffer Pointer Rewind" "Not rewound,Rewound"
|
|
bitfld.word 0x00 13. " DCLRM ,Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DREQE ,DMA/DTC Transfer Request Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " MBW ,FIFO Port Access Bit Width" "8-bit,16-bit"
|
|
bitfld.word 0x00 8. " BIGEND ,FIFO Port Endian Control" "Little,Big"
|
|
bitfld.word 0x00 0.--3. " CURPIPE ,FIFO Port Access Pipe Specification" "DCP,Pipe 1,Pipe 2,Pipe 3,Pipe 4,Pipe 5,Pipe 6,Pipe 7,Pipe 8,Pipe 9,?..."
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "D1FIFOSEL,D1FIFO Port Select Register"
|
|
bitfld.word 0x00 15. " RCNT ,Read Count Mode" "Cleared,Decremented"
|
|
bitfld.word 0x00 14. " REW ,Buffer Pointer Rewind" "Not rewound,Rewound"
|
|
bitfld.word 0x00 13. " DCLRM ,Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DREQE ,DMA/DTC Transfer Request Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " MBW ,FIFO Port Access Bit Width" "8-bit,16-bit"
|
|
bitfld.word 0x00 8. " BIGEND ,FIFO Port Endian Control" "Little,Big"
|
|
bitfld.word 0x00 0.--3. " CURPIPE ,FIFO Port Access Pipe Specification" "DCP,Pipe 1,Pipe 2,Pipe 3,Pipe 4,Pipe 5,Pipe 6,Pipe 7,Pipe 8,Pipe 9,?..."
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "CFIFOCTR,CFIFO Port Control Register"
|
|
bitfld.word 0x00 15. " BVAL ,Buffer Memory Valid Flag" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " BCLR ,CPU Buffer Clear" "Not cleared,Cleared"
|
|
rbitfld.word 0x00 13. " FRDY ,FIFO Port Ready" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--8. 1. " DTLN ,Receive Data Length"
|
|
group.word 0x2A++0x01
|
|
line.word 0x00 "D0FIFOCTR,D0FIFO Port Control Register"
|
|
bitfld.word 0x00 15. " BVAL ,Buffer Memory Valid Flag" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " BCLR ,CPU Buffer Clear" "Not cleared,Cleared"
|
|
rbitfld.word 0x00 13. " FRDY ,FIFO Port Ready" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--8. 1. " DTLN ,Receive Data Length"
|
|
group.word 0x2E++0x01
|
|
line.word 0x00 "D1FIFOCTR,D1FIFO Port Control Register"
|
|
bitfld.word 0x00 15. " BVAL ,Buffer Memory Valid Flag" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " BCLR ,CPU Buffer Clear" "Not cleared,Cleared"
|
|
rbitfld.word 0x00 13. " FRDY ,FIFO Port Ready" "Disabled,Enabled"
|
|
hexmask.word 0x00 0.--8. 1. " DTLN ,Receive Data Length"
|
|
group.word 0x30++0x03
|
|
line.word 0x00 "INTENB0,Interrupt Enable Register 0"
|
|
bitfld.word 0x00 15. " VBSE ,VBUS Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RSME ,Resume Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SOFE ,Frame Number Update Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " DVSE ,Device State Transition Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CTRE ,Control Transfer Stage Transition Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " BEMPE ,Buffer Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " NRDYE ,Buffer Not Ready Response Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " BRDYE ,Buffer Ready Interrupt Enable" "Disabled,Enabled"
|
|
line.word 0x02 "INTENB1,Interrupt Enable Register 1"
|
|
bitfld.word 0x02 15. " OVRCRE ,Overcurrent Input Change Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 15. " BCHGE ,USB Bus Change Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 12. " DTCHE ,Disconnection Detection Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 11. " ATTCHE ,Connection Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x02 6. " EOFERRE ,EOF Error Detection Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " SIGNE ,Setup Transaction Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " SACKE ,Setup Transaction Normal Response Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " PDDETINTE0 ,PDDETINT0 Detection Interrupt Enable" "Disabled,Enabled"
|
|
group.word 0x36++0x07
|
|
line.word 0x00 "BRDYENB,BRDY Interrupt Enable Register"
|
|
bitfld.word 0x00 9. " PIPE9BRDYE ,BRDY Interrupt Enable for PIPE9" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PIPE8BRDYE ,BRDY Interrupt Enable for PIPE8" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " PIPE7BRDYE ,BRDY Interrupt Enable for PIPE7" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " PIPE6BRDYE ,BRDY Interrupt Enable for PIPE6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PIPE5BRDYE ,BRDY Interrupt Enable for PIPE5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " PIPE4BRDYE ,BRDY Interrupt Enable for PIPE4" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " PIPE3BRDYE ,BRDY Interrupt Enable for PIPE3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " PIPE2BRDYE ,BRDY Interrupt Enable for PIPE2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " PIPE1BRDYE ,BRDY Interrupt Enable for PIPE1" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " PIPE0BRDYE ,BRDY Interrupt Enable for PIPE0" "Disabled,Enabled"
|
|
line.word 0x02 "NRDYENN,NRDY Interrupt Enable Register"
|
|
bitfld.word 0x02 9. " PIPE9NRDYE ,NRDY Interrupt Enable for PIPE9" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " PIPE8NRDYE ,NRDY Interrupt Enable for PIPE8" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " PIPE7NRDYE ,NRDY Interrupt Enable for PIPE7" "Disabled,Enabled"
|
|
bitfld.word 0x02 6. " PIPE6NRDYE ,NRDY Interrupt Enable for PIPE6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x02 5. " PIPE5NRDYE ,NRDY Interrupt Enable for PIPE5" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " PIPE4NRDYE ,NRDY Interrupt Enable for PIPE4" "Disabled,Enabled"
|
|
bitfld.word 0x02 3. " PIPE3NRDYE ,NRDY Interrupt Enable for PIPE3" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " PIPE2NRDYE ,NRDY Interrupt Enable for PIPE2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x02 1. " PIPE1NRDYE ,NRDY Interrupt Enable for PIPE1" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " PIPE0NRDYE ,NRDY Interrupt Enable for PIPE0" "Disabled,Enabled"
|
|
line.word 0x04 "BEMPENB,BEMP Interrupt Enable Register"
|
|
bitfld.word 0x04 9. " PIPE9BEMPE ,BEMP Interrupt Enable for PIPE9" "Disabled,Enabled"
|
|
bitfld.word 0x04 8. " PIPE8BEMPE ,BEMP Interrupt Enable for PIPE8" "Disabled,Enabled"
|
|
bitfld.word 0x04 7. " PIPE7BEMPE ,BEMP Interrupt Enable for PIPE7" "Disabled,Enabled"
|
|
bitfld.word 0x04 6. " PIPE6BEMPE ,BEMP Interrupt Enable for PIPE6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 5. " PIPE5BEMPE ,BEMP Interrupt Enable for PIPE5" "Disabled,Enabled"
|
|
bitfld.word 0x04 4. " PIPE4BEMPE ,BEMP Interrupt Enable for PIPE4" "Disabled,Enabled"
|
|
bitfld.word 0x04 3. " PIPE3BEMPE ,BEMP Interrupt Enable for PIPE3" "Disabled,Enabled"
|
|
bitfld.word 0x04 2. " PIPE2BEMPE ,BEMP Interrupt Enable for PIPE2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 1. " PIPE1BEMPE ,BEMP Interrupt Enable for PIPE1" "Disabled,Enabled"
|
|
bitfld.word 0x04 0. " PIPE0BEMPE ,BEMP Interrupt Enable for PIPE0" "Disabled,Enabled"
|
|
line.word 0x06 "SOFCFG,SOF Output Configuration Register"
|
|
bitfld.word 0x06 8. " TRNENSEL ,Transaction-Enabled Time Select" "Not low-speed,Low-speed"
|
|
bitfld.word 0x06 6. " BRDYM ,BRDY Interrupt Status Clear Timing" "Software,USBFS"
|
|
rbitfld.word 0x06 4. " EDGESTS ,Edge Interrupt Output Status Monitor" "Not processing,Processing"
|
|
group.word 0x40++0x03
|
|
line.word 0x00 "INTSTS0,Interrupt Status Register 0"
|
|
bitfld.word 0x00 15. " VBINT ,VBUS Interrupt Status" "Not generated,Generated"
|
|
bitfld.word 0x00 14. " RESM ,Resume Interrupt Status" "Not generated,Generated"
|
|
bitfld.word 0x00 13. " SOFR ,Frame Number Refresh Interrupt Status" "Not generated,Generated"
|
|
bitfld.word 0x00 12. " DVST ,Device State Transition Interrupt Status" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CTRT ,Control Transfer Stage Transition Interrupt Status" "Not generated,Generated"
|
|
rbitfld.word 0x00 10. " BEMP ,Buffer Empty Interrupt Status" "Not generated,Generated"
|
|
rbitfld.word 0x00 9. " NRDY ,Buffer Not Ready Interrupt Status" "Not generated,Generated"
|
|
rbitfld.word 0x00 8. " BRDY ,Buffer Ready Interrupt Status" "Not generated,Generated"
|
|
textline " "
|
|
rbitfld.word 0x00 7. " VBSTS ,VBUS Input Status" "Low,High"
|
|
rbitfld.word 0x00 4.--6. " DVSQ ,Device State" "Powered state,Default state,Address state,Configured state,Suspended state,Suspended state,Suspended state,Suspended state"
|
|
bitfld.word 0x00 3. " VALID ,USB Request Reception" "Not received,Received"
|
|
rbitfld.word 0x00 0.--2. " CTSQ ,Control Transfer Stage" "Idle or setup,Read data,Read status,Write data,Write status,Write (no data) status,Transfer sequence error,"
|
|
line.word 0x02 "INTSTS1,Interrupt Status Register 1"
|
|
bitfld.word 0x02 15. " OVRCR ,Over Current Input Change Interrupt Status" "Not generated,Generated"
|
|
bitfld.word 0x02 14. " BCHG ,USB Bus Change Interrupt Status" "Not generated,Generated"
|
|
bitfld.word 0x02 12. " DTCH ,USB Disconnection Detection Interrupt Status" "Not generated,Generated"
|
|
bitfld.word 0x02 11. " ATTCH ,ATTCH Interrupt Status" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.word 0x02 6. " EOFERR ,EOF Error Detection Interrupt Status" "Not generated,Generated"
|
|
bitfld.word 0x02 5. " SIGN ,Setup Transaction Error Interrupt Status" "Not generated,Generated"
|
|
bitfld.word 0x02 4. " SACK ,Setup Transaction Normal Response Interrupt Status" "Not generated,Generated"
|
|
bitfld.word 0x02 0. " PDDETINT0 ,PDDET0 Detection Interrupt Status" "Not generated,Generated"
|
|
group.word 0x46++0x07
|
|
line.word 0x00 "BRDYSTS,BRDY Interrupt Status Register"
|
|
bitfld.word 0x00 9. " PIPE9BRDY ,BRDY Interrupt Status for PIPE9" "Not generated,Generated"
|
|
bitfld.word 0x00 8. " PIPE8BRDY ,BRDY Interrupt Status for PIPE8" "Not generated,Generated"
|
|
bitfld.word 0x00 7. " PIPE7BRDY ,BRDY Interrupt Status for PIPE7" "Not generated,Generated"
|
|
bitfld.word 0x00 6. " PIPE6BRDY ,BRDY Interrupt Status for PIPE6" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PIPE5BRDY ,BRDY Interrupt Status for PIPE5" "Not generated,Generated"
|
|
bitfld.word 0x00 4. " PIPE4BRDY ,BRDY Interrupt Status for PIPE4" "Not generated,Generated"
|
|
bitfld.word 0x00 3. " PIPE3BRDY ,BRDY Interrupt Status for PIPE3" "Not generated,Generated"
|
|
bitfld.word 0x00 2. " PIPE2BRDY ,BRDY Interrupt Status for PIPE2" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.word 0x00 1. " PIPE1BRDY ,BRDY Interrupt Status for PIPE1" "Not generated,Generated"
|
|
bitfld.word 0x00 0. " PIPE0BRDY ,BRDY Interrupt Status for PIPE0" "Not generated,Generated"
|
|
line.word 0x02 "NRDYSTS,NRDY Interrupt Status Register"
|
|
bitfld.word 0x02 9. " PIPE9NRDY ,NRDY Interrupt Status for PIPE9" "Not generated,Generated"
|
|
bitfld.word 0x02 8. " PIPE8NRDY ,NRDY Interrupt Status for PIPE8" "Not generated,Generated"
|
|
bitfld.word 0x02 7. " PIPE7NRDY ,NRDY Interrupt Status for PIPE7" "Not generated,Generated"
|
|
bitfld.word 0x02 6. " PIPE6NRDY ,NRDY Interrupt Status for PIPE6" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.word 0x02 5. " PIPE5NRDY ,NRDY Interrupt Status for PIPE5" "Not generated,Generated"
|
|
bitfld.word 0x02 4. " PIPE4NRDY ,NRDY Interrupt Status for PIPE4" "Not generated,Generated"
|
|
bitfld.word 0x02 3. " PIPE3NRDY ,NRDY Interrupt Status for PIPE3" "Not generated,Generated"
|
|
bitfld.word 0x02 2. " PIPE2NRDY ,NRDY Interrupt Status for PIPE2" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.word 0x02 1. " PIPE1NRDY ,NRDY Interrupt Status for PIPE1" "Not generated,Generated"
|
|
bitfld.word 0x02 0. " PIPE0NRDY ,NRDY Interrupt Status for PIPE0" "Not generated,Generated"
|
|
line.word 0x04 "BEMPSTS,BEMP Interrupt Status Register"
|
|
bitfld.word 0x04 9. " PIPE9BEMP ,BEMP Interrupt Status for PIPE9" "Not generated,Generated"
|
|
bitfld.word 0x04 8. " PIPE8BEMP ,BEMP Interrupt Status for PIPE8" "Not generated,Generated"
|
|
bitfld.word 0x04 7. " PIPE7BEMP ,BEMP Interrupt Status for PIPE7" "Not generated,Generated"
|
|
bitfld.word 0x04 6. " PIPE6BEMP ,BEMP Interrupt Status for PIPE6" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.word 0x04 5. " PIPE5BEMP ,BEMP Interrupt Status for PIPE5" "Not generated,Generated"
|
|
bitfld.word 0x04 4. " PIPE4BEMP ,BEMP Interrupt Status for PIPE4" "Not generated,Generated"
|
|
bitfld.word 0x04 3. " PIPE3BEMP ,BEMP Interrupt Status for PIPE3" "Not generated,Generated"
|
|
bitfld.word 0x04 2. " PIPE2BEMP ,BEMP Interrupt Status for PIPE2" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.word 0x04 1. " PIPE1BEMP ,BEMP Interrupt Status for PIPE1" "Not generated,Generated"
|
|
bitfld.word 0x04 0. " PIPE0BEMP ,BEMP Interrupt Status for PIPE0" "Not generated,Generated"
|
|
line.word 0x06 "FRMNUM,Frame Number Register"
|
|
bitfld.word 0x06 15. " OVRN ,Overrun/Underrun Detection Status" "No error,Error"
|
|
bitfld.word 0x06 14. " CRCE ,Receive Data Error" "No error,Error"
|
|
hexmask.word 0x06 0.--10. 1. " FRNM ,Frame Number"
|
|
if (((per.w(ad:0x40090000))&0x40)==0x0)
|
|
rgroup.word 0x54++0x07
|
|
line.word 0x00 "USBREQ,USB Request Type Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " BREQUEST ,Request"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BMREQUESTTYPE ,Request Type"
|
|
line.word 0x02 "USBVAL,USB Request Value Register"
|
|
line.word 0x04 "USBINDX,USB Request Index Register"
|
|
line.word 0x06 "USBLENG,USB Request Length Register"
|
|
else
|
|
group.word 0x54++0x07
|
|
line.word 0x00 "USBREQ,USB Request Type Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " BREQUEST ,Request"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BMREQUESTTYPE ,Request Type"
|
|
line.word 0x02 "USBVAL,USB Request Value Register"
|
|
line.word 0x04 "USBINDX,USB Request Index Register"
|
|
line.word 0x06 "USBLENG,USB Request Length Register"
|
|
endif
|
|
group.word 0x5C++0x05
|
|
line.word 0x00 "DCPCFG,DCP Configuration Register"
|
|
bitfld.word 0x00 7. " SHTNAK ,Pipe Disabled at End of Transfer" "No,Yes"
|
|
bitfld.word 0x00 4. " DIR ,Transfer Direction" "Received,Transmitted"
|
|
line.word 0x02 "DCPMAXP,DCP Maximum Packet Size Register"
|
|
bitfld.word 0x02 12.--15. " DEVSEL ,Device Select" "0000,0001,0010,0011,0100,0101,?..."
|
|
hexmask.word.byte 0x02 0.--6. 1. " MXPS ,Maximum Packet Size"
|
|
line.word 0x04 "DCPCTR,DCP Control Register"
|
|
rbitfld.word 0x04 15. " BSTS ,Buffer Status" "Disabled,Enabled"
|
|
bitfld.word 0x04 14. " SUREQ ,Setup Token Transmission" "No effect,Transmitted"
|
|
bitfld.word 0x04 11. " SUREQCLR ,SUREQ Bit Clear" "No effect,Cleared"
|
|
bitfld.word 0x04 8. " SQCLR ,Sequence Toggle Bit Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.word 0x04 7. " SQSET ,Sequence Toggle Bit Set" "No effect,Set"
|
|
rbitfld.word 0x04 6. " SQMON ,Sequence Toggle Bit Monitor" "DATA0,DATA1"
|
|
rbitfld.word 0x04 5. " PBUSY ,Pipe Busy" "Not used,Used"
|
|
bitfld.word 0x04 2. " CCPL ,Control Transfer End Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 0.--1. " PID ,Response PID" "NAK,BUF,STALL,STALL"
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "PIPESEL,Pipe Window Select Register"
|
|
bitfld.word 0x00 0.--3. " PIPESEL ,Pipe Window Select" "No pipe,PIPE1,PIPE2,PIPE3,PIPE4,PIPE5,PIPE6,PIPE7,PIPE8,PIPE9,?..."
|
|
if (((per.w(ad:0x40090000+0x64))&0xF)==0x0)
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "PIPECFG,Pipe Configuration Register"
|
|
bitfld.word 0x00 10. " BFRE ,BRDY Interrupt Operation Specification" "TX/RX,Completion"
|
|
bitfld.word 0x00 9. " DBLB ,Double Buffer Mode" "Single,Double"
|
|
bitfld.word 0x00 7. " SHTNAK ,Pipe Disabled at End of Transfer" "No,Yes"
|
|
bitfld.word 0x00 4. " DIR ,Transfer Direction" "Receiving,Transmitting"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " EPNUM ,Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.w(ad:0x40090000+0x64))&0xF)==0x1)||(((per.w(ad:0x40090000+0x64))&0xF)==0x2)
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "PIPECFG,Pipe Configuration Register"
|
|
bitfld.word 0x00 14.--15. " TYPE ,Transfer Type" "Pipe not used,Bulk,,Isochronous"
|
|
bitfld.word 0x00 10. " BFRE ,BRDY Interrupt Operation Specification" "TX/RX,Completion"
|
|
bitfld.word 0x00 9. " DBLB ,Double Buffer Mode" "Single,Double"
|
|
bitfld.word 0x00 7. " SHTNAK ,Pipe Disabled at End of Transfer" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Transfer Direction" "Receiving,Transmitting"
|
|
bitfld.word 0x00 0.--3. " EPNUM ,Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.w(ad:0x40090000+0x64))&0xF)==0x3)||(((per.w(ad:0x40090000+0x64))&0xF)==0x4)||(((per.w(ad:0x40090000+0x64))&0xF)==0x5)
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "PIPECFG,Pipe Configuration Register"
|
|
bitfld.word 0x00 14.--15. " TYPE ,Transfer Type" "Pipe not used,Bulk,,"
|
|
bitfld.word 0x00 10. " BFRE ,BRDY Interrupt Operation Specification" "TX/RX,Completion"
|
|
bitfld.word 0x00 9. " DBLB ,Double Buffer Mode" "Single,Double"
|
|
bitfld.word 0x00 7. " SHTNAK ,Pipe Disabled at End of Transfer" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Transfer Direction" "Receiving,Transmitting"
|
|
bitfld.word 0x00 0.--3. " EPNUM ,Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.w(ad:0x40090000+0x64))&0xF)==0x6)||(((per.w(ad:0x40090000+0x64))&0xF)==0x7)||(((per.w(ad:0x40090000+0x64))&0xF)==0x8)||(((per.w(ad:0x40090000+0x64))&0xF)==0x9)
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "PIPECFG,Pipe Configuration Register"
|
|
bitfld.word 0x00 14.--15. " TYPE ,Transfer Type" "Pipe not used,,Interrupt,"
|
|
bitfld.word 0x00 10. " BFRE ,BRDY Interrupt Operation Specification" "TX/RX,Completion"
|
|
bitfld.word 0x00 9. " DBLB ,Double Buffer Mode" "Single,Double"
|
|
bitfld.word 0x00 7. " SHTNAK ,Pipe Disabled at End of Transfer" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 4. " DIR ,Transfer Direction" "Receiving,Transmitting"
|
|
bitfld.word 0x00 0.--3. " EPNUM ,Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x6C++0x03
|
|
line.word 0x00 "PIPEMAXP,Pipe Maximum Packet Size Register"
|
|
bitfld.word 0x00 12.--15. " DEVSEL ,Device Select" "Address 0000,Address 0001,Address 0010,Address 0011,Address 0100,Address 0101,?..."
|
|
hexmask.word 0x00 0.--8. 1. " MXPS ,Maximum Packet Size"
|
|
line.word 0x02 "PIPEPERI,Pipe Cycle Control Register"
|
|
bitfld.word 0x02 12. " IFIS ,Isochronous IN Buffer Flush" "Not flushed,Flushed"
|
|
bitfld.word 0x02 0.--2. " IITV ,Interval Error Detection Interval" "1,2,4,8,16,32,64,128"
|
|
group.word 0x70++0x01
|
|
line.word 0x00 "PIPE1CTR,PIPE1 Control Registers"
|
|
rbitfld.word 0x00 15. " BSTS ,Buffer Status" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " INBUFM ,Transmit Buffer Monitor" "Empty,Not empty"
|
|
bitfld.word 0x00 10. " ATREPM ,Auto Response Mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " ACLRM ,Auto Buffer Clear Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " SQCLR ,Sequence Toggle Bit Clear" "No effect,Cleared"
|
|
bitfld.word 0x00 7. " SQSET ,Sequence Toggle Bit Set" "No effect,Set"
|
|
rbitfld.word 0x00 6. " SQMON ,Sequence Toggle Bit Confirmation" "DATA0,DATA1"
|
|
rbitfld.word 0x00 5. " PBUSY ,Pipe Busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " PID ,Response PID" "NAK,BUF,STALL,STALL"
|
|
group.word 0x72++0x01
|
|
line.word 0x00 "PIPE2CTR,PIPE2 Control Registers"
|
|
rbitfld.word 0x00 15. " BSTS ,Buffer Status" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " INBUFM ,Transmit Buffer Monitor" "Empty,Not empty"
|
|
bitfld.word 0x00 10. " ATREPM ,Auto Response Mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " ACLRM ,Auto Buffer Clear Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " SQCLR ,Sequence Toggle Bit Clear" "No effect,Cleared"
|
|
bitfld.word 0x00 7. " SQSET ,Sequence Toggle Bit Set" "No effect,Set"
|
|
rbitfld.word 0x00 6. " SQMON ,Sequence Toggle Bit Confirmation" "DATA0,DATA1"
|
|
rbitfld.word 0x00 5. " PBUSY ,Pipe Busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " PID ,Response PID" "NAK,BUF,STALL,STALL"
|
|
group.word 0x74++0x01
|
|
line.word 0x00 "PIPE3CTR,PIPE3 Control Registers"
|
|
rbitfld.word 0x00 15. " BSTS ,Buffer Status" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " INBUFM ,Transmit Buffer Monitor" "Empty,Not empty"
|
|
bitfld.word 0x00 10. " ATREPM ,Auto Response Mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " ACLRM ,Auto Buffer Clear Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " SQCLR ,Sequence Toggle Bit Clear" "No effect,Cleared"
|
|
bitfld.word 0x00 7. " SQSET ,Sequence Toggle Bit Set" "No effect,Set"
|
|
rbitfld.word 0x00 6. " SQMON ,Sequence Toggle Bit Confirmation" "DATA0,DATA1"
|
|
rbitfld.word 0x00 5. " PBUSY ,Pipe Busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " PID ,Response PID" "NAK,BUF,STALL,STALL"
|
|
group.word 0x76++0x01
|
|
line.word 0x00 "PIPE4CTR,PIPE4 Control Registers"
|
|
rbitfld.word 0x00 15. " BSTS ,Buffer Status" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " INBUFM ,Transmit Buffer Monitor" "Empty,Not empty"
|
|
bitfld.word 0x00 10. " ATREPM ,Auto Response Mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " ACLRM ,Auto Buffer Clear Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " SQCLR ,Sequence Toggle Bit Clear" "No effect,Cleared"
|
|
bitfld.word 0x00 7. " SQSET ,Sequence Toggle Bit Set" "No effect,Set"
|
|
rbitfld.word 0x00 6. " SQMON ,Sequence Toggle Bit Confirmation" "DATA0,DATA1"
|
|
rbitfld.word 0x00 5. " PBUSY ,Pipe Busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " PID ,Response PID" "NAK,BUF,STALL,STALL"
|
|
group.word 0x78++0x01
|
|
line.word 0x00 "PIPE5CTR,PIPE5 Control Registers"
|
|
rbitfld.word 0x00 15. " BSTS ,Buffer Status" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " INBUFM ,Transmit Buffer Monitor" "Empty,Not empty"
|
|
bitfld.word 0x00 10. " ATREPM ,Auto Response Mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " ACLRM ,Auto Buffer Clear Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " SQCLR ,Sequence Toggle Bit Clear" "No effect,Cleared"
|
|
bitfld.word 0x00 7. " SQSET ,Sequence Toggle Bit Set" "No effect,Set"
|
|
rbitfld.word 0x00 6. " SQMON ,Sequence Toggle Bit Confirmation" "DATA0,DATA1"
|
|
rbitfld.word 0x00 5. " PBUSY ,Pipe Busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " PID ,Response PID" "NAK,BUF,STALL,STALL"
|
|
group.word 0x7A++0x01
|
|
line.word 0x00 "PIPE6CTR,PIPE6 Control Registers"
|
|
rbitfld.word 0x00 15. " BSTS ,Buffer Status" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " ACLRM ,Auto Buffer Clear Mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SQCLR ,Sequence Toggle Bit Clear" "No effect,Cleared"
|
|
bitfld.word 0x00 7. " SQSET ,Sequence Toggle Bit Set" "No effect,Set"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " SQMON ,Sequence Toggle Bit Confirmation" "DATA0,DATA1"
|
|
rbitfld.word 0x00 5. " PBUSY ,Pipe Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 0.--1. " PID ,Response PID" "NAK,BUF,STALL,STALL"
|
|
group.word 0x7C++0x01
|
|
line.word 0x00 "PIPE7CTR,PIPE7 Control Registers"
|
|
rbitfld.word 0x00 15. " BSTS ,Buffer Status" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " ACLRM ,Auto Buffer Clear Mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SQCLR ,Sequence Toggle Bit Clear" "No effect,Cleared"
|
|
bitfld.word 0x00 7. " SQSET ,Sequence Toggle Bit Set" "No effect,Set"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " SQMON ,Sequence Toggle Bit Confirmation" "DATA0,DATA1"
|
|
rbitfld.word 0x00 5. " PBUSY ,Pipe Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 0.--1. " PID ,Response PID" "NAK,BUF,STALL,STALL"
|
|
group.word 0x7E++0x01
|
|
line.word 0x00 "PIPE8CTR,PIPE8 Control Registers"
|
|
rbitfld.word 0x00 15. " BSTS ,Buffer Status" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " ACLRM ,Auto Buffer Clear Mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SQCLR ,Sequence Toggle Bit Clear" "No effect,Cleared"
|
|
bitfld.word 0x00 7. " SQSET ,Sequence Toggle Bit Set" "No effect,Set"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " SQMON ,Sequence Toggle Bit Confirmation" "DATA0,DATA1"
|
|
rbitfld.word 0x00 5. " PBUSY ,Pipe Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 0.--1. " PID ,Response PID" "NAK,BUF,STALL,STALL"
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "PIPE9CTR,PIPE9 Control Registers"
|
|
rbitfld.word 0x00 15. " BSTS ,Buffer Status" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " ACLRM ,Auto Buffer Clear Mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SQCLR ,Sequence Toggle Bit Clear" "No effect,Cleared"
|
|
bitfld.word 0x00 7. " SQSET ,Sequence Toggle Bit Set" "No effect,Set"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " SQMON ,Sequence Toggle Bit Confirmation" "DATA0,DATA1"
|
|
rbitfld.word 0x00 5. " PBUSY ,Pipe Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 0.--1. " PID ,Response PID" "NAK,BUF,STALL,STALL"
|
|
group.word 0x90++0x01
|
|
line.word 0x00 "PIPE1TRE,PIPE1 Transaction Counter Enable Register"
|
|
bitfld.word 0x00 9. " TRENB ,Transaction Counter Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TRCLR ,Transaction Counter Clear" "No effect,Cleared"
|
|
group.word 0x94++0x01
|
|
line.word 0x00 "PIPE6TRE,PIPE6 Transaction Counter Enable Register"
|
|
bitfld.word 0x00 9. " TRENB ,Transaction Counter Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TRCLR ,Transaction Counter Clear" "No effect,Cleared"
|
|
group.word 0x98++0x01
|
|
line.word 0x00 "PIPE11TRE,PIPE11 Transaction Counter Enable Register"
|
|
bitfld.word 0x00 9. " TRENB ,Transaction Counter Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TRCLR ,Transaction Counter Clear" "No effect,Cleared"
|
|
group.word 0x9C++0x01
|
|
line.word 0x00 "PIPE16TRE,PIPE16 Transaction Counter Enable Register"
|
|
bitfld.word 0x00 9. " TRENB ,Transaction Counter Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TRCLR ,Transaction Counter Clear" "No effect,Cleared"
|
|
group.word 0xA0++0x01
|
|
line.word 0x00 "PIPE21TRE,PIPE21 Transaction Counter Enable Register"
|
|
bitfld.word 0x00 9. " TRENB ,Transaction Counter Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TRCLR ,Transaction Counter Clear" "No effect,Cleared"
|
|
group.word 0x92++0x01
|
|
line.word 0x00 "PIPE1TRN,PIPE1 Transaction Counter Register"
|
|
group.word 0x96++0x01
|
|
line.word 0x00 "PIPE6TRN,PIPE6 Transaction Counter Register"
|
|
group.word 0x9A++0x01
|
|
line.word 0x00 "PIPE11TRN,PIPE11 Transaction Counter Register"
|
|
group.word 0x9E++0x01
|
|
line.word 0x00 "PIPE16TRN,PIPE16 Transaction Counter Register"
|
|
group.word 0xA2++0x01
|
|
line.word 0x00 "PIPE21TRN,PIPE21 Transaction Counter Register"
|
|
group.word 0xD0++0x01
|
|
line.word 0x00 "DEVADD0,Device Address 0 Configuration Register"
|
|
bitfld.word 0x00 6.--7. " USBSPD ,Transfer Speed of Communication Target Device" "Not used,Low-speed,Full-speed,"
|
|
group.word 0xD2++0x01
|
|
line.word 0x00 "DEVADD1,Device Address 1 Configuration Register"
|
|
bitfld.word 0x00 6.--7. " USBSPD ,Transfer Speed of Communication Target Device" "Not used,Low-speed,Full-speed,"
|
|
group.word 0xD4++0x01
|
|
line.word 0x00 "DEVADD2,Device Address 2 Configuration Register"
|
|
bitfld.word 0x00 6.--7. " USBSPD ,Transfer Speed of Communication Target Device" "Not used,Low-speed,Full-speed,"
|
|
group.word 0xD6++0x01
|
|
line.word 0x00 "DEVADD3,Device Address 3 Configuration Register"
|
|
bitfld.word 0x00 6.--7. " USBSPD ,Transfer Speed of Communication Target Device" "Not used,Low-speed,Full-speed,"
|
|
group.word 0xD8++0x01
|
|
line.word 0x00 "DEVADD4,Device Address 4 Configuration Register"
|
|
bitfld.word 0x00 6.--7. " USBSPD ,Transfer Speed of Communication Target Device" "Not used,Low-speed,Full-speed,"
|
|
group.word 0xDA++0x01
|
|
line.word 0x00 "DEVADD5,Device Address 5 Configuration Register"
|
|
bitfld.word 0x00 6.--7. " USBSPD ,Transfer Speed of Communication Target Device" "Not used,Low-speed,Full-speed,"
|
|
group.word 0xCC++0x01
|
|
line.word 0x00 "USBMC,USB Module Control Register"
|
|
bitfld.word 0x00 7. " VDCEN ,USB Regulator On/Off Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " VDDUSBE ,USB Reference Power Supply Circuit On/Off Control" "Disabled,Enabled"
|
|
if (((per.w(ad:0x40090000+0xB0))&0x4)==0x4)&&(((per.w(ad:0x40090000+0xB0))&0x10)==0x10)
|
|
group.word 0xB0++0x01
|
|
line.word 0x00 "USBBCCTRL0,BC Control Register 0"
|
|
rbitfld.word 0x00 9. " PDDETSTS0 ,D_Plus Pin 0.6 V Input Detection Status" "Not detected,Detected"
|
|
rbitfld.word 0x00 8. " CHGDETSTS0 ,D_Minus Pin 0.6 V Input Detection Status" "Not detected,Detected"
|
|
bitfld.word 0x00 7. " BATCHGE0 ,BC (Battery Charger) Function General Enable Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " VDMSRCE0 ,D_Minus Pin VDMSRC (0.6 V) Output Control" "Stopped,0.6 V output"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IDPSINKE0 ,D_Plus Pin 0.6 V Input Detection (Comparator and Sink) Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " VDPSRCE0 ,D_Plus Pin VDPSRC (0.6 V) Output Control" "Stopped,0.6 V output"
|
|
bitfld.word 0x00 2. " IDMSINKE0 ,D_Minus Pin 0.6 V Input Detection (Comparator and Sink) Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " IDPSRCE0 ,D_Plus Pin IDPSRC Output Control" "Stopped,10 uA output"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RPDME0 ,D_Minus Pin Pull-Down Control" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40090000+0xB0))&0x4)==0x4)&&(((per.w(ad:0x40090000+0xB0))&0x10)==0x0)
|
|
group.word 0xB0++0x01
|
|
line.word 0x00 "USBBCCTRL0,BC Control Register 0"
|
|
rbitfld.word 0x00 8. " CHGDETSTS0 ,D_Minus Pin 0.6 V Input Detection Status" "Not detected,Detected"
|
|
bitfld.word 0x00 7. " BATCHGE0 ,BC (Battery Charger) Function General Enable Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " VDMSRCE0 ,D_Minus Pin VDMSRC (0.6 V) Output Control" "Stopped,0.6 V output"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IDPSINKE0 ,D_Plus Pin 0.6 V Input Detection (Comparator and Sink) Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " VDPSRCE0 ,D_Plus Pin VDPSRC (0.6 V) Output Control" "Stopped,0.6 V output"
|
|
bitfld.word 0x00 2. " IDMSINKE0 ,D_Minus Pin 0.6 V Input Detection (Comparator and Sink) Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " IDPSRCE0 ,D_Plus Pin IDPSRC Output Control" "Stopped,10 uA output"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RPDME0 ,D_Minus Pin Pull-Down Control" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40090000+0xB0))&0x4)==0x0)&&(((per.w(ad:0x40090000+0xB0))&0x10)==0x10)
|
|
group.word 0xB0++0x01
|
|
line.word 0x00 "USBBCCTRL0,BC Control Register 0"
|
|
rbitfld.word 0x00 9. " PDDETSTS0 ,D_Plus Pin 0.6 V Input Detection Status" "Not detected,Detected"
|
|
bitfld.word 0x00 7. " BATCHGE0 ,BC (Battery Charger) Function General Enable Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " VDMSRCE0 ,D_Minus Pin VDMSRC (0.6 V) Output Control" "Stopped,0.6 V output"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IDPSINKE0 ,D_Plus Pin 0.6 V Input Detection (Comparator and Sink) Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " VDPSRCE0 ,D_Plus Pin VDPSRC (0.6 V) Output Control" "Stopped,0.6 V output"
|
|
bitfld.word 0x00 2. " IDMSINKE0 ,D_Minus Pin 0.6 V Input Detection (Comparator and Sink) Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " IDPSRCE0 ,D_Plus Pin IDPSRC Output Control" "Stopped,10 uA output"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RPDME0 ,D_Minus Pin Pull-Down Control" "Disabled,Enabled"
|
|
else
|
|
group.word 0xB0++0x01
|
|
line.word 0x00 "USBBCCTRL0,BC Control Register 0"
|
|
bitfld.word 0x00 7. " BATCHGE0 ,BC (Battery Charger) Function General Enable Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " VDMSRCE0 ,D_Minus Pin VDMSRC (0.6 V) Output Control" "Stopped,0.6 V output"
|
|
textline " "
|
|
bitfld.word 0x00 4. " IDPSINKE0 ,D_Plus Pin 0.6 V Input Detection (Comparator and Sink) Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " VDPSRCE0 ,D_Plus Pin VDPSRC (0.6 V) Output Control" "Stopped,0.6 V output"
|
|
bitfld.word 0x00 2. " IDMSINKE0 ,D_Minus Pin 0.6 V Input Detection (Comparator and Sink) Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " IDPSRCE0 ,D_Plus Pin IDPSRC Output Control" "Stopped,10 uA output"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RPDME0 ,D_Minus Pin Pull-Down Control" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCI (Serial Communications Interface)"
|
|
tree "SCI0"
|
|
base ad:0x40070000
|
|
width 8.
|
|
hgroup.byte 0x05++0x00
|
|
hide.byte 0x00 "RDR,Receive Data Register"
|
|
in
|
|
hgroup.word 0x10++0x01
|
|
hide.word 0x00 "RDRHL,Receive 9-bit Data Register"
|
|
in
|
|
if (((per.w(ad:0x40070000+0x14))&0x1)==0x1)
|
|
if (((per.b(ad:0x40070000))&0x4)==0x4)
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "FRDRHL,Receive FIFO Data Register HL"
|
|
bitfld.word 0x00 14. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.word 0x00 13. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.word 0x00 12. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 11. " PER ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DR ,Receive Data Ready Flag" "Not finished,Finished"
|
|
bitfld.word 0x00 9. " MPB ,Multi-Processor Bit Flag" "Data transmission,ID transmission"
|
|
hexmask.word 0x00 0.--8. 1. " RDAT ,Serial Receive Data"
|
|
else
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "FRDRHL,Receive FIFO Data Register HL"
|
|
bitfld.word 0x00 14. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.word 0x00 13. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.word 0x00 12. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 11. " PER ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DR ,Receive Data Ready Flag" "Not finished,Finished"
|
|
hexmask.word 0x00 0.--8. 1. " RDAT ,Serial Receive Data"
|
|
endif
|
|
else
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "FRDRHL,Receive FIFO Data Register HL"
|
|
bitfld.word 0x00 14. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.word 0x00 13. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.word 0x00 12. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 11. " PER ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DR ,Receive Data Ready Flag" "Not finished,Finished"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "TDR,Transmit Data Register"
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "TDRHL,Transmit 9-Bit Data Register"
|
|
if (((per.w(ad:0x40070000+0x14))&0x1)==0x1)
|
|
if (((per.b(ad:0x40070000))&0x4)==0x4)
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "FTDRHL,Transmit FIFO Data Register HL"
|
|
bitfld.word 0x00 9. " MPBT ,Multi-Processor Transfer Bit Flag" "Data,ID"
|
|
hexmask.word 0x00 0.--8. 1. " TDAT ,Serial Transmit Data"
|
|
else
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "FTDRHL,Transmit FIFO Data Register HL"
|
|
hexmask.word 0x00 0.--8. 1. " TDAT ,Serial Transmit Data"
|
|
endif
|
|
else
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "FTDRHL,Transmit FIFO Data Register HL"
|
|
endif
|
|
if (((per.b(ad:0x40070000+0x06))&0x1)==0x0)
|
|
if (((per.b(ad:0x40070000))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070000))&0x20)==0x0)
|
|
if (((per.b(ad:0x40070000+0x06))&0x10)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "9-bit,9-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "8-bit,7-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070000+0x06))&0x10)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "9-bit,9-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "8-bit,7-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
endif
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070000))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070000+0x06))&0x80)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "93 clock,128 clock,186 clock,512 clock"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "32 clock,64 clock,372 clock,256 clock"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070000+0x06))&0x80)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "93 clock,128 clock,186 clock,512 clock"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "32 clock,64 clock,372 clock,256 clock"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070000+0x06))&0x1)==0x0)
|
|
if (((per.b(ad:0x40070000))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070000))&0x4)==0x4)
|
|
if (((per.b(ad:0x40070000+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070000+0x02))&0x10)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK0,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK0,External,External"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070000+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070000+0x02))&0x10)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK0,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK0,External,External"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070000+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070000+0x02))&0x10)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Internal,Internal,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK0,External,External"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070000+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070000+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070000))&0x8)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Disabled,Output,,"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Low,Output,High,"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070000+0x06))&0x1)==0x0)&&(((per.b(ad:0x40070000+0x14))&0x1)==0x0)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " FER ,Framing Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
rbitfld.byte 0x00 1. " MPB ,Multi-Processor" "Data,ID"
|
|
bitfld.byte 0x00 0. " MPBT ,Multi-Processor Bit Transfer" "Data,ID"
|
|
elif (((per.b(ad:0x40070000+0x06))&0x1)==0x0)&&(((per.b(ad:0x40070000+0x14))&0x1)==0x1)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR_FIFO,Serial Status Register"
|
|
bitfld.byte 0x00 7. " TDFE ,Transmit FIFO Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " FER ,Framing Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
bitfld.byte 0x00 0. " DR ,Receive Data Ready Flag" "Not ready,Ready"
|
|
elif (((per.b(ad:0x40070000+0x06))&0x1)==0x1)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR_SMCI,Serial Status Register"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " ERS ,Error Signal Status Flag" "Not sampled,Sampled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
rbitfld.byte 0x00 1. " MPB ,Multi-Processor" "Data,ID"
|
|
bitfld.byte 0x00 0. " MPBT ,Multi-Processor Bit Transfer" "Data,ID"
|
|
endif
|
|
if (((per.b(ad:0x40070000+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070000+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070000))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070000))&0x40)==0x0)
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,8-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,7-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070000))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070000))&0x40)==0x0)
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,8-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
else
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,7-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
else
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070000+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070000+0x02))&0x10)==0x0)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "BRR,Bit Rate Register"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MDDR,Modulation Duty Register"
|
|
else
|
|
rgroup.byte 0x01++0x00
|
|
line.byte 0x00 "BRR,Bit Rate Register"
|
|
rgroup.byte 0x12++0x00
|
|
line.byte 0x00 "MDDR,Modulation Duty Register"
|
|
endif
|
|
if (((per.b(ad:0x40070000+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070000+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070000))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070000+0x02))&0x2)==0x0)
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 6. " BGDM ,Baud Rate Generator Double-Speed Mode Select" "Normal,Doubled"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ABCSE ,Asynchronous Mode Extended Base Clock Select 1" "1-bit,6 base"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070000))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070000+0x02))&0x2)==0x0)
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 6. " BGDM ,Baud Rate Generator Double-Speed Mode Select" "Normal,Doubled"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ABCSE ,Asynchronous Mode Extended Base Clock Select 1" "1-bit,6 base"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070000+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070000+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070000))&0x80)==0x0)
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" "/1,?..."
|
|
else
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" ",/1,/2,/3,/4,?..."
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070000))&0x80)==0x0)
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" "/1,?..."
|
|
else
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" ",/1,/2,/3,/4,?..."
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0x40070000+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070000+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070000+0x06))&0x1)==0x0)
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Asynchronous/Multi-processor/Clock-synchronous/Simple I2C,Simple I2C"
|
|
else
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Smart card interface,"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070000+0x06))&0x1)==0x0)
|
|
rgroup.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Asynchronous/Multi-processor/Clock-synchronous/Simple I2C,Simple I2C"
|
|
else
|
|
rgroup.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Smart card interface,"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0x40070000+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070000+0x02))&0x10)==0x0)
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SIMR2,I2C Mode Register 2"
|
|
bitfld.byte 0x00 5. " IICACKT ,ACK Transmission Data" "ACK,NACK"
|
|
bitfld.byte 0x00 1. " IICCSC ,Clock Synchronization" "No synchronization,Synchronization"
|
|
bitfld.byte 0x00 0. " IICINTM ,I2C Interrupt Mode Select" "ACK/NACK,Reception and transmission"
|
|
else
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SIMR2,I2C Mode Register 2"
|
|
bitfld.byte 0x00 5. " IICACKT ,ACK Transmission Data" "ACK,NACK"
|
|
rbitfld.byte 0x00 1. " IICCSC ,Clock Synchronization" "No synchronization,Synchronization"
|
|
rbitfld.byte 0x00 0. " IICINTM ,I2C Interrupt Mode Select" "ACK/NACK,Reception and transmission"
|
|
endif
|
|
group.byte 0x0B++0x01
|
|
line.byte 0x00 "SIMR3,I2C Mode Register 3"
|
|
bitfld.byte 0x00 6.--7. " IICSCLS ,SCL Output Select" "Serial output,Start/restart/stop,Low level,High-Z"
|
|
bitfld.byte 0x00 4.--5. " IICSDAS ,SDA Output Select" "Serial output,Start/restart/stop,Low level,High-Z"
|
|
bitfld.byte 0x00 3. " IICSTIF ,Issuing of Start/Restart/Stop Condition Completed Flag" "Not generated,Generated"
|
|
bitfld.byte 0x00 2. " IICSTPREQ ,Stop Condition Generation" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " IICRSTAREQ ,Restart Condition Generation" "Not generated,Generated"
|
|
bitfld.byte 0x00 0. " IICSTAREQ ,Start Condition Generation" "Not generated,Generated"
|
|
line.byte 0x01 "SISR,I2C Status Register"
|
|
bitfld.byte 0x01 0. " IICACKR ,ACK Reception Data Flag" "ACK,NACK"
|
|
if (((per.b(ad:0x40070000+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070000+0x02))&0x10)==0x0)
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "SPMR,SPI Mode Register"
|
|
bitfld.byte 0x00 7. " CKPH ,Clock Phase Select" "Not delayed,Delayed"
|
|
bitfld.byte 0x00 6. " CKPOL ,Clock Polarity Select" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " MFF ,Mode Fault Flag" "No error,Error"
|
|
bitfld.byte 0x00 2. " MSS ,Master Slave Select" "Master,Slave"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SSE ,SSn Pin Function Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "SPMR,SPI Mode Register"
|
|
rbitfld.byte 0x00 7. " CKPH ,Clock Phase Select" "Not delayed,Delayed"
|
|
rbitfld.byte 0x00 6. " CKPOL ,Clock Polarity Select" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " MFF ,Mode Fault Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " MSS ,Master Slave Select" "Master,Slave"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " SSE ,SSn Pin Function Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40070000+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070000+0x02))&0x10)==0x0)
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 12.--15. " RSTRG ,RTS Output Active Trigger Number Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " RTRG ,Receive FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " TTRG ,Transmit FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 3. " DRES ,Receive Data Ready Error Select Bit" "Reception,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 0. " FM ,FIFO Mode Select" "Non-FIFO,FIFO"
|
|
else
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 12.--15. " RSTRG ,RTS Output Active Trigger Number Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " RTRG ,Receive FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " TTRG ,Transmit FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 3. " DRES ,Receive Data Ready Error Select Bit" "Reception,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO Data Register Reset" "No reset,Reset"
|
|
rbitfld.word 0x00 0. " FM ,FIFO Mode Select" "Non-FIFO,FIFO"
|
|
endif
|
|
rgroup.word 0x16++0x03
|
|
line.word 0x00 "FDR,FIFO Data Count Register"
|
|
bitfld.word 0x00 8.--12. " T ,Transmit FIFO Data Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " R ,Receive FIFO Data Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.word 0x02 "LSR,Line Status Register"
|
|
bitfld.word 0x02 8.--12. " PNUM ,Parity Error Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 2.--6. " FNUM ,Framing Error Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0. " ORER ,Overrun Error Flag" "No overrun,Overrun"
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "CDR,Compare Match Data Register"
|
|
hexmask.word 0x00 0.--8. 1. " CMPD ,Compare Match Data"
|
|
if (((per.b(ad:0x40070000))&0x80)==0x0)
|
|
group.word 0x13++0x01
|
|
line.word 0x00 "DCCR,Data Compare Match Control Register"
|
|
bitfld.word 0x00 7. " DCME ,Data Compare Match Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " IDSEL ,ID Frame Select" "Always compare MPB,Compare only MPB=1"
|
|
bitfld.word 0x00 4. " DFER ,Data Compare Match Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 3. " DPER ,Data Compare Match Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DCMF ,Data Compare Match Flag" "Not matched,Matched"
|
|
else
|
|
group.word 0x13++0x01
|
|
line.word 0x00 "DCCR,Data Compare Match Control Register"
|
|
bitfld.word 0x00 4. " DFER ,Data Compare Match Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 3. " DPER ,Data Compare Match Parity Error Flag" "No error,Error"
|
|
bitfld.word 0x00 0. " DCMF ,Data Compare Match Flag" "Not matched,Matched"
|
|
endif
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SPTR,Serial Port Register"
|
|
bitfld.byte 0x00 2. " SPB2IO ,Serial Port Break I/O" "No output,Output"
|
|
bitfld.byte 0x00 1. " SPB2DT ,Serial Port Break Data Select" "Low,High"
|
|
rbitfld.byte 0x00 0. " RXDMON ,Serial Input Data Monitor" "Low,High"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCI1"
|
|
base ad:0x40070020
|
|
width 8.
|
|
hgroup.byte 0x05++0x00
|
|
hide.byte 0x00 "RDR,Receive Data Register"
|
|
in
|
|
hgroup.word 0x10++0x01
|
|
hide.word 0x00 "RDRHL,Receive 9-bit Data Register"
|
|
in
|
|
if (((per.w(ad:0x40070020+0x14))&0x1)==0x1)
|
|
if (((per.b(ad:0x40070020))&0x4)==0x4)
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "FRDRHL,Receive FIFO Data Register HL"
|
|
bitfld.word 0x00 14. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.word 0x00 13. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.word 0x00 12. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 11. " PER ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DR ,Receive Data Ready Flag" "Not finished,Finished"
|
|
bitfld.word 0x00 9. " MPB ,Multi-Processor Bit Flag" "Data transmission,ID transmission"
|
|
hexmask.word 0x00 0.--8. 1. " RDAT ,Serial Receive Data"
|
|
else
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "FRDRHL,Receive FIFO Data Register HL"
|
|
bitfld.word 0x00 14. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.word 0x00 13. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.word 0x00 12. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 11. " PER ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DR ,Receive Data Ready Flag" "Not finished,Finished"
|
|
hexmask.word 0x00 0.--8. 1. " RDAT ,Serial Receive Data"
|
|
endif
|
|
else
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "FRDRHL,Receive FIFO Data Register HL"
|
|
bitfld.word 0x00 14. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.word 0x00 13. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.word 0x00 12. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 11. " PER ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DR ,Receive Data Ready Flag" "Not finished,Finished"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "TDR,Transmit Data Register"
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "TDRHL,Transmit 9-Bit Data Register"
|
|
if (((per.w(ad:0x40070020+0x14))&0x1)==0x1)
|
|
if (((per.b(ad:0x40070020))&0x4)==0x4)
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "FTDRHL,Transmit FIFO Data Register HL"
|
|
bitfld.word 0x00 9. " MPBT ,Multi-Processor Transfer Bit Flag" "Data,ID"
|
|
hexmask.word 0x00 0.--8. 1. " TDAT ,Serial Transmit Data"
|
|
else
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "FTDRHL,Transmit FIFO Data Register HL"
|
|
hexmask.word 0x00 0.--8. 1. " TDAT ,Serial Transmit Data"
|
|
endif
|
|
else
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "FTDRHL,Transmit FIFO Data Register HL"
|
|
endif
|
|
if (((per.b(ad:0x40070020+0x06))&0x1)==0x0)
|
|
if (((per.b(ad:0x40070020))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070020))&0x20)==0x0)
|
|
if (((per.b(ad:0x40070020+0x06))&0x10)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "9-bit,9-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "8-bit,7-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070020+0x06))&0x10)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "9-bit,9-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "8-bit,7-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
endif
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070020))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070020+0x06))&0x80)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "93 clock,128 clock,186 clock,512 clock"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "32 clock,64 clock,372 clock,256 clock"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070020+0x06))&0x80)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "93 clock,128 clock,186 clock,512 clock"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "32 clock,64 clock,372 clock,256 clock"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070020+0x06))&0x1)==0x0)
|
|
if (((per.b(ad:0x40070020))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070020))&0x4)==0x4)
|
|
if (((per.b(ad:0x40070020+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070020+0x02))&0x10)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK1,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK1,External,External"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070020+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070020+0x02))&0x10)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK1,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK1,External,External"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070020+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070020+0x02))&0x10)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Internal,Internal,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK1,External,External"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070020+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070020+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070020))&0x8)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Disabled,Output,,"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Low,Output,High,"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070020+0x06))&0x1)==0x0)&&(((per.b(ad:0x40070020+0x14))&0x1)==0x0)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " FER ,Framing Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
rbitfld.byte 0x00 1. " MPB ,Multi-Processor" "Data,ID"
|
|
bitfld.byte 0x00 0. " MPBT ,Multi-Processor Bit Transfer" "Data,ID"
|
|
elif (((per.b(ad:0x40070020+0x06))&0x1)==0x0)&&(((per.b(ad:0x40070020+0x14))&0x1)==0x1)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR_FIFO,Serial Status Register"
|
|
bitfld.byte 0x00 7. " TDFE ,Transmit FIFO Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " FER ,Framing Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
bitfld.byte 0x00 0. " DR ,Receive Data Ready Flag" "Not ready,Ready"
|
|
elif (((per.b(ad:0x40070020+0x06))&0x1)==0x1)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR_SMCI,Serial Status Register"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " ERS ,Error Signal Status Flag" "Not sampled,Sampled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
rbitfld.byte 0x00 1. " MPB ,Multi-Processor" "Data,ID"
|
|
bitfld.byte 0x00 0. " MPBT ,Multi-Processor Bit Transfer" "Data,ID"
|
|
endif
|
|
if (((per.b(ad:0x40070020+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070020+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070020))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070020))&0x40)==0x0)
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,8-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,7-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070020))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070020))&0x40)==0x0)
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,8-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
else
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,7-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
else
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070020+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070020+0x02))&0x10)==0x0)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "BRR,Bit Rate Register"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MDDR,Modulation Duty Register"
|
|
else
|
|
rgroup.byte 0x01++0x00
|
|
line.byte 0x00 "BRR,Bit Rate Register"
|
|
rgroup.byte 0x12++0x00
|
|
line.byte 0x00 "MDDR,Modulation Duty Register"
|
|
endif
|
|
if (((per.b(ad:0x40070020+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070020+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070020))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070020+0x02))&0x2)==0x0)
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 6. " BGDM ,Baud Rate Generator Double-Speed Mode Select" "Normal,Doubled"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ABCSE ,Asynchronous Mode Extended Base Clock Select 1" "1-bit,6 base"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070020))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070020+0x02))&0x2)==0x0)
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 6. " BGDM ,Baud Rate Generator Double-Speed Mode Select" "Normal,Doubled"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ABCSE ,Asynchronous Mode Extended Base Clock Select 1" "1-bit,6 base"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070020+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070020+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070020))&0x80)==0x0)
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" "/1,?..."
|
|
else
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" ",/1,/2,/3,/4,?..."
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070020))&0x80)==0x0)
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" "/1,?..."
|
|
else
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" ",/1,/2,/3,/4,?..."
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0x40070020+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070020+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070020+0x06))&0x1)==0x0)
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Asynchronous/Multi-processor/Clock-synchronous/Simple I2C,Simple I2C"
|
|
else
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Smart card interface,"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070020+0x06))&0x1)==0x0)
|
|
rgroup.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Asynchronous/Multi-processor/Clock-synchronous/Simple I2C,Simple I2C"
|
|
else
|
|
rgroup.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Smart card interface,"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0x40070020+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070020+0x02))&0x10)==0x0)
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SIMR2,I2C Mode Register 2"
|
|
bitfld.byte 0x00 5. " IICACKT ,ACK Transmission Data" "ACK,NACK"
|
|
bitfld.byte 0x00 1. " IICCSC ,Clock Synchronization" "No synchronization,Synchronization"
|
|
bitfld.byte 0x00 0. " IICINTM ,I2C Interrupt Mode Select" "ACK/NACK,Reception and transmission"
|
|
else
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SIMR2,I2C Mode Register 2"
|
|
bitfld.byte 0x00 5. " IICACKT ,ACK Transmission Data" "ACK,NACK"
|
|
rbitfld.byte 0x00 1. " IICCSC ,Clock Synchronization" "No synchronization,Synchronization"
|
|
rbitfld.byte 0x00 0. " IICINTM ,I2C Interrupt Mode Select" "ACK/NACK,Reception and transmission"
|
|
endif
|
|
group.byte 0x0B++0x01
|
|
line.byte 0x00 "SIMR3,I2C Mode Register 3"
|
|
bitfld.byte 0x00 6.--7. " IICSCLS ,SCL Output Select" "Serial output,Start/restart/stop,Low level,High-Z"
|
|
bitfld.byte 0x00 4.--5. " IICSDAS ,SDA Output Select" "Serial output,Start/restart/stop,Low level,High-Z"
|
|
bitfld.byte 0x00 3. " IICSTIF ,Issuing of Start/Restart/Stop Condition Completed Flag" "Not generated,Generated"
|
|
bitfld.byte 0x00 2. " IICSTPREQ ,Stop Condition Generation" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " IICRSTAREQ ,Restart Condition Generation" "Not generated,Generated"
|
|
bitfld.byte 0x00 0. " IICSTAREQ ,Start Condition Generation" "Not generated,Generated"
|
|
line.byte 0x01 "SISR,I2C Status Register"
|
|
bitfld.byte 0x01 0. " IICACKR ,ACK Reception Data Flag" "ACK,NACK"
|
|
if (((per.b(ad:0x40070020+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070020+0x02))&0x10)==0x0)
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "SPMR,SPI Mode Register"
|
|
bitfld.byte 0x00 7. " CKPH ,Clock Phase Select" "Not delayed,Delayed"
|
|
bitfld.byte 0x00 6. " CKPOL ,Clock Polarity Select" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " MFF ,Mode Fault Flag" "No error,Error"
|
|
bitfld.byte 0x00 2. " MSS ,Master Slave Select" "Master,Slave"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SSE ,SSn Pin Function Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "SPMR,SPI Mode Register"
|
|
rbitfld.byte 0x00 7. " CKPH ,Clock Phase Select" "Not delayed,Delayed"
|
|
rbitfld.byte 0x00 6. " CKPOL ,Clock Polarity Select" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " MFF ,Mode Fault Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " MSS ,Master Slave Select" "Master,Slave"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " SSE ,SSn Pin Function Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40070020+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070020+0x02))&0x10)==0x0)
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 12.--15. " RSTRG ,RTS Output Active Trigger Number Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " RTRG ,Receive FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " TTRG ,Transmit FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 3. " DRES ,Receive Data Ready Error Select Bit" "Reception,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 0. " FM ,FIFO Mode Select" "Non-FIFO,FIFO"
|
|
else
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 12.--15. " RSTRG ,RTS Output Active Trigger Number Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " RTRG ,Receive FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " TTRG ,Transmit FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 3. " DRES ,Receive Data Ready Error Select Bit" "Reception,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO Data Register Reset" "No reset,Reset"
|
|
rbitfld.word 0x00 0. " FM ,FIFO Mode Select" "Non-FIFO,FIFO"
|
|
endif
|
|
rgroup.word 0x16++0x03
|
|
line.word 0x00 "FDR,FIFO Data Count Register"
|
|
bitfld.word 0x00 8.--12. " T ,Transmit FIFO Data Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " R ,Receive FIFO Data Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.word 0x02 "LSR,Line Status Register"
|
|
bitfld.word 0x02 8.--12. " PNUM ,Parity Error Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 2.--6. " FNUM ,Framing Error Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0. " ORER ,Overrun Error Flag" "No overrun,Overrun"
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "CDR,Compare Match Data Register"
|
|
hexmask.word 0x00 0.--8. 1. " CMPD ,Compare Match Data"
|
|
if (((per.b(ad:0x40070020))&0x80)==0x0)
|
|
group.word 0x13++0x01
|
|
line.word 0x00 "DCCR,Data Compare Match Control Register"
|
|
bitfld.word 0x00 7. " DCME ,Data Compare Match Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " IDSEL ,ID Frame Select" "Always compare MPB,Compare only MPB=1"
|
|
bitfld.word 0x00 4. " DFER ,Data Compare Match Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 3. " DPER ,Data Compare Match Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DCMF ,Data Compare Match Flag" "Not matched,Matched"
|
|
else
|
|
group.word 0x13++0x01
|
|
line.word 0x00 "DCCR,Data Compare Match Control Register"
|
|
bitfld.word 0x00 4. " DFER ,Data Compare Match Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 3. " DPER ,Data Compare Match Parity Error Flag" "No error,Error"
|
|
bitfld.word 0x00 0. " DCMF ,Data Compare Match Flag" "Not matched,Matched"
|
|
endif
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SPTR,Serial Port Register"
|
|
bitfld.byte 0x00 2. " SPB2IO ,Serial Port Break I/O" "No output,Output"
|
|
bitfld.byte 0x00 1. " SPB2DT ,Serial Port Break Data Select" "Low,High"
|
|
rbitfld.byte 0x00 0. " RXDMON ,Serial Input Data Monitor" "Low,High"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCI2"
|
|
base ad:0x40070040
|
|
width 8.
|
|
hgroup.byte 0x05++0x00
|
|
hide.byte 0x00 "RDR,Receive Data Register"
|
|
in
|
|
hgroup.word 0x10++0x01
|
|
hide.word 0x00 "RDRHL,Receive 9-bit Data Register"
|
|
in
|
|
if (((per.w(ad:0x40070040+0x14))&0x1)==0x1)
|
|
if (((per.b(ad:0x40070040))&0x4)==0x4)
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "FRDRHL,Receive FIFO Data Register HL"
|
|
bitfld.word 0x00 14. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.word 0x00 13. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.word 0x00 12. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 11. " PER ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DR ,Receive Data Ready Flag" "Not finished,Finished"
|
|
bitfld.word 0x00 9. " MPB ,Multi-Processor Bit Flag" "Data transmission,ID transmission"
|
|
hexmask.word 0x00 0.--8. 1. " RDAT ,Serial Receive Data"
|
|
else
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "FRDRHL,Receive FIFO Data Register HL"
|
|
bitfld.word 0x00 14. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.word 0x00 13. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.word 0x00 12. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 11. " PER ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DR ,Receive Data Ready Flag" "Not finished,Finished"
|
|
hexmask.word 0x00 0.--8. 1. " RDAT ,Serial Receive Data"
|
|
endif
|
|
else
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "FRDRHL,Receive FIFO Data Register HL"
|
|
bitfld.word 0x00 14. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.word 0x00 13. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.word 0x00 12. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 11. " PER ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DR ,Receive Data Ready Flag" "Not finished,Finished"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "TDR,Transmit Data Register"
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "TDRHL,Transmit 9-Bit Data Register"
|
|
if (((per.w(ad:0x40070040+0x14))&0x1)==0x1)
|
|
if (((per.b(ad:0x40070040))&0x4)==0x4)
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "FTDRHL,Transmit FIFO Data Register HL"
|
|
bitfld.word 0x00 9. " MPBT ,Multi-Processor Transfer Bit Flag" "Data,ID"
|
|
hexmask.word 0x00 0.--8. 1. " TDAT ,Serial Transmit Data"
|
|
else
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "FTDRHL,Transmit FIFO Data Register HL"
|
|
hexmask.word 0x00 0.--8. 1. " TDAT ,Serial Transmit Data"
|
|
endif
|
|
else
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "FTDRHL,Transmit FIFO Data Register HL"
|
|
endif
|
|
if (((per.b(ad:0x40070040+0x06))&0x1)==0x0)
|
|
if (((per.b(ad:0x40070040))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070040))&0x20)==0x0)
|
|
if (((per.b(ad:0x40070040+0x06))&0x10)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "9-bit,9-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "8-bit,7-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070040+0x06))&0x10)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "9-bit,9-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "8-bit,7-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
endif
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070040))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070040+0x06))&0x80)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "93 clock,128 clock,186 clock,512 clock"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "32 clock,64 clock,372 clock,256 clock"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070040+0x06))&0x80)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "93 clock,128 clock,186 clock,512 clock"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "32 clock,64 clock,372 clock,256 clock"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070040+0x06))&0x1)==0x0)
|
|
if (((per.b(ad:0x40070040))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070040))&0x4)==0x4)
|
|
if (((per.b(ad:0x40070040+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070040+0x02))&0x10)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK2,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK2,External,External"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070040+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070040+0x02))&0x10)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK2,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK2,External,External"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070040+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070040+0x02))&0x10)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Internal,Internal,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK2,External,External"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070040+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070040+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070040))&0x8)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Disabled,Output,,"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Low,Output,High,"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070040+0x06))&0x1)==0x0)&&(((per.b(ad:0x40070040+0x14))&0x1)==0x0)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " FER ,Framing Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
rbitfld.byte 0x00 1. " MPB ,Multi-Processor" "Data,ID"
|
|
bitfld.byte 0x00 0. " MPBT ,Multi-Processor Bit Transfer" "Data,ID"
|
|
elif (((per.b(ad:0x40070040+0x06))&0x1)==0x0)&&(((per.b(ad:0x40070040+0x14))&0x1)==0x1)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR_FIFO,Serial Status Register"
|
|
bitfld.byte 0x00 7. " TDFE ,Transmit FIFO Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " FER ,Framing Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
bitfld.byte 0x00 0. " DR ,Receive Data Ready Flag" "Not ready,Ready"
|
|
elif (((per.b(ad:0x40070040+0x06))&0x1)==0x1)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR_SMCI,Serial Status Register"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " ERS ,Error Signal Status Flag" "Not sampled,Sampled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
rbitfld.byte 0x00 1. " MPB ,Multi-Processor" "Data,ID"
|
|
bitfld.byte 0x00 0. " MPBT ,Multi-Processor Bit Transfer" "Data,ID"
|
|
endif
|
|
if (((per.b(ad:0x40070040+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070040+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070040))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070040))&0x40)==0x0)
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,8-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,7-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070040))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070040))&0x40)==0x0)
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,8-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
else
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,7-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
else
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070040+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070040+0x02))&0x10)==0x0)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "BRR,Bit Rate Register"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MDDR,Modulation Duty Register"
|
|
else
|
|
rgroup.byte 0x01++0x00
|
|
line.byte 0x00 "BRR,Bit Rate Register"
|
|
rgroup.byte 0x12++0x00
|
|
line.byte 0x00 "MDDR,Modulation Duty Register"
|
|
endif
|
|
if (((per.b(ad:0x40070040+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070040+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070040))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070040+0x02))&0x2)==0x0)
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 6. " BGDM ,Baud Rate Generator Double-Speed Mode Select" "Normal,Doubled"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ABCSE ,Asynchronous Mode Extended Base Clock Select 1" "1-bit,6 base"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070040))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070040+0x02))&0x2)==0x0)
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 6. " BGDM ,Baud Rate Generator Double-Speed Mode Select" "Normal,Doubled"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ABCSE ,Asynchronous Mode Extended Base Clock Select 1" "1-bit,6 base"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070040+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070040+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070040))&0x80)==0x0)
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" "/1,?..."
|
|
else
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" ",/1,/2,/3,/4,?..."
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070040))&0x80)==0x0)
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" "/1,?..."
|
|
else
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" ",/1,/2,/3,/4,?..."
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0x40070040+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070040+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070040+0x06))&0x1)==0x0)
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Asynchronous/Multi-processor/Clock-synchronous/Simple I2C,Simple I2C"
|
|
else
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Smart card interface,"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070040+0x06))&0x1)==0x0)
|
|
rgroup.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Asynchronous/Multi-processor/Clock-synchronous/Simple I2C,Simple I2C"
|
|
else
|
|
rgroup.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Smart card interface,"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0x40070040+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070040+0x02))&0x10)==0x0)
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SIMR2,I2C Mode Register 2"
|
|
bitfld.byte 0x00 5. " IICACKT ,ACK Transmission Data" "ACK,NACK"
|
|
bitfld.byte 0x00 1. " IICCSC ,Clock Synchronization" "No synchronization,Synchronization"
|
|
bitfld.byte 0x00 0. " IICINTM ,I2C Interrupt Mode Select" "ACK/NACK,Reception and transmission"
|
|
else
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SIMR2,I2C Mode Register 2"
|
|
bitfld.byte 0x00 5. " IICACKT ,ACK Transmission Data" "ACK,NACK"
|
|
rbitfld.byte 0x00 1. " IICCSC ,Clock Synchronization" "No synchronization,Synchronization"
|
|
rbitfld.byte 0x00 0. " IICINTM ,I2C Interrupt Mode Select" "ACK/NACK,Reception and transmission"
|
|
endif
|
|
group.byte 0x0B++0x01
|
|
line.byte 0x00 "SIMR3,I2C Mode Register 3"
|
|
bitfld.byte 0x00 6.--7. " IICSCLS ,SCL Output Select" "Serial output,Start/restart/stop,Low level,High-Z"
|
|
bitfld.byte 0x00 4.--5. " IICSDAS ,SDA Output Select" "Serial output,Start/restart/stop,Low level,High-Z"
|
|
bitfld.byte 0x00 3. " IICSTIF ,Issuing of Start/Restart/Stop Condition Completed Flag" "Not generated,Generated"
|
|
bitfld.byte 0x00 2. " IICSTPREQ ,Stop Condition Generation" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " IICRSTAREQ ,Restart Condition Generation" "Not generated,Generated"
|
|
bitfld.byte 0x00 0. " IICSTAREQ ,Start Condition Generation" "Not generated,Generated"
|
|
line.byte 0x01 "SISR,I2C Status Register"
|
|
bitfld.byte 0x01 0. " IICACKR ,ACK Reception Data Flag" "ACK,NACK"
|
|
if (((per.b(ad:0x40070040+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070040+0x02))&0x10)==0x0)
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "SPMR,SPI Mode Register"
|
|
bitfld.byte 0x00 7. " CKPH ,Clock Phase Select" "Not delayed,Delayed"
|
|
bitfld.byte 0x00 6. " CKPOL ,Clock Polarity Select" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " MFF ,Mode Fault Flag" "No error,Error"
|
|
bitfld.byte 0x00 2. " MSS ,Master Slave Select" "Master,Slave"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SSE ,SSn Pin Function Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "SPMR,SPI Mode Register"
|
|
rbitfld.byte 0x00 7. " CKPH ,Clock Phase Select" "Not delayed,Delayed"
|
|
rbitfld.byte 0x00 6. " CKPOL ,Clock Polarity Select" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " MFF ,Mode Fault Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " MSS ,Master Slave Select" "Master,Slave"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " SSE ,SSn Pin Function Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40070040+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070040+0x02))&0x10)==0x0)
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 12.--15. " RSTRG ,RTS Output Active Trigger Number Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " RTRG ,Receive FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " TTRG ,Transmit FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 3. " DRES ,Receive Data Ready Error Select Bit" "Reception,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 0. " FM ,FIFO Mode Select" "Non-FIFO,FIFO"
|
|
else
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 12.--15. " RSTRG ,RTS Output Active Trigger Number Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " RTRG ,Receive FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " TTRG ,Transmit FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 3. " DRES ,Receive Data Ready Error Select Bit" "Reception,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO Data Register Reset" "No reset,Reset"
|
|
rbitfld.word 0x00 0. " FM ,FIFO Mode Select" "Non-FIFO,FIFO"
|
|
endif
|
|
rgroup.word 0x16++0x03
|
|
line.word 0x00 "FDR,FIFO Data Count Register"
|
|
bitfld.word 0x00 8.--12. " T ,Transmit FIFO Data Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " R ,Receive FIFO Data Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.word 0x02 "LSR,Line Status Register"
|
|
bitfld.word 0x02 8.--12. " PNUM ,Parity Error Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 2.--6. " FNUM ,Framing Error Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0. " ORER ,Overrun Error Flag" "No overrun,Overrun"
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "CDR,Compare Match Data Register"
|
|
hexmask.word 0x00 0.--8. 1. " CMPD ,Compare Match Data"
|
|
if (((per.b(ad:0x40070040))&0x80)==0x0)
|
|
group.word 0x13++0x01
|
|
line.word 0x00 "DCCR,Data Compare Match Control Register"
|
|
bitfld.word 0x00 7. " DCME ,Data Compare Match Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " IDSEL ,ID Frame Select" "Always compare MPB,Compare only MPB=1"
|
|
bitfld.word 0x00 4. " DFER ,Data Compare Match Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 3. " DPER ,Data Compare Match Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DCMF ,Data Compare Match Flag" "Not matched,Matched"
|
|
else
|
|
group.word 0x13++0x01
|
|
line.word 0x00 "DCCR,Data Compare Match Control Register"
|
|
bitfld.word 0x00 4. " DFER ,Data Compare Match Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 3. " DPER ,Data Compare Match Parity Error Flag" "No error,Error"
|
|
bitfld.word 0x00 0. " DCMF ,Data Compare Match Flag" "Not matched,Matched"
|
|
endif
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SPTR,Serial Port Register"
|
|
bitfld.byte 0x00 2. " SPB2IO ,Serial Port Break I/O" "No output,Output"
|
|
bitfld.byte 0x00 1. " SPB2DT ,Serial Port Break Data Select" "Low,High"
|
|
rbitfld.byte 0x00 0. " RXDMON ,Serial Input Data Monitor" "Low,High"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCI3"
|
|
base ad:0x40070060
|
|
width 8.
|
|
hgroup.byte 0x05++0x00
|
|
hide.byte 0x00 "RDR,Receive Data Register"
|
|
in
|
|
hgroup.word 0x10++0x01
|
|
hide.word 0x00 "RDRHL,Receive 9-bit Data Register"
|
|
in
|
|
if (((per.w(ad:0x40070060+0x14))&0x1)==0x1)
|
|
if (((per.b(ad:0x40070060))&0x4)==0x4)
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "FRDRHL,Receive FIFO Data Register HL"
|
|
bitfld.word 0x00 14. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.word 0x00 13. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.word 0x00 12. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 11. " PER ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DR ,Receive Data Ready Flag" "Not finished,Finished"
|
|
bitfld.word 0x00 9. " MPB ,Multi-Processor Bit Flag" "Data transmission,ID transmission"
|
|
hexmask.word 0x00 0.--8. 1. " RDAT ,Serial Receive Data"
|
|
else
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "FRDRHL,Receive FIFO Data Register HL"
|
|
bitfld.word 0x00 14. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.word 0x00 13. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.word 0x00 12. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 11. " PER ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DR ,Receive Data Ready Flag" "Not finished,Finished"
|
|
hexmask.word 0x00 0.--8. 1. " RDAT ,Serial Receive Data"
|
|
endif
|
|
else
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "FRDRHL,Receive FIFO Data Register HL"
|
|
bitfld.word 0x00 14. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.word 0x00 13. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.word 0x00 12. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 11. " PER ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DR ,Receive Data Ready Flag" "Not finished,Finished"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "TDR,Transmit Data Register"
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "TDRHL,Transmit 9-Bit Data Register"
|
|
if (((per.w(ad:0x40070060+0x14))&0x1)==0x1)
|
|
if (((per.b(ad:0x40070060))&0x4)==0x4)
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "FTDRHL,Transmit FIFO Data Register HL"
|
|
bitfld.word 0x00 9. " MPBT ,Multi-Processor Transfer Bit Flag" "Data,ID"
|
|
hexmask.word 0x00 0.--8. 1. " TDAT ,Serial Transmit Data"
|
|
else
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "FTDRHL,Transmit FIFO Data Register HL"
|
|
hexmask.word 0x00 0.--8. 1. " TDAT ,Serial Transmit Data"
|
|
endif
|
|
else
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "FTDRHL,Transmit FIFO Data Register HL"
|
|
endif
|
|
if (((per.b(ad:0x40070060+0x06))&0x1)==0x0)
|
|
if (((per.b(ad:0x40070060))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070060))&0x20)==0x0)
|
|
if (((per.b(ad:0x40070060+0x06))&0x10)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "9-bit,9-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "8-bit,7-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070060+0x06))&0x10)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "9-bit,9-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "8-bit,7-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
endif
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070060))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070060+0x06))&0x80)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "93 clock,128 clock,186 clock,512 clock"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "32 clock,64 clock,372 clock,256 clock"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070060+0x06))&0x80)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "93 clock,128 clock,186 clock,512 clock"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "32 clock,64 clock,372 clock,256 clock"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070060+0x06))&0x1)==0x0)
|
|
if (((per.b(ad:0x40070060))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070060))&0x4)==0x4)
|
|
if (((per.b(ad:0x40070060+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070060+0x02))&0x10)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK3,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK3,External,External"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070060+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070060+0x02))&0x10)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK3,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK3,External,External"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070060+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070060+0x02))&0x10)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Internal,Internal,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK3,External,External"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070060+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070060+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070060))&0x8)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Disabled,Output,,"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Low,Output,High,"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070060+0x06))&0x1)==0x0)&&(((per.b(ad:0x40070060+0x14))&0x1)==0x0)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " FER ,Framing Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
rbitfld.byte 0x00 1. " MPB ,Multi-Processor" "Data,ID"
|
|
bitfld.byte 0x00 0. " MPBT ,Multi-Processor Bit Transfer" "Data,ID"
|
|
elif (((per.b(ad:0x40070060+0x06))&0x1)==0x0)&&(((per.b(ad:0x40070060+0x14))&0x1)==0x1)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR_FIFO,Serial Status Register"
|
|
bitfld.byte 0x00 7. " TDFE ,Transmit FIFO Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " FER ,Framing Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
bitfld.byte 0x00 0. " DR ,Receive Data Ready Flag" "Not ready,Ready"
|
|
elif (((per.b(ad:0x40070060+0x06))&0x1)==0x1)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR_SMCI,Serial Status Register"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " ERS ,Error Signal Status Flag" "Not sampled,Sampled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
rbitfld.byte 0x00 1. " MPB ,Multi-Processor" "Data,ID"
|
|
bitfld.byte 0x00 0. " MPBT ,Multi-Processor Bit Transfer" "Data,ID"
|
|
endif
|
|
if (((per.b(ad:0x40070060+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070060+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070060))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070060))&0x40)==0x0)
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,8-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,7-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070060))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070060))&0x40)==0x0)
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,8-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
else
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,7-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
else
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070060+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070060+0x02))&0x10)==0x0)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "BRR,Bit Rate Register"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MDDR,Modulation Duty Register"
|
|
else
|
|
rgroup.byte 0x01++0x00
|
|
line.byte 0x00 "BRR,Bit Rate Register"
|
|
rgroup.byte 0x12++0x00
|
|
line.byte 0x00 "MDDR,Modulation Duty Register"
|
|
endif
|
|
if (((per.b(ad:0x40070060+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070060+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070060))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070060+0x02))&0x2)==0x0)
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 6. " BGDM ,Baud Rate Generator Double-Speed Mode Select" "Normal,Doubled"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ABCSE ,Asynchronous Mode Extended Base Clock Select 1" "1-bit,6 base"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070060))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070060+0x02))&0x2)==0x0)
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 6. " BGDM ,Baud Rate Generator Double-Speed Mode Select" "Normal,Doubled"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ABCSE ,Asynchronous Mode Extended Base Clock Select 1" "1-bit,6 base"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070060+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070060+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070060))&0x80)==0x0)
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" "/1,?..."
|
|
else
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" ",/1,/2,/3,/4,?..."
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070060))&0x80)==0x0)
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" "/1,?..."
|
|
else
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" ",/1,/2,/3,/4,?..."
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0x40070060+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070060+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070060+0x06))&0x1)==0x0)
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Asynchronous/Multi-processor/Clock-synchronous/Simple I2C,Simple I2C"
|
|
else
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Smart card interface,"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070060+0x06))&0x1)==0x0)
|
|
rgroup.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Asynchronous/Multi-processor/Clock-synchronous/Simple I2C,Simple I2C"
|
|
else
|
|
rgroup.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Smart card interface,"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0x40070060+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070060+0x02))&0x10)==0x0)
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SIMR2,I2C Mode Register 2"
|
|
bitfld.byte 0x00 5. " IICACKT ,ACK Transmission Data" "ACK,NACK"
|
|
bitfld.byte 0x00 1. " IICCSC ,Clock Synchronization" "No synchronization,Synchronization"
|
|
bitfld.byte 0x00 0. " IICINTM ,I2C Interrupt Mode Select" "ACK/NACK,Reception and transmission"
|
|
else
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SIMR2,I2C Mode Register 2"
|
|
bitfld.byte 0x00 5. " IICACKT ,ACK Transmission Data" "ACK,NACK"
|
|
rbitfld.byte 0x00 1. " IICCSC ,Clock Synchronization" "No synchronization,Synchronization"
|
|
rbitfld.byte 0x00 0. " IICINTM ,I2C Interrupt Mode Select" "ACK/NACK,Reception and transmission"
|
|
endif
|
|
group.byte 0x0B++0x01
|
|
line.byte 0x00 "SIMR3,I2C Mode Register 3"
|
|
bitfld.byte 0x00 6.--7. " IICSCLS ,SCL Output Select" "Serial output,Start/restart/stop,Low level,High-Z"
|
|
bitfld.byte 0x00 4.--5. " IICSDAS ,SDA Output Select" "Serial output,Start/restart/stop,Low level,High-Z"
|
|
bitfld.byte 0x00 3. " IICSTIF ,Issuing of Start/Restart/Stop Condition Completed Flag" "Not generated,Generated"
|
|
bitfld.byte 0x00 2. " IICSTPREQ ,Stop Condition Generation" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " IICRSTAREQ ,Restart Condition Generation" "Not generated,Generated"
|
|
bitfld.byte 0x00 0. " IICSTAREQ ,Start Condition Generation" "Not generated,Generated"
|
|
line.byte 0x01 "SISR,I2C Status Register"
|
|
bitfld.byte 0x01 0. " IICACKR ,ACK Reception Data Flag" "ACK,NACK"
|
|
if (((per.b(ad:0x40070060+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070060+0x02))&0x10)==0x0)
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "SPMR,SPI Mode Register"
|
|
bitfld.byte 0x00 7. " CKPH ,Clock Phase Select" "Not delayed,Delayed"
|
|
bitfld.byte 0x00 6. " CKPOL ,Clock Polarity Select" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " MFF ,Mode Fault Flag" "No error,Error"
|
|
bitfld.byte 0x00 2. " MSS ,Master Slave Select" "Master,Slave"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SSE ,SSn Pin Function Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "SPMR,SPI Mode Register"
|
|
rbitfld.byte 0x00 7. " CKPH ,Clock Phase Select" "Not delayed,Delayed"
|
|
rbitfld.byte 0x00 6. " CKPOL ,Clock Polarity Select" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " MFF ,Mode Fault Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " MSS ,Master Slave Select" "Master,Slave"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " SSE ,SSn Pin Function Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40070060+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070060+0x02))&0x10)==0x0)
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 12.--15. " RSTRG ,RTS Output Active Trigger Number Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " RTRG ,Receive FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " TTRG ,Transmit FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 3. " DRES ,Receive Data Ready Error Select Bit" "Reception,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 0. " FM ,FIFO Mode Select" "Non-FIFO,FIFO"
|
|
else
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 12.--15. " RSTRG ,RTS Output Active Trigger Number Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " RTRG ,Receive FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " TTRG ,Transmit FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 3. " DRES ,Receive Data Ready Error Select Bit" "Reception,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO Data Register Reset" "No reset,Reset"
|
|
rbitfld.word 0x00 0. " FM ,FIFO Mode Select" "Non-FIFO,FIFO"
|
|
endif
|
|
rgroup.word 0x16++0x03
|
|
line.word 0x00 "FDR,FIFO Data Count Register"
|
|
bitfld.word 0x00 8.--12. " T ,Transmit FIFO Data Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " R ,Receive FIFO Data Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.word 0x02 "LSR,Line Status Register"
|
|
bitfld.word 0x02 8.--12. " PNUM ,Parity Error Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 2.--6. " FNUM ,Framing Error Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0. " ORER ,Overrun Error Flag" "No overrun,Overrun"
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "CDR,Compare Match Data Register"
|
|
hexmask.word 0x00 0.--8. 1. " CMPD ,Compare Match Data"
|
|
if (((per.b(ad:0x40070060))&0x80)==0x0)
|
|
group.word 0x13++0x01
|
|
line.word 0x00 "DCCR,Data Compare Match Control Register"
|
|
bitfld.word 0x00 7. " DCME ,Data Compare Match Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " IDSEL ,ID Frame Select" "Always compare MPB,Compare only MPB=1"
|
|
bitfld.word 0x00 4. " DFER ,Data Compare Match Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 3. " DPER ,Data Compare Match Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DCMF ,Data Compare Match Flag" "Not matched,Matched"
|
|
else
|
|
group.word 0x13++0x01
|
|
line.word 0x00 "DCCR,Data Compare Match Control Register"
|
|
bitfld.word 0x00 4. " DFER ,Data Compare Match Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 3. " DPER ,Data Compare Match Parity Error Flag" "No error,Error"
|
|
bitfld.word 0x00 0. " DCMF ,Data Compare Match Flag" "Not matched,Matched"
|
|
endif
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SPTR,Serial Port Register"
|
|
bitfld.byte 0x00 2. " SPB2IO ,Serial Port Break I/O" "No output,Output"
|
|
bitfld.byte 0x00 1. " SPB2DT ,Serial Port Break Data Select" "Low,High"
|
|
rbitfld.byte 0x00 0. " RXDMON ,Serial Input Data Monitor" "Low,High"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCI4"
|
|
base ad:0x40070080
|
|
width 8.
|
|
hgroup.byte 0x05++0x00
|
|
hide.byte 0x00 "RDR,Receive Data Register"
|
|
in
|
|
hgroup.word 0x10++0x01
|
|
hide.word 0x00 "RDRHL,Receive 9-bit Data Register"
|
|
in
|
|
if (((per.w(ad:0x40070080+0x14))&0x1)==0x1)
|
|
if (((per.b(ad:0x40070080))&0x4)==0x4)
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "FRDRHL,Receive FIFO Data Register HL"
|
|
bitfld.word 0x00 14. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.word 0x00 13. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.word 0x00 12. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 11. " PER ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DR ,Receive Data Ready Flag" "Not finished,Finished"
|
|
bitfld.word 0x00 9. " MPB ,Multi-Processor Bit Flag" "Data transmission,ID transmission"
|
|
hexmask.word 0x00 0.--8. 1. " RDAT ,Serial Receive Data"
|
|
else
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "FRDRHL,Receive FIFO Data Register HL"
|
|
bitfld.word 0x00 14. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.word 0x00 13. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.word 0x00 12. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 11. " PER ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DR ,Receive Data Ready Flag" "Not finished,Finished"
|
|
hexmask.word 0x00 0.--8. 1. " RDAT ,Serial Receive Data"
|
|
endif
|
|
else
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "FRDRHL,Receive FIFO Data Register HL"
|
|
bitfld.word 0x00 14. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.word 0x00 13. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.word 0x00 12. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 11. " PER ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DR ,Receive Data Ready Flag" "Not finished,Finished"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "TDR,Transmit Data Register"
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "TDRHL,Transmit 9-Bit Data Register"
|
|
if (((per.w(ad:0x40070080+0x14))&0x1)==0x1)
|
|
if (((per.b(ad:0x40070080))&0x4)==0x4)
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "FTDRHL,Transmit FIFO Data Register HL"
|
|
bitfld.word 0x00 9. " MPBT ,Multi-Processor Transfer Bit Flag" "Data,ID"
|
|
hexmask.word 0x00 0.--8. 1. " TDAT ,Serial Transmit Data"
|
|
else
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "FTDRHL,Transmit FIFO Data Register HL"
|
|
hexmask.word 0x00 0.--8. 1. " TDAT ,Serial Transmit Data"
|
|
endif
|
|
else
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "FTDRHL,Transmit FIFO Data Register HL"
|
|
endif
|
|
if (((per.b(ad:0x40070080+0x06))&0x1)==0x0)
|
|
if (((per.b(ad:0x40070080))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070080))&0x20)==0x0)
|
|
if (((per.b(ad:0x40070080+0x06))&0x10)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "9-bit,9-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "8-bit,7-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070080+0x06))&0x10)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "9-bit,9-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "8-bit,7-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
endif
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070080))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070080+0x06))&0x80)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "93 clock,128 clock,186 clock,512 clock"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "32 clock,64 clock,372 clock,256 clock"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070080+0x06))&0x80)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "93 clock,128 clock,186 clock,512 clock"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "32 clock,64 clock,372 clock,256 clock"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070080+0x06))&0x1)==0x0)
|
|
if (((per.b(ad:0x40070080))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070080))&0x4)==0x4)
|
|
if (((per.b(ad:0x40070080+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070080+0x02))&0x10)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK4,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK4,External,External"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070080+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070080+0x02))&0x10)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK4,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK4,External,External"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070080+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070080+0x02))&0x10)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Internal,Internal,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK4,External,External"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070080+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070080+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070080))&0x8)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Disabled,Output,,"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Low,Output,High,"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070080+0x06))&0x1)==0x0)&&(((per.b(ad:0x40070080+0x14))&0x1)==0x0)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " FER ,Framing Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
rbitfld.byte 0x00 1. " MPB ,Multi-Processor" "Data,ID"
|
|
bitfld.byte 0x00 0. " MPBT ,Multi-Processor Bit Transfer" "Data,ID"
|
|
elif (((per.b(ad:0x40070080+0x06))&0x1)==0x0)&&(((per.b(ad:0x40070080+0x14))&0x1)==0x1)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR_FIFO,Serial Status Register"
|
|
bitfld.byte 0x00 7. " TDFE ,Transmit FIFO Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " FER ,Framing Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
bitfld.byte 0x00 0. " DR ,Receive Data Ready Flag" "Not ready,Ready"
|
|
elif (((per.b(ad:0x40070080+0x06))&0x1)==0x1)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR_SMCI,Serial Status Register"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " ERS ,Error Signal Status Flag" "Not sampled,Sampled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
rbitfld.byte 0x00 1. " MPB ,Multi-Processor" "Data,ID"
|
|
bitfld.byte 0x00 0. " MPBT ,Multi-Processor Bit Transfer" "Data,ID"
|
|
endif
|
|
if (((per.b(ad:0x40070080+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070080+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070080))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070080))&0x40)==0x0)
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,8-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,7-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070080))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070080))&0x40)==0x0)
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,8-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
else
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,7-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
else
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070080+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070080+0x02))&0x10)==0x0)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "BRR,Bit Rate Register"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MDDR,Modulation Duty Register"
|
|
else
|
|
rgroup.byte 0x01++0x00
|
|
line.byte 0x00 "BRR,Bit Rate Register"
|
|
rgroup.byte 0x12++0x00
|
|
line.byte 0x00 "MDDR,Modulation Duty Register"
|
|
endif
|
|
if (((per.b(ad:0x40070080+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070080+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070080))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070080+0x02))&0x2)==0x0)
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 6. " BGDM ,Baud Rate Generator Double-Speed Mode Select" "Normal,Doubled"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ABCSE ,Asynchronous Mode Extended Base Clock Select 1" "1-bit,6 base"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070080))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070080+0x02))&0x2)==0x0)
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 6. " BGDM ,Baud Rate Generator Double-Speed Mode Select" "Normal,Doubled"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ABCSE ,Asynchronous Mode Extended Base Clock Select 1" "1-bit,6 base"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070080+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070080+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070080))&0x80)==0x0)
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" "/1,?..."
|
|
else
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" ",/1,/2,/3,/4,?..."
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070080))&0x80)==0x0)
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" "/1,?..."
|
|
else
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" ",/1,/2,/3,/4,?..."
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0x40070080+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070080+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070080+0x06))&0x1)==0x0)
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Asynchronous/Multi-processor/Clock-synchronous/Simple I2C,Simple I2C"
|
|
else
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Smart card interface,"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070080+0x06))&0x1)==0x0)
|
|
rgroup.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Asynchronous/Multi-processor/Clock-synchronous/Simple I2C,Simple I2C"
|
|
else
|
|
rgroup.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Smart card interface,"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0x40070080+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070080+0x02))&0x10)==0x0)
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SIMR2,I2C Mode Register 2"
|
|
bitfld.byte 0x00 5. " IICACKT ,ACK Transmission Data" "ACK,NACK"
|
|
bitfld.byte 0x00 1. " IICCSC ,Clock Synchronization" "No synchronization,Synchronization"
|
|
bitfld.byte 0x00 0. " IICINTM ,I2C Interrupt Mode Select" "ACK/NACK,Reception and transmission"
|
|
else
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SIMR2,I2C Mode Register 2"
|
|
bitfld.byte 0x00 5. " IICACKT ,ACK Transmission Data" "ACK,NACK"
|
|
rbitfld.byte 0x00 1. " IICCSC ,Clock Synchronization" "No synchronization,Synchronization"
|
|
rbitfld.byte 0x00 0. " IICINTM ,I2C Interrupt Mode Select" "ACK/NACK,Reception and transmission"
|
|
endif
|
|
group.byte 0x0B++0x01
|
|
line.byte 0x00 "SIMR3,I2C Mode Register 3"
|
|
bitfld.byte 0x00 6.--7. " IICSCLS ,SCL Output Select" "Serial output,Start/restart/stop,Low level,High-Z"
|
|
bitfld.byte 0x00 4.--5. " IICSDAS ,SDA Output Select" "Serial output,Start/restart/stop,Low level,High-Z"
|
|
bitfld.byte 0x00 3. " IICSTIF ,Issuing of Start/Restart/Stop Condition Completed Flag" "Not generated,Generated"
|
|
bitfld.byte 0x00 2. " IICSTPREQ ,Stop Condition Generation" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " IICRSTAREQ ,Restart Condition Generation" "Not generated,Generated"
|
|
bitfld.byte 0x00 0. " IICSTAREQ ,Start Condition Generation" "Not generated,Generated"
|
|
line.byte 0x01 "SISR,I2C Status Register"
|
|
bitfld.byte 0x01 0. " IICACKR ,ACK Reception Data Flag" "ACK,NACK"
|
|
if (((per.b(ad:0x40070080+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070080+0x02))&0x10)==0x0)
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "SPMR,SPI Mode Register"
|
|
bitfld.byte 0x00 7. " CKPH ,Clock Phase Select" "Not delayed,Delayed"
|
|
bitfld.byte 0x00 6. " CKPOL ,Clock Polarity Select" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " MFF ,Mode Fault Flag" "No error,Error"
|
|
bitfld.byte 0x00 2. " MSS ,Master Slave Select" "Master,Slave"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SSE ,SSn Pin Function Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "SPMR,SPI Mode Register"
|
|
rbitfld.byte 0x00 7. " CKPH ,Clock Phase Select" "Not delayed,Delayed"
|
|
rbitfld.byte 0x00 6. " CKPOL ,Clock Polarity Select" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " MFF ,Mode Fault Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " MSS ,Master Slave Select" "Master,Slave"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " SSE ,SSn Pin Function Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40070080+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070080+0x02))&0x10)==0x0)
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 12.--15. " RSTRG ,RTS Output Active Trigger Number Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " RTRG ,Receive FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " TTRG ,Transmit FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 3. " DRES ,Receive Data Ready Error Select Bit" "Reception,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 0. " FM ,FIFO Mode Select" "Non-FIFO,FIFO"
|
|
else
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 12.--15. " RSTRG ,RTS Output Active Trigger Number Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " RTRG ,Receive FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " TTRG ,Transmit FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 3. " DRES ,Receive Data Ready Error Select Bit" "Reception,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO Data Register Reset" "No reset,Reset"
|
|
rbitfld.word 0x00 0. " FM ,FIFO Mode Select" "Non-FIFO,FIFO"
|
|
endif
|
|
rgroup.word 0x16++0x03
|
|
line.word 0x00 "FDR,FIFO Data Count Register"
|
|
bitfld.word 0x00 8.--12. " T ,Transmit FIFO Data Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " R ,Receive FIFO Data Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.word 0x02 "LSR,Line Status Register"
|
|
bitfld.word 0x02 8.--12. " PNUM ,Parity Error Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 2.--6. " FNUM ,Framing Error Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0. " ORER ,Overrun Error Flag" "No overrun,Overrun"
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "CDR,Compare Match Data Register"
|
|
hexmask.word 0x00 0.--8. 1. " CMPD ,Compare Match Data"
|
|
if (((per.b(ad:0x40070080))&0x80)==0x0)
|
|
group.word 0x13++0x01
|
|
line.word 0x00 "DCCR,Data Compare Match Control Register"
|
|
bitfld.word 0x00 7. " DCME ,Data Compare Match Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " IDSEL ,ID Frame Select" "Always compare MPB,Compare only MPB=1"
|
|
bitfld.word 0x00 4. " DFER ,Data Compare Match Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 3. " DPER ,Data Compare Match Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DCMF ,Data Compare Match Flag" "Not matched,Matched"
|
|
else
|
|
group.word 0x13++0x01
|
|
line.word 0x00 "DCCR,Data Compare Match Control Register"
|
|
bitfld.word 0x00 4. " DFER ,Data Compare Match Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 3. " DPER ,Data Compare Match Parity Error Flag" "No error,Error"
|
|
bitfld.word 0x00 0. " DCMF ,Data Compare Match Flag" "Not matched,Matched"
|
|
endif
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SPTR,Serial Port Register"
|
|
bitfld.byte 0x00 2. " SPB2IO ,Serial Port Break I/O" "No output,Output"
|
|
bitfld.byte 0x00 1. " SPB2DT ,Serial Port Break Data Select" "Low,High"
|
|
rbitfld.byte 0x00 0. " RXDMON ,Serial Input Data Monitor" "Low,High"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCI9"
|
|
base ad:0x40070120
|
|
width 8.
|
|
hgroup.byte 0x05++0x00
|
|
hide.byte 0x00 "RDR,Receive Data Register"
|
|
in
|
|
hgroup.word 0x10++0x01
|
|
hide.word 0x00 "RDRHL,Receive 9-bit Data Register"
|
|
in
|
|
if (((per.w(ad:0x40070120+0x14))&0x1)==0x1)
|
|
if (((per.b(ad:0x40070120))&0x4)==0x4)
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "FRDRHL,Receive FIFO Data Register HL"
|
|
bitfld.word 0x00 14. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.word 0x00 13. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.word 0x00 12. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 11. " PER ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DR ,Receive Data Ready Flag" "Not finished,Finished"
|
|
bitfld.word 0x00 9. " MPB ,Multi-Processor Bit Flag" "Data transmission,ID transmission"
|
|
hexmask.word 0x00 0.--8. 1. " RDAT ,Serial Receive Data"
|
|
else
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "FRDRHL,Receive FIFO Data Register HL"
|
|
bitfld.word 0x00 14. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.word 0x00 13. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.word 0x00 12. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 11. " PER ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DR ,Receive Data Ready Flag" "Not finished,Finished"
|
|
hexmask.word 0x00 0.--8. 1. " RDAT ,Serial Receive Data"
|
|
endif
|
|
else
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "FRDRHL,Receive FIFO Data Register HL"
|
|
bitfld.word 0x00 14. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.word 0x00 13. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.word 0x00 12. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 11. " PER ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 10. " DR ,Receive Data Ready Flag" "Not finished,Finished"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "TDR,Transmit Data Register"
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "TDRHL,Transmit 9-Bit Data Register"
|
|
if (((per.w(ad:0x40070120+0x14))&0x1)==0x1)
|
|
if (((per.b(ad:0x40070120))&0x4)==0x4)
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "FTDRHL,Transmit FIFO Data Register HL"
|
|
bitfld.word 0x00 9. " MPBT ,Multi-Processor Transfer Bit Flag" "Data,ID"
|
|
hexmask.word 0x00 0.--8. 1. " TDAT ,Serial Transmit Data"
|
|
else
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "FTDRHL,Transmit FIFO Data Register HL"
|
|
hexmask.word 0x00 0.--8. 1. " TDAT ,Serial Transmit Data"
|
|
endif
|
|
else
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "FTDRHL,Transmit FIFO Data Register HL"
|
|
endif
|
|
if (((per.b(ad:0x40070120+0x06))&0x1)==0x0)
|
|
if (((per.b(ad:0x40070120))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070120))&0x20)==0x0)
|
|
if (((per.b(ad:0x40070120+0x06))&0x10)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "9-bit,9-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "8-bit,7-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070120+0x06))&0x10)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "9-bit,9-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length" "8-bit,7-bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 stop,2 stop"
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
endif
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/I2C,Clock-synchronous/SPI"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070120))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070120+0x06))&0x80)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "93 clock,128 clock,186 clock,512 clock"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "32 clock,64 clock,372 clock,256 clock"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070120+0x06))&0x80)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "93 clock,128 clock,186 clock,512 clock"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register"
|
|
bitfld.byte 0x00 7. " GM ,GSM Mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "Normal,Block"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse" "32 clock,64 clock,372 clock,256 clock"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" ",/4,/16,/64"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070120+0x06))&0x1)==0x0)
|
|
if (((per.b(ad:0x40070120))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070120))&0x4)==0x4)
|
|
if (((per.b(ad:0x40070120+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070120+0x02))&0x10)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK9,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Enabled,Disabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK9,External,External"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070120+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070120+0x02))&0x10)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK9,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK9,External,External"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070120+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070120+0x02))&0x10)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Internal,Internal,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "I/O port,SCK9,External,External"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070120+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070120+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070120))&0x8)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Disabled,Output,,"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Low,Output,High,"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070120+0x06))&0x1)==0x0)&&(((per.b(ad:0x40070120+0x14))&0x1)==0x0)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " FER ,Framing Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
rbitfld.byte 0x00 1. " MPB ,Multi-Processor" "Data,ID"
|
|
bitfld.byte 0x00 0. " MPBT ,Multi-Processor Bit Transfer" "Data,ID"
|
|
elif (((per.b(ad:0x40070120+0x06))&0x1)==0x0)&&(((per.b(ad:0x40070120+0x14))&0x1)==0x1)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR_FIFO,Serial Status Register"
|
|
bitfld.byte 0x00 7. " TDFE ,Transmit FIFO Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " FER ,Framing Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
bitfld.byte 0x00 0. " DR ,Receive Data Ready Flag" "Not ready,Ready"
|
|
elif (((per.b(ad:0x40070120+0x06))&0x1)==0x1)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR_SMCI,Serial Status Register"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 4. " ERS ,Error Signal Status Flag" "Not sampled,Sampled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
rbitfld.byte 0x00 1. " MPB ,Multi-Processor" "Data,ID"
|
|
bitfld.byte 0x00 0. " MPBT ,Multi-Processor Bit Transfer" "Data,ID"
|
|
endif
|
|
if (((per.b(ad:0x40070120+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070120+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070120))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070120))&0x40)==0x0)
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,8-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,7-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070120))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070120))&0x40)==0x0)
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,8-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
else
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9-bit,7-bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
else
|
|
rgroup.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070120+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070120+0x02))&0x10)==0x0)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "BRR,Bit Rate Register"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MDDR,Modulation Duty Register"
|
|
else
|
|
rgroup.byte 0x01++0x00
|
|
line.byte 0x00 "BRR,Bit Rate Register"
|
|
rgroup.byte 0x12++0x00
|
|
line.byte 0x00 "MDDR,Modulation Duty Register"
|
|
endif
|
|
if (((per.b(ad:0x40070120+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070120+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070120))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070120+0x02))&0x2)==0x0)
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 6. " BGDM ,Baud Rate Generator Double-Speed Mode Select" "Normal,Doubled"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ABCSE ,Asynchronous Mode Extended Base Clock Select 1" "1-bit,6 base"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070120))&0x80)==0x0)
|
|
if (((per.b(ad:0x40070120+0x02))&0x2)==0x0)
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 6. " BGDM ,Baud Rate Generator Double-Speed Mode Select" "Normal,Doubled"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ABCSE ,Asynchronous Mode Extended Base Clock Select 1" "1-bit,6 base"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous ModeBase Clock Select" "16,8"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
rgroup.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070120+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070120+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070120))&0x80)==0x0)
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" "/1,?..."
|
|
else
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" ",/1,/2,/3,/4,?..."
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070120))&0x80)==0x0)
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" "/1,?..."
|
|
else
|
|
rgroup.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" ",/1,/2,/3,/4,?..."
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0x40070120+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070120+0x02))&0x10)==0x0)
|
|
if (((per.b(ad:0x40070120+0x06))&0x1)==0x0)
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Asynchronous/Multi-processor/Clock-synchronous/Simple I2C,Simple I2C"
|
|
else
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Smart card interface,"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070120+0x06))&0x1)==0x0)
|
|
rgroup.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Asynchronous/Multi-processor/Clock-synchronous/Simple I2C,Simple I2C"
|
|
else
|
|
rgroup.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No output,0-1,1-2,2-3,3-4,4-5,5-6,6-7,7-8,8-9,9-10,10-11,11-12,12-13,13-14,14-15,15-16,16-17,17-18,18-19,19-20,20-21,21-22,22-23,23-24,24-25,25-26,26-27,27-28,28-29,29-30,30-31"
|
|
bitfld.byte 0x00 0. " IICM ,Simple I2C Mode Select" "Smart card interface,"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0x40070120+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070120+0x02))&0x10)==0x0)
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SIMR2,I2C Mode Register 2"
|
|
bitfld.byte 0x00 5. " IICACKT ,ACK Transmission Data" "ACK,NACK"
|
|
bitfld.byte 0x00 1. " IICCSC ,Clock Synchronization" "No synchronization,Synchronization"
|
|
bitfld.byte 0x00 0. " IICINTM ,I2C Interrupt Mode Select" "ACK/NACK,Reception and transmission"
|
|
else
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SIMR2,I2C Mode Register 2"
|
|
bitfld.byte 0x00 5. " IICACKT ,ACK Transmission Data" "ACK,NACK"
|
|
rbitfld.byte 0x00 1. " IICCSC ,Clock Synchronization" "No synchronization,Synchronization"
|
|
rbitfld.byte 0x00 0. " IICINTM ,I2C Interrupt Mode Select" "ACK/NACK,Reception and transmission"
|
|
endif
|
|
group.byte 0x0B++0x01
|
|
line.byte 0x00 "SIMR3,I2C Mode Register 3"
|
|
bitfld.byte 0x00 6.--7. " IICSCLS ,SCL Output Select" "Serial output,Start/restart/stop,Low level,High-Z"
|
|
bitfld.byte 0x00 4.--5. " IICSDAS ,SDA Output Select" "Serial output,Start/restart/stop,Low level,High-Z"
|
|
bitfld.byte 0x00 3. " IICSTIF ,Issuing of Start/Restart/Stop Condition Completed Flag" "Not generated,Generated"
|
|
bitfld.byte 0x00 2. " IICSTPREQ ,Stop Condition Generation" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " IICRSTAREQ ,Restart Condition Generation" "Not generated,Generated"
|
|
bitfld.byte 0x00 0. " IICSTAREQ ,Start Condition Generation" "Not generated,Generated"
|
|
line.byte 0x01 "SISR,I2C Status Register"
|
|
bitfld.byte 0x01 0. " IICACKR ,ACK Reception Data Flag" "ACK,NACK"
|
|
if (((per.b(ad:0x40070120+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070120+0x02))&0x10)==0x0)
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "SPMR,SPI Mode Register"
|
|
bitfld.byte 0x00 7. " CKPH ,Clock Phase Select" "Not delayed,Delayed"
|
|
bitfld.byte 0x00 6. " CKPOL ,Clock Polarity Select" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " MFF ,Mode Fault Flag" "No error,Error"
|
|
bitfld.byte 0x00 2. " MSS ,Master Slave Select" "Master,Slave"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SSE ,SSn Pin Function Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "SPMR,SPI Mode Register"
|
|
rbitfld.byte 0x00 7. " CKPH ,Clock Phase Select" "Not delayed,Delayed"
|
|
rbitfld.byte 0x00 6. " CKPOL ,Clock Polarity Select" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " MFF ,Mode Fault Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " MSS ,Master Slave Select" "Master,Slave"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " SSE ,SSn Pin Function Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40070120+0x02))&0x20)==0x0)&&(((per.b(ad:0x40070120+0x02))&0x10)==0x0)
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 12.--15. " RSTRG ,RTS Output Active Trigger Number Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " RTRG ,Receive FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " TTRG ,Transmit FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 3. " DRES ,Receive Data Ready Error Select Bit" "Reception,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 0. " FM ,FIFO Mode Select" "Non-FIFO,FIFO"
|
|
else
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 12.--15. " RSTRG ,RTS Output Active Trigger Number Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " RTRG ,Receive FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " TTRG ,Transmit FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 3. " DRES ,Receive Data Ready Error Select Bit" "Reception,Receive"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO Data Register Reset" "No reset,Reset"
|
|
rbitfld.word 0x00 0. " FM ,FIFO Mode Select" "Non-FIFO,FIFO"
|
|
endif
|
|
rgroup.word 0x16++0x03
|
|
line.word 0x00 "FDR,FIFO Data Count Register"
|
|
bitfld.word 0x00 8.--12. " T ,Transmit FIFO Data Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " R ,Receive FIFO Data Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.word 0x02 "LSR,Line Status Register"
|
|
bitfld.word 0x02 8.--12. " PNUM ,Parity Error Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 2.--6. " FNUM ,Framing Error Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x02 0. " ORER ,Overrun Error Flag" "No overrun,Overrun"
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "CDR,Compare Match Data Register"
|
|
hexmask.word 0x00 0.--8. 1. " CMPD ,Compare Match Data"
|
|
if (((per.b(ad:0x40070120))&0x80)==0x0)
|
|
group.word 0x13++0x01
|
|
line.word 0x00 "DCCR,Data Compare Match Control Register"
|
|
bitfld.word 0x00 7. " DCME ,Data Compare Match Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " IDSEL ,ID Frame Select" "Always compare MPB,Compare only MPB=1"
|
|
bitfld.word 0x00 4. " DFER ,Data Compare Match Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 3. " DPER ,Data Compare Match Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DCMF ,Data Compare Match Flag" "Not matched,Matched"
|
|
else
|
|
group.word 0x13++0x01
|
|
line.word 0x00 "DCCR,Data Compare Match Control Register"
|
|
bitfld.word 0x00 4. " DFER ,Data Compare Match Framing Error Flag" "No error,Error"
|
|
bitfld.word 0x00 3. " DPER ,Data Compare Match Parity Error Flag" "No error,Error"
|
|
bitfld.word 0x00 0. " DCMF ,Data Compare Match Flag" "Not matched,Matched"
|
|
endif
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SPTR,Serial Port Register"
|
|
bitfld.byte 0x00 2. " SPB2IO ,Serial Port Break I/O" "No output,Output"
|
|
bitfld.byte 0x00 1. " SPB2DT ,Serial Port Break Data Select" "Low,High"
|
|
rbitfld.byte 0x00 0. " RXDMON ,Serial Input Data Monitor" "Low,High"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "IrDA Interface"
|
|
base ad:0x40070F00
|
|
width 6.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "IRCR,IrDA Control Register"
|
|
bitfld.byte 0x00 7. " IRE ,IrDA enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " IRTXINV ,IRTXD polarity switching" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 2. " IRRXINV ,IRRXD polarity switching" "Not inverted,Inverted"
|
|
width 0x0B
|
|
tree.end
|
|
tree "IIC (I2C Bus Interface)"
|
|
tree "Channel 0"
|
|
base ad:0x40053000
|
|
width 8.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "ICCR1,I2C Bus Control Register 1"
|
|
bitfld.byte 0x00 7. " ICE ,IIC Interface Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " IICRST ,IIC Interface Internal Reset" "Released,Initiated"
|
|
bitfld.byte 0x00 5. " CLO ,Extra SCL Clock Cycle Output" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " SOWP ,SCLO/SDAO Write Protect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SCLO ,SCL Output Control/Monitor" "Not released,Released"
|
|
bitfld.byte 0x00 2. " SDAO ,SDA Output Control/Monitor" "Not released,Released"
|
|
rbitfld.byte 0x00 1. " SCLI ,SCL Line Monitor" "Low,High"
|
|
rbitfld.byte 0x00 0. " SDAI ,SDA Line Monitor" "Low,High"
|
|
if (((per.b(ad:0x40053000+0x02))&0x80)==0x0)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "ICCR2,I2C Bus Control Register 2"
|
|
rbitfld.byte 0x00 7. " BBSY ,Bus Busy Detection Flag" "Released,Occupied"
|
|
rbitfld.byte 0x00 6. " MST ,Master/Slave Mode" "Slave,Master"
|
|
rbitfld.byte 0x00 5. " TRS ,Transmit/Receive Mode" "Receive,Transmit"
|
|
bitfld.byte 0x00 3. " SP ,Stop Condition Issuance Request" "No request,Request"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RS ,Restart Condition Issuance Request" "No request,Request"
|
|
bitfld.byte 0x00 1. " ST ,Start Condition Issuance Request" "No request,Request"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "ICCR2,I2C Bus Control Register 2"
|
|
rbitfld.byte 0x00 7. " BBSY ,Bus Busy Detection Flag" "Released,Occupied"
|
|
bitfld.byte 0x00 6. " MST ,Master/Slave Mode" "Slave,Master"
|
|
bitfld.byte 0x00 5. " TRS ,Transmit/Receive Mode" "Receive,Transmit"
|
|
bitfld.byte 0x00 3. " SP ,Stop Condition Issuance Request" "No request,Request"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RS ,Restart Condition Issuance Request" "No request,Request"
|
|
bitfld.byte 0x00 1. " ST ,Start Condition Issuance Request" "No request,Request"
|
|
endif
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ICMR1,I2C Bus Mode Register 1"
|
|
bitfld.byte 0x00 7. " MTWP ,MST/TRS Write Protect" "Enabled,Disabled"
|
|
bitfld.byte 0x00 4.--6. " CKS ,Internal Reference Clock Select" "PCLKB,PCLKB/2,PCLKB/4,PCLKB/8,PCLKB/16,PCLKB/32,PCLKB/64,PCLKB/128"
|
|
bitfld.byte 0x00 3. " BCWP ,BC Write Protect" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " BC ,Bit Counter" "9,2,3,4,5,6,7,8"
|
|
if (((per.b(ad:0x40053000+0x03))&0x80)==0x0)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "ICMR2,I2C Bus Mode Register 2"
|
|
bitfld.byte 0x00 7. " DLCS ,SDA Output Delay Clock Source Select" "IIC clock,IIC clock/2"
|
|
bitfld.byte 0x00 4.--6. " SDDL ,SDA Output Delay Counter" "No output,1 IIC cycle,2 IIC cycles,3 IIC cycles,4 IIC cycles,5 IIC cycles,6 IIC cycles,7 IIC cycles"
|
|
bitfld.byte 0x00 2. " TMOH ,Timeout H Count Control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " TMOL ,Timeout L Count Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TMOS ,Timeout Detection Time Select" "Long,Short"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "ICMR2,I2C Bus Mode Register 2"
|
|
bitfld.byte 0x00 7. " DLCS ,SDA Output Delay Clock Source Select" ",/2"
|
|
bitfld.byte 0x00 4.--6. " SDDL ,SDA Output Delay Counter" "No output,1/2 IIC cycles,3/4 IIC cycles,5/6 IIC cycles,7/8 IIC cycles,9/10 IIC cycles,11/12 IIC cycles,13/14 IIC cycles"
|
|
bitfld.byte 0x00 2. " TMOH ,Timeout H Count Control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " TMOL ,Timeout L Count Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TMOS ,Timeout Detection Time Select" "Long,Short"
|
|
endif
|
|
if (((per.b(ad:0x40053000+0x01))&0x20)==0x0)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ICMR3,I2C Bus Mode Register 3"
|
|
bitfld.byte 0x00 7. " SMBS ,SMBus/I2C Bus Select" "I2C bus,SMBus"
|
|
bitfld.byte 0x00 6. " WAIT ,WAIT" "No wait,Wait"
|
|
bitfld.byte 0x00 5. " RDRFS ,RDRF Flag Set Timing Select" "9th cycle,8th cycle"
|
|
bitfld.byte 0x00 4. " ACKWP ,ACKBT Write Protect" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ACKBT ,Transmit Acknowledge" "NACK,ACK"
|
|
rbitfld.byte 0x00 2. " ACKBR ,Receive Acknowledge" "NACK,ACK"
|
|
bitfld.byte 0x00 0.--1. " NF ,Noise Filter Stage Select" "1-stage,2-stage,3-stage,4-stage"
|
|
else
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ICMR3,I2C Bus Mode Register 3"
|
|
bitfld.byte 0x00 7. " SMBS ,SMBus/I2C Bus Select" "I2C bus,SMBus"
|
|
bitfld.byte 0x00 4. " ACKWP ,ACKBT Write Protect" "Enabled,Disabled"
|
|
bitfld.byte 0x00 3. " ACKBT ,Transmit Acknowledge" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " ACKBR ,Receive Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " NF ,Noise Filter Stage Select" "1-stage,2-stage,3-stage,4-stage"
|
|
endif
|
|
group.byte 0x05++0x04
|
|
line.byte 0x00 "ICFER,I2C Bus Function Enable Register"
|
|
bitfld.byte 0x00 6. " SCLE ,SCL Synchronous Circuit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " NFE ,Digital Noise Filter Circuit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " NACKE ,NACK Reception Transfer Suspension Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SALE ,Slave Arbitration-Lost Detection Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " NALE ,NACK Transmission Arbitration-Lost Detection Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " MALE ,Master Arbitration-Lost Detection Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TMOE ,Timeout Function Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "ICSER,I2C Bus Status Enable Register"
|
|
bitfld.byte 0x01 7. " HOAE ,Host Address Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " DIDE ,Device-ID Address Detection Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 3. " GCAE ,General Call Address Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " SAR2E ,Slave Address Register 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " SAR1E ,Slave Address Register 1 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " SAR0E ,Slave Address Register 0 Enable" "Disabled,Enabled"
|
|
line.byte 0x02 "ICIER,I2C Bus Interrupt Enable Register"
|
|
bitfld.byte 0x02 7. " TIE ,Transmit Data Empty Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " TEIE ,Transmit End Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " RIE ,Receive Data Full Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 4. " NAKIE ,NACK Reception Interrupt Request Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x02 3. " SPIE ,Stop Condition Detection Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 2. " STIE ,Start Condition Detection Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 1. " ALIE ,Arbitration-Lost Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " TMOIE ,Timeout Interrupt Request Enable" "Disabled,Enabled"
|
|
line.byte 0x03 "ICSR1,I2C Bus Status Register 1"
|
|
bitfld.byte 0x03 7. " HOA ,Host Address Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x03 5. " DID ,Device-ID Address Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x03 3. " GCA ,General Call Address Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x03 2. " AAS2 ,Slave Address 2 Detection Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " AAS1 ,Slave Address 1 Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x03 0. " AAS0 ,Slave Address 0 Detection Flag" "Not detected,Detected"
|
|
line.byte 0x04 "ICSR2,I2C Bus Status Register 2"
|
|
rbitfld.byte 0x04 7. " TDRE ,Transmit Data Empty Flag" "Not completed,Completed"
|
|
bitfld.byte 0x04 6. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
bitfld.byte 0x04 5. " RDRF ,Receive Data Full Flag" "Not received,Received"
|
|
bitfld.byte 0x04 4. " NACKF ,NACK Detection Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x04 3. " STOP ,Stop Condition Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x04 2. " START ,Start Condition Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x04 1. " AL ,Arbitration-Lost Flag" "Not lost,Lost"
|
|
bitfld.byte 0x04 0. " TMOF ,Timeout Detection Flag" "Not detected,Detected"
|
|
if (((per.b(ad:0x40053000))&0x40)==0)
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "ICWUR,I2C Bus Wakeup Unit Register"
|
|
bitfld.byte 0x00 7. " WUE ,Wakeup Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " WUIE ,Wakeup Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " WUF ,Wakeup Event Occurrence Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " WUACK ,ACK bit for Wakeup Mode" "Normal wakeup 1,Normal wakeup 2"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " WUAFA ,Wakeup Analog Filter Additional Selection" "Not added,Added"
|
|
else
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "ICWUR,I2C Bus Wakeup Unit Register"
|
|
bitfld.byte 0x00 7. " WUE ,Wakeup Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " WUIE ,Wakeup Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " WUF ,Wakeup Event Occurrence Flag" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " WUACK ,ACK bit for Wakeup Mode" "Command return,EEP response"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " WUAFA ,Wakeup Analog Filter Additional Selection" "Not added,Added"
|
|
endif
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "SARL0,Slave Address Register L0"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " SVA0 ,10-Bit Address LSB" "0,1"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "SARL1,Slave Address Register L1"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " SVA0 ,10-Bit Address LSB" "0,1"
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "SARL2,Slave Address Register L2"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " SVA0 ,10-Bit Address LSB" "0,1"
|
|
group.byte 0xB++0x00
|
|
line.byte 0x00 "SARU0,Slave Address Register U0"
|
|
bitfld.byte 0x00 1.--2. " SVA ,10-Bit Address Upper Bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0. " FS ,7-Bit/10-Bit Address Format Select" "7-bit,10-bit"
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "SARU1,Slave Address Register U1"
|
|
bitfld.byte 0x00 1.--2. " SVA ,10-Bit Address Upper Bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0. " FS ,7-Bit/10-Bit Address Format Select" "7-bit,10-bit"
|
|
group.byte 0xF++0x00
|
|
line.byte 0x00 "SARU2,Slave Address Register U2"
|
|
bitfld.byte 0x00 1.--2. " SVA ,10-Bit Address Upper Bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0. " FS ,7-Bit/10-Bit Address Format Select" "7-bit,10-bit"
|
|
group.byte 0x10++0x02
|
|
line.byte 0x00 "ICBRL,I2C Bus Bit Rate Low-Level Register"
|
|
bitfld.byte 0x00 0.--4. " BRL ,Bit Rate Low-Level Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "ICBRH,I2C Bus Bit Rate High-Level Register"
|
|
bitfld.byte 0x01 0.--4. " BRH ,Bit Rate High-Level Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x02 "ICDRT,I2C Bus Transmit Data Register"
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "ICDRR,I2C Bus Receive Data Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0x40053100
|
|
width 8.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "ICCR1,I2C Bus Control Register 1"
|
|
bitfld.byte 0x00 7. " ICE ,IIC Interface Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " IICRST ,IIC Interface Internal Reset" "Released,Initiated"
|
|
bitfld.byte 0x00 5. " CLO ,Extra SCL Clock Cycle Output" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " SOWP ,SCLO/SDAO Write Protect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SCLO ,SCL Output Control/Monitor" "Not released,Released"
|
|
bitfld.byte 0x00 2. " SDAO ,SDA Output Control/Monitor" "Not released,Released"
|
|
rbitfld.byte 0x00 1. " SCLI ,SCL Line Monitor" "Low,High"
|
|
rbitfld.byte 0x00 0. " SDAI ,SDA Line Monitor" "Low,High"
|
|
if (((per.b(ad:0x40053100+0x02))&0x80)==0x0)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "ICCR2,I2C Bus Control Register 2"
|
|
rbitfld.byte 0x00 7. " BBSY ,Bus Busy Detection Flag" "Released,Occupied"
|
|
rbitfld.byte 0x00 6. " MST ,Master/Slave Mode" "Slave,Master"
|
|
rbitfld.byte 0x00 5. " TRS ,Transmit/Receive Mode" "Receive,Transmit"
|
|
bitfld.byte 0x00 3. " SP ,Stop Condition Issuance Request" "No request,Request"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RS ,Restart Condition Issuance Request" "No request,Request"
|
|
bitfld.byte 0x00 1. " ST ,Start Condition Issuance Request" "No request,Request"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "ICCR2,I2C Bus Control Register 2"
|
|
rbitfld.byte 0x00 7. " BBSY ,Bus Busy Detection Flag" "Released,Occupied"
|
|
bitfld.byte 0x00 6. " MST ,Master/Slave Mode" "Slave,Master"
|
|
bitfld.byte 0x00 5. " TRS ,Transmit/Receive Mode" "Receive,Transmit"
|
|
bitfld.byte 0x00 3. " SP ,Stop Condition Issuance Request" "No request,Request"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RS ,Restart Condition Issuance Request" "No request,Request"
|
|
bitfld.byte 0x00 1. " ST ,Start Condition Issuance Request" "No request,Request"
|
|
endif
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ICMR1,I2C Bus Mode Register 1"
|
|
bitfld.byte 0x00 7. " MTWP ,MST/TRS Write Protect" "Enabled,Disabled"
|
|
bitfld.byte 0x00 4.--6. " CKS ,Internal Reference Clock Select" "PCLKB,PCLKB/2,PCLKB/4,PCLKB/8,PCLKB/16,PCLKB/32,PCLKB/64,PCLKB/128"
|
|
bitfld.byte 0x00 3. " BCWP ,BC Write Protect" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " BC ,Bit Counter" "9,2,3,4,5,6,7,8"
|
|
if (((per.b(ad:0x40053100+0x03))&0x80)==0x0)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "ICMR2,I2C Bus Mode Register 2"
|
|
bitfld.byte 0x00 7. " DLCS ,SDA Output Delay Clock Source Select" "IIC clock,IIC clock/2"
|
|
bitfld.byte 0x00 4.--6. " SDDL ,SDA Output Delay Counter" "No output,1 IIC cycle,2 IIC cycles,3 IIC cycles,4 IIC cycles,5 IIC cycles,6 IIC cycles,7 IIC cycles"
|
|
bitfld.byte 0x00 2. " TMOH ,Timeout H Count Control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " TMOL ,Timeout L Count Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TMOS ,Timeout Detection Time Select" "Long,Short"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "ICMR2,I2C Bus Mode Register 2"
|
|
bitfld.byte 0x00 7. " DLCS ,SDA Output Delay Clock Source Select" ",/2"
|
|
bitfld.byte 0x00 4.--6. " SDDL ,SDA Output Delay Counter" "No output,1/2 IIC cycles,3/4 IIC cycles,5/6 IIC cycles,7/8 IIC cycles,9/10 IIC cycles,11/12 IIC cycles,13/14 IIC cycles"
|
|
bitfld.byte 0x00 2. " TMOH ,Timeout H Count Control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " TMOL ,Timeout L Count Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TMOS ,Timeout Detection Time Select" "Long,Short"
|
|
endif
|
|
if (((per.b(ad:0x40053100+0x01))&0x20)==0x0)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ICMR3,I2C Bus Mode Register 3"
|
|
bitfld.byte 0x00 7. " SMBS ,SMBus/I2C Bus Select" "I2C bus,SMBus"
|
|
bitfld.byte 0x00 6. " WAIT ,WAIT" "No wait,Wait"
|
|
bitfld.byte 0x00 5. " RDRFS ,RDRF Flag Set Timing Select" "9th cycle,8th cycle"
|
|
bitfld.byte 0x00 4. " ACKWP ,ACKBT Write Protect" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ACKBT ,Transmit Acknowledge" "NACK,ACK"
|
|
rbitfld.byte 0x00 2. " ACKBR ,Receive Acknowledge" "NACK,ACK"
|
|
bitfld.byte 0x00 0.--1. " NF ,Noise Filter Stage Select" "1-stage,2-stage,3-stage,4-stage"
|
|
else
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ICMR3,I2C Bus Mode Register 3"
|
|
bitfld.byte 0x00 7. " SMBS ,SMBus/I2C Bus Select" "I2C bus,SMBus"
|
|
bitfld.byte 0x00 4. " ACKWP ,ACKBT Write Protect" "Enabled,Disabled"
|
|
bitfld.byte 0x00 3. " ACKBT ,Transmit Acknowledge" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " ACKBR ,Receive Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " NF ,Noise Filter Stage Select" "1-stage,2-stage,3-stage,4-stage"
|
|
endif
|
|
group.byte 0x05++0x04
|
|
line.byte 0x00 "ICFER,I2C Bus Function Enable Register"
|
|
bitfld.byte 0x00 6. " SCLE ,SCL Synchronous Circuit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " NFE ,Digital Noise Filter Circuit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " NACKE ,NACK Reception Transfer Suspension Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SALE ,Slave Arbitration-Lost Detection Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " NALE ,NACK Transmission Arbitration-Lost Detection Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " MALE ,Master Arbitration-Lost Detection Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TMOE ,Timeout Function Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "ICSER,I2C Bus Status Enable Register"
|
|
bitfld.byte 0x01 7. " HOAE ,Host Address Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " DIDE ,Device-ID Address Detection Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 3. " GCAE ,General Call Address Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " SAR2E ,Slave Address Register 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " SAR1E ,Slave Address Register 1 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " SAR0E ,Slave Address Register 0 Enable" "Disabled,Enabled"
|
|
line.byte 0x02 "ICIER,I2C Bus Interrupt Enable Register"
|
|
bitfld.byte 0x02 7. " TIE ,Transmit Data Empty Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " TEIE ,Transmit End Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " RIE ,Receive Data Full Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 4. " NAKIE ,NACK Reception Interrupt Request Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x02 3. " SPIE ,Stop Condition Detection Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 2. " STIE ,Start Condition Detection Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 1. " ALIE ,Arbitration-Lost Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " TMOIE ,Timeout Interrupt Request Enable" "Disabled,Enabled"
|
|
line.byte 0x03 "ICSR1,I2C Bus Status Register 1"
|
|
bitfld.byte 0x03 7. " HOA ,Host Address Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x03 5. " DID ,Device-ID Address Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x03 3. " GCA ,General Call Address Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x03 2. " AAS2 ,Slave Address 2 Detection Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " AAS1 ,Slave Address 1 Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x03 0. " AAS0 ,Slave Address 0 Detection Flag" "Not detected,Detected"
|
|
line.byte 0x04 "ICSR2,I2C Bus Status Register 2"
|
|
rbitfld.byte 0x04 7. " TDRE ,Transmit Data Empty Flag" "Not completed,Completed"
|
|
bitfld.byte 0x04 6. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
bitfld.byte 0x04 5. " RDRF ,Receive Data Full Flag" "Not received,Received"
|
|
bitfld.byte 0x04 4. " NACKF ,NACK Detection Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x04 3. " STOP ,Stop Condition Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x04 2. " START ,Start Condition Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x04 1. " AL ,Arbitration-Lost Flag" "Not lost,Lost"
|
|
bitfld.byte 0x04 0. " TMOF ,Timeout Detection Flag" "Not detected,Detected"
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "SARL0,Slave Address Register L0"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " SVA0 ,10-Bit Address LSB" "0,1"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "SARL1,Slave Address Register L1"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " SVA0 ,10-Bit Address LSB" "0,1"
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "SARL2,Slave Address Register L2"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " SVA0 ,10-Bit Address LSB" "0,1"
|
|
group.byte 0xB++0x00
|
|
line.byte 0x00 "SARU0,Slave Address Register U0"
|
|
bitfld.byte 0x00 1.--2. " SVA ,10-Bit Address Upper Bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0. " FS ,7-Bit/10-Bit Address Format Select" "7-bit,10-bit"
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "SARU1,Slave Address Register U1"
|
|
bitfld.byte 0x00 1.--2. " SVA ,10-Bit Address Upper Bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0. " FS ,7-Bit/10-Bit Address Format Select" "7-bit,10-bit"
|
|
group.byte 0xF++0x00
|
|
line.byte 0x00 "SARU2,Slave Address Register U2"
|
|
bitfld.byte 0x00 1.--2. " SVA ,10-Bit Address Upper Bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0. " FS ,7-Bit/10-Bit Address Format Select" "7-bit,10-bit"
|
|
group.byte 0x10++0x02
|
|
line.byte 0x00 "ICBRL,I2C Bus Bit Rate Low-Level Register"
|
|
bitfld.byte 0x00 0.--4. " BRL ,Bit Rate Low-Level Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "ICBRH,I2C Bus Bit Rate High-Level Register"
|
|
bitfld.byte 0x01 0.--4. " BRH ,Bit Rate High-Level Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x02 "ICDRT,I2C Bus Transmit Data Register"
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "ICDRR,I2C Bus Receive Data Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
tree "Channel 2"
|
|
base ad:0x40053200
|
|
width 8.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "ICCR1,I2C Bus Control Register 1"
|
|
bitfld.byte 0x00 7. " ICE ,IIC Interface Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " IICRST ,IIC Interface Internal Reset" "Released,Initiated"
|
|
bitfld.byte 0x00 5. " CLO ,Extra SCL Clock Cycle Output" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " SOWP ,SCLO/SDAO Write Protect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SCLO ,SCL Output Control/Monitor" "Not released,Released"
|
|
bitfld.byte 0x00 2. " SDAO ,SDA Output Control/Monitor" "Not released,Released"
|
|
rbitfld.byte 0x00 1. " SCLI ,SCL Line Monitor" "Low,High"
|
|
rbitfld.byte 0x00 0. " SDAI ,SDA Line Monitor" "Low,High"
|
|
if (((per.b(ad:0x40053200+0x02))&0x80)==0x0)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "ICCR2,I2C Bus Control Register 2"
|
|
rbitfld.byte 0x00 7. " BBSY ,Bus Busy Detection Flag" "Released,Occupied"
|
|
rbitfld.byte 0x00 6. " MST ,Master/Slave Mode" "Slave,Master"
|
|
rbitfld.byte 0x00 5. " TRS ,Transmit/Receive Mode" "Receive,Transmit"
|
|
bitfld.byte 0x00 3. " SP ,Stop Condition Issuance Request" "No request,Request"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RS ,Restart Condition Issuance Request" "No request,Request"
|
|
bitfld.byte 0x00 1. " ST ,Start Condition Issuance Request" "No request,Request"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "ICCR2,I2C Bus Control Register 2"
|
|
rbitfld.byte 0x00 7. " BBSY ,Bus Busy Detection Flag" "Released,Occupied"
|
|
bitfld.byte 0x00 6. " MST ,Master/Slave Mode" "Slave,Master"
|
|
bitfld.byte 0x00 5. " TRS ,Transmit/Receive Mode" "Receive,Transmit"
|
|
bitfld.byte 0x00 3. " SP ,Stop Condition Issuance Request" "No request,Request"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RS ,Restart Condition Issuance Request" "No request,Request"
|
|
bitfld.byte 0x00 1. " ST ,Start Condition Issuance Request" "No request,Request"
|
|
endif
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ICMR1,I2C Bus Mode Register 1"
|
|
bitfld.byte 0x00 7. " MTWP ,MST/TRS Write Protect" "Enabled,Disabled"
|
|
bitfld.byte 0x00 4.--6. " CKS ,Internal Reference Clock Select" "PCLKB,PCLKB/2,PCLKB/4,PCLKB/8,PCLKB/16,PCLKB/32,PCLKB/64,PCLKB/128"
|
|
bitfld.byte 0x00 3. " BCWP ,BC Write Protect" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " BC ,Bit Counter" "9,2,3,4,5,6,7,8"
|
|
if (((per.b(ad:0x40053200+0x03))&0x80)==0x0)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "ICMR2,I2C Bus Mode Register 2"
|
|
bitfld.byte 0x00 7. " DLCS ,SDA Output Delay Clock Source Select" "IIC clock,IIC clock/2"
|
|
bitfld.byte 0x00 4.--6. " SDDL ,SDA Output Delay Counter" "No output,1 IIC cycle,2 IIC cycles,3 IIC cycles,4 IIC cycles,5 IIC cycles,6 IIC cycles,7 IIC cycles"
|
|
bitfld.byte 0x00 2. " TMOH ,Timeout H Count Control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " TMOL ,Timeout L Count Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TMOS ,Timeout Detection Time Select" "Long,Short"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "ICMR2,I2C Bus Mode Register 2"
|
|
bitfld.byte 0x00 7. " DLCS ,SDA Output Delay Clock Source Select" ",/2"
|
|
bitfld.byte 0x00 4.--6. " SDDL ,SDA Output Delay Counter" "No output,1/2 IIC cycles,3/4 IIC cycles,5/6 IIC cycles,7/8 IIC cycles,9/10 IIC cycles,11/12 IIC cycles,13/14 IIC cycles"
|
|
bitfld.byte 0x00 2. " TMOH ,Timeout H Count Control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " TMOL ,Timeout L Count Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TMOS ,Timeout Detection Time Select" "Long,Short"
|
|
endif
|
|
if (((per.b(ad:0x40053200+0x01))&0x20)==0x0)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ICMR3,I2C Bus Mode Register 3"
|
|
bitfld.byte 0x00 7. " SMBS ,SMBus/I2C Bus Select" "I2C bus,SMBus"
|
|
bitfld.byte 0x00 6. " WAIT ,WAIT" "No wait,Wait"
|
|
bitfld.byte 0x00 5. " RDRFS ,RDRF Flag Set Timing Select" "9th cycle,8th cycle"
|
|
bitfld.byte 0x00 4. " ACKWP ,ACKBT Write Protect" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ACKBT ,Transmit Acknowledge" "NACK,ACK"
|
|
rbitfld.byte 0x00 2. " ACKBR ,Receive Acknowledge" "NACK,ACK"
|
|
bitfld.byte 0x00 0.--1. " NF ,Noise Filter Stage Select" "1-stage,2-stage,3-stage,4-stage"
|
|
else
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ICMR3,I2C Bus Mode Register 3"
|
|
bitfld.byte 0x00 7. " SMBS ,SMBus/I2C Bus Select" "I2C bus,SMBus"
|
|
bitfld.byte 0x00 4. " ACKWP ,ACKBT Write Protect" "Enabled,Disabled"
|
|
bitfld.byte 0x00 3. " ACKBT ,Transmit Acknowledge" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " ACKBR ,Receive Acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " NF ,Noise Filter Stage Select" "1-stage,2-stage,3-stage,4-stage"
|
|
endif
|
|
group.byte 0x05++0x04
|
|
line.byte 0x00 "ICFER,I2C Bus Function Enable Register"
|
|
bitfld.byte 0x00 6. " SCLE ,SCL Synchronous Circuit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " NFE ,Digital Noise Filter Circuit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " NACKE ,NACK Reception Transfer Suspension Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SALE ,Slave Arbitration-Lost Detection Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " NALE ,NACK Transmission Arbitration-Lost Detection Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " MALE ,Master Arbitration-Lost Detection Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TMOE ,Timeout Function Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "ICSER,I2C Bus Status Enable Register"
|
|
bitfld.byte 0x01 7. " HOAE ,Host Address Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " DIDE ,Device-ID Address Detection Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 3. " GCAE ,General Call Address Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " SAR2E ,Slave Address Register 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " SAR1E ,Slave Address Register 1 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " SAR0E ,Slave Address Register 0 Enable" "Disabled,Enabled"
|
|
line.byte 0x02 "ICIER,I2C Bus Interrupt Enable Register"
|
|
bitfld.byte 0x02 7. " TIE ,Transmit Data Empty Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 6. " TEIE ,Transmit End Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " RIE ,Receive Data Full Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 4. " NAKIE ,NACK Reception Interrupt Request Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x02 3. " SPIE ,Stop Condition Detection Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 2. " STIE ,Start Condition Detection Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 1. " ALIE ,Arbitration-Lost Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " TMOIE ,Timeout Interrupt Request Enable" "Disabled,Enabled"
|
|
line.byte 0x03 "ICSR1,I2C Bus Status Register 1"
|
|
bitfld.byte 0x03 7. " HOA ,Host Address Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x03 5. " DID ,Device-ID Address Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x03 3. " GCA ,General Call Address Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x03 2. " AAS2 ,Slave Address 2 Detection Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " AAS1 ,Slave Address 1 Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x03 0. " AAS0 ,Slave Address 0 Detection Flag" "Not detected,Detected"
|
|
line.byte 0x04 "ICSR2,I2C Bus Status Register 2"
|
|
rbitfld.byte 0x04 7. " TDRE ,Transmit Data Empty Flag" "Not completed,Completed"
|
|
bitfld.byte 0x04 6. " TEND ,Transmit End Flag" "Not completed,Completed"
|
|
bitfld.byte 0x04 5. " RDRF ,Receive Data Full Flag" "Not received,Received"
|
|
bitfld.byte 0x04 4. " NACKF ,NACK Detection Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x04 3. " STOP ,Stop Condition Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x04 2. " START ,Start Condition Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x04 1. " AL ,Arbitration-Lost Flag" "Not lost,Lost"
|
|
bitfld.byte 0x04 0. " TMOF ,Timeout Detection Flag" "Not detected,Detected"
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "SARL0,Slave Address Register L0"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " SVA0 ,10-Bit Address LSB" "0,1"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "SARL1,Slave Address Register L1"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " SVA0 ,10-Bit Address LSB" "0,1"
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "SARL2,Slave Address Register L2"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " SVA0 ,10-Bit Address LSB" "0,1"
|
|
group.byte 0xB++0x00
|
|
line.byte 0x00 "SARU0,Slave Address Register U0"
|
|
bitfld.byte 0x00 1.--2. " SVA ,10-Bit Address Upper Bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0. " FS ,7-Bit/10-Bit Address Format Select" "7-bit,10-bit"
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "SARU1,Slave Address Register U1"
|
|
bitfld.byte 0x00 1.--2. " SVA ,10-Bit Address Upper Bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0. " FS ,7-Bit/10-Bit Address Format Select" "7-bit,10-bit"
|
|
group.byte 0xF++0x00
|
|
line.byte 0x00 "SARU2,Slave Address Register U2"
|
|
bitfld.byte 0x00 1.--2. " SVA ,10-Bit Address Upper Bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0. " FS ,7-Bit/10-Bit Address Format Select" "7-bit,10-bit"
|
|
group.byte 0x10++0x02
|
|
line.byte 0x00 "ICBRL,I2C Bus Bit Rate Low-Level Register"
|
|
bitfld.byte 0x00 0.--4. " BRL ,Bit Rate Low-Level Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "ICBRH,I2C Bus Bit Rate High-Level Register"
|
|
bitfld.byte 0x01 0.--4. " BRH ,Bit Rate High-Level Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x02 "ICDRT,I2C Bus Transmit Data Register"
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "ICDRR,I2C Bus Receive Data Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "CAN (Controller Area Network)"
|
|
base ad:0x40050000
|
|
width 14.
|
|
if (((per.w(ad:0x40050000+0x840))&0x300)==0x100)||(((per.w(ad:0x40050000+0x840))&0x300)==0x300)
|
|
group.word 0x840++0x01
|
|
line.word 0x00 "CTLR,Control Register"
|
|
eventfld.word 0x00 13. " RBOC ,Forced Return from Bus-Off" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11.--12. " BOM ,Bus-Off Recovery Mode" "Normal,Halt on bus-off entering,Halt on bus-off end,Halt during recovery"
|
|
bitfld.word 0x00 10. " SLPM ,CAN Sleep Mode" "Exit,Enter"
|
|
bitfld.word 0x00 8.--9. " CANM ,CAN Mode of Operation Select" "Operation,Reset,Halt,Forced reset"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " TSPS ,Time Stamp Prescaler Select" "1-bit,2-bit,4-bit,8-bit"
|
|
bitfld.word 0x00 5. " TSRC ,Time Stamp Counter Reset Command" "No reset,Reset"
|
|
bitfld.word 0x00 4. " TPM ,Transmission Priority Mode Select" "ID,Mailbox"
|
|
bitfld.word 0x00 3. " MLM ,Message Lost Mode Select" "Overwrite,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " IDFM ,ID Format Mode Select" "Standard,Extended,Mixed,"
|
|
bitfld.word 0x00 0. " MBM ,CAN Mailbox Mode Select" "Normal,FIFO"
|
|
else
|
|
group.word 0x440++0x01
|
|
line.word 0x00 "CTLR,Control Register"
|
|
eventfld.word 0x00 13. " RBOC ,Forced Return from Bus-Off" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 11.--12. " BOM ,Bus-Off Recovery Mode" "Normal,Halt on bus-off entering,Halt on bus-off end,Halt during recovery"
|
|
bitfld.word 0x00 10. " SLPM ,CAN Sleep Mode" "Exit,Enter"
|
|
bitfld.word 0x00 8.--9. " CANM ,CAN Mode of Operation Select" "Operation,Reset,Halt,Reset"
|
|
textline " "
|
|
rbitfld.word 0x00 6.--7. " TSPS ,Time Stamp Prescaler Select" "1-bit,2-bit,4-bit,8-bit"
|
|
bitfld.word 0x00 5. " TSRC ,Time Stamp Counter Reset Command" "No reset,Forced reset"
|
|
rbitfld.word 0x00 4. " TPM ,Transmission Priority Mode Select" "ID,Mailbox"
|
|
rbitfld.word 0x00 3. " MLM ,Message Lost Mode Select" "Overwrite,Overrun"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--2. " IDFM ,ID Format Mode Select" "Standard,Extended,Mixed,"
|
|
endif
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "BCR,Bit Configuration Register"
|
|
bitfld.long 0x00 28.--31. " TSEG1 ,Time Segment 1 Control" ",,,4 Tq,5 Tq,6 Tq,7 Tq,8 Tq,9 Tq,10 Tq,11 Tq,12 Tq,13 Tq,14 Tq,15 Tq,16 Tq"
|
|
hexmask.long.word 0x00 16.--25. 1. " BRP ,Baud Rate Prescaler select"
|
|
bitfld.long 0x00 12.--13. " SJW ,Synchronization Jump Width Control" "1 Tq,2 Tq,3 Tq,4 Tq"
|
|
bitfld.long 0x00 8.--10. " TSEG2 ,Time Segment 2 Control" ",2 Tq,3 Tq,4 Tq,5 Tq,6 Tq,7 Tq,8 Tq"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCLKS ,CAN Clock Source Selection" "PCLKB,CANMCLK"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "MKR0,Mask Register 0"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "MKR1,Mask Register 1"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "MKR2,Mask Register 2"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "MKR3,Mask Register 3"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MKR4,Mask Register 4"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MKR5,Mask Register 5"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MKR6,Mask Register 6"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MKR7,Mask Register 7"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FIDCR0,FIFO Received ID Compare Registers 0"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FIDCR1,FIFO Received ID Compare Registers 1"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "MKIVLR,Mask Invalid Register"
|
|
bitfld.long 0x00 31. " MB31 ,Mailbox 31 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 30. " MB30 ,Mailbox 30 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 29. " MB29 ,Mailbox 29 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 28. " MB28 ,Mailbox 28 Mask Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 27. " MB27 ,Mailbox 27 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 26. " MB26 ,Mailbox 26 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 25. " MB25 ,Mailbox 25 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 24. " MB24 ,Mailbox 24 Mask Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MB23 ,Mailbox 23 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 22. " MB22 ,Mailbox 22 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 21. " MB21 ,Mailbox 21 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 20. " MB20 ,Mailbox 20 Mask Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MB19 ,Mailbox 19 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " MB18 ,Mailbox 18 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 17. " MB17 ,Mailbox 17 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 16. " MB16 ,Mailbox 16 Mask Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MB15 ,Mailbox 15 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 14. " MB14 ,Mailbox 14 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 13. " MB13 ,Mailbox 13 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 12. " MB12 ,Mailbox 12 Mask Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MB11 ,Mailbox 11 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 10. " MB10 ,Mailbox 10 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 9. " MB9 ,Mailbox 9 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 8. " MB8 ,Mailbox 8 Mask Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MB7 ,Mailbox 7 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 6. " MB6 ,Mailbox 6 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 5. " MB5 ,Mailbox 5 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 4. " MB4 ,Mailbox 4 Mask Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MB3 ,Mailbox 3 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 2. " MB2 ,Mailbox 2 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 1. " MB1 ,Mailbox 1 Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x00 0. " MB0 ,Mailbox 0 Mask Invalid" "Valid,Invalid"
|
|
tree "Mailbox Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "MB0_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x200+0x04)++0x01
|
|
line.word 0x00 "MB0_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x200+0x06)++0x07
|
|
line.byte 0x00 "MB0_D0,DATA0"
|
|
line.byte 0x01 "MB0_D1,DATA1"
|
|
line.byte 0x02 "MB0_D2,DATA2"
|
|
line.byte 0x03 "MB0_D3,DATA3"
|
|
line.byte 0x04 "MB0_D4,DATA4"
|
|
line.byte 0x05 "MB0_D5,DATA5"
|
|
line.byte 0x06 "MB0_D6,DATA6"
|
|
line.byte 0x07 "MB0_D7,DATA7"
|
|
group.word (0x200+0x0E)++0x01
|
|
line.word 0x00 "MB0_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "MB1_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x20C+0x04)++0x01
|
|
line.word 0x00 "MB1_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x20C+0x06)++0x07
|
|
line.byte 0x00 "MB1_D0,DATA0"
|
|
line.byte 0x01 "MB1_D1,DATA1"
|
|
line.byte 0x02 "MB1_D2,DATA2"
|
|
line.byte 0x03 "MB1_D3,DATA3"
|
|
line.byte 0x04 "MB1_D4,DATA4"
|
|
line.byte 0x05 "MB1_D5,DATA5"
|
|
line.byte 0x06 "MB1_D6,DATA6"
|
|
line.byte 0x07 "MB1_D7,DATA7"
|
|
group.word (0x20C+0x0E)++0x01
|
|
line.word 0x00 "MB1_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "MB2_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x218+0x04)++0x01
|
|
line.word 0x00 "MB2_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x218+0x06)++0x07
|
|
line.byte 0x00 "MB2_D0,DATA0"
|
|
line.byte 0x01 "MB2_D1,DATA1"
|
|
line.byte 0x02 "MB2_D2,DATA2"
|
|
line.byte 0x03 "MB2_D3,DATA3"
|
|
line.byte 0x04 "MB2_D4,DATA4"
|
|
line.byte 0x05 "MB2_D5,DATA5"
|
|
line.byte 0x06 "MB2_D6,DATA6"
|
|
line.byte 0x07 "MB2_D7,DATA7"
|
|
group.word (0x218+0x0E)++0x01
|
|
line.word 0x00 "MB2_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "MB3_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x224+0x04)++0x01
|
|
line.word 0x00 "MB3_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x224+0x06)++0x07
|
|
line.byte 0x00 "MB3_D0,DATA0"
|
|
line.byte 0x01 "MB3_D1,DATA1"
|
|
line.byte 0x02 "MB3_D2,DATA2"
|
|
line.byte 0x03 "MB3_D3,DATA3"
|
|
line.byte 0x04 "MB3_D4,DATA4"
|
|
line.byte 0x05 "MB3_D5,DATA5"
|
|
line.byte 0x06 "MB3_D6,DATA6"
|
|
line.byte 0x07 "MB3_D7,DATA7"
|
|
group.word (0x224+0x0E)++0x01
|
|
line.word 0x00 "MB3_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "MB4_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x230+0x04)++0x01
|
|
line.word 0x00 "MB4_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x230+0x06)++0x07
|
|
line.byte 0x00 "MB4_D0,DATA0"
|
|
line.byte 0x01 "MB4_D1,DATA1"
|
|
line.byte 0x02 "MB4_D2,DATA2"
|
|
line.byte 0x03 "MB4_D3,DATA3"
|
|
line.byte 0x04 "MB4_D4,DATA4"
|
|
line.byte 0x05 "MB4_D5,DATA5"
|
|
line.byte 0x06 "MB4_D6,DATA6"
|
|
line.byte 0x07 "MB4_D7,DATA7"
|
|
group.word (0x230+0x0E)++0x01
|
|
line.word 0x00 "MB4_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "MB5_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x23C+0x04)++0x01
|
|
line.word 0x00 "MB5_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x23C+0x06)++0x07
|
|
line.byte 0x00 "MB5_D0,DATA0"
|
|
line.byte 0x01 "MB5_D1,DATA1"
|
|
line.byte 0x02 "MB5_D2,DATA2"
|
|
line.byte 0x03 "MB5_D3,DATA3"
|
|
line.byte 0x04 "MB5_D4,DATA4"
|
|
line.byte 0x05 "MB5_D5,DATA5"
|
|
line.byte 0x06 "MB5_D6,DATA6"
|
|
line.byte 0x07 "MB5_D7,DATA7"
|
|
group.word (0x23C+0x0E)++0x01
|
|
line.word 0x00 "MB5_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "MB6_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x248+0x04)++0x01
|
|
line.word 0x00 "MB6_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x248+0x06)++0x07
|
|
line.byte 0x00 "MB6_D0,DATA0"
|
|
line.byte 0x01 "MB6_D1,DATA1"
|
|
line.byte 0x02 "MB6_D2,DATA2"
|
|
line.byte 0x03 "MB6_D3,DATA3"
|
|
line.byte 0x04 "MB6_D4,DATA4"
|
|
line.byte 0x05 "MB6_D5,DATA5"
|
|
line.byte 0x06 "MB6_D6,DATA6"
|
|
line.byte 0x07 "MB6_D7,DATA7"
|
|
group.word (0x248+0x0E)++0x01
|
|
line.word 0x00 "MB6_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "MB7_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x254+0x04)++0x01
|
|
line.word 0x00 "MB7_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x254+0x06)++0x07
|
|
line.byte 0x00 "MB7_D0,DATA0"
|
|
line.byte 0x01 "MB7_D1,DATA1"
|
|
line.byte 0x02 "MB7_D2,DATA2"
|
|
line.byte 0x03 "MB7_D3,DATA3"
|
|
line.byte 0x04 "MB7_D4,DATA4"
|
|
line.byte 0x05 "MB7_D5,DATA5"
|
|
line.byte 0x06 "MB7_D6,DATA6"
|
|
line.byte 0x07 "MB7_D7,DATA7"
|
|
group.word (0x254+0x0E)++0x01
|
|
line.word 0x00 "MB7_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "MB8_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x260+0x04)++0x01
|
|
line.word 0x00 "MB8_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x260+0x06)++0x07
|
|
line.byte 0x00 "MB8_D0,DATA0"
|
|
line.byte 0x01 "MB8_D1,DATA1"
|
|
line.byte 0x02 "MB8_D2,DATA2"
|
|
line.byte 0x03 "MB8_D3,DATA3"
|
|
line.byte 0x04 "MB8_D4,DATA4"
|
|
line.byte 0x05 "MB8_D5,DATA5"
|
|
line.byte 0x06 "MB8_D6,DATA6"
|
|
line.byte 0x07 "MB8_D7,DATA7"
|
|
group.word (0x260+0x0E)++0x01
|
|
line.word 0x00 "MB8_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "MB9_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x26C+0x04)++0x01
|
|
line.word 0x00 "MB9_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x26C+0x06)++0x07
|
|
line.byte 0x00 "MB9_D0,DATA0"
|
|
line.byte 0x01 "MB9_D1,DATA1"
|
|
line.byte 0x02 "MB9_D2,DATA2"
|
|
line.byte 0x03 "MB9_D3,DATA3"
|
|
line.byte 0x04 "MB9_D4,DATA4"
|
|
line.byte 0x05 "MB9_D5,DATA5"
|
|
line.byte 0x06 "MB9_D6,DATA6"
|
|
line.byte 0x07 "MB9_D7,DATA7"
|
|
group.word (0x26C+0x0E)++0x01
|
|
line.word 0x00 "MB9_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "MB10_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x278+0x04)++0x01
|
|
line.word 0x00 "MB10_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x278+0x06)++0x07
|
|
line.byte 0x00 "MB10_D0,DATA0"
|
|
line.byte 0x01 "MB10_D1,DATA1"
|
|
line.byte 0x02 "MB10_D2,DATA2"
|
|
line.byte 0x03 "MB10_D3,DATA3"
|
|
line.byte 0x04 "MB10_D4,DATA4"
|
|
line.byte 0x05 "MB10_D5,DATA5"
|
|
line.byte 0x06 "MB10_D6,DATA6"
|
|
line.byte 0x07 "MB10_D7,DATA7"
|
|
group.word (0x278+0x0E)++0x01
|
|
line.word 0x00 "MB10_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "MB11_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x284+0x04)++0x01
|
|
line.word 0x00 "MB11_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x284+0x06)++0x07
|
|
line.byte 0x00 "MB11_D0,DATA0"
|
|
line.byte 0x01 "MB11_D1,DATA1"
|
|
line.byte 0x02 "MB11_D2,DATA2"
|
|
line.byte 0x03 "MB11_D3,DATA3"
|
|
line.byte 0x04 "MB11_D4,DATA4"
|
|
line.byte 0x05 "MB11_D5,DATA5"
|
|
line.byte 0x06 "MB11_D6,DATA6"
|
|
line.byte 0x07 "MB11_D7,DATA7"
|
|
group.word (0x284+0x0E)++0x01
|
|
line.word 0x00 "MB11_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "MB12_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x290+0x04)++0x01
|
|
line.word 0x00 "MB12_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x290+0x06)++0x07
|
|
line.byte 0x00 "MB12_D0,DATA0"
|
|
line.byte 0x01 "MB12_D1,DATA1"
|
|
line.byte 0x02 "MB12_D2,DATA2"
|
|
line.byte 0x03 "MB12_D3,DATA3"
|
|
line.byte 0x04 "MB12_D4,DATA4"
|
|
line.byte 0x05 "MB12_D5,DATA5"
|
|
line.byte 0x06 "MB12_D6,DATA6"
|
|
line.byte 0x07 "MB12_D7,DATA7"
|
|
group.word (0x290+0x0E)++0x01
|
|
line.word 0x00 "MB12_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "MB13_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x29C+0x04)++0x01
|
|
line.word 0x00 "MB13_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x29C+0x06)++0x07
|
|
line.byte 0x00 "MB13_D0,DATA0"
|
|
line.byte 0x01 "MB13_D1,DATA1"
|
|
line.byte 0x02 "MB13_D2,DATA2"
|
|
line.byte 0x03 "MB13_D3,DATA3"
|
|
line.byte 0x04 "MB13_D4,DATA4"
|
|
line.byte 0x05 "MB13_D5,DATA5"
|
|
line.byte 0x06 "MB13_D6,DATA6"
|
|
line.byte 0x07 "MB13_D7,DATA7"
|
|
group.word (0x29C+0x0E)++0x01
|
|
line.word 0x00 "MB13_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "MB14_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x2A8+0x04)++0x01
|
|
line.word 0x00 "MB14_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2A8+0x06)++0x07
|
|
line.byte 0x00 "MB14_D0,DATA0"
|
|
line.byte 0x01 "MB14_D1,DATA1"
|
|
line.byte 0x02 "MB14_D2,DATA2"
|
|
line.byte 0x03 "MB14_D3,DATA3"
|
|
line.byte 0x04 "MB14_D4,DATA4"
|
|
line.byte 0x05 "MB14_D5,DATA5"
|
|
line.byte 0x06 "MB14_D6,DATA6"
|
|
line.byte 0x07 "MB14_D7,DATA7"
|
|
group.word (0x2A8+0x0E)++0x01
|
|
line.word 0x00 "MB14_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "MB15_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x2B4+0x04)++0x01
|
|
line.word 0x00 "MB15_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2B4+0x06)++0x07
|
|
line.byte 0x00 "MB15_D0,DATA0"
|
|
line.byte 0x01 "MB15_D1,DATA1"
|
|
line.byte 0x02 "MB15_D2,DATA2"
|
|
line.byte 0x03 "MB15_D3,DATA3"
|
|
line.byte 0x04 "MB15_D4,DATA4"
|
|
line.byte 0x05 "MB15_D5,DATA5"
|
|
line.byte 0x06 "MB15_D6,DATA6"
|
|
line.byte 0x07 "MB15_D7,DATA7"
|
|
group.word (0x2B4+0x0E)++0x01
|
|
line.word 0x00 "MB15_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "MB16_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x2C0+0x04)++0x01
|
|
line.word 0x00 "MB16_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2C0+0x06)++0x07
|
|
line.byte 0x00 "MB16_D0,DATA0"
|
|
line.byte 0x01 "MB16_D1,DATA1"
|
|
line.byte 0x02 "MB16_D2,DATA2"
|
|
line.byte 0x03 "MB16_D3,DATA3"
|
|
line.byte 0x04 "MB16_D4,DATA4"
|
|
line.byte 0x05 "MB16_D5,DATA5"
|
|
line.byte 0x06 "MB16_D6,DATA6"
|
|
line.byte 0x07 "MB16_D7,DATA7"
|
|
group.word (0x2C0+0x0E)++0x01
|
|
line.word 0x00 "MB16_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "MB17_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x2CC+0x04)++0x01
|
|
line.word 0x00 "MB17_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2CC+0x06)++0x07
|
|
line.byte 0x00 "MB17_D0,DATA0"
|
|
line.byte 0x01 "MB17_D1,DATA1"
|
|
line.byte 0x02 "MB17_D2,DATA2"
|
|
line.byte 0x03 "MB17_D3,DATA3"
|
|
line.byte 0x04 "MB17_D4,DATA4"
|
|
line.byte 0x05 "MB17_D5,DATA5"
|
|
line.byte 0x06 "MB17_D6,DATA6"
|
|
line.byte 0x07 "MB17_D7,DATA7"
|
|
group.word (0x2CC+0x0E)++0x01
|
|
line.word 0x00 "MB17_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "MB18_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x2D8+0x04)++0x01
|
|
line.word 0x00 "MB18_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2D8+0x06)++0x07
|
|
line.byte 0x00 "MB18_D0,DATA0"
|
|
line.byte 0x01 "MB18_D1,DATA1"
|
|
line.byte 0x02 "MB18_D2,DATA2"
|
|
line.byte 0x03 "MB18_D3,DATA3"
|
|
line.byte 0x04 "MB18_D4,DATA4"
|
|
line.byte 0x05 "MB18_D5,DATA5"
|
|
line.byte 0x06 "MB18_D6,DATA6"
|
|
line.byte 0x07 "MB18_D7,DATA7"
|
|
group.word (0x2D8+0x0E)++0x01
|
|
line.word 0x00 "MB18_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "MB19_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x2E4+0x04)++0x01
|
|
line.word 0x00 "MB19_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2E4+0x06)++0x07
|
|
line.byte 0x00 "MB19_D0,DATA0"
|
|
line.byte 0x01 "MB19_D1,DATA1"
|
|
line.byte 0x02 "MB19_D2,DATA2"
|
|
line.byte 0x03 "MB19_D3,DATA3"
|
|
line.byte 0x04 "MB19_D4,DATA4"
|
|
line.byte 0x05 "MB19_D5,DATA5"
|
|
line.byte 0x06 "MB19_D6,DATA6"
|
|
line.byte 0x07 "MB19_D7,DATA7"
|
|
group.word (0x2E4+0x0E)++0x01
|
|
line.word 0x00 "MB19_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "MB20_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x2F0+0x04)++0x01
|
|
line.word 0x00 "MB20_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2F0+0x06)++0x07
|
|
line.byte 0x00 "MB20_D0,DATA0"
|
|
line.byte 0x01 "MB20_D1,DATA1"
|
|
line.byte 0x02 "MB20_D2,DATA2"
|
|
line.byte 0x03 "MB20_D3,DATA3"
|
|
line.byte 0x04 "MB20_D4,DATA4"
|
|
line.byte 0x05 "MB20_D5,DATA5"
|
|
line.byte 0x06 "MB20_D6,DATA6"
|
|
line.byte 0x07 "MB20_D7,DATA7"
|
|
group.word (0x2F0+0x0E)++0x01
|
|
line.word 0x00 "MB20_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "MB21_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x2FC+0x04)++0x01
|
|
line.word 0x00 "MB21_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2FC+0x06)++0x07
|
|
line.byte 0x00 "MB21_D0,DATA0"
|
|
line.byte 0x01 "MB21_D1,DATA1"
|
|
line.byte 0x02 "MB21_D2,DATA2"
|
|
line.byte 0x03 "MB21_D3,DATA3"
|
|
line.byte 0x04 "MB21_D4,DATA4"
|
|
line.byte 0x05 "MB21_D5,DATA5"
|
|
line.byte 0x06 "MB21_D6,DATA6"
|
|
line.byte 0x07 "MB21_D7,DATA7"
|
|
group.word (0x2FC+0x0E)++0x01
|
|
line.word 0x00 "MB21_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "MB22_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x308+0x04)++0x01
|
|
line.word 0x00 "MB22_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x308+0x06)++0x07
|
|
line.byte 0x00 "MB22_D0,DATA0"
|
|
line.byte 0x01 "MB22_D1,DATA1"
|
|
line.byte 0x02 "MB22_D2,DATA2"
|
|
line.byte 0x03 "MB22_D3,DATA3"
|
|
line.byte 0x04 "MB22_D4,DATA4"
|
|
line.byte 0x05 "MB22_D5,DATA5"
|
|
line.byte 0x06 "MB22_D6,DATA6"
|
|
line.byte 0x07 "MB22_D7,DATA7"
|
|
group.word (0x308+0x0E)++0x01
|
|
line.word 0x00 "MB22_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "MB23_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x314+0x04)++0x01
|
|
line.word 0x00 "MB23_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x314+0x06)++0x07
|
|
line.byte 0x00 "MB23_D0,DATA0"
|
|
line.byte 0x01 "MB23_D1,DATA1"
|
|
line.byte 0x02 "MB23_D2,DATA2"
|
|
line.byte 0x03 "MB23_D3,DATA3"
|
|
line.byte 0x04 "MB23_D4,DATA4"
|
|
line.byte 0x05 "MB23_D5,DATA5"
|
|
line.byte 0x06 "MB23_D6,DATA6"
|
|
line.byte 0x07 "MB23_D7,DATA7"
|
|
group.word (0x314+0x0E)++0x01
|
|
line.word 0x00 "MB23_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "MB24_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x320+0x04)++0x01
|
|
line.word 0x00 "MB24_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x320+0x06)++0x07
|
|
line.byte 0x00 "MB24_D0,DATA0"
|
|
line.byte 0x01 "MB24_D1,DATA1"
|
|
line.byte 0x02 "MB24_D2,DATA2"
|
|
line.byte 0x03 "MB24_D3,DATA3"
|
|
line.byte 0x04 "MB24_D4,DATA4"
|
|
line.byte 0x05 "MB24_D5,DATA5"
|
|
line.byte 0x06 "MB24_D6,DATA6"
|
|
line.byte 0x07 "MB24_D7,DATA7"
|
|
group.word (0x320+0x0E)++0x01
|
|
line.word 0x00 "MB24_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "MB25_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x32C+0x04)++0x01
|
|
line.word 0x00 "MB25_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x32C+0x06)++0x07
|
|
line.byte 0x00 "MB25_D0,DATA0"
|
|
line.byte 0x01 "MB25_D1,DATA1"
|
|
line.byte 0x02 "MB25_D2,DATA2"
|
|
line.byte 0x03 "MB25_D3,DATA3"
|
|
line.byte 0x04 "MB25_D4,DATA4"
|
|
line.byte 0x05 "MB25_D5,DATA5"
|
|
line.byte 0x06 "MB25_D6,DATA6"
|
|
line.byte 0x07 "MB25_D7,DATA7"
|
|
group.word (0x32C+0x0E)++0x01
|
|
line.word 0x00 "MB25_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "MB26_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x338+0x04)++0x01
|
|
line.word 0x00 "MB26_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x338+0x06)++0x07
|
|
line.byte 0x00 "MB26_D0,DATA0"
|
|
line.byte 0x01 "MB26_D1,DATA1"
|
|
line.byte 0x02 "MB26_D2,DATA2"
|
|
line.byte 0x03 "MB26_D3,DATA3"
|
|
line.byte 0x04 "MB26_D4,DATA4"
|
|
line.byte 0x05 "MB26_D5,DATA5"
|
|
line.byte 0x06 "MB26_D6,DATA6"
|
|
line.byte 0x07 "MB26_D7,DATA7"
|
|
group.word (0x338+0x0E)++0x01
|
|
line.word 0x00 "MB26_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "MB27_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x344+0x04)++0x01
|
|
line.word 0x00 "MB27_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x344+0x06)++0x07
|
|
line.byte 0x00 "MB27_D0,DATA0"
|
|
line.byte 0x01 "MB27_D1,DATA1"
|
|
line.byte 0x02 "MB27_D2,DATA2"
|
|
line.byte 0x03 "MB27_D3,DATA3"
|
|
line.byte 0x04 "MB27_D4,DATA4"
|
|
line.byte 0x05 "MB27_D5,DATA5"
|
|
line.byte 0x06 "MB27_D6,DATA6"
|
|
line.byte 0x07 "MB27_D7,DATA7"
|
|
group.word (0x344+0x0E)++0x01
|
|
line.word 0x00 "MB27_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "MB28_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x350+0x04)++0x01
|
|
line.word 0x00 "MB28_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x350+0x06)++0x07
|
|
line.byte 0x00 "MB28_D0,DATA0"
|
|
line.byte 0x01 "MB28_D1,DATA1"
|
|
line.byte 0x02 "MB28_D2,DATA2"
|
|
line.byte 0x03 "MB28_D3,DATA3"
|
|
line.byte 0x04 "MB28_D4,DATA4"
|
|
line.byte 0x05 "MB28_D5,DATA5"
|
|
line.byte 0x06 "MB28_D6,DATA6"
|
|
line.byte 0x07 "MB28_D7,DATA7"
|
|
group.word (0x350+0x0E)++0x01
|
|
line.word 0x00 "MB28_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x35C++0x03
|
|
line.long 0x00 "MB29_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x35C+0x04)++0x01
|
|
line.word 0x00 "MB29_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x35C+0x06)++0x07
|
|
line.byte 0x00 "MB29_D0,DATA0"
|
|
line.byte 0x01 "MB29_D1,DATA1"
|
|
line.byte 0x02 "MB29_D2,DATA2"
|
|
line.byte 0x03 "MB29_D3,DATA3"
|
|
line.byte 0x04 "MB29_D4,DATA4"
|
|
line.byte 0x05 "MB29_D5,DATA5"
|
|
line.byte 0x06 "MB29_D6,DATA6"
|
|
line.byte 0x07 "MB29_D7,DATA7"
|
|
group.word (0x35C+0x0E)++0x01
|
|
line.word 0x00 "MB29_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x368++0x03
|
|
line.long 0x00 "MB30_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x368+0x04)++0x01
|
|
line.word 0x00 "MB30_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x368+0x06)++0x07
|
|
line.byte 0x00 "MB30_D0,DATA0"
|
|
line.byte 0x01 "MB30_D1,DATA1"
|
|
line.byte 0x02 "MB30_D2,DATA2"
|
|
line.byte 0x03 "MB30_D3,DATA3"
|
|
line.byte 0x04 "MB30_D4,DATA4"
|
|
line.byte 0x05 "MB30_D5,DATA5"
|
|
line.byte 0x06 "MB30_D6,DATA6"
|
|
line.byte 0x07 "MB30_D7,DATA7"
|
|
group.word (0x368+0x0E)++0x01
|
|
line.word 0x00 "MB30_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x374++0x03
|
|
line.long 0x00 "MB31_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x374+0x04)++0x01
|
|
line.word 0x00 "MB31_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x374+0x06)++0x07
|
|
line.byte 0x00 "MB31_D0,DATA0"
|
|
line.byte 0x01 "MB31_D1,DATA1"
|
|
line.byte 0x02 "MB31_D2,DATA2"
|
|
line.byte 0x03 "MB31_D3,DATA3"
|
|
line.byte 0x04 "MB31_D4,DATA4"
|
|
line.byte 0x05 "MB31_D5,DATA5"
|
|
line.byte 0x06 "MB31_D6,DATA6"
|
|
line.byte 0x07 "MB31_D7,DATA7"
|
|
group.word (0x374+0x0E)++0x01
|
|
line.word 0x00 "MB31_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
tree.end
|
|
textline " "
|
|
if (((per.w(ad:0x40050000+0x840))&0x1)==0x0)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MIER,Mailbox Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " MB31 ,Mailbox 31 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MB30 ,Mailbox 30 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " MB29 ,Mailbox 29 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " MB28 ,Mailbox 28 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " MB27 ,Mailbox 27 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " MB26 ,Mailbox 26 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " MB25 ,Mailbox 25 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MB24 ,Mailbox 24 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MB23 ,Mailbox 23 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MB22 ,Mailbox 22 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " MB21 ,Mailbox 21 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MB20 ,Mailbox 20 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MB19 ,Mailbox 19 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " MB18 ,Mailbox 18 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " MB17 ,Mailbox 17 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " MB16 ,Mailbox 16 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MB15 ,Mailbox 15 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MB14 ,Mailbox 14 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MB13 ,Mailbox 13 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " MB12 ,Mailbox 12 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MB11 ,Mailbox 11 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MB10 ,Mailbox 10 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MB9 ,Mailbox 9 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MB8 ,Mailbox 8 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MB7 ,Mailbox 7 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MB6 ,Mailbox 6 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MB5 ,Mailbox 5 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MB4 ,Mailbox 4 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MB3 ,Mailbox 3 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MB2 ,Mailbox 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MB1 ,Mailbox 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MB0 ,Mailbox 0 Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MIER_FIFO,Mailbox Interrupt Enable Register for FIFO Mailbox Mode"
|
|
bitfld.long 0x00 29. " MB29 ,Mailbox 29 Interrupt Enable" "RX completed,FIFO buffer warning"
|
|
bitfld.long 0x00 28. " MB28 ,Mailbox 28 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " MB25 ,Mailbox 25 Interrupt Enable" "TX completed,FIFO emptied"
|
|
bitfld.long 0x00 24. " MB24 ,Mailbox 24 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MB23 ,Mailbox 23 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MB22 ,Mailbox 22 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " MB21 ,Mailbox 21 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MB20 ,Mailbox 20 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MB19 ,Mailbox 19 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " MB18 ,Mailbox 18 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " MB17 ,Mailbox 17 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " MB16 ,Mailbox 16 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MB15 ,Mailbox 15 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MB14 ,Mailbox 14 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MB13 ,Mailbox 13 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " MB12 ,Mailbox 12 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MB11 ,Mailbox 11 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MB10 ,Mailbox 10 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MB9 ,Mailbox 9 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MB8 ,Mailbox 8 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MB7 ,Mailbox 7 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MB6 ,Mailbox 6 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MB5 ,Mailbox 5 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MB4 ,Mailbox 4 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MB3 ,Mailbox 3 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MB2 ,Mailbox 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MB1 ,Mailbox 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MB0 ,Mailbox 0 Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x820))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x820))&0x40)==0x0)
|
|
group.byte 0x820++0x00
|
|
line.byte 0x00 "MCTL_TX0,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x820))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x820))&0x40)==0x40)
|
|
group.byte 0x820++0x00
|
|
line.byte 0x00 "MCTL_RX0,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x820++0x00
|
|
line.byte 0x00 "MCTL_TX_RX0,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x821))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x821))&0x40)==0x0)
|
|
group.byte 0x821++0x00
|
|
line.byte 0x00 "MCTL_TX1,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x821))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x821))&0x40)==0x40)
|
|
group.byte 0x821++0x00
|
|
line.byte 0x00 "MCTL_RX1,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x821++0x00
|
|
line.byte 0x00 "MCTL_TX_RX1,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x822))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x822))&0x40)==0x0)
|
|
group.byte 0x822++0x00
|
|
line.byte 0x00 "MCTL_TX2,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x822))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x822))&0x40)==0x40)
|
|
group.byte 0x822++0x00
|
|
line.byte 0x00 "MCTL_RX2,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x822++0x00
|
|
line.byte 0x00 "MCTL_TX_RX2,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x823))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x823))&0x40)==0x0)
|
|
group.byte 0x823++0x00
|
|
line.byte 0x00 "MCTL_TX3,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x823))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x823))&0x40)==0x40)
|
|
group.byte 0x823++0x00
|
|
line.byte 0x00 "MCTL_RX3,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x823++0x00
|
|
line.byte 0x00 "MCTL_TX_RX3,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x824))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x824))&0x40)==0x0)
|
|
group.byte 0x824++0x00
|
|
line.byte 0x00 "MCTL_TX4,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x824))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x824))&0x40)==0x40)
|
|
group.byte 0x824++0x00
|
|
line.byte 0x00 "MCTL_RX4,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x824++0x00
|
|
line.byte 0x00 "MCTL_TX_RX4,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x825))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x825))&0x40)==0x0)
|
|
group.byte 0x825++0x00
|
|
line.byte 0x00 "MCTL_TX5,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x825))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x825))&0x40)==0x40)
|
|
group.byte 0x825++0x00
|
|
line.byte 0x00 "MCTL_RX5,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x825++0x00
|
|
line.byte 0x00 "MCTL_TX_RX5,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x826))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x826))&0x40)==0x0)
|
|
group.byte 0x826++0x00
|
|
line.byte 0x00 "MCTL_TX6,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x826))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x826))&0x40)==0x40)
|
|
group.byte 0x826++0x00
|
|
line.byte 0x00 "MCTL_RX6,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x826++0x00
|
|
line.byte 0x00 "MCTL_TX_RX6,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x827))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x827))&0x40)==0x0)
|
|
group.byte 0x827++0x00
|
|
line.byte 0x00 "MCTL_TX7,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x827))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x827))&0x40)==0x40)
|
|
group.byte 0x827++0x00
|
|
line.byte 0x00 "MCTL_RX7,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x827++0x00
|
|
line.byte 0x00 "MCTL_TX_RX7,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x828))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x828))&0x40)==0x0)
|
|
group.byte 0x828++0x00
|
|
line.byte 0x00 "MCTL_TX8,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x828))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x828))&0x40)==0x40)
|
|
group.byte 0x828++0x00
|
|
line.byte 0x00 "MCTL_RX8,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x828++0x00
|
|
line.byte 0x00 "MCTL_TX_RX8,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x829))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x829))&0x40)==0x0)
|
|
group.byte 0x829++0x00
|
|
line.byte 0x00 "MCTL_TX9,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x829))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x829))&0x40)==0x40)
|
|
group.byte 0x829++0x00
|
|
line.byte 0x00 "MCTL_RX9,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x829++0x00
|
|
line.byte 0x00 "MCTL_TX_RX9,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x82A))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x82A))&0x40)==0x0)
|
|
group.byte 0x82A++0x00
|
|
line.byte 0x00 "MCTL_TX10,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x82A))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x82A))&0x40)==0x40)
|
|
group.byte 0x82A++0x00
|
|
line.byte 0x00 "MCTL_RX10,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x82A++0x00
|
|
line.byte 0x00 "MCTL_TX_RX10,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x82B))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x82B))&0x40)==0x0)
|
|
group.byte 0x82B++0x00
|
|
line.byte 0x00 "MCTL_TX11,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x82B))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x82B))&0x40)==0x40)
|
|
group.byte 0x82B++0x00
|
|
line.byte 0x00 "MCTL_RX11,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x82B++0x00
|
|
line.byte 0x00 "MCTL_TX_RX11,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x82C))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x82C))&0x40)==0x0)
|
|
group.byte 0x82C++0x00
|
|
line.byte 0x00 "MCTL_TX12,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x82C))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x82C))&0x40)==0x40)
|
|
group.byte 0x82C++0x00
|
|
line.byte 0x00 "MCTL_RX12,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x82C++0x00
|
|
line.byte 0x00 "MCTL_TX_RX12,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x82D))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x82D))&0x40)==0x0)
|
|
group.byte 0x82D++0x00
|
|
line.byte 0x00 "MCTL_TX13,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x82D))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x82D))&0x40)==0x40)
|
|
group.byte 0x82D++0x00
|
|
line.byte 0x00 "MCTL_RX13,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x82D++0x00
|
|
line.byte 0x00 "MCTL_TX_RX13,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x82E))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x82E))&0x40)==0x0)
|
|
group.byte 0x82E++0x00
|
|
line.byte 0x00 "MCTL_TX14,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x82E))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x82E))&0x40)==0x40)
|
|
group.byte 0x82E++0x00
|
|
line.byte 0x00 "MCTL_RX14,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x82E++0x00
|
|
line.byte 0x00 "MCTL_TX_RX14,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x82F))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x82F))&0x40)==0x0)
|
|
group.byte 0x82F++0x00
|
|
line.byte 0x00 "MCTL_TX15,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x82F))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x82F))&0x40)==0x40)
|
|
group.byte 0x82F++0x00
|
|
line.byte 0x00 "MCTL_RX15,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x82F++0x00
|
|
line.byte 0x00 "MCTL_TX_RX15,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x830))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x830))&0x40)==0x0)
|
|
group.byte 0x830++0x00
|
|
line.byte 0x00 "MCTL_TX16,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x830))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x830))&0x40)==0x40)
|
|
group.byte 0x830++0x00
|
|
line.byte 0x00 "MCTL_RX16,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x830++0x00
|
|
line.byte 0x00 "MCTL_TX_RX16,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x831))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x831))&0x40)==0x0)
|
|
group.byte 0x831++0x00
|
|
line.byte 0x00 "MCTL_TX17,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x831))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x831))&0x40)==0x40)
|
|
group.byte 0x831++0x00
|
|
line.byte 0x00 "MCTL_RX17,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x831++0x00
|
|
line.byte 0x00 "MCTL_TX_RX17,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x832))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x832))&0x40)==0x0)
|
|
group.byte 0x832++0x00
|
|
line.byte 0x00 "MCTL_TX18,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x832))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x832))&0x40)==0x40)
|
|
group.byte 0x832++0x00
|
|
line.byte 0x00 "MCTL_RX18,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x832++0x00
|
|
line.byte 0x00 "MCTL_TX_RX18,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x833))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x833))&0x40)==0x0)
|
|
group.byte 0x833++0x00
|
|
line.byte 0x00 "MCTL_TX19,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x833))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x833))&0x40)==0x40)
|
|
group.byte 0x833++0x00
|
|
line.byte 0x00 "MCTL_RX19,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x833++0x00
|
|
line.byte 0x00 "MCTL_TX_RX19,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x834))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x834))&0x40)==0x0)
|
|
group.byte 0x834++0x00
|
|
line.byte 0x00 "MCTL_TX20,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x834))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x834))&0x40)==0x40)
|
|
group.byte 0x834++0x00
|
|
line.byte 0x00 "MCTL_RX20,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x834++0x00
|
|
line.byte 0x00 "MCTL_TX_RX20,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x835))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x835))&0x40)==0x0)
|
|
group.byte 0x835++0x00
|
|
line.byte 0x00 "MCTL_TX21,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x835))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x835))&0x40)==0x40)
|
|
group.byte 0x835++0x00
|
|
line.byte 0x00 "MCTL_RX21,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x835++0x00
|
|
line.byte 0x00 "MCTL_TX_RX21,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x836))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x836))&0x40)==0x0)
|
|
group.byte 0x836++0x00
|
|
line.byte 0x00 "MCTL_TX22,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x836))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x836))&0x40)==0x40)
|
|
group.byte 0x836++0x00
|
|
line.byte 0x00 "MCTL_RX22,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x836++0x00
|
|
line.byte 0x00 "MCTL_TX_RX22,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x837))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x837))&0x40)==0x0)
|
|
group.byte 0x837++0x00
|
|
line.byte 0x00 "MCTL_TX23,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x837))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x837))&0x40)==0x40)
|
|
group.byte 0x837++0x00
|
|
line.byte 0x00 "MCTL_RX23,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x837++0x00
|
|
line.byte 0x00 "MCTL_TX_RX23,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x838))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x838))&0x40)==0x0)
|
|
group.byte 0x838++0x00
|
|
line.byte 0x00 "MCTL_TX24,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x838))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x838))&0x40)==0x40)
|
|
group.byte 0x838++0x00
|
|
line.byte 0x00 "MCTL_RX24,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x838++0x00
|
|
line.byte 0x00 "MCTL_TX_RX24,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x839))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x839))&0x40)==0x0)
|
|
group.byte 0x839++0x00
|
|
line.byte 0x00 "MCTL_TX25,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x839))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x839))&0x40)==0x40)
|
|
group.byte 0x839++0x00
|
|
line.byte 0x00 "MCTL_RX25,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x839++0x00
|
|
line.byte 0x00 "MCTL_TX_RX25,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x83A))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x83A))&0x40)==0x0)
|
|
group.byte 0x83A++0x00
|
|
line.byte 0x00 "MCTL_TX26,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x83A))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x83A))&0x40)==0x40)
|
|
group.byte 0x83A++0x00
|
|
line.byte 0x00 "MCTL_RX26,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x83A++0x00
|
|
line.byte 0x00 "MCTL_TX_RX26,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x83B))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x83B))&0x40)==0x0)
|
|
group.byte 0x83B++0x00
|
|
line.byte 0x00 "MCTL_TX27,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x83B))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x83B))&0x40)==0x40)
|
|
group.byte 0x83B++0x00
|
|
line.byte 0x00 "MCTL_RX27,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x83B++0x00
|
|
line.byte 0x00 "MCTL_TX_RX27,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x83C))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x83C))&0x40)==0x0)
|
|
group.byte 0x83C++0x00
|
|
line.byte 0x00 "MCTL_TX28,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x83C))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x83C))&0x40)==0x40)
|
|
group.byte 0x83C++0x00
|
|
line.byte 0x00 "MCTL_RX28,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x83C++0x00
|
|
line.byte 0x00 "MCTL_TX_RX28,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x83D))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x83D))&0x40)==0x0)
|
|
group.byte 0x83D++0x00
|
|
line.byte 0x00 "MCTL_TX29,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x83D))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x83D))&0x40)==0x40)
|
|
group.byte 0x83D++0x00
|
|
line.byte 0x00 "MCTL_RX29,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x83D++0x00
|
|
line.byte 0x00 "MCTL_TX_RX29,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x83E))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x83E))&0x40)==0x0)
|
|
group.byte 0x83E++0x00
|
|
line.byte 0x00 "MCTL_TX30,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x83E))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x83E))&0x40)==0x40)
|
|
group.byte 0x83E++0x00
|
|
line.byte 0x00 "MCTL_RX30,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x83E++0x00
|
|
line.byte 0x00 "MCTL_TX_RX30,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.b(ad:0x40050000+0x83F))&0x80)==0x80)&&(((per.b(ad:0x40050000+0x83F))&0x40)==0x0)
|
|
group.byte 0x83F++0x00
|
|
line.byte 0x00 "MCTL_TX31,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0x40050000+0x83F))&0x80)==0x0)&&(((per.b(ad:0x40050000+0x83F))&0x40)==0x40)
|
|
group.byte 0x83F++0x00
|
|
line.byte 0x00 "MCTL_RX31,Message Control Register for Receive"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Not valid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte 0x83F++0x00
|
|
line.byte 0x00 "MCTL_TX_RX31,Message Control Register"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
group.byte 0x848++0x00
|
|
line.byte 0x00 "RFCR,Receive FIFO Control Register"
|
|
rbitfld.byte 0x00 7. " RFEST ,Receive FIFO Empty Status Flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 6. " RFWST ,Receive FIFO Buffer Warning Status Flag" "No buffer warning,Buffer warning"
|
|
rbitfld.byte 0x00 5. " RFFST ,Receive FIFO Full Status Flag" "Not full,Full"
|
|
bitfld.byte 0x00 4. " RFMLF ,Receive FIFO Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
rbitfld.byte 0x00 1.--3. " RFUST ,Receive FIFO Unread Message Number Status" "0,1,2,3,4,,,"
|
|
bitfld.byte 0x00 0. " RFE ,Receive FIFO Enable" "Disabled,Enabled"
|
|
wgroup.byte 0x849++0x00
|
|
line.byte 0x00 "RFPCR,Receive FIFO Pointer Control Register"
|
|
group.byte 0x84A++0x00
|
|
line.byte 0x00 "TFCR,Transmit FIFO Control Register"
|
|
rbitfld.byte 0x00 7. " TFEST ,Transmit FIFO Empty Status" "Not empty,Empty"
|
|
rbitfld.byte 0x00 6. " TFFST ,Transmit FIFO Full Status" "Not full,Full"
|
|
rbitfld.byte 0x00 1.--3. " TFUST ,Transmit FIFO Unsent Message Number Status" "No Unsent message,1,2,3,4,,,"
|
|
bitfld.byte 0x00 0. " TFE ,Transmit FIFO Enable" "Disabled,Enabled"
|
|
wgroup.byte 0x84B++0x00
|
|
line.byte 0x00 "TFPCR,Transmit FIFO Pointer Control Register"
|
|
rgroup.word 0x842++0x01
|
|
line.word 0x00 "STR,Status Register"
|
|
bitfld.word 0x00 14. " RECST ,Receive Status Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 13. " TRMST ,Transmit Status Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 12. " BOST ,Bus-Off Status Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " EPST ,Error-Passive Status Flagg" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 11. " SLPST ,CAN Sleep Status Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " HLTST ,CAN Halt Status Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 8. " RSTST ,CAN Reset Status Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " EST ,Error Status Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TABST ,Transmission Abort Status Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " FMLST ,FIFO Mailbox Message Lost Status Flag" "Not lost,Lost"
|
|
bitfld.word 0x00 4. " NMLST ,Normal Mailbox Message Lost Status Flag" "Not lost,Lost"
|
|
bitfld.word 0x00 3. " TFST ,Transmit FIFO Status Flag" "Full,Not full"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RFST ,Receive FIFO Status Flag" "Empty,Not empty"
|
|
bitfld.word 0x00 1. " SDST ,SENTDATA Status Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 0. " NDST ,NEWDATA Status Flag" "Not occurred,Occurred"
|
|
group.byte 0x853++0x00
|
|
line.byte 0x00 "MSMR,Mailbox Search Mode Register"
|
|
bitfld.byte 0x00 0.--1. " MBSM ,Mailbox Search Mode Select" "Received,Transmited,Lost,Search"
|
|
rgroup.byte 0x852++0x00
|
|
line.byte 0x00 "MSSR,Mailbox Search Status Register"
|
|
bitfld.byte 0x00 7. " SEST ,Search Result Status" "Found,Not found"
|
|
bitfld.byte 0x00 0.--4. " MBNST ,Search Result Mailbox Number Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x851++0x00
|
|
line.byte 0x00 "CSSR,Channel Search Support Register"
|
|
group.word 0x856++0x01
|
|
line.word 0x00 "AFSR,Acceptance Filter Support Register"
|
|
group.byte 0x84C++0x01
|
|
line.byte 0x00 "EIER,Error Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " BLIE ,Bus Lock Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " OLIE ,Overload Frame Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ORIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " BORIE ,Bus-Off Recovery Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " BOEIE ,Bus-Off Entry Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EPIE ,Error-Passive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " EWIE ,Error-Warning Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " BEIE ,Bus Error Interrupt Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "EIFR,Error Interrupt Factor Judge Register"
|
|
bitfld.byte 0x01 7. " BLIF ,Bus Lock Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 6. " OLIF ,Overload Frame Transmission Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 5. " ORIF ,Receive Overrun Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 4. " BORIF ,Bus-Off Recovery Detect Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " BOEIF ,Bus-Off Entry Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 2. " EPIF ,Error-Passive Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 1. " EWIF ,Error-Warning Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 0. " BEIF ,Bus Error Detect Flag" "Not detected,Detected"
|
|
rgroup.byte 0x84E++0x01
|
|
line.byte 0x00 "RECR,Receive Error Count Register"
|
|
line.byte 0x01 "TECR,Transmit Error Count Register"
|
|
group.byte 0x850++0x00
|
|
line.byte 0x00 "ECSR,Error Code Store Register"
|
|
bitfld.byte 0x00 7. " EDPM ,Error Display Mode Select" "Not error,Error"
|
|
bitfld.byte 0x00 6. " ADEF ,ACK Delimiter Error Flag" "Not error,Error"
|
|
bitfld.byte 0x00 5. " BE0F ,Bit Error (dominant) Flag" "Not error,Error"
|
|
bitfld.byte 0x00 4. " BE1F ,Bit Error (recessive) Flag" "Not error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CEF ,CRC Error Flag" "Not error,Error"
|
|
bitfld.byte 0x00 2. " AEF ,ACK Error Flag" "Not error,Error"
|
|
bitfld.byte 0x00 1. " FEF ,Form Error Flag" "Not error,Error"
|
|
bitfld.byte 0x00 0. " SEF ,Stuff Error Flag" "Not error,Error"
|
|
rgroup.word 0x854++0x01
|
|
line.word 0x00 "TSR,Time Stamp Register"
|
|
group.byte 0x858++0x00
|
|
line.byte 0x00 "TCR,Test Control Register"
|
|
bitfld.byte 0x00 1.--2. " TSTM ,CAN Test Mode Select" "No test mode,Listen-only,Self-test 0,Self-test 1"
|
|
bitfld.byte 0x00 0. " TSTE ,CAN Test Mode Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
tree "Channel 0"
|
|
base ad:0x40072000
|
|
width 9.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "SPCR,SPI Control Register"
|
|
bitfld.byte 0x00 7. " SPRIE ,SPI Receive Buffer Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,Transmit Buffer Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " SPEIE ,SPI Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MSTR ,SPI Master/Slave Mode Select" "Slave,Master"
|
|
bitfld.byte 0x00 2. " MODFEN ,Mode Fault Error Detection Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " TXMD ,Communications Operating Mode Select" "Full-duplex,Serial"
|
|
bitfld.byte 0x00 0. " SPMS ,SPI Mode Select" "4-wire,3-wire"
|
|
line.byte 0x01 "SSLP,SPI Slave Select Polarity Register"
|
|
bitfld.byte 0x01 3. " SSL3P ,SSL3 Signal Polarity Setting" "Active low,Active high"
|
|
bitfld.byte 0x01 2. " SSL2P ,SSL2 Signal Polarity Setting" "Active low,Active high"
|
|
bitfld.byte 0x01 1. " SSL1P ,SSL1 Signal Polarity Setting" "Active low,Active high"
|
|
bitfld.byte 0x01 0. " SSL0P ,SSL0 Signal Polarity Setting" "Active low,Active high"
|
|
line.byte 0x02 "SPPCR,SPI Pin Control Register"
|
|
bitfld.byte 0x02 5. " MOIFE ,MOSI Idle Value Fixing Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 4. " MOIFV ,MOSI Idle Fixed Value" "Low,High"
|
|
bitfld.byte 0x02 1. " SPLP2 ,SPI Loopback 2" "Normal,Loopback"
|
|
bitfld.byte 0x02 0. " SPLP ,SPI Loopback" "Normal,Loopback"
|
|
line.byte 0x03 "SPSR,SPI Status Register"
|
|
bitfld.byte 0x03 7. " SPRF ,SPI Receive Buffer Full Flag" "Not full,Full"
|
|
bitfld.byte 0x03 5. " SPTEF ,SPI Transmit Buffer Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x03 4. " UDRF ,Underrun Error Flag" "Fault,Underrun"
|
|
bitfld.byte 0x03 3. " PERF ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x03 2. " MODF ,Mode Fault Error Flag" "No error,error"
|
|
rbitfld.byte 0x03 1. " IDLNF ,SPI Idle Flag" "Idle,Transfer"
|
|
bitfld.byte 0x03 0. " OVRF ,Overrun Error Flag" "No error,Error"
|
|
if (((per.b(ad:0x40072000+0x0B))&0x20)==0x20)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPDR,SPI Data Register"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPDR_HA,SPI Data Register"
|
|
endif
|
|
group.byte 0x08++0x07
|
|
line.byte 0x00 "SPSCR,SPI Sequence Control Register"
|
|
bitfld.byte 0x00 0.--2. " SPSLN ,SPI Sequence Length Specification" "1,2,3,4,5,6,7,8"
|
|
line.byte 0x01 "SPSSR,SPI Sequence Status Register"
|
|
bitfld.byte 0x01 4.--6. " SPECM ,SPI Error Command" "SPCMD0,SPCMD1,SPCMD2,SPCMD3,SPCMD4,SPCMD5,SPCMD6,SPCMD7"
|
|
bitfld.byte 0x01 0.--2. " SPCP ,SPI Command Pointer" "SPCMD0,SPCMD1,SPCMD2,SPCMD3,SPCMD4,SPCMD5,SPCMD6,SPCMD7"
|
|
line.byte 0x02 "SPBR,SPI Bit Rate Register"
|
|
line.byte 0x03 "SPDCR,SPI Data Control Register"
|
|
bitfld.byte 0x03 5. " SPLW ,SPI Word Access/Halfword Access Specification" "SPDR_HA,SPDR"
|
|
bitfld.byte 0x03 4. " SPRDTD ,SPI Receive/Transmit Data Select" "Received,Transmited"
|
|
bitfld.byte 0x03 0.--1. " SPFC ,Number of Frames Specification" "1 frame,2 frames,3 frames,4 frames"
|
|
line.byte 0x04 "SPCKD,SPI Clock Delay Register"
|
|
bitfld.byte 0x04 0.--2. " SCKDL ,RSPCK Delay Setting" "1 RSPCK,2 RSPCK,3 RSPCK,4 RSPCK,5 RSPCK,6 RSPCK,7 RSPCK,8 RSPCK"
|
|
line.byte 0x05 "SSLND,SPI Slave Select Negation Delay Register"
|
|
bitfld.byte 0x05 0.--2. " SLNDL ,SSL Negation Delay Setting" "1 RSPCK,2 RSPCK,3 RSPCK,4 RSPCK,5 RSPCK,6 RSPCK,7 RSPCK,8 RSPCK"
|
|
line.byte 0x06 "SPND,SPI Next-Access Delay Register"
|
|
bitfld.byte 0x06 0.--2. " SPNDL ,SPI Next-Access Delay Setting" "1 RSPCK + 2,2 RSPCK + 2,3 RSPCK + 2,4 RSPCK + 2,5 RSPCK + 2,6 RSPCK + 2,7 RSPCK + 2,8 RSPCK + 2"
|
|
line.byte 0x07 "SPCR2,SPI Control Register 2"
|
|
bitfld.byte 0x07 4. " SCKASE ,RSPCK Auto-Stop Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x07 3. " PTE ,Parity Self-Testing" "Disabled,Enabled"
|
|
bitfld.byte 0x07 2. " SPIIE ,SPI Idle Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x07 1. " SPOE ,Parity Mode" "Even,Odd"
|
|
bitfld.byte 0x07 0. " SPPE ,Parity Enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SPCMD0,SPI Command Registers 0"
|
|
bitfld.word 0x00 15. " SCKDEN ,RSPCK Delay Setting Enable" "1 RSPCK,SPCKD"
|
|
bitfld.word 0x00 14. " SLNDEN ,SSL Negation Delay Setting Enable" "1 RSPCK,SSLND"
|
|
bitfld.word 0x00 13. " SPNDEN ,SPI Next-Access Delay Enable" "1 RSPCK + 2,SPND"
|
|
bitfld.word 0x00 12. " LSBF ,SPI LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " SPB ,SPI Data Length Setting" "20 bits,24 bits,32 bits,32 bits,8 bits,8 bits,8 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.word 0x00 7. " SSLKP ,SSL Signal Level Keeping" "Negative,Positive"
|
|
bitfld.word 0x00 4.--6. " SSLA ,SSL Signal Assertion Setting" "SSL0,SSL1,SSL2,SSL3,?..."
|
|
bitfld.word 0x00 2.--3. " BRDV ,Bit Rate Division Setting" "/1,/2,/4,/8"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,RSPCK Polarity Setting" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CPHA ,RSPCK Phase Setting" "Leading/Trailing,Trailing/Trailing"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "SPCMD1,SPI Command Registers 1"
|
|
bitfld.word 0x00 15. " SCKDEN ,RSPCK Delay Setting Enable" "1 RSPCK,SPCKD"
|
|
bitfld.word 0x00 14. " SLNDEN ,SSL Negation Delay Setting Enable" "1 RSPCK,SSLND"
|
|
bitfld.word 0x00 13. " SPNDEN ,SPI Next-Access Delay Enable" "1 RSPCK + 2,SPND"
|
|
bitfld.word 0x00 12. " LSBF ,SPI LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " SPB ,SPI Data Length Setting" "20 bits,24 bits,32 bits,32 bits,8 bits,8 bits,8 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.word 0x00 7. " SSLKP ,SSL Signal Level Keeping" "Negative,Positive"
|
|
bitfld.word 0x00 4.--6. " SSLA ,SSL Signal Assertion Setting" "SSL0,SSL1,SSL2,SSL3,?..."
|
|
bitfld.word 0x00 2.--3. " BRDV ,Bit Rate Division Setting" "/1,/2,/4,/8"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,RSPCK Polarity Setting" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CPHA ,RSPCK Phase Setting" "Leading/Trailing,Trailing/Trailing"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "SPCMD2,SPI Command Registers 2"
|
|
bitfld.word 0x00 15. " SCKDEN ,RSPCK Delay Setting Enable" "1 RSPCK,SPCKD"
|
|
bitfld.word 0x00 14. " SLNDEN ,SSL Negation Delay Setting Enable" "1 RSPCK,SSLND"
|
|
bitfld.word 0x00 13. " SPNDEN ,SPI Next-Access Delay Enable" "1 RSPCK + 2,SPND"
|
|
bitfld.word 0x00 12. " LSBF ,SPI LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " SPB ,SPI Data Length Setting" "20 bits,24 bits,32 bits,32 bits,8 bits,8 bits,8 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.word 0x00 7. " SSLKP ,SSL Signal Level Keeping" "Negative,Positive"
|
|
bitfld.word 0x00 4.--6. " SSLA ,SSL Signal Assertion Setting" "SSL0,SSL1,SSL2,SSL3,?..."
|
|
bitfld.word 0x00 2.--3. " BRDV ,Bit Rate Division Setting" "/1,/2,/4,/8"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,RSPCK Polarity Setting" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CPHA ,RSPCK Phase Setting" "Leading/Trailing,Trailing/Trailing"
|
|
group.word 0x16++0x01
|
|
line.word 0x00 "SPCMD3,SPI Command Registers 3"
|
|
bitfld.word 0x00 15. " SCKDEN ,RSPCK Delay Setting Enable" "1 RSPCK,SPCKD"
|
|
bitfld.word 0x00 14. " SLNDEN ,SSL Negation Delay Setting Enable" "1 RSPCK,SSLND"
|
|
bitfld.word 0x00 13. " SPNDEN ,SPI Next-Access Delay Enable" "1 RSPCK + 2,SPND"
|
|
bitfld.word 0x00 12. " LSBF ,SPI LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " SPB ,SPI Data Length Setting" "20 bits,24 bits,32 bits,32 bits,8 bits,8 bits,8 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.word 0x00 7. " SSLKP ,SSL Signal Level Keeping" "Negative,Positive"
|
|
bitfld.word 0x00 4.--6. " SSLA ,SSL Signal Assertion Setting" "SSL0,SSL1,SSL2,SSL3,?..."
|
|
bitfld.word 0x00 2.--3. " BRDV ,Bit Rate Division Setting" "/1,/2,/4,/8"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,RSPCK Polarity Setting" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CPHA ,RSPCK Phase Setting" "Leading/Trailing,Trailing/Trailing"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "SPCMD4,SPI Command Registers 4"
|
|
bitfld.word 0x00 15. " SCKDEN ,RSPCK Delay Setting Enable" "1 RSPCK,SPCKD"
|
|
bitfld.word 0x00 14. " SLNDEN ,SSL Negation Delay Setting Enable" "1 RSPCK,SSLND"
|
|
bitfld.word 0x00 13. " SPNDEN ,SPI Next-Access Delay Enable" "1 RSPCK + 2,SPND"
|
|
bitfld.word 0x00 12. " LSBF ,SPI LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " SPB ,SPI Data Length Setting" "20 bits,24 bits,32 bits,32 bits,8 bits,8 bits,8 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.word 0x00 7. " SSLKP ,SSL Signal Level Keeping" "Negative,Positive"
|
|
bitfld.word 0x00 4.--6. " SSLA ,SSL Signal Assertion Setting" "SSL0,SSL1,SSL2,SSL3,?..."
|
|
bitfld.word 0x00 2.--3. " BRDV ,Bit Rate Division Setting" "/1,/2,/4,/8"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,RSPCK Polarity Setting" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CPHA ,RSPCK Phase Setting" "Leading/Trailing,Trailing/Trailing"
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "SPCMD5,SPI Command Registers 5"
|
|
bitfld.word 0x00 15. " SCKDEN ,RSPCK Delay Setting Enable" "1 RSPCK,SPCKD"
|
|
bitfld.word 0x00 14. " SLNDEN ,SSL Negation Delay Setting Enable" "1 RSPCK,SSLND"
|
|
bitfld.word 0x00 13. " SPNDEN ,SPI Next-Access Delay Enable" "1 RSPCK + 2,SPND"
|
|
bitfld.word 0x00 12. " LSBF ,SPI LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " SPB ,SPI Data Length Setting" "20 bits,24 bits,32 bits,32 bits,8 bits,8 bits,8 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.word 0x00 7. " SSLKP ,SSL Signal Level Keeping" "Negative,Positive"
|
|
bitfld.word 0x00 4.--6. " SSLA ,SSL Signal Assertion Setting" "SSL0,SSL1,SSL2,SSL3,?..."
|
|
bitfld.word 0x00 2.--3. " BRDV ,Bit Rate Division Setting" "/1,/2,/4,/8"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,RSPCK Polarity Setting" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CPHA ,RSPCK Phase Setting" "Leading/Trailing,Trailing/Trailing"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPCMD6,SPI Command Registers 6"
|
|
bitfld.word 0x00 15. " SCKDEN ,RSPCK Delay Setting Enable" "1 RSPCK,SPCKD"
|
|
bitfld.word 0x00 14. " SLNDEN ,SSL Negation Delay Setting Enable" "1 RSPCK,SSLND"
|
|
bitfld.word 0x00 13. " SPNDEN ,SPI Next-Access Delay Enable" "1 RSPCK + 2,SPND"
|
|
bitfld.word 0x00 12. " LSBF ,SPI LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " SPB ,SPI Data Length Setting" "20 bits,24 bits,32 bits,32 bits,8 bits,8 bits,8 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.word 0x00 7. " SSLKP ,SSL Signal Level Keeping" "Negative,Positive"
|
|
bitfld.word 0x00 4.--6. " SSLA ,SSL Signal Assertion Setting" "SSL0,SSL1,SSL2,SSL3,?..."
|
|
bitfld.word 0x00 2.--3. " BRDV ,Bit Rate Division Setting" "/1,/2,/4,/8"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,RSPCK Polarity Setting" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CPHA ,RSPCK Phase Setting" "Leading/Trailing,Trailing/Trailing"
|
|
group.word 0x1E++0x01
|
|
line.word 0x00 "SPCMD7,SPI Command Registers 7"
|
|
bitfld.word 0x00 15. " SCKDEN ,RSPCK Delay Setting Enable" "1 RSPCK,SPCKD"
|
|
bitfld.word 0x00 14. " SLNDEN ,SSL Negation Delay Setting Enable" "1 RSPCK,SSLND"
|
|
bitfld.word 0x00 13. " SPNDEN ,SPI Next-Access Delay Enable" "1 RSPCK + 2,SPND"
|
|
bitfld.word 0x00 12. " LSBF ,SPI LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " SPB ,SPI Data Length Setting" "20 bits,24 bits,32 bits,32 bits,8 bits,8 bits,8 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.word 0x00 7. " SSLKP ,SSL Signal Level Keeping" "Negative,Positive"
|
|
bitfld.word 0x00 4.--6. " SSLA ,SSL Signal Assertion Setting" "SSL0,SSL1,SSL2,SSL3,?..."
|
|
bitfld.word 0x00 2.--3. " BRDV ,Bit Rate Division Setting" "/1,/2,/4,/8"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,RSPCK Polarity Setting" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CPHA ,RSPCK Phase Setting" "Leading/Trailing,Trailing/Trailing"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0x40072100
|
|
width 9.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "SPCR,SPI Control Register"
|
|
bitfld.byte 0x00 7. " SPRIE ,SPI Receive Buffer Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,Transmit Buffer Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " SPEIE ,SPI Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MSTR ,SPI Master/Slave Mode Select" "Slave,Master"
|
|
bitfld.byte 0x00 2. " MODFEN ,Mode Fault Error Detection Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " TXMD ,Communications Operating Mode Select" "Full-duplex,Serial"
|
|
bitfld.byte 0x00 0. " SPMS ,SPI Mode Select" "4-wire,3-wire"
|
|
line.byte 0x01 "SSLP,SPI Slave Select Polarity Register"
|
|
bitfld.byte 0x01 3. " SSL3P ,SSL3 Signal Polarity Setting" "Active low,Active high"
|
|
bitfld.byte 0x01 2. " SSL2P ,SSL2 Signal Polarity Setting" "Active low,Active high"
|
|
bitfld.byte 0x01 1. " SSL1P ,SSL1 Signal Polarity Setting" "Active low,Active high"
|
|
bitfld.byte 0x01 0. " SSL0P ,SSL0 Signal Polarity Setting" "Active low,Active high"
|
|
line.byte 0x02 "SPPCR,SPI Pin Control Register"
|
|
bitfld.byte 0x02 5. " MOIFE ,MOSI Idle Value Fixing Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 4. " MOIFV ,MOSI Idle Fixed Value" "Low,High"
|
|
bitfld.byte 0x02 1. " SPLP2 ,SPI Loopback 2" "Normal,Loopback"
|
|
bitfld.byte 0x02 0. " SPLP ,SPI Loopback" "Normal,Loopback"
|
|
line.byte 0x03 "SPSR,SPI Status Register"
|
|
bitfld.byte 0x03 7. " SPRF ,SPI Receive Buffer Full Flag" "Not full,Full"
|
|
bitfld.byte 0x03 5. " SPTEF ,SPI Transmit Buffer Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x03 4. " UDRF ,Underrun Error Flag" "Fault,Underrun"
|
|
bitfld.byte 0x03 3. " PERF ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x03 2. " MODF ,Mode Fault Error Flag" "No error,error"
|
|
rbitfld.byte 0x03 1. " IDLNF ,SPI Idle Flag" "Idle,Transfer"
|
|
bitfld.byte 0x03 0. " OVRF ,Overrun Error Flag" "No error,Error"
|
|
if (((per.b(ad:0x40072100+0x0B))&0x20)==0x20)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPDR,SPI Data Register"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPDR_HA,SPI Data Register"
|
|
endif
|
|
group.byte 0x08++0x07
|
|
line.byte 0x00 "SPSCR,SPI Sequence Control Register"
|
|
bitfld.byte 0x00 0.--2. " SPSLN ,SPI Sequence Length Specification" "1,2,3,4,5,6,7,8"
|
|
line.byte 0x01 "SPSSR,SPI Sequence Status Register"
|
|
bitfld.byte 0x01 4.--6. " SPECM ,SPI Error Command" "SPCMD0,SPCMD1,SPCMD2,SPCMD3,SPCMD4,SPCMD5,SPCMD6,SPCMD7"
|
|
bitfld.byte 0x01 0.--2. " SPCP ,SPI Command Pointer" "SPCMD0,SPCMD1,SPCMD2,SPCMD3,SPCMD4,SPCMD5,SPCMD6,SPCMD7"
|
|
line.byte 0x02 "SPBR,SPI Bit Rate Register"
|
|
line.byte 0x03 "SPDCR,SPI Data Control Register"
|
|
bitfld.byte 0x03 5. " SPLW ,SPI Word Access/Halfword Access Specification" "SPDR_HA,SPDR"
|
|
bitfld.byte 0x03 4. " SPRDTD ,SPI Receive/Transmit Data Select" "Received,Transmited"
|
|
bitfld.byte 0x03 0.--1. " SPFC ,Number of Frames Specification" "1 frame,2 frames,3 frames,4 frames"
|
|
line.byte 0x04 "SPCKD,SPI Clock Delay Register"
|
|
bitfld.byte 0x04 0.--2. " SCKDL ,RSPCK Delay Setting" "1 RSPCK,2 RSPCK,3 RSPCK,4 RSPCK,5 RSPCK,6 RSPCK,7 RSPCK,8 RSPCK"
|
|
line.byte 0x05 "SSLND,SPI Slave Select Negation Delay Register"
|
|
bitfld.byte 0x05 0.--2. " SLNDL ,SSL Negation Delay Setting" "1 RSPCK,2 RSPCK,3 RSPCK,4 RSPCK,5 RSPCK,6 RSPCK,7 RSPCK,8 RSPCK"
|
|
line.byte 0x06 "SPND,SPI Next-Access Delay Register"
|
|
bitfld.byte 0x06 0.--2. " SPNDL ,SPI Next-Access Delay Setting" "1 RSPCK + 2,2 RSPCK + 2,3 RSPCK + 2,4 RSPCK + 2,5 RSPCK + 2,6 RSPCK + 2,7 RSPCK + 2,8 RSPCK + 2"
|
|
line.byte 0x07 "SPCR2,SPI Control Register 2"
|
|
bitfld.byte 0x07 4. " SCKASE ,RSPCK Auto-Stop Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x07 3. " PTE ,Parity Self-Testing" "Disabled,Enabled"
|
|
bitfld.byte 0x07 2. " SPIIE ,SPI Idle Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x07 1. " SPOE ,Parity Mode" "Even,Odd"
|
|
bitfld.byte 0x07 0. " SPPE ,Parity Enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SPCMD0,SPI Command Registers 0"
|
|
bitfld.word 0x00 15. " SCKDEN ,RSPCK Delay Setting Enable" "1 RSPCK,SPCKD"
|
|
bitfld.word 0x00 14. " SLNDEN ,SSL Negation Delay Setting Enable" "1 RSPCK,SSLND"
|
|
bitfld.word 0x00 13. " SPNDEN ,SPI Next-Access Delay Enable" "1 RSPCK + 2,SPND"
|
|
bitfld.word 0x00 12. " LSBF ,SPI LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " SPB ,SPI Data Length Setting" "20 bits,24 bits,32 bits,32 bits,8 bits,8 bits,8 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.word 0x00 7. " SSLKP ,SSL Signal Level Keeping" "Negative,Positive"
|
|
bitfld.word 0x00 4.--6. " SSLA ,SSL Signal Assertion Setting" "SSL0,SSL1,SSL2,SSL3,?..."
|
|
bitfld.word 0x00 2.--3. " BRDV ,Bit Rate Division Setting" "/1,/2,/4,/8"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,RSPCK Polarity Setting" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CPHA ,RSPCK Phase Setting" "Leading/Trailing,Trailing/Trailing"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "SPCMD1,SPI Command Registers 1"
|
|
bitfld.word 0x00 15. " SCKDEN ,RSPCK Delay Setting Enable" "1 RSPCK,SPCKD"
|
|
bitfld.word 0x00 14. " SLNDEN ,SSL Negation Delay Setting Enable" "1 RSPCK,SSLND"
|
|
bitfld.word 0x00 13. " SPNDEN ,SPI Next-Access Delay Enable" "1 RSPCK + 2,SPND"
|
|
bitfld.word 0x00 12. " LSBF ,SPI LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " SPB ,SPI Data Length Setting" "20 bits,24 bits,32 bits,32 bits,8 bits,8 bits,8 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.word 0x00 7. " SSLKP ,SSL Signal Level Keeping" "Negative,Positive"
|
|
bitfld.word 0x00 4.--6. " SSLA ,SSL Signal Assertion Setting" "SSL0,SSL1,SSL2,SSL3,?..."
|
|
bitfld.word 0x00 2.--3. " BRDV ,Bit Rate Division Setting" "/1,/2,/4,/8"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,RSPCK Polarity Setting" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CPHA ,RSPCK Phase Setting" "Leading/Trailing,Trailing/Trailing"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "SPCMD2,SPI Command Registers 2"
|
|
bitfld.word 0x00 15. " SCKDEN ,RSPCK Delay Setting Enable" "1 RSPCK,SPCKD"
|
|
bitfld.word 0x00 14. " SLNDEN ,SSL Negation Delay Setting Enable" "1 RSPCK,SSLND"
|
|
bitfld.word 0x00 13. " SPNDEN ,SPI Next-Access Delay Enable" "1 RSPCK + 2,SPND"
|
|
bitfld.word 0x00 12. " LSBF ,SPI LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " SPB ,SPI Data Length Setting" "20 bits,24 bits,32 bits,32 bits,8 bits,8 bits,8 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.word 0x00 7. " SSLKP ,SSL Signal Level Keeping" "Negative,Positive"
|
|
bitfld.word 0x00 4.--6. " SSLA ,SSL Signal Assertion Setting" "SSL0,SSL1,SSL2,SSL3,?..."
|
|
bitfld.word 0x00 2.--3. " BRDV ,Bit Rate Division Setting" "/1,/2,/4,/8"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,RSPCK Polarity Setting" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CPHA ,RSPCK Phase Setting" "Leading/Trailing,Trailing/Trailing"
|
|
group.word 0x16++0x01
|
|
line.word 0x00 "SPCMD3,SPI Command Registers 3"
|
|
bitfld.word 0x00 15. " SCKDEN ,RSPCK Delay Setting Enable" "1 RSPCK,SPCKD"
|
|
bitfld.word 0x00 14. " SLNDEN ,SSL Negation Delay Setting Enable" "1 RSPCK,SSLND"
|
|
bitfld.word 0x00 13. " SPNDEN ,SPI Next-Access Delay Enable" "1 RSPCK + 2,SPND"
|
|
bitfld.word 0x00 12. " LSBF ,SPI LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " SPB ,SPI Data Length Setting" "20 bits,24 bits,32 bits,32 bits,8 bits,8 bits,8 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.word 0x00 7. " SSLKP ,SSL Signal Level Keeping" "Negative,Positive"
|
|
bitfld.word 0x00 4.--6. " SSLA ,SSL Signal Assertion Setting" "SSL0,SSL1,SSL2,SSL3,?..."
|
|
bitfld.word 0x00 2.--3. " BRDV ,Bit Rate Division Setting" "/1,/2,/4,/8"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,RSPCK Polarity Setting" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CPHA ,RSPCK Phase Setting" "Leading/Trailing,Trailing/Trailing"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "SPCMD4,SPI Command Registers 4"
|
|
bitfld.word 0x00 15. " SCKDEN ,RSPCK Delay Setting Enable" "1 RSPCK,SPCKD"
|
|
bitfld.word 0x00 14. " SLNDEN ,SSL Negation Delay Setting Enable" "1 RSPCK,SSLND"
|
|
bitfld.word 0x00 13. " SPNDEN ,SPI Next-Access Delay Enable" "1 RSPCK + 2,SPND"
|
|
bitfld.word 0x00 12. " LSBF ,SPI LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " SPB ,SPI Data Length Setting" "20 bits,24 bits,32 bits,32 bits,8 bits,8 bits,8 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.word 0x00 7. " SSLKP ,SSL Signal Level Keeping" "Negative,Positive"
|
|
bitfld.word 0x00 4.--6. " SSLA ,SSL Signal Assertion Setting" "SSL0,SSL1,SSL2,SSL3,?..."
|
|
bitfld.word 0x00 2.--3. " BRDV ,Bit Rate Division Setting" "/1,/2,/4,/8"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,RSPCK Polarity Setting" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CPHA ,RSPCK Phase Setting" "Leading/Trailing,Trailing/Trailing"
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "SPCMD5,SPI Command Registers 5"
|
|
bitfld.word 0x00 15. " SCKDEN ,RSPCK Delay Setting Enable" "1 RSPCK,SPCKD"
|
|
bitfld.word 0x00 14. " SLNDEN ,SSL Negation Delay Setting Enable" "1 RSPCK,SSLND"
|
|
bitfld.word 0x00 13. " SPNDEN ,SPI Next-Access Delay Enable" "1 RSPCK + 2,SPND"
|
|
bitfld.word 0x00 12. " LSBF ,SPI LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " SPB ,SPI Data Length Setting" "20 bits,24 bits,32 bits,32 bits,8 bits,8 bits,8 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.word 0x00 7. " SSLKP ,SSL Signal Level Keeping" "Negative,Positive"
|
|
bitfld.word 0x00 4.--6. " SSLA ,SSL Signal Assertion Setting" "SSL0,SSL1,SSL2,SSL3,?..."
|
|
bitfld.word 0x00 2.--3. " BRDV ,Bit Rate Division Setting" "/1,/2,/4,/8"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,RSPCK Polarity Setting" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CPHA ,RSPCK Phase Setting" "Leading/Trailing,Trailing/Trailing"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPCMD6,SPI Command Registers 6"
|
|
bitfld.word 0x00 15. " SCKDEN ,RSPCK Delay Setting Enable" "1 RSPCK,SPCKD"
|
|
bitfld.word 0x00 14. " SLNDEN ,SSL Negation Delay Setting Enable" "1 RSPCK,SSLND"
|
|
bitfld.word 0x00 13. " SPNDEN ,SPI Next-Access Delay Enable" "1 RSPCK + 2,SPND"
|
|
bitfld.word 0x00 12. " LSBF ,SPI LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " SPB ,SPI Data Length Setting" "20 bits,24 bits,32 bits,32 bits,8 bits,8 bits,8 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.word 0x00 7. " SSLKP ,SSL Signal Level Keeping" "Negative,Positive"
|
|
bitfld.word 0x00 4.--6. " SSLA ,SSL Signal Assertion Setting" "SSL0,SSL1,SSL2,SSL3,?..."
|
|
bitfld.word 0x00 2.--3. " BRDV ,Bit Rate Division Setting" "/1,/2,/4,/8"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,RSPCK Polarity Setting" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CPHA ,RSPCK Phase Setting" "Leading/Trailing,Trailing/Trailing"
|
|
group.word 0x1E++0x01
|
|
line.word 0x00 "SPCMD7,SPI Command Registers 7"
|
|
bitfld.word 0x00 15. " SCKDEN ,RSPCK Delay Setting Enable" "1 RSPCK,SPCKD"
|
|
bitfld.word 0x00 14. " SLNDEN ,SSL Negation Delay Setting Enable" "1 RSPCK,SSLND"
|
|
bitfld.word 0x00 13. " SPNDEN ,SPI Next-Access Delay Enable" "1 RSPCK + 2,SPND"
|
|
bitfld.word 0x00 12. " LSBF ,SPI LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " SPB ,SPI Data Length Setting" "20 bits,24 bits,32 bits,32 bits,8 bits,8 bits,8 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.word 0x00 7. " SSLKP ,SSL Signal Level Keeping" "Negative,Positive"
|
|
bitfld.word 0x00 4.--6. " SSLA ,SSL Signal Assertion Setting" "SSL0,SSL1,SSL2,SSL3,?..."
|
|
bitfld.word 0x00 2.--3. " BRDV ,Bit Rate Division Setting" "/1,/2,/4,/8"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,RSPCK Polarity Setting" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CPHA ,RSPCK Phase Setting" "Leading/Trailing,Trailing/Trailing"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
tree "QSPI (Quad Serial Peripheral Interface)"
|
|
base ad:0x64000000
|
|
width 9.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "SFMSMD,Transfer Mode Control Register"
|
|
bitfld.long 0x00 15. " SFMCCE ,Read instruction code select" "Default,SFMSIC"
|
|
bitfld.long 0x00 11. " SFMOSW ,Setup time adjustment for serial transmission" "Normal,Extended"
|
|
bitfld.long 0x00 10. " SFMOHW ,Hold time adjustment for serial transmission" "Normal,Extended"
|
|
bitfld.long 0x00 9. " SFMOEX ,Extension select for the I/O buffer output enable signal for the serial interface" "Normal,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SFMMD3 ,SPI mode select" "Mode 0,Mode 3"
|
|
bitfld.long 0x00 7. " SFMPAE ,Function select for stopping prefetch at locations other than on byte boundaries" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SFMPFE ,Prefetch function select" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " SFMSE ,QSSL extension function select after SPI bus access" "No extension,Extended by 33,Extended by 129,Extended infinitely"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " SFMRM ,Serial interface read mode select" "Standard Read,Fast Read,Fast Read Dual Output,Fast Read Dual I/O,Fast Read Quad Output,Fast Read Quad I/O,,"
|
|
line.long 0x04 "SFMSSC,Chip Selection Control Register"
|
|
bitfld.long 0x04 5. " SFMSLD ,QSSL signal output timing select" "0.5,1.5"
|
|
bitfld.long 0x04 4. " SFMSHD ,QSSL signal release timing select" "0.5,1.5"
|
|
bitfld.long 0x04 0.--3. " SFMSW ,Minimum high-level width select for QSSL signal" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x08 "SFMSKC,Clock Control Register"
|
|
bitfld.long 0x08 5. " SFMDTY ,Duty ratio correction function select for the QSPCLK signal" "Disabled,Enabled"
|
|
bitfld.long 0x08 0.--4. " SFMDV ,Serial interface reference cycle select" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SFMSST,Status Register"
|
|
bitfld.long 0x00 7. " PFOFF ,Prefetch function operation state" "Active,Not active"
|
|
bitfld.long 0x00 6. " PFFUL ,Prefetch buffer state" "Not full,Full"
|
|
bitfld.long 0x00 0.--4. " PFCNT ,Number of bytes of prefetched data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "SFMCOM,Communication Port Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SFMD ,Port for direct communication with the SPI bus"
|
|
line.long 0x04 "SFMCMD,Communication Mode Control Register"
|
|
bitfld.long 0x04 0. " DCOM ,Mode select for communication with the SPI bus" "ROM,Direct"
|
|
line.long 0x08 "SFMCST,Communication Status Register"
|
|
bitfld.long 0x08 7. " EROMR ,ROM access detection status in direct communication mode" "Not detected,Detected"
|
|
rbitfld.long 0x08 0. " COMBSY ,SPI bus cycle completion state in direct communication" "Not busy,Busy"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "SFMSIC,Instruction Code Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SFMCIC ,Serial flash instruction code to substitute"
|
|
line.long 0x04 "SFMSAC,Address Mode Control Register"
|
|
bitfld.long 0x04 4. " SFM4BC ,Default instruction code select - use 4-bytes address read instruction code" "Not used,Used"
|
|
bitfld.long 0x04 0.--1. " SFMAS ,Number of address bytes select for the serial interface" "1,2,3,4"
|
|
line.long 0x08 "SFMSDC,Dummy Cycle Control Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " SFMXD ,Mode data for serial flash"
|
|
bitfld.long 0x08 7. " SFMXEN ,XIP mode permission" "Prohibited,Permitted"
|
|
rbitfld.long 0x08 6. " SFMXST ,XIP mode status" "Normal,XIP"
|
|
bitfld.long 0x08 0.--3. " SFMDN ,Number of dummy cycles select for Fast Read instructions" "Default,3 QSPCLK,4 QSPCLK,5 QSPCLK,6 QSPCLK,7 QSPCLK,8 QSPCLK,9 QSPCLK,10 QSPCLK,11 QSPCLK,12 QSPCLK,13 QSPCLK,14 QSPCLK,15 QSPCLK,16 QSPCLK,17 QSPCLK"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "SFMSPC,SPI Protocol Control Register"
|
|
bitfld.long 0x00 4. " SFMSDE ,Minimum time select for input output switch" "Not allocated,Allocated"
|
|
bitfld.long 0x00 0.--1. " SFMSPI ,SPI protocol select" "Extended,Dual,Quad,"
|
|
line.long 0x04 "SFMPMD,Port Control Register"
|
|
bitfld.long 0x04 2. " SFMWPL ,WP pin specification" "Low,High"
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "SFMCNT1,External QSPI Address Register"
|
|
hexmask.long.byte 0x00 26.--31. 4. " QSPI_EXT ,Bank switching address"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
base ad:0x40074000
|
|
width 11.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "CRCCR0,CRC Control Register 0"
|
|
eventfld.byte 0x00 7. " DORCLR ,CRCDOR/CRCDOR_HA/CRCDOR_BY Register Clear" "Not cleared,Cleared"
|
|
bitfld.byte 0x00 6. " LMS ,CRC Calculation Switching" "LSB-first,MSB-first"
|
|
bitfld.byte 0x00 0.--2. " GPS ,CRC Generating Polynomial Switching" "Not calculated,8-bit CRC-8,16-bit CRC-16,16-bit CRC-CCITT,32-bit CRC-32,32-bit CRC-32C,,"
|
|
line.byte 0x01 "CRCCR1,CRC Control Register 1"
|
|
bitfld.byte 0x01 7. " CRCSEN ,Snoop Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " CRCSWR ,Snoop-On-Write/Read Switch" "Read,Write"
|
|
if (((per.b(ad:0x40074000))&0x07)==0x01)||(((per.b(ad:0x40074000))&0x07)==0x02)||(((per.b(ad:0x40074000))&0x07)==0x03)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "CRCDIR_BY,CRC Data Input Register"
|
|
elif (((per.b(ad:0x40074000))&0x07)==0x04)||(((per.b(ad:0x40074000))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRCDIR,CRC Data Input Register"
|
|
endif
|
|
if (((per.b(ad:0x40074000))&0x07)==0x01)
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "CRCDOR_BY,CRC Data Output Register"
|
|
elif (((per.b(ad:0x40074000))&0x07)==0x02)||(((per.b(ad:0x40074000))&0x07)==0x03)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "CRCDOR_HA,CRC Data Output Register"
|
|
elif (((per.b(ad:0x40074000))&0x07)==0x04)||(((per.b(ad:0x40074000))&0x07)==0x05)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CRCDOR,CRC Data Output Register"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "CRCSAR,Snoop Address Register"
|
|
hexmask.word 0x00 0.--13. 1. " CRCSA ,Register Snoop Address"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SSI (Serial Sound Interface)"
|
|
tree "Channel 0"
|
|
base ad:0x4004E000
|
|
width 9.
|
|
if (((per.l(ad:0x4004E000))&0x380000)==0x0)||(((per.l(ad:0x4004E000))&0x380000)==0x80000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SSICR,Control Register"
|
|
bitfld.long 0x00 30. " CKS ,Audio Clock Select" "AUDIO_CLK,"
|
|
bitfld.long 0x00 29. " TUIEN ,Transmit FIFO Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " TOIEN ,Transmit FIFO Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RUIEN ,Receive FIFO Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ROIEN ,Receive FIFO Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels" "One,?..."
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length" "8,16,18,20,22,24,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length" "8,6,24,32,?..."
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Slave,Master"
|
|
bitfld.long 0x00 14. " SWSD ,Word Select Direction" "Slave,Master"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Bit Clock Polarity" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Word Select Polarity (1st System Word/2nd System Word)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "0,1"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial-Padding,Padding-Serial"
|
|
bitfld.long 0x00 9. " PDTA ,Parallel Data Allocation" "Lower before upper,Upper before lower"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
bitfld.long 0x00 4.--7. " CKDV ,Serial Bit Clock Frequency Setting" "MCLK,MCLK/2,MCLK/4,MCLK/8,MCLK/16,MCLK/32,MCLK/64,MCLK/128,MCLK/6,MCLK/12,MCLK/24,MCLK/48,MCLK/96,?..."
|
|
bitfld.long 0x00 3. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
bitfld.long 0x00 1. " TEN ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " REN ,Receive Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x4004E000))&0x380000)==0x100000)||(((per.l(ad:0x4004E000))&0x380000)==0x180000)||(((per.l(ad:0x4004E000))&0x380000)==0x200000)||(((per.l(ad:0x4004E000))&0x380000)==0x280000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SSICR,Control Register"
|
|
bitfld.long 0x00 30. " CKS ,Audio Clock Select" "AUDIO_CLK,"
|
|
bitfld.long 0x00 29. " TUIEN ,Transmit FIFO Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " TOIEN ,Transmit FIFO Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RUIEN ,Receive FIFO Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ROIEN ,Receive FIFO Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels" "One,?..."
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length" "8,16,18,20,22,24,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length" "8,6,24,32,?..."
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Slave,Master"
|
|
bitfld.long 0x00 14. " SWSD ,Word Select Direction" "Slave,Master"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Bit Clock Polarity" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Word Select Polarity" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "0,1"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial-Padding,Padding-Serial"
|
|
bitfld.long 0x00 9. " PDTA ,Parallel Data Allocation" "Lower before upper,Upper before lower"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
bitfld.long 0x00 4.--7. " CKDV ,Serial Bit Clock Frequency Setting" "MCLK,MCLK/2,MCLK/4,MCLK/8,MCLK/16,MCLK/32,MCLK/64,MCLK/128,MCLK/6,MCLK/12,MCLK/24,MCLK/48,MCLK/96,?..."
|
|
bitfld.long 0x00 3. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
bitfld.long 0x00 1. " TEN ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " REN ,Receive Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR,Status Register"
|
|
bitfld.long 0x00 29. " TUIRQ ,Transmit Underflow Interrupt Status Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " TOIRQ ,Transmit Overflow Interrupt Status Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " RUIRQ ,Receive Underflow Interrupt Status Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " ROIRQ ,Receive Overflow Interrupt Status Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " IIRQ ,Idle Interrupt Status Flag" "No idle,Idle"
|
|
rbitfld.long 0x00 5.--6. " TCHNO ,Transmit Channel Number" "0,1,2,3"
|
|
rbitfld.long 0x00 4. " TSWNO ,Transmit System Word Number" "0,1"
|
|
rbitfld.long 0x00 2.--3. " RCHNO ,Receive Channel Number" "0,1,2,3"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " RSWNO ,Receive System Word Number" "0,1"
|
|
rbitfld.long 0x00 0. " IDST ,Idle Status Flag" "No idle,Idle"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SSIFCR,FIFO Control Register"
|
|
bitfld.long 0x00 31. " AUCKE ,Master Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SSIRST ,SSI Software Reset" "No reset,Reset"
|
|
bitfld.long 0x00 6.--7. " TTRG ,Transmit FIFO Threshold Setting Trigger" "7,6,4,2"
|
|
bitfld.long 0x00 4.--5. " RTRG ,Receive FIFO Threshold Setting Trigger" "1,2,4,6"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TIE ,Transmit FIFO Data Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RIE ,Receive FIFO Data Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TFRST ,Transmit FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " RFRST ,Receive FIFO Data Register Reset" "No reset,Reset"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SSIFSR,FIFO Status Register"
|
|
rbitfld.long 0x00 24.--27. " TDC ,Transmit Data Indicate Flag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " TDE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
rbitfld.long 0x00 8.--11. " RDC ,Receive Data Indicate Flag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " RDF ,Receive Data Full Flag" "Not full,Full"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "SSIFTDR,Transmit FIFO Data Register"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "SSIFRDR,Receive FIFO Data Register"
|
|
in
|
|
if (((per.l(ad:0x4004E000))&0x8000)==0x8000)&&(((per.l(ad:0x4004E000))&0x4000)==0x4000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSITDMR,TDM Mode Register"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSITDMR,TDM Mode Register"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
tree "Channel 1"
|
|
base ad:0x4004E100
|
|
width 9.
|
|
if (((per.l(ad:0x4004E100))&0x380000)==0x0)||(((per.l(ad:0x4004E100))&0x380000)==0x80000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SSICR,Control Register"
|
|
bitfld.long 0x00 30. " CKS ,Audio Clock Select" "AUDIO_CLK,"
|
|
bitfld.long 0x00 29. " TUIEN ,Transmit FIFO Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " TOIEN ,Transmit FIFO Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RUIEN ,Receive FIFO Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ROIEN ,Receive FIFO Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels" "One,?..."
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length" "8,16,18,20,22,24,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length" "8,6,24,32,?..."
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Slave,Master"
|
|
bitfld.long 0x00 14. " SWSD ,Word Select Direction" "Slave,Master"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Bit Clock Polarity" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Word Select Polarity (1st System Word/2nd System Word)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "0,1"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial-Padding,Padding-Serial"
|
|
bitfld.long 0x00 9. " PDTA ,Parallel Data Allocation" "Lower before upper,Upper before lower"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
bitfld.long 0x00 4.--7. " CKDV ,Serial Bit Clock Frequency Setting" "MCLK,MCLK/2,MCLK/4,MCLK/8,MCLK/16,MCLK/32,MCLK/64,MCLK/128,MCLK/6,MCLK/12,MCLK/24,MCLK/48,MCLK/96,?..."
|
|
bitfld.long 0x00 3. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
bitfld.long 0x00 1. " TEN ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " REN ,Receive Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x4004E100))&0x380000)==0x100000)||(((per.l(ad:0x4004E100))&0x380000)==0x180000)||(((per.l(ad:0x4004E100))&0x380000)==0x200000)||(((per.l(ad:0x4004E100))&0x380000)==0x280000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SSICR,Control Register"
|
|
bitfld.long 0x00 30. " CKS ,Audio Clock Select" "AUDIO_CLK,"
|
|
bitfld.long 0x00 29. " TUIEN ,Transmit FIFO Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " TOIEN ,Transmit FIFO Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RUIEN ,Receive FIFO Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ROIEN ,Receive FIFO Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels" "One,?..."
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length" "8,16,18,20,22,24,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length" "8,6,24,32,?..."
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Slave,Master"
|
|
bitfld.long 0x00 14. " SWSD ,Word Select Direction" "Slave,Master"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Bit Clock Polarity" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Word Select Polarity" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "0,1"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial-Padding,Padding-Serial"
|
|
bitfld.long 0x00 9. " PDTA ,Parallel Data Allocation" "Lower before upper,Upper before lower"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
bitfld.long 0x00 4.--7. " CKDV ,Serial Bit Clock Frequency Setting" "MCLK,MCLK/2,MCLK/4,MCLK/8,MCLK/16,MCLK/32,MCLK/64,MCLK/128,MCLK/6,MCLK/12,MCLK/24,MCLK/48,MCLK/96,?..."
|
|
bitfld.long 0x00 3. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
bitfld.long 0x00 1. " TEN ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " REN ,Receive Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR,Status Register"
|
|
bitfld.long 0x00 29. " TUIRQ ,Transmit Underflow Interrupt Status Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " TOIRQ ,Transmit Overflow Interrupt Status Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " RUIRQ ,Receive Underflow Interrupt Status Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " ROIRQ ,Receive Overflow Interrupt Status Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " IIRQ ,Idle Interrupt Status Flag" "No idle,Idle"
|
|
rbitfld.long 0x00 5.--6. " TCHNO ,Transmit Channel Number" "0,1,2,3"
|
|
rbitfld.long 0x00 4. " TSWNO ,Transmit System Word Number" "0,1"
|
|
rbitfld.long 0x00 2.--3. " RCHNO ,Receive Channel Number" "0,1,2,3"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " RSWNO ,Receive System Word Number" "0,1"
|
|
rbitfld.long 0x00 0. " IDST ,Idle Status Flag" "No idle,Idle"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SSIFCR,FIFO Control Register"
|
|
bitfld.long 0x00 31. " AUCKE ,Master Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SSIRST ,SSI Software Reset" "No reset,Reset"
|
|
bitfld.long 0x00 6.--7. " TTRG ,Transmit FIFO Threshold Setting Trigger" "7,6,4,2"
|
|
bitfld.long 0x00 4.--5. " RTRG ,Receive FIFO Threshold Setting Trigger" "1,2,4,6"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TIE ,Transmit FIFO Data Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RIE ,Receive FIFO Data Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TFRST ,Transmit FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " RFRST ,Receive FIFO Data Register Reset" "No reset,Reset"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SSIFSR,FIFO Status Register"
|
|
rbitfld.long 0x00 24.--27. " TDC ,Transmit Data Indicate Flag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " TDE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
rbitfld.long 0x00 8.--11. " RDC ,Receive Data Indicate Flag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " RDF ,Receive Data Full Flag" "Not full,Full"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "SSIFTDR,Transmit FIFO Data Register"
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "SSIFRDR,Receive FIFO Data Register"
|
|
in
|
|
if (((per.l(ad:0x4004E100))&0x8000)==0x8000)&&(((per.l(ad:0x4004E100))&0x4000)==0x4000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSITDMR,TDM Mode Register"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSITDMR,TDM Mode Register"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
tree "SDHI (SD/MMC Host Interface)"
|
|
base ad:0x40062000
|
|
width 17.
|
|
if (((per.l(ad:0x40062000))&0x700)==(0x300||0x400||0x500||0x600||0x700))&&((((per.l(ad:0x40062000))&0x800)==0x800)&&(((per.l(ad:0x40062000))&0x2000)==0x2000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SD_CMD,Command Type Register"
|
|
bitfld.long 0x00 14.--15. " CMD12AT ,CMD12 automatic issue select" "Automatically,Not automatically,?..."
|
|
newline
|
|
bitfld.long 0x00 13. " TRSTP ,Block transfer select" "Single,Multiple"
|
|
bitfld.long 0x00 12. " CMDRW ,Data transfer direction select" "Write,Read"
|
|
newline
|
|
bitfld.long 0x00 11. " CMDTP ,Data transfer select" "Not included,Included"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " RSPTP ,Response type select" "Normal,,,Extended,Extended/R1/R5/R6/R7,Extended/R1b,Extended/R2,Extended/R3/R4"
|
|
bitfld.long 0x00 6.--7. " ACMD ,Command type select" "CMD,ACMD,?..."
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDIDX ,Command index field value select"
|
|
elif (((per.l(ad:0x40062000))&0x700)==(0x300||0x400||0x500||0x600||0x700))&&(((per.l(ad:0x40062000))&0x800)==0x800)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SD_CMD,Command Type Register"
|
|
newline
|
|
bitfld.long 0x00 13. " TRSTP ,Block transfer select" "Single,Multiple"
|
|
bitfld.long 0x00 12. " CMDRW ,Data transfer direction select" "Write,Read"
|
|
newline
|
|
bitfld.long 0x00 11. " CMDTP ,Data transfer select" "Not included,Included"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " RSPTP ,Response type select" "Normal,,,Extended,Extended/R1/R5/R6/R7,Extended/R1b,Extended/R2,Extended/R3/R4"
|
|
bitfld.long 0x00 6.--7. " ACMD ,Command type select" "CMD,ACMD,?..."
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDIDX ,Command index field value select"
|
|
elif (((per.l(ad:0x40062000))&0x700)==(0x300||0x400||0x500||0x600||0x700))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SD_CMD,Command Type Register"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 11. " CMDTP ,Data transfer select" "Not included,Included"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " RSPTP ,Response type select" "Normal,,,Extended,Extended/R1/R5/R6/R7,Extended/R1b,Extended/R2,Extended/R3/R4"
|
|
bitfld.long 0x00 6.--7. " ACMD ,Command type select" "CMD,ACMD,?..."
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDIDX ,Command index field value select"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SD_CMD,Command Type Register"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 8.--10. " RSPTP ,Response Type Select" "Normal,,,Extended,Extended/R1/R5/R6/R7,Extended/R1b,Extended/R2,Extended/R3/R4"
|
|
bitfld.long 0x00 6.--7. " ACMD ,Command Type Select" "CMD,ACMD,?..."
|
|
hexmask.long.byte 0x00 0.--5. 1. " CMDIDX ,Command index field value select"
|
|
endif
|
|
tree.open "Bus Slave MPU"
|
|
group.word 0xC10++0x01
|
|
line.word 0x00 "SMPUMBIU,Access Control Register for Memory bus 3"
|
|
sif cpuis("R7FS5*")
|
|
bitfld.word 0x00 15. " WPSRAMHS ,SRAMHS write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RPSRAMHS ,SRAMHS read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " WPFLI ,Code flash memory write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " RPFLI ,Code flash memory read protection" "No effect,Enabled"
|
|
newline
|
|
sif !cpuis("R7FS5D5*")
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b read protection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
group.word 0xC14++0x01
|
|
line.word 0x00 "SMPUFBIU,Access Control Register for Internal peripheral bus 9"
|
|
sif cpuis("R7FS5*")
|
|
sif !cpuis("R7FS5D5*")
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "No effect,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "No effect,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b ReadProtection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WPCPU ,CPU write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RPCPU ,CPU read protection" "Disabled,Enabled"
|
|
group.word 0xC18++0x01
|
|
line.word 0x00 "SMPUSRAM0,Access Control Register for Memory bus 4"
|
|
sif cpuis("R7FS5*")
|
|
sif !cpuis("R7FS5D5*")
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b ReadProtection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WPCPU ,CPU write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RPCPU ,CPU read protection" "Disabled,Enabled"
|
|
group.word 0xC1C++0x01
|
|
line.word 0x00 "SMPUSRAM1,Access Control Register for Memory bus 5"
|
|
sif cpuis("R7FS5*")
|
|
sif !cpuis("R7FS5D5*")
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b ReadProtection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WPCPU ,CPU write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RPCPU ,CPU read protection" "Disabled,Enabled"
|
|
group.word 0xC20++0x01
|
|
line.word 0x00 "SMPUP0BIU,Access Control Register for Internal peripheral bus 1"
|
|
sif cpuis("R7FS5*")
|
|
sif !cpuis("R7FS5D5*")
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "No effect,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "No effect,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "No effect,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b ReadProtection" "No effect,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WPCPU ,CPU write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RPCPU ,CPU read protection" "Disabled,Enabled"
|
|
group.word 0xC24++0x01
|
|
line.word 0x00 "SMPUP3BIU,Access Control Register for Internal peripheral bus 3"
|
|
sif cpuis("R7FS5*")
|
|
sif !cpuis("R7FS5D5*")
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "No effect,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "No effect,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "No effect,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b ReadProtection" "No effect,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WPCPU ,CPU write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RPCPU ,CPU read protection" "Disabled,Enabled"
|
|
group.word 0xC28++0x01
|
|
line.word 0x00 "SMPUP7BIU,Access Control Register for Internal peripheral bus 7"
|
|
sif cpuis("R7FS5*")
|
|
sif !cpuis("R7FS5D5*")
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "No effect,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "No effect,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "No effect,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b ReadProtection" "No effect,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WPCPU ,CPU write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RPCPU ,CPU read protection" "Disabled,Enabled"
|
|
sif cpuis("R7FS5D9*")
|
|
group.word 0xC2C++0x01
|
|
line.word 0x00 "SMPUP8BIU,Access Control Register for Internal peripheral bus 8"
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "No effect,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "No effect,Enabled"
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "No effect,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b ReadProtection" "No effect,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WPCPU ,CPU write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RPCPU ,CPU read protection" "Disabled,Enabled"
|
|
endif
|
|
group.word 0xC30++0x01
|
|
line.word 0x00 "SMPUEXBIU,Access Control Register for CS area"
|
|
sif cpuis("R7FS5D9*")
|
|
sif !cpuis("R7FS5D5*")
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b ReadProtection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WPCPU ,CPU write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RPCPU ,CPU read protection" "Disabled,Enabled"
|
|
group.word 0xC34++0x01
|
|
line.word 0x00 "SMPUEXBIU2,Access Control Register for QSPI area"
|
|
sif cpuis("R7FS5D9*")
|
|
sif !cpuis("R7FS5D5*")
|
|
bitfld.word 0x00 7. " WPGRPC ,Master group c write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RPGRPC ,Master group c read protection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 5. " WPGRPB ,Master group b write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RPGRPB ,Master group b ReadProtection" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.word 0x00 3. " WPGRPA ,Master group a write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RPGRPA ,Master group a read protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WPCPU ,CPU write protection" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RPCPU ,CPU read protection" "Disabled,Enabled"
|
|
group.word 0xC00++0x01
|
|
line.word 0x00 "SMPUCTL,Slave MPU Control Register"
|
|
hexmask.word.BYTE 0x00 8.--15. 1. " KEY ,Key code"
|
|
bitfld.word 0x00 1. " PROTECT ,Protection of register" "Not protected,Protected"
|
|
bitfld.word 0x00 0. " OAD ,Operation after detection" "Interrupt,Reset"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "ADC14 (14-Bit A/D Converter)"
|
|
base ad:0x4005C000
|
|
width 12.
|
|
if (((per.b(ad:0x4005C000+0x0C))&0x07)==0x00)
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x8000)==0x0)
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x6)==0x6)
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Registers 0"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Registers 1"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Registers 2"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Registers 3"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Registers 4"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Registers 5"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Registers 6"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Registers 7"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Registers 8"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Registers 9"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Registers 10"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x36++0x01
|
|
line.word 0x00 "ADDR11,A/D Data Registers 11"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "ADDR12,A/D Data Registers 12"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3A++0x01
|
|
line.word 0x00 "ADDR13,A/D Data Registers 13"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADDR14,A/D Data Registers 14"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3E++0x01
|
|
line.word 0x00 "ADDR15,A/D Data Registers 15"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Registers 16"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Registers 17"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Registers 18"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Registers 19"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Registers 20"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Registers 21"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Registers 22"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x4E++0x01
|
|
line.word 0x00 "ADDR23,A/D Data Registers 23"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "ADDR24,A/D Data Registers 24"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x52++0x01
|
|
line.word 0x00 "ADDR25,A/D Data Registers 25"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x54++0x01
|
|
line.word 0x00 "ADDR26,A/D Data Registers 26"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x56++0x01
|
|
line.word 0x00 "ADDR27,A/D Data Registers 27"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
elif (cpuis("R7FS3A77C2A01CBJ"))
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Registers 0"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Registers 1"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Registers 2"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Registers 3"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Registers 4"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Registers 5"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Registers 6"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Registers 7"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Registers 8"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Registers 9"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Registers 10"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x36++0x01
|
|
line.word 0x00 "ADDR11,A/D Data Registers 11"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "ADDR12,A/D Data Registers 12"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3A++0x01
|
|
line.word 0x00 "ADDR13,A/D Data Registers 13"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADDR14,A/D Data Registers 14"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3E++0x01
|
|
line.word 0x00 "ADDR15,A/D Data Registers 15"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Registers 16"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Registers 17"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Registers 18"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Registers 19"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Registers 20"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Registers 21"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Registers 22"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x4E++0x01
|
|
line.word 0x00 "ADDR23,A/D Data Registers 23"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "ADDR24,A/D Data Registers 24"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x52++0x01
|
|
line.word 0x00 "ADDR25,A/D Data Registers 25"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
elif (cpuis("R7FS3A77C3A01CFP"))||(cpuis("R7FS3A77C2A01CLJ"))
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Registers 0"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Registers 1"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Registers 2"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Registers 3"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Registers 4"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Registers 5"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Registers 6"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Registers 7"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Registers 8"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Registers 9"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Registers 10"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x36++0x01
|
|
line.word 0x00 "ADDR11,A/D Data Registers 11"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "ADDR12,A/D Data Registers 12"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3A++0x01
|
|
line.word 0x00 "ADDR13,A/D Data Registers 13"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADDR14,A/D Data Registers 14"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3E++0x01
|
|
line.word 0x00 "ADDR15,A/D Data Registers 15"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Registers 16"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Registers 17"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Registers 18"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Registers 19"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Registers 20"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Registers 21"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Registers 22"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x4E++0x01
|
|
line.word 0x00 "ADDR23,A/D Data Registers 23"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "ADDR24,A/D Data Registers 24"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
elif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Registers 0"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Registers 1"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Registers 2"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Registers 3"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Registers 4"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Registers 5"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Registers 6"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Registers 7"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Registers 8"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Registers 9"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Registers 10"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x36++0x01
|
|
line.word 0x00 "ADDR11,A/D Data Registers 11"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "ADDR12,A/D Data Registers 12"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3A++0x01
|
|
line.word 0x00 "ADDR13,A/D Data Registers 13"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADDR14,A/D Data Registers 14"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3E++0x01
|
|
line.word 0x00 "ADDR15,A/D Data Registers 15"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Registers 16"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Registers 17"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
endif
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
else
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Registers 0"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Registers 1"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Registers 2"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Registers 3"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Registers 4"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Registers 5"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Registers 6"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Registers 7"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Registers 8"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Registers 9"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Registers 10"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x36++0x01
|
|
line.word 0x00 "ADDR11,A/D Data Registers 11"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "ADDR12,A/D Data Registers 12"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x3A++0x01
|
|
line.word 0x00 "ADDR13,A/D Data Registers 13"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADDR14,A/D Data Registers 14"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x3E++0x01
|
|
line.word 0x00 "ADDR15,A/D Data Registers 15"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Registers 16"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Registers 17"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Registers 18"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Registers 19"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Registers 20"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Registers 21"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Registers 22"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x4E++0x01
|
|
line.word 0x00 "ADDR23,A/D Data Registers 23"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "ADDR24,A/D Data Registers 24"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x52++0x01
|
|
line.word 0x00 "ADDR25,A/D Data Registers 25"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x54++0x01
|
|
line.word 0x00 "ADDR26,A/D Data Registers 26"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x56++0x01
|
|
line.word 0x00 "ADDR27,A/D Data Registers 27"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x06)==0x06)
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Registers 0"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Registers 1"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Registers 2"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Registers 3"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Registers 4"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Registers 5"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Registers 6"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Registers 7"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Registers 8"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Registers 9"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Registers 10"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x36++0x01
|
|
line.word 0x00 "ADDR11,A/D Data Registers 11"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "ADDR12,A/D Data Registers 12"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3A++0x01
|
|
line.word 0x00 "ADDR13,A/D Data Registers 13"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADDR14,A/D Data Registers 14"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3E++0x01
|
|
line.word 0x00 "ADDR15,A/D Data Registers 15"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Registers 16"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Registers 17"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Registers 18"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Registers 19"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Registers 20"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Registers 21"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Registers 22"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x4E++0x01
|
|
line.word 0x00 "ADDR23,A/D Data Registers 23"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "ADDR24,A/D Data Registers 24"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x52++0x01
|
|
line.word 0x00 "ADDR25,A/D Data Registers 25"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x54++0x01
|
|
line.word 0x00 "ADDR26,A/D Data Registers 26"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x56++0x01
|
|
line.word 0x00 "ADDR27,A/D Data Registers 27"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
else
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Registers 0"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Registers 1"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Registers 2"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Registers 3"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Registers 4"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Registers 5"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Registers 6"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Registers 7"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Registers 8"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Registers 9"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Registers 10"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x36++0x01
|
|
line.word 0x00 "ADDR11,A/D Data Registers 11"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "ADDR12,A/D Data Registers 12"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x3A++0x01
|
|
line.word 0x00 "ADDR13,A/D Data Registers 13"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADDR14,A/D Data Registers 14"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x3E++0x01
|
|
line.word 0x00 "ADDR15,A/D Data Registers 15"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Registers 16"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Registers 17"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Registers 18"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Registers 19"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Registers 20"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Registers 21"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Registers 22"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x4E++0x01
|
|
line.word 0x00 "ADDR23,A/D Data Registers 23"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "ADDR24,A/D Data Registers 24"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x52++0x01
|
|
line.word 0x00 "ADDR25,A/D Data Registers 25"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x54++0x01
|
|
line.word 0x00 "ADDR26,A/D Data Registers 26"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x56++0x01
|
|
line.word 0x00 "ADDR27,A/D Data Registers 27"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,Converted Value 11 to 0"
|
|
endif
|
|
endif
|
|
elif (((per.b(ad:0x4005C000+0x0C))&0x80)==0x80)
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x06)==0x06)
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Registers 0"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Registers 1"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Registers 2"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Registers 3"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Registers 4"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Registers 5"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Registers 6"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Registers 7"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Registers 8"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Registers 9"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Registers 10"
|
|
rgroup.word 0x36++0x01
|
|
line.word 0x00 "ADDR11,A/D Data Registers 11"
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "ADDR12,A/D Data Registers 12"
|
|
rgroup.word 0x3A++0x01
|
|
line.word 0x00 "ADDR13,A/D Data Registers 13"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADDR14,A/D Data Registers 14"
|
|
rgroup.word 0x3E++0x01
|
|
line.word 0x00 "ADDR15,A/D Data Registers 15"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Registers 16"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Registers 17"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Registers 18"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Registers 19"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Registers 20"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Registers 21"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Registers 22"
|
|
rgroup.word 0x4E++0x01
|
|
line.word 0x00 "ADDR23,A/D Data Registers 23"
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "ADDR24,A/D Data Registers 24"
|
|
rgroup.word 0x52++0x01
|
|
line.word 0x00 "ADDR25,A/D Data Registers 25"
|
|
rgroup.word 0x54++0x01
|
|
line.word 0x00 "ADDR26,A/D Data Registers 26"
|
|
rgroup.word 0x56++0x01
|
|
line.word 0x00 "ADDR27,A/D Data Registers 27"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
else
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Registers 0"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Registers 1"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Registers 2"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Registers 3"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Registers 4"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Registers 5"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Registers 6"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Registers 7"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Registers 8"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Registers 9"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Registers 10"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x36++0x01
|
|
line.word 0x00 "ADDR11,A/D Data Registers 11"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "ADDR12,A/D Data Registers 12"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x3A++0x01
|
|
line.word 0x00 "ADDR13,A/D Data Registers 13"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADDR14,A/D Data Registers 14"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x3E++0x01
|
|
line.word 0x00 "ADDR15,A/D Data Registers 15"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Registers 16"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Registers 17"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Registers 18"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Registers 19"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Registers 20"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Registers 21"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Registers 22"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x4E++0x01
|
|
line.word 0x00 "ADDR23,A/D Data Registers 23"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "ADDR24,A/D Data Registers 24"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x52++0x01
|
|
line.word 0x00 "ADDR25,A/D Data Registers 25"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x54++0x01
|
|
line.word 0x00 "ADDR26,A/D Data Registers 26"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x56++0x01
|
|
line.word 0x00 "ADDR27,A/D Data Registers 27"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,Converted Value 11 to 0"
|
|
endif
|
|
elif (((per.b(ad:0x4005C000+0x0C))&0x80)==0x0)
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x8000)==0x0)
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x6)==0x6)
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Registers 0"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Registers 1"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Registers 2"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Registers 3"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Registers 4"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Registers 5"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Registers 6"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Registers 7"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Registers 8"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Registers 9"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Registers 10"
|
|
rgroup.word 0x36++0x01
|
|
line.word 0x00 "ADDR11,A/D Data Registers 11"
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "ADDR12,A/D Data Registers 12"
|
|
rgroup.word 0x3A++0x01
|
|
line.word 0x00 "ADDR13,A/D Data Registers 13"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADDR14,A/D Data Registers 14"
|
|
rgroup.word 0x3E++0x01
|
|
line.word 0x00 "ADDR15,A/D Data Registers 15"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Registers 16"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Registers 17"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Registers 18"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Registers 19"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Registers 20"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Registers 21"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Registers 22"
|
|
rgroup.word 0x4E++0x01
|
|
line.word 0x00 "ADDR23,A/D Data Registers 23"
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "ADDR24,A/D Data Registers 24"
|
|
rgroup.word 0x52++0x01
|
|
line.word 0x00 "ADDR25,A/D Data Registers 25"
|
|
rgroup.word 0x54++0x01
|
|
line.word 0x00 "ADDR26,A/D Data Registers 26"
|
|
rgroup.word 0x56++0x01
|
|
line.word 0x00 "ADDR27,A/D Data Registers 27"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
else
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Registers 0"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Registers 1"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Registers 2"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Registers 3"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Registers 4"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Registers 5"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Registers 6"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Registers 7"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Registers 8"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Registers 9"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Registers 10"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x36++0x01
|
|
line.word 0x00 "ADDR11,A/D Data Registers 11"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "ADDR12,A/D Data Registers 12"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3A++0x01
|
|
line.word 0x00 "ADDR13,A/D Data Registers 13"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADDR14,A/D Data Registers 14"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3E++0x01
|
|
line.word 0x00 "ADDR15,A/D Data Registers 15"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Registers 16"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Registers 17"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Registers 18"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Registers 19"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Registers 20"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Registers 21"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Registers 22"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x4E++0x01
|
|
line.word 0x00 "ADDR23,A/D Data Registers 23"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "ADDR24,A/D Data Registers 24"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x52++0x01
|
|
line.word 0x00 "ADDR25,A/D Data Registers 25"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x54++0x01
|
|
line.word 0x00 "ADDR26,A/D Data Registers 26"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x56++0x01
|
|
line.word 0x00 "ADDR27,A/D Data Registers 27"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,Converted Value 13 to 0"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x6)==0x6)
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Registers 0"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Registers 1"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Registers 2"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Registers 3"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Registers 4"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Registers 5"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Registers 6"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Registers 7"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Registers 8"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Registers 9"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Registers 10"
|
|
rgroup.word 0x36++0x01
|
|
line.word 0x00 "ADDR11,A/D Data Registers 11"
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "ADDR12,A/D Data Registers 12"
|
|
rgroup.word 0x3A++0x01
|
|
line.word 0x00 "ADDR13,A/D Data Registers 13"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADDR14,A/D Data Registers 14"
|
|
rgroup.word 0x3E++0x01
|
|
line.word 0x00 "ADDR15,A/D Data Registers 15"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Registers 16"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Registers 17"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Registers 18"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Registers 19"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Registers 20"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Registers 21"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Registers 22"
|
|
rgroup.word 0x4E++0x01
|
|
line.word 0x00 "ADDR23,A/D Data Registers 23"
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "ADDR24,A/D Data Registers 24"
|
|
rgroup.word 0x52++0x01
|
|
line.word 0x00 "ADDR25,A/D Data Registers 25"
|
|
rgroup.word 0x54++0x01
|
|
line.word 0x00 "ADDR26,A/D Data Registers 26"
|
|
rgroup.word 0x56++0x01
|
|
line.word 0x00 "ADDR27,A/D Data Registers 27"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
else
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Registers 0"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Registers 1"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Registers 2"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Registers 3"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Registers 4"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Registers 5"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Registers 6"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Registers 7"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Registers 8"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Registers 9"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Registers 10"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x36++0x01
|
|
line.word 0x00 "ADDR11,A/D Data Registers 11"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "ADDR12,A/D Data Registers 12"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3A++0x01
|
|
line.word 0x00 "ADDR13,A/D Data Registers 13"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADDR14,A/D Data Registers 14"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x3E++0x01
|
|
line.word 0x00 "ADDR15,A/D Data Registers 15"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Registers 16"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Registers 17"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Registers 18"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Registers 19"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Registers 20"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Registers 21"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Registers 22"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x4E++0x01
|
|
line.word 0x00 "ADDR23,A/D Data Registers 23"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "ADDR24,A/D Data Registers 24"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x52++0x01
|
|
line.word 0x00 "ADDR25,A/D Data Registers 25"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x54++0x01
|
|
line.word 0x00 "ADDR26,A/D Data Registers 26"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x56++0x01
|
|
line.word 0x00 "ADDR27,A/D Data Registers 27"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,Converted Value 13 to 0"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x8000)==0x0)
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x6)==0x6)
|
|
rgroup.word 0x1E++0x01
|
|
line.word 0x00 "ADRD,A/D Self-Diagnosis Data Register"
|
|
bitfld.word 0x00 14.--15. " DIAGST ,Self-Diagnosis Status" "Not executed,0 V,VREFH0/2,VREFH0"
|
|
hexmask.word 0x00 0.--13. 1. " AD[13:0] ,Converted Value 13 to 0"
|
|
else
|
|
rgroup.word 0x1E++0x01
|
|
line.word 0x00 "ADRD,A/D Self-Diagnosis Data Register"
|
|
bitfld.word 0x00 14.--15. " DIAGST ,Self-Diagnosis Status" "Not executed,0 V,VREFH0/2,VREFH0"
|
|
hexmask.word 0x00 0.--11. 1. " AD[11:0] ,Converted Value 11 to 0"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x6)==0x6)
|
|
rgroup.word 0x1E++0x01
|
|
line.word 0x00 "ADRD,A/D Self-Diagnosis Data Register"
|
|
bitfld.word 0x00 0.--1. " DIAGST ,Self-Diagnosis Status" "Not executed,0 V,VREFH0/2,VREFH0"
|
|
hexmask.word 0x00 2.--15. 1. " AD[13:0] ,Converted Value 13 to 0"
|
|
else
|
|
rgroup.word 0x1E++0x01
|
|
line.word 0x00 "ADRD,A/D Self-Diagnosis Data Register"
|
|
bitfld.word 0x00 0.--1. " DIAGST ,Self-Diagnosis Status" "Not executed,0 V,VREFH0/2,VREFH0"
|
|
hexmask.word 0x00 4.--15. 1. " AD[11:0] ,Converted Value 11 to 0"
|
|
endif
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "ADCSR,A/D Control Register"
|
|
bitfld.word 0x00 15. " ADST ,A/D Conversion Start" "Stopped,Started"
|
|
bitfld.word 0x00 13.--14. " ADCS ,Scan Mode Select" "Single,Group,Continous,"
|
|
bitfld.word 0x00 10. " ASHSC ,A/D Conversion Mode Select" "High-speed,Low-power"
|
|
bitfld.word 0x00 9. " TRGE ,Trigger Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " EXTRG ,Trigger Select" "Synchronous,Asynchronous"
|
|
bitfld.word 0x00 7. " DBLE ,Double Trigger Mode Select" "Deselected,Selected"
|
|
bitfld.word 0x00 6. " GBADIE ,Group B Scan End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--4. " DBLANS ,Double Trigger Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0x04++0x03
|
|
line.word 0x00 "ADANSA0,A/D Channel Select Register A0"
|
|
bitfld.word 0x00 15. " ANSA15 ,A/D Conversion Channel 15 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 14. " ANSA14 ,A/D Conversion Channel 14 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 13. " ANSA13 ,A/D Conversion Channel 13 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 12. " ANSA12 ,A/D Conversion Channel 12 Select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x00 11. " ANSA11 ,A/D Conversion Channel 11 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 10. " ANSA10 ,A/D Conversion Channel 10 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 9. " ANSA09 ,A/D Conversion Channel 9 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 8. " ANSA08 ,A/D Conversion Channel 8 Select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ANSA07 ,A/D Conversion Channel 7 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 6. " ANSA06 ,A/D Conversion Channel 6 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 5. " ANSA05 ,A/D Conversion Channel 5 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 4. " ANSA04 ,A/D Conversion Channel 4 Select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ANSA03 ,A/D Conversion Channel 3 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 2. " ANSA02 ,A/D Conversion Channel 2 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 1. " ANSA01 ,A/D Conversion Channel 1 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 0. " ANSA00 ,A/D Conversion Channel 0 Select" "Not selected,Selected"
|
|
line.word 0x02 "ADANSA1,A/D Channel Select Register A1"
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x02 11. " ANSA27 ,A/D Conversion Channel 27 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 10. " ANSA26 ,A/D Conversion Channel 26 Select" "Not selected,Selected"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x02 9. " ANSA25 ,A/D Conversion Channel 25 Select" "Not selected,Selected"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x02 8. " ANSA24 ,A/D Conversion Channel 24 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 7. " ANSA23 ,A/D Conversion Channel 23 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 6. " ANSA22 ,A/D Conversion Channel 22 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 5. " ANSA21 ,A/D Conversion Channel 21 Select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x02 4. " ANSA20 ,A/D Conversion Channel 20 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 3. " ANSA19 ,A/D Conversion Channel 19 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 2. " ANSA18 ,A/D Conversion Channel 18 Select" "Not selected,Selected"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x02 1. " ANSA17 ,A/D Conversion Channel 17 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 0. " ANSA16 ,A/D Conversion Channel 16 Select" "Not selected,Selected"
|
|
group.word 0x14++0x03
|
|
line.word 0x00 "ADANSB0,A/D Channel Select Register B0"
|
|
bitfld.word 0x00 15. " ANSB15 ,A/D Conversion Channel 15 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 14. " ANSB14 ,A/D Conversion Channel 14 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 13. " ANSB13 ,A/D Conversion Channel 13 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 12. " ANSB12 ,A/D Conversion Channel 12 Select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x00 11. " ANSB11 ,A/D Conversion Channel 11 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 10. " ANSB10 ,A/D Conversion Channel 10 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 9. " ANSB09 ,A/D Conversion Channel 9 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 8. " ANSB08 ,A/D Conversion Channel 8 Select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ANSB07 ,A/D Conversion Channel 7 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 6. " ANSB06 ,A/D Conversion Channel 6 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 5. " ANSB05 ,A/D Conversion Channel 5 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 4. " ANSB04 ,A/D Conversion Channel 4 Select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ANSB03 ,A/D Conversion Channel 3 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 2. " ANSB02 ,A/D Conversion Channel 2 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 1. " ANSB01 ,A/D Conversion Channel 1 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 0. " ANSB00 ,A/D Conversion Channel 0 Select" "Not selected,Selected"
|
|
line.word 0x02 "ADANSB1,A/D Channel Select Register B1"
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x02 11. " ANSB27 ,A/D Conversion Channel 27 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 10. " ANSB26 ,A/D Conversion Channel 26 Select" "Not selected,Selected"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x02 9. " ANSB25 ,A/D Conversion Channel 25 Select" "Not selected,Selected"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x02 8. " ANSB24 ,A/D Conversion Channel 24 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 7. " ANSB23 ,A/D Conversion Channel 23 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 6. " ANSB22 ,A/D Conversion Channel 22 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 5. " ANSB21 ,A/D Conversion Channel 21 Select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x02 4. " ANSB20 ,A/D Conversion Channel 20 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 3. " ANSB19 ,A/D Conversion Channel 19 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 2. " ANSB18 ,A/D Conversion Channel 18 Select" "Not selected,Selected"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x02 1. " ANSB17 ,A/D Conversion Channel 17 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 0. " ANSB16 ,A/D Conversion Channel 16 Select" "Not selected,Selected"
|
|
group.word 0x08++0x03
|
|
line.word 0x00 "ADADS0,A/D-Converted Value Addition/Average Channel Select Register 0"
|
|
bitfld.word 0x00 15. " ANSA15 ,A/D-Converted Value Addition/Average Channel 15 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 14. " ANSA14 ,A/D-Converted Value Addition/Average Channel 14 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 13. " ANSA13 ,A/D-Converted Value Addition/Average Channel 13 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 12. " ANSA12 ,A/D-Converted Value Addition/Average Channel 12 Select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x00 11. " ANSA11 ,A/D-Converted Value Addition/Average Channel 11 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 10. " ANSA10 ,A/D-Converted Value Addition/Average Channel 10 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 9. " ANSA09 ,A/D-Converted Value Addition/Average Channel 9 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 8. " ANSA08 ,A/D-Converted Value Addition/Average Channel 8 Select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ANSA07 ,A/D-Converted Value Addition/Average Channel 7 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 6. " ANSA06 ,A/D-Converted Value Addition/Average Channel 6 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 5. " ANSA05 ,A/D-Converted Value Addition/Average Channel 5 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 4. " ANSA04 ,A/D-Converted Value Addition/Average Channel 4 Select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ANSA03 ,A/D-Converted Value Addition/Average Channel 3 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 2. " ANSA02 ,A/D-Converted Value Addition/Average Channel 2 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 1. " ANSA01 ,A/D-Converted Value Addition/Average Channel 1 Select" "Not selected,Selected"
|
|
bitfld.word 0x00 0. " ANSA00 ,A/D-Converted Value Addition/Average Channel 0 Select" "Not selected,Selected"
|
|
line.word 0x02 "ADADS1,A/D-Converted Value Addition/Average Channel Select Register 1"
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x02 11. " ANSA27 ,A/D-Converted Value Addition/Average Channel 27 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 10. " ANSA26 ,A/D-Converted Value Addition/Average Channel 26 Select" "Not selected,Selected"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x02 9. " ANSA25 ,A/D-Converted Value Addition/Average Channel 25 Select" "Not selected,Selected"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x02 8. " ANSA24 ,A/D-Converted Value Addition/Average Channel 24 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 7. " ANSA23 ,A/D-Converted Value Addition/Average Channel 23 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 6. " ANSA22 ,A/D-Converted Value Addition/Average Channel 22 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 5. " ANSA21 ,A/D-Converted Value Addition/Average Channel 21 Select" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x02 4. " ANSA20 ,A/D-Converted Value Addition/Average Channel 20 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 3. " ANSA19 ,A/D-Converted Value Addition/Average Channel 19 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 2. " ANSA18 ,A/D-Converted Value Addition/Average Channel 18 Select" "Not selected,Selected"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x02 1. " ANSA17 ,A/D-Converted Value Addition/Average Channel 17 Select" "Not selected,Selected"
|
|
bitfld.word 0x02 0. " ANSA16 ,A/D-Converted Value Addition/Average Channel 16 Select" "Not selected,Selected"
|
|
group.byte 0x0C++0x01
|
|
line.byte 0x00 "ADADC,A/D-Converted Value Addition/Average Count Select Register"
|
|
bitfld.byte 0x00 7. " AVEE ,Average Mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " ADC ,Count Select" "1,2,3,4,16,,,"
|
|
group.word 0x0E++0x05
|
|
line.word 0x00 "ADCER,A/D Control Extended Register"
|
|
bitfld.word 0x00 15. " ADRFMT ,A/D Data Register Format Select" "Flush-right,Flush-left"
|
|
bitfld.word 0x00 11. " DIAGM ,Self-Diagnosis Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DIAGLD ,Self-Diagnosis Mode Select" "Rotation,Fixed"
|
|
bitfld.word 0x00 8.--9. " DIAGVAL ,Self-Diagnosis Conversion Voltage Select" ",0 V,VREFH0/2,VREFH0"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ACE ,A/D Data Register Automatic Clearing Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--2. " ADPRC ,A/D Conversion Accuracy Specify" "12 bit,,,14 bit"
|
|
line.word 0x02 "ADSTRGR,A/D Conversion Start Trigger Select Register"
|
|
hexmask.word.byte 0x02 8.--13. 1. " TRSA ,A/D Conversion Start Trigger Select"
|
|
hexmask.word.byte 0x02 0.--5. 1. " TRSB ,A/D Conversion Start Trigger Select for Group B"
|
|
line.word 0x04 "ADEXICR,A/D Conversion Extended Input Control Register"
|
|
bitfld.word 0x04 9. " OCSA ,Internal Reference Voltage A/D Conversion Select" "Disabled,Enabled"
|
|
bitfld.word 0x04 8. " TSSA ,Temperature Sensor Output A/D Conversion Select" "Disabled,Enabled"
|
|
bitfld.word 0x04 1. " OCSAD ,Internal Reference Voltage A/DConverted Value Addition/Average Mode Select" "Not selected,Selected"
|
|
bitfld.word 0x04 0. " TSSAD ,Temperature Sensor Output A/DConverted Value Addition/Average Mode Select" "Not selected,Selected"
|
|
group.byte 0xE0++0x00
|
|
line.byte 0x00 "ADSSTR00,A/D Sampling State Register 0"
|
|
group.byte 0xE1++0x00
|
|
line.byte 0x00 "ADSSTR01,A/D Sampling State Register 1"
|
|
group.byte 0xE2++0x00
|
|
line.byte 0x00 "ADSSTR02,A/D Sampling State Register 2"
|
|
group.byte 0xE3++0x00
|
|
line.byte 0x00 "ADSSTR03,A/D Sampling State Register 3"
|
|
group.byte 0xE4++0x00
|
|
line.byte 0x00 "ADSSTR04,A/D Sampling State Register 4"
|
|
group.byte 0xE5++0x00
|
|
line.byte 0x00 "ADSSTR05,A/D Sampling State Register 5"
|
|
group.byte 0xE6++0x00
|
|
line.byte 0x00 "ADSSTR06,A/D Sampling State Register 6"
|
|
group.byte 0xE7++0x00
|
|
line.byte 0x00 "ADSSTR07,A/D Sampling State Register 7"
|
|
group.byte 0xE8++0x00
|
|
line.byte 0x00 "ADSSTR08,A/D Sampling State Register 8"
|
|
group.byte 0xE9++0x00
|
|
line.byte 0x00 "ADSSTR09,A/D Sampling State Register 9"
|
|
group.byte 0xEA++0x00
|
|
line.byte 0x00 "ADSSTR010,A/D Sampling State Register 10"
|
|
group.byte 0xEB++0x00
|
|
line.byte 0x00 "ADSSTR011,A/D Sampling State Register 11"
|
|
group.byte 0xEC++0x00
|
|
line.byte 0x00 "ADSSTR012,A/D Sampling State Register 12"
|
|
group.byte 0xED++0x00
|
|
line.byte 0x00 "ADSSTR013,A/D Sampling State Register 13"
|
|
group.byte 0xEE++0x00
|
|
line.byte 0x00 "ADSSTR014,A/D Sampling State Register 14"
|
|
group.byte 0xEF++0x00
|
|
line.byte 0x00 "ADSSTR015,A/D Sampling State Register 15"
|
|
group.byte 0xDD++0x02
|
|
line.byte 0x00 "ADSSTRL,A/D Sampling State Register L"
|
|
line.byte 0x01 "ADSSTRT,A/D Sampling State Register T"
|
|
line.byte 0x02 "ADSSTRO,A/D Sampling State Register O"
|
|
group.byte 0x7A++0x00
|
|
line.byte 0x00 "ADDISCR, A/D Disconnection Detection Control Register "
|
|
bitfld.byte 0x00 4. " ADNDIS[4] ,Precharge/discharge select" "Discharge,Precharge"
|
|
bitfld.byte 0x00 0.--3. " ADNDIS[3:0] ,Precharge/discharge period" "0,,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.w(ad:0x4005C000+0x80))&0x01)==0x01)
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "ADGSPCR,A/D Group Scan Priority Control Register"
|
|
bitfld.word 0x00 15. " GBRP ,Group B Single Scan Continuous Start" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " GBRSCN ,Group B Restart Setting" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " PGS ,Group A Priority Control Setting" "Disabled,Enabled"
|
|
else
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "ADGSPCR,A/D Group Scan Priority Control Register"
|
|
bitfld.word 0x00 0. " PGS ,Group A Priority Control Setting" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x90++0x01
|
|
line.word 0x00 "ADCMPCR,A/D Compare Function Control Register"
|
|
bitfld.word 0x00 15. " CMPAIE ,Compare A Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " WCMPE ,Window Function Setting" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CMPBIE ,Compare B Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CMPAE ,Compare Window A Operation Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CMPBE ,Compare Window B Operation Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CMPAB ,Window A/B Composite Conditions Setting" "OR,EXOR,AND,"
|
|
group.word 0x94++0x03
|
|
line.word 0x00 "ADCMPANSR0,A/D Compare Function Window A Channel Select Register 0"
|
|
bitfld.word 0x00 15. " CMPCHA15 ,Compare Window A Channel 15 Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " CMPCHA14 ,Compare Window A Channel 14 Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CMPCHA13 ,Compare Window A Channel 13 Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CMPCHA12 ,Compare Window A Channel 12 Select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CMPCHA11 ,Compare Window A Channel 11 Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CMPCHA10 ,Compare Window A Channel 10 Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CMPCHA09 ,Compare Window A Channel 9 Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CMPCHA08 ,Compare Window A Channel 8 Select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CMPCHA07 ,Compare Window A Channel 7 Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " CMPCHA06 ,Compare Window A Channel 6 Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CMPCHA05 ,Compare Window A Channel 5 Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CMPCHA04 ,Compare Window A Channel 4 Select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CMPCHA03 ,Compare Window A Channel 3 Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CMPCHA02 ,Compare Window A Channel 2 Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CMPCHA01 ,Compare Window A Channel 1 Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CMPCHA00 ,Compare Window A Channel 0 Select" "Disabled,Enabled"
|
|
line.word 0x02 "ADCMPANSR1,A/D Compare Function Window A Channel Select Register 1"
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x02 11. " CMPCHA27 ,Compare Window A Channel XX Select" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " CMPCHA26 ,Compare Window A Channel XX Select" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x02 9. " CMPCHA25 ,Compare Window A Channel XX Select" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x02 8. " CMPCHA24 ,Compare Window A Channel 24 Select" "Disabled,Enabled"
|
|
bitfld.word 0x02 7. " CMPCHA23 ,Compare Window A Channel 23 Select" "Disabled,Enabled"
|
|
bitfld.word 0x02 6. " CMPCHA22 ,Compare Window A Channel 22 Select" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " CMPCHA21 ,Compare Window A Channel 21 Select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x02 4. " CMPCHA20 ,Compare Window A Channel 20 Select" "Disabled,Enabled"
|
|
bitfld.word 0x02 3. " CMPCHA19 ,Compare Window A Channel 19 Select" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " CMPCHA18 ,Compare Window A Channel 18 Select" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x02 1. " CMPCHA17 ,Compare Window A Channel 17 Select" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " CMPCHA16 ,Compare Window A Channel 16 Select" "Disabled,Enabled"
|
|
group.byte 0x92++0x00
|
|
line.byte 0x00 "ADCMPANSER,A/D Compare Function Window A Extended Input Select Register"
|
|
bitfld.byte 0x00 1. " CMPOCA ,Internal Reference Voltage Compare Select" "Excluded,Included"
|
|
bitfld.byte 0x00 0. " CMPTSA ,Temperature Sensor Output Compare Select" "Excluded,Included"
|
|
if (((per.l(ad:0x4005C000+0x90))&0x4000)==0x0)
|
|
group.word 0x98++0x01
|
|
line.word 0x00 "ADCMPLR0,A/D Compare Function Window A Comparison Condition Setting Register 0"
|
|
bitfld.word 0x00 15. " CMPLCHA15 ,Compare Window A Comparison Condition Select for Channel 15" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 14. " CMPLCHA14 ,Compare Window A Comparison Condition Select for Channel 14" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 13. " CMPLCHA13 ,Compare Window A Comparison Condition Select for Channel 13" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 12. " CMPLCHA12 ,Compare Window A Comparison Condition Select for Channel 12" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CMPLCHA11 ,Compare Window A Comparison Condition Select for Channel 11" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 10. " CMPLCHA10 ,Compare Window A Comparison Condition Select for Channel 10" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 9. " CMPLCHA09 ,Compare Window A Comparison Condition Select for Channel 9" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 8. " CMPLCHA08 ,Compare Window A Comparison Condition Select for Channel 8" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CMPLCHA07 ,Compare Window A Comparison Condition Select for Channel 7" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 6. " CMPLCHA06 ,Compare Window A Comparison Condition Select for Channel 6" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 5. " CMPLCHA05 ,Compare Window A Comparison Condition Select for Channel 5" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 4. " CMPLCHA04 ,Compare Window A Comparison Condition Select for Channel 4" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CMPLCHA03 ,Compare Window A Comparison Condition Select for Channel 3" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 2. " CMPLCHA02 ,Compare Window A Comparison Condition Select for Channel 2" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 1. " CMPLCHA01 ,Compare Window A Comparison Condition Select for Channel 1" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 0. " CMPLCHA00 ,Compare Window A Comparison Condition Select for Channel 0" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
else
|
|
group.word 0x98++0x01
|
|
line.word 0x00 "ADCMPLR0,A/D Compare Function Window A Comparison Condition Setting Register 0"
|
|
bitfld.word 0x00 15. " CMPLCHA15 ,Compare Window A Comparison Condition Select for Channel 15" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 14. " CMPLCHA14 ,Compare Window A Comparison Condition Select for Channel 14" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 13. " CMPLCHA13 ,Compare Window A Comparison Condition Select for Channel 13" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CMPLCHA12 ,Compare Window A Comparison Condition Select for Channel 12" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 11. " CMPLCHA11 ,Compare Window A Comparison Condition Select for Channel 11" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 10. " CMPLCHA10 ,Compare Window A Comparison Condition Select for Channel 10" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CMPLCHA09 ,Compare Window A Comparison Condition Select for Channel 09" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 8. " CMPLCHA08 ,Compare Window A Comparison Condition Select for Channel 08" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 7. " CMPLCHA07 ,Compare Window A Comparison Condition Select for Channel 07" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CMPLCHA06 ,Compare Window A Comparison Condition Select for Channel 06" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 5. " CMPLCHA05 ,Compare Window A Comparison Condition Select for Channel 05" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 4. " CMPLCHA04 ,Compare Window A Comparison Condition Select for Channel 04" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CMPLCHA03 ,Compare Window A Comparison Condition Select for Channel 03" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 2. " CMPLCHA02 ,Compare Window A Comparison Condition Select for Channel 02" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 1. " CMPLCHA01 ,Compare Window A Comparison Condition Select for Channel 01" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CMPLCHA00 ,Compare Window A Comparison Condition Select for Channel 00" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
endif
|
|
if (((per.l(ad:0x4005C000+0x90))&0x4000)==0x00)
|
|
group.word 0x9A++0x01
|
|
line.word 0x00 "ADCMPLR1,A/D Compare Function Window A Comparison Condition Setting Register 1"
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x00 11. " CMPLCHA27 ,Compare Window A Comparison Condition Select for Channel 27" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 10. " CMPLCHA26 ,Compare Window A Comparison Condition Select for Channel 26" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x00 9. " CMPLCHA25 ,Compare Window A Comparison Condition Select for Channel 25" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x00 8. " CMPLCHA24 ,Compare Window A Comparison Condition Select for Channel 24" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 7. " CMPLCHA23 ,Compare Window A Comparison Condition Select for Channel 23" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 6. " CMPLCHA22 ,Compare Window A Comparison Condition Select for Channel 22" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 5. " CMPLCHA21 ,Compare Window A Comparison Condition Select for Channel 21" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CMPLCHA20 ,Compare Window A Comparison Condition Select for Channel 20" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 3. " CMPLCHA19 ,Compare Window A Comparison Condition Select for Channel 19" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 2. " CMPLCHA18 ,Compare Window A Comparison Condition Select for Channel 18" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 1. " CMPLCHA17 ,Compare Window A Comparison Condition Select for Channel 17" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 0. " CMPLCHA16 ,Compare Window A Comparison Condition Select for Channel 16" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
else
|
|
group.word 0x9A++0x01
|
|
line.word 0x00 "ADCMPLR1,A/D Compare Function Window A Comparison Condition Setting Register 1"
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x00 11. " CMPLCHA27 ,Compare Window A Comparison Condition Select for Channel 27" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 10. " CMPLCHA26 ,Compare Window A Comparison Condition Select for Channel 26" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x00 9. " CMPLCHA25 ,Compare Window A Comparison Condition Select for Channel 25" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x00 8. " CMPLCHA24 ,Compare Window A Comparison Condition Select for Channel 24" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 7. " CMPLCHA23 ,Compare Window A Comparison Condition Select for Channel 23" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 6. " CMPLCHA22 ,Compare Window A Comparison Condition Select for Channel 22" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CMPLCHA21 ,Compare Window A Comparison Condition Select for Channel 21" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 4. " CMPLCHA20 ,Compare Window A Comparison Condition Select for Channel 20" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 3. " CMPLCHA19 ,Compare Window A Comparison Condition Select for Channel 19" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CMPLCHA18 ,Compare Window A Comparison Condition Select for Channel 18" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 1. " CMPLCHA17 ,Compare Window A Comparison Condition Select for Channel 17" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 0. " CMPLCHA16 ,Compare Window A Comparison Condition Select for Channel 16" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
endif
|
|
if (((per.l(ad:0x4005C000+0x90))&0x4000)==0x00)
|
|
group.byte 0x93++0x00
|
|
line.byte 0x00 "ADCMPLER,A/D Compare Function Window A Extended Input Comparison Condition Setting Register"
|
|
bitfld.byte 0x00 1. " CMPLOCA ,Compare Window A Internal Reference Voltage Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.byte 0x00 0. " CMPLTSA ,Compare Window A Temperature Sensor Output Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
else
|
|
group.byte 0x93++0x00
|
|
line.byte 0x00 "ADCMPLER,A/D Compare Function Window A Extended Input Comparison Condition Setting Register"
|
|
bitfld.byte 0x00 1. " CMPLOCA ,Compare Window A Internal Reference Voltage Comparison Condition Select" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.byte 0x00 0. " CMPLTSA ,Compare Window A Temperature Sensor Output Comparison Condition Select" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
endif
|
|
group.word 0x9C++0x03
|
|
line.word 0x00 "ADCMPDR0,A/D Compare Function Window A Lower-Side Level Setting Register"
|
|
line.word 0x02 "ADCMPDR1,A/D Compare Function Window A Upper-Side Level Setting Register"
|
|
group.word 0xA8++0x03
|
|
line.word 0x00 "ADWINLLB,A/D Compare Function Window B Lower-Side Level Setting Register"
|
|
line.word 0x02 "ADWINULB,A/D Compare Function Window B Upper-Side Level Setting Register"
|
|
group.word 0xA0++0x03
|
|
line.word 0x00 "ADCMPSR0,A/D Compare Function Window A Channel Status Register 0"
|
|
bitfld.word 0x00 15. " CMPSTCHA15 ,Channel 15 Compare Window A Flag" "Not met,Met"
|
|
bitfld.word 0x00 14. " CMPSTCHA14 ,Channel 14 Compare Window A Flag" "Not met,Met"
|
|
bitfld.word 0x00 13. " CMPSTCHA13 ,Channel 13 Compare Window A Flag" "Not met,Met"
|
|
bitfld.word 0x00 12. " CMPSTCHA12 ,Channel 12 Compare Window A Flag" "Not met,Met"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CMPSTCHA11 ,Channel 11 Compare Window A Flag" "Not met,Met"
|
|
bitfld.word 0x00 10. " CMPSTCHA10 ,Channel 10 Compare Window A Flag" "Not met,Met"
|
|
bitfld.word 0x00 9. " CMPSTCHA9 ,Channel 9 Compare Window A Flag" "Not met,Met"
|
|
bitfld.word 0x00 8. " CMPSTCHA8 ,Channel 8 Compare Window A Flag" "Not met,Met"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CMPSTCHA7 ,Channel 7 Compare Window A Flag" "Not met,Met"
|
|
bitfld.word 0x00 6. " CMPSTCHA6 ,Channel 6 Compare Window A Flag" "Not met,Met"
|
|
bitfld.word 0x00 5. " CMPSTCHA5 ,Channel 5 Compare Window A Flag" "Not met,Met"
|
|
bitfld.word 0x00 4. " CMPSTCHA4 ,Channel 4 Compare Window A Flag" "Not met,Met"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CMPSTCHA3 ,Channel 3 Compare Window A Flag" "Not met,Met"
|
|
bitfld.word 0x00 2. " CMPSTCHA2 ,Channel 2 Compare Window A Flag" "Not met,Met"
|
|
bitfld.word 0x00 1. " CMPSTCHA1 ,Channel 1 Compare Window A Flag" "Not met,Met"
|
|
bitfld.word 0x00 0. " CMPSTCHA0 ,Channel 0 Compare Window A Flag" "Not met,Met"
|
|
line.word 0x02 "ADCMPSR1,A/D Compare Function Window A Channel Status Register1"
|
|
sif (!cpuis("R7FS3A77C2A01CBJ"))&&(!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x02 11. " CMPSTCHA27 ,Channel 27 Compare Window A Flag" "Not met,Met"
|
|
bitfld.word 0x02 10. " CMPSTCHA26 ,Channel 26 Compare Window A Flag" "Not met,Met"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))&&(!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x02 9. " CMPSTCHA25 ,Channel 25 Compare Window A Flag" "Not met,Met"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.word 0x02 8. " CMPSTCHA24 ,Channel 24 Compare Window A Flag" "Not met,Met"
|
|
bitfld.word 0x02 7. " CMPSTCHA23 ,Channel 23 Compare Window A Flag" "Not met,Met"
|
|
bitfld.word 0x02 6. " CMPSTCHA22 ,Channel 22 Compare Window A Flag" "Not met,Met"
|
|
bitfld.word 0x02 5. " CMPSTCHA21 ,Channel 21 Compare Window A Flag" "Not met,Met"
|
|
textline " "
|
|
bitfld.word 0x02 4. " CMPSTCHA20 ,Channel 20 Compare Window A Flag" "Not met,Met"
|
|
bitfld.word 0x02 3. " CMPSTCHA19 ,Channel 19 Compare Window A Flag" "Not met,Met"
|
|
bitfld.word 0x02 2. " CMPSTCHA18 ,Channel 18 Compare Window A Flag" "Not met,Met"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x02 1. " CMPSTCHA17 ,Channel 17 Compare Window A Flag" "Not met,Met"
|
|
bitfld.word 0x02 0. " CMPSTCHA16 ,Channel 16 Compare Window A Flag" "Not met,Met"
|
|
group.byte 0xA4++0x00
|
|
line.byte 0x00 "ADCMPSER,A/D Compare Function Window A Extended Input Channel Status Register"
|
|
bitfld.byte 0x00 1. " CMPSTOCA ,Compare Window A Internal Reference Voltage Compare Flag" "Not met,Met"
|
|
bitfld.byte 0x00 0. " ADCMPSER ,Compare Window A Temperature Sensor Output Compare Flag" "Not met,Met"
|
|
if (((per.l(ad:0x4005C000+0x90))&0x4000)==0x0)
|
|
group.byte 0xA6++0x00
|
|
line.byte 0x00 "ADCMPBNSR,A/D Compare Function Window B Channel Select Register"
|
|
bitfld.byte 0x00 7. " CMPLB ,Compare Window B Comparison Condition Setting" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.byte 0x00 0.--5. " CMPCHB ,Compare Window B Channel Select" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,,,,,Temperature sensor,Internal reference voltage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Not selected"
|
|
else
|
|
group.byte 0xA6++0x00
|
|
line.byte 0x00 "ADCMPBNSR,A/D Compare Function Window B Channel Select Register"
|
|
bitfld.byte 0x00 7. " CMPLB ,Compare Window B Comparison Condition Setting" "A/D<ADCMPDR0 or ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.byte 0x00 0.--5. " CMPCHB ,Compare Window B Channel Select" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,AN011,AN012,AN013,AN014,AN015,AN016,AN017,AN018,AN019,AN020,AN021,AN022,AN023,AN024,AN025,AN026,AN027,,,,,Temperature sensor,Internal reference voltage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Not selected"
|
|
endif
|
|
group.byte 0xAC++0x00
|
|
line.byte 0x00 "ADCMPBSR,A/D Compare Function Window B Status Register"
|
|
bitfld.byte 0x00 0. " CMPSTB ,Compare Window B Flag" "Not met,Met"
|
|
rgroup.byte 0x8C++0x00
|
|
line.byte 0x00 "ADWINMON,A/D Compare Function Window A/B Status Monitor Register"
|
|
bitfld.byte 0x00 5. " MONCMPB ,Comparison Result Monitor B" "Not met,Met"
|
|
bitfld.byte 0x00 4. " MONCMPA ,Comparison Result Monitor A" "Not met,Met"
|
|
bitfld.byte 0x00 0. " MONCOMB ,Combination Result Monitor" "Not met,Met"
|
|
group.byte 0x8A++0x00
|
|
line.byte 0x00 "ADHVREFCNT,A/D High-Potential/Low-Potential Reference Voltage Control Register"
|
|
bitfld.byte 0x00 7. " ADSLP ,Sleep" "Normal,Standby"
|
|
bitfld.byte 0x00 4. " LVSEL ,Low-Potential Reference Voltage Select" "AVSS0,VREFL0"
|
|
bitfld.byte 0x00 0.--1. " HVSEL ,High-Potential Reference Voltage Select" "AVCC0,VREFH0,Internal referenced,Internal discharged"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DAC12 (12-Bit D/A Converter)"
|
|
tree "Channel 0"
|
|
base ad:0x4005E000
|
|
width 10.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DADR0,D/A Data Register 0"
|
|
group.byte ad:0x4005E004++0x03
|
|
line.byte 0x00 "DACR,D/A Control Register"
|
|
bitfld.byte 0x00 7. " DAADST ,D/A A/D Synchronous Conversion" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DAOE0 ,D/A Output Enable 0" "Disabled,Enabled"
|
|
line.byte 0x01 "DADPR,DADR0 Format Select Register"
|
|
bitfld.byte 0x01 7. " DPSEL ,DADR0 Format Select" "Right,Left"
|
|
line.byte 0x02 "DAADSCR,D/A A/D Synchronous Start Control Register"
|
|
bitfld.byte 0x02 7. " DAADST ,D/A A/D Synchronous Conversion" "Do not synchronize,Synchronize"
|
|
line.byte 0x03 "DAVREFCR,D/A VREF Control Register"
|
|
bitfld.byte 0x03 0.--2. " REF ,D/A Reference Voltage Select" "None,AVCC0/AVSS0,,Internal/AVSS0,,,VREFH/VREFL,"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0x4005E002
|
|
width 10.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DADR1,D/A Data Register 1"
|
|
group.byte ad:0x4005E004++0x03
|
|
line.byte 0x00 "DACR,D/A Control Register"
|
|
bitfld.byte 0x00 7. " DAADST ,D/A A/D Synchronous Conversion" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DAOE0 ,D/A Output Enable 0" "Disabled,Enabled"
|
|
line.byte 0x01 "DADPR,DADR0 Format Select Register"
|
|
bitfld.byte 0x01 7. " DPSEL ,DADR1 Format Select" "Right,Left"
|
|
line.byte 0x02 "DAADSCR,D/A A/D Synchronous Start Control Register"
|
|
bitfld.byte 0x02 7. " DAADST ,D/A A/D Synchronous Conversion" "Do not synchronize,Synchronize"
|
|
line.byte 0x03 "DAVREFCR,D/A VREF Control Register"
|
|
bitfld.byte 0x03 0.--2. " REF ,D/A Reference Voltage Select" "None,AVCC0/AVSS0,,Internal/AVSS0,,,VREFH/VREFL,"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "TSN (Temperature Sensor)"
|
|
base ad:0x407EC228
|
|
width 8.
|
|
rgroup.byte 0x00++0x01
|
|
line.byte 0x00 "TSCDRH,Temperature Sensor Calibration Data Register H"
|
|
line.byte 0x01 "TSCDRL,Temperature Sensor Calibration Data Register L"
|
|
width 0x0B
|
|
tree.end
|
|
tree "OPAMP (Operational Amplifier)"
|
|
tree "Unit 0"
|
|
base ad:0x40086008
|
|
width 8.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "AMPMC,Operational Amplifier Mode Control Register"
|
|
bitfld.byte 0x00 7. " AMPSP ,OPAMP Operation Mode Selection" "Low-power,High-power"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x00 3. " AMPPC3 ,Operational Amplifier Precharge Control Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 2. " AMPPC2 ,Operational Amplifier Precharge Control Status" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " AMPPC1 ,Operational Amplifier Precharge Control Status" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " AMPPC0 ,Operational Amplifier Precharge Control Status" "Disabled,Enabled"
|
|
line.byte 0x01 "AMPTRM,Operational Amplifier Trigger Mode Control Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x01 6.--7. " AMPTRM3 ,OPAMP Function Activation/Stop Trigger Control 3" "Software,Activation,,Activation/AD"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x01 4.--5. " AMPTRM2 ,OPAMP Function Activation/Stop Trigger Control 2" "Software,Activation,,Activation/AD"
|
|
bitfld.byte 0x01 2.--3. " AMPTRM1 ,OPAMP Function Activation/Stop Trigger Control 1" "Software,Activation,,Activation/AD"
|
|
bitfld.byte 0x01 0.--1. " AMPTRM0 ,OPAMP Function Activation/Stop Trigger Control 0" "Software,Activation,,Activation/AD"
|
|
line.byte 0x02 "AMPTRS,Operational Amplifier Activation Trigger Select Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x02 0.--1. " AMPTRS ,Activation Trigger Selection" "0/1/2/3,0/0/1/1,,0/1/2/3"
|
|
else
|
|
bitfld.byte 0x02 0.--1. " AMPTRS ,Activation Trigger Selection" "0/1/2,0/0/1,,0/1/2"
|
|
endif
|
|
line.byte 0x03 "AMPC,Operational Amplifier Control Register"
|
|
bitfld.byte 0x03 7. " IREFE ,OPAMP Reference Current Circuit Operation Control" "Disabled,Enabled"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x03 3. " AMPE3 ,OPAMP Operation Control" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x03 2. " AMPE2 ,OPAMP Operation Control" "Disabled,Enabled"
|
|
bitfld.byte 0x03 1. " AMPE1 ,OPAMP Operation Control" "Disabled,Enabled"
|
|
bitfld.byte 0x03 0. " AMPE0 ,OPAMP Operation Control" "Disabled,Enabled"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "AMPMON,Operational Amplifier Monitor Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x00 3. " AMPMON3 ,Operational Amplifier Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 2. " AMPMON2 ,Operational Amplifier Status" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " AMPMON1 ,Operational Amplifier Status" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " AMPMON0 ,Operational Amplifier Status" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 1"
|
|
base ad:0x40086008
|
|
width 8.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "AMPMC,Operational Amplifier Mode Control Register"
|
|
bitfld.byte 0x00 7. " AMPSP ,OPAMP Operation Mode Selection" "Low-power,High-power"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x00 3. " AMPPC3 ,Operational Amplifier Precharge Control Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 2. " AMPPC2 ,Operational Amplifier Precharge Control Status" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " AMPPC1 ,Operational Amplifier Precharge Control Status" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " AMPPC0 ,Operational Amplifier Precharge Control Status" "Disabled,Enabled"
|
|
line.byte 0x01 "AMPTRM,Operational Amplifier Trigger Mode Control Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x01 6.--7. " AMPTRM3 ,OPAMP Function Activation/Stop Trigger Control 3" "Software,Activation,,Activation/AD"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x01 4.--5. " AMPTRM2 ,OPAMP Function Activation/Stop Trigger Control 2" "Software,Activation,,Activation/AD"
|
|
bitfld.byte 0x01 2.--3. " AMPTRM1 ,OPAMP Function Activation/Stop Trigger Control 1" "Software,Activation,,Activation/AD"
|
|
bitfld.byte 0x01 0.--1. " AMPTRM0 ,OPAMP Function Activation/Stop Trigger Control 0" "Software,Activation,,Activation/AD"
|
|
line.byte 0x02 "AMPTRS,Operational Amplifier Activation Trigger Select Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x02 0.--1. " AMPTRS ,Activation Trigger Selection" "0/1/2/3,0/0/1/1,,0/1/2/3"
|
|
else
|
|
bitfld.byte 0x02 0.--1. " AMPTRS ,Activation Trigger Selection" "0/1/2,0/0/1,,0/1/2"
|
|
endif
|
|
line.byte 0x03 "AMPC,Operational Amplifier Control Register"
|
|
bitfld.byte 0x03 7. " IREFE ,OPAMP Reference Current Circuit Operation Control" "Disabled,Enabled"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x03 3. " AMPE3 ,OPAMP Operation Control" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x03 2. " AMPE2 ,OPAMP Operation Control" "Disabled,Enabled"
|
|
bitfld.byte 0x03 1. " AMPE1 ,OPAMP Operation Control" "Disabled,Enabled"
|
|
bitfld.byte 0x03 0. " AMPE0 ,OPAMP Operation Control" "Disabled,Enabled"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "AMPMON,Operational Amplifier Monitor Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x00 3. " AMPMON3 ,Operational Amplifier Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 2. " AMPMON2 ,Operational Amplifier Status" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " AMPMON1 ,Operational Amplifier Status" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " AMPMON0 ,Operational Amplifier Status" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Unit 2"
|
|
base ad:0x40086008
|
|
width 8.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "AMPMC,Operational Amplifier Mode Control Register"
|
|
bitfld.byte 0x00 7. " AMPSP ,OPAMP Operation Mode Selection" "Low-power,High-power"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x00 3. " AMPPC3 ,Operational Amplifier Precharge Control Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 2. " AMPPC2 ,Operational Amplifier Precharge Control Status" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " AMPPC1 ,Operational Amplifier Precharge Control Status" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " AMPPC0 ,Operational Amplifier Precharge Control Status" "Disabled,Enabled"
|
|
line.byte 0x01 "AMPTRM,Operational Amplifier Trigger Mode Control Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x01 6.--7. " AMPTRM3 ,OPAMP Function Activation/Stop Trigger Control 3" "Software,Activation,,Activation/AD"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x01 4.--5. " AMPTRM2 ,OPAMP Function Activation/Stop Trigger Control 2" "Software,Activation,,Activation/AD"
|
|
bitfld.byte 0x01 2.--3. " AMPTRM1 ,OPAMP Function Activation/Stop Trigger Control 1" "Software,Activation,,Activation/AD"
|
|
bitfld.byte 0x01 0.--1. " AMPTRM0 ,OPAMP Function Activation/Stop Trigger Control 0" "Software,Activation,,Activation/AD"
|
|
line.byte 0x02 "AMPTRS,Operational Amplifier Activation Trigger Select Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x02 0.--1. " AMPTRS ,Activation Trigger Selection" "0/1/2/3,0/0/1/1,,0/1/2/3"
|
|
else
|
|
bitfld.byte 0x02 0.--1. " AMPTRS ,Activation Trigger Selection" "0/1/2,0/0/1,,0/1/2"
|
|
endif
|
|
line.byte 0x03 "AMPC,Operational Amplifier Control Register"
|
|
bitfld.byte 0x03 7. " IREFE ,OPAMP Reference Current Circuit Operation Control" "Disabled,Enabled"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x03 3. " AMPE3 ,OPAMP Operation Control" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x03 2. " AMPE2 ,OPAMP Operation Control" "Disabled,Enabled"
|
|
bitfld.byte 0x03 1. " AMPE1 ,OPAMP Operation Control" "Disabled,Enabled"
|
|
bitfld.byte 0x03 0. " AMPE0 ,OPAMP Operation Control" "Disabled,Enabled"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "AMPMON,Operational Amplifier Monitor Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x00 3. " AMPMON3 ,Operational Amplifier Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 2. " AMPMON2 ,Operational Amplifier Status" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " AMPMON1 ,Operational Amplifier Status" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " AMPMON0 ,Operational Amplifier Status" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
tree "Unit 3"
|
|
base ad:0x40086008
|
|
width 8.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "AMPMC,Operational Amplifier Mode Control Register"
|
|
bitfld.byte 0x00 7. " AMPSP ,OPAMP Operation Mode Selection" "Low-power,High-power"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x00 3. " AMPPC3 ,Operational Amplifier Precharge Control Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 2. " AMPPC2 ,Operational Amplifier Precharge Control Status" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " AMPPC1 ,Operational Amplifier Precharge Control Status" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " AMPPC0 ,Operational Amplifier Precharge Control Status" "Disabled,Enabled"
|
|
line.byte 0x01 "AMPTRM,Operational Amplifier Trigger Mode Control Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x01 6.--7. " AMPTRM3 ,OPAMP Function Activation/Stop Trigger Control 3" "Software,Activation,,Activation/AD"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x01 4.--5. " AMPTRM2 ,OPAMP Function Activation/Stop Trigger Control 2" "Software,Activation,,Activation/AD"
|
|
bitfld.byte 0x01 2.--3. " AMPTRM1 ,OPAMP Function Activation/Stop Trigger Control 1" "Software,Activation,,Activation/AD"
|
|
bitfld.byte 0x01 0.--1. " AMPTRM0 ,OPAMP Function Activation/Stop Trigger Control 0" "Software,Activation,,Activation/AD"
|
|
line.byte 0x02 "AMPTRS,Operational Amplifier Activation Trigger Select Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x02 0.--1. " AMPTRS ,Activation Trigger Selection" "0/1/2/3,0/0/1/1,,0/1/2/3"
|
|
else
|
|
bitfld.byte 0x02 0.--1. " AMPTRS ,Activation Trigger Selection" "0/1/2,0/0/1,,0/1/2"
|
|
endif
|
|
line.byte 0x03 "AMPC,Operational Amplifier Control Register"
|
|
bitfld.byte 0x03 7. " IREFE ,OPAMP Reference Current Circuit Operation Control" "Disabled,Enabled"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x03 3. " AMPE3 ,OPAMP Operation Control" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x03 2. " AMPE2 ,OPAMP Operation Control" "Disabled,Enabled"
|
|
bitfld.byte 0x03 1. " AMPE1 ,OPAMP Operation Control" "Disabled,Enabled"
|
|
bitfld.byte 0x03 0. " AMPE0 ,OPAMP Operation Control" "Disabled,Enabled"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "AMPMON,Operational Amplifier Monitor Register"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x00 3. " AMPMON3 ,Operational Amplifier Status" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 2. " AMPMON2 ,Operational Amplifier Status" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " AMPMON1 ,Operational Amplifier Status" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " AMPMON0 ,Operational Amplifier Status" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "ACMPHS (High-Speed Analog Comparator)"
|
|
tree "Channel 0"
|
|
base ad:0x40085000
|
|
width 9.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CMPCTL,Comparator Control Register"
|
|
bitfld.byte 0x00 7. " HCMPON ,Comparator Operation Control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5.--6. " CDFS ,Noise Filter Selection" "Not used,2^3/PCLKB,2^4/PCLKB,2^5/PCLKB"
|
|
bitfld.byte 0x00 3.--4. " CEG ,Selection of Valid Edge" "No edge,Rising,Falling,Both"
|
|
bitfld.byte 0x00 1. " COE ,Comparator Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " CINV ,Comparator Output Polarity Selection" "Not inverted,Inverted"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "CMPSEL0,Comparator Input Select Register"
|
|
bitfld.byte 0x00 0.--5. " CMPSEL ,Comparator Input Selection" "AN004/AMP2O,AN007/AMP3O,DA1,Vref,?..."
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "CMPSEL1,Comparator Reference Voltage Select Register"
|
|
bitfld.byte 0x00 0.--5. " CRVS ,Reference Voltage Selection" "AN005,AN006,DA0,Vref,?..."
|
|
rgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "CMPMON,Comparator Output Monitor Register"
|
|
bitfld.byte 0x00 0. " CMPMON ,Comparator Output Monitor" "Low,High"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "CPIOC,Comparator Output Control Register"
|
|
bitfld.byte 0x00 7. " VREFEN ,Internal Vref Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " CPOE ,Comparator Output Selection" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0x40085C00
|
|
width 9.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CMPCTL,Comparator Control Register"
|
|
bitfld.byte 0x00 7. " HCMPON ,Comparator Operation Control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5.--6. " CDFS ,Noise Filter Selection" "Not used,2^3/PCLKB,2^4/PCLKB,2^5/PCLKB"
|
|
bitfld.byte 0x00 3.--4. " CEG ,Selection of Valid Edge" "No edge,Rising,Falling,Both"
|
|
bitfld.byte 0x00 1. " COE ,Comparator Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " CINV ,Comparator Output Polarity Selection" "Not inverted,Inverted"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "CMPSEL0,Comparator Input Select Register"
|
|
bitfld.byte 0x00 0.--5. " CMPSEL ,Comparator Input Selection" "AN000,AN001,AN002/AMP0O,AN003/AMP1O,AN007/AMP3O,DA1,?..."
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "CMPSEL1,Comparator Reference Voltage Select Register"
|
|
bitfld.byte 0x00 0.--5. " CRVS ,Reference Voltage Selection" "AN000,AN001,AN002/AMP0O,AN003/AMP1O,AN006,DA0,?..."
|
|
rgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "CMPMON,Comparator Output Monitor Register"
|
|
bitfld.byte 0x00 0. " CMPMON ,Comparator Output Monitor" "Low,High"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "CPIOC,Comparator Output Control Register"
|
|
bitfld.byte 0x00 0. " CPOE ,Comparator Output Selection" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "ACMPLP (Low-Power Analog Comparator)"
|
|
base ad:0x40085E00
|
|
width 9.
|
|
if (((per.b(ad:0x40085E00))&0x2)==0x2)&&(((per.b(ad:0x40085E00))&0x20)==0x20)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "COMPMDR,ACMPLP Mode Setting Register"
|
|
bitfld.byte 0x00 7. " C1MON ,ACMPLP1 Monitor Flag" "CMPIN1<VRFL/CMPIN1>VRFH/ACMPLP1 disabled,VRFL<CMPIN1<VRFH"
|
|
bitfld.byte 0x00 6. " C1VRF ,ACMPLP1 Reference Voltage Selection" "CMPREF1,Vref"
|
|
bitfld.byte 0x00 5. " C1WDE ,ACMPLP1 Window Function Mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " C1ENB ,ACMPLP1 Operation Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " C0MON ,ACMPLP0 Monitor Flag" "CMPIN0<VRFL/CMPIN0>VRFH/ACMPLP0 disabled,VRFL<CMPIN0<VRFH"
|
|
bitfld.byte 0x00 2. " C0VRF ,ACMPLP0 Reference Voltage Selection" "CMPREF0,Vref"
|
|
bitfld.byte 0x00 1. " C0WDE ,ACMPLP0 Window Function Mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " C0ENB ,ACMPLP0 Operation Enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0x40085E00))&0x2)==0x2)&&(((per.b(ad:0x40085E00))&0x20)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "COMPMDR,ACMPLP Mode Setting Register"
|
|
bitfld.byte 0x00 7. " C1MON ,ACMPLP1 Monitor Flag" "CMPIN1<CMPREF1/CMPIN1<Vref/ACMPLP1 disabled,CMPIN1>CMPREF1/CMPIN1>Vref"
|
|
bitfld.byte 0x00 6. " C1VRF ,ACMPLP1 Reference Voltage Selection" "CMPREF1,Vref"
|
|
bitfld.byte 0x00 5. " C1WDE ,ACMPLP1 Window Function Mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " C1ENB ,ACMPLP1 Operation Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " C0MON ,ACMPLP0 Monitor Flag" "CMPIN0<VRFL/CMPIN0>VRFH/ACMPLP0 disabled,VRFL<CMPIN0<VRFH"
|
|
bitfld.byte 0x00 2. " C0VRF ,ACMPLP0 Reference Voltage Selection" "CMPREF0,Vref"
|
|
bitfld.byte 0x00 1. " C0WDE ,ACMPLP0 Window Function Mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " C0ENB ,ACMPLP0 Operation Enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0x40085E00))&0x2)==0x0)&&(((per.b(ad:0x40085E00))&0x20)==0x20)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "COMPMDR,ACMPLP Mode Setting Register"
|
|
bitfld.byte 0x00 7. " C1MON ,ACMPLP1 Monitor Flag" "CMPIN1<VRFL/CMPIN1>VRFH/ACMPLP1 disabled,VRFL<CMPIN1<VRFH"
|
|
bitfld.byte 0x00 6. " C1VRF ,ACMPLP1 Reference Voltage Selection" "CMPREF1,Vref"
|
|
bitfld.byte 0x00 5. " C1WDE ,ACMPLP1 Window Function Mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " C1ENB ,ACMPLP1 Operation Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " C0MON ,ACMPLP0 Monitor Flag" "CMPIN0<CMPREF0/CMPIN0<Vref/ACMPLP0 disabled,CMPIN0>CMPREF0/CMPIN0>Vref"
|
|
bitfld.byte 0x00 2. " C0VRF ,ACMPLP0 Reference Voltage Selection" "CMPREF0,Vref"
|
|
bitfld.byte 0x00 1. " C0WDE ,ACMPLP0 Window Function Mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " C0ENB ,ACMPLP0 Operation Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "COMPMDR,ACMPLP Mode Setting Register"
|
|
bitfld.byte 0x00 7. " C1MON ,ACMPLP1 Monitor Flag" "CMPIN1<CMPREF1/CMPIN1<Vref/ACMPLP1 disabled,CMPIN1>CMPREF1/CMPIN1>Vref"
|
|
bitfld.byte 0x00 6. " C1VRF ,ACMPLP1 Reference Voltage Selection" "CMPREF1,Vref"
|
|
bitfld.byte 0x00 5. " C1WDE ,ACMPLP1 Window Function Mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " C1ENB ,ACMPLP1 Operation Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " C0MON ,ACMPLP0 Monitor Flag" "CMPIN0<CMPREF0/CMPIN0<Vref/ACMPLP0 disabled,CMPIN0>CMPREF0/CMPIN0>Vref"
|
|
bitfld.byte 0x00 2. " C0VRF ,ACMPLP0 Reference Voltage Selection" "CMPREF0,Vref"
|
|
bitfld.byte 0x00 1. " C0WDE ,ACMPLP0 Window Function Mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " C0ENB ,ACMPLP0 Operation Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.byte 0x01++0x01
|
|
line.byte 0x00 "COMPFIR,ACMPLP Filter Control Register"
|
|
bitfld.byte 0x00 7. " C1EDG ,ACMPLP1 Edge Detection Selection" "One,Both"
|
|
bitfld.byte 0x00 6. " C1EPO ,ACMPLP1 Edge Polarity Switching" "Rising,Falling"
|
|
bitfld.byte 0x00 4.--5. " C1FCK ,ACMPLP1 Filter Select" "Bypass,PCLK,PCLK/8,PCLK/32"
|
|
bitfld.byte 0x00 3. " C0EDG ,ACMPLP0 Edge Detection Selection" "One,Both"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " C0EPO ,ACMPLP0 Edge Polarity Switching" "Rising,Falling"
|
|
bitfld.byte 0x00 0.--1. " C0FCK ,ACMPLP0 Filter Select" "Bypass,PCLK,PCLK/8,PCLK/32"
|
|
line.byte 0x01 "COMPOCR,ACMPLP Output Control Register"
|
|
bitfld.byte 0x01 7. " SPDMD ,ACMPLP0/ACMPLP1 Speed Selection" "Low,High"
|
|
bitfld.byte 0x01 6. " C1OP ,ACMPLP1 VCOUT Output Polarity Selection" "Non-inverted,Inverted"
|
|
bitfld.byte 0x01 5. " C1OE ,ACMPLP1 VCOUT Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " C0OP ,ACMPLP0 VCOUT Output Polarity Selection" "Non-inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " C0OE ,ACMPLP0 VCOUT Pin Output Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CTSU (Capacitive Touch Sensing Unit)"
|
|
base ad:0x40081000
|
|
width 12.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "CTSUCR0,CTSU Control Register 0"
|
|
bitfld.byte 0x00 4. " CTSUINIT ,CTSU Control Block Initialization" "No effect,Initialized"
|
|
bitfld.byte 0x00 2. " CTSUSNZ ,CTSU Wait State Power-Saving Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " CTSUCAP ,CTSU Measurement Operation Start Trigger Select" "Software,External"
|
|
bitfld.byte 0x00 0. " CTSUSTRT ,CTSU Measurement Operation Start" "Stopped,Started"
|
|
line.byte 0x01 "CTSUCR1,CTSU Control Register 1"
|
|
bitfld.byte 0x01 6.--7. " CTSUMD ,CTSU Measurement Mode Select" "Single-scan,Multi-scan,,Full-scan"
|
|
bitfld.byte 0x01 4.--5. " CTSUCLK ,CTSU Operating Clock Select" "PCLK,PCLK/2,PCLK/4,"
|
|
bitfld.byte 0x01 3. " CTSUATUNE1 ,CTSU Power Supply Capacity Adjustment" "Normal,High-current"
|
|
bitfld.byte 0x01 2. " CTSUATUNE0 ,CTSU Power Supply Operating Mode Setting" "Normal,Low voltage"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " CTSUCSW ,CTSU LPF Capacitance Charging Control" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " CTSUPON ,CTSU Power Supply Enable" "Disabled,Enabled"
|
|
line.byte 0x02 "CTSUSDPRS,CTSU Synchronous Noise Reduction Setting Register"
|
|
bitfld.byte 0x02 6. " CTSUSOFF ,CTSU High-Pass Noise Reduction Function" "Enabled,Disabled"
|
|
bitfld.byte 0x02 4.--5. " CTSUPRMODE ,CTSU Base Period and Pulse Count Setting" "510,126,62,"
|
|
bitfld.byte 0x02 0.--3. " CTSUPRRATIO ,CTSU Measurement Time and Pulse Count Adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x03 "CTSUSST,CTSU Sensor Stabilization Wait Control Register"
|
|
if ((per.b(ad:0x40081000+0x01)&0xC0)==0x0)
|
|
group.byte 0x04++0x01
|
|
line.byte 0x00 "CTSUMCH0,CTSU Measurement Channel Register 0"
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
bitfld.byte 0x00 0.--5. " CTSHMCH0 ,CTSU Measurement Channel 0" "TS00,TS01,TS03,TS04,TS05,TS06,TS07,TS08,TS09,TS10,TS11,TS12,TS13,TS14,TS15,TS16,TS17,TS18,TS19,TS20,TS21,TS22,TS26,TS27,TS29,TS30,TS32,TS33,TS34,TS35,?..."
|
|
elif (cpuis("R7FS3A77C3A01CFP"))||(cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.byte 0x00 0.--5. " CTSHMCH0 ,CTSU Measurement Channel 0" "TS00,TS01,TS03,TS04,TS05,TS06,TS07,TS08,TS09,TS10,TS11,TS12,TS13,TS14,TS15,TS16,TS17,TS18,TS19,TS20,TS21,TS22,TS26,TS27,TS29,TS30,?..."
|
|
elif (cpuis("R7FS3A77C3A01CFM"))||(cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x00 0.--5. " CTSHMCH0 ,CTSU Measurement Channel 0" "TS00,TS01,TS03,TS04,TS05,TS06,TS07,TS08,TS09,TS10,TS11,TS12,TS13,TS14,?..."
|
|
endif
|
|
line.byte 0x01 "CTSUMCH1,CTSU Measurement Channel Register 1"
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
bitfld.byte 0x01 0.--5. " CTSHMCH1 ,CTSU Measurement Channel 1" "TS00,TS01,TS03,TS04,TS05,TS06,TS07,TS08,TS09,TS10,TS11,TS12,TS13,TS14,TS15,TS16,TS17,TS18,TS19,TS20,TS21,TS22,TS26,TS27,TS29,TS30,TS32,TS33,TS34,TS35,?..."
|
|
elif (cpuis("R7FS3A77C3A01CFP"))||(cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.byte 0x01 0.--5. " CTSHMCH1 ,CTSU Measurement Channel 1" "TS00,TS01,TS03,TS04,TS05,TS06,TS07,TS08,TS09,TS10,TS11,TS12,TS13,TS14,TS15,TS16,TS17,TS18,TS19,TS20,TS21,TS22,TS26,TS27,TS29,TS30,?..."
|
|
elif (cpuis("R7FS3A77C3A01CFM"))||(cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x01 0.--5. " CTSHMCH1 ,CTSU Measurement Channel 1" "TS00,TS01,TS03,TS04,TS05,TS06,TS07,TS08,TS09,TS10,TS11,TS12,TS13,TS14,?..."
|
|
endif
|
|
else
|
|
rgroup.byte 0x04++0x01
|
|
line.byte 0x00 "CTSUMCH0,CTSU Measurement Channel Register 0"
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
bitfld.byte 0x00 0.--5. " CTSHMCH0 ,CTSU Measurement Channel 0" "TS00,TS01,TS03,TS04,TS05,TS06,TS07,TS08,TS09,TS10,TS11,TS12,TS13,TS14,TS15,TS16,TS17,TS18,TS19,TS20,TS21,TS22,TS26,TS27,TS29,TS30,TS32,TS33,TS34,TS35,?..."
|
|
elif (cpuis("R7FS3A77C3A01CFP"))||(cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.byte 0x00 0.--5. " CTSHMCH0 ,CTSU Measurement Channel 0" "TS00,TS01,TS03,TS04,TS05,TS06,TS07,TS08,TS09,TS10,TS11,TS12,TS13,TS14,TS15,TS16,TS17,TS18,TS19,TS20,TS21,TS22,TS26,TS27,TS29,TS30,?..."
|
|
elif (cpuis("R7FS3A77C3A01CFM"))||(cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x00 0.--5. " CTSHMCH0 ,CTSU Measurement Channel 0" "TS00,TS01,TS03,TS04,TS05,TS06,TS07,TS08,TS09,TS10,TS11,TS12,TS13,TS14,?..."
|
|
endif
|
|
line.byte 0x01 "CTSUMCH1,CTSU Measurement Channel Register 1"
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
bitfld.byte 0x01 0.--5. " CTSHMCH1 ,CTSU Measurement Channel 1" "TS00,TS01,TS03,TS04,TS05,TS06,TS07,TS08,TS09,TS10,TS11,TS12,TS13,TS14,TS15,TS16,TS17,TS18,TS19,TS20,TS21,TS22,TS26,TS27,TS29,TS30,TS32,TS33,TS34,TS35,?..."
|
|
elif (cpuis("R7FS3A77C3A01CFP"))||(cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.byte 0x01 0.--5. " CTSHMCH1 ,CTSU Measurement Channel 1" "TS00,TS01,TS03,TS04,TS05,TS06,TS07,TS08,TS09,TS10,TS11,TS12,TS13,TS14,TS15,TS16,TS17,TS18,TS19,TS20,TS21,TS22,TS26,TS27,TS29,TS30,?..."
|
|
elif (cpuis("R7FS3A77C3A01CFM"))||(cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x01 0.--5. " CTSHMCH1 ,CTSU Measurement Channel 1" "TS00,TS01,TS03,TS04,TS05,TS06,TS07,TS08,TS09,TS10,TS11,TS12,TS13,TS14,?..."
|
|
endif
|
|
endif
|
|
group.byte 0x06++0x01
|
|
line.byte 0x00 "CTSUCHAC0,CTSU Channel Enable Control Register 0"
|
|
bitfld.byte 0x00 7. " CTSUCHAC0 ,CTSU Pin 07 Channel Enable Control" "Not measured,Measured"
|
|
bitfld.byte 0x00 6. " CTSUCHAC0 ,CTSU Pin 06 Channel Enable Control" "Not measured,Measured"
|
|
bitfld.byte 0x00 5. " CTSUCHAC0 ,CTSU Pin 05 Channel Enable Control" "Not measured,Measured"
|
|
bitfld.byte 0x00 4. " CTSUCHAC0 ,CTSU Pin 04 Channel Enable Control" "Not measured,Measured"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CTSUCHAC0 ,CTSU Pin 03 Channel Enable Control" "Not measured,Measured"
|
|
bitfld.byte 0x00 1. " CTSUCHAC0 ,CTSU Pin 01 Channel Enable Control" "Not measured,Measured"
|
|
bitfld.byte 0x00 0. " CTSUCHAC0 ,CTSU Pin 00 Channel Enable Control" "Not measured,Measured"
|
|
line.byte 0x01 "CTSUCHAC1,CTSU Channel Enable Control Register 1"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x01 7. " CTSUCHAC1 ,CTSU Pin 15 Channel Enable Control" "Not measured,Measured"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x01 6. " CTSUCHAC1 ,CTSU Pin 14 Channel Enable Control" "Not measured,Measured"
|
|
bitfld.byte 0x01 5. " CTSUCHAC1 ,CTSU Pin 13 Channel Enable Control" "Not measured,Measured"
|
|
bitfld.byte 0x01 4. " CTSUCHAC1 ,CTSU Pin 12 Channel Enable Control" "Not measured,Measured"
|
|
bitfld.byte 0x01 3. " CTSUCHAC1 ,CTSU Pin 11 Channel Enable Control" "Not measured,Measured"
|
|
textline " "
|
|
bitfld.byte 0x01 2. " CTSUCHAC1 ,CTSU Pin 10 Channel Enable Control" "Not measured,Measured"
|
|
bitfld.byte 0x01 1. " CTSUCHAC1 ,CTSU Pin 09 Channel Enable Control" "Not measured,Measured"
|
|
bitfld.byte 0x01 0. " CTSUCHAC1 ,CTSU Pin 08 Channel Enable Control" "Not measured,Measured"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.byte 0x08++0x01
|
|
line.byte 0x00 "CTSUCHAC2,CTSU Channel Enable Control Register 2"
|
|
bitfld.byte 0x00 6. " CTSUCHAC2 ,CTSU Pin 22 Channel Enable Control 2" "Not measured,Measured"
|
|
bitfld.byte 0x00 5. " CTSUCHAC2 ,CTSU Pin 21 Channel Enable Control 2" "Not measured,Measured"
|
|
bitfld.byte 0x00 4. " CTSUCHAC2 ,CTSU Pin 20 Channel Enable Control 2" "Not measured,Measured"
|
|
bitfld.byte 0x00 3. " CTSUCHAC2 ,CTSU Pin 19 Channel Enable Control 2" "Not measured,Measured"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " CTSUCHAC2 ,CTSU Pin 18 Channel Enable Control 2" "Not measured,Measured"
|
|
bitfld.byte 0x00 1. " CTSUCHAC2 ,CTSU Pin 17 Channel Enable Control 2" "Not measured,Measured"
|
|
bitfld.byte 0x00 0. " CTSUCHAC2 ,CTSU Pin 16 Channel Enable Control 2" "Not measured,Measured"
|
|
line.byte 0x01 "CTSUCHAC3,CTSU Channel Enable Control Register 3"
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.byte 0x01 7. " CTSUCHAC3 ,CTSU Pin 31 Channel Enable Control 3" "Not measured,Measured"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x01 6. " CTSUCHAC3 ,CTSU Pin 30 Channel Enable Control 3" "Not measured,Measured"
|
|
bitfld.byte 0x01 5. " CTSUCHAC3 ,CTSU Pin 29 Channel Enable Control 3" "Not measured,Measured"
|
|
bitfld.byte 0x01 3. " CTSUCHAC3 ,CTSU Pin 27 Channel Enable Control 3" "Not measured,Measured"
|
|
bitfld.byte 0x01 2. " CTSUCHAC3 ,CTSU Pin 26 Channel Enable Control 3" "Not measured,Measured"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "CTSUCHAC4,CTSU Channel Enable Control Register 4"
|
|
bitfld.byte 0x00 3. " CTSUCHAC4 ,CTSU Pin 35 Channel Enable Control 4" "Not measured,Measured"
|
|
bitfld.byte 0x00 2. " CTSUCHAC4 ,CTSU Pin 34 Channel Enable Control 4" "Not measured,Measured"
|
|
bitfld.byte 0x00 1. " CTSUCHAC4 ,CTSU Pin 33 Channel Enable Control 4" "Not measured,Measured"
|
|
bitfld.byte 0x00 0. " CTSUCHAC4 ,CTSU Pin 32 Channel Enable Control 4" "Not measured,Measured"
|
|
endif
|
|
group.byte 0x0B++0x01
|
|
line.byte 0x00 "CTSUCHTRC0,CTSU Channel Transmit/Receive Control Register 0"
|
|
bitfld.byte 0x00 7. " CTSUCHTRC0 ,CTSU 07 Channel Transmit/Receive Control 0" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x00 6. " CTSUCHTRC0 ,CTSU 06 Channel Transmit/Receive Control 0" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x00 5. " CTSUCHTRC0 ,CTSU 05 Channel Transmit/Receive Control 0" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x00 4. " CTSUCHTRC0 ,CTSU 04 Channel Transmit/Receive Control 0" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CTSUCHTRC0 ,CTSU 03 Channel Transmit/Receive Control 0" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x00 1. " CTSUCHTRC0 ,CTSU 01 Channel Transmit/Receive Control 0" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x00 0. " CTSUCHTRC0 ,CTSU 00 Channel Transmit/Receive Control 0" "Not transmitted,Transmitted"
|
|
line.byte 0x01 "CTSUCHTRC1,CTSU Channel Transmit/Receive Control Register 1"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
bitfld.byte 0x01 7. " CTSUCHTRC1 ,CTSU Pin 15 Channel Transmit/Receive Control 1" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x01 6. " CTSUCHTRC1 ,CTSU Pin 14 Channel Transmit/Receive Control 1" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x01 5. " CTSUCHTRC1 ,CTSU Pin 13 Channel Transmit/Receive Control 1" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x01 4. " CTSUCHTRC1 ,CTSU Pin 12 Channel Transmit/Receive Control 1" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x01 3. " CTSUCHTRC1 ,CTSU Pin 11 Channel Transmit/Receive Control 1" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.byte 0x01 2. " CTSUCHTRC1 ,CTSU Pin 10 Channel Transmit/Receive Control 1" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x01 1. " CTSUCHTRC1 ,CTSU Pin 09 Channel Transmit/Receive Control 1" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x01 0. " CTSUCHTRC1 ,CTSU Pin 08 Channel Transmit/Receive Control 1" "Not transmitted,Transmitted"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.byte 0x0D++0x01
|
|
line.byte 0x00 "CTSUCHTRC2,CTSU Channel Transmit/Receive Control Register 2"
|
|
bitfld.byte 0x00 6. " CTSUCHTRC2 ,CTSU Pin 22 Channel Transmit/Receive Control 2" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x00 5. " CTSUCHTRC2 ,CTSU Pin 21 Channel Transmit/Receive Control 2" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x00 4. " CTSUCHTRC2 ,CTSU Pin 20 Channel Transmit/Receive Control 2" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x00 3. " CTSUCHTRC2 ,CTSU Pin 19 Channel Transmit/Receive Control 2" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " CTSUCHTRC2 ,CTSU Pin 18 Channel Transmit/Receive Control 2" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x00 1. " CTSUCHTRC2 ,CTSU Pin 17 Channel Transmit/Receive Control 2" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x00 0. " CTSUCHTRC2 ,CTSU Pin 16 Channel Transmit/Receive Control 2" "Not transmitted,Transmitted"
|
|
line.byte 0x01 "CTSUCHTRC3,CTSU Channel Transmit/Receive Control Register 3"
|
|
sif (!cpuis("R7FS3A77C3A01CFP"))&&(!cpuis("R7FS3A77C2A01CLJ"))
|
|
bitfld.byte 0x01 7. " CTSUCHTRC3 ,CTSU Pin 31 Channel Transmit/Receive Control 3" "Not transmitted,Transmitted"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x01 6. " CTSUCHTRC3 ,CTSU Pin 30 Channel Transmit/Receive Control 3" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x01 5. " CTSUCHTRC3 ,CTSU Pin 29 Channel Transmit/Receive Control 3" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x01 3. " CTSUCHTRC3 ,CTSU Pin 27 Channel Transmit/Receive Control 3" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x01 2. " CTSUCHTRC3 ,CTSU Pin 26 Channel Transmit/Receive Control 3" "Not transmitted,Transmitted"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "CTSUCHTRC4,CTSU Channel Transmit/Receive Control Register 4"
|
|
bitfld.byte 0x00 3. " CTSUCHTRC4 ,CTSU Pin 35 Channel Transmit/Receive Control 4" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x00 2. " CTSUCHTRC4 ,CTSU Pin 34 Channel Transmit/Receive Control 4" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x00 1. " CTSUCHTRC4 ,CTSU Pin 33 Channel Transmit/Receive Control 4" "Not transmitted,Transmitted"
|
|
bitfld.byte 0x00 0. " CTSUCHTRC4 ,CTSU Pin 32 Channel Transmit/Receive Control 4" "Not transmitted,Transmitted"
|
|
endif
|
|
group.byte 0x10++0x01
|
|
line.byte 0x00 "CTSUDCLKC,CTSU High-Pass Noise Reduction Control Register"
|
|
bitfld.byte 0x00 4.--5. " CTSUSSCNT ,CTSU Diffusion Clock Mode Control" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--1. " CTSUSSMOD ,CTSU Diffusion Clock Mode Select" "0,1,2,3"
|
|
line.byte 0x01 "CTSUST,CTSU Status Register"
|
|
rbitfld.byte 0x01 7. " CTSUPS ,CTSU Mutual Capacitance Status Flag" "First,Second"
|
|
bitfld.byte 0x01 6. " CTSUROVF ,CTSU Reference Counter Overflow Flag" "No overflow,Overflow"
|
|
bitfld.byte 0x01 5. " CTSUSOVF ,CTSU Sensor Counter Overflow Flag" "No overflow,Overflow"
|
|
rbitfld.byte 0x01 4. " CTSUDTSR ,CTSU Data Transfer Status Flag" "Read,Not read"
|
|
textline " "
|
|
rbitfld.byte 0x01 0.--2. " CTSUSTC ,CTSU Measurement Status Counter" "0,1,2,3,4,5,?..."
|
|
group.word 0x12++0x05
|
|
line.word 0x00 "CTSUSSC,CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register"
|
|
bitfld.word 0x00 8.--11. " CTSUSSDIV ,CTSU Spectrum Diffusion Frequency Division Setting" "4.00<=fb,2.00<=fb<4.00,1.33<=fb<2.00,1.00<=fb<1.33,0.80<=fb<1.00,0.67<=fb<0.80,0.57<=fb<0.67,0.50<=fb<0.57,0.44<=fb<0.50,0.40<=fb<0.44,0.36<=fb<0.40,0.33<=fb<0.36,0.31<=fb<0.33,0.29<=fb<0.31,0.27<=fb<0.29,fb<=0.27"
|
|
line.word 0x02 "CTSUSO0,CTSU Sensor Offset Register 0"
|
|
bitfld.word 0x02 10.--15. " CTSUSNUM ,CTSU Measurement Count Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
|
|
hexmask.word 0x02 0.--9. 1. " CTSUSO ,CTSU Sensor Offset Adjustment"
|
|
line.word 0x04 "CTSUSO1,CTSU Sensor Offset Register 1"
|
|
bitfld.word 0x04 13.--14. " CTSUICOG ,CTSU ICO Gain Adjustment" "100%,66%,50%,40%"
|
|
bitfld.word 0x04 8.--12. " CTSUSDPA ,CTSU Base Clock Setting" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62,/64"
|
|
hexmask.word.byte 0x04 0.--7. 1. " CTSURICOA ,CTSU Reference ICO Current Adjustment"
|
|
rgroup.word 0x18++0x05
|
|
line.word 0x00 "CTSUSC,CTSU Sensor Counter"
|
|
line.word 0x02 "CTSURC,CTSU Reference Counter"
|
|
line.word 0x04 "CTSUERRS,CTSU Error Status Register"
|
|
bitfld.word 0x04 15. " CTSUICOMP ,TSCAP Voltage Error Monitor" "Normal,Abnormal"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DOC (Data Operation Circuit)"
|
|
base ad:0x40054100
|
|
width 7.
|
|
if (((per.b(ad:0x40054100))&0x03)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "DOCR,DOC Control Register"
|
|
bitfld.byte 0x00 6. " DOPCFCL ,DOPCF clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " DOPCF ,Data operation circuit flag" "No,Yes"
|
|
bitfld.byte 0x00 2. " DCSEL ,Detection condition select" "Mismatch,Match"
|
|
newline
|
|
bitfld.byte 0x00 0.--1. " OMS ,Operating mode select" "Comparison,Addition,Subtraction,?..."
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "DOCR,DOC Control Register"
|
|
bitfld.byte 0x00 6. " DOPCFCL ,DOPCF clear" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " DOPCF ,Data operation circuit flag" "No,Yes"
|
|
newline
|
|
bitfld.byte 0x00 0.--1. " OMS ,Operating mode select" "Comparison,Addition,Subtraction,?..."
|
|
endif
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "DODIR,DOC Data Input Register"
|
|
line.word 0x02 "DODSR,DOC Data Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SRAM"
|
|
base ad:0x40002000
|
|
width 11.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "PARIOAD,SRAM Parity Error Operation After Detection Register"
|
|
bitfld.byte 0x00 0. " OAD ,Operation After Detection" "Reset,NMI"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SRAMPRCR,SRAM Protection Register"
|
|
hexmask.byte 0x00 1.--7. 1. " KW ,Write Key Code"
|
|
bitfld.byte 0x00 0. " SRAMPRCR ,Register Write Control" "Disabled,Enabled"
|
|
group.byte 0xC0++0x04
|
|
line.byte 0x00 "ECCMODE,ECC Operating Mode Control Register"
|
|
bitfld.byte 0x00 0.--1. " ECCMOD ,ECC Operating Mode Select" "Disabled,,Enabled-no error check,Enabled-error check"
|
|
line.byte 0x01 "ECC2STS,ECC 2-Bit Error Status Register"
|
|
bitfld.byte 0x01 0. " ECC2ERR ,ECC 2-Bit Error Status" "Not occurred,Occurred"
|
|
line.byte 0x02 "ECC1STSEN,ECC 1-Bit Error Information Update Enable Register"
|
|
bitfld.byte 0x02 0. " E1STSEN ,ECC 1-Bit Error Information Update Enable" "Disabled,Enabled"
|
|
line.byte 0x03 "ECC1STS,ECC 1-Bit Error Status Register"
|
|
bitfld.byte 0x03 0. " ECC1ERR ,ECC 1-Bit Error Status" "Not occurred,Occurred"
|
|
line.byte 0x04 "ECCPRCR,ECC Protection Register"
|
|
hexmask.byte 0x04 1.--7. 1. " KW ,Write Key Code"
|
|
bitfld.byte 0x04 0. " ECCPRCR ,Register Write Control" "Disabled,Enabled"
|
|
group.byte 0xD0++0x00
|
|
line.byte 0x00 "ECCPRCR2,ECC Protection Register 2"
|
|
hexmask.byte 0x00 1.--7. 1. " KW ,Write Key Code"
|
|
bitfld.byte 0x00 0. " ECCPRCR2 ,Register Write Control" "Disabled,Enabled"
|
|
group.byte 0xD4++0x00
|
|
line.byte 0x00 "ECCETST,ECC Test Control Register"
|
|
bitfld.byte 0x00 0. " TSTBYP ,ECC Bypass Select" "Disabled,Enabled"
|
|
group.byte 0xD8++0x00
|
|
line.byte 0x00 "ECCOAD,SRAM ECC Error Operation After Detection Register"
|
|
bitfld.byte 0x00 0. " OAD ,Operation After Detection" "Reset,NMI"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Flash Memory"
|
|
base ad:0x4001C100
|
|
width 10.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "FCACHEE,Flash Cache Enable Register"
|
|
bitfld.word 0x00 0. " FCACHEEN ,Flash cache enable" "Disabled,Enabled"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "FCACHEIV,Flash Cache Invalidate Register"
|
|
bitfld.word 0x00 0. " FCACHEIV ,Flash cache invalidate" "Not invalidated,Invalidated"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "FLWT,Flash Wait Cycle Register"
|
|
sif cpuis("R7FS7*")||cpuis("R7FS5D*")
|
|
bitfld.byte 0x00 0.--2. " FLWT ,Flash wait cycle" "0 waits,1 wait,2 waits,?..."
|
|
else
|
|
bitfld.byte 0x00 0.--2. " FLWT ,Flash wait cycle" "Wait,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
tree "SLCDC (Segment LCD Controller/Driver)"
|
|
base ad:0x40082000
|
|
width 7.
|
|
group.byte 0x00++0x02
|
|
line.byte 0x00 "LCDM0,LCD Mode Register 0"
|
|
bitfld.byte 0x00 6.--7. " MDSET ,LCD Drive Voltage Generator Select" "External,Internal,Capacitor,"
|
|
bitfld.byte 0x00 5. " LWAVE ,LCD Display Waveform Select" "A,B"
|
|
bitfld.byte 0x00 2.--4. " LDTY ,Time Slice of LCD Display Select" "Static,2,3,4,,8,,"
|
|
bitfld.byte 0x00 0.--1. " LBAS ,LCD Display Bias Method Select" "1/2,1/3,1/4,"
|
|
line.byte 0x01 "LCDM1,LCD Mode Register 1"
|
|
bitfld.byte 0x01 6.--7. " SCOC_LCDON ,LCD Display Enable/Disable" "Output ground,Display off,Output ground,Display on"
|
|
bitfld.byte 0x01 5. " VLCON ,Voltage boost Circuit or Capacitor Split Circuit Operation Enable/Disable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 3.--4. " BLON_LCDSEL ,Display Data Area Control" "A-pattern,B-pattern,A/B-pattern,A/B-pattern"
|
|
bitfld.byte 0x01 0. " LCDVLM ,Voltage Boosting Pin Initial Value Switching Control" "VCC>=2.7 V,VCC<=4.2 V"
|
|
line.byte 0x02 "LCDC0,LCD Clock Control Register 0"
|
|
bitfld.byte 0x02 0.--5. " LCDC0 ,LCD Clock (LCDCL) Setting" "(Sub clock)/2^2/(LOCO clock)/2^2,(Sub clock)/2^3/(LOCO clock)/2^3,(Sub clock)/2^4/(LOCO clock)/2^4,(Sub clock)/2^5/(LOCO clock)/2^5,(Sub clock)/2^6/(LOCO clock)/2^6,(Sub clock)/2^7/(LOCO clock)/2^7,(Sub clock)/2^8/(LOCO clock)/2^8,(Sub clock)/2^9/(LOCO clock)/2^9,(Sub clock)/2^10/(LOCO clock)/2^10,(Main clock)/2^8/(HOCO clock)/2^8,(Main clock)/2^9/(HOCO clock)/2^9,(Main clock)/2^10/(HOCO clock)/2^10,(Main clock)/2^11/(HOCO clock)/2^11,(Main clock)/2^12/(HOCO clock)/2^12,(Main clock)/2^13/(HOCO clock)/2^13,(Main clock)/2^14/(HOCO clock)/2^14,(Main clock)/2^15/(HOCO clock)/2^15,(Main clock)/2^16/(HOCO clock)/2^16,(Main clock)/2^17/(HOCO clock)/2^17,(Main clock)/2^18/(HOCO clock)/2^18,(Main clock)/2^19/(HOCO clock)/2^19,?..."
|
|
if (((per.b(ad:0x40082000))&0x3)==0x1)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "VLCD,LCD Boost Level Control Register"
|
|
bitfld.byte 0x00 0.--4. " VLCD ,Reference Voltage Select" ",,,,3.00 V,3.15 V,3.30 V,3.45 V,3.60 V,3.75 V,3.90 V,4.05 V,4.20 V,4.35 V,4.50 V,4.65 V,4.80 V,4.95 V,5.10 V,5.25 V,?..."
|
|
elif (((per.b(ad:0x40082000))&0x3)==0x2)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "VLCD,LCD Boost Level Control Register"
|
|
bitfld.byte 0x00 0.--4. " VLCD ,Reference Voltage Select" ",,,,4.00 V,4.20 V,4.40 V,4.60 V,4.80 V,5.00 V,5.20 V,?..."
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "VLCD,LCD Boost Level Control Register"
|
|
bitfld.byte 0x00 0.--4. " VLCD ,Reference Voltage Select" ",,,,1.00 V,1.05 V,1.10 V,1.15 V,1.20 V,1.25 V,1.30 V,1.35 V,1.40 V,1.45 V,1.50 V,1.55 V,1.60 V,1.65 V,1.70 V,1.75 V,?..."
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0x40082000))&0x1C)!=0x14)
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "SEG00,Segment 0 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.byte 0x101++0x01
|
|
line.byte 0x00 "SEG01,Segment 1 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SEG02,Segment 2 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x01 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.byte 0x103++0x02
|
|
line.byte 0x00 "SEG03,Segment 3 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SEG04,Segment 4 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x01 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x02 "SEG05,Segment 5 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x02 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))
|
|
group.byte 0x106++0x05
|
|
line.byte 0x00 "SEG06,Segment 6 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SEG07,Segment 7 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x01 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x02 "SEG08,Segment 8 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x02 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x03 "SEG09,Segment 9 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x03 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x03 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x04 "SEG10,Segment 10 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x04 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x04 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x05 "SEG11,Segment 11 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x05 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x05 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.byte 0x10C++0x02
|
|
line.byte 0x00 "SEG12,Segment 12 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SEG13,Segment 13 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x01 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.byte 0x10E++0x02
|
|
line.byte 0x00 "SEG14,Segment 14 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SEG15,Segment 15 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x01 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x02 "SEG16,Segment 16 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x02 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.byte 0x111++0x00
|
|
line.byte 0x00 "SEG17,Segment 17 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.byte 0x112++0x01
|
|
line.byte 0x00 "SEG18,Segment 18 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SEG19,Segment 19 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x01 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.byte 0x114++0x03
|
|
line.byte 0x00 "SEG20,Segment 20 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SEG21,Segment 21 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x01 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x02 "SEG22,Segment 22 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x02 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x03 "SEG23,Segment 23 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x03 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x03 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.byte 0x118++0x01
|
|
line.byte 0x00 "SEG24,Segment 24 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SEG25,Segment 25 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x01 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))
|
|
group.byte 0x11A++0x01
|
|
line.byte 0x00 "SEG26,Segment 26 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SEG27,Segment 27 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x01 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.byte 0x11C++0x02
|
|
line.byte 0x00 "SEG28,Segment 28 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SEG29,Segment 29 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x01 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x02 "SEG30,Segment 30 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x02 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.byte 0x11F++0x02
|
|
line.byte 0x00 "SEG31,Segment 31 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SEG32,Segment 32 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x01 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x02 "SEG33,Segment 33 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x02 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))
|
|
group.byte 0x122++0x01
|
|
line.byte 0x00 "SEG34,Segment 34 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SEG35,Segment 35 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x01 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.byte 0x124++0x01
|
|
line.byte 0x00 "SEG36,Segment 36 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SEG37,Segment 37 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x01 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.byte 0x126++0x03
|
|
line.byte 0x00 "SEG38,Segment 38 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SEG39,Segment 39 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x01 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x02 "SEG40,Segment 40 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x02 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x03 "SEG41,Segment 41 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x03 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x03 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))
|
|
group.byte 0x12A++0x01
|
|
line.byte 0x00 "SEG42,Segment 42 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SEG43,Segment 43 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x01 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.byte 0x12C++0x01
|
|
line.byte 0x00 "SEG44,Segment 44 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SEG45,Segment 45 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x01 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))
|
|
group.byte 0x12E++0x01
|
|
line.byte 0x00 "SEG46,Segment 46 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SEG47,Segment 47 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x01 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.byte 0x130++0x02
|
|
line.byte 0x00 "SEG48,Segment 48 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SEG49,Segment 49 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x01 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x01 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x02 "SEG50,Segment 50 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x02 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x02 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.byte 0x133++0x02
|
|
line.byte 0x00 "SEG51,Segment 51 signal output pins for the LCD controller/driver"
|
|
bitfld.byte 0x00 0.--3. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 4.--7. " COM ,Common signal output pins for the LCD controller/driver" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "SEG00,Segment 0 signal output pins for the LCD controller/driver"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.byte 0x101++0x01
|
|
line.byte 0x00 "SEG01,Segment 1 signal output pins for the LCD controller/driver"
|
|
line.byte 0x01 "SEG02,Segment 2 signal output pins for the LCD controller/driver"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.byte 0x103++0x02
|
|
line.byte 0x00 "SEG03,Segment 3 signal output pins for the LCD controller/driver"
|
|
line.byte 0x01 "SEG04,Segment 4 signal output pins for the LCD controller/driver"
|
|
line.byte 0x02 "SEG05,Segment 5 signal output pins for the LCD controller/driver"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))
|
|
group.byte 0x106++0x05
|
|
line.byte 0x00 "SEG06,Segment 6 signal output pins for the LCD controller/driver"
|
|
line.byte 0x01 "SEG07,Segment 7 signal output pins for the LCD controller/driver"
|
|
line.byte 0x02 "SEG08,Segment 8 signal output pins for the LCD controller/driver"
|
|
line.byte 0x03 "SEG09,Segment 9 signal output pins for the LCD controller/driver"
|
|
line.byte 0x04 "SEG10,Segment 10 signal output pins for the LCD controller/driver"
|
|
line.byte 0x05 "SEG11,Segment 11 signal output pins for the LCD controller/driver"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.byte 0x10C++0x01
|
|
line.byte 0x00 "SEG12,Segment 12 signal output pins for the LCD controller/driver"
|
|
line.byte 0x01 "SEG12,Segment 12 signal output pins for the LCD controller/driver"
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.byte 0x10E++0x02
|
|
line.byte 0x00 "SEG14,Segment 14 signal output pins for the LCD controller/driver"
|
|
line.byte 0x01 "SEG15,Segment 15 signal output pins for the LCD controller/driver"
|
|
line.byte 0x02 "SEG16,Segment 16 signal output pins for the LCD controller/driver"
|
|
endif
|
|
group.byte 0x111++0x00
|
|
line.byte 0x00 "SEG17,Segment 17 signal output pins for the LCD controller/driver"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.byte 0x112++0x01
|
|
line.byte 0x00 "SEG18,Segment 18 signal output pins for the LCD controller/driver"
|
|
line.byte 0x01 "SEG19,Segment 19 signal output pins for the LCD controller/driver"
|
|
endif
|
|
group.byte 0x114++0x03
|
|
line.byte 0x00 "SEG20,Segment 20 signal output pins for the LCD controller/driver"
|
|
line.byte 0x01 "SEG21,Segment 21 signal output pins for the LCD controller/driver"
|
|
line.byte 0x02 "SEG22,Segment 22 signal output pins for the LCD controller/driver"
|
|
line.byte 0x03 "SEG23,Segment 23 signal output pins for the LCD controller/driver"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.byte 0x11A++0x01
|
|
line.byte 0x00 "SEG24,Segment 24 signal output pins for the LCD controller/driver"
|
|
line.byte 0x01 "SEG25,Segment 25 signal output pins for the LCD controller/driver"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))
|
|
group.byte 0x11A++0x01
|
|
line.byte 0x00 "SEG26,Segment 26 signal output pins for the LCD controller/driver"
|
|
line.byte 0x01 "SEG27,Segment 27 signal output pins for the LCD controller/driver"
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.byte 0x11C++0x02
|
|
line.byte 0x00 "SEG28,Segment 28 signal output pins for the LCD controller/driver"
|
|
line.byte 0x01 "SEG29,Segment 29 signal output pins for the LCD controller/driver"
|
|
line.byte 0x02 "SEG30,Segment 30 signal output pins for the LCD controller/driver"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.byte 0x11F++0x02
|
|
line.byte 0x00 "SEG31,Segment 31 signal output pins for the LCD controller/driver"
|
|
line.byte 0x01 "SEG32,Segment 32 signal output pins for the LCD controller/driver"
|
|
line.byte 0x02 "SEG33,Segment 33 signal output pins for the LCD controller/driver"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))
|
|
group.byte 0x122++0x01
|
|
line.byte 0x00 "SEG34,Segment 34 signal output pins for the LCD controller/driver"
|
|
line.byte 0x01 "SEG35,Segment 35 signal output pins for the LCD controller/driver"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.byte 0x124++0x01
|
|
line.byte 0x00 "SEG36,Segment 36 signal output pins for the LCD controller/driver"
|
|
line.byte 0x01 "SEG37,Segment 37 signal output pins for the LCD controller/driver"
|
|
endif
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.byte 0x126++0x03
|
|
line.byte 0x00 "SEG38,Segment 38 signal output pins for the LCD controller/driver"
|
|
line.byte 0x01 "SEG39,Segment 39 signal output pins for the LCD controller/driver"
|
|
line.byte 0x02 "SEG40,Segment 40 signal output pins for the LCD controller/driver"
|
|
line.byte 0x03 "SEG41,Segment 41 signal output pins for the LCD controller/driver"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))
|
|
group.byte 0x12A++0x01
|
|
line.byte 0x00 "SEG42,Segment 42 signal output pins for the LCD controller/driver"
|
|
line.byte 0x01 "SEG43,Segment 43 signal output pins for the LCD controller/driver"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))||(cpuis("R7FS3A77C2A01CBJ"))
|
|
group.byte 0x12C++0x01
|
|
line.byte 0x00 "SEG44,Segment 44 signal output pins for the LCD controller/driver"
|
|
line.byte 0x01 "SEG45,Segment 45 signal output pins for the LCD controller/driver"
|
|
endif
|
|
sif (cpuis("R7FS3A77C2A01CLK"))||(cpuis("R7FS3A77C3A01CFB"))
|
|
group.byte 0x12E++0x01
|
|
line.byte 0x00 "SEG46,Segment 46 signal output pins for the LCD controller/driver"
|
|
line.byte 0x01 "SEG47,Segment 47 signal output pins for the LCD controller/driver"
|
|
endif
|
|
group.byte 0x130++0x02
|
|
line.byte 0x00 "SEG48,Segment 48 signal output pins for the LCD controller/driver"
|
|
line.byte 0x01 "SEG49,Segment 49 signal output pins for the LCD controller/driver"
|
|
line.byte 0x02 "SEG50,Segment 50 signal output pins for the LCD controller/driver"
|
|
sif (!cpuis("R7FS3A77C3A01CFM"))&&(!cpuis("R7FS3A77C3A01CNB"))
|
|
group.byte 0x133++0x02
|
|
line.byte 0x00 "SEG51,Segment 51 signal output pins for the LCD controller/driver"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
textline ""
|